time.c 4.9 KB

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  1. /*
  2. * Copyright (C) 2004-2007 Atmel Corporation
  3. *
  4. * Based on MIPS implementation arch/mips/kernel/time.c
  5. * Copyright 2001 MontaVista Software Inc.
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. */
  11. #include <linux/clk.h>
  12. #include <linux/clocksource.h>
  13. #include <linux/time.h>
  14. #include <linux/module.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/irq.h>
  17. #include <linux/kernel_stat.h>
  18. #include <linux/errno.h>
  19. #include <linux/init.h>
  20. #include <linux/profile.h>
  21. #include <linux/sysdev.h>
  22. #include <linux/err.h>
  23. #include <asm/div64.h>
  24. #include <asm/sysreg.h>
  25. #include <asm/io.h>
  26. #include <asm/sections.h>
  27. /* how many counter cycles in a jiffy? */
  28. static u32 cycles_per_jiffy;
  29. /* the count value for the next timer interrupt */
  30. static u32 expirelo;
  31. cycle_t __weak read_cycle_count(void)
  32. {
  33. return (cycle_t)sysreg_read(COUNT);
  34. }
  35. struct clocksource __weak clocksource_avr32 = {
  36. .name = "avr32",
  37. .rating = 350,
  38. .read = read_cycle_count,
  39. .mask = CLOCKSOURCE_MASK(32),
  40. .shift = 16,
  41. .flags = CLOCK_SOURCE_IS_CONTINUOUS,
  42. };
  43. irqreturn_t __weak timer_interrupt(int irq, void *dev_id);
  44. struct irqaction timer_irqaction = {
  45. .handler = timer_interrupt,
  46. .flags = IRQF_DISABLED,
  47. .name = "timer",
  48. };
  49. /*
  50. * By default we provide the null RTC ops
  51. */
  52. static unsigned long null_rtc_get_time(void)
  53. {
  54. return mktime(2007, 1, 1, 0, 0, 0);
  55. }
  56. static int null_rtc_set_time(unsigned long sec)
  57. {
  58. return 0;
  59. }
  60. static unsigned long (*rtc_get_time)(void) = null_rtc_get_time;
  61. static int (*rtc_set_time)(unsigned long) = null_rtc_set_time;
  62. static void avr32_timer_ack(void)
  63. {
  64. u32 count;
  65. /* Ack this timer interrupt and set the next one */
  66. expirelo += cycles_per_jiffy;
  67. /* setting COMPARE to 0 stops the COUNT-COMPARE */
  68. if (expirelo == 0) {
  69. sysreg_write(COMPARE, expirelo + 1);
  70. } else {
  71. sysreg_write(COMPARE, expirelo);
  72. }
  73. /* Check to see if we have missed any timer interrupts */
  74. count = sysreg_read(COUNT);
  75. if ((count - expirelo) < 0x7fffffff) {
  76. expirelo = count + cycles_per_jiffy;
  77. sysreg_write(COMPARE, expirelo);
  78. }
  79. }
  80. int __weak avr32_hpt_init(void)
  81. {
  82. int ret;
  83. unsigned long mult, shift, count_hz;
  84. count_hz = clk_get_rate(boot_cpu_data.clk);
  85. shift = clocksource_avr32.shift;
  86. mult = clocksource_hz2mult(count_hz, shift);
  87. clocksource_avr32.mult = mult;
  88. {
  89. u64 tmp;
  90. tmp = TICK_NSEC;
  91. tmp <<= shift;
  92. tmp += mult / 2;
  93. do_div(tmp, mult);
  94. cycles_per_jiffy = tmp;
  95. }
  96. ret = setup_irq(0, &timer_irqaction);
  97. if (ret) {
  98. pr_debug("timer: could not request IRQ 0: %d\n", ret);
  99. return -ENODEV;
  100. }
  101. printk(KERN_INFO "timer: AT32AP COUNT-COMPARE at irq 0, "
  102. "%lu.%03lu MHz\n",
  103. ((count_hz + 500) / 1000) / 1000,
  104. ((count_hz + 500) / 1000) % 1000);
  105. return 0;
  106. }
  107. /*
  108. * Taken from MIPS c0_hpt_timer_init().
  109. *
  110. * The reason COUNT is written twice is probably to make sure we don't get any
  111. * timer interrupts while we are messing with the counter.
  112. */
  113. int __weak avr32_hpt_start(void)
  114. {
  115. u32 count = sysreg_read(COUNT);
  116. expirelo = (count / cycles_per_jiffy + 1) * cycles_per_jiffy;
  117. sysreg_write(COUNT, expirelo - cycles_per_jiffy);
  118. sysreg_write(COMPARE, expirelo);
  119. sysreg_write(COUNT, count);
  120. return 0;
  121. }
  122. /*
  123. * local_timer_interrupt() does profiling and process accounting on a
  124. * per-CPU basis.
  125. *
  126. * In UP mode, it is invoked from the (global) timer_interrupt.
  127. */
  128. void local_timer_interrupt(int irq, void *dev_id)
  129. {
  130. if (current->pid)
  131. profile_tick(CPU_PROFILING);
  132. update_process_times(user_mode(get_irq_regs()));
  133. }
  134. irqreturn_t __weak timer_interrupt(int irq, void *dev_id)
  135. {
  136. /* ack timer interrupt and try to set next interrupt */
  137. avr32_timer_ack();
  138. /*
  139. * Call the generic timer interrupt handler
  140. */
  141. write_seqlock(&xtime_lock);
  142. do_timer(1);
  143. write_sequnlock(&xtime_lock);
  144. /*
  145. * In UP mode, we call local_timer_interrupt() to do profiling
  146. * and process accounting.
  147. *
  148. * SMP is not supported yet.
  149. */
  150. local_timer_interrupt(irq, dev_id);
  151. return IRQ_HANDLED;
  152. }
  153. void __init time_init(void)
  154. {
  155. int ret;
  156. /*
  157. * Make sure we don't get any COMPARE interrupts before we can
  158. * handle them.
  159. */
  160. sysreg_write(COMPARE, 0);
  161. xtime.tv_sec = rtc_get_time();
  162. xtime.tv_nsec = 0;
  163. set_normalized_timespec(&wall_to_monotonic,
  164. -xtime.tv_sec, -xtime.tv_nsec);
  165. ret = avr32_hpt_init();
  166. if (ret) {
  167. pr_debug("timer: failed setup: %d\n", ret);
  168. return;
  169. }
  170. ret = clocksource_register(&clocksource_avr32);
  171. if (ret)
  172. pr_debug("timer: could not register clocksource: %d\n", ret);
  173. ret = avr32_hpt_start();
  174. if (ret) {
  175. pr_debug("timer: failed starting: %d\n", ret);
  176. return;
  177. }
  178. }
  179. static struct sysdev_class timer_class = {
  180. set_kset_name("timer"),
  181. };
  182. static struct sys_device timer_device = {
  183. .id = 0,
  184. .cls = &timer_class,
  185. };
  186. static int __init init_timer_sysfs(void)
  187. {
  188. int err = sysdev_class_register(&timer_class);
  189. if (!err)
  190. err = sysdev_register(&timer_device);
  191. return err;
  192. }
  193. device_initcall(init_timer_sysfs);