mainstone.c 12 KB

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  1. /*
  2. * linux/arch/arm/mach-pxa/mainstone.c
  3. *
  4. * Support for the Intel HCDDBBVA0 Development Platform.
  5. * (go figure how they came up with such name...)
  6. *
  7. * Author: Nicolas Pitre
  8. * Created: Nov 05, 2002
  9. * Copyright: MontaVista Software Inc.
  10. *
  11. * This program is free software; you can redistribute it and/or modify
  12. * it under the terms of the GNU General Public License version 2 as
  13. * published by the Free Software Foundation.
  14. */
  15. #include <linux/init.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/sysdev.h>
  18. #include <linux/interrupt.h>
  19. #include <linux/sched.h>
  20. #include <linux/bitops.h>
  21. #include <linux/fb.h>
  22. #include <linux/ioport.h>
  23. #include <linux/mtd/mtd.h>
  24. #include <linux/mtd/partitions.h>
  25. #include <asm/types.h>
  26. #include <asm/setup.h>
  27. #include <asm/memory.h>
  28. #include <asm/mach-types.h>
  29. #include <asm/hardware.h>
  30. #include <asm/irq.h>
  31. #include <asm/sizes.h>
  32. #include <asm/mach/arch.h>
  33. #include <asm/mach/map.h>
  34. #include <asm/mach/irq.h>
  35. #include <asm/mach/flash.h>
  36. #include <asm/arch/pxa-regs.h>
  37. #include <asm/arch/mainstone.h>
  38. #include <asm/arch/audio.h>
  39. #include <asm/arch/pxafb.h>
  40. #include <asm/arch/mmc.h>
  41. #include <asm/arch/irda.h>
  42. #include <asm/arch/ohci.h>
  43. #include "generic.h"
  44. #include "devices.h"
  45. static unsigned long mainstone_irq_enabled;
  46. static void mainstone_mask_irq(unsigned int irq)
  47. {
  48. int mainstone_irq = (irq - MAINSTONE_IRQ(0));
  49. MST_INTMSKENA = (mainstone_irq_enabled &= ~(1 << mainstone_irq));
  50. }
  51. static void mainstone_unmask_irq(unsigned int irq)
  52. {
  53. int mainstone_irq = (irq - MAINSTONE_IRQ(0));
  54. /* the irq can be acknowledged only if deasserted, so it's done here */
  55. MST_INTSETCLR &= ~(1 << mainstone_irq);
  56. MST_INTMSKENA = (mainstone_irq_enabled |= (1 << mainstone_irq));
  57. }
  58. static struct irq_chip mainstone_irq_chip = {
  59. .name = "FPGA",
  60. .ack = mainstone_mask_irq,
  61. .mask = mainstone_mask_irq,
  62. .unmask = mainstone_unmask_irq,
  63. };
  64. static void mainstone_irq_handler(unsigned int irq, struct irq_desc *desc)
  65. {
  66. unsigned long pending = MST_INTSETCLR & mainstone_irq_enabled;
  67. do {
  68. GEDR(0) = GPIO_bit(0); /* clear useless edge notification */
  69. if (likely(pending)) {
  70. irq = MAINSTONE_IRQ(0) + __ffs(pending);
  71. desc = irq_desc + irq;
  72. desc_handle_irq(irq, desc);
  73. }
  74. pending = MST_INTSETCLR & mainstone_irq_enabled;
  75. } while (pending);
  76. }
  77. static void __init mainstone_init_irq(void)
  78. {
  79. int irq;
  80. pxa27x_init_irq();
  81. /* setup extra Mainstone irqs */
  82. for(irq = MAINSTONE_IRQ(0); irq <= MAINSTONE_IRQ(15); irq++) {
  83. set_irq_chip(irq, &mainstone_irq_chip);
  84. set_irq_handler(irq, handle_level_irq);
  85. if (irq == MAINSTONE_IRQ(10) || irq == MAINSTONE_IRQ(14))
  86. set_irq_flags(irq, IRQF_VALID | IRQF_PROBE | IRQF_NOAUTOEN);
  87. else
  88. set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
  89. }
  90. set_irq_flags(MAINSTONE_IRQ(8), 0);
  91. set_irq_flags(MAINSTONE_IRQ(12), 0);
  92. MST_INTMSKENA = 0;
  93. MST_INTSETCLR = 0;
  94. set_irq_chained_handler(IRQ_GPIO(0), mainstone_irq_handler);
  95. set_irq_type(IRQ_GPIO(0), IRQT_FALLING);
  96. }
  97. #ifdef CONFIG_PM
  98. static int mainstone_irq_resume(struct sys_device *dev)
  99. {
  100. MST_INTMSKENA = mainstone_irq_enabled;
  101. return 0;
  102. }
  103. static struct sysdev_class mainstone_irq_sysclass = {
  104. set_kset_name("cpld_irq"),
  105. .resume = mainstone_irq_resume,
  106. };
  107. static struct sys_device mainstone_irq_device = {
  108. .cls = &mainstone_irq_sysclass,
  109. };
  110. static int __init mainstone_irq_device_init(void)
  111. {
  112. int ret = sysdev_class_register(&mainstone_irq_sysclass);
  113. if (ret == 0)
  114. ret = sysdev_register(&mainstone_irq_device);
  115. return ret;
  116. }
  117. device_initcall(mainstone_irq_device_init);
  118. #endif
  119. static struct resource smc91x_resources[] = {
  120. [0] = {
  121. .start = (MST_ETH_PHYS + 0x300),
  122. .end = (MST_ETH_PHYS + 0xfffff),
  123. .flags = IORESOURCE_MEM,
  124. },
  125. [1] = {
  126. .start = MAINSTONE_IRQ(3),
  127. .end = MAINSTONE_IRQ(3),
  128. .flags = IORESOURCE_IRQ,
  129. }
  130. };
  131. static struct platform_device smc91x_device = {
  132. .name = "smc91x",
  133. .id = 0,
  134. .num_resources = ARRAY_SIZE(smc91x_resources),
  135. .resource = smc91x_resources,
  136. };
  137. static int mst_audio_startup(struct snd_pcm_substream *substream, void *priv)
  138. {
  139. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  140. MST_MSCWR2 &= ~MST_MSCWR2_AC97_SPKROFF;
  141. return 0;
  142. }
  143. static void mst_audio_shutdown(struct snd_pcm_substream *substream, void *priv)
  144. {
  145. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  146. MST_MSCWR2 |= MST_MSCWR2_AC97_SPKROFF;
  147. }
  148. static long mst_audio_suspend_mask;
  149. static void mst_audio_suspend(void *priv)
  150. {
  151. mst_audio_suspend_mask = MST_MSCWR2;
  152. MST_MSCWR2 |= MST_MSCWR2_AC97_SPKROFF;
  153. }
  154. static void mst_audio_resume(void *priv)
  155. {
  156. MST_MSCWR2 &= mst_audio_suspend_mask | ~MST_MSCWR2_AC97_SPKROFF;
  157. }
  158. static pxa2xx_audio_ops_t mst_audio_ops = {
  159. .startup = mst_audio_startup,
  160. .shutdown = mst_audio_shutdown,
  161. .suspend = mst_audio_suspend,
  162. .resume = mst_audio_resume,
  163. };
  164. static struct platform_device mst_audio_device = {
  165. .name = "pxa2xx-ac97",
  166. .id = -1,
  167. .dev = { .platform_data = &mst_audio_ops },
  168. };
  169. static struct resource flash_resources[] = {
  170. [0] = {
  171. .start = PXA_CS0_PHYS,
  172. .end = PXA_CS0_PHYS + SZ_64M - 1,
  173. .flags = IORESOURCE_MEM,
  174. },
  175. [1] = {
  176. .start = PXA_CS1_PHYS,
  177. .end = PXA_CS1_PHYS + SZ_64M - 1,
  178. .flags = IORESOURCE_MEM,
  179. },
  180. };
  181. static struct mtd_partition mainstoneflash0_partitions[] = {
  182. {
  183. .name = "Bootloader",
  184. .size = 0x00040000,
  185. .offset = 0,
  186. .mask_flags = MTD_WRITEABLE /* force read-only */
  187. },{
  188. .name = "Kernel",
  189. .size = 0x00400000,
  190. .offset = 0x00040000,
  191. },{
  192. .name = "Filesystem",
  193. .size = MTDPART_SIZ_FULL,
  194. .offset = 0x00440000
  195. }
  196. };
  197. static struct flash_platform_data mst_flash_data[2] = {
  198. {
  199. .map_name = "cfi_probe",
  200. .parts = mainstoneflash0_partitions,
  201. .nr_parts = ARRAY_SIZE(mainstoneflash0_partitions),
  202. }, {
  203. .map_name = "cfi_probe",
  204. .parts = NULL,
  205. .nr_parts = 0,
  206. }
  207. };
  208. static struct platform_device mst_flash_device[2] = {
  209. {
  210. .name = "pxa2xx-flash",
  211. .id = 0,
  212. .dev = {
  213. .platform_data = &mst_flash_data[0],
  214. },
  215. .resource = &flash_resources[0],
  216. .num_resources = 1,
  217. },
  218. {
  219. .name = "pxa2xx-flash",
  220. .id = 1,
  221. .dev = {
  222. .platform_data = &mst_flash_data[1],
  223. },
  224. .resource = &flash_resources[1],
  225. .num_resources = 1,
  226. },
  227. };
  228. static void mainstone_backlight_power(int on)
  229. {
  230. if (on) {
  231. pxa_gpio_mode(GPIO16_PWM0_MD);
  232. pxa_set_cken(CKEN_PWM0, 1);
  233. PWM_CTRL0 = 0;
  234. PWM_PWDUTY0 = 0x3ff;
  235. PWM_PERVAL0 = 0x3ff;
  236. } else {
  237. PWM_CTRL0 = 0;
  238. PWM_PWDUTY0 = 0x0;
  239. PWM_PERVAL0 = 0x3FF;
  240. pxa_set_cken(CKEN_PWM0, 0);
  241. }
  242. }
  243. static struct pxafb_mode_info toshiba_ltm04c380k_mode = {
  244. .pixclock = 50000,
  245. .xres = 640,
  246. .yres = 480,
  247. .bpp = 16,
  248. .hsync_len = 1,
  249. .left_margin = 0x9f,
  250. .right_margin = 1,
  251. .vsync_len = 44,
  252. .upper_margin = 0,
  253. .lower_margin = 0,
  254. .sync = FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT,
  255. };
  256. static struct pxafb_mode_info toshiba_ltm035a776c_mode = {
  257. .pixclock = 110000,
  258. .xres = 240,
  259. .yres = 320,
  260. .bpp = 16,
  261. .hsync_len = 4,
  262. .left_margin = 8,
  263. .right_margin = 20,
  264. .vsync_len = 3,
  265. .upper_margin = 1,
  266. .lower_margin = 10,
  267. .sync = FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT,
  268. };
  269. static struct pxafb_mach_info mainstone_pxafb_info = {
  270. .num_modes = 1,
  271. .lccr0 = LCCR0_Act,
  272. .lccr3 = LCCR3_PCP,
  273. .pxafb_backlight_power = mainstone_backlight_power,
  274. };
  275. static int mainstone_mci_init(struct device *dev, irq_handler_t mstone_detect_int, void *data)
  276. {
  277. int err;
  278. /*
  279. * setup GPIO for PXA27x MMC controller
  280. */
  281. pxa_gpio_mode(GPIO32_MMCCLK_MD);
  282. pxa_gpio_mode(GPIO112_MMCCMD_MD);
  283. pxa_gpio_mode(GPIO92_MMCDAT0_MD);
  284. pxa_gpio_mode(GPIO109_MMCDAT1_MD);
  285. pxa_gpio_mode(GPIO110_MMCDAT2_MD);
  286. pxa_gpio_mode(GPIO111_MMCDAT3_MD);
  287. /* make sure SD/Memory Stick multiplexer's signals
  288. * are routed to MMC controller
  289. */
  290. MST_MSCWR1 &= ~MST_MSCWR1_MS_SEL;
  291. err = request_irq(MAINSTONE_MMC_IRQ, mstone_detect_int, IRQF_DISABLED,
  292. "MMC card detect", data);
  293. if (err) {
  294. printk(KERN_ERR "mainstone_mci_init: MMC/SD: can't request MMC card detect IRQ\n");
  295. return -1;
  296. }
  297. return 0;
  298. }
  299. static void mainstone_mci_setpower(struct device *dev, unsigned int vdd)
  300. {
  301. struct pxamci_platform_data* p_d = dev->platform_data;
  302. if (( 1 << vdd) & p_d->ocr_mask) {
  303. printk(KERN_DEBUG "%s: on\n", __FUNCTION__);
  304. MST_MSCWR1 |= MST_MSCWR1_MMC_ON;
  305. MST_MSCWR1 &= ~MST_MSCWR1_MS_SEL;
  306. } else {
  307. printk(KERN_DEBUG "%s: off\n", __FUNCTION__);
  308. MST_MSCWR1 &= ~MST_MSCWR1_MMC_ON;
  309. }
  310. }
  311. static void mainstone_mci_exit(struct device *dev, void *data)
  312. {
  313. free_irq(MAINSTONE_MMC_IRQ, data);
  314. }
  315. static struct pxamci_platform_data mainstone_mci_platform_data = {
  316. .ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
  317. .init = mainstone_mci_init,
  318. .setpower = mainstone_mci_setpower,
  319. .exit = mainstone_mci_exit,
  320. };
  321. static void mainstone_irda_transceiver_mode(struct device *dev, int mode)
  322. {
  323. unsigned long flags;
  324. local_irq_save(flags);
  325. if (mode & IR_SIRMODE) {
  326. MST_MSCWR1 &= ~MST_MSCWR1_IRDA_FIR;
  327. } else if (mode & IR_FIRMODE) {
  328. MST_MSCWR1 |= MST_MSCWR1_IRDA_FIR;
  329. }
  330. if (mode & IR_OFF) {
  331. MST_MSCWR1 = (MST_MSCWR1 & ~MST_MSCWR1_IRDA_MASK) | MST_MSCWR1_IRDA_OFF;
  332. } else {
  333. MST_MSCWR1 = (MST_MSCWR1 & ~MST_MSCWR1_IRDA_MASK) | MST_MSCWR1_IRDA_FULL;
  334. }
  335. local_irq_restore(flags);
  336. }
  337. static struct pxaficp_platform_data mainstone_ficp_platform_data = {
  338. .transceiver_cap = IR_SIRMODE | IR_FIRMODE | IR_OFF,
  339. .transceiver_mode = mainstone_irda_transceiver_mode,
  340. };
  341. static struct platform_device *platform_devices[] __initdata = {
  342. &smc91x_device,
  343. &mst_audio_device,
  344. &mst_flash_device[0],
  345. &mst_flash_device[1],
  346. };
  347. static int mainstone_ohci_init(struct device *dev)
  348. {
  349. /* setup Port1 GPIO pin. */
  350. pxa_gpio_mode( 88 | GPIO_ALT_FN_1_IN); /* USBHPWR1 */
  351. pxa_gpio_mode( 89 | GPIO_ALT_FN_2_OUT); /* USBHPEN1 */
  352. /* Set the Power Control Polarity Low and Power Sense
  353. Polarity Low to active low. */
  354. UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
  355. ~(UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSEP3 | UHCHR_SSE);
  356. return 0;
  357. }
  358. static struct pxaohci_platform_data mainstone_ohci_platform_data = {
  359. .port_mode = PMM_PERPORT_MODE,
  360. .init = mainstone_ohci_init,
  361. };
  362. static void __init mainstone_init(void)
  363. {
  364. int SW7 = 0; /* FIXME: get from SCR (Mst doc section 3.2.1.1) */
  365. mst_flash_data[0].width = (BOOT_DEF & 1) ? 2 : 4;
  366. mst_flash_data[1].width = 4;
  367. /* Compensate for SW7 which swaps the flash banks */
  368. mst_flash_data[SW7].name = "processor-flash";
  369. mst_flash_data[SW7 ^ 1].name = "mainboard-flash";
  370. printk(KERN_NOTICE "Mainstone configured to boot from %s\n",
  371. mst_flash_data[0].name);
  372. /* system bus arbiter setting
  373. * - Core_Park
  374. * - LCD_wt:DMA_wt:CORE_Wt = 2:3:4
  375. */
  376. ARB_CNTRL = ARB_CORE_PARK | 0x234;
  377. /*
  378. * On Mainstone, we route AC97_SYSCLK via GPIO45 to
  379. * the audio daughter card
  380. */
  381. pxa_gpio_mode(GPIO45_SYSCLK_AC97_MD);
  382. platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
  383. /* reading Mainstone's "Virtual Configuration Register"
  384. might be handy to select LCD type here */
  385. if (0)
  386. mainstone_pxafb_info.modes = &toshiba_ltm04c380k_mode;
  387. else
  388. mainstone_pxafb_info.modes = &toshiba_ltm035a776c_mode;
  389. set_pxa_fb_info(&mainstone_pxafb_info);
  390. pxa_set_mci_info(&mainstone_mci_platform_data);
  391. pxa_set_ficp_info(&mainstone_ficp_platform_data);
  392. pxa_set_ohci_info(&mainstone_ohci_platform_data);
  393. }
  394. static struct map_desc mainstone_io_desc[] __initdata = {
  395. { /* CPLD */
  396. .virtual = MST_FPGA_VIRT,
  397. .pfn = __phys_to_pfn(MST_FPGA_PHYS),
  398. .length = 0x00100000,
  399. .type = MT_DEVICE
  400. }
  401. };
  402. static void __init mainstone_map_io(void)
  403. {
  404. pxa_map_io();
  405. iotable_init(mainstone_io_desc, ARRAY_SIZE(mainstone_io_desc));
  406. /* initialize sleep mode regs (wake-up sources, etc) */
  407. PGSR0 = 0x00008800;
  408. PGSR1 = 0x00000002;
  409. PGSR2 = 0x0001FC00;
  410. PGSR3 = 0x00001F81;
  411. PWER = 0xC0000002;
  412. PRER = 0x00000002;
  413. PFER = 0x00000002;
  414. /* for use I SRAM as framebuffer. */
  415. PSLR |= 0xF04;
  416. PCFR = 0x66;
  417. /* For Keypad wakeup. */
  418. KPC &=~KPC_ASACT;
  419. KPC |=KPC_AS;
  420. PKWR = 0x000FD000;
  421. /* Need read PKWR back after set it. */
  422. PKWR;
  423. }
  424. MACHINE_START(MAINSTONE, "Intel HCDDBBVA0 Development Platform (aka Mainstone)")
  425. /* Maintainer: MontaVista Software Inc. */
  426. .phys_io = 0x40000000,
  427. .boot_params = 0xa0000100, /* BLOB boot parameter setting */
  428. .io_pg_offst = (io_p2v(0x40000000) >> 18) & 0xfffc,
  429. .map_io = mainstone_map_io,
  430. .init_irq = mainstone_init_irq,
  431. .timer = &pxa_timer,
  432. .init_machine = mainstone_init,
  433. MACHINE_END