at91sam9260_devices.c 21 KB

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  1. /*
  2. * arch/arm/mach-at91/at91sam9260_devices.c
  3. *
  4. * Copyright (C) 2006 Atmel
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. */
  12. #include <asm/mach/arch.h>
  13. #include <asm/mach/map.h>
  14. #include <linux/platform_device.h>
  15. #include <asm/arch/board.h>
  16. #include <asm/arch/gpio.h>
  17. #include <asm/arch/at91sam9260.h>
  18. #include <asm/arch/at91sam926x_mc.h>
  19. #include <asm/arch/at91sam9260_matrix.h>
  20. #include "generic.h"
  21. /* --------------------------------------------------------------------
  22. * USB Host
  23. * -------------------------------------------------------------------- */
  24. #if defined(CONFIG_USB_OHCI_HCD) || defined(CONFIG_USB_OHCI_HCD_MODULE)
  25. static u64 ohci_dmamask = 0xffffffffUL;
  26. static struct at91_usbh_data usbh_data;
  27. static struct resource usbh_resources[] = {
  28. [0] = {
  29. .start = AT91SAM9260_UHP_BASE,
  30. .end = AT91SAM9260_UHP_BASE + SZ_1M - 1,
  31. .flags = IORESOURCE_MEM,
  32. },
  33. [1] = {
  34. .start = AT91SAM9260_ID_UHP,
  35. .end = AT91SAM9260_ID_UHP,
  36. .flags = IORESOURCE_IRQ,
  37. },
  38. };
  39. static struct platform_device at91_usbh_device = {
  40. .name = "at91_ohci",
  41. .id = -1,
  42. .dev = {
  43. .dma_mask = &ohci_dmamask,
  44. .coherent_dma_mask = 0xffffffff,
  45. .platform_data = &usbh_data,
  46. },
  47. .resource = usbh_resources,
  48. .num_resources = ARRAY_SIZE(usbh_resources),
  49. };
  50. void __init at91_add_device_usbh(struct at91_usbh_data *data)
  51. {
  52. if (!data)
  53. return;
  54. usbh_data = *data;
  55. platform_device_register(&at91_usbh_device);
  56. }
  57. #else
  58. void __init at91_add_device_usbh(struct at91_usbh_data *data) {}
  59. #endif
  60. /* --------------------------------------------------------------------
  61. * USB Device (Gadget)
  62. * -------------------------------------------------------------------- */
  63. #ifdef CONFIG_USB_GADGET_AT91
  64. static struct at91_udc_data udc_data;
  65. static struct resource udc_resources[] = {
  66. [0] = {
  67. .start = AT91SAM9260_BASE_UDP,
  68. .end = AT91SAM9260_BASE_UDP + SZ_16K - 1,
  69. .flags = IORESOURCE_MEM,
  70. },
  71. [1] = {
  72. .start = AT91SAM9260_ID_UDP,
  73. .end = AT91SAM9260_ID_UDP,
  74. .flags = IORESOURCE_IRQ,
  75. },
  76. };
  77. static struct platform_device at91_udc_device = {
  78. .name = "at91_udc",
  79. .id = -1,
  80. .dev = {
  81. .platform_data = &udc_data,
  82. },
  83. .resource = udc_resources,
  84. .num_resources = ARRAY_SIZE(udc_resources),
  85. };
  86. void __init at91_add_device_udc(struct at91_udc_data *data)
  87. {
  88. if (!data)
  89. return;
  90. if (data->vbus_pin) {
  91. at91_set_gpio_input(data->vbus_pin, 0);
  92. at91_set_deglitch(data->vbus_pin, 1);
  93. }
  94. /* Pullup pin is handled internally by USB device peripheral */
  95. udc_data = *data;
  96. platform_device_register(&at91_udc_device);
  97. }
  98. #else
  99. void __init at91_add_device_udc(struct at91_udc_data *data) {}
  100. #endif
  101. /* --------------------------------------------------------------------
  102. * Ethernet
  103. * -------------------------------------------------------------------- */
  104. #if defined(CONFIG_MACB) || defined(CONFIG_MACB_MODULE)
  105. static u64 eth_dmamask = 0xffffffffUL;
  106. static struct at91_eth_data eth_data;
  107. static struct resource eth_resources[] = {
  108. [0] = {
  109. .start = AT91SAM9260_BASE_EMAC,
  110. .end = AT91SAM9260_BASE_EMAC + SZ_16K - 1,
  111. .flags = IORESOURCE_MEM,
  112. },
  113. [1] = {
  114. .start = AT91SAM9260_ID_EMAC,
  115. .end = AT91SAM9260_ID_EMAC,
  116. .flags = IORESOURCE_IRQ,
  117. },
  118. };
  119. static struct platform_device at91sam9260_eth_device = {
  120. .name = "macb",
  121. .id = -1,
  122. .dev = {
  123. .dma_mask = &eth_dmamask,
  124. .coherent_dma_mask = 0xffffffff,
  125. .platform_data = &eth_data,
  126. },
  127. .resource = eth_resources,
  128. .num_resources = ARRAY_SIZE(eth_resources),
  129. };
  130. void __init at91_add_device_eth(struct at91_eth_data *data)
  131. {
  132. if (!data)
  133. return;
  134. if (data->phy_irq_pin) {
  135. at91_set_gpio_input(data->phy_irq_pin, 0);
  136. at91_set_deglitch(data->phy_irq_pin, 1);
  137. }
  138. /* Pins used for MII and RMII */
  139. at91_set_A_periph(AT91_PIN_PA19, 0); /* ETXCK_EREFCK */
  140. at91_set_A_periph(AT91_PIN_PA17, 0); /* ERXDV */
  141. at91_set_A_periph(AT91_PIN_PA14, 0); /* ERX0 */
  142. at91_set_A_periph(AT91_PIN_PA15, 0); /* ERX1 */
  143. at91_set_A_periph(AT91_PIN_PA18, 0); /* ERXER */
  144. at91_set_A_periph(AT91_PIN_PA16, 0); /* ETXEN */
  145. at91_set_A_periph(AT91_PIN_PA12, 0); /* ETX0 */
  146. at91_set_A_periph(AT91_PIN_PA13, 0); /* ETX1 */
  147. at91_set_A_periph(AT91_PIN_PA21, 0); /* EMDIO */
  148. at91_set_A_periph(AT91_PIN_PA20, 0); /* EMDC */
  149. if (!data->is_rmii) {
  150. at91_set_B_periph(AT91_PIN_PA28, 0); /* ECRS */
  151. at91_set_B_periph(AT91_PIN_PA29, 0); /* ECOL */
  152. at91_set_B_periph(AT91_PIN_PA25, 0); /* ERX2 */
  153. at91_set_B_periph(AT91_PIN_PA26, 0); /* ERX3 */
  154. at91_set_B_periph(AT91_PIN_PA27, 0); /* ERXCK */
  155. at91_set_B_periph(AT91_PIN_PA23, 0); /* ETX2 */
  156. at91_set_B_periph(AT91_PIN_PA24, 0); /* ETX3 */
  157. at91_set_B_periph(AT91_PIN_PA22, 0); /* ETXER */
  158. }
  159. eth_data = *data;
  160. platform_device_register(&at91sam9260_eth_device);
  161. }
  162. #else
  163. void __init at91_add_device_eth(struct at91_eth_data *data) {}
  164. #endif
  165. /* --------------------------------------------------------------------
  166. * MMC / SD
  167. * -------------------------------------------------------------------- */
  168. #if defined(CONFIG_MMC_AT91) || defined(CONFIG_MMC_AT91_MODULE)
  169. static u64 mmc_dmamask = 0xffffffffUL;
  170. static struct at91_mmc_data mmc_data;
  171. static struct resource mmc_resources[] = {
  172. [0] = {
  173. .start = AT91SAM9260_BASE_MCI,
  174. .end = AT91SAM9260_BASE_MCI + SZ_16K - 1,
  175. .flags = IORESOURCE_MEM,
  176. },
  177. [1] = {
  178. .start = AT91SAM9260_ID_MCI,
  179. .end = AT91SAM9260_ID_MCI,
  180. .flags = IORESOURCE_IRQ,
  181. },
  182. };
  183. static struct platform_device at91sam9260_mmc_device = {
  184. .name = "at91_mci",
  185. .id = -1,
  186. .dev = {
  187. .dma_mask = &mmc_dmamask,
  188. .coherent_dma_mask = 0xffffffff,
  189. .platform_data = &mmc_data,
  190. },
  191. .resource = mmc_resources,
  192. .num_resources = ARRAY_SIZE(mmc_resources),
  193. };
  194. void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data)
  195. {
  196. if (!data)
  197. return;
  198. /* input/irq */
  199. if (data->det_pin) {
  200. at91_set_gpio_input(data->det_pin, 1);
  201. at91_set_deglitch(data->det_pin, 1);
  202. }
  203. if (data->wp_pin)
  204. at91_set_gpio_input(data->wp_pin, 1);
  205. if (data->vcc_pin)
  206. at91_set_gpio_output(data->vcc_pin, 0);
  207. /* CLK */
  208. at91_set_A_periph(AT91_PIN_PA8, 0);
  209. if (data->slot_b) {
  210. /* CMD */
  211. at91_set_B_periph(AT91_PIN_PA1, 1);
  212. /* DAT0, maybe DAT1..DAT3 */
  213. at91_set_B_periph(AT91_PIN_PA0, 1);
  214. if (data->wire4) {
  215. at91_set_B_periph(AT91_PIN_PA5, 1);
  216. at91_set_B_periph(AT91_PIN_PA4, 1);
  217. at91_set_B_periph(AT91_PIN_PA3, 1);
  218. }
  219. } else {
  220. /* CMD */
  221. at91_set_A_periph(AT91_PIN_PA7, 1);
  222. /* DAT0, maybe DAT1..DAT3 */
  223. at91_set_A_periph(AT91_PIN_PA6, 1);
  224. if (data->wire4) {
  225. at91_set_A_periph(AT91_PIN_PA9, 1);
  226. at91_set_A_periph(AT91_PIN_PA10, 1);
  227. at91_set_A_periph(AT91_PIN_PA11, 1);
  228. }
  229. }
  230. mmc_data = *data;
  231. platform_device_register(&at91sam9260_mmc_device);
  232. }
  233. #else
  234. void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) {}
  235. #endif
  236. /* --------------------------------------------------------------------
  237. * NAND / SmartMedia
  238. * -------------------------------------------------------------------- */
  239. #if defined(CONFIG_MTD_NAND_AT91) || defined(CONFIG_MTD_NAND_AT91_MODULE)
  240. static struct at91_nand_data nand_data;
  241. #define NAND_BASE AT91_CHIPSELECT_3
  242. static struct resource nand_resources[] = {
  243. {
  244. .start = NAND_BASE,
  245. .end = NAND_BASE + SZ_8M - 1,
  246. .flags = IORESOURCE_MEM,
  247. }
  248. };
  249. static struct platform_device at91sam9260_nand_device = {
  250. .name = "at91_nand",
  251. .id = -1,
  252. .dev = {
  253. .platform_data = &nand_data,
  254. },
  255. .resource = nand_resources,
  256. .num_resources = ARRAY_SIZE(nand_resources),
  257. };
  258. void __init at91_add_device_nand(struct at91_nand_data *data)
  259. {
  260. unsigned long csa, mode;
  261. if (!data)
  262. return;
  263. csa = at91_sys_read(AT91_MATRIX_EBICSA);
  264. at91_sys_write(AT91_MATRIX_EBICSA, csa | AT91_MATRIX_CS3A_SMC);
  265. /* set the bus interface characteristics */
  266. at91_sys_write(AT91_SMC_SETUP(3), AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0)
  267. | AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0));
  268. at91_sys_write(AT91_SMC_PULSE(3), AT91_SMC_NWEPULSE_(3) | AT91_SMC_NCS_WRPULSE_(3)
  269. | AT91_SMC_NRDPULSE_(3) | AT91_SMC_NCS_RDPULSE_(3));
  270. at91_sys_write(AT91_SMC_CYCLE(3), AT91_SMC_NWECYCLE_(5) | AT91_SMC_NRDCYCLE_(5));
  271. if (data->bus_width_16)
  272. mode = AT91_SMC_DBW_16;
  273. else
  274. mode = AT91_SMC_DBW_8;
  275. at91_sys_write(AT91_SMC_MODE(3), mode | AT91_SMC_READMODE | AT91_SMC_WRITEMODE | AT91_SMC_EXNWMODE_DISABLE | AT91_SMC_TDF_(2));
  276. /* enable pin */
  277. if (data->enable_pin)
  278. at91_set_gpio_output(data->enable_pin, 1);
  279. /* ready/busy pin */
  280. if (data->rdy_pin)
  281. at91_set_gpio_input(data->rdy_pin, 1);
  282. /* card detect pin */
  283. if (data->det_pin)
  284. at91_set_gpio_input(data->det_pin, 1);
  285. nand_data = *data;
  286. platform_device_register(&at91sam9260_nand_device);
  287. }
  288. #else
  289. void __init at91_add_device_nand(struct at91_nand_data *data) {}
  290. #endif
  291. /* --------------------------------------------------------------------
  292. * TWI (i2c)
  293. * -------------------------------------------------------------------- */
  294. #if defined(CONFIG_I2C_AT91) || defined(CONFIG_I2C_AT91_MODULE)
  295. static struct resource twi_resources[] = {
  296. [0] = {
  297. .start = AT91SAM9260_BASE_TWI,
  298. .end = AT91SAM9260_BASE_TWI + SZ_16K - 1,
  299. .flags = IORESOURCE_MEM,
  300. },
  301. [1] = {
  302. .start = AT91SAM9260_ID_TWI,
  303. .end = AT91SAM9260_ID_TWI,
  304. .flags = IORESOURCE_IRQ,
  305. },
  306. };
  307. static struct platform_device at91sam9260_twi_device = {
  308. .name = "at91_i2c",
  309. .id = -1,
  310. .resource = twi_resources,
  311. .num_resources = ARRAY_SIZE(twi_resources),
  312. };
  313. void __init at91_add_device_i2c(void)
  314. {
  315. /* pins used for TWI interface */
  316. at91_set_A_periph(AT91_PIN_PA23, 0); /* TWD */
  317. at91_set_multi_drive(AT91_PIN_PA23, 1);
  318. at91_set_A_periph(AT91_PIN_PA24, 0); /* TWCK */
  319. at91_set_multi_drive(AT91_PIN_PA24, 1);
  320. platform_device_register(&at91sam9260_twi_device);
  321. }
  322. #else
  323. void __init at91_add_device_i2c(void) {}
  324. #endif
  325. /* --------------------------------------------------------------------
  326. * SPI
  327. * -------------------------------------------------------------------- */
  328. #if defined(CONFIG_SPI_ATMEL) || defined(CONFIG_SPI_ATMEL_MODULE)
  329. static u64 spi_dmamask = 0xffffffffUL;
  330. static struct resource spi0_resources[] = {
  331. [0] = {
  332. .start = AT91SAM9260_BASE_SPI0,
  333. .end = AT91SAM9260_BASE_SPI0 + SZ_16K - 1,
  334. .flags = IORESOURCE_MEM,
  335. },
  336. [1] = {
  337. .start = AT91SAM9260_ID_SPI0,
  338. .end = AT91SAM9260_ID_SPI0,
  339. .flags = IORESOURCE_IRQ,
  340. },
  341. };
  342. static struct platform_device at91sam9260_spi0_device = {
  343. .name = "atmel_spi",
  344. .id = 0,
  345. .dev = {
  346. .dma_mask = &spi_dmamask,
  347. .coherent_dma_mask = 0xffffffff,
  348. },
  349. .resource = spi0_resources,
  350. .num_resources = ARRAY_SIZE(spi0_resources),
  351. };
  352. static const unsigned spi0_standard_cs[4] = { AT91_PIN_PA3, AT91_PIN_PC11, AT91_PIN_PC16, AT91_PIN_PC17 };
  353. static struct resource spi1_resources[] = {
  354. [0] = {
  355. .start = AT91SAM9260_BASE_SPI1,
  356. .end = AT91SAM9260_BASE_SPI1 + SZ_16K - 1,
  357. .flags = IORESOURCE_MEM,
  358. },
  359. [1] = {
  360. .start = AT91SAM9260_ID_SPI1,
  361. .end = AT91SAM9260_ID_SPI1,
  362. .flags = IORESOURCE_IRQ,
  363. },
  364. };
  365. static struct platform_device at91sam9260_spi1_device = {
  366. .name = "atmel_spi",
  367. .id = 1,
  368. .dev = {
  369. .dma_mask = &spi_dmamask,
  370. .coherent_dma_mask = 0xffffffff,
  371. },
  372. .resource = spi1_resources,
  373. .num_resources = ARRAY_SIZE(spi1_resources),
  374. };
  375. static const unsigned spi1_standard_cs[4] = { AT91_PIN_PB3, AT91_PIN_PC5, AT91_PIN_PC4, AT91_PIN_PC3 };
  376. void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices)
  377. {
  378. int i;
  379. unsigned long cs_pin;
  380. short enable_spi0 = 0;
  381. short enable_spi1 = 0;
  382. /* Choose SPI chip-selects */
  383. for (i = 0; i < nr_devices; i++) {
  384. if (devices[i].controller_data)
  385. cs_pin = (unsigned long) devices[i].controller_data;
  386. else if (devices[i].bus_num == 0)
  387. cs_pin = spi0_standard_cs[devices[i].chip_select];
  388. else
  389. cs_pin = spi1_standard_cs[devices[i].chip_select];
  390. if (devices[i].bus_num == 0)
  391. enable_spi0 = 1;
  392. else
  393. enable_spi1 = 1;
  394. /* enable chip-select pin */
  395. at91_set_gpio_output(cs_pin, 1);
  396. /* pass chip-select pin to driver */
  397. devices[i].controller_data = (void *) cs_pin;
  398. }
  399. spi_register_board_info(devices, nr_devices);
  400. /* Configure SPI bus(es) */
  401. if (enable_spi0) {
  402. at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */
  403. at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */
  404. at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI1_SPCK */
  405. at91_clock_associate("spi0_clk", &at91sam9260_spi0_device.dev, "spi_clk");
  406. platform_device_register(&at91sam9260_spi0_device);
  407. }
  408. if (enable_spi1) {
  409. at91_set_A_periph(AT91_PIN_PB0, 0); /* SPI1_MISO */
  410. at91_set_A_periph(AT91_PIN_PB1, 0); /* SPI1_MOSI */
  411. at91_set_A_periph(AT91_PIN_PB2, 0); /* SPI1_SPCK */
  412. at91_clock_associate("spi1_clk", &at91sam9260_spi1_device.dev, "spi_clk");
  413. platform_device_register(&at91sam9260_spi1_device);
  414. }
  415. }
  416. #else
  417. void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) {}
  418. #endif
  419. /* --------------------------------------------------------------------
  420. * LEDs
  421. * -------------------------------------------------------------------- */
  422. #if defined(CONFIG_LEDS)
  423. u8 at91_leds_cpu;
  424. u8 at91_leds_timer;
  425. void __init at91_init_leds(u8 cpu_led, u8 timer_led)
  426. {
  427. /* Enable GPIO to access the LEDs */
  428. at91_set_gpio_output(cpu_led, 1);
  429. at91_set_gpio_output(timer_led, 1);
  430. at91_leds_cpu = cpu_led;
  431. at91_leds_timer = timer_led;
  432. }
  433. #else
  434. void __init at91_init_leds(u8 cpu_led, u8 timer_led) {}
  435. #endif
  436. /* --------------------------------------------------------------------
  437. * UART
  438. * -------------------------------------------------------------------- */
  439. #if defined(CONFIG_SERIAL_ATMEL)
  440. static struct resource dbgu_resources[] = {
  441. [0] = {
  442. .start = AT91_VA_BASE_SYS + AT91_DBGU,
  443. .end = AT91_VA_BASE_SYS + AT91_DBGU + SZ_512 - 1,
  444. .flags = IORESOURCE_MEM,
  445. },
  446. [1] = {
  447. .start = AT91_ID_SYS,
  448. .end = AT91_ID_SYS,
  449. .flags = IORESOURCE_IRQ,
  450. },
  451. };
  452. static struct atmel_uart_data dbgu_data = {
  453. .use_dma_tx = 0,
  454. .use_dma_rx = 0, /* DBGU not capable of receive DMA */
  455. .regs = (void __iomem *)(AT91_VA_BASE_SYS + AT91_DBGU),
  456. };
  457. static struct platform_device at91sam9260_dbgu_device = {
  458. .name = "atmel_usart",
  459. .id = 0,
  460. .dev = {
  461. .platform_data = &dbgu_data,
  462. .coherent_dma_mask = 0xffffffff,
  463. },
  464. .resource = dbgu_resources,
  465. .num_resources = ARRAY_SIZE(dbgu_resources),
  466. };
  467. static inline void configure_dbgu_pins(void)
  468. {
  469. at91_set_A_periph(AT91_PIN_PB14, 0); /* DRXD */
  470. at91_set_A_periph(AT91_PIN_PB15, 1); /* DTXD */
  471. }
  472. static struct resource uart0_resources[] = {
  473. [0] = {
  474. .start = AT91SAM9260_BASE_US0,
  475. .end = AT91SAM9260_BASE_US0 + SZ_16K - 1,
  476. .flags = IORESOURCE_MEM,
  477. },
  478. [1] = {
  479. .start = AT91SAM9260_ID_US0,
  480. .end = AT91SAM9260_ID_US0,
  481. .flags = IORESOURCE_IRQ,
  482. },
  483. };
  484. static struct atmel_uart_data uart0_data = {
  485. .use_dma_tx = 1,
  486. .use_dma_rx = 1,
  487. };
  488. static struct platform_device at91sam9260_uart0_device = {
  489. .name = "atmel_usart",
  490. .id = 1,
  491. .dev = {
  492. .platform_data = &uart0_data,
  493. .coherent_dma_mask = 0xffffffff,
  494. },
  495. .resource = uart0_resources,
  496. .num_resources = ARRAY_SIZE(uart0_resources),
  497. };
  498. static inline void configure_usart0_pins(void)
  499. {
  500. at91_set_A_periph(AT91_PIN_PB4, 1); /* TXD0 */
  501. at91_set_A_periph(AT91_PIN_PB5, 0); /* RXD0 */
  502. at91_set_A_periph(AT91_PIN_PB26, 0); /* RTS0 */
  503. at91_set_A_periph(AT91_PIN_PB27, 0); /* CTS0 */
  504. at91_set_A_periph(AT91_PIN_PB24, 0); /* DTR0 */
  505. at91_set_A_periph(AT91_PIN_PB22, 0); /* DSR0 */
  506. at91_set_A_periph(AT91_PIN_PB23, 0); /* DCD0 */
  507. at91_set_A_periph(AT91_PIN_PB25, 0); /* RI0 */
  508. }
  509. static struct resource uart1_resources[] = {
  510. [0] = {
  511. .start = AT91SAM9260_BASE_US1,
  512. .end = AT91SAM9260_BASE_US1 + SZ_16K - 1,
  513. .flags = IORESOURCE_MEM,
  514. },
  515. [1] = {
  516. .start = AT91SAM9260_ID_US1,
  517. .end = AT91SAM9260_ID_US1,
  518. .flags = IORESOURCE_IRQ,
  519. },
  520. };
  521. static struct atmel_uart_data uart1_data = {
  522. .use_dma_tx = 1,
  523. .use_dma_rx = 1,
  524. };
  525. static struct platform_device at91sam9260_uart1_device = {
  526. .name = "atmel_usart",
  527. .id = 2,
  528. .dev = {
  529. .platform_data = &uart1_data,
  530. .coherent_dma_mask = 0xffffffff,
  531. },
  532. .resource = uart1_resources,
  533. .num_resources = ARRAY_SIZE(uart1_resources),
  534. };
  535. static inline void configure_usart1_pins(void)
  536. {
  537. at91_set_A_periph(AT91_PIN_PB6, 1); /* TXD1 */
  538. at91_set_A_periph(AT91_PIN_PB7, 0); /* RXD1 */
  539. at91_set_A_periph(AT91_PIN_PB28, 0); /* RTS1 */
  540. at91_set_A_periph(AT91_PIN_PB29, 0); /* CTS1 */
  541. }
  542. static struct resource uart2_resources[] = {
  543. [0] = {
  544. .start = AT91SAM9260_BASE_US2,
  545. .end = AT91SAM9260_BASE_US2 + SZ_16K - 1,
  546. .flags = IORESOURCE_MEM,
  547. },
  548. [1] = {
  549. .start = AT91SAM9260_ID_US2,
  550. .end = AT91SAM9260_ID_US2,
  551. .flags = IORESOURCE_IRQ,
  552. },
  553. };
  554. static struct atmel_uart_data uart2_data = {
  555. .use_dma_tx = 1,
  556. .use_dma_rx = 1,
  557. };
  558. static struct platform_device at91sam9260_uart2_device = {
  559. .name = "atmel_usart",
  560. .id = 3,
  561. .dev = {
  562. .platform_data = &uart2_data,
  563. .coherent_dma_mask = 0xffffffff,
  564. },
  565. .resource = uart2_resources,
  566. .num_resources = ARRAY_SIZE(uart2_resources),
  567. };
  568. static inline void configure_usart2_pins(void)
  569. {
  570. at91_set_A_periph(AT91_PIN_PB8, 1); /* TXD2 */
  571. at91_set_A_periph(AT91_PIN_PB9, 0); /* RXD2 */
  572. }
  573. static struct resource uart3_resources[] = {
  574. [0] = {
  575. .start = AT91SAM9260_BASE_US3,
  576. .end = AT91SAM9260_BASE_US3 + SZ_16K - 1,
  577. .flags = IORESOURCE_MEM,
  578. },
  579. [1] = {
  580. .start = AT91SAM9260_ID_US3,
  581. .end = AT91SAM9260_ID_US3,
  582. .flags = IORESOURCE_IRQ,
  583. },
  584. };
  585. static struct atmel_uart_data uart3_data = {
  586. .use_dma_tx = 1,
  587. .use_dma_rx = 1,
  588. };
  589. static struct platform_device at91sam9260_uart3_device = {
  590. .name = "atmel_usart",
  591. .id = 4,
  592. .dev = {
  593. .platform_data = &uart3_data,
  594. .coherent_dma_mask = 0xffffffff,
  595. },
  596. .resource = uart3_resources,
  597. .num_resources = ARRAY_SIZE(uart3_resources),
  598. };
  599. static inline void configure_usart3_pins(void)
  600. {
  601. at91_set_A_periph(AT91_PIN_PB10, 1); /* TXD3 */
  602. at91_set_A_periph(AT91_PIN_PB11, 0); /* RXD3 */
  603. }
  604. static struct resource uart4_resources[] = {
  605. [0] = {
  606. .start = AT91SAM9260_BASE_US4,
  607. .end = AT91SAM9260_BASE_US4 + SZ_16K - 1,
  608. .flags = IORESOURCE_MEM,
  609. },
  610. [1] = {
  611. .start = AT91SAM9260_ID_US4,
  612. .end = AT91SAM9260_ID_US4,
  613. .flags = IORESOURCE_IRQ,
  614. },
  615. };
  616. static struct atmel_uart_data uart4_data = {
  617. .use_dma_tx = 1,
  618. .use_dma_rx = 1,
  619. };
  620. static struct platform_device at91sam9260_uart4_device = {
  621. .name = "atmel_usart",
  622. .id = 5,
  623. .dev = {
  624. .platform_data = &uart4_data,
  625. .coherent_dma_mask = 0xffffffff,
  626. },
  627. .resource = uart4_resources,
  628. .num_resources = ARRAY_SIZE(uart4_resources),
  629. };
  630. static inline void configure_usart4_pins(void)
  631. {
  632. at91_set_B_periph(AT91_PIN_PA31, 1); /* TXD4 */
  633. at91_set_B_periph(AT91_PIN_PA30, 0); /* RXD4 */
  634. }
  635. static struct resource uart5_resources[] = {
  636. [0] = {
  637. .start = AT91SAM9260_BASE_US5,
  638. .end = AT91SAM9260_BASE_US5 + SZ_16K - 1,
  639. .flags = IORESOURCE_MEM,
  640. },
  641. [1] = {
  642. .start = AT91SAM9260_ID_US5,
  643. .end = AT91SAM9260_ID_US5,
  644. .flags = IORESOURCE_IRQ,
  645. },
  646. };
  647. static struct atmel_uart_data uart5_data = {
  648. .use_dma_tx = 1,
  649. .use_dma_rx = 1,
  650. };
  651. static struct platform_device at91sam9260_uart5_device = {
  652. .name = "atmel_usart",
  653. .id = 6,
  654. .dev = {
  655. .platform_data = &uart5_data,
  656. .coherent_dma_mask = 0xffffffff,
  657. },
  658. .resource = uart5_resources,
  659. .num_resources = ARRAY_SIZE(uart5_resources),
  660. };
  661. static inline void configure_usart5_pins(void)
  662. {
  663. at91_set_A_periph(AT91_PIN_PB12, 1); /* TXD5 */
  664. at91_set_A_periph(AT91_PIN_PB13, 0); /* RXD5 */
  665. }
  666. struct platform_device *at91_uarts[ATMEL_MAX_UART]; /* the UARTs to use */
  667. struct platform_device *atmel_default_console_device; /* the serial console device */
  668. void __init at91_init_serial(struct at91_uart_config *config)
  669. {
  670. int i;
  671. /* Fill in list of supported UARTs */
  672. for (i = 0; i < config->nr_tty; i++) {
  673. switch (config->tty_map[i]) {
  674. case 0:
  675. configure_usart0_pins();
  676. at91_uarts[i] = &at91sam9260_uart0_device;
  677. at91_clock_associate("usart0_clk", &at91sam9260_uart0_device.dev, "usart");
  678. break;
  679. case 1:
  680. configure_usart1_pins();
  681. at91_uarts[i] = &at91sam9260_uart1_device;
  682. at91_clock_associate("usart1_clk", &at91sam9260_uart1_device.dev, "usart");
  683. break;
  684. case 2:
  685. configure_usart2_pins();
  686. at91_uarts[i] = &at91sam9260_uart2_device;
  687. at91_clock_associate("usart2_clk", &at91sam9260_uart2_device.dev, "usart");
  688. break;
  689. case 3:
  690. configure_usart3_pins();
  691. at91_uarts[i] = &at91sam9260_uart3_device;
  692. at91_clock_associate("usart3_clk", &at91sam9260_uart3_device.dev, "usart");
  693. break;
  694. case 4:
  695. configure_usart4_pins();
  696. at91_uarts[i] = &at91sam9260_uart4_device;
  697. at91_clock_associate("usart4_clk", &at91sam9260_uart4_device.dev, "usart");
  698. break;
  699. case 5:
  700. configure_usart5_pins();
  701. at91_uarts[i] = &at91sam9260_uart5_device;
  702. at91_clock_associate("usart5_clk", &at91sam9260_uart5_device.dev, "usart");
  703. break;
  704. case 6:
  705. configure_dbgu_pins();
  706. at91_uarts[i] = &at91sam9260_dbgu_device;
  707. at91_clock_associate("mck", &at91sam9260_dbgu_device.dev, "usart");
  708. break;
  709. default:
  710. continue;
  711. }
  712. at91_uarts[i]->id = i; /* update ID number to mapped ID */
  713. }
  714. /* Set serial console device */
  715. if (config->console_tty < ATMEL_MAX_UART)
  716. atmel_default_console_device = at91_uarts[config->console_tty];
  717. if (!atmel_default_console_device)
  718. printk(KERN_INFO "AT91: No default serial console defined.\n");
  719. }
  720. void __init at91_add_device_serial(void)
  721. {
  722. int i;
  723. for (i = 0; i < ATMEL_MAX_UART; i++) {
  724. if (at91_uarts[i])
  725. platform_device_register(at91_uarts[i]);
  726. }
  727. }
  728. #else
  729. void __init at91_init_serial(struct at91_uart_config *config) {}
  730. void __init at91_add_device_serial(void) {}
  731. #endif
  732. /* -------------------------------------------------------------------- */
  733. /*
  734. * These devices are always present and don't need any board-specific
  735. * setup.
  736. */
  737. static int __init at91_add_standard_devices(void)
  738. {
  739. return 0;
  740. }
  741. arch_initcall(at91_add_standard_devices);