tx.c 30 KB

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  1. /****************************************************************************
  2. * Driver for Solarflare Solarstorm network controllers and boards
  3. * Copyright 2005-2006 Fen Systems Ltd.
  4. * Copyright 2005-2008 Solarflare Communications Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published
  8. * by the Free Software Foundation, incorporated herein by reference.
  9. */
  10. #include <linux/pci.h>
  11. #include <linux/tcp.h>
  12. #include <linux/ip.h>
  13. #include <linux/in.h>
  14. #include <linux/if_ether.h>
  15. #include <linux/highmem.h>
  16. #include "net_driver.h"
  17. #include "efx.h"
  18. #include "nic.h"
  19. #include "workarounds.h"
  20. /*
  21. * TX descriptor ring full threshold
  22. *
  23. * The tx_queue descriptor ring fill-level must fall below this value
  24. * before we restart the netif queue
  25. */
  26. #define EFX_TXQ_THRESHOLD (EFX_TXQ_MASK / 2u)
  27. /* We want to be able to nest calls to netif_stop_queue(), since each
  28. * channel can have an individual stop on the queue.
  29. */
  30. void efx_stop_queue(struct efx_nic *efx)
  31. {
  32. spin_lock_bh(&efx->netif_stop_lock);
  33. EFX_TRACE(efx, "stop TX queue\n");
  34. atomic_inc(&efx->netif_stop_count);
  35. netif_stop_queue(efx->net_dev);
  36. spin_unlock_bh(&efx->netif_stop_lock);
  37. }
  38. /* Wake netif's TX queue
  39. * We want to be able to nest calls to netif_stop_queue(), since each
  40. * channel can have an individual stop on the queue.
  41. */
  42. void efx_wake_queue(struct efx_nic *efx)
  43. {
  44. local_bh_disable();
  45. if (atomic_dec_and_lock(&efx->netif_stop_count,
  46. &efx->netif_stop_lock)) {
  47. EFX_TRACE(efx, "waking TX queue\n");
  48. netif_wake_queue(efx->net_dev);
  49. spin_unlock(&efx->netif_stop_lock);
  50. }
  51. local_bh_enable();
  52. }
  53. static void efx_dequeue_buffer(struct efx_tx_queue *tx_queue,
  54. struct efx_tx_buffer *buffer)
  55. {
  56. if (buffer->unmap_len) {
  57. struct pci_dev *pci_dev = tx_queue->efx->pci_dev;
  58. dma_addr_t unmap_addr = (buffer->dma_addr + buffer->len -
  59. buffer->unmap_len);
  60. if (buffer->unmap_single)
  61. pci_unmap_single(pci_dev, unmap_addr, buffer->unmap_len,
  62. PCI_DMA_TODEVICE);
  63. else
  64. pci_unmap_page(pci_dev, unmap_addr, buffer->unmap_len,
  65. PCI_DMA_TODEVICE);
  66. buffer->unmap_len = 0;
  67. buffer->unmap_single = false;
  68. }
  69. if (buffer->skb) {
  70. dev_kfree_skb_any((struct sk_buff *) buffer->skb);
  71. buffer->skb = NULL;
  72. EFX_TRACE(tx_queue->efx, "TX queue %d transmission id %x "
  73. "complete\n", tx_queue->queue, read_ptr);
  74. }
  75. }
  76. /**
  77. * struct efx_tso_header - a DMA mapped buffer for packet headers
  78. * @next: Linked list of free ones.
  79. * The list is protected by the TX queue lock.
  80. * @dma_unmap_len: Length to unmap for an oversize buffer, or 0.
  81. * @dma_addr: The DMA address of the header below.
  82. *
  83. * This controls the memory used for a TSO header. Use TSOH_DATA()
  84. * to find the packet header data. Use TSOH_SIZE() to calculate the
  85. * total size required for a given packet header length. TSO headers
  86. * in the free list are exactly %TSOH_STD_SIZE bytes in size.
  87. */
  88. struct efx_tso_header {
  89. union {
  90. struct efx_tso_header *next;
  91. size_t unmap_len;
  92. };
  93. dma_addr_t dma_addr;
  94. };
  95. static int efx_enqueue_skb_tso(struct efx_tx_queue *tx_queue,
  96. struct sk_buff *skb);
  97. static void efx_fini_tso(struct efx_tx_queue *tx_queue);
  98. static void efx_tsoh_heap_free(struct efx_tx_queue *tx_queue,
  99. struct efx_tso_header *tsoh);
  100. static void efx_tsoh_free(struct efx_tx_queue *tx_queue,
  101. struct efx_tx_buffer *buffer)
  102. {
  103. if (buffer->tsoh) {
  104. if (likely(!buffer->tsoh->unmap_len)) {
  105. buffer->tsoh->next = tx_queue->tso_headers_free;
  106. tx_queue->tso_headers_free = buffer->tsoh;
  107. } else {
  108. efx_tsoh_heap_free(tx_queue, buffer->tsoh);
  109. }
  110. buffer->tsoh = NULL;
  111. }
  112. }
  113. static inline unsigned
  114. efx_max_tx_len(struct efx_nic *efx, dma_addr_t dma_addr)
  115. {
  116. /* Depending on the NIC revision, we can use descriptor
  117. * lengths up to 8K or 8K-1. However, since PCI Express
  118. * devices must split read requests at 4K boundaries, there is
  119. * little benefit from using descriptors that cross those
  120. * boundaries and we keep things simple by not doing so.
  121. */
  122. unsigned len = (~dma_addr & 0xfff) + 1;
  123. /* Work around hardware bug for unaligned buffers. */
  124. if (EFX_WORKAROUND_5391(efx) && (dma_addr & 0xf))
  125. len = min_t(unsigned, len, 512 - (dma_addr & 0xf));
  126. return len;
  127. }
  128. /*
  129. * Add a socket buffer to a TX queue
  130. *
  131. * This maps all fragments of a socket buffer for DMA and adds them to
  132. * the TX queue. The queue's insert pointer will be incremented by
  133. * the number of fragments in the socket buffer.
  134. *
  135. * If any DMA mapping fails, any mapped fragments will be unmapped,
  136. * the queue's insert pointer will be restored to its original value.
  137. *
  138. * This function is split out from efx_hard_start_xmit to allow the
  139. * loopback test to direct packets via specific TX queues.
  140. *
  141. * Returns NETDEV_TX_OK or NETDEV_TX_BUSY
  142. * You must hold netif_tx_lock() to call this function.
  143. */
  144. netdev_tx_t efx_enqueue_skb(struct efx_tx_queue *tx_queue, struct sk_buff *skb)
  145. {
  146. struct efx_nic *efx = tx_queue->efx;
  147. struct pci_dev *pci_dev = efx->pci_dev;
  148. struct efx_tx_buffer *buffer;
  149. skb_frag_t *fragment;
  150. struct page *page;
  151. int page_offset;
  152. unsigned int len, unmap_len = 0, fill_level, insert_ptr;
  153. dma_addr_t dma_addr, unmap_addr = 0;
  154. unsigned int dma_len;
  155. bool unmap_single;
  156. int q_space, i = 0;
  157. netdev_tx_t rc = NETDEV_TX_OK;
  158. EFX_BUG_ON_PARANOID(tx_queue->write_count != tx_queue->insert_count);
  159. if (skb_shinfo(skb)->gso_size)
  160. return efx_enqueue_skb_tso(tx_queue, skb);
  161. /* Get size of the initial fragment */
  162. len = skb_headlen(skb);
  163. /* Pad if necessary */
  164. if (EFX_WORKAROUND_15592(efx) && skb->len <= 32) {
  165. EFX_BUG_ON_PARANOID(skb->data_len);
  166. len = 32 + 1;
  167. if (skb_pad(skb, len - skb->len))
  168. return NETDEV_TX_OK;
  169. }
  170. fill_level = tx_queue->insert_count - tx_queue->old_read_count;
  171. q_space = EFX_TXQ_MASK - 1 - fill_level;
  172. /* Map for DMA. Use pci_map_single rather than pci_map_page
  173. * since this is more efficient on machines with sparse
  174. * memory.
  175. */
  176. unmap_single = true;
  177. dma_addr = pci_map_single(pci_dev, skb->data, len, PCI_DMA_TODEVICE);
  178. /* Process all fragments */
  179. while (1) {
  180. if (unlikely(pci_dma_mapping_error(pci_dev, dma_addr)))
  181. goto pci_err;
  182. /* Store fields for marking in the per-fragment final
  183. * descriptor */
  184. unmap_len = len;
  185. unmap_addr = dma_addr;
  186. /* Add to TX queue, splitting across DMA boundaries */
  187. do {
  188. if (unlikely(q_space-- <= 0)) {
  189. /* It might be that completions have
  190. * happened since the xmit path last
  191. * checked. Update the xmit path's
  192. * copy of read_count.
  193. */
  194. ++tx_queue->stopped;
  195. /* This memory barrier protects the
  196. * change of stopped from the access
  197. * of read_count. */
  198. smp_mb();
  199. tx_queue->old_read_count =
  200. *(volatile unsigned *)
  201. &tx_queue->read_count;
  202. fill_level = (tx_queue->insert_count
  203. - tx_queue->old_read_count);
  204. q_space = EFX_TXQ_MASK - 1 - fill_level;
  205. if (unlikely(q_space-- <= 0))
  206. goto stop;
  207. smp_mb();
  208. --tx_queue->stopped;
  209. }
  210. insert_ptr = tx_queue->insert_count & EFX_TXQ_MASK;
  211. buffer = &tx_queue->buffer[insert_ptr];
  212. efx_tsoh_free(tx_queue, buffer);
  213. EFX_BUG_ON_PARANOID(buffer->tsoh);
  214. EFX_BUG_ON_PARANOID(buffer->skb);
  215. EFX_BUG_ON_PARANOID(buffer->len);
  216. EFX_BUG_ON_PARANOID(!buffer->continuation);
  217. EFX_BUG_ON_PARANOID(buffer->unmap_len);
  218. dma_len = efx_max_tx_len(efx, dma_addr);
  219. if (likely(dma_len >= len))
  220. dma_len = len;
  221. /* Fill out per descriptor fields */
  222. buffer->len = dma_len;
  223. buffer->dma_addr = dma_addr;
  224. len -= dma_len;
  225. dma_addr += dma_len;
  226. ++tx_queue->insert_count;
  227. } while (len);
  228. /* Transfer ownership of the unmapping to the final buffer */
  229. buffer->unmap_single = unmap_single;
  230. buffer->unmap_len = unmap_len;
  231. unmap_len = 0;
  232. /* Get address and size of next fragment */
  233. if (i >= skb_shinfo(skb)->nr_frags)
  234. break;
  235. fragment = &skb_shinfo(skb)->frags[i];
  236. len = fragment->size;
  237. page = fragment->page;
  238. page_offset = fragment->page_offset;
  239. i++;
  240. /* Map for DMA */
  241. unmap_single = false;
  242. dma_addr = pci_map_page(pci_dev, page, page_offset, len,
  243. PCI_DMA_TODEVICE);
  244. }
  245. /* Transfer ownership of the skb to the final buffer */
  246. buffer->skb = skb;
  247. buffer->continuation = false;
  248. /* Pass off to hardware */
  249. efx_nic_push_buffers(tx_queue);
  250. return NETDEV_TX_OK;
  251. pci_err:
  252. EFX_ERR_RL(efx, " TX queue %d could not map skb with %d bytes %d "
  253. "fragments for DMA\n", tx_queue->queue, skb->len,
  254. skb_shinfo(skb)->nr_frags + 1);
  255. /* Mark the packet as transmitted, and free the SKB ourselves */
  256. dev_kfree_skb_any(skb);
  257. goto unwind;
  258. stop:
  259. rc = NETDEV_TX_BUSY;
  260. if (tx_queue->stopped == 1)
  261. efx_stop_queue(efx);
  262. unwind:
  263. /* Work backwards until we hit the original insert pointer value */
  264. while (tx_queue->insert_count != tx_queue->write_count) {
  265. --tx_queue->insert_count;
  266. insert_ptr = tx_queue->insert_count & EFX_TXQ_MASK;
  267. buffer = &tx_queue->buffer[insert_ptr];
  268. efx_dequeue_buffer(tx_queue, buffer);
  269. buffer->len = 0;
  270. }
  271. /* Free the fragment we were mid-way through pushing */
  272. if (unmap_len) {
  273. if (unmap_single)
  274. pci_unmap_single(pci_dev, unmap_addr, unmap_len,
  275. PCI_DMA_TODEVICE);
  276. else
  277. pci_unmap_page(pci_dev, unmap_addr, unmap_len,
  278. PCI_DMA_TODEVICE);
  279. }
  280. return rc;
  281. }
  282. /* Remove packets from the TX queue
  283. *
  284. * This removes packets from the TX queue, up to and including the
  285. * specified index.
  286. */
  287. static void efx_dequeue_buffers(struct efx_tx_queue *tx_queue,
  288. unsigned int index)
  289. {
  290. struct efx_nic *efx = tx_queue->efx;
  291. unsigned int stop_index, read_ptr;
  292. stop_index = (index + 1) & EFX_TXQ_MASK;
  293. read_ptr = tx_queue->read_count & EFX_TXQ_MASK;
  294. while (read_ptr != stop_index) {
  295. struct efx_tx_buffer *buffer = &tx_queue->buffer[read_ptr];
  296. if (unlikely(buffer->len == 0)) {
  297. EFX_ERR(tx_queue->efx, "TX queue %d spurious TX "
  298. "completion id %x\n", tx_queue->queue,
  299. read_ptr);
  300. efx_schedule_reset(efx, RESET_TYPE_TX_SKIP);
  301. return;
  302. }
  303. efx_dequeue_buffer(tx_queue, buffer);
  304. buffer->continuation = true;
  305. buffer->len = 0;
  306. ++tx_queue->read_count;
  307. read_ptr = tx_queue->read_count & EFX_TXQ_MASK;
  308. }
  309. }
  310. /* Initiate a packet transmission. We use one channel per CPU
  311. * (sharing when we have more CPUs than channels). On Falcon, the TX
  312. * completion events will be directed back to the CPU that transmitted
  313. * the packet, which should be cache-efficient.
  314. *
  315. * Context: non-blocking.
  316. * Note that returning anything other than NETDEV_TX_OK will cause the
  317. * OS to free the skb.
  318. */
  319. netdev_tx_t efx_hard_start_xmit(struct sk_buff *skb,
  320. struct net_device *net_dev)
  321. {
  322. struct efx_nic *efx = netdev_priv(net_dev);
  323. struct efx_tx_queue *tx_queue;
  324. if (unlikely(efx->port_inhibited))
  325. return NETDEV_TX_BUSY;
  326. if (likely(skb->ip_summed == CHECKSUM_PARTIAL))
  327. tx_queue = &efx->tx_queue[EFX_TX_QUEUE_OFFLOAD_CSUM];
  328. else
  329. tx_queue = &efx->tx_queue[EFX_TX_QUEUE_NO_CSUM];
  330. return efx_enqueue_skb(tx_queue, skb);
  331. }
  332. void efx_xmit_done(struct efx_tx_queue *tx_queue, unsigned int index)
  333. {
  334. unsigned fill_level;
  335. struct efx_nic *efx = tx_queue->efx;
  336. EFX_BUG_ON_PARANOID(index > EFX_TXQ_MASK);
  337. efx_dequeue_buffers(tx_queue, index);
  338. /* See if we need to restart the netif queue. This barrier
  339. * separates the update of read_count from the test of
  340. * stopped. */
  341. smp_mb();
  342. if (unlikely(tx_queue->stopped) && likely(efx->port_enabled)) {
  343. fill_level = tx_queue->insert_count - tx_queue->read_count;
  344. if (fill_level < EFX_TXQ_THRESHOLD) {
  345. EFX_BUG_ON_PARANOID(!efx_dev_registered(efx));
  346. /* Do this under netif_tx_lock(), to avoid racing
  347. * with efx_xmit(). */
  348. netif_tx_lock(efx->net_dev);
  349. if (tx_queue->stopped) {
  350. tx_queue->stopped = 0;
  351. efx_wake_queue(efx);
  352. }
  353. netif_tx_unlock(efx->net_dev);
  354. }
  355. }
  356. }
  357. int efx_probe_tx_queue(struct efx_tx_queue *tx_queue)
  358. {
  359. struct efx_nic *efx = tx_queue->efx;
  360. unsigned int txq_size;
  361. int i, rc;
  362. EFX_LOG(efx, "creating TX queue %d\n", tx_queue->queue);
  363. /* Allocate software ring */
  364. txq_size = EFX_TXQ_SIZE * sizeof(*tx_queue->buffer);
  365. tx_queue->buffer = kzalloc(txq_size, GFP_KERNEL);
  366. if (!tx_queue->buffer)
  367. return -ENOMEM;
  368. for (i = 0; i <= EFX_TXQ_MASK; ++i)
  369. tx_queue->buffer[i].continuation = true;
  370. /* Allocate hardware ring */
  371. rc = efx_nic_probe_tx(tx_queue);
  372. if (rc)
  373. goto fail;
  374. return 0;
  375. fail:
  376. kfree(tx_queue->buffer);
  377. tx_queue->buffer = NULL;
  378. return rc;
  379. }
  380. void efx_init_tx_queue(struct efx_tx_queue *tx_queue)
  381. {
  382. EFX_LOG(tx_queue->efx, "initialising TX queue %d\n", tx_queue->queue);
  383. tx_queue->insert_count = 0;
  384. tx_queue->write_count = 0;
  385. tx_queue->read_count = 0;
  386. tx_queue->old_read_count = 0;
  387. BUG_ON(tx_queue->stopped);
  388. /* Set up TX descriptor ring */
  389. efx_nic_init_tx(tx_queue);
  390. }
  391. void efx_release_tx_buffers(struct efx_tx_queue *tx_queue)
  392. {
  393. struct efx_tx_buffer *buffer;
  394. if (!tx_queue->buffer)
  395. return;
  396. /* Free any buffers left in the ring */
  397. while (tx_queue->read_count != tx_queue->write_count) {
  398. buffer = &tx_queue->buffer[tx_queue->read_count & EFX_TXQ_MASK];
  399. efx_dequeue_buffer(tx_queue, buffer);
  400. buffer->continuation = true;
  401. buffer->len = 0;
  402. ++tx_queue->read_count;
  403. }
  404. }
  405. void efx_fini_tx_queue(struct efx_tx_queue *tx_queue)
  406. {
  407. EFX_LOG(tx_queue->efx, "shutting down TX queue %d\n", tx_queue->queue);
  408. /* Flush TX queue, remove descriptor ring */
  409. efx_nic_fini_tx(tx_queue);
  410. efx_release_tx_buffers(tx_queue);
  411. /* Free up TSO header cache */
  412. efx_fini_tso(tx_queue);
  413. /* Release queue's stop on port, if any */
  414. if (tx_queue->stopped) {
  415. tx_queue->stopped = 0;
  416. efx_wake_queue(tx_queue->efx);
  417. }
  418. }
  419. void efx_remove_tx_queue(struct efx_tx_queue *tx_queue)
  420. {
  421. EFX_LOG(tx_queue->efx, "destroying TX queue %d\n", tx_queue->queue);
  422. efx_nic_remove_tx(tx_queue);
  423. kfree(tx_queue->buffer);
  424. tx_queue->buffer = NULL;
  425. }
  426. /* Efx TCP segmentation acceleration.
  427. *
  428. * Why? Because by doing it here in the driver we can go significantly
  429. * faster than the GSO.
  430. *
  431. * Requires TX checksum offload support.
  432. */
  433. /* Number of bytes inserted at the start of a TSO header buffer,
  434. * similar to NET_IP_ALIGN.
  435. */
  436. #ifdef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
  437. #define TSOH_OFFSET 0
  438. #else
  439. #define TSOH_OFFSET NET_IP_ALIGN
  440. #endif
  441. #define TSOH_BUFFER(tsoh) ((u8 *)(tsoh + 1) + TSOH_OFFSET)
  442. /* Total size of struct efx_tso_header, buffer and padding */
  443. #define TSOH_SIZE(hdr_len) \
  444. (sizeof(struct efx_tso_header) + TSOH_OFFSET + hdr_len)
  445. /* Size of blocks on free list. Larger blocks must be allocated from
  446. * the heap.
  447. */
  448. #define TSOH_STD_SIZE 128
  449. #define PTR_DIFF(p1, p2) ((u8 *)(p1) - (u8 *)(p2))
  450. #define ETH_HDR_LEN(skb) (skb_network_header(skb) - (skb)->data)
  451. #define SKB_TCP_OFF(skb) PTR_DIFF(tcp_hdr(skb), (skb)->data)
  452. #define SKB_IPV4_OFF(skb) PTR_DIFF(ip_hdr(skb), (skb)->data)
  453. /**
  454. * struct tso_state - TSO state for an SKB
  455. * @out_len: Remaining length in current segment
  456. * @seqnum: Current sequence number
  457. * @ipv4_id: Current IPv4 ID, host endian
  458. * @packet_space: Remaining space in current packet
  459. * @dma_addr: DMA address of current position
  460. * @in_len: Remaining length in current SKB fragment
  461. * @unmap_len: Length of SKB fragment
  462. * @unmap_addr: DMA address of SKB fragment
  463. * @unmap_single: DMA single vs page mapping flag
  464. * @header_len: Number of bytes of header
  465. * @full_packet_size: Number of bytes to put in each outgoing segment
  466. *
  467. * The state used during segmentation. It is put into this data structure
  468. * just to make it easy to pass into inline functions.
  469. */
  470. struct tso_state {
  471. /* Output position */
  472. unsigned out_len;
  473. unsigned seqnum;
  474. unsigned ipv4_id;
  475. unsigned packet_space;
  476. /* Input position */
  477. dma_addr_t dma_addr;
  478. unsigned in_len;
  479. unsigned unmap_len;
  480. dma_addr_t unmap_addr;
  481. bool unmap_single;
  482. unsigned header_len;
  483. int full_packet_size;
  484. };
  485. /*
  486. * Verify that our various assumptions about sk_buffs and the conditions
  487. * under which TSO will be attempted hold true.
  488. */
  489. static void efx_tso_check_safe(struct sk_buff *skb)
  490. {
  491. __be16 protocol = skb->protocol;
  492. EFX_BUG_ON_PARANOID(((struct ethhdr *)skb->data)->h_proto !=
  493. protocol);
  494. if (protocol == htons(ETH_P_8021Q)) {
  495. /* Find the encapsulated protocol; reset network header
  496. * and transport header based on that. */
  497. struct vlan_ethhdr *veh = (struct vlan_ethhdr *)skb->data;
  498. protocol = veh->h_vlan_encapsulated_proto;
  499. skb_set_network_header(skb, sizeof(*veh));
  500. if (protocol == htons(ETH_P_IP))
  501. skb_set_transport_header(skb, sizeof(*veh) +
  502. 4 * ip_hdr(skb)->ihl);
  503. }
  504. EFX_BUG_ON_PARANOID(protocol != htons(ETH_P_IP));
  505. EFX_BUG_ON_PARANOID(ip_hdr(skb)->protocol != IPPROTO_TCP);
  506. EFX_BUG_ON_PARANOID((PTR_DIFF(tcp_hdr(skb), skb->data)
  507. + (tcp_hdr(skb)->doff << 2u)) >
  508. skb_headlen(skb));
  509. }
  510. /*
  511. * Allocate a page worth of efx_tso_header structures, and string them
  512. * into the tx_queue->tso_headers_free linked list. Return 0 or -ENOMEM.
  513. */
  514. static int efx_tsoh_block_alloc(struct efx_tx_queue *tx_queue)
  515. {
  516. struct pci_dev *pci_dev = tx_queue->efx->pci_dev;
  517. struct efx_tso_header *tsoh;
  518. dma_addr_t dma_addr;
  519. u8 *base_kva, *kva;
  520. base_kva = pci_alloc_consistent(pci_dev, PAGE_SIZE, &dma_addr);
  521. if (base_kva == NULL) {
  522. EFX_ERR(tx_queue->efx, "Unable to allocate page for TSO"
  523. " headers\n");
  524. return -ENOMEM;
  525. }
  526. /* pci_alloc_consistent() allocates pages. */
  527. EFX_BUG_ON_PARANOID(dma_addr & (PAGE_SIZE - 1u));
  528. for (kva = base_kva; kva < base_kva + PAGE_SIZE; kva += TSOH_STD_SIZE) {
  529. tsoh = (struct efx_tso_header *)kva;
  530. tsoh->dma_addr = dma_addr + (TSOH_BUFFER(tsoh) - base_kva);
  531. tsoh->next = tx_queue->tso_headers_free;
  532. tx_queue->tso_headers_free = tsoh;
  533. }
  534. return 0;
  535. }
  536. /* Free up a TSO header, and all others in the same page. */
  537. static void efx_tsoh_block_free(struct efx_tx_queue *tx_queue,
  538. struct efx_tso_header *tsoh,
  539. struct pci_dev *pci_dev)
  540. {
  541. struct efx_tso_header **p;
  542. unsigned long base_kva;
  543. dma_addr_t base_dma;
  544. base_kva = (unsigned long)tsoh & PAGE_MASK;
  545. base_dma = tsoh->dma_addr & PAGE_MASK;
  546. p = &tx_queue->tso_headers_free;
  547. while (*p != NULL) {
  548. if (((unsigned long)*p & PAGE_MASK) == base_kva)
  549. *p = (*p)->next;
  550. else
  551. p = &(*p)->next;
  552. }
  553. pci_free_consistent(pci_dev, PAGE_SIZE, (void *)base_kva, base_dma);
  554. }
  555. static struct efx_tso_header *
  556. efx_tsoh_heap_alloc(struct efx_tx_queue *tx_queue, size_t header_len)
  557. {
  558. struct efx_tso_header *tsoh;
  559. tsoh = kmalloc(TSOH_SIZE(header_len), GFP_ATOMIC | GFP_DMA);
  560. if (unlikely(!tsoh))
  561. return NULL;
  562. tsoh->dma_addr = pci_map_single(tx_queue->efx->pci_dev,
  563. TSOH_BUFFER(tsoh), header_len,
  564. PCI_DMA_TODEVICE);
  565. if (unlikely(pci_dma_mapping_error(tx_queue->efx->pci_dev,
  566. tsoh->dma_addr))) {
  567. kfree(tsoh);
  568. return NULL;
  569. }
  570. tsoh->unmap_len = header_len;
  571. return tsoh;
  572. }
  573. static void
  574. efx_tsoh_heap_free(struct efx_tx_queue *tx_queue, struct efx_tso_header *tsoh)
  575. {
  576. pci_unmap_single(tx_queue->efx->pci_dev,
  577. tsoh->dma_addr, tsoh->unmap_len,
  578. PCI_DMA_TODEVICE);
  579. kfree(tsoh);
  580. }
  581. /**
  582. * efx_tx_queue_insert - push descriptors onto the TX queue
  583. * @tx_queue: Efx TX queue
  584. * @dma_addr: DMA address of fragment
  585. * @len: Length of fragment
  586. * @final_buffer: The final buffer inserted into the queue
  587. *
  588. * Push descriptors onto the TX queue. Return 0 on success or 1 if
  589. * @tx_queue full.
  590. */
  591. static int efx_tx_queue_insert(struct efx_tx_queue *tx_queue,
  592. dma_addr_t dma_addr, unsigned len,
  593. struct efx_tx_buffer **final_buffer)
  594. {
  595. struct efx_tx_buffer *buffer;
  596. struct efx_nic *efx = tx_queue->efx;
  597. unsigned dma_len, fill_level, insert_ptr;
  598. int q_space;
  599. EFX_BUG_ON_PARANOID(len <= 0);
  600. fill_level = tx_queue->insert_count - tx_queue->old_read_count;
  601. /* -1 as there is no way to represent all descriptors used */
  602. q_space = EFX_TXQ_MASK - 1 - fill_level;
  603. while (1) {
  604. if (unlikely(q_space-- <= 0)) {
  605. /* It might be that completions have happened
  606. * since the xmit path last checked. Update
  607. * the xmit path's copy of read_count.
  608. */
  609. ++tx_queue->stopped;
  610. /* This memory barrier protects the change of
  611. * stopped from the access of read_count. */
  612. smp_mb();
  613. tx_queue->old_read_count =
  614. *(volatile unsigned *)&tx_queue->read_count;
  615. fill_level = (tx_queue->insert_count
  616. - tx_queue->old_read_count);
  617. q_space = EFX_TXQ_MASK - 1 - fill_level;
  618. if (unlikely(q_space-- <= 0)) {
  619. *final_buffer = NULL;
  620. return 1;
  621. }
  622. smp_mb();
  623. --tx_queue->stopped;
  624. }
  625. insert_ptr = tx_queue->insert_count & EFX_TXQ_MASK;
  626. buffer = &tx_queue->buffer[insert_ptr];
  627. ++tx_queue->insert_count;
  628. EFX_BUG_ON_PARANOID(tx_queue->insert_count -
  629. tx_queue->read_count >
  630. EFX_TXQ_MASK);
  631. efx_tsoh_free(tx_queue, buffer);
  632. EFX_BUG_ON_PARANOID(buffer->len);
  633. EFX_BUG_ON_PARANOID(buffer->unmap_len);
  634. EFX_BUG_ON_PARANOID(buffer->skb);
  635. EFX_BUG_ON_PARANOID(!buffer->continuation);
  636. EFX_BUG_ON_PARANOID(buffer->tsoh);
  637. buffer->dma_addr = dma_addr;
  638. dma_len = efx_max_tx_len(efx, dma_addr);
  639. /* If there is enough space to send then do so */
  640. if (dma_len >= len)
  641. break;
  642. buffer->len = dma_len; /* Don't set the other members */
  643. dma_addr += dma_len;
  644. len -= dma_len;
  645. }
  646. EFX_BUG_ON_PARANOID(!len);
  647. buffer->len = len;
  648. *final_buffer = buffer;
  649. return 0;
  650. }
  651. /*
  652. * Put a TSO header into the TX queue.
  653. *
  654. * This is special-cased because we know that it is small enough to fit in
  655. * a single fragment, and we know it doesn't cross a page boundary. It
  656. * also allows us to not worry about end-of-packet etc.
  657. */
  658. static void efx_tso_put_header(struct efx_tx_queue *tx_queue,
  659. struct efx_tso_header *tsoh, unsigned len)
  660. {
  661. struct efx_tx_buffer *buffer;
  662. buffer = &tx_queue->buffer[tx_queue->insert_count & EFX_TXQ_MASK];
  663. efx_tsoh_free(tx_queue, buffer);
  664. EFX_BUG_ON_PARANOID(buffer->len);
  665. EFX_BUG_ON_PARANOID(buffer->unmap_len);
  666. EFX_BUG_ON_PARANOID(buffer->skb);
  667. EFX_BUG_ON_PARANOID(!buffer->continuation);
  668. EFX_BUG_ON_PARANOID(buffer->tsoh);
  669. buffer->len = len;
  670. buffer->dma_addr = tsoh->dma_addr;
  671. buffer->tsoh = tsoh;
  672. ++tx_queue->insert_count;
  673. }
  674. /* Remove descriptors put into a tx_queue. */
  675. static void efx_enqueue_unwind(struct efx_tx_queue *tx_queue)
  676. {
  677. struct efx_tx_buffer *buffer;
  678. dma_addr_t unmap_addr;
  679. /* Work backwards until we hit the original insert pointer value */
  680. while (tx_queue->insert_count != tx_queue->write_count) {
  681. --tx_queue->insert_count;
  682. buffer = &tx_queue->buffer[tx_queue->insert_count &
  683. EFX_TXQ_MASK];
  684. efx_tsoh_free(tx_queue, buffer);
  685. EFX_BUG_ON_PARANOID(buffer->skb);
  686. buffer->len = 0;
  687. buffer->continuation = true;
  688. if (buffer->unmap_len) {
  689. unmap_addr = (buffer->dma_addr + buffer->len -
  690. buffer->unmap_len);
  691. if (buffer->unmap_single)
  692. pci_unmap_single(tx_queue->efx->pci_dev,
  693. unmap_addr, buffer->unmap_len,
  694. PCI_DMA_TODEVICE);
  695. else
  696. pci_unmap_page(tx_queue->efx->pci_dev,
  697. unmap_addr, buffer->unmap_len,
  698. PCI_DMA_TODEVICE);
  699. buffer->unmap_len = 0;
  700. }
  701. }
  702. }
  703. /* Parse the SKB header and initialise state. */
  704. static void tso_start(struct tso_state *st, const struct sk_buff *skb)
  705. {
  706. /* All ethernet/IP/TCP headers combined size is TCP header size
  707. * plus offset of TCP header relative to start of packet.
  708. */
  709. st->header_len = ((tcp_hdr(skb)->doff << 2u)
  710. + PTR_DIFF(tcp_hdr(skb), skb->data));
  711. st->full_packet_size = st->header_len + skb_shinfo(skb)->gso_size;
  712. st->ipv4_id = ntohs(ip_hdr(skb)->id);
  713. st->seqnum = ntohl(tcp_hdr(skb)->seq);
  714. EFX_BUG_ON_PARANOID(tcp_hdr(skb)->urg);
  715. EFX_BUG_ON_PARANOID(tcp_hdr(skb)->syn);
  716. EFX_BUG_ON_PARANOID(tcp_hdr(skb)->rst);
  717. st->packet_space = st->full_packet_size;
  718. st->out_len = skb->len - st->header_len;
  719. st->unmap_len = 0;
  720. st->unmap_single = false;
  721. }
  722. static int tso_get_fragment(struct tso_state *st, struct efx_nic *efx,
  723. skb_frag_t *frag)
  724. {
  725. st->unmap_addr = pci_map_page(efx->pci_dev, frag->page,
  726. frag->page_offset, frag->size,
  727. PCI_DMA_TODEVICE);
  728. if (likely(!pci_dma_mapping_error(efx->pci_dev, st->unmap_addr))) {
  729. st->unmap_single = false;
  730. st->unmap_len = frag->size;
  731. st->in_len = frag->size;
  732. st->dma_addr = st->unmap_addr;
  733. return 0;
  734. }
  735. return -ENOMEM;
  736. }
  737. static int tso_get_head_fragment(struct tso_state *st, struct efx_nic *efx,
  738. const struct sk_buff *skb)
  739. {
  740. int hl = st->header_len;
  741. int len = skb_headlen(skb) - hl;
  742. st->unmap_addr = pci_map_single(efx->pci_dev, skb->data + hl,
  743. len, PCI_DMA_TODEVICE);
  744. if (likely(!pci_dma_mapping_error(efx->pci_dev, st->unmap_addr))) {
  745. st->unmap_single = true;
  746. st->unmap_len = len;
  747. st->in_len = len;
  748. st->dma_addr = st->unmap_addr;
  749. return 0;
  750. }
  751. return -ENOMEM;
  752. }
  753. /**
  754. * tso_fill_packet_with_fragment - form descriptors for the current fragment
  755. * @tx_queue: Efx TX queue
  756. * @skb: Socket buffer
  757. * @st: TSO state
  758. *
  759. * Form descriptors for the current fragment, until we reach the end
  760. * of fragment or end-of-packet. Return 0 on success, 1 if not enough
  761. * space in @tx_queue.
  762. */
  763. static int tso_fill_packet_with_fragment(struct efx_tx_queue *tx_queue,
  764. const struct sk_buff *skb,
  765. struct tso_state *st)
  766. {
  767. struct efx_tx_buffer *buffer;
  768. int n, end_of_packet, rc;
  769. if (st->in_len == 0)
  770. return 0;
  771. if (st->packet_space == 0)
  772. return 0;
  773. EFX_BUG_ON_PARANOID(st->in_len <= 0);
  774. EFX_BUG_ON_PARANOID(st->packet_space <= 0);
  775. n = min(st->in_len, st->packet_space);
  776. st->packet_space -= n;
  777. st->out_len -= n;
  778. st->in_len -= n;
  779. rc = efx_tx_queue_insert(tx_queue, st->dma_addr, n, &buffer);
  780. if (likely(rc == 0)) {
  781. if (st->out_len == 0)
  782. /* Transfer ownership of the skb */
  783. buffer->skb = skb;
  784. end_of_packet = st->out_len == 0 || st->packet_space == 0;
  785. buffer->continuation = !end_of_packet;
  786. if (st->in_len == 0) {
  787. /* Transfer ownership of the pci mapping */
  788. buffer->unmap_len = st->unmap_len;
  789. buffer->unmap_single = st->unmap_single;
  790. st->unmap_len = 0;
  791. }
  792. }
  793. st->dma_addr += n;
  794. return rc;
  795. }
  796. /**
  797. * tso_start_new_packet - generate a new header and prepare for the new packet
  798. * @tx_queue: Efx TX queue
  799. * @skb: Socket buffer
  800. * @st: TSO state
  801. *
  802. * Generate a new header and prepare for the new packet. Return 0 on
  803. * success, or -1 if failed to alloc header.
  804. */
  805. static int tso_start_new_packet(struct efx_tx_queue *tx_queue,
  806. const struct sk_buff *skb,
  807. struct tso_state *st)
  808. {
  809. struct efx_tso_header *tsoh;
  810. struct iphdr *tsoh_iph;
  811. struct tcphdr *tsoh_th;
  812. unsigned ip_length;
  813. u8 *header;
  814. /* Allocate a DMA-mapped header buffer. */
  815. if (likely(TSOH_SIZE(st->header_len) <= TSOH_STD_SIZE)) {
  816. if (tx_queue->tso_headers_free == NULL) {
  817. if (efx_tsoh_block_alloc(tx_queue))
  818. return -1;
  819. }
  820. EFX_BUG_ON_PARANOID(!tx_queue->tso_headers_free);
  821. tsoh = tx_queue->tso_headers_free;
  822. tx_queue->tso_headers_free = tsoh->next;
  823. tsoh->unmap_len = 0;
  824. } else {
  825. tx_queue->tso_long_headers++;
  826. tsoh = efx_tsoh_heap_alloc(tx_queue, st->header_len);
  827. if (unlikely(!tsoh))
  828. return -1;
  829. }
  830. header = TSOH_BUFFER(tsoh);
  831. tsoh_th = (struct tcphdr *)(header + SKB_TCP_OFF(skb));
  832. tsoh_iph = (struct iphdr *)(header + SKB_IPV4_OFF(skb));
  833. /* Copy and update the headers. */
  834. memcpy(header, skb->data, st->header_len);
  835. tsoh_th->seq = htonl(st->seqnum);
  836. st->seqnum += skb_shinfo(skb)->gso_size;
  837. if (st->out_len > skb_shinfo(skb)->gso_size) {
  838. /* This packet will not finish the TSO burst. */
  839. ip_length = st->full_packet_size - ETH_HDR_LEN(skb);
  840. tsoh_th->fin = 0;
  841. tsoh_th->psh = 0;
  842. } else {
  843. /* This packet will be the last in the TSO burst. */
  844. ip_length = st->header_len - ETH_HDR_LEN(skb) + st->out_len;
  845. tsoh_th->fin = tcp_hdr(skb)->fin;
  846. tsoh_th->psh = tcp_hdr(skb)->psh;
  847. }
  848. tsoh_iph->tot_len = htons(ip_length);
  849. /* Linux leaves suitable gaps in the IP ID space for us to fill. */
  850. tsoh_iph->id = htons(st->ipv4_id);
  851. st->ipv4_id++;
  852. st->packet_space = skb_shinfo(skb)->gso_size;
  853. ++tx_queue->tso_packets;
  854. /* Form a descriptor for this header. */
  855. efx_tso_put_header(tx_queue, tsoh, st->header_len);
  856. return 0;
  857. }
  858. /**
  859. * efx_enqueue_skb_tso - segment and transmit a TSO socket buffer
  860. * @tx_queue: Efx TX queue
  861. * @skb: Socket buffer
  862. *
  863. * Context: You must hold netif_tx_lock() to call this function.
  864. *
  865. * Add socket buffer @skb to @tx_queue, doing TSO or return != 0 if
  866. * @skb was not enqueued. In all cases @skb is consumed. Return
  867. * %NETDEV_TX_OK or %NETDEV_TX_BUSY.
  868. */
  869. static int efx_enqueue_skb_tso(struct efx_tx_queue *tx_queue,
  870. struct sk_buff *skb)
  871. {
  872. struct efx_nic *efx = tx_queue->efx;
  873. int frag_i, rc, rc2 = NETDEV_TX_OK;
  874. struct tso_state state;
  875. /* Verify TSO is safe - these checks should never fail. */
  876. efx_tso_check_safe(skb);
  877. EFX_BUG_ON_PARANOID(tx_queue->write_count != tx_queue->insert_count);
  878. tso_start(&state, skb);
  879. /* Assume that skb header area contains exactly the headers, and
  880. * all payload is in the frag list.
  881. */
  882. if (skb_headlen(skb) == state.header_len) {
  883. /* Grab the first payload fragment. */
  884. EFX_BUG_ON_PARANOID(skb_shinfo(skb)->nr_frags < 1);
  885. frag_i = 0;
  886. rc = tso_get_fragment(&state, efx,
  887. skb_shinfo(skb)->frags + frag_i);
  888. if (rc)
  889. goto mem_err;
  890. } else {
  891. rc = tso_get_head_fragment(&state, efx, skb);
  892. if (rc)
  893. goto mem_err;
  894. frag_i = -1;
  895. }
  896. if (tso_start_new_packet(tx_queue, skb, &state) < 0)
  897. goto mem_err;
  898. while (1) {
  899. rc = tso_fill_packet_with_fragment(tx_queue, skb, &state);
  900. if (unlikely(rc))
  901. goto stop;
  902. /* Move onto the next fragment? */
  903. if (state.in_len == 0) {
  904. if (++frag_i >= skb_shinfo(skb)->nr_frags)
  905. /* End of payload reached. */
  906. break;
  907. rc = tso_get_fragment(&state, efx,
  908. skb_shinfo(skb)->frags + frag_i);
  909. if (rc)
  910. goto mem_err;
  911. }
  912. /* Start at new packet? */
  913. if (state.packet_space == 0 &&
  914. tso_start_new_packet(tx_queue, skb, &state) < 0)
  915. goto mem_err;
  916. }
  917. /* Pass off to hardware */
  918. efx_nic_push_buffers(tx_queue);
  919. tx_queue->tso_bursts++;
  920. return NETDEV_TX_OK;
  921. mem_err:
  922. EFX_ERR(efx, "Out of memory for TSO headers, or PCI mapping error\n");
  923. dev_kfree_skb_any(skb);
  924. goto unwind;
  925. stop:
  926. rc2 = NETDEV_TX_BUSY;
  927. /* Stop the queue if it wasn't stopped before. */
  928. if (tx_queue->stopped == 1)
  929. efx_stop_queue(efx);
  930. unwind:
  931. /* Free the DMA mapping we were in the process of writing out */
  932. if (state.unmap_len) {
  933. if (state.unmap_single)
  934. pci_unmap_single(efx->pci_dev, state.unmap_addr,
  935. state.unmap_len, PCI_DMA_TODEVICE);
  936. else
  937. pci_unmap_page(efx->pci_dev, state.unmap_addr,
  938. state.unmap_len, PCI_DMA_TODEVICE);
  939. }
  940. efx_enqueue_unwind(tx_queue);
  941. return rc2;
  942. }
  943. /*
  944. * Free up all TSO datastructures associated with tx_queue. This
  945. * routine should be called only once the tx_queue is both empty and
  946. * will no longer be used.
  947. */
  948. static void efx_fini_tso(struct efx_tx_queue *tx_queue)
  949. {
  950. unsigned i;
  951. if (tx_queue->buffer) {
  952. for (i = 0; i <= EFX_TXQ_MASK; ++i)
  953. efx_tsoh_free(tx_queue, &tx_queue->buffer[i]);
  954. }
  955. while (tx_queue->tso_headers_free != NULL)
  956. efx_tsoh_block_free(tx_queue, tx_queue->tso_headers_free,
  957. tx_queue->efx->pci_dev);
  958. }