iwl-agn.c 97 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/kernel.h>
  30. #include <linux/module.h>
  31. #include <linux/init.h>
  32. #include <linux/pci.h>
  33. #include <linux/dma-mapping.h>
  34. #include <linux/delay.h>
  35. #include <linux/skbuff.h>
  36. #include <linux/netdevice.h>
  37. #include <linux/wireless.h>
  38. #include <linux/firmware.h>
  39. #include <linux/etherdevice.h>
  40. #include <linux/if_arp.h>
  41. #include <net/mac80211.h>
  42. #include <asm/div64.h>
  43. #define DRV_NAME "iwlagn"
  44. #include "iwl-eeprom.h"
  45. #include "iwl-dev.h"
  46. #include "iwl-core.h"
  47. #include "iwl-io.h"
  48. #include "iwl-helpers.h"
  49. #include "iwl-sta.h"
  50. #include "iwl-calib.h"
  51. /******************************************************************************
  52. *
  53. * module boiler plate
  54. *
  55. ******************************************************************************/
  56. /*
  57. * module name, copyright, version, etc.
  58. */
  59. #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
  60. #ifdef CONFIG_IWLWIFI_DEBUG
  61. #define VD "d"
  62. #else
  63. #define VD
  64. #endif
  65. #ifdef CONFIG_IWLWIFI_SPECTRUM_MEASUREMENT
  66. #define VS "s"
  67. #else
  68. #define VS
  69. #endif
  70. #define DRV_VERSION IWLWIFI_VERSION VD VS
  71. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  72. MODULE_VERSION(DRV_VERSION);
  73. MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  74. MODULE_LICENSE("GPL");
  75. MODULE_ALIAS("iwl4965");
  76. /*************** STATION TABLE MANAGEMENT ****
  77. * mac80211 should be examined to determine if sta_info is duplicating
  78. * the functionality provided here
  79. */
  80. /**************************************************************/
  81. /**
  82. * iwl_commit_rxon - commit staging_rxon to hardware
  83. *
  84. * The RXON command in staging_rxon is committed to the hardware and
  85. * the active_rxon structure is updated with the new data. This
  86. * function correctly transitions out of the RXON_ASSOC_MSK state if
  87. * a HW tune is required based on the RXON structure changes.
  88. */
  89. int iwl_commit_rxon(struct iwl_priv *priv)
  90. {
  91. /* cast away the const for active_rxon in this function */
  92. struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
  93. int ret;
  94. bool new_assoc =
  95. !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
  96. if (!iwl_is_alive(priv))
  97. return -EBUSY;
  98. /* always get timestamp with Rx frame */
  99. priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
  100. ret = iwl_check_rxon_cmd(priv);
  101. if (ret) {
  102. IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
  103. return -EINVAL;
  104. }
  105. /*
  106. * receive commit_rxon request
  107. * abort any previous channel switch if still in process
  108. */
  109. if (priv->switch_rxon.switch_in_progress &&
  110. (priv->switch_rxon.channel != priv->staging_rxon.channel)) {
  111. IWL_DEBUG_11H(priv, "abort channel switch on %d\n",
  112. le16_to_cpu(priv->switch_rxon.channel));
  113. priv->switch_rxon.switch_in_progress = false;
  114. }
  115. /* If we don't need to send a full RXON, we can use
  116. * iwl_rxon_assoc_cmd which is used to reconfigure filter
  117. * and other flags for the current radio configuration. */
  118. if (!iwl_full_rxon_required(priv)) {
  119. ret = iwl_send_rxon_assoc(priv);
  120. if (ret) {
  121. IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
  122. return ret;
  123. }
  124. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  125. iwl_print_rx_config_cmd(priv);
  126. return 0;
  127. }
  128. /* station table will be cleared */
  129. priv->assoc_station_added = 0;
  130. /* If we are currently associated and the new config requires
  131. * an RXON_ASSOC and the new config wants the associated mask enabled,
  132. * we must clear the associated from the active configuration
  133. * before we apply the new config */
  134. if (iwl_is_associated(priv) && new_assoc) {
  135. IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
  136. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  137. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  138. sizeof(struct iwl_rxon_cmd),
  139. &priv->active_rxon);
  140. /* If the mask clearing failed then we set
  141. * active_rxon back to what it was previously */
  142. if (ret) {
  143. active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
  144. IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
  145. return ret;
  146. }
  147. }
  148. IWL_DEBUG_INFO(priv, "Sending RXON\n"
  149. "* with%s RXON_FILTER_ASSOC_MSK\n"
  150. "* channel = %d\n"
  151. "* bssid = %pM\n",
  152. (new_assoc ? "" : "out"),
  153. le16_to_cpu(priv->staging_rxon.channel),
  154. priv->staging_rxon.bssid_addr);
  155. iwl_set_rxon_hwcrypto(priv, !priv->cfg->mod_params->sw_crypto);
  156. /* Apply the new configuration
  157. * RXON unassoc clears the station table in uCode, send it before
  158. * we add the bcast station. If assoc bit is set, we will send RXON
  159. * after having added the bcast and bssid station.
  160. */
  161. if (!new_assoc) {
  162. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  163. sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
  164. if (ret) {
  165. IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
  166. return ret;
  167. }
  168. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  169. }
  170. iwl_clear_stations_table(priv);
  171. priv->start_calib = 0;
  172. /* Add the broadcast address so we can send broadcast frames */
  173. iwl_add_bcast_station(priv);
  174. /* If we have set the ASSOC_MSK and we are in BSS mode then
  175. * add the IWL_AP_ID to the station rate table */
  176. if (new_assoc) {
  177. if (priv->iw_mode == NL80211_IFTYPE_STATION) {
  178. ret = iwl_rxon_add_station(priv,
  179. priv->active_rxon.bssid_addr, 1);
  180. if (ret == IWL_INVALID_STATION) {
  181. IWL_ERR(priv,
  182. "Error adding AP address for TX.\n");
  183. return -EIO;
  184. }
  185. priv->assoc_station_added = 1;
  186. if (priv->default_wep_key &&
  187. iwl_send_static_wepkey_cmd(priv, 0))
  188. IWL_ERR(priv,
  189. "Could not send WEP static key.\n");
  190. }
  191. /*
  192. * allow CTS-to-self if possible for new association.
  193. * this is relevant only for 5000 series and up,
  194. * but will not damage 4965
  195. */
  196. priv->staging_rxon.flags |= RXON_FLG_SELF_CTS_EN;
  197. /* Apply the new configuration
  198. * RXON assoc doesn't clear the station table in uCode,
  199. */
  200. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  201. sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
  202. if (ret) {
  203. IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
  204. return ret;
  205. }
  206. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  207. }
  208. iwl_print_rx_config_cmd(priv);
  209. iwl_init_sensitivity(priv);
  210. /* If we issue a new RXON command which required a tune then we must
  211. * send a new TXPOWER command or we won't be able to Tx any frames */
  212. ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
  213. if (ret) {
  214. IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
  215. return ret;
  216. }
  217. return 0;
  218. }
  219. void iwl_update_chain_flags(struct iwl_priv *priv)
  220. {
  221. if (priv->cfg->ops->hcmd->set_rxon_chain)
  222. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  223. iwlcore_commit_rxon(priv);
  224. }
  225. static void iwl_clear_free_frames(struct iwl_priv *priv)
  226. {
  227. struct list_head *element;
  228. IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
  229. priv->frames_count);
  230. while (!list_empty(&priv->free_frames)) {
  231. element = priv->free_frames.next;
  232. list_del(element);
  233. kfree(list_entry(element, struct iwl_frame, list));
  234. priv->frames_count--;
  235. }
  236. if (priv->frames_count) {
  237. IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
  238. priv->frames_count);
  239. priv->frames_count = 0;
  240. }
  241. }
  242. static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
  243. {
  244. struct iwl_frame *frame;
  245. struct list_head *element;
  246. if (list_empty(&priv->free_frames)) {
  247. frame = kzalloc(sizeof(*frame), GFP_KERNEL);
  248. if (!frame) {
  249. IWL_ERR(priv, "Could not allocate frame!\n");
  250. return NULL;
  251. }
  252. priv->frames_count++;
  253. return frame;
  254. }
  255. element = priv->free_frames.next;
  256. list_del(element);
  257. return list_entry(element, struct iwl_frame, list);
  258. }
  259. static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
  260. {
  261. memset(frame, 0, sizeof(*frame));
  262. list_add(&frame->list, &priv->free_frames);
  263. }
  264. static unsigned int iwl_fill_beacon_frame(struct iwl_priv *priv,
  265. struct ieee80211_hdr *hdr,
  266. int left)
  267. {
  268. if (!iwl_is_associated(priv) || !priv->ibss_beacon ||
  269. ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
  270. (priv->iw_mode != NL80211_IFTYPE_AP)))
  271. return 0;
  272. if (priv->ibss_beacon->len > left)
  273. return 0;
  274. memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
  275. return priv->ibss_beacon->len;
  276. }
  277. static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
  278. struct iwl_frame *frame, u8 rate)
  279. {
  280. struct iwl_tx_beacon_cmd *tx_beacon_cmd;
  281. unsigned int frame_size;
  282. tx_beacon_cmd = &frame->u.beacon;
  283. memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
  284. tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
  285. tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  286. frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
  287. sizeof(frame->u) - sizeof(*tx_beacon_cmd));
  288. BUG_ON(frame_size > MAX_MPDU_SIZE);
  289. tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
  290. if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP))
  291. tx_beacon_cmd->tx.rate_n_flags =
  292. iwl_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK);
  293. else
  294. tx_beacon_cmd->tx.rate_n_flags =
  295. iwl_hw_set_rate_n_flags(rate, 0);
  296. tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
  297. TX_CMD_FLG_TSF_MSK |
  298. TX_CMD_FLG_STA_RATE_MSK;
  299. return sizeof(*tx_beacon_cmd) + frame_size;
  300. }
  301. static int iwl_send_beacon_cmd(struct iwl_priv *priv)
  302. {
  303. struct iwl_frame *frame;
  304. unsigned int frame_size;
  305. int rc;
  306. u8 rate;
  307. frame = iwl_get_free_frame(priv);
  308. if (!frame) {
  309. IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
  310. "command.\n");
  311. return -ENOMEM;
  312. }
  313. rate = iwl_rate_get_lowest_plcp(priv);
  314. frame_size = iwl_hw_get_beacon_cmd(priv, frame, rate);
  315. rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
  316. &frame->u.cmd[0]);
  317. iwl_free_frame(priv, frame);
  318. return rc;
  319. }
  320. static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
  321. {
  322. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  323. dma_addr_t addr = get_unaligned_le32(&tb->lo);
  324. if (sizeof(dma_addr_t) > sizeof(u32))
  325. addr |=
  326. ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
  327. return addr;
  328. }
  329. static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
  330. {
  331. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  332. return le16_to_cpu(tb->hi_n_len) >> 4;
  333. }
  334. static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
  335. dma_addr_t addr, u16 len)
  336. {
  337. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  338. u16 hi_n_len = len << 4;
  339. put_unaligned_le32(addr, &tb->lo);
  340. if (sizeof(dma_addr_t) > sizeof(u32))
  341. hi_n_len |= ((addr >> 16) >> 16) & 0xF;
  342. tb->hi_n_len = cpu_to_le16(hi_n_len);
  343. tfd->num_tbs = idx + 1;
  344. }
  345. static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
  346. {
  347. return tfd->num_tbs & 0x1f;
  348. }
  349. /**
  350. * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
  351. * @priv - driver private data
  352. * @txq - tx queue
  353. *
  354. * Does NOT advance any TFD circular buffer read/write indexes
  355. * Does NOT free the TFD itself (which is within circular buffer)
  356. */
  357. void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
  358. {
  359. struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
  360. struct iwl_tfd *tfd;
  361. struct pci_dev *dev = priv->pci_dev;
  362. int index = txq->q.read_ptr;
  363. int i;
  364. int num_tbs;
  365. tfd = &tfd_tmp[index];
  366. /* Sanity check on number of chunks */
  367. num_tbs = iwl_tfd_get_num_tbs(tfd);
  368. if (num_tbs >= IWL_NUM_OF_TBS) {
  369. IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
  370. /* @todo issue fatal error, it is quite serious situation */
  371. return;
  372. }
  373. /* Unmap tx_cmd */
  374. if (num_tbs)
  375. pci_unmap_single(dev,
  376. pci_unmap_addr(&txq->meta[index], mapping),
  377. pci_unmap_len(&txq->meta[index], len),
  378. PCI_DMA_BIDIRECTIONAL);
  379. /* Unmap chunks, if any. */
  380. for (i = 1; i < num_tbs; i++) {
  381. pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
  382. iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
  383. if (txq->txb) {
  384. dev_kfree_skb(txq->txb[txq->q.read_ptr].skb[i - 1]);
  385. txq->txb[txq->q.read_ptr].skb[i - 1] = NULL;
  386. }
  387. }
  388. }
  389. int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
  390. struct iwl_tx_queue *txq,
  391. dma_addr_t addr, u16 len,
  392. u8 reset, u8 pad)
  393. {
  394. struct iwl_queue *q;
  395. struct iwl_tfd *tfd, *tfd_tmp;
  396. u32 num_tbs;
  397. q = &txq->q;
  398. tfd_tmp = (struct iwl_tfd *)txq->tfds;
  399. tfd = &tfd_tmp[q->write_ptr];
  400. if (reset)
  401. memset(tfd, 0, sizeof(*tfd));
  402. num_tbs = iwl_tfd_get_num_tbs(tfd);
  403. /* Each TFD can point to a maximum 20 Tx buffers */
  404. if (num_tbs >= IWL_NUM_OF_TBS) {
  405. IWL_ERR(priv, "Error can not send more than %d chunks\n",
  406. IWL_NUM_OF_TBS);
  407. return -EINVAL;
  408. }
  409. BUG_ON(addr & ~DMA_BIT_MASK(36));
  410. if (unlikely(addr & ~IWL_TX_DMA_MASK))
  411. IWL_ERR(priv, "Unaligned address = %llx\n",
  412. (unsigned long long)addr);
  413. iwl_tfd_set_tb(tfd, num_tbs, addr, len);
  414. return 0;
  415. }
  416. /*
  417. * Tell nic where to find circular buffer of Tx Frame Descriptors for
  418. * given Tx queue, and enable the DMA channel used for that queue.
  419. *
  420. * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
  421. * channels supported in hardware.
  422. */
  423. int iwl_hw_tx_queue_init(struct iwl_priv *priv,
  424. struct iwl_tx_queue *txq)
  425. {
  426. int txq_id = txq->q.id;
  427. /* Circular buffer (TFD queue in DRAM) physical base address */
  428. iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
  429. txq->q.dma_addr >> 8);
  430. return 0;
  431. }
  432. /******************************************************************************
  433. *
  434. * Generic RX handler implementations
  435. *
  436. ******************************************************************************/
  437. static void iwl_rx_reply_alive(struct iwl_priv *priv,
  438. struct iwl_rx_mem_buffer *rxb)
  439. {
  440. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  441. struct iwl_alive_resp *palive;
  442. struct delayed_work *pwork;
  443. palive = &pkt->u.alive_frame;
  444. IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
  445. "0x%01X 0x%01X\n",
  446. palive->is_valid, palive->ver_type,
  447. palive->ver_subtype);
  448. if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
  449. IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
  450. memcpy(&priv->card_alive_init,
  451. &pkt->u.alive_frame,
  452. sizeof(struct iwl_init_alive_resp));
  453. pwork = &priv->init_alive_start;
  454. } else {
  455. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  456. memcpy(&priv->card_alive, &pkt->u.alive_frame,
  457. sizeof(struct iwl_alive_resp));
  458. pwork = &priv->alive_start;
  459. }
  460. /* We delay the ALIVE response by 5ms to
  461. * give the HW RF Kill time to activate... */
  462. if (palive->is_valid == UCODE_VALID_OK)
  463. queue_delayed_work(priv->workqueue, pwork,
  464. msecs_to_jiffies(5));
  465. else
  466. IWL_WARN(priv, "uCode did not respond OK.\n");
  467. }
  468. static void iwl_bg_beacon_update(struct work_struct *work)
  469. {
  470. struct iwl_priv *priv =
  471. container_of(work, struct iwl_priv, beacon_update);
  472. struct sk_buff *beacon;
  473. /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
  474. beacon = ieee80211_beacon_get(priv->hw, priv->vif);
  475. if (!beacon) {
  476. IWL_ERR(priv, "update beacon failed\n");
  477. return;
  478. }
  479. mutex_lock(&priv->mutex);
  480. /* new beacon skb is allocated every time; dispose previous.*/
  481. if (priv->ibss_beacon)
  482. dev_kfree_skb(priv->ibss_beacon);
  483. priv->ibss_beacon = beacon;
  484. mutex_unlock(&priv->mutex);
  485. iwl_send_beacon_cmd(priv);
  486. }
  487. /**
  488. * iwl_bg_statistics_periodic - Timer callback to queue statistics
  489. *
  490. * This callback is provided in order to send a statistics request.
  491. *
  492. * This timer function is continually reset to execute within
  493. * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
  494. * was received. We need to ensure we receive the statistics in order
  495. * to update the temperature used for calibrating the TXPOWER.
  496. */
  497. static void iwl_bg_statistics_periodic(unsigned long data)
  498. {
  499. struct iwl_priv *priv = (struct iwl_priv *)data;
  500. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  501. return;
  502. /* dont send host command if rf-kill is on */
  503. if (!iwl_is_ready_rf(priv))
  504. return;
  505. iwl_send_statistics_request(priv, CMD_ASYNC);
  506. }
  507. static void iwl_rx_beacon_notif(struct iwl_priv *priv,
  508. struct iwl_rx_mem_buffer *rxb)
  509. {
  510. #ifdef CONFIG_IWLWIFI_DEBUG
  511. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  512. struct iwl4965_beacon_notif *beacon =
  513. (struct iwl4965_beacon_notif *)pkt->u.raw;
  514. u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
  515. IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
  516. "tsf %d %d rate %d\n",
  517. le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
  518. beacon->beacon_notify_hdr.failure_frame,
  519. le32_to_cpu(beacon->ibss_mgr_status),
  520. le32_to_cpu(beacon->high_tsf),
  521. le32_to_cpu(beacon->low_tsf), rate);
  522. #endif
  523. if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
  524. (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
  525. queue_work(priv->workqueue, &priv->beacon_update);
  526. }
  527. /* Handle notification from uCode that card's power state is changing
  528. * due to software, hardware, or critical temperature RFKILL */
  529. static void iwl_rx_card_state_notif(struct iwl_priv *priv,
  530. struct iwl_rx_mem_buffer *rxb)
  531. {
  532. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  533. u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
  534. unsigned long status = priv->status;
  535. IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s\n",
  536. (flags & HW_CARD_DISABLED) ? "Kill" : "On",
  537. (flags & SW_CARD_DISABLED) ? "Kill" : "On");
  538. if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
  539. RF_CARD_DISABLED)) {
  540. iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
  541. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  542. iwl_write_direct32(priv, HBUS_TARG_MBX_C,
  543. HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
  544. if (!(flags & RXON_CARD_DISABLED)) {
  545. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  546. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  547. iwl_write_direct32(priv, HBUS_TARG_MBX_C,
  548. HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
  549. }
  550. if (flags & RF_CARD_DISABLED)
  551. iwl_tt_enter_ct_kill(priv);
  552. }
  553. if (!(flags & RF_CARD_DISABLED))
  554. iwl_tt_exit_ct_kill(priv);
  555. if (flags & HW_CARD_DISABLED)
  556. set_bit(STATUS_RF_KILL_HW, &priv->status);
  557. else
  558. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  559. if (!(flags & RXON_CARD_DISABLED))
  560. iwl_scan_cancel(priv);
  561. if ((test_bit(STATUS_RF_KILL_HW, &status) !=
  562. test_bit(STATUS_RF_KILL_HW, &priv->status)))
  563. wiphy_rfkill_set_hw_state(priv->hw->wiphy,
  564. test_bit(STATUS_RF_KILL_HW, &priv->status));
  565. else
  566. wake_up_interruptible(&priv->wait_command_queue);
  567. }
  568. int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
  569. {
  570. if (src == IWL_PWR_SRC_VAUX) {
  571. if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
  572. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  573. APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
  574. ~APMG_PS_CTRL_MSK_PWR_SRC);
  575. } else {
  576. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  577. APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
  578. ~APMG_PS_CTRL_MSK_PWR_SRC);
  579. }
  580. return 0;
  581. }
  582. /**
  583. * iwl_setup_rx_handlers - Initialize Rx handler callbacks
  584. *
  585. * Setup the RX handlers for each of the reply types sent from the uCode
  586. * to the host.
  587. *
  588. * This function chains into the hardware specific files for them to setup
  589. * any hardware specific handlers as well.
  590. */
  591. static void iwl_setup_rx_handlers(struct iwl_priv *priv)
  592. {
  593. priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
  594. priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
  595. priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
  596. priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
  597. priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
  598. iwl_rx_pm_debug_statistics_notif;
  599. priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
  600. /*
  601. * The same handler is used for both the REPLY to a discrete
  602. * statistics request from the host as well as for the periodic
  603. * statistics notifications (after received beacons) from the uCode.
  604. */
  605. priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_rx_statistics;
  606. priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
  607. iwl_setup_spectrum_handlers(priv);
  608. iwl_setup_rx_scan_handlers(priv);
  609. /* status change handler */
  610. priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
  611. priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
  612. iwl_rx_missed_beacon_notif;
  613. /* Rx handlers */
  614. priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl_rx_reply_rx_phy;
  615. priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl_rx_reply_rx;
  616. /* block ack */
  617. priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl_rx_reply_compressed_ba;
  618. /* Set up hardware specific Rx handlers */
  619. priv->cfg->ops->lib->rx_handler_setup(priv);
  620. }
  621. /**
  622. * iwl_rx_handle - Main entry function for receiving responses from uCode
  623. *
  624. * Uses the priv->rx_handlers callback function array to invoke
  625. * the appropriate handlers, including command responses,
  626. * frame-received notifications, and other notifications.
  627. */
  628. void iwl_rx_handle(struct iwl_priv *priv)
  629. {
  630. struct iwl_rx_mem_buffer *rxb;
  631. struct iwl_rx_packet *pkt;
  632. struct iwl_rx_queue *rxq = &priv->rxq;
  633. u32 r, i;
  634. int reclaim;
  635. unsigned long flags;
  636. u8 fill_rx = 0;
  637. u32 count = 8;
  638. int total_empty;
  639. /* uCode's read index (stored in shared DRAM) indicates the last Rx
  640. * buffer that the driver may process (last buffer filled by ucode). */
  641. r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
  642. i = rxq->read;
  643. /* Rx interrupt, but nothing sent from uCode */
  644. if (i == r)
  645. IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
  646. /* calculate total frames need to be restock after handling RX */
  647. total_empty = r - rxq->write_actual;
  648. if (total_empty < 0)
  649. total_empty += RX_QUEUE_SIZE;
  650. if (total_empty > (RX_QUEUE_SIZE / 2))
  651. fill_rx = 1;
  652. while (i != r) {
  653. rxb = rxq->queue[i];
  654. /* If an RXB doesn't have a Rx queue slot associated with it,
  655. * then a bug has been introduced in the queue refilling
  656. * routines -- catch it here */
  657. BUG_ON(rxb == NULL);
  658. rxq->queue[i] = NULL;
  659. pci_unmap_page(priv->pci_dev, rxb->page_dma,
  660. PAGE_SIZE << priv->hw_params.rx_page_order,
  661. PCI_DMA_FROMDEVICE);
  662. pkt = rxb_addr(rxb);
  663. trace_iwlwifi_dev_rx(priv, pkt,
  664. le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
  665. /* Reclaim a command buffer only if this packet is a response
  666. * to a (driver-originated) command.
  667. * If the packet (e.g. Rx frame) originated from uCode,
  668. * there is no command buffer to reclaim.
  669. * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
  670. * but apparently a few don't get set; catch them here. */
  671. reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
  672. (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
  673. (pkt->hdr.cmd != REPLY_RX) &&
  674. (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
  675. (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
  676. (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
  677. (pkt->hdr.cmd != REPLY_TX);
  678. /* Based on type of command response or notification,
  679. * handle those that need handling via function in
  680. * rx_handlers table. See iwl_setup_rx_handlers() */
  681. if (priv->rx_handlers[pkt->hdr.cmd]) {
  682. IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
  683. i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
  684. priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
  685. priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
  686. } else {
  687. /* No handling needed */
  688. IWL_DEBUG_RX(priv,
  689. "r %d i %d No handler needed for %s, 0x%02x\n",
  690. r, i, get_cmd_string(pkt->hdr.cmd),
  691. pkt->hdr.cmd);
  692. }
  693. /*
  694. * XXX: After here, we should always check rxb->page
  695. * against NULL before touching it or its virtual
  696. * memory (pkt). Because some rx_handler might have
  697. * already taken or freed the pages.
  698. */
  699. if (reclaim) {
  700. /* Invoke any callbacks, transfer the buffer to caller,
  701. * and fire off the (possibly) blocking iwl_send_cmd()
  702. * as we reclaim the driver command queue */
  703. if (rxb->page)
  704. iwl_tx_cmd_complete(priv, rxb);
  705. else
  706. IWL_WARN(priv, "Claim null rxb?\n");
  707. }
  708. /* Reuse the page if possible. For notification packets and
  709. * SKBs that fail to Rx correctly, add them back into the
  710. * rx_free list for reuse later. */
  711. spin_lock_irqsave(&rxq->lock, flags);
  712. if (rxb->page != NULL) {
  713. rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
  714. 0, PAGE_SIZE << priv->hw_params.rx_page_order,
  715. PCI_DMA_FROMDEVICE);
  716. list_add_tail(&rxb->list, &rxq->rx_free);
  717. rxq->free_count++;
  718. } else
  719. list_add_tail(&rxb->list, &rxq->rx_used);
  720. spin_unlock_irqrestore(&rxq->lock, flags);
  721. i = (i + 1) & RX_QUEUE_MASK;
  722. /* If there are a lot of unused frames,
  723. * restock the Rx queue so ucode wont assert. */
  724. if (fill_rx) {
  725. count++;
  726. if (count >= 8) {
  727. rxq->read = i;
  728. iwl_rx_replenish_now(priv);
  729. count = 0;
  730. }
  731. }
  732. }
  733. /* Backtrack one entry */
  734. rxq->read = i;
  735. if (fill_rx)
  736. iwl_rx_replenish_now(priv);
  737. else
  738. iwl_rx_queue_restock(priv);
  739. }
  740. /* call this function to flush any scheduled tasklet */
  741. static inline void iwl_synchronize_irq(struct iwl_priv *priv)
  742. {
  743. /* wait to make sure we flush pending tasklet*/
  744. synchronize_irq(priv->pci_dev->irq);
  745. tasklet_kill(&priv->irq_tasklet);
  746. }
  747. static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
  748. {
  749. u32 inta, handled = 0;
  750. u32 inta_fh;
  751. unsigned long flags;
  752. u32 i;
  753. #ifdef CONFIG_IWLWIFI_DEBUG
  754. u32 inta_mask;
  755. #endif
  756. spin_lock_irqsave(&priv->lock, flags);
  757. /* Ack/clear/reset pending uCode interrupts.
  758. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  759. * and will clear only when CSR_FH_INT_STATUS gets cleared. */
  760. inta = iwl_read32(priv, CSR_INT);
  761. iwl_write32(priv, CSR_INT, inta);
  762. /* Ack/clear/reset pending flow-handler (DMA) interrupts.
  763. * Any new interrupts that happen after this, either while we're
  764. * in this tasklet, or later, will show up in next ISR/tasklet. */
  765. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  766. iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
  767. #ifdef CONFIG_IWLWIFI_DEBUG
  768. if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
  769. /* just for debug */
  770. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  771. IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  772. inta, inta_mask, inta_fh);
  773. }
  774. #endif
  775. spin_unlock_irqrestore(&priv->lock, flags);
  776. /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
  777. * atomic, make sure that inta covers all the interrupts that
  778. * we've discovered, even if FH interrupt came in just after
  779. * reading CSR_INT. */
  780. if (inta_fh & CSR49_FH_INT_RX_MASK)
  781. inta |= CSR_INT_BIT_FH_RX;
  782. if (inta_fh & CSR49_FH_INT_TX_MASK)
  783. inta |= CSR_INT_BIT_FH_TX;
  784. /* Now service all interrupt bits discovered above. */
  785. if (inta & CSR_INT_BIT_HW_ERR) {
  786. IWL_ERR(priv, "Hardware error detected. Restarting.\n");
  787. /* Tell the device to stop sending interrupts */
  788. iwl_disable_interrupts(priv);
  789. priv->isr_stats.hw++;
  790. iwl_irq_handle_error(priv);
  791. handled |= CSR_INT_BIT_HW_ERR;
  792. return;
  793. }
  794. #ifdef CONFIG_IWLWIFI_DEBUG
  795. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  796. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  797. if (inta & CSR_INT_BIT_SCD) {
  798. IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
  799. "the frame/frames.\n");
  800. priv->isr_stats.sch++;
  801. }
  802. /* Alive notification via Rx interrupt will do the real work */
  803. if (inta & CSR_INT_BIT_ALIVE) {
  804. IWL_DEBUG_ISR(priv, "Alive interrupt\n");
  805. priv->isr_stats.alive++;
  806. }
  807. }
  808. #endif
  809. /* Safely ignore these bits for debug checks below */
  810. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  811. /* HW RF KILL switch toggled */
  812. if (inta & CSR_INT_BIT_RF_KILL) {
  813. int hw_rf_kill = 0;
  814. if (!(iwl_read32(priv, CSR_GP_CNTRL) &
  815. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  816. hw_rf_kill = 1;
  817. IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
  818. hw_rf_kill ? "disable radio" : "enable radio");
  819. priv->isr_stats.rfkill++;
  820. /* driver only loads ucode once setting the interface up.
  821. * the driver allows loading the ucode even if the radio
  822. * is killed. Hence update the killswitch state here. The
  823. * rfkill handler will care about restarting if needed.
  824. */
  825. if (!test_bit(STATUS_ALIVE, &priv->status)) {
  826. if (hw_rf_kill)
  827. set_bit(STATUS_RF_KILL_HW, &priv->status);
  828. else
  829. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  830. wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
  831. }
  832. handled |= CSR_INT_BIT_RF_KILL;
  833. }
  834. /* Chip got too hot and stopped itself */
  835. if (inta & CSR_INT_BIT_CT_KILL) {
  836. IWL_ERR(priv, "Microcode CT kill error detected.\n");
  837. priv->isr_stats.ctkill++;
  838. handled |= CSR_INT_BIT_CT_KILL;
  839. }
  840. /* Error detected by uCode */
  841. if (inta & CSR_INT_BIT_SW_ERR) {
  842. IWL_ERR(priv, "Microcode SW error detected. "
  843. " Restarting 0x%X.\n", inta);
  844. priv->isr_stats.sw++;
  845. priv->isr_stats.sw_err = inta;
  846. iwl_irq_handle_error(priv);
  847. handled |= CSR_INT_BIT_SW_ERR;
  848. }
  849. /*
  850. * uCode wakes up after power-down sleep.
  851. * Tell device about any new tx or host commands enqueued,
  852. * and about any Rx buffers made available while asleep.
  853. */
  854. if (inta & CSR_INT_BIT_WAKEUP) {
  855. IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
  856. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  857. for (i = 0; i < priv->hw_params.max_txq_num; i++)
  858. iwl_txq_update_write_ptr(priv, &priv->txq[i]);
  859. priv->isr_stats.wakeup++;
  860. handled |= CSR_INT_BIT_WAKEUP;
  861. }
  862. /* All uCode command responses, including Tx command responses,
  863. * Rx "responses" (frame-received notification), and other
  864. * notifications from uCode come through here*/
  865. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  866. iwl_rx_handle(priv);
  867. priv->isr_stats.rx++;
  868. iwl_leds_background(priv);
  869. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  870. }
  871. /* This "Tx" DMA channel is used only for loading uCode */
  872. if (inta & CSR_INT_BIT_FH_TX) {
  873. IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
  874. priv->isr_stats.tx++;
  875. handled |= CSR_INT_BIT_FH_TX;
  876. /* Wake up uCode load routine, now that load is complete */
  877. priv->ucode_write_complete = 1;
  878. wake_up_interruptible(&priv->wait_command_queue);
  879. }
  880. if (inta & ~handled) {
  881. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  882. priv->isr_stats.unhandled++;
  883. }
  884. if (inta & ~(priv->inta_mask)) {
  885. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  886. inta & ~priv->inta_mask);
  887. IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
  888. }
  889. /* Re-enable all interrupts */
  890. /* only Re-enable if diabled by irq */
  891. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  892. iwl_enable_interrupts(priv);
  893. #ifdef CONFIG_IWLWIFI_DEBUG
  894. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  895. inta = iwl_read32(priv, CSR_INT);
  896. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  897. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  898. IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
  899. "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
  900. }
  901. #endif
  902. }
  903. /* tasklet for iwlagn interrupt */
  904. static void iwl_irq_tasklet(struct iwl_priv *priv)
  905. {
  906. u32 inta = 0;
  907. u32 handled = 0;
  908. unsigned long flags;
  909. #ifdef CONFIG_IWLWIFI_DEBUG
  910. u32 inta_mask;
  911. #endif
  912. spin_lock_irqsave(&priv->lock, flags);
  913. /* Ack/clear/reset pending uCode interrupts.
  914. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  915. */
  916. iwl_write32(priv, CSR_INT, priv->inta);
  917. inta = priv->inta;
  918. #ifdef CONFIG_IWLWIFI_DEBUG
  919. if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
  920. /* just for debug */
  921. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  922. IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
  923. inta, inta_mask);
  924. }
  925. #endif
  926. spin_unlock_irqrestore(&priv->lock, flags);
  927. /* saved interrupt in inta variable now we can reset priv->inta */
  928. priv->inta = 0;
  929. /* Now service all interrupt bits discovered above. */
  930. if (inta & CSR_INT_BIT_HW_ERR) {
  931. IWL_ERR(priv, "Hardware error detected. Restarting.\n");
  932. /* Tell the device to stop sending interrupts */
  933. iwl_disable_interrupts(priv);
  934. priv->isr_stats.hw++;
  935. iwl_irq_handle_error(priv);
  936. handled |= CSR_INT_BIT_HW_ERR;
  937. return;
  938. }
  939. #ifdef CONFIG_IWLWIFI_DEBUG
  940. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  941. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  942. if (inta & CSR_INT_BIT_SCD) {
  943. IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
  944. "the frame/frames.\n");
  945. priv->isr_stats.sch++;
  946. }
  947. /* Alive notification via Rx interrupt will do the real work */
  948. if (inta & CSR_INT_BIT_ALIVE) {
  949. IWL_DEBUG_ISR(priv, "Alive interrupt\n");
  950. priv->isr_stats.alive++;
  951. }
  952. }
  953. #endif
  954. /* Safely ignore these bits for debug checks below */
  955. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  956. /* HW RF KILL switch toggled */
  957. if (inta & CSR_INT_BIT_RF_KILL) {
  958. int hw_rf_kill = 0;
  959. if (!(iwl_read32(priv, CSR_GP_CNTRL) &
  960. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  961. hw_rf_kill = 1;
  962. IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
  963. hw_rf_kill ? "disable radio" : "enable radio");
  964. priv->isr_stats.rfkill++;
  965. /* driver only loads ucode once setting the interface up.
  966. * the driver allows loading the ucode even if the radio
  967. * is killed. Hence update the killswitch state here. The
  968. * rfkill handler will care about restarting if needed.
  969. */
  970. if (!test_bit(STATUS_ALIVE, &priv->status)) {
  971. if (hw_rf_kill)
  972. set_bit(STATUS_RF_KILL_HW, &priv->status);
  973. else
  974. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  975. wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
  976. }
  977. handled |= CSR_INT_BIT_RF_KILL;
  978. }
  979. /* Chip got too hot and stopped itself */
  980. if (inta & CSR_INT_BIT_CT_KILL) {
  981. IWL_ERR(priv, "Microcode CT kill error detected.\n");
  982. priv->isr_stats.ctkill++;
  983. handled |= CSR_INT_BIT_CT_KILL;
  984. }
  985. /* Error detected by uCode */
  986. if (inta & CSR_INT_BIT_SW_ERR) {
  987. IWL_ERR(priv, "Microcode SW error detected. "
  988. " Restarting 0x%X.\n", inta);
  989. priv->isr_stats.sw++;
  990. priv->isr_stats.sw_err = inta;
  991. iwl_irq_handle_error(priv);
  992. handled |= CSR_INT_BIT_SW_ERR;
  993. }
  994. /* uCode wakes up after power-down sleep */
  995. if (inta & CSR_INT_BIT_WAKEUP) {
  996. IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
  997. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  998. iwl_txq_update_write_ptr(priv, &priv->txq[0]);
  999. iwl_txq_update_write_ptr(priv, &priv->txq[1]);
  1000. iwl_txq_update_write_ptr(priv, &priv->txq[2]);
  1001. iwl_txq_update_write_ptr(priv, &priv->txq[3]);
  1002. iwl_txq_update_write_ptr(priv, &priv->txq[4]);
  1003. iwl_txq_update_write_ptr(priv, &priv->txq[5]);
  1004. priv->isr_stats.wakeup++;
  1005. handled |= CSR_INT_BIT_WAKEUP;
  1006. }
  1007. /* All uCode command responses, including Tx command responses,
  1008. * Rx "responses" (frame-received notification), and other
  1009. * notifications from uCode come through here*/
  1010. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
  1011. CSR_INT_BIT_RX_PERIODIC)) {
  1012. IWL_DEBUG_ISR(priv, "Rx interrupt\n");
  1013. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  1014. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  1015. iwl_write32(priv, CSR_FH_INT_STATUS,
  1016. CSR49_FH_INT_RX_MASK);
  1017. }
  1018. if (inta & CSR_INT_BIT_RX_PERIODIC) {
  1019. handled |= CSR_INT_BIT_RX_PERIODIC;
  1020. iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
  1021. }
  1022. /* Sending RX interrupt require many steps to be done in the
  1023. * the device:
  1024. * 1- write interrupt to current index in ICT table.
  1025. * 2- dma RX frame.
  1026. * 3- update RX shared data to indicate last write index.
  1027. * 4- send interrupt.
  1028. * This could lead to RX race, driver could receive RX interrupt
  1029. * but the shared data changes does not reflect this.
  1030. * this could lead to RX race, RX periodic will solve this race
  1031. */
  1032. iwl_write32(priv, CSR_INT_PERIODIC_REG,
  1033. CSR_INT_PERIODIC_DIS);
  1034. iwl_rx_handle(priv);
  1035. /* Only set RX periodic if real RX is received. */
  1036. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
  1037. iwl_write32(priv, CSR_INT_PERIODIC_REG,
  1038. CSR_INT_PERIODIC_ENA);
  1039. priv->isr_stats.rx++;
  1040. iwl_leds_background(priv);
  1041. }
  1042. /* This "Tx" DMA channel is used only for loading uCode */
  1043. if (inta & CSR_INT_BIT_FH_TX) {
  1044. iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
  1045. IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
  1046. priv->isr_stats.tx++;
  1047. handled |= CSR_INT_BIT_FH_TX;
  1048. /* Wake up uCode load routine, now that load is complete */
  1049. priv->ucode_write_complete = 1;
  1050. wake_up_interruptible(&priv->wait_command_queue);
  1051. }
  1052. if (inta & ~handled) {
  1053. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  1054. priv->isr_stats.unhandled++;
  1055. }
  1056. if (inta & ~(priv->inta_mask)) {
  1057. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  1058. inta & ~priv->inta_mask);
  1059. }
  1060. /* Re-enable all interrupts */
  1061. /* only Re-enable if diabled by irq */
  1062. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  1063. iwl_enable_interrupts(priv);
  1064. }
  1065. /******************************************************************************
  1066. *
  1067. * uCode download functions
  1068. *
  1069. ******************************************************************************/
  1070. static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
  1071. {
  1072. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
  1073. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
  1074. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1075. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
  1076. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1077. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1078. }
  1079. static void iwl_nic_start(struct iwl_priv *priv)
  1080. {
  1081. /* Remove all resets to allow NIC to operate */
  1082. iwl_write32(priv, CSR_RESET, 0);
  1083. }
  1084. /**
  1085. * iwl_read_ucode - Read uCode images from disk file.
  1086. *
  1087. * Copy into buffers for card to fetch via bus-mastering
  1088. */
  1089. static int iwl_read_ucode(struct iwl_priv *priv)
  1090. {
  1091. struct iwl_ucode_header *ucode;
  1092. int ret = -EINVAL, index;
  1093. const struct firmware *ucode_raw;
  1094. const char *name_pre = priv->cfg->fw_name_pre;
  1095. const unsigned int api_max = priv->cfg->ucode_api_max;
  1096. const unsigned int api_min = priv->cfg->ucode_api_min;
  1097. char buf[25];
  1098. u8 *src;
  1099. size_t len;
  1100. u32 api_ver, build;
  1101. u32 inst_size, data_size, init_size, init_data_size, boot_size;
  1102. u16 eeprom_ver;
  1103. /* Ask kernel firmware_class module to get the boot firmware off disk.
  1104. * request_firmware() is synchronous, file is in memory on return. */
  1105. for (index = api_max; index >= api_min; index--) {
  1106. sprintf(buf, "%s%d%s", name_pre, index, ".ucode");
  1107. ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
  1108. if (ret < 0) {
  1109. IWL_ERR(priv, "%s firmware file req failed: %d\n",
  1110. buf, ret);
  1111. if (ret == -ENOENT)
  1112. continue;
  1113. else
  1114. goto error;
  1115. } else {
  1116. if (index < api_max)
  1117. IWL_ERR(priv, "Loaded firmware %s, "
  1118. "which is deprecated. "
  1119. "Please use API v%u instead.\n",
  1120. buf, api_max);
  1121. IWL_DEBUG_INFO(priv, "Got firmware '%s' file (%zd bytes) from disk\n",
  1122. buf, ucode_raw->size);
  1123. break;
  1124. }
  1125. }
  1126. if (ret < 0)
  1127. goto error;
  1128. /* Make sure that we got at least the v1 header! */
  1129. if (ucode_raw->size < priv->cfg->ops->ucode->get_header_size(1)) {
  1130. IWL_ERR(priv, "File size way too small!\n");
  1131. ret = -EINVAL;
  1132. goto err_release;
  1133. }
  1134. /* Data from ucode file: header followed by uCode images */
  1135. ucode = (struct iwl_ucode_header *)ucode_raw->data;
  1136. priv->ucode_ver = le32_to_cpu(ucode->ver);
  1137. api_ver = IWL_UCODE_API(priv->ucode_ver);
  1138. build = priv->cfg->ops->ucode->get_build(ucode, api_ver);
  1139. inst_size = priv->cfg->ops->ucode->get_inst_size(ucode, api_ver);
  1140. data_size = priv->cfg->ops->ucode->get_data_size(ucode, api_ver);
  1141. init_size = priv->cfg->ops->ucode->get_init_size(ucode, api_ver);
  1142. init_data_size =
  1143. priv->cfg->ops->ucode->get_init_data_size(ucode, api_ver);
  1144. boot_size = priv->cfg->ops->ucode->get_boot_size(ucode, api_ver);
  1145. src = priv->cfg->ops->ucode->get_data(ucode, api_ver);
  1146. /* api_ver should match the api version forming part of the
  1147. * firmware filename ... but we don't check for that and only rely
  1148. * on the API version read from firmware header from here on forward */
  1149. if (api_ver < api_min || api_ver > api_max) {
  1150. IWL_ERR(priv, "Driver unable to support your firmware API. "
  1151. "Driver supports v%u, firmware is v%u.\n",
  1152. api_max, api_ver);
  1153. priv->ucode_ver = 0;
  1154. ret = -EINVAL;
  1155. goto err_release;
  1156. }
  1157. if (api_ver != api_max)
  1158. IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
  1159. "got v%u. New firmware can be obtained "
  1160. "from http://www.intellinuxwireless.org.\n",
  1161. api_max, api_ver);
  1162. IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
  1163. IWL_UCODE_MAJOR(priv->ucode_ver),
  1164. IWL_UCODE_MINOR(priv->ucode_ver),
  1165. IWL_UCODE_API(priv->ucode_ver),
  1166. IWL_UCODE_SERIAL(priv->ucode_ver));
  1167. snprintf(priv->hw->wiphy->fw_version,
  1168. sizeof(priv->hw->wiphy->fw_version),
  1169. "%u.%u.%u.%u",
  1170. IWL_UCODE_MAJOR(priv->ucode_ver),
  1171. IWL_UCODE_MINOR(priv->ucode_ver),
  1172. IWL_UCODE_API(priv->ucode_ver),
  1173. IWL_UCODE_SERIAL(priv->ucode_ver));
  1174. if (build)
  1175. IWL_DEBUG_INFO(priv, "Build %u\n", build);
  1176. eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
  1177. IWL_DEBUG_INFO(priv, "NVM Type: %s, version: 0x%x\n",
  1178. (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP)
  1179. ? "OTP" : "EEPROM", eeprom_ver);
  1180. IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
  1181. priv->ucode_ver);
  1182. IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n",
  1183. inst_size);
  1184. IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n",
  1185. data_size);
  1186. IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n",
  1187. init_size);
  1188. IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n",
  1189. init_data_size);
  1190. IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n",
  1191. boot_size);
  1192. /* Verify size of file vs. image size info in file's header */
  1193. if (ucode_raw->size !=
  1194. priv->cfg->ops->ucode->get_header_size(api_ver) +
  1195. inst_size + data_size + init_size +
  1196. init_data_size + boot_size) {
  1197. IWL_DEBUG_INFO(priv,
  1198. "uCode file size %d does not match expected size\n",
  1199. (int)ucode_raw->size);
  1200. ret = -EINVAL;
  1201. goto err_release;
  1202. }
  1203. /* Verify that uCode images will fit in card's SRAM */
  1204. if (inst_size > priv->hw_params.max_inst_size) {
  1205. IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n",
  1206. inst_size);
  1207. ret = -EINVAL;
  1208. goto err_release;
  1209. }
  1210. if (data_size > priv->hw_params.max_data_size) {
  1211. IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n",
  1212. data_size);
  1213. ret = -EINVAL;
  1214. goto err_release;
  1215. }
  1216. if (init_size > priv->hw_params.max_inst_size) {
  1217. IWL_INFO(priv, "uCode init instr len %d too large to fit in\n",
  1218. init_size);
  1219. ret = -EINVAL;
  1220. goto err_release;
  1221. }
  1222. if (init_data_size > priv->hw_params.max_data_size) {
  1223. IWL_INFO(priv, "uCode init data len %d too large to fit in\n",
  1224. init_data_size);
  1225. ret = -EINVAL;
  1226. goto err_release;
  1227. }
  1228. if (boot_size > priv->hw_params.max_bsm_size) {
  1229. IWL_INFO(priv, "uCode boot instr len %d too large to fit in\n",
  1230. boot_size);
  1231. ret = -EINVAL;
  1232. goto err_release;
  1233. }
  1234. /* Allocate ucode buffers for card's bus-master loading ... */
  1235. /* Runtime instructions and 2 copies of data:
  1236. * 1) unmodified from disk
  1237. * 2) backup cache for save/restore during power-downs */
  1238. priv->ucode_code.len = inst_size;
  1239. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
  1240. priv->ucode_data.len = data_size;
  1241. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
  1242. priv->ucode_data_backup.len = data_size;
  1243. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1244. if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
  1245. !priv->ucode_data_backup.v_addr)
  1246. goto err_pci_alloc;
  1247. /* Initialization instructions and data */
  1248. if (init_size && init_data_size) {
  1249. priv->ucode_init.len = init_size;
  1250. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
  1251. priv->ucode_init_data.len = init_data_size;
  1252. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1253. if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
  1254. goto err_pci_alloc;
  1255. }
  1256. /* Bootstrap (instructions only, no data) */
  1257. if (boot_size) {
  1258. priv->ucode_boot.len = boot_size;
  1259. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1260. if (!priv->ucode_boot.v_addr)
  1261. goto err_pci_alloc;
  1262. }
  1263. /* Copy images into buffers for card's bus-master reads ... */
  1264. /* Runtime instructions (first block of data in file) */
  1265. len = inst_size;
  1266. IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n", len);
  1267. memcpy(priv->ucode_code.v_addr, src, len);
  1268. src += len;
  1269. IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
  1270. priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
  1271. /* Runtime data (2nd block)
  1272. * NOTE: Copy into backup buffer will be done in iwl_up() */
  1273. len = data_size;
  1274. IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n", len);
  1275. memcpy(priv->ucode_data.v_addr, src, len);
  1276. memcpy(priv->ucode_data_backup.v_addr, src, len);
  1277. src += len;
  1278. /* Initialization instructions (3rd block) */
  1279. if (init_size) {
  1280. len = init_size;
  1281. IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
  1282. len);
  1283. memcpy(priv->ucode_init.v_addr, src, len);
  1284. src += len;
  1285. }
  1286. /* Initialization data (4th block) */
  1287. if (init_data_size) {
  1288. len = init_data_size;
  1289. IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
  1290. len);
  1291. memcpy(priv->ucode_init_data.v_addr, src, len);
  1292. src += len;
  1293. }
  1294. /* Bootstrap instructions (5th block) */
  1295. len = boot_size;
  1296. IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n", len);
  1297. memcpy(priv->ucode_boot.v_addr, src, len);
  1298. /* We have our copies now, allow OS release its copies */
  1299. release_firmware(ucode_raw);
  1300. return 0;
  1301. err_pci_alloc:
  1302. IWL_ERR(priv, "failed to allocate pci memory\n");
  1303. ret = -ENOMEM;
  1304. iwl_dealloc_ucode_pci(priv);
  1305. err_release:
  1306. release_firmware(ucode_raw);
  1307. error:
  1308. return ret;
  1309. }
  1310. #ifdef CONFIG_IWLWIFI_DEBUG
  1311. static const char *desc_lookup_text[] = {
  1312. "OK",
  1313. "FAIL",
  1314. "BAD_PARAM",
  1315. "BAD_CHECKSUM",
  1316. "NMI_INTERRUPT_WDG",
  1317. "SYSASSERT",
  1318. "FATAL_ERROR",
  1319. "BAD_COMMAND",
  1320. "HW_ERROR_TUNE_LOCK",
  1321. "HW_ERROR_TEMPERATURE",
  1322. "ILLEGAL_CHAN_FREQ",
  1323. "VCC_NOT_STABLE",
  1324. "FH_ERROR",
  1325. "NMI_INTERRUPT_HOST",
  1326. "NMI_INTERRUPT_ACTION_PT",
  1327. "NMI_INTERRUPT_UNKNOWN",
  1328. "UCODE_VERSION_MISMATCH",
  1329. "HW_ERROR_ABS_LOCK",
  1330. "HW_ERROR_CAL_LOCK_FAIL",
  1331. "NMI_INTERRUPT_INST_ACTION_PT",
  1332. "NMI_INTERRUPT_DATA_ACTION_PT",
  1333. "NMI_TRM_HW_ER",
  1334. "NMI_INTERRUPT_TRM",
  1335. "NMI_INTERRUPT_BREAK_POINT"
  1336. "DEBUG_0",
  1337. "DEBUG_1",
  1338. "DEBUG_2",
  1339. "DEBUG_3",
  1340. "UNKNOWN"
  1341. };
  1342. static const char *desc_lookup(int i)
  1343. {
  1344. int max = ARRAY_SIZE(desc_lookup_text) - 1;
  1345. if (i < 0 || i > max)
  1346. i = max;
  1347. return desc_lookup_text[i];
  1348. }
  1349. #define ERROR_START_OFFSET (1 * sizeof(u32))
  1350. #define ERROR_ELEM_SIZE (7 * sizeof(u32))
  1351. void iwl_dump_nic_error_log(struct iwl_priv *priv)
  1352. {
  1353. u32 data2, line;
  1354. u32 desc, time, count, base, data1;
  1355. u32 blink1, blink2, ilink1, ilink2;
  1356. if (priv->ucode_type == UCODE_INIT)
  1357. base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
  1358. else
  1359. base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
  1360. if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  1361. IWL_ERR(priv, "Not valid error log pointer 0x%08X\n", base);
  1362. return;
  1363. }
  1364. count = iwl_read_targ_mem(priv, base);
  1365. if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
  1366. IWL_ERR(priv, "Start IWL Error Log Dump:\n");
  1367. IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
  1368. priv->status, count);
  1369. }
  1370. desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
  1371. blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
  1372. blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
  1373. ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
  1374. ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
  1375. data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
  1376. data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
  1377. line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
  1378. time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
  1379. trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
  1380. blink1, blink2, ilink1, ilink2);
  1381. IWL_ERR(priv, "Desc Time "
  1382. "data1 data2 line\n");
  1383. IWL_ERR(priv, "%-28s (#%02d) %010u 0x%08X 0x%08X %u\n",
  1384. desc_lookup(desc), desc, time, data1, data2, line);
  1385. IWL_ERR(priv, "blink1 blink2 ilink1 ilink2\n");
  1386. IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
  1387. ilink1, ilink2);
  1388. }
  1389. #define EVENT_START_OFFSET (4 * sizeof(u32))
  1390. /**
  1391. * iwl_print_event_log - Dump error event log to syslog
  1392. *
  1393. */
  1394. static void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
  1395. u32 num_events, u32 mode)
  1396. {
  1397. u32 i;
  1398. u32 base; /* SRAM byte address of event log header */
  1399. u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
  1400. u32 ptr; /* SRAM byte address of log data */
  1401. u32 ev, time, data; /* event log data */
  1402. if (num_events == 0)
  1403. return;
  1404. if (priv->ucode_type == UCODE_INIT)
  1405. base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
  1406. else
  1407. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  1408. if (mode == 0)
  1409. event_size = 2 * sizeof(u32);
  1410. else
  1411. event_size = 3 * sizeof(u32);
  1412. ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
  1413. /* "time" is actually "data" for mode 0 (no timestamp).
  1414. * place event id # at far right for easier visual parsing. */
  1415. for (i = 0; i < num_events; i++) {
  1416. ev = iwl_read_targ_mem(priv, ptr);
  1417. ptr += sizeof(u32);
  1418. time = iwl_read_targ_mem(priv, ptr);
  1419. ptr += sizeof(u32);
  1420. if (mode == 0) {
  1421. /* data, ev */
  1422. trace_iwlwifi_dev_ucode_event(priv, 0, time, ev);
  1423. IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n", time, ev);
  1424. } else {
  1425. data = iwl_read_targ_mem(priv, ptr);
  1426. ptr += sizeof(u32);
  1427. IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
  1428. time, data, ev);
  1429. trace_iwlwifi_dev_ucode_event(priv, time, data, ev);
  1430. }
  1431. }
  1432. }
  1433. void iwl_dump_nic_event_log(struct iwl_priv *priv)
  1434. {
  1435. u32 base; /* SRAM byte address of event log header */
  1436. u32 capacity; /* event log capacity in # entries */
  1437. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  1438. u32 num_wraps; /* # times uCode wrapped to top of log */
  1439. u32 next_entry; /* index of next entry to be written by uCode */
  1440. u32 size; /* # entries that we'll print */
  1441. if (priv->ucode_type == UCODE_INIT)
  1442. base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
  1443. else
  1444. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  1445. if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  1446. IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base);
  1447. return;
  1448. }
  1449. /* event log header */
  1450. capacity = iwl_read_targ_mem(priv, base);
  1451. mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
  1452. num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
  1453. next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
  1454. size = num_wraps ? capacity : next_entry;
  1455. /* bail out if nothing in log */
  1456. if (size == 0) {
  1457. IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
  1458. return;
  1459. }
  1460. IWL_ERR(priv, "Start IWL Event Log Dump: display count %d, wraps %d\n",
  1461. size, num_wraps);
  1462. /* if uCode has wrapped back to top of log, start at the oldest entry,
  1463. * i.e the next one that uCode would fill. */
  1464. if (num_wraps)
  1465. iwl_print_event_log(priv, next_entry,
  1466. capacity - next_entry, mode);
  1467. /* (then/else) start at top of log */
  1468. iwl_print_event_log(priv, 0, next_entry, mode);
  1469. }
  1470. #endif
  1471. /**
  1472. * iwl_alive_start - called after REPLY_ALIVE notification received
  1473. * from protocol/runtime uCode (initialization uCode's
  1474. * Alive gets handled by iwl_init_alive_start()).
  1475. */
  1476. static void iwl_alive_start(struct iwl_priv *priv)
  1477. {
  1478. int ret = 0;
  1479. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  1480. if (priv->card_alive.is_valid != UCODE_VALID_OK) {
  1481. /* We had an error bringing up the hardware, so take it
  1482. * all the way back down so we can try again */
  1483. IWL_DEBUG_INFO(priv, "Alive failed.\n");
  1484. goto restart;
  1485. }
  1486. /* Initialize uCode has loaded Runtime uCode ... verify inst image.
  1487. * This is a paranoid check, because we would not have gotten the
  1488. * "runtime" alive if code weren't properly loaded. */
  1489. if (iwl_verify_ucode(priv)) {
  1490. /* Runtime instruction load was bad;
  1491. * take it all the way back down so we can try again */
  1492. IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
  1493. goto restart;
  1494. }
  1495. iwl_clear_stations_table(priv);
  1496. ret = priv->cfg->ops->lib->alive_notify(priv);
  1497. if (ret) {
  1498. IWL_WARN(priv,
  1499. "Could not complete ALIVE transition [ntf]: %d\n", ret);
  1500. goto restart;
  1501. }
  1502. /* After the ALIVE response, we can send host commands to the uCode */
  1503. set_bit(STATUS_ALIVE, &priv->status);
  1504. if (iwl_is_rfkill(priv))
  1505. return;
  1506. ieee80211_wake_queues(priv->hw);
  1507. priv->active_rate = priv->rates_mask;
  1508. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  1509. /* Configure Tx antenna selection based on H/W config */
  1510. if (priv->cfg->ops->hcmd->set_tx_ant)
  1511. priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
  1512. if (iwl_is_associated(priv)) {
  1513. struct iwl_rxon_cmd *active_rxon =
  1514. (struct iwl_rxon_cmd *)&priv->active_rxon;
  1515. /* apply any changes in staging */
  1516. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  1517. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  1518. } else {
  1519. /* Initialize our rx_config data */
  1520. iwl_connection_init_rx_config(priv, priv->iw_mode);
  1521. if (priv->cfg->ops->hcmd->set_rxon_chain)
  1522. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  1523. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  1524. }
  1525. /* Configure Bluetooth device coexistence support */
  1526. iwl_send_bt_config(priv);
  1527. iwl_reset_run_time_calib(priv);
  1528. /* Configure the adapter for unassociated operation */
  1529. iwlcore_commit_rxon(priv);
  1530. /* At this point, the NIC is initialized and operational */
  1531. iwl_rf_kill_ct_config(priv);
  1532. iwl_leds_init(priv);
  1533. IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
  1534. set_bit(STATUS_READY, &priv->status);
  1535. wake_up_interruptible(&priv->wait_command_queue);
  1536. iwl_power_update_mode(priv, true);
  1537. /* reassociate for ADHOC mode */
  1538. if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) {
  1539. struct sk_buff *beacon = ieee80211_beacon_get(priv->hw,
  1540. priv->vif);
  1541. if (beacon)
  1542. iwl_mac_beacon_update(priv->hw, beacon);
  1543. }
  1544. if (test_and_clear_bit(STATUS_MODE_PENDING, &priv->status))
  1545. iwl_set_mode(priv, priv->iw_mode);
  1546. return;
  1547. restart:
  1548. queue_work(priv->workqueue, &priv->restart);
  1549. }
  1550. static void iwl_cancel_deferred_work(struct iwl_priv *priv);
  1551. static void __iwl_down(struct iwl_priv *priv)
  1552. {
  1553. unsigned long flags;
  1554. int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
  1555. IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
  1556. if (!exit_pending)
  1557. set_bit(STATUS_EXIT_PENDING, &priv->status);
  1558. iwl_clear_stations_table(priv);
  1559. /* Unblock any waiting calls */
  1560. wake_up_interruptible_all(&priv->wait_command_queue);
  1561. /* Wipe out the EXIT_PENDING status bit if we are not actually
  1562. * exiting the module */
  1563. if (!exit_pending)
  1564. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  1565. /* stop and reset the on-board processor */
  1566. iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  1567. /* tell the device to stop sending interrupts */
  1568. spin_lock_irqsave(&priv->lock, flags);
  1569. iwl_disable_interrupts(priv);
  1570. spin_unlock_irqrestore(&priv->lock, flags);
  1571. iwl_synchronize_irq(priv);
  1572. if (priv->mac80211_registered)
  1573. ieee80211_stop_queues(priv->hw);
  1574. /* If we have not previously called iwl_init() then
  1575. * clear all bits but the RF Kill bit and return */
  1576. if (!iwl_is_init(priv)) {
  1577. priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  1578. STATUS_RF_KILL_HW |
  1579. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  1580. STATUS_GEO_CONFIGURED |
  1581. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  1582. STATUS_EXIT_PENDING;
  1583. goto exit;
  1584. }
  1585. /* ...otherwise clear out all the status bits but the RF Kill
  1586. * bit and continue taking the NIC down. */
  1587. priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  1588. STATUS_RF_KILL_HW |
  1589. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  1590. STATUS_GEO_CONFIGURED |
  1591. test_bit(STATUS_FW_ERROR, &priv->status) <<
  1592. STATUS_FW_ERROR |
  1593. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  1594. STATUS_EXIT_PENDING;
  1595. /* device going down, Stop using ICT table */
  1596. iwl_disable_ict(priv);
  1597. spin_lock_irqsave(&priv->lock, flags);
  1598. iwl_clear_bit(priv, CSR_GP_CNTRL,
  1599. CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  1600. spin_unlock_irqrestore(&priv->lock, flags);
  1601. iwl_txq_ctx_stop(priv);
  1602. iwl_rxq_stop(priv);
  1603. iwl_write_prph(priv, APMG_CLK_DIS_REG,
  1604. APMG_CLK_VAL_DMA_CLK_RQT);
  1605. udelay(5);
  1606. /* Stop the device, and put it in low power state */
  1607. priv->cfg->ops->lib->apm_ops.stop(priv);
  1608. exit:
  1609. memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
  1610. if (priv->ibss_beacon)
  1611. dev_kfree_skb(priv->ibss_beacon);
  1612. priv->ibss_beacon = NULL;
  1613. /* clear out any free frames */
  1614. iwl_clear_free_frames(priv);
  1615. }
  1616. static void iwl_down(struct iwl_priv *priv)
  1617. {
  1618. mutex_lock(&priv->mutex);
  1619. __iwl_down(priv);
  1620. mutex_unlock(&priv->mutex);
  1621. iwl_cancel_deferred_work(priv);
  1622. }
  1623. #define HW_READY_TIMEOUT (50)
  1624. static int iwl_set_hw_ready(struct iwl_priv *priv)
  1625. {
  1626. int ret = 0;
  1627. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  1628. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
  1629. /* See if we got it */
  1630. ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
  1631. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
  1632. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
  1633. HW_READY_TIMEOUT);
  1634. if (ret != -ETIMEDOUT)
  1635. priv->hw_ready = true;
  1636. else
  1637. priv->hw_ready = false;
  1638. IWL_DEBUG_INFO(priv, "hardware %s\n",
  1639. (priv->hw_ready == 1) ? "ready" : "not ready");
  1640. return ret;
  1641. }
  1642. static int iwl_prepare_card_hw(struct iwl_priv *priv)
  1643. {
  1644. int ret = 0;
  1645. IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter \n");
  1646. ret = iwl_set_hw_ready(priv);
  1647. if (priv->hw_ready)
  1648. return ret;
  1649. /* If HW is not ready, prepare the conditions to check again */
  1650. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  1651. CSR_HW_IF_CONFIG_REG_PREPARE);
  1652. ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
  1653. ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
  1654. CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
  1655. /* HW should be ready by now, check again. */
  1656. if (ret != -ETIMEDOUT)
  1657. iwl_set_hw_ready(priv);
  1658. return ret;
  1659. }
  1660. #define MAX_HW_RESTARTS 5
  1661. static int __iwl_up(struct iwl_priv *priv)
  1662. {
  1663. int i;
  1664. int ret;
  1665. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  1666. IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
  1667. return -EIO;
  1668. }
  1669. if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
  1670. IWL_ERR(priv, "ucode not available for device bringup\n");
  1671. return -EIO;
  1672. }
  1673. iwl_prepare_card_hw(priv);
  1674. if (!priv->hw_ready) {
  1675. IWL_WARN(priv, "Exit HW not ready\n");
  1676. return -EIO;
  1677. }
  1678. /* If platform's RF_KILL switch is NOT set to KILL */
  1679. if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  1680. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  1681. else
  1682. set_bit(STATUS_RF_KILL_HW, &priv->status);
  1683. if (iwl_is_rfkill(priv)) {
  1684. wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
  1685. iwl_enable_interrupts(priv);
  1686. IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
  1687. return 0;
  1688. }
  1689. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  1690. ret = iwl_hw_nic_init(priv);
  1691. if (ret) {
  1692. IWL_ERR(priv, "Unable to init nic\n");
  1693. return ret;
  1694. }
  1695. /* make sure rfkill handshake bits are cleared */
  1696. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1697. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  1698. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  1699. /* clear (again), then enable host interrupts */
  1700. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  1701. iwl_enable_interrupts(priv);
  1702. /* really make sure rfkill handshake bits are cleared */
  1703. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1704. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1705. /* Copy original ucode data image from disk into backup cache.
  1706. * This will be used to initialize the on-board processor's
  1707. * data SRAM for a clean start when the runtime program first loads. */
  1708. memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
  1709. priv->ucode_data.len);
  1710. for (i = 0; i < MAX_HW_RESTARTS; i++) {
  1711. iwl_clear_stations_table(priv);
  1712. /* load bootstrap state machine,
  1713. * load bootstrap program into processor's memory,
  1714. * prepare to load the "initialize" uCode */
  1715. ret = priv->cfg->ops->lib->load_ucode(priv);
  1716. if (ret) {
  1717. IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
  1718. ret);
  1719. continue;
  1720. }
  1721. /* start card; "initialize" will load runtime ucode */
  1722. iwl_nic_start(priv);
  1723. IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
  1724. return 0;
  1725. }
  1726. set_bit(STATUS_EXIT_PENDING, &priv->status);
  1727. __iwl_down(priv);
  1728. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  1729. /* tried to restart and config the device for as long as our
  1730. * patience could withstand */
  1731. IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
  1732. return -EIO;
  1733. }
  1734. /*****************************************************************************
  1735. *
  1736. * Workqueue callbacks
  1737. *
  1738. *****************************************************************************/
  1739. static void iwl_bg_init_alive_start(struct work_struct *data)
  1740. {
  1741. struct iwl_priv *priv =
  1742. container_of(data, struct iwl_priv, init_alive_start.work);
  1743. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1744. return;
  1745. mutex_lock(&priv->mutex);
  1746. priv->cfg->ops->lib->init_alive_start(priv);
  1747. mutex_unlock(&priv->mutex);
  1748. }
  1749. static void iwl_bg_alive_start(struct work_struct *data)
  1750. {
  1751. struct iwl_priv *priv =
  1752. container_of(data, struct iwl_priv, alive_start.work);
  1753. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1754. return;
  1755. /* enable dram interrupt */
  1756. iwl_reset_ict(priv);
  1757. mutex_lock(&priv->mutex);
  1758. iwl_alive_start(priv);
  1759. mutex_unlock(&priv->mutex);
  1760. }
  1761. static void iwl_bg_run_time_calib_work(struct work_struct *work)
  1762. {
  1763. struct iwl_priv *priv = container_of(work, struct iwl_priv,
  1764. run_time_calib_work);
  1765. mutex_lock(&priv->mutex);
  1766. if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
  1767. test_bit(STATUS_SCANNING, &priv->status)) {
  1768. mutex_unlock(&priv->mutex);
  1769. return;
  1770. }
  1771. if (priv->start_calib) {
  1772. iwl_chain_noise_calibration(priv, &priv->statistics);
  1773. iwl_sensitivity_calibration(priv, &priv->statistics);
  1774. }
  1775. mutex_unlock(&priv->mutex);
  1776. return;
  1777. }
  1778. static void iwl_bg_up(struct work_struct *data)
  1779. {
  1780. struct iwl_priv *priv = container_of(data, struct iwl_priv, up);
  1781. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1782. return;
  1783. mutex_lock(&priv->mutex);
  1784. __iwl_up(priv);
  1785. mutex_unlock(&priv->mutex);
  1786. }
  1787. static void iwl_bg_restart(struct work_struct *data)
  1788. {
  1789. struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
  1790. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1791. return;
  1792. if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
  1793. mutex_lock(&priv->mutex);
  1794. priv->vif = NULL;
  1795. priv->is_open = 0;
  1796. mutex_unlock(&priv->mutex);
  1797. iwl_down(priv);
  1798. ieee80211_restart_hw(priv->hw);
  1799. } else {
  1800. iwl_down(priv);
  1801. queue_work(priv->workqueue, &priv->up);
  1802. }
  1803. }
  1804. static void iwl_bg_rx_replenish(struct work_struct *data)
  1805. {
  1806. struct iwl_priv *priv =
  1807. container_of(data, struct iwl_priv, rx_replenish);
  1808. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1809. return;
  1810. mutex_lock(&priv->mutex);
  1811. iwl_rx_replenish(priv);
  1812. mutex_unlock(&priv->mutex);
  1813. }
  1814. #define IWL_DELAY_NEXT_SCAN (HZ*2)
  1815. void iwl_post_associate(struct iwl_priv *priv)
  1816. {
  1817. struct ieee80211_conf *conf = NULL;
  1818. int ret = 0;
  1819. unsigned long flags;
  1820. if (priv->iw_mode == NL80211_IFTYPE_AP) {
  1821. IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
  1822. return;
  1823. }
  1824. IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
  1825. priv->assoc_id, priv->active_rxon.bssid_addr);
  1826. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1827. return;
  1828. if (!priv->vif || !priv->is_open)
  1829. return;
  1830. iwl_scan_cancel_timeout(priv, 200);
  1831. conf = ieee80211_get_hw_conf(priv->hw);
  1832. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  1833. iwlcore_commit_rxon(priv);
  1834. iwl_setup_rxon_timing(priv);
  1835. ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  1836. sizeof(priv->rxon_timing), &priv->rxon_timing);
  1837. if (ret)
  1838. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  1839. "Attempting to continue.\n");
  1840. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  1841. iwl_set_rxon_ht(priv, &priv->current_ht_config);
  1842. if (priv->cfg->ops->hcmd->set_rxon_chain)
  1843. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  1844. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  1845. IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
  1846. priv->assoc_id, priv->beacon_int);
  1847. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  1848. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  1849. else
  1850. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  1851. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  1852. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  1853. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  1854. else
  1855. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1856. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  1857. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1858. }
  1859. iwlcore_commit_rxon(priv);
  1860. switch (priv->iw_mode) {
  1861. case NL80211_IFTYPE_STATION:
  1862. break;
  1863. case NL80211_IFTYPE_ADHOC:
  1864. /* assume default assoc id */
  1865. priv->assoc_id = 1;
  1866. iwl_rxon_add_station(priv, priv->bssid, 0);
  1867. iwl_send_beacon_cmd(priv);
  1868. break;
  1869. default:
  1870. IWL_ERR(priv, "%s Should not be called in %d mode\n",
  1871. __func__, priv->iw_mode);
  1872. break;
  1873. }
  1874. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  1875. priv->assoc_station_added = 1;
  1876. spin_lock_irqsave(&priv->lock, flags);
  1877. iwl_activate_qos(priv, 0);
  1878. spin_unlock_irqrestore(&priv->lock, flags);
  1879. /* the chain noise calibration will enabled PM upon completion
  1880. * If chain noise has already been run, then we need to enable
  1881. * power management here */
  1882. if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
  1883. iwl_power_update_mode(priv, false);
  1884. /* Enable Rx differential gain and sensitivity calibrations */
  1885. iwl_chain_noise_reset(priv);
  1886. priv->start_calib = 1;
  1887. }
  1888. /*****************************************************************************
  1889. *
  1890. * mac80211 entry point functions
  1891. *
  1892. *****************************************************************************/
  1893. #define UCODE_READY_TIMEOUT (4 * HZ)
  1894. /*
  1895. * Not a mac80211 entry point function, but it fits in with all the
  1896. * other mac80211 functions grouped here.
  1897. */
  1898. static int iwl_setup_mac(struct iwl_priv *priv)
  1899. {
  1900. int ret;
  1901. struct ieee80211_hw *hw = priv->hw;
  1902. hw->rate_control_algorithm = "iwl-agn-rs";
  1903. /* Tell mac80211 our characteristics */
  1904. hw->flags = IEEE80211_HW_SIGNAL_DBM |
  1905. IEEE80211_HW_NOISE_DBM |
  1906. IEEE80211_HW_AMPDU_AGGREGATION |
  1907. IEEE80211_HW_SPECTRUM_MGMT;
  1908. if (!priv->cfg->broken_powersave)
  1909. hw->flags |= IEEE80211_HW_SUPPORTS_PS |
  1910. IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
  1911. hw->sta_data_size = sizeof(struct iwl_station_priv);
  1912. hw->wiphy->interface_modes =
  1913. BIT(NL80211_IFTYPE_STATION) |
  1914. BIT(NL80211_IFTYPE_ADHOC);
  1915. hw->wiphy->custom_regulatory = true;
  1916. /* Firmware does not support this */
  1917. hw->wiphy->disable_beacon_hints = true;
  1918. /*
  1919. * For now, disable PS by default because it affects
  1920. * RX performance significantly.
  1921. */
  1922. hw->wiphy->ps_default = false;
  1923. hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
  1924. /* we create the 802.11 header and a zero-length SSID element */
  1925. hw->wiphy->max_scan_ie_len = IWL_MAX_PROBE_REQUEST - 24 - 2;
  1926. /* Default value; 4 EDCA QOS priorities */
  1927. hw->queues = 4;
  1928. hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
  1929. if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
  1930. priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  1931. &priv->bands[IEEE80211_BAND_2GHZ];
  1932. if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
  1933. priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  1934. &priv->bands[IEEE80211_BAND_5GHZ];
  1935. ret = ieee80211_register_hw(priv->hw);
  1936. if (ret) {
  1937. IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
  1938. return ret;
  1939. }
  1940. priv->mac80211_registered = 1;
  1941. return 0;
  1942. }
  1943. static int iwl_mac_start(struct ieee80211_hw *hw)
  1944. {
  1945. struct iwl_priv *priv = hw->priv;
  1946. int ret;
  1947. IWL_DEBUG_MAC80211(priv, "enter\n");
  1948. /* we should be verifying the device is ready to be opened */
  1949. mutex_lock(&priv->mutex);
  1950. /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
  1951. * ucode filename and max sizes are card-specific. */
  1952. if (!priv->ucode_code.len) {
  1953. ret = iwl_read_ucode(priv);
  1954. if (ret) {
  1955. IWL_ERR(priv, "Could not read microcode: %d\n", ret);
  1956. mutex_unlock(&priv->mutex);
  1957. return ret;
  1958. }
  1959. }
  1960. ret = __iwl_up(priv);
  1961. mutex_unlock(&priv->mutex);
  1962. if (ret)
  1963. return ret;
  1964. if (iwl_is_rfkill(priv))
  1965. goto out;
  1966. IWL_DEBUG_INFO(priv, "Start UP work done.\n");
  1967. /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
  1968. * mac80211 will not be run successfully. */
  1969. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  1970. test_bit(STATUS_READY, &priv->status),
  1971. UCODE_READY_TIMEOUT);
  1972. if (!ret) {
  1973. if (!test_bit(STATUS_READY, &priv->status)) {
  1974. IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
  1975. jiffies_to_msecs(UCODE_READY_TIMEOUT));
  1976. return -ETIMEDOUT;
  1977. }
  1978. }
  1979. iwl_led_start(priv);
  1980. out:
  1981. priv->is_open = 1;
  1982. IWL_DEBUG_MAC80211(priv, "leave\n");
  1983. return 0;
  1984. }
  1985. static void iwl_mac_stop(struct ieee80211_hw *hw)
  1986. {
  1987. struct iwl_priv *priv = hw->priv;
  1988. IWL_DEBUG_MAC80211(priv, "enter\n");
  1989. if (!priv->is_open)
  1990. return;
  1991. priv->is_open = 0;
  1992. if (iwl_is_ready_rf(priv) || test_bit(STATUS_SCAN_HW, &priv->status)) {
  1993. /* stop mac, cancel any scan request and clear
  1994. * RXON_FILTER_ASSOC_MSK BIT
  1995. */
  1996. mutex_lock(&priv->mutex);
  1997. iwl_scan_cancel_timeout(priv, 100);
  1998. mutex_unlock(&priv->mutex);
  1999. }
  2000. iwl_down(priv);
  2001. flush_workqueue(priv->workqueue);
  2002. /* enable interrupts again in order to receive rfkill changes */
  2003. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  2004. iwl_enable_interrupts(priv);
  2005. IWL_DEBUG_MAC80211(priv, "leave\n");
  2006. }
  2007. static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  2008. {
  2009. struct iwl_priv *priv = hw->priv;
  2010. IWL_DEBUG_MACDUMP(priv, "enter\n");
  2011. IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
  2012. ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
  2013. if (iwl_tx_skb(priv, skb))
  2014. dev_kfree_skb_any(skb);
  2015. IWL_DEBUG_MACDUMP(priv, "leave\n");
  2016. return NETDEV_TX_OK;
  2017. }
  2018. void iwl_config_ap(struct iwl_priv *priv)
  2019. {
  2020. int ret = 0;
  2021. unsigned long flags;
  2022. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2023. return;
  2024. /* The following should be done only at AP bring up */
  2025. if (!iwl_is_associated(priv)) {
  2026. /* RXON - unassoc (to set timing command) */
  2027. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2028. iwlcore_commit_rxon(priv);
  2029. /* RXON Timing */
  2030. iwl_setup_rxon_timing(priv);
  2031. ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  2032. sizeof(priv->rxon_timing), &priv->rxon_timing);
  2033. if (ret)
  2034. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  2035. "Attempting to continue.\n");
  2036. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2037. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2038. /* FIXME: what should be the assoc_id for AP? */
  2039. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  2040. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  2041. priv->staging_rxon.flags |=
  2042. RXON_FLG_SHORT_PREAMBLE_MSK;
  2043. else
  2044. priv->staging_rxon.flags &=
  2045. ~RXON_FLG_SHORT_PREAMBLE_MSK;
  2046. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  2047. if (priv->assoc_capability &
  2048. WLAN_CAPABILITY_SHORT_SLOT_TIME)
  2049. priv->staging_rxon.flags |=
  2050. RXON_FLG_SHORT_SLOT_MSK;
  2051. else
  2052. priv->staging_rxon.flags &=
  2053. ~RXON_FLG_SHORT_SLOT_MSK;
  2054. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  2055. priv->staging_rxon.flags &=
  2056. ~RXON_FLG_SHORT_SLOT_MSK;
  2057. }
  2058. /* restore RXON assoc */
  2059. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  2060. iwlcore_commit_rxon(priv);
  2061. spin_lock_irqsave(&priv->lock, flags);
  2062. iwl_activate_qos(priv, 1);
  2063. spin_unlock_irqrestore(&priv->lock, flags);
  2064. iwl_add_bcast_station(priv);
  2065. }
  2066. iwl_send_beacon_cmd(priv);
  2067. /* FIXME - we need to add code here to detect a totally new
  2068. * configuration, reset the AP, unassoc, rxon timing, assoc,
  2069. * clear sta table, add BCAST sta... */
  2070. }
  2071. static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
  2072. struct ieee80211_key_conf *keyconf, const u8 *addr,
  2073. u32 iv32, u16 *phase1key)
  2074. {
  2075. struct iwl_priv *priv = hw->priv;
  2076. IWL_DEBUG_MAC80211(priv, "enter\n");
  2077. iwl_update_tkip_key(priv, keyconf, addr, iv32, phase1key);
  2078. IWL_DEBUG_MAC80211(priv, "leave\n");
  2079. }
  2080. static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  2081. struct ieee80211_vif *vif,
  2082. struct ieee80211_sta *sta,
  2083. struct ieee80211_key_conf *key)
  2084. {
  2085. struct iwl_priv *priv = hw->priv;
  2086. const u8 *addr;
  2087. int ret;
  2088. u8 sta_id;
  2089. bool is_default_wep_key = false;
  2090. IWL_DEBUG_MAC80211(priv, "enter\n");
  2091. if (priv->cfg->mod_params->sw_crypto) {
  2092. IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
  2093. return -EOPNOTSUPP;
  2094. }
  2095. addr = sta ? sta->addr : iwl_bcast_addr;
  2096. sta_id = iwl_find_station(priv, addr);
  2097. if (sta_id == IWL_INVALID_STATION) {
  2098. IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n",
  2099. addr);
  2100. return -EINVAL;
  2101. }
  2102. mutex_lock(&priv->mutex);
  2103. iwl_scan_cancel_timeout(priv, 100);
  2104. mutex_unlock(&priv->mutex);
  2105. /* If we are getting WEP group key and we didn't receive any key mapping
  2106. * so far, we are in legacy wep mode (group key only), otherwise we are
  2107. * in 1X mode.
  2108. * In legacy wep mode, we use another host command to the uCode */
  2109. if (key->alg == ALG_WEP && sta_id == priv->hw_params.bcast_sta_id &&
  2110. priv->iw_mode != NL80211_IFTYPE_AP) {
  2111. if (cmd == SET_KEY)
  2112. is_default_wep_key = !priv->key_mapping_key;
  2113. else
  2114. is_default_wep_key =
  2115. (key->hw_key_idx == HW_KEY_DEFAULT);
  2116. }
  2117. switch (cmd) {
  2118. case SET_KEY:
  2119. if (is_default_wep_key)
  2120. ret = iwl_set_default_wep_key(priv, key);
  2121. else
  2122. ret = iwl_set_dynamic_key(priv, key, sta_id);
  2123. IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
  2124. break;
  2125. case DISABLE_KEY:
  2126. if (is_default_wep_key)
  2127. ret = iwl_remove_default_wep_key(priv, key);
  2128. else
  2129. ret = iwl_remove_dynamic_key(priv, key, sta_id);
  2130. IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
  2131. break;
  2132. default:
  2133. ret = -EINVAL;
  2134. }
  2135. IWL_DEBUG_MAC80211(priv, "leave\n");
  2136. return ret;
  2137. }
  2138. static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
  2139. enum ieee80211_ampdu_mlme_action action,
  2140. struct ieee80211_sta *sta, u16 tid, u16 *ssn)
  2141. {
  2142. struct iwl_priv *priv = hw->priv;
  2143. int ret;
  2144. IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
  2145. sta->addr, tid);
  2146. if (!(priv->cfg->sku & IWL_SKU_N))
  2147. return -EACCES;
  2148. switch (action) {
  2149. case IEEE80211_AMPDU_RX_START:
  2150. IWL_DEBUG_HT(priv, "start Rx\n");
  2151. return iwl_sta_rx_agg_start(priv, sta->addr, tid, *ssn);
  2152. case IEEE80211_AMPDU_RX_STOP:
  2153. IWL_DEBUG_HT(priv, "stop Rx\n");
  2154. ret = iwl_sta_rx_agg_stop(priv, sta->addr, tid);
  2155. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2156. return 0;
  2157. else
  2158. return ret;
  2159. case IEEE80211_AMPDU_TX_START:
  2160. IWL_DEBUG_HT(priv, "start Tx\n");
  2161. return iwl_tx_agg_start(priv, sta->addr, tid, ssn);
  2162. case IEEE80211_AMPDU_TX_STOP:
  2163. IWL_DEBUG_HT(priv, "stop Tx\n");
  2164. ret = iwl_tx_agg_stop(priv, sta->addr, tid);
  2165. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2166. return 0;
  2167. else
  2168. return ret;
  2169. default:
  2170. IWL_DEBUG_HT(priv, "unknown\n");
  2171. return -EINVAL;
  2172. break;
  2173. }
  2174. return 0;
  2175. }
  2176. static int iwl_mac_get_stats(struct ieee80211_hw *hw,
  2177. struct ieee80211_low_level_stats *stats)
  2178. {
  2179. struct iwl_priv *priv = hw->priv;
  2180. priv = hw->priv;
  2181. IWL_DEBUG_MAC80211(priv, "enter\n");
  2182. IWL_DEBUG_MAC80211(priv, "leave\n");
  2183. return 0;
  2184. }
  2185. /*****************************************************************************
  2186. *
  2187. * sysfs attributes
  2188. *
  2189. *****************************************************************************/
  2190. #ifdef CONFIG_IWLWIFI_DEBUG
  2191. /*
  2192. * The following adds a new attribute to the sysfs representation
  2193. * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
  2194. * used for controlling the debug level.
  2195. *
  2196. * See the level definitions in iwl for details.
  2197. *
  2198. * The debug_level being managed using sysfs below is a per device debug
  2199. * level that is used instead of the global debug level if it (the per
  2200. * device debug level) is set.
  2201. */
  2202. static ssize_t show_debug_level(struct device *d,
  2203. struct device_attribute *attr, char *buf)
  2204. {
  2205. struct iwl_priv *priv = dev_get_drvdata(d);
  2206. return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
  2207. }
  2208. static ssize_t store_debug_level(struct device *d,
  2209. struct device_attribute *attr,
  2210. const char *buf, size_t count)
  2211. {
  2212. struct iwl_priv *priv = dev_get_drvdata(d);
  2213. unsigned long val;
  2214. int ret;
  2215. ret = strict_strtoul(buf, 0, &val);
  2216. if (ret)
  2217. IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
  2218. else {
  2219. priv->debug_level = val;
  2220. if (iwl_alloc_traffic_mem(priv))
  2221. IWL_ERR(priv,
  2222. "Not enough memory to generate traffic log\n");
  2223. }
  2224. return strnlen(buf, count);
  2225. }
  2226. static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
  2227. show_debug_level, store_debug_level);
  2228. #endif /* CONFIG_IWLWIFI_DEBUG */
  2229. static ssize_t show_temperature(struct device *d,
  2230. struct device_attribute *attr, char *buf)
  2231. {
  2232. struct iwl_priv *priv = dev_get_drvdata(d);
  2233. if (!iwl_is_alive(priv))
  2234. return -EAGAIN;
  2235. return sprintf(buf, "%d\n", priv->temperature);
  2236. }
  2237. static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
  2238. static ssize_t show_tx_power(struct device *d,
  2239. struct device_attribute *attr, char *buf)
  2240. {
  2241. struct iwl_priv *priv = dev_get_drvdata(d);
  2242. if (!iwl_is_ready_rf(priv))
  2243. return sprintf(buf, "off\n");
  2244. else
  2245. return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
  2246. }
  2247. static ssize_t store_tx_power(struct device *d,
  2248. struct device_attribute *attr,
  2249. const char *buf, size_t count)
  2250. {
  2251. struct iwl_priv *priv = dev_get_drvdata(d);
  2252. unsigned long val;
  2253. int ret;
  2254. ret = strict_strtoul(buf, 10, &val);
  2255. if (ret)
  2256. IWL_INFO(priv, "%s is not in decimal form.\n", buf);
  2257. else {
  2258. ret = iwl_set_tx_power(priv, val, false);
  2259. if (ret)
  2260. IWL_ERR(priv, "failed setting tx power (0x%d).\n",
  2261. ret);
  2262. else
  2263. ret = count;
  2264. }
  2265. return ret;
  2266. }
  2267. static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
  2268. static ssize_t show_flags(struct device *d,
  2269. struct device_attribute *attr, char *buf)
  2270. {
  2271. struct iwl_priv *priv = dev_get_drvdata(d);
  2272. return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
  2273. }
  2274. static ssize_t store_flags(struct device *d,
  2275. struct device_attribute *attr,
  2276. const char *buf, size_t count)
  2277. {
  2278. struct iwl_priv *priv = dev_get_drvdata(d);
  2279. unsigned long val;
  2280. u32 flags;
  2281. int ret = strict_strtoul(buf, 0, &val);
  2282. if (ret)
  2283. return ret;
  2284. flags = (u32)val;
  2285. mutex_lock(&priv->mutex);
  2286. if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
  2287. /* Cancel any currently running scans... */
  2288. if (iwl_scan_cancel_timeout(priv, 100))
  2289. IWL_WARN(priv, "Could not cancel scan.\n");
  2290. else {
  2291. IWL_DEBUG_INFO(priv, "Commit rxon.flags = 0x%04X\n", flags);
  2292. priv->staging_rxon.flags = cpu_to_le32(flags);
  2293. iwlcore_commit_rxon(priv);
  2294. }
  2295. }
  2296. mutex_unlock(&priv->mutex);
  2297. return count;
  2298. }
  2299. static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
  2300. static ssize_t show_filter_flags(struct device *d,
  2301. struct device_attribute *attr, char *buf)
  2302. {
  2303. struct iwl_priv *priv = dev_get_drvdata(d);
  2304. return sprintf(buf, "0x%04X\n",
  2305. le32_to_cpu(priv->active_rxon.filter_flags));
  2306. }
  2307. static ssize_t store_filter_flags(struct device *d,
  2308. struct device_attribute *attr,
  2309. const char *buf, size_t count)
  2310. {
  2311. struct iwl_priv *priv = dev_get_drvdata(d);
  2312. unsigned long val;
  2313. u32 filter_flags;
  2314. int ret = strict_strtoul(buf, 0, &val);
  2315. if (ret)
  2316. return ret;
  2317. filter_flags = (u32)val;
  2318. mutex_lock(&priv->mutex);
  2319. if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
  2320. /* Cancel any currently running scans... */
  2321. if (iwl_scan_cancel_timeout(priv, 100))
  2322. IWL_WARN(priv, "Could not cancel scan.\n");
  2323. else {
  2324. IWL_DEBUG_INFO(priv, "Committing rxon.filter_flags = "
  2325. "0x%04X\n", filter_flags);
  2326. priv->staging_rxon.filter_flags =
  2327. cpu_to_le32(filter_flags);
  2328. iwlcore_commit_rxon(priv);
  2329. }
  2330. }
  2331. mutex_unlock(&priv->mutex);
  2332. return count;
  2333. }
  2334. static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
  2335. store_filter_flags);
  2336. static ssize_t show_statistics(struct device *d,
  2337. struct device_attribute *attr, char *buf)
  2338. {
  2339. struct iwl_priv *priv = dev_get_drvdata(d);
  2340. u32 size = sizeof(struct iwl_notif_statistics);
  2341. u32 len = 0, ofs = 0;
  2342. u8 *data = (u8 *)&priv->statistics;
  2343. int rc = 0;
  2344. if (!iwl_is_alive(priv))
  2345. return -EAGAIN;
  2346. mutex_lock(&priv->mutex);
  2347. rc = iwl_send_statistics_request(priv, 0);
  2348. mutex_unlock(&priv->mutex);
  2349. if (rc) {
  2350. len = sprintf(buf,
  2351. "Error sending statistics request: 0x%08X\n", rc);
  2352. return len;
  2353. }
  2354. while (size && (PAGE_SIZE - len)) {
  2355. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  2356. PAGE_SIZE - len, 1);
  2357. len = strlen(buf);
  2358. if (PAGE_SIZE - len)
  2359. buf[len++] = '\n';
  2360. ofs += 16;
  2361. size -= min(size, 16U);
  2362. }
  2363. return len;
  2364. }
  2365. static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
  2366. static ssize_t show_rts_ht_protection(struct device *d,
  2367. struct device_attribute *attr, char *buf)
  2368. {
  2369. struct iwl_priv *priv = dev_get_drvdata(d);
  2370. return sprintf(buf, "%s\n",
  2371. priv->cfg->use_rts_for_ht ? "RTS/CTS" : "CTS-to-self");
  2372. }
  2373. static ssize_t store_rts_ht_protection(struct device *d,
  2374. struct device_attribute *attr,
  2375. const char *buf, size_t count)
  2376. {
  2377. struct iwl_priv *priv = dev_get_drvdata(d);
  2378. unsigned long val;
  2379. int ret;
  2380. ret = strict_strtoul(buf, 10, &val);
  2381. if (ret)
  2382. IWL_INFO(priv, "Input is not in decimal form.\n");
  2383. else {
  2384. if (!iwl_is_associated(priv))
  2385. priv->cfg->use_rts_for_ht = val ? true : false;
  2386. else
  2387. IWL_ERR(priv, "Sta associated with AP - "
  2388. "Change protection mechanism is not allowed\n");
  2389. ret = count;
  2390. }
  2391. return ret;
  2392. }
  2393. static DEVICE_ATTR(rts_ht_protection, S_IWUSR | S_IRUGO,
  2394. show_rts_ht_protection, store_rts_ht_protection);
  2395. /*****************************************************************************
  2396. *
  2397. * driver setup and teardown
  2398. *
  2399. *****************************************************************************/
  2400. static void iwl_setup_deferred_work(struct iwl_priv *priv)
  2401. {
  2402. priv->workqueue = create_singlethread_workqueue(DRV_NAME);
  2403. init_waitqueue_head(&priv->wait_command_queue);
  2404. INIT_WORK(&priv->up, iwl_bg_up);
  2405. INIT_WORK(&priv->restart, iwl_bg_restart);
  2406. INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
  2407. INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
  2408. INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
  2409. INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
  2410. INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
  2411. iwl_setup_scan_deferred_work(priv);
  2412. if (priv->cfg->ops->lib->setup_deferred_work)
  2413. priv->cfg->ops->lib->setup_deferred_work(priv);
  2414. init_timer(&priv->statistics_periodic);
  2415. priv->statistics_periodic.data = (unsigned long)priv;
  2416. priv->statistics_periodic.function = iwl_bg_statistics_periodic;
  2417. if (!priv->cfg->use_isr_legacy)
  2418. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  2419. iwl_irq_tasklet, (unsigned long)priv);
  2420. else
  2421. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  2422. iwl_irq_tasklet_legacy, (unsigned long)priv);
  2423. }
  2424. static void iwl_cancel_deferred_work(struct iwl_priv *priv)
  2425. {
  2426. if (priv->cfg->ops->lib->cancel_deferred_work)
  2427. priv->cfg->ops->lib->cancel_deferred_work(priv);
  2428. cancel_delayed_work_sync(&priv->init_alive_start);
  2429. cancel_delayed_work(&priv->scan_check);
  2430. cancel_delayed_work(&priv->alive_start);
  2431. cancel_work_sync(&priv->beacon_update);
  2432. del_timer_sync(&priv->statistics_periodic);
  2433. }
  2434. static void iwl_init_hw_rates(struct iwl_priv *priv,
  2435. struct ieee80211_rate *rates)
  2436. {
  2437. int i;
  2438. for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
  2439. rates[i].bitrate = iwl_rates[i].ieee * 5;
  2440. rates[i].hw_value = i; /* Rate scaling will work on indexes */
  2441. rates[i].hw_value_short = i;
  2442. rates[i].flags = 0;
  2443. if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
  2444. /*
  2445. * If CCK != 1M then set short preamble rate flag.
  2446. */
  2447. rates[i].flags |=
  2448. (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
  2449. 0 : IEEE80211_RATE_SHORT_PREAMBLE;
  2450. }
  2451. }
  2452. }
  2453. static int iwl_init_drv(struct iwl_priv *priv)
  2454. {
  2455. int ret;
  2456. priv->ibss_beacon = NULL;
  2457. spin_lock_init(&priv->lock);
  2458. spin_lock_init(&priv->sta_lock);
  2459. spin_lock_init(&priv->hcmd_lock);
  2460. INIT_LIST_HEAD(&priv->free_frames);
  2461. mutex_init(&priv->mutex);
  2462. /* Clear the driver's (not device's) station table */
  2463. iwl_clear_stations_table(priv);
  2464. priv->ieee_channels = NULL;
  2465. priv->ieee_rates = NULL;
  2466. priv->band = IEEE80211_BAND_2GHZ;
  2467. priv->iw_mode = NL80211_IFTYPE_STATION;
  2468. if (priv->cfg->support_sm_ps)
  2469. priv->current_ht_config.sm_ps = WLAN_HT_CAP_SM_PS_DYNAMIC;
  2470. else
  2471. priv->current_ht_config.sm_ps = WLAN_HT_CAP_SM_PS_DISABLED;
  2472. /* Choose which receivers/antennas to use */
  2473. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2474. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2475. iwl_init_scan_params(priv);
  2476. iwl_reset_qos(priv);
  2477. priv->qos_data.qos_active = 0;
  2478. priv->qos_data.qos_cap.val = 0;
  2479. priv->rates_mask = IWL_RATES_MASK;
  2480. /* Set the tx_power_user_lmt to the lowest power level
  2481. * this value will get overwritten by channel max power avg
  2482. * from eeprom */
  2483. priv->tx_power_user_lmt = IWL_TX_POWER_TARGET_POWER_MIN;
  2484. ret = iwl_init_channel_map(priv);
  2485. if (ret) {
  2486. IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
  2487. goto err;
  2488. }
  2489. ret = iwlcore_init_geos(priv);
  2490. if (ret) {
  2491. IWL_ERR(priv, "initializing geos failed: %d\n", ret);
  2492. goto err_free_channel_map;
  2493. }
  2494. iwl_init_hw_rates(priv, priv->ieee_rates);
  2495. return 0;
  2496. err_free_channel_map:
  2497. iwl_free_channel_map(priv);
  2498. err:
  2499. return ret;
  2500. }
  2501. static void iwl_uninit_drv(struct iwl_priv *priv)
  2502. {
  2503. iwl_calib_free_results(priv);
  2504. iwlcore_free_geos(priv);
  2505. iwl_free_channel_map(priv);
  2506. kfree(priv->scan);
  2507. }
  2508. static struct attribute *iwl_sysfs_entries[] = {
  2509. &dev_attr_flags.attr,
  2510. &dev_attr_filter_flags.attr,
  2511. &dev_attr_statistics.attr,
  2512. &dev_attr_temperature.attr,
  2513. &dev_attr_tx_power.attr,
  2514. &dev_attr_rts_ht_protection.attr,
  2515. #ifdef CONFIG_IWLWIFI_DEBUG
  2516. &dev_attr_debug_level.attr,
  2517. #endif
  2518. NULL
  2519. };
  2520. static struct attribute_group iwl_attribute_group = {
  2521. .name = NULL, /* put in device directory */
  2522. .attrs = iwl_sysfs_entries,
  2523. };
  2524. static struct ieee80211_ops iwl_hw_ops = {
  2525. .tx = iwl_mac_tx,
  2526. .start = iwl_mac_start,
  2527. .stop = iwl_mac_stop,
  2528. .add_interface = iwl_mac_add_interface,
  2529. .remove_interface = iwl_mac_remove_interface,
  2530. .config = iwl_mac_config,
  2531. .configure_filter = iwl_configure_filter,
  2532. .set_key = iwl_mac_set_key,
  2533. .update_tkip_key = iwl_mac_update_tkip_key,
  2534. .get_stats = iwl_mac_get_stats,
  2535. .get_tx_stats = iwl_mac_get_tx_stats,
  2536. .conf_tx = iwl_mac_conf_tx,
  2537. .reset_tsf = iwl_mac_reset_tsf,
  2538. .bss_info_changed = iwl_bss_info_changed,
  2539. .ampdu_action = iwl_mac_ampdu_action,
  2540. .hw_scan = iwl_mac_hw_scan
  2541. };
  2542. static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  2543. {
  2544. int err = 0;
  2545. struct iwl_priv *priv;
  2546. struct ieee80211_hw *hw;
  2547. struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
  2548. unsigned long flags;
  2549. u16 pci_cmd;
  2550. /************************
  2551. * 1. Allocating HW data
  2552. ************************/
  2553. /* Disabling hardware scan means that mac80211 will perform scans
  2554. * "the hard way", rather than using device's scan. */
  2555. if (cfg->mod_params->disable_hw_scan) {
  2556. if (iwl_debug_level & IWL_DL_INFO)
  2557. dev_printk(KERN_DEBUG, &(pdev->dev),
  2558. "Disabling hw_scan\n");
  2559. iwl_hw_ops.hw_scan = NULL;
  2560. }
  2561. hw = iwl_alloc_all(cfg, &iwl_hw_ops);
  2562. if (!hw) {
  2563. err = -ENOMEM;
  2564. goto out;
  2565. }
  2566. priv = hw->priv;
  2567. /* At this point both hw and priv are allocated. */
  2568. SET_IEEE80211_DEV(hw, &pdev->dev);
  2569. IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
  2570. priv->cfg = cfg;
  2571. priv->pci_dev = pdev;
  2572. priv->inta_mask = CSR_INI_SET_MASK;
  2573. #ifdef CONFIG_IWLWIFI_DEBUG
  2574. atomic_set(&priv->restrict_refcnt, 0);
  2575. #endif
  2576. if (iwl_alloc_traffic_mem(priv))
  2577. IWL_ERR(priv, "Not enough memory to generate traffic log\n");
  2578. /**************************
  2579. * 2. Initializing PCI bus
  2580. **************************/
  2581. if (pci_enable_device(pdev)) {
  2582. err = -ENODEV;
  2583. goto out_ieee80211_free_hw;
  2584. }
  2585. pci_set_master(pdev);
  2586. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
  2587. if (!err)
  2588. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
  2589. if (err) {
  2590. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  2591. if (!err)
  2592. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
  2593. /* both attempts failed: */
  2594. if (err) {
  2595. IWL_WARN(priv, "No suitable DMA available.\n");
  2596. goto out_pci_disable_device;
  2597. }
  2598. }
  2599. err = pci_request_regions(pdev, DRV_NAME);
  2600. if (err)
  2601. goto out_pci_disable_device;
  2602. pci_set_drvdata(pdev, priv);
  2603. /***********************
  2604. * 3. Read REV register
  2605. ***********************/
  2606. priv->hw_base = pci_iomap(pdev, 0, 0);
  2607. if (!priv->hw_base) {
  2608. err = -ENODEV;
  2609. goto out_pci_release_regions;
  2610. }
  2611. IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
  2612. (unsigned long long) pci_resource_len(pdev, 0));
  2613. IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
  2614. /* this spin lock will be used in apm_ops.init and EEPROM access
  2615. * we should init now
  2616. */
  2617. spin_lock_init(&priv->reg_lock);
  2618. iwl_hw_detect(priv);
  2619. IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s REV=0x%X\n",
  2620. priv->cfg->name, priv->hw_rev);
  2621. /* We disable the RETRY_TIMEOUT register (0x41) to keep
  2622. * PCI Tx retries from interfering with C3 CPU state */
  2623. pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
  2624. iwl_prepare_card_hw(priv);
  2625. if (!priv->hw_ready) {
  2626. IWL_WARN(priv, "Failed, HW not ready\n");
  2627. goto out_iounmap;
  2628. }
  2629. /*****************
  2630. * 4. Read EEPROM
  2631. *****************/
  2632. /* Read the EEPROM */
  2633. err = iwl_eeprom_init(priv);
  2634. if (err) {
  2635. IWL_ERR(priv, "Unable to init EEPROM\n");
  2636. goto out_iounmap;
  2637. }
  2638. err = iwl_eeprom_check_version(priv);
  2639. if (err)
  2640. goto out_free_eeprom;
  2641. /* extract MAC Address */
  2642. iwl_eeprom_get_mac(priv, priv->mac_addr);
  2643. IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr);
  2644. SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
  2645. /************************
  2646. * 5. Setup HW constants
  2647. ************************/
  2648. if (iwl_set_hw_params(priv)) {
  2649. IWL_ERR(priv, "failed to set hw parameters\n");
  2650. goto out_free_eeprom;
  2651. }
  2652. /*******************
  2653. * 6. Setup priv
  2654. *******************/
  2655. err = iwl_init_drv(priv);
  2656. if (err)
  2657. goto out_free_eeprom;
  2658. /* At this point both hw and priv are initialized. */
  2659. /********************
  2660. * 7. Setup services
  2661. ********************/
  2662. spin_lock_irqsave(&priv->lock, flags);
  2663. iwl_disable_interrupts(priv);
  2664. spin_unlock_irqrestore(&priv->lock, flags);
  2665. pci_enable_msi(priv->pci_dev);
  2666. iwl_alloc_isr_ict(priv);
  2667. err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
  2668. IRQF_SHARED, DRV_NAME, priv);
  2669. if (err) {
  2670. IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
  2671. goto out_disable_msi;
  2672. }
  2673. err = sysfs_create_group(&pdev->dev.kobj, &iwl_attribute_group);
  2674. if (err) {
  2675. IWL_ERR(priv, "failed to create sysfs device attributes\n");
  2676. goto out_free_irq;
  2677. }
  2678. iwl_setup_deferred_work(priv);
  2679. iwl_setup_rx_handlers(priv);
  2680. /**********************************
  2681. * 8. Setup and register mac80211
  2682. **********************************/
  2683. /* enable interrupts if needed: hw bug w/a */
  2684. pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
  2685. if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
  2686. pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
  2687. pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
  2688. }
  2689. iwl_enable_interrupts(priv);
  2690. err = iwl_setup_mac(priv);
  2691. if (err)
  2692. goto out_remove_sysfs;
  2693. err = iwl_dbgfs_register(priv, DRV_NAME);
  2694. if (err)
  2695. IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
  2696. /* If platform's RF_KILL switch is NOT set to KILL */
  2697. if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  2698. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  2699. else
  2700. set_bit(STATUS_RF_KILL_HW, &priv->status);
  2701. wiphy_rfkill_set_hw_state(priv->hw->wiphy,
  2702. test_bit(STATUS_RF_KILL_HW, &priv->status));
  2703. iwl_power_initialize(priv);
  2704. iwl_tt_initialize(priv);
  2705. return 0;
  2706. out_remove_sysfs:
  2707. destroy_workqueue(priv->workqueue);
  2708. priv->workqueue = NULL;
  2709. sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
  2710. out_free_irq:
  2711. free_irq(priv->pci_dev->irq, priv);
  2712. iwl_free_isr_ict(priv);
  2713. out_disable_msi:
  2714. pci_disable_msi(priv->pci_dev);
  2715. iwl_uninit_drv(priv);
  2716. out_free_eeprom:
  2717. iwl_eeprom_free(priv);
  2718. out_iounmap:
  2719. pci_iounmap(pdev, priv->hw_base);
  2720. out_pci_release_regions:
  2721. pci_set_drvdata(pdev, NULL);
  2722. pci_release_regions(pdev);
  2723. out_pci_disable_device:
  2724. pci_disable_device(pdev);
  2725. out_ieee80211_free_hw:
  2726. iwl_free_traffic_mem(priv);
  2727. ieee80211_free_hw(priv->hw);
  2728. out:
  2729. return err;
  2730. }
  2731. static void __devexit iwl_pci_remove(struct pci_dev *pdev)
  2732. {
  2733. struct iwl_priv *priv = pci_get_drvdata(pdev);
  2734. unsigned long flags;
  2735. if (!priv)
  2736. return;
  2737. IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
  2738. iwl_dbgfs_unregister(priv);
  2739. sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
  2740. /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
  2741. * to be called and iwl_down since we are removing the device
  2742. * we need to set STATUS_EXIT_PENDING bit.
  2743. */
  2744. set_bit(STATUS_EXIT_PENDING, &priv->status);
  2745. if (priv->mac80211_registered) {
  2746. ieee80211_unregister_hw(priv->hw);
  2747. priv->mac80211_registered = 0;
  2748. } else {
  2749. iwl_down(priv);
  2750. }
  2751. /*
  2752. * Make sure device is reset to low power before unloading driver.
  2753. * This may be redundant with iwl_down(), but there are paths to
  2754. * run iwl_down() without calling apm_ops.stop(), and there are
  2755. * paths to avoid running iwl_down() at all before leaving driver.
  2756. * This (inexpensive) call *makes sure* device is reset.
  2757. */
  2758. priv->cfg->ops->lib->apm_ops.stop(priv);
  2759. iwl_tt_exit(priv);
  2760. /* make sure we flush any pending irq or
  2761. * tasklet for the driver
  2762. */
  2763. spin_lock_irqsave(&priv->lock, flags);
  2764. iwl_disable_interrupts(priv);
  2765. spin_unlock_irqrestore(&priv->lock, flags);
  2766. iwl_synchronize_irq(priv);
  2767. iwl_dealloc_ucode_pci(priv);
  2768. if (priv->rxq.bd)
  2769. iwl_rx_queue_free(priv, &priv->rxq);
  2770. iwl_hw_txq_ctx_free(priv);
  2771. iwl_clear_stations_table(priv);
  2772. iwl_eeprom_free(priv);
  2773. /*netif_stop_queue(dev); */
  2774. flush_workqueue(priv->workqueue);
  2775. /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
  2776. * priv->workqueue... so we can't take down the workqueue
  2777. * until now... */
  2778. destroy_workqueue(priv->workqueue);
  2779. priv->workqueue = NULL;
  2780. iwl_free_traffic_mem(priv);
  2781. free_irq(priv->pci_dev->irq, priv);
  2782. pci_disable_msi(priv->pci_dev);
  2783. pci_iounmap(pdev, priv->hw_base);
  2784. pci_release_regions(pdev);
  2785. pci_disable_device(pdev);
  2786. pci_set_drvdata(pdev, NULL);
  2787. iwl_uninit_drv(priv);
  2788. iwl_free_isr_ict(priv);
  2789. if (priv->ibss_beacon)
  2790. dev_kfree_skb(priv->ibss_beacon);
  2791. ieee80211_free_hw(priv->hw);
  2792. }
  2793. /*****************************************************************************
  2794. *
  2795. * driver and module entry point
  2796. *
  2797. *****************************************************************************/
  2798. /* Hardware specific file defines the PCI IDs table for that hardware module */
  2799. static struct pci_device_id iwl_hw_card_ids[] = {
  2800. #ifdef CONFIG_IWL4965
  2801. {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
  2802. {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
  2803. #endif /* CONFIG_IWL4965 */
  2804. #ifdef CONFIG_IWL5000
  2805. {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bg_cfg)},
  2806. {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bg_cfg)},
  2807. {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)},
  2808. {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)},
  2809. {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)},
  2810. {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)},
  2811. {IWL_PCI_DEVICE(0x4232, PCI_ANY_ID, iwl5100_agn_cfg)},
  2812. {IWL_PCI_DEVICE(0x4235, PCI_ANY_ID, iwl5300_agn_cfg)},
  2813. {IWL_PCI_DEVICE(0x4236, PCI_ANY_ID, iwl5300_agn_cfg)},
  2814. {IWL_PCI_DEVICE(0x4237, PCI_ANY_ID, iwl5100_agn_cfg)},
  2815. /* 5350 WiFi/WiMax */
  2816. {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)},
  2817. {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)},
  2818. {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)},
  2819. /* 5150 Wifi/WiMax */
  2820. {IWL_PCI_DEVICE(0x423C, PCI_ANY_ID, iwl5150_agn_cfg)},
  2821. {IWL_PCI_DEVICE(0x423D, PCI_ANY_ID, iwl5150_agn_cfg)},
  2822. /* 6x00 Series */
  2823. {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
  2824. {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
  2825. {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
  2826. {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
  2827. {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
  2828. {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
  2829. {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
  2830. {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
  2831. {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
  2832. {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
  2833. /* 6x50 WiFi/WiMax Series */
  2834. {IWL_PCI_DEVICE(0x0086, 0x1101, iwl6050_3agn_cfg)},
  2835. {IWL_PCI_DEVICE(0x0086, 0x1121, iwl6050_3agn_cfg)},
  2836. {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
  2837. {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
  2838. {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
  2839. {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
  2840. {IWL_PCI_DEVICE(0x0088, 0x1111, iwl6050_3agn_cfg)},
  2841. {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
  2842. {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
  2843. /* 1000 Series WiFi */
  2844. {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
  2845. {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
  2846. {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
  2847. {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
  2848. {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
  2849. {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
  2850. {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
  2851. {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
  2852. {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
  2853. {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
  2854. {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
  2855. {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
  2856. #endif /* CONFIG_IWL5000 */
  2857. {0}
  2858. };
  2859. MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
  2860. static struct pci_driver iwl_driver = {
  2861. .name = DRV_NAME,
  2862. .id_table = iwl_hw_card_ids,
  2863. .probe = iwl_pci_probe,
  2864. .remove = __devexit_p(iwl_pci_remove),
  2865. #ifdef CONFIG_PM
  2866. .suspend = iwl_pci_suspend,
  2867. .resume = iwl_pci_resume,
  2868. #endif
  2869. };
  2870. static int __init iwl_init(void)
  2871. {
  2872. int ret;
  2873. printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
  2874. printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
  2875. ret = iwlagn_rate_control_register();
  2876. if (ret) {
  2877. printk(KERN_ERR DRV_NAME
  2878. "Unable to register rate control algorithm: %d\n", ret);
  2879. return ret;
  2880. }
  2881. ret = pci_register_driver(&iwl_driver);
  2882. if (ret) {
  2883. printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
  2884. goto error_register;
  2885. }
  2886. return ret;
  2887. error_register:
  2888. iwlagn_rate_control_unregister();
  2889. return ret;
  2890. }
  2891. static void __exit iwl_exit(void)
  2892. {
  2893. pci_unregister_driver(&iwl_driver);
  2894. iwlagn_rate_control_unregister();
  2895. }
  2896. module_exit(iwl_exit);
  2897. module_init(iwl_init);
  2898. #ifdef CONFIG_IWLWIFI_DEBUG
  2899. module_param_named(debug50, iwl_debug_level, uint, S_IRUGO);
  2900. MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
  2901. module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
  2902. MODULE_PARM_DESC(debug, "debug output mask");
  2903. #endif