fimc-lite.c 43 KB

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  1. /*
  2. * Samsung EXYNOS FIMC-LITE (camera host interface) driver
  3. *
  4. * Copyright (C) 2012 Samsung Electronics Co., Ltd.
  5. * Sylwester Nawrocki <s.nawrocki@samsung.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. */
  11. #define pr_fmt(fmt) "%s:%d " fmt, __func__, __LINE__
  12. #include <linux/bug.h>
  13. #include <linux/device.h>
  14. #include <linux/errno.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/kernel.h>
  17. #include <linux/list.h>
  18. #include <linux/module.h>
  19. #include <linux/types.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/pm_runtime.h>
  22. #include <linux/slab.h>
  23. #include <linux/videodev2.h>
  24. #include <media/v4l2-device.h>
  25. #include <media/v4l2-ioctl.h>
  26. #include <media/v4l2-mem2mem.h>
  27. #include <media/videobuf2-core.h>
  28. #include <media/videobuf2-dma-contig.h>
  29. #include <media/s5p_fimc.h>
  30. #include "fimc-mdevice.h"
  31. #include "fimc-core.h"
  32. #include "fimc-lite.h"
  33. #include "fimc-lite-reg.h"
  34. static int debug;
  35. module_param(debug, int, 0644);
  36. static const struct fimc_fmt fimc_lite_formats[] = {
  37. {
  38. .name = "YUV 4:2:2 packed, YCbYCr",
  39. .fourcc = V4L2_PIX_FMT_YUYV,
  40. .depth = { 16 },
  41. .color = FIMC_FMT_YCBYCR422,
  42. .memplanes = 1,
  43. .mbus_code = V4L2_MBUS_FMT_YUYV8_2X8,
  44. }, {
  45. .name = "YUV 4:2:2 packed, CbYCrY",
  46. .fourcc = V4L2_PIX_FMT_UYVY,
  47. .depth = { 16 },
  48. .color = FIMC_FMT_CBYCRY422,
  49. .memplanes = 1,
  50. .mbus_code = V4L2_MBUS_FMT_UYVY8_2X8,
  51. }, {
  52. .name = "YUV 4:2:2 packed, CrYCbY",
  53. .fourcc = V4L2_PIX_FMT_VYUY,
  54. .depth = { 16 },
  55. .color = FIMC_FMT_CRYCBY422,
  56. .memplanes = 1,
  57. .mbus_code = V4L2_MBUS_FMT_VYUY8_2X8,
  58. }, {
  59. .name = "YUV 4:2:2 packed, YCrYCb",
  60. .fourcc = V4L2_PIX_FMT_YVYU,
  61. .depth = { 16 },
  62. .color = FIMC_FMT_YCRYCB422,
  63. .memplanes = 1,
  64. .mbus_code = V4L2_MBUS_FMT_YVYU8_2X8,
  65. }, {
  66. .name = "RAW8 (GRBG)",
  67. .fourcc = V4L2_PIX_FMT_SGRBG8,
  68. .depth = { 8 },
  69. .color = FIMC_FMT_RAW8,
  70. .memplanes = 1,
  71. .mbus_code = V4L2_MBUS_FMT_SGRBG8_1X8,
  72. }, {
  73. .name = "RAW10 (GRBG)",
  74. .fourcc = V4L2_PIX_FMT_SGRBG10,
  75. .depth = { 10 },
  76. .color = FIMC_FMT_RAW10,
  77. .memplanes = 1,
  78. .mbus_code = V4L2_MBUS_FMT_SGRBG10_1X10,
  79. }, {
  80. .name = "RAW12 (GRBG)",
  81. .fourcc = V4L2_PIX_FMT_SGRBG12,
  82. .depth = { 12 },
  83. .color = FIMC_FMT_RAW12,
  84. .memplanes = 1,
  85. .mbus_code = V4L2_MBUS_FMT_SGRBG12_1X12,
  86. },
  87. };
  88. /**
  89. * fimc_lite_find_format - lookup fimc color format by fourcc or media bus code
  90. * @pixelformat: fourcc to match, ignored if null
  91. * @mbus_code: media bus code to match, ignored if null
  92. * @index: index to the fimc_lite_formats array, ignored if negative
  93. */
  94. static const struct fimc_fmt *fimc_lite_find_format(const u32 *pixelformat,
  95. const u32 *mbus_code, int index)
  96. {
  97. const struct fimc_fmt *fmt, *def_fmt = NULL;
  98. unsigned int i;
  99. int id = 0;
  100. if (index >= (int)ARRAY_SIZE(fimc_lite_formats))
  101. return NULL;
  102. for (i = 0; i < ARRAY_SIZE(fimc_lite_formats); ++i) {
  103. fmt = &fimc_lite_formats[i];
  104. if (pixelformat && fmt->fourcc == *pixelformat)
  105. return fmt;
  106. if (mbus_code && fmt->mbus_code == *mbus_code)
  107. return fmt;
  108. if (index == id)
  109. def_fmt = fmt;
  110. id++;
  111. }
  112. return def_fmt;
  113. }
  114. static int fimc_lite_hw_init(struct fimc_lite *fimc, bool isp_output)
  115. {
  116. struct fimc_pipeline *pipeline = &fimc->pipeline;
  117. struct v4l2_subdev *sensor;
  118. struct fimc_sensor_info *si;
  119. unsigned long flags;
  120. sensor = isp_output ? fimc->sensor : pipeline->subdevs[IDX_SENSOR];
  121. if (sensor == NULL)
  122. return -ENXIO;
  123. if (fimc->fmt == NULL)
  124. return -EINVAL;
  125. /* Get sensor configuration data from the sensor subdev */
  126. si = v4l2_get_subdev_hostdata(sensor);
  127. spin_lock_irqsave(&fimc->slock, flags);
  128. flite_hw_set_camera_bus(fimc, &si->pdata);
  129. flite_hw_set_source_format(fimc, &fimc->inp_frame);
  130. flite_hw_set_window_offset(fimc, &fimc->inp_frame);
  131. flite_hw_set_output_dma(fimc, &fimc->out_frame, !isp_output);
  132. flite_hw_set_interrupt_mask(fimc);
  133. flite_hw_set_test_pattern(fimc, fimc->test_pattern->val);
  134. if (debug > 0)
  135. flite_hw_dump_regs(fimc, __func__);
  136. spin_unlock_irqrestore(&fimc->slock, flags);
  137. return 0;
  138. }
  139. /*
  140. * Reinitialize the driver so it is ready to start the streaming again.
  141. * Set fimc->state to indicate stream off and the hardware shut down state.
  142. * If not suspending (@suspend is false), return any buffers to videobuf2.
  143. * Otherwise put any owned buffers onto the pending buffers queue, so they
  144. * can be re-spun when the device is being resumed. Also perform FIMC
  145. * software reset and disable streaming on the whole pipeline if required.
  146. */
  147. static int fimc_lite_reinit(struct fimc_lite *fimc, bool suspend)
  148. {
  149. struct flite_buffer *buf;
  150. unsigned long flags;
  151. bool streaming;
  152. spin_lock_irqsave(&fimc->slock, flags);
  153. streaming = fimc->state & (1 << ST_SENSOR_STREAM);
  154. fimc->state &= ~(1 << ST_FLITE_RUN | 1 << ST_FLITE_OFF |
  155. 1 << ST_FLITE_STREAM | 1 << ST_SENSOR_STREAM);
  156. if (suspend)
  157. fimc->state |= (1 << ST_FLITE_SUSPENDED);
  158. else
  159. fimc->state &= ~(1 << ST_FLITE_PENDING |
  160. 1 << ST_FLITE_SUSPENDED);
  161. /* Release unused buffers */
  162. while (!suspend && !list_empty(&fimc->pending_buf_q)) {
  163. buf = fimc_lite_pending_queue_pop(fimc);
  164. vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR);
  165. }
  166. /* If suspending put unused buffers onto pending queue */
  167. while (!list_empty(&fimc->active_buf_q)) {
  168. buf = fimc_lite_active_queue_pop(fimc);
  169. if (suspend)
  170. fimc_lite_pending_queue_add(fimc, buf);
  171. else
  172. vb2_buffer_done(&buf->vb, VB2_BUF_STATE_ERROR);
  173. }
  174. spin_unlock_irqrestore(&fimc->slock, flags);
  175. flite_hw_reset(fimc);
  176. if (!streaming)
  177. return 0;
  178. return fimc_pipeline_call(fimc, set_stream, &fimc->pipeline, 0);
  179. }
  180. static int fimc_lite_stop_capture(struct fimc_lite *fimc, bool suspend)
  181. {
  182. unsigned long flags;
  183. if (!fimc_lite_active(fimc))
  184. return 0;
  185. spin_lock_irqsave(&fimc->slock, flags);
  186. set_bit(ST_FLITE_OFF, &fimc->state);
  187. flite_hw_capture_stop(fimc);
  188. spin_unlock_irqrestore(&fimc->slock, flags);
  189. wait_event_timeout(fimc->irq_queue,
  190. !test_bit(ST_FLITE_OFF, &fimc->state),
  191. (2*HZ/10)); /* 200 ms */
  192. return fimc_lite_reinit(fimc, suspend);
  193. }
  194. /* Must be called with fimc.slock spinlock held. */
  195. static void fimc_lite_config_update(struct fimc_lite *fimc)
  196. {
  197. flite_hw_set_window_offset(fimc, &fimc->inp_frame);
  198. flite_hw_set_dma_window(fimc, &fimc->out_frame);
  199. flite_hw_set_test_pattern(fimc, fimc->test_pattern->val);
  200. clear_bit(ST_FLITE_CONFIG, &fimc->state);
  201. }
  202. static irqreturn_t flite_irq_handler(int irq, void *priv)
  203. {
  204. struct fimc_lite *fimc = priv;
  205. struct flite_buffer *vbuf;
  206. unsigned long flags;
  207. struct timeval *tv;
  208. struct timespec ts;
  209. u32 intsrc;
  210. spin_lock_irqsave(&fimc->slock, flags);
  211. intsrc = flite_hw_get_interrupt_source(fimc);
  212. flite_hw_clear_pending_irq(fimc);
  213. if (test_and_clear_bit(ST_FLITE_OFF, &fimc->state)) {
  214. wake_up(&fimc->irq_queue);
  215. goto done;
  216. }
  217. if (intsrc & FLITE_REG_CISTATUS_IRQ_SRC_OVERFLOW) {
  218. clear_bit(ST_FLITE_RUN, &fimc->state);
  219. fimc->events.data_overflow++;
  220. }
  221. if (intsrc & FLITE_REG_CISTATUS_IRQ_SRC_LASTCAPEND) {
  222. flite_hw_clear_last_capture_end(fimc);
  223. clear_bit(ST_FLITE_STREAM, &fimc->state);
  224. wake_up(&fimc->irq_queue);
  225. }
  226. if (fimc->out_path != FIMC_IO_DMA)
  227. goto done;
  228. if ((intsrc & FLITE_REG_CISTATUS_IRQ_SRC_FRMSTART) &&
  229. test_bit(ST_FLITE_RUN, &fimc->state) &&
  230. !list_empty(&fimc->active_buf_q) &&
  231. !list_empty(&fimc->pending_buf_q)) {
  232. vbuf = fimc_lite_active_queue_pop(fimc);
  233. ktime_get_ts(&ts);
  234. tv = &vbuf->vb.v4l2_buf.timestamp;
  235. tv->tv_sec = ts.tv_sec;
  236. tv->tv_usec = ts.tv_nsec / NSEC_PER_USEC;
  237. vbuf->vb.v4l2_buf.sequence = fimc->frame_count++;
  238. vb2_buffer_done(&vbuf->vb, VB2_BUF_STATE_DONE);
  239. vbuf = fimc_lite_pending_queue_pop(fimc);
  240. flite_hw_set_output_addr(fimc, vbuf->paddr);
  241. fimc_lite_active_queue_add(fimc, vbuf);
  242. }
  243. if (test_bit(ST_FLITE_CONFIG, &fimc->state))
  244. fimc_lite_config_update(fimc);
  245. if (list_empty(&fimc->pending_buf_q)) {
  246. flite_hw_capture_stop(fimc);
  247. clear_bit(ST_FLITE_STREAM, &fimc->state);
  248. }
  249. done:
  250. set_bit(ST_FLITE_RUN, &fimc->state);
  251. spin_unlock_irqrestore(&fimc->slock, flags);
  252. return IRQ_HANDLED;
  253. }
  254. static int start_streaming(struct vb2_queue *q, unsigned int count)
  255. {
  256. struct fimc_lite *fimc = q->drv_priv;
  257. int ret;
  258. fimc->frame_count = 0;
  259. ret = fimc_lite_hw_init(fimc, false);
  260. if (ret) {
  261. fimc_lite_reinit(fimc, false);
  262. return ret;
  263. }
  264. set_bit(ST_FLITE_PENDING, &fimc->state);
  265. if (!list_empty(&fimc->active_buf_q) &&
  266. !test_and_set_bit(ST_FLITE_STREAM, &fimc->state)) {
  267. flite_hw_capture_start(fimc);
  268. if (!test_and_set_bit(ST_SENSOR_STREAM, &fimc->state))
  269. fimc_pipeline_call(fimc, set_stream,
  270. &fimc->pipeline, 1);
  271. }
  272. if (debug > 0)
  273. flite_hw_dump_regs(fimc, __func__);
  274. return 0;
  275. }
  276. static int stop_streaming(struct vb2_queue *q)
  277. {
  278. struct fimc_lite *fimc = q->drv_priv;
  279. if (!fimc_lite_active(fimc))
  280. return -EINVAL;
  281. return fimc_lite_stop_capture(fimc, false);
  282. }
  283. static int queue_setup(struct vb2_queue *vq, const struct v4l2_format *pfmt,
  284. unsigned int *num_buffers, unsigned int *num_planes,
  285. unsigned int sizes[], void *allocators[])
  286. {
  287. const struct v4l2_pix_format_mplane *pixm = NULL;
  288. struct fimc_lite *fimc = vq->drv_priv;
  289. struct flite_frame *frame = &fimc->out_frame;
  290. const struct fimc_fmt *fmt = fimc->fmt;
  291. unsigned long wh;
  292. int i;
  293. if (pfmt) {
  294. pixm = &pfmt->fmt.pix_mp;
  295. fmt = fimc_lite_find_format(&pixm->pixelformat, NULL, -1);
  296. wh = pixm->width * pixm->height;
  297. } else {
  298. wh = frame->f_width * frame->f_height;
  299. }
  300. if (fmt == NULL)
  301. return -EINVAL;
  302. *num_planes = fmt->memplanes;
  303. for (i = 0; i < fmt->memplanes; i++) {
  304. unsigned int size = (wh * fmt->depth[i]) / 8;
  305. if (pixm)
  306. sizes[i] = max(size, pixm->plane_fmt[i].sizeimage);
  307. else
  308. sizes[i] = size;
  309. allocators[i] = fimc->alloc_ctx;
  310. }
  311. return 0;
  312. }
  313. static int buffer_prepare(struct vb2_buffer *vb)
  314. {
  315. struct vb2_queue *vq = vb->vb2_queue;
  316. struct fimc_lite *fimc = vq->drv_priv;
  317. int i;
  318. if (fimc->fmt == NULL)
  319. return -EINVAL;
  320. for (i = 0; i < fimc->fmt->memplanes; i++) {
  321. unsigned long size = fimc->payload[i];
  322. if (vb2_plane_size(vb, i) < size) {
  323. v4l2_err(&fimc->vfd,
  324. "User buffer too small (%ld < %ld)\n",
  325. vb2_plane_size(vb, i), size);
  326. return -EINVAL;
  327. }
  328. vb2_set_plane_payload(vb, i, size);
  329. }
  330. return 0;
  331. }
  332. static void buffer_queue(struct vb2_buffer *vb)
  333. {
  334. struct flite_buffer *buf
  335. = container_of(vb, struct flite_buffer, vb);
  336. struct fimc_lite *fimc = vb2_get_drv_priv(vb->vb2_queue);
  337. unsigned long flags;
  338. spin_lock_irqsave(&fimc->slock, flags);
  339. buf->paddr = vb2_dma_contig_plane_dma_addr(vb, 0);
  340. if (!test_bit(ST_FLITE_SUSPENDED, &fimc->state) &&
  341. !test_bit(ST_FLITE_STREAM, &fimc->state) &&
  342. list_empty(&fimc->active_buf_q)) {
  343. flite_hw_set_output_addr(fimc, buf->paddr);
  344. fimc_lite_active_queue_add(fimc, buf);
  345. } else {
  346. fimc_lite_pending_queue_add(fimc, buf);
  347. }
  348. if (vb2_is_streaming(&fimc->vb_queue) &&
  349. !list_empty(&fimc->pending_buf_q) &&
  350. !test_and_set_bit(ST_FLITE_STREAM, &fimc->state)) {
  351. flite_hw_capture_start(fimc);
  352. spin_unlock_irqrestore(&fimc->slock, flags);
  353. if (!test_and_set_bit(ST_SENSOR_STREAM, &fimc->state))
  354. fimc_pipeline_call(fimc, set_stream,
  355. &fimc->pipeline, 1);
  356. return;
  357. }
  358. spin_unlock_irqrestore(&fimc->slock, flags);
  359. }
  360. static void fimc_lock(struct vb2_queue *vq)
  361. {
  362. struct fimc_lite *fimc = vb2_get_drv_priv(vq);
  363. mutex_lock(&fimc->lock);
  364. }
  365. static void fimc_unlock(struct vb2_queue *vq)
  366. {
  367. struct fimc_lite *fimc = vb2_get_drv_priv(vq);
  368. mutex_unlock(&fimc->lock);
  369. }
  370. static const struct vb2_ops fimc_lite_qops = {
  371. .queue_setup = queue_setup,
  372. .buf_prepare = buffer_prepare,
  373. .buf_queue = buffer_queue,
  374. .wait_prepare = fimc_unlock,
  375. .wait_finish = fimc_lock,
  376. .start_streaming = start_streaming,
  377. .stop_streaming = stop_streaming,
  378. };
  379. static void fimc_lite_clear_event_counters(struct fimc_lite *fimc)
  380. {
  381. unsigned long flags;
  382. spin_lock_irqsave(&fimc->slock, flags);
  383. memset(&fimc->events, 0, sizeof(fimc->events));
  384. spin_unlock_irqrestore(&fimc->slock, flags);
  385. }
  386. static int fimc_lite_open(struct file *file)
  387. {
  388. struct fimc_lite *fimc = video_drvdata(file);
  389. struct media_entity *me = &fimc->vfd.entity;
  390. int ret;
  391. mutex_lock(&me->parent->graph_mutex);
  392. mutex_lock(&fimc->lock);
  393. if (fimc->out_path != FIMC_IO_DMA) {
  394. ret = -EBUSY;
  395. goto done;
  396. }
  397. set_bit(ST_FLITE_IN_USE, &fimc->state);
  398. ret = pm_runtime_get_sync(&fimc->pdev->dev);
  399. if (ret < 0)
  400. goto done;
  401. ret = v4l2_fh_open(file);
  402. if (ret < 0)
  403. goto done;
  404. if (++fimc->ref_count == 1 && fimc->out_path == FIMC_IO_DMA) {
  405. ret = fimc_pipeline_call(fimc, open, &fimc->pipeline,
  406. &fimc->vfd.entity, true);
  407. if (ret < 0) {
  408. pm_runtime_put_sync(&fimc->pdev->dev);
  409. fimc->ref_count--;
  410. v4l2_fh_release(file);
  411. clear_bit(ST_FLITE_IN_USE, &fimc->state);
  412. }
  413. fimc_lite_clear_event_counters(fimc);
  414. }
  415. done:
  416. mutex_unlock(&fimc->lock);
  417. mutex_unlock(&me->parent->graph_mutex);
  418. return ret;
  419. }
  420. static int fimc_lite_close(struct file *file)
  421. {
  422. struct fimc_lite *fimc = video_drvdata(file);
  423. int ret;
  424. mutex_lock(&fimc->lock);
  425. if (--fimc->ref_count == 0 && fimc->out_path == FIMC_IO_DMA) {
  426. clear_bit(ST_FLITE_IN_USE, &fimc->state);
  427. fimc_lite_stop_capture(fimc, false);
  428. fimc_pipeline_call(fimc, close, &fimc->pipeline);
  429. clear_bit(ST_FLITE_SUSPENDED, &fimc->state);
  430. }
  431. pm_runtime_put(&fimc->pdev->dev);
  432. if (fimc->ref_count == 0)
  433. vb2_queue_release(&fimc->vb_queue);
  434. ret = v4l2_fh_release(file);
  435. mutex_unlock(&fimc->lock);
  436. return ret;
  437. }
  438. static unsigned int fimc_lite_poll(struct file *file,
  439. struct poll_table_struct *wait)
  440. {
  441. struct fimc_lite *fimc = video_drvdata(file);
  442. int ret;
  443. if (mutex_lock_interruptible(&fimc->lock))
  444. return POLL_ERR;
  445. ret = vb2_poll(&fimc->vb_queue, file, wait);
  446. mutex_unlock(&fimc->lock);
  447. return ret;
  448. }
  449. static int fimc_lite_mmap(struct file *file, struct vm_area_struct *vma)
  450. {
  451. struct fimc_lite *fimc = video_drvdata(file);
  452. int ret;
  453. if (mutex_lock_interruptible(&fimc->lock))
  454. return -ERESTARTSYS;
  455. ret = vb2_mmap(&fimc->vb_queue, vma);
  456. mutex_unlock(&fimc->lock);
  457. return ret;
  458. }
  459. static const struct v4l2_file_operations fimc_lite_fops = {
  460. .owner = THIS_MODULE,
  461. .open = fimc_lite_open,
  462. .release = fimc_lite_close,
  463. .poll = fimc_lite_poll,
  464. .unlocked_ioctl = video_ioctl2,
  465. .mmap = fimc_lite_mmap,
  466. };
  467. /*
  468. * Format and crop negotiation helpers
  469. */
  470. static const struct fimc_fmt *fimc_lite_try_format(struct fimc_lite *fimc,
  471. u32 *width, u32 *height,
  472. u32 *code, u32 *fourcc, int pad)
  473. {
  474. struct flite_variant *variant = fimc->variant;
  475. const struct fimc_fmt *fmt;
  476. fmt = fimc_lite_find_format(fourcc, code, 0);
  477. if (WARN_ON(!fmt))
  478. return NULL;
  479. if (code)
  480. *code = fmt->mbus_code;
  481. if (fourcc)
  482. *fourcc = fmt->fourcc;
  483. if (pad == FLITE_SD_PAD_SINK) {
  484. v4l_bound_align_image(width, 8, variant->max_width,
  485. ffs(variant->out_width_align) - 1,
  486. height, 0, variant->max_height, 0, 0);
  487. } else {
  488. v4l_bound_align_image(width, 8, fimc->inp_frame.rect.width,
  489. ffs(variant->out_width_align) - 1,
  490. height, 0, fimc->inp_frame.rect.height,
  491. 0, 0);
  492. }
  493. v4l2_dbg(1, debug, &fimc->subdev, "code: 0x%x, %dx%d\n",
  494. code ? *code : 0, *width, *height);
  495. return fmt;
  496. }
  497. static void fimc_lite_try_crop(struct fimc_lite *fimc, struct v4l2_rect *r)
  498. {
  499. struct flite_frame *frame = &fimc->inp_frame;
  500. v4l_bound_align_image(&r->width, 0, frame->f_width, 0,
  501. &r->height, 0, frame->f_height, 0, 0);
  502. /* Adjust left/top if cropping rectangle got out of bounds */
  503. r->left = clamp_t(u32, r->left, 0, frame->f_width - r->width);
  504. r->left = round_down(r->left, fimc->variant->win_hor_offs_align);
  505. r->top = clamp_t(u32, r->top, 0, frame->f_height - r->height);
  506. v4l2_dbg(1, debug, &fimc->subdev, "(%d,%d)/%dx%d, sink fmt: %dx%d",
  507. r->left, r->top, r->width, r->height,
  508. frame->f_width, frame->f_height);
  509. }
  510. static void fimc_lite_try_compose(struct fimc_lite *fimc, struct v4l2_rect *r)
  511. {
  512. struct flite_frame *frame = &fimc->out_frame;
  513. struct v4l2_rect *crop_rect = &fimc->inp_frame.rect;
  514. /* Scaling is not supported so we enforce compose rectangle size
  515. same as size of the sink crop rectangle. */
  516. r->width = crop_rect->width;
  517. r->height = crop_rect->height;
  518. /* Adjust left/top if the composing rectangle got out of bounds */
  519. r->left = clamp_t(u32, r->left, 0, frame->f_width - r->width);
  520. r->left = round_down(r->left, fimc->variant->out_hor_offs_align);
  521. r->top = clamp_t(u32, r->top, 0, fimc->out_frame.f_height - r->height);
  522. v4l2_dbg(1, debug, &fimc->subdev, "(%d,%d)/%dx%d, source fmt: %dx%d",
  523. r->left, r->top, r->width, r->height,
  524. frame->f_width, frame->f_height);
  525. }
  526. /*
  527. * Video node ioctl operations
  528. */
  529. static int fimc_vidioc_querycap_capture(struct file *file, void *priv,
  530. struct v4l2_capability *cap)
  531. {
  532. strlcpy(cap->driver, FIMC_LITE_DRV_NAME, sizeof(cap->driver));
  533. cap->bus_info[0] = 0;
  534. cap->card[0] = 0;
  535. cap->capabilities = V4L2_CAP_STREAMING;
  536. return 0;
  537. }
  538. static int fimc_lite_enum_fmt_mplane(struct file *file, void *priv,
  539. struct v4l2_fmtdesc *f)
  540. {
  541. const struct fimc_fmt *fmt;
  542. if (f->index >= ARRAY_SIZE(fimc_lite_formats))
  543. return -EINVAL;
  544. fmt = &fimc_lite_formats[f->index];
  545. strlcpy(f->description, fmt->name, sizeof(f->description));
  546. f->pixelformat = fmt->fourcc;
  547. return 0;
  548. }
  549. static int fimc_lite_g_fmt_mplane(struct file *file, void *fh,
  550. struct v4l2_format *f)
  551. {
  552. struct fimc_lite *fimc = video_drvdata(file);
  553. struct v4l2_pix_format_mplane *pixm = &f->fmt.pix_mp;
  554. struct v4l2_plane_pix_format *plane_fmt = &pixm->plane_fmt[0];
  555. struct flite_frame *frame = &fimc->out_frame;
  556. const struct fimc_fmt *fmt = fimc->fmt;
  557. plane_fmt->bytesperline = (frame->f_width * fmt->depth[0]) / 8;
  558. plane_fmt->sizeimage = plane_fmt->bytesperline * frame->f_height;
  559. pixm->num_planes = fmt->memplanes;
  560. pixm->pixelformat = fmt->fourcc;
  561. pixm->width = frame->f_width;
  562. pixm->height = frame->f_height;
  563. pixm->field = V4L2_FIELD_NONE;
  564. pixm->colorspace = V4L2_COLORSPACE_JPEG;
  565. return 0;
  566. }
  567. static int fimc_lite_try_fmt(struct fimc_lite *fimc,
  568. struct v4l2_pix_format_mplane *pixm,
  569. const struct fimc_fmt **ffmt)
  570. {
  571. struct flite_variant *variant = fimc->variant;
  572. u32 bpl = pixm->plane_fmt[0].bytesperline;
  573. const struct fimc_fmt *fmt;
  574. fmt = fimc_lite_find_format(&pixm->pixelformat, NULL, 0);
  575. if (WARN_ON(fmt == NULL))
  576. return -EINVAL;
  577. if (ffmt)
  578. *ffmt = fmt;
  579. v4l_bound_align_image(&pixm->width, 8, variant->max_width,
  580. ffs(variant->out_width_align) - 1,
  581. &pixm->height, 0, variant->max_height, 0, 0);
  582. if ((bpl == 0 || ((bpl * 8) / fmt->depth[0]) < pixm->width))
  583. pixm->plane_fmt[0].bytesperline = (pixm->width *
  584. fmt->depth[0]) / 8;
  585. if (pixm->plane_fmt[0].sizeimage == 0)
  586. pixm->plane_fmt[0].sizeimage = (pixm->width * pixm->height *
  587. fmt->depth[0]) / 8;
  588. pixm->num_planes = fmt->memplanes;
  589. pixm->pixelformat = fmt->fourcc;
  590. pixm->colorspace = V4L2_COLORSPACE_JPEG;
  591. pixm->field = V4L2_FIELD_NONE;
  592. return 0;
  593. }
  594. static int fimc_lite_try_fmt_mplane(struct file *file, void *fh,
  595. struct v4l2_format *f)
  596. {
  597. struct fimc_lite *fimc = video_drvdata(file);
  598. return fimc_lite_try_fmt(fimc, &f->fmt.pix_mp, NULL);
  599. }
  600. static int fimc_lite_s_fmt_mplane(struct file *file, void *priv,
  601. struct v4l2_format *f)
  602. {
  603. struct v4l2_pix_format_mplane *pixm = &f->fmt.pix_mp;
  604. struct fimc_lite *fimc = video_drvdata(file);
  605. struct flite_frame *frame = &fimc->out_frame;
  606. const struct fimc_fmt *fmt = NULL;
  607. int ret;
  608. if (vb2_is_busy(&fimc->vb_queue))
  609. return -EBUSY;
  610. ret = fimc_lite_try_fmt(fimc, &f->fmt.pix_mp, &fmt);
  611. if (ret < 0)
  612. return ret;
  613. fimc->fmt = fmt;
  614. fimc->payload[0] = max((pixm->width * pixm->height * fmt->depth[0]) / 8,
  615. pixm->plane_fmt[0].sizeimage);
  616. frame->f_width = pixm->width;
  617. frame->f_height = pixm->height;
  618. return 0;
  619. }
  620. static int fimc_pipeline_validate(struct fimc_lite *fimc)
  621. {
  622. struct v4l2_subdev *sd = &fimc->subdev;
  623. struct v4l2_subdev_format sink_fmt, src_fmt;
  624. struct media_pad *pad;
  625. int ret;
  626. while (1) {
  627. /* Retrieve format at the sink pad */
  628. pad = &sd->entity.pads[0];
  629. if (!(pad->flags & MEDIA_PAD_FL_SINK))
  630. break;
  631. /* Don't call FIMC subdev operation to avoid nested locking */
  632. if (sd == &fimc->subdev) {
  633. struct flite_frame *ff = &fimc->out_frame;
  634. sink_fmt.format.width = ff->f_width;
  635. sink_fmt.format.height = ff->f_height;
  636. sink_fmt.format.code = fimc->fmt->mbus_code;
  637. } else {
  638. sink_fmt.pad = pad->index;
  639. sink_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
  640. ret = v4l2_subdev_call(sd, pad, get_fmt, NULL,
  641. &sink_fmt);
  642. if (ret < 0 && ret != -ENOIOCTLCMD)
  643. return -EPIPE;
  644. }
  645. /* Retrieve format at the source pad */
  646. pad = media_entity_remote_source(pad);
  647. if (pad == NULL ||
  648. media_entity_type(pad->entity) != MEDIA_ENT_T_V4L2_SUBDEV)
  649. break;
  650. sd = media_entity_to_v4l2_subdev(pad->entity);
  651. src_fmt.pad = pad->index;
  652. src_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
  653. ret = v4l2_subdev_call(sd, pad, get_fmt, NULL, &src_fmt);
  654. if (ret < 0 && ret != -ENOIOCTLCMD)
  655. return -EPIPE;
  656. if (src_fmt.format.width != sink_fmt.format.width ||
  657. src_fmt.format.height != sink_fmt.format.height ||
  658. src_fmt.format.code != sink_fmt.format.code)
  659. return -EPIPE;
  660. }
  661. return 0;
  662. }
  663. static int fimc_lite_streamon(struct file *file, void *priv,
  664. enum v4l2_buf_type type)
  665. {
  666. struct fimc_lite *fimc = video_drvdata(file);
  667. struct v4l2_subdev *sensor = fimc->pipeline.subdevs[IDX_SENSOR];
  668. struct fimc_pipeline *p = &fimc->pipeline;
  669. int ret;
  670. if (fimc_lite_active(fimc))
  671. return -EBUSY;
  672. ret = media_entity_pipeline_start(&sensor->entity, p->m_pipeline);
  673. if (ret < 0)
  674. return ret;
  675. ret = fimc_pipeline_validate(fimc);
  676. if (ret) {
  677. media_entity_pipeline_stop(&sensor->entity);
  678. return ret;
  679. }
  680. return vb2_streamon(&fimc->vb_queue, type);
  681. }
  682. static int fimc_lite_streamoff(struct file *file, void *priv,
  683. enum v4l2_buf_type type)
  684. {
  685. struct fimc_lite *fimc = video_drvdata(file);
  686. struct v4l2_subdev *sd = fimc->pipeline.subdevs[IDX_SENSOR];
  687. int ret;
  688. ret = vb2_streamoff(&fimc->vb_queue, type);
  689. if (ret == 0)
  690. media_entity_pipeline_stop(&sd->entity);
  691. return ret;
  692. }
  693. static int fimc_lite_reqbufs(struct file *file, void *priv,
  694. struct v4l2_requestbuffers *reqbufs)
  695. {
  696. struct fimc_lite *fimc = video_drvdata(file);
  697. int ret;
  698. reqbufs->count = max_t(u32, FLITE_REQ_BUFS_MIN, reqbufs->count);
  699. ret = vb2_reqbufs(&fimc->vb_queue, reqbufs);
  700. if (!ret)
  701. fimc->reqbufs_count = reqbufs->count;
  702. return ret;
  703. }
  704. static int fimc_lite_querybuf(struct file *file, void *priv,
  705. struct v4l2_buffer *buf)
  706. {
  707. struct fimc_lite *fimc = video_drvdata(file);
  708. return vb2_querybuf(&fimc->vb_queue, buf);
  709. }
  710. static int fimc_lite_qbuf(struct file *file, void *priv,
  711. struct v4l2_buffer *buf)
  712. {
  713. struct fimc_lite *fimc = video_drvdata(file);
  714. return vb2_qbuf(&fimc->vb_queue, buf);
  715. }
  716. static int fimc_lite_dqbuf(struct file *file, void *priv,
  717. struct v4l2_buffer *buf)
  718. {
  719. struct fimc_lite *fimc = video_drvdata(file);
  720. return vb2_dqbuf(&fimc->vb_queue, buf, file->f_flags & O_NONBLOCK);
  721. }
  722. static int fimc_lite_create_bufs(struct file *file, void *priv,
  723. struct v4l2_create_buffers *create)
  724. {
  725. struct fimc_lite *fimc = video_drvdata(file);
  726. return vb2_create_bufs(&fimc->vb_queue, create);
  727. }
  728. static int fimc_lite_prepare_buf(struct file *file, void *priv,
  729. struct v4l2_buffer *b)
  730. {
  731. struct fimc_lite *fimc = video_drvdata(file);
  732. return vb2_prepare_buf(&fimc->vb_queue, b);
  733. }
  734. /* Return 1 if rectangle a is enclosed in rectangle b, or 0 otherwise. */
  735. static int enclosed_rectangle(struct v4l2_rect *a, struct v4l2_rect *b)
  736. {
  737. if (a->left < b->left || a->top < b->top)
  738. return 0;
  739. if (a->left + a->width > b->left + b->width)
  740. return 0;
  741. if (a->top + a->height > b->top + b->height)
  742. return 0;
  743. return 1;
  744. }
  745. static int fimc_lite_g_selection(struct file *file, void *fh,
  746. struct v4l2_selection *sel)
  747. {
  748. struct fimc_lite *fimc = video_drvdata(file);
  749. struct flite_frame *f = &fimc->out_frame;
  750. if (sel->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
  751. return -EINVAL;
  752. switch (sel->target) {
  753. case V4L2_SEL_TGT_COMPOSE_BOUNDS:
  754. case V4L2_SEL_TGT_COMPOSE_DEFAULT:
  755. sel->r.left = 0;
  756. sel->r.top = 0;
  757. sel->r.width = f->f_width;
  758. sel->r.height = f->f_height;
  759. return 0;
  760. case V4L2_SEL_TGT_COMPOSE:
  761. sel->r = f->rect;
  762. return 0;
  763. }
  764. return -EINVAL;
  765. }
  766. static int fimc_lite_s_selection(struct file *file, void *fh,
  767. struct v4l2_selection *sel)
  768. {
  769. struct fimc_lite *fimc = video_drvdata(file);
  770. struct flite_frame *f = &fimc->out_frame;
  771. struct v4l2_rect rect = sel->r;
  772. unsigned long flags;
  773. if (sel->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE ||
  774. sel->target != V4L2_SEL_TGT_COMPOSE)
  775. return -EINVAL;
  776. fimc_lite_try_compose(fimc, &rect);
  777. if ((sel->flags & V4L2_SEL_FLAG_LE) &&
  778. !enclosed_rectangle(&rect, &sel->r))
  779. return -ERANGE;
  780. if ((sel->flags & V4L2_SEL_FLAG_GE) &&
  781. !enclosed_rectangle(&sel->r, &rect))
  782. return -ERANGE;
  783. sel->r = rect;
  784. spin_lock_irqsave(&fimc->slock, flags);
  785. f->rect = rect;
  786. set_bit(ST_FLITE_CONFIG, &fimc->state);
  787. spin_unlock_irqrestore(&fimc->slock, flags);
  788. return 0;
  789. }
  790. static const struct v4l2_ioctl_ops fimc_lite_ioctl_ops = {
  791. .vidioc_querycap = fimc_vidioc_querycap_capture,
  792. .vidioc_enum_fmt_vid_cap_mplane = fimc_lite_enum_fmt_mplane,
  793. .vidioc_try_fmt_vid_cap_mplane = fimc_lite_try_fmt_mplane,
  794. .vidioc_s_fmt_vid_cap_mplane = fimc_lite_s_fmt_mplane,
  795. .vidioc_g_fmt_vid_cap_mplane = fimc_lite_g_fmt_mplane,
  796. .vidioc_g_selection = fimc_lite_g_selection,
  797. .vidioc_s_selection = fimc_lite_s_selection,
  798. .vidioc_reqbufs = fimc_lite_reqbufs,
  799. .vidioc_querybuf = fimc_lite_querybuf,
  800. .vidioc_prepare_buf = fimc_lite_prepare_buf,
  801. .vidioc_create_bufs = fimc_lite_create_bufs,
  802. .vidioc_qbuf = fimc_lite_qbuf,
  803. .vidioc_dqbuf = fimc_lite_dqbuf,
  804. .vidioc_streamon = fimc_lite_streamon,
  805. .vidioc_streamoff = fimc_lite_streamoff,
  806. };
  807. /* Called with the media graph mutex held */
  808. static struct v4l2_subdev *__find_remote_sensor(struct media_entity *me)
  809. {
  810. struct media_pad *pad = &me->pads[0];
  811. struct v4l2_subdev *sd;
  812. while (pad->flags & MEDIA_PAD_FL_SINK) {
  813. /* source pad */
  814. pad = media_entity_remote_source(pad);
  815. if (pad == NULL ||
  816. media_entity_type(pad->entity) != MEDIA_ENT_T_V4L2_SUBDEV)
  817. break;
  818. sd = media_entity_to_v4l2_subdev(pad->entity);
  819. if (sd->grp_id == GRP_ID_FIMC_IS_SENSOR)
  820. return sd;
  821. /* sink pad */
  822. pad = &sd->entity.pads[0];
  823. }
  824. return NULL;
  825. }
  826. /* Capture subdev media entity operations */
  827. static int fimc_lite_link_setup(struct media_entity *entity,
  828. const struct media_pad *local,
  829. const struct media_pad *remote, u32 flags)
  830. {
  831. struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
  832. struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
  833. unsigned int remote_ent_type = media_entity_type(remote->entity);
  834. int ret = 0;
  835. if (WARN_ON(fimc == NULL))
  836. return 0;
  837. v4l2_dbg(1, debug, sd, "%s: %s --> %s, flags: 0x%x. source_id: 0x%x",
  838. __func__, remote->entity->name, local->entity->name,
  839. flags, fimc->source_subdev_grp_id);
  840. mutex_lock(&fimc->lock);
  841. switch (local->index) {
  842. case FLITE_SD_PAD_SINK:
  843. if (remote_ent_type != MEDIA_ENT_T_V4L2_SUBDEV) {
  844. ret = -EINVAL;
  845. break;
  846. }
  847. if (flags & MEDIA_LNK_FL_ENABLED) {
  848. if (fimc->source_subdev_grp_id == 0)
  849. fimc->source_subdev_grp_id = sd->grp_id;
  850. else
  851. ret = -EBUSY;
  852. } else {
  853. fimc->source_subdev_grp_id = 0;
  854. fimc->sensor = NULL;
  855. }
  856. break;
  857. case FLITE_SD_PAD_SOURCE_DMA:
  858. if (!(flags & MEDIA_LNK_FL_ENABLED))
  859. fimc->out_path = FIMC_IO_NONE;
  860. else if (remote_ent_type == MEDIA_ENT_T_DEVNODE)
  861. fimc->out_path = FIMC_IO_DMA;
  862. else
  863. ret = -EINVAL;
  864. break;
  865. case FLITE_SD_PAD_SOURCE_ISP:
  866. if (!(flags & MEDIA_LNK_FL_ENABLED))
  867. fimc->out_path = FIMC_IO_NONE;
  868. else if (remote_ent_type == MEDIA_ENT_T_V4L2_SUBDEV)
  869. fimc->out_path = FIMC_IO_ISP;
  870. else
  871. ret = -EINVAL;
  872. break;
  873. default:
  874. v4l2_err(sd, "Invalid pad index\n");
  875. ret = -EINVAL;
  876. }
  877. mutex_unlock(&fimc->lock);
  878. return ret;
  879. }
  880. static const struct media_entity_operations fimc_lite_subdev_media_ops = {
  881. .link_setup = fimc_lite_link_setup,
  882. };
  883. static int fimc_lite_subdev_enum_mbus_code(struct v4l2_subdev *sd,
  884. struct v4l2_subdev_fh *fh,
  885. struct v4l2_subdev_mbus_code_enum *code)
  886. {
  887. const struct fimc_fmt *fmt;
  888. fmt = fimc_lite_find_format(NULL, NULL, code->index);
  889. if (!fmt)
  890. return -EINVAL;
  891. code->code = fmt->mbus_code;
  892. return 0;
  893. }
  894. static int fimc_lite_subdev_get_fmt(struct v4l2_subdev *sd,
  895. struct v4l2_subdev_fh *fh,
  896. struct v4l2_subdev_format *fmt)
  897. {
  898. struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
  899. struct v4l2_mbus_framefmt *mf = &fmt->format;
  900. struct flite_frame *f = &fimc->out_frame;
  901. if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
  902. mf = v4l2_subdev_get_try_format(fh, fmt->pad);
  903. fmt->format = *mf;
  904. return 0;
  905. }
  906. mf->colorspace = V4L2_COLORSPACE_JPEG;
  907. mutex_lock(&fimc->lock);
  908. mf->code = fimc->fmt->mbus_code;
  909. if (fmt->pad == FLITE_SD_PAD_SINK) {
  910. /* full camera input frame size */
  911. mf->width = f->f_width;
  912. mf->height = f->f_height;
  913. } else {
  914. /* crop size */
  915. mf->width = f->rect.width;
  916. mf->height = f->rect.height;
  917. }
  918. mutex_unlock(&fimc->lock);
  919. return 0;
  920. }
  921. static int fimc_lite_subdev_set_fmt(struct v4l2_subdev *sd,
  922. struct v4l2_subdev_fh *fh,
  923. struct v4l2_subdev_format *fmt)
  924. {
  925. struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
  926. struct v4l2_mbus_framefmt *mf = &fmt->format;
  927. struct flite_frame *sink = &fimc->inp_frame;
  928. struct flite_frame *source = &fimc->out_frame;
  929. const struct fimc_fmt *ffmt;
  930. v4l2_dbg(1, debug, sd, "pad%d: code: 0x%x, %dx%d",
  931. fmt->pad, mf->code, mf->width, mf->height);
  932. mf->colorspace = V4L2_COLORSPACE_JPEG;
  933. mutex_lock(&fimc->lock);
  934. if ((fimc->out_path == FIMC_IO_ISP && sd->entity.stream_count > 0) ||
  935. (fimc->out_path == FIMC_IO_DMA && vb2_is_busy(&fimc->vb_queue))) {
  936. mutex_unlock(&fimc->lock);
  937. return -EBUSY;
  938. }
  939. ffmt = fimc_lite_try_format(fimc, &mf->width, &mf->height,
  940. &mf->code, NULL, fmt->pad);
  941. if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
  942. mf = v4l2_subdev_get_try_format(fh, fmt->pad);
  943. *mf = fmt->format;
  944. mutex_unlock(&fimc->lock);
  945. return 0;
  946. }
  947. if (fmt->pad == FLITE_SD_PAD_SINK) {
  948. sink->f_width = mf->width;
  949. sink->f_height = mf->height;
  950. fimc->fmt = ffmt;
  951. /* Set sink crop rectangle */
  952. sink->rect.width = mf->width;
  953. sink->rect.height = mf->height;
  954. sink->rect.left = 0;
  955. sink->rect.top = 0;
  956. /* Reset source format and crop rectangle */
  957. source->rect = sink->rect;
  958. source->f_width = mf->width;
  959. source->f_height = mf->height;
  960. } else {
  961. /* Allow changing format only on sink pad */
  962. mf->code = fimc->fmt->mbus_code;
  963. mf->width = sink->rect.width;
  964. mf->height = sink->rect.height;
  965. }
  966. mutex_unlock(&fimc->lock);
  967. return 0;
  968. }
  969. static int fimc_lite_subdev_get_selection(struct v4l2_subdev *sd,
  970. struct v4l2_subdev_fh *fh,
  971. struct v4l2_subdev_selection *sel)
  972. {
  973. struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
  974. struct flite_frame *f = &fimc->inp_frame;
  975. if ((sel->target != V4L2_SEL_TGT_CROP &&
  976. sel->target != V4L2_SEL_TGT_CROP_BOUNDS) ||
  977. sel->pad != FLITE_SD_PAD_SINK)
  978. return -EINVAL;
  979. if (sel->which == V4L2_SUBDEV_FORMAT_TRY) {
  980. sel->r = *v4l2_subdev_get_try_crop(fh, sel->pad);
  981. return 0;
  982. }
  983. mutex_lock(&fimc->lock);
  984. if (sel->target == V4L2_SEL_TGT_CROP) {
  985. sel->r = f->rect;
  986. } else {
  987. sel->r.left = 0;
  988. sel->r.top = 0;
  989. sel->r.width = f->f_width;
  990. sel->r.height = f->f_height;
  991. }
  992. mutex_unlock(&fimc->lock);
  993. v4l2_dbg(1, debug, sd, "%s: (%d,%d) %dx%d, f_w: %d, f_h: %d",
  994. __func__, f->rect.left, f->rect.top, f->rect.width,
  995. f->rect.height, f->f_width, f->f_height);
  996. return 0;
  997. }
  998. static int fimc_lite_subdev_set_selection(struct v4l2_subdev *sd,
  999. struct v4l2_subdev_fh *fh,
  1000. struct v4l2_subdev_selection *sel)
  1001. {
  1002. struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
  1003. struct flite_frame *f = &fimc->inp_frame;
  1004. int ret = 0;
  1005. if (sel->target != V4L2_SEL_TGT_CROP || sel->pad != FLITE_SD_PAD_SINK)
  1006. return -EINVAL;
  1007. mutex_lock(&fimc->lock);
  1008. fimc_lite_try_crop(fimc, &sel->r);
  1009. if (sel->which == V4L2_SUBDEV_FORMAT_TRY) {
  1010. *v4l2_subdev_get_try_crop(fh, sel->pad) = sel->r;
  1011. } else {
  1012. unsigned long flags;
  1013. spin_lock_irqsave(&fimc->slock, flags);
  1014. f->rect = sel->r;
  1015. /* Same crop rectangle on the source pad */
  1016. fimc->out_frame.rect = sel->r;
  1017. set_bit(ST_FLITE_CONFIG, &fimc->state);
  1018. spin_unlock_irqrestore(&fimc->slock, flags);
  1019. }
  1020. mutex_unlock(&fimc->lock);
  1021. v4l2_dbg(1, debug, sd, "%s: (%d,%d) %dx%d, f_w: %d, f_h: %d",
  1022. __func__, f->rect.left, f->rect.top, f->rect.width,
  1023. f->rect.height, f->f_width, f->f_height);
  1024. return ret;
  1025. }
  1026. static int fimc_lite_subdev_s_stream(struct v4l2_subdev *sd, int on)
  1027. {
  1028. struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
  1029. unsigned long flags;
  1030. int ret;
  1031. /*
  1032. * Find sensor subdev linked to FIMC-LITE directly or through
  1033. * MIPI-CSIS. This is required for configuration where FIMC-LITE
  1034. * is used as a subdev only and feeds data internally to FIMC-IS.
  1035. * The pipeline links are protected through entity.stream_count
  1036. * so there is no need to take the media graph mutex here.
  1037. */
  1038. fimc->sensor = __find_remote_sensor(&sd->entity);
  1039. mutex_lock(&fimc->lock);
  1040. if (fimc->out_path != FIMC_IO_ISP) {
  1041. mutex_unlock(&fimc->lock);
  1042. return -ENOIOCTLCMD;
  1043. }
  1044. if (on) {
  1045. flite_hw_reset(fimc);
  1046. ret = fimc_lite_hw_init(fimc, true);
  1047. if (!ret) {
  1048. spin_lock_irqsave(&fimc->slock, flags);
  1049. flite_hw_capture_start(fimc);
  1050. spin_unlock_irqrestore(&fimc->slock, flags);
  1051. }
  1052. } else {
  1053. set_bit(ST_FLITE_OFF, &fimc->state);
  1054. spin_lock_irqsave(&fimc->slock, flags);
  1055. flite_hw_capture_stop(fimc);
  1056. spin_unlock_irqrestore(&fimc->slock, flags);
  1057. ret = wait_event_timeout(fimc->irq_queue,
  1058. !test_bit(ST_FLITE_OFF, &fimc->state),
  1059. msecs_to_jiffies(200));
  1060. if (ret == 0)
  1061. v4l2_err(sd, "s_stream(0) timeout\n");
  1062. clear_bit(ST_FLITE_RUN, &fimc->state);
  1063. }
  1064. mutex_unlock(&fimc->lock);
  1065. return ret;
  1066. }
  1067. static int fimc_lite_subdev_s_power(struct v4l2_subdev *sd, int on)
  1068. {
  1069. struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
  1070. if (fimc->out_path == FIMC_IO_DMA)
  1071. return -ENOIOCTLCMD;
  1072. /* TODO: */
  1073. return 0;
  1074. }
  1075. static int fimc_lite_log_status(struct v4l2_subdev *sd)
  1076. {
  1077. struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
  1078. flite_hw_dump_regs(fimc, __func__);
  1079. return 0;
  1080. }
  1081. static int fimc_lite_subdev_registered(struct v4l2_subdev *sd)
  1082. {
  1083. struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
  1084. struct vb2_queue *q = &fimc->vb_queue;
  1085. struct video_device *vfd = &fimc->vfd;
  1086. int ret;
  1087. memset(vfd, 0, sizeof(*vfd));
  1088. fimc->fmt = &fimc_lite_formats[0];
  1089. fimc->out_path = FIMC_IO_DMA;
  1090. snprintf(vfd->name, sizeof(vfd->name), "fimc-lite.%d.capture",
  1091. fimc->index);
  1092. vfd->fops = &fimc_lite_fops;
  1093. vfd->ioctl_ops = &fimc_lite_ioctl_ops;
  1094. vfd->v4l2_dev = sd->v4l2_dev;
  1095. vfd->minor = -1;
  1096. vfd->release = video_device_release_empty;
  1097. vfd->lock = &fimc->lock;
  1098. fimc->ref_count = 0;
  1099. fimc->reqbufs_count = 0;
  1100. INIT_LIST_HEAD(&fimc->pending_buf_q);
  1101. INIT_LIST_HEAD(&fimc->active_buf_q);
  1102. memset(q, 0, sizeof(*q));
  1103. q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
  1104. q->io_modes = VB2_MMAP | VB2_USERPTR;
  1105. q->ops = &fimc_lite_qops;
  1106. q->mem_ops = &vb2_dma_contig_memops;
  1107. q->buf_struct_size = sizeof(struct flite_buffer);
  1108. q->drv_priv = fimc;
  1109. ret = vb2_queue_init(q);
  1110. if (ret < 0)
  1111. return ret;
  1112. fimc->vd_pad.flags = MEDIA_PAD_FL_SINK;
  1113. ret = media_entity_init(&vfd->entity, 1, &fimc->vd_pad, 0);
  1114. if (ret < 0)
  1115. return ret;
  1116. video_set_drvdata(vfd, fimc);
  1117. fimc->pipeline_ops = v4l2_get_subdev_hostdata(sd);
  1118. ret = video_register_device(vfd, VFL_TYPE_GRABBER, -1);
  1119. if (ret < 0) {
  1120. media_entity_cleanup(&vfd->entity);
  1121. fimc->pipeline_ops = NULL;
  1122. return ret;
  1123. }
  1124. v4l2_info(sd->v4l2_dev, "Registered %s as /dev/%s\n",
  1125. vfd->name, video_device_node_name(vfd));
  1126. return 0;
  1127. }
  1128. static void fimc_lite_subdev_unregistered(struct v4l2_subdev *sd)
  1129. {
  1130. struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
  1131. if (fimc == NULL)
  1132. return;
  1133. if (video_is_registered(&fimc->vfd)) {
  1134. video_unregister_device(&fimc->vfd);
  1135. media_entity_cleanup(&fimc->vfd.entity);
  1136. fimc->pipeline_ops = NULL;
  1137. }
  1138. }
  1139. static const struct v4l2_subdev_internal_ops fimc_lite_subdev_internal_ops = {
  1140. .registered = fimc_lite_subdev_registered,
  1141. .unregistered = fimc_lite_subdev_unregistered,
  1142. };
  1143. static const struct v4l2_subdev_pad_ops fimc_lite_subdev_pad_ops = {
  1144. .enum_mbus_code = fimc_lite_subdev_enum_mbus_code,
  1145. .get_selection = fimc_lite_subdev_get_selection,
  1146. .set_selection = fimc_lite_subdev_set_selection,
  1147. .get_fmt = fimc_lite_subdev_get_fmt,
  1148. .set_fmt = fimc_lite_subdev_set_fmt,
  1149. };
  1150. static const struct v4l2_subdev_video_ops fimc_lite_subdev_video_ops = {
  1151. .s_stream = fimc_lite_subdev_s_stream,
  1152. };
  1153. static const struct v4l2_subdev_core_ops fimc_lite_core_ops = {
  1154. .s_power = fimc_lite_subdev_s_power,
  1155. .log_status = fimc_lite_log_status,
  1156. };
  1157. static struct v4l2_subdev_ops fimc_lite_subdev_ops = {
  1158. .core = &fimc_lite_core_ops,
  1159. .video = &fimc_lite_subdev_video_ops,
  1160. .pad = &fimc_lite_subdev_pad_ops,
  1161. };
  1162. static int fimc_lite_s_ctrl(struct v4l2_ctrl *ctrl)
  1163. {
  1164. struct fimc_lite *fimc = container_of(ctrl->handler, struct fimc_lite,
  1165. ctrl_handler);
  1166. set_bit(ST_FLITE_CONFIG, &fimc->state);
  1167. return 0;
  1168. }
  1169. static const struct v4l2_ctrl_ops fimc_lite_ctrl_ops = {
  1170. .s_ctrl = fimc_lite_s_ctrl,
  1171. };
  1172. static const struct v4l2_ctrl_config fimc_lite_ctrl = {
  1173. .ops = &fimc_lite_ctrl_ops,
  1174. .id = V4L2_CTRL_CLASS_USER | 0x1001,
  1175. .type = V4L2_CTRL_TYPE_BOOLEAN,
  1176. .name = "Test Pattern 640x480",
  1177. };
  1178. static int fimc_lite_create_capture_subdev(struct fimc_lite *fimc)
  1179. {
  1180. struct v4l2_ctrl_handler *handler = &fimc->ctrl_handler;
  1181. struct v4l2_subdev *sd = &fimc->subdev;
  1182. int ret;
  1183. v4l2_subdev_init(sd, &fimc_lite_subdev_ops);
  1184. sd->flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
  1185. snprintf(sd->name, sizeof(sd->name), "FIMC-LITE.%d", fimc->index);
  1186. fimc->subdev_pads[FLITE_SD_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
  1187. fimc->subdev_pads[FLITE_SD_PAD_SOURCE_DMA].flags = MEDIA_PAD_FL_SOURCE;
  1188. fimc->subdev_pads[FLITE_SD_PAD_SOURCE_ISP].flags = MEDIA_PAD_FL_SOURCE;
  1189. ret = media_entity_init(&sd->entity, FLITE_SD_PADS_NUM,
  1190. fimc->subdev_pads, 0);
  1191. if (ret)
  1192. return ret;
  1193. v4l2_ctrl_handler_init(handler, 1);
  1194. fimc->test_pattern = v4l2_ctrl_new_custom(handler, &fimc_lite_ctrl,
  1195. NULL);
  1196. if (handler->error) {
  1197. media_entity_cleanup(&sd->entity);
  1198. return handler->error;
  1199. }
  1200. sd->ctrl_handler = handler;
  1201. sd->internal_ops = &fimc_lite_subdev_internal_ops;
  1202. sd->entity.ops = &fimc_lite_subdev_media_ops;
  1203. v4l2_set_subdevdata(sd, fimc);
  1204. return 0;
  1205. }
  1206. static void fimc_lite_unregister_capture_subdev(struct fimc_lite *fimc)
  1207. {
  1208. struct v4l2_subdev *sd = &fimc->subdev;
  1209. v4l2_device_unregister_subdev(sd);
  1210. media_entity_cleanup(&sd->entity);
  1211. v4l2_ctrl_handler_free(&fimc->ctrl_handler);
  1212. v4l2_set_subdevdata(sd, NULL);
  1213. }
  1214. static void fimc_lite_clk_put(struct fimc_lite *fimc)
  1215. {
  1216. if (IS_ERR_OR_NULL(fimc->clock))
  1217. return;
  1218. clk_unprepare(fimc->clock);
  1219. clk_put(fimc->clock);
  1220. fimc->clock = NULL;
  1221. }
  1222. static int fimc_lite_clk_get(struct fimc_lite *fimc)
  1223. {
  1224. int ret;
  1225. fimc->clock = clk_get(&fimc->pdev->dev, FLITE_CLK_NAME);
  1226. if (IS_ERR(fimc->clock))
  1227. return PTR_ERR(fimc->clock);
  1228. ret = clk_prepare(fimc->clock);
  1229. if (ret < 0) {
  1230. clk_put(fimc->clock);
  1231. fimc->clock = NULL;
  1232. }
  1233. return ret;
  1234. }
  1235. static int __devinit fimc_lite_probe(struct platform_device *pdev)
  1236. {
  1237. struct flite_drvdata *drv_data = fimc_lite_get_drvdata(pdev);
  1238. struct fimc_lite *fimc;
  1239. struct resource *res;
  1240. int ret;
  1241. fimc = devm_kzalloc(&pdev->dev, sizeof(*fimc), GFP_KERNEL);
  1242. if (!fimc)
  1243. return -ENOMEM;
  1244. fimc->index = pdev->id;
  1245. fimc->variant = drv_data->variant[fimc->index];
  1246. fimc->pdev = pdev;
  1247. init_waitqueue_head(&fimc->irq_queue);
  1248. spin_lock_init(&fimc->slock);
  1249. mutex_init(&fimc->lock);
  1250. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1251. fimc->regs = devm_request_and_ioremap(&pdev->dev, res);
  1252. if (fimc->regs == NULL) {
  1253. dev_err(&pdev->dev, "Failed to obtain io memory\n");
  1254. return -ENOENT;
  1255. }
  1256. res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  1257. if (res == NULL) {
  1258. dev_err(&pdev->dev, "Failed to get IRQ resource\n");
  1259. return -ENXIO;
  1260. }
  1261. ret = fimc_lite_clk_get(fimc);
  1262. if (ret)
  1263. return ret;
  1264. ret = devm_request_irq(&pdev->dev, res->start, flite_irq_handler,
  1265. 0, dev_name(&pdev->dev), fimc);
  1266. if (ret) {
  1267. dev_err(&pdev->dev, "Failed to install irq (%d)\n", ret);
  1268. goto err_clk;
  1269. }
  1270. /* The video node will be created within the subdev's registered() op */
  1271. ret = fimc_lite_create_capture_subdev(fimc);
  1272. if (ret)
  1273. goto err_clk;
  1274. platform_set_drvdata(pdev, fimc);
  1275. pm_runtime_enable(&pdev->dev);
  1276. ret = pm_runtime_get_sync(&pdev->dev);
  1277. if (ret < 0)
  1278. goto err_sd;
  1279. fimc->alloc_ctx = vb2_dma_contig_init_ctx(&pdev->dev);
  1280. if (IS_ERR(fimc->alloc_ctx)) {
  1281. ret = PTR_ERR(fimc->alloc_ctx);
  1282. goto err_pm;
  1283. }
  1284. pm_runtime_put(&pdev->dev);
  1285. dev_dbg(&pdev->dev, "FIMC-LITE.%d registered successfully\n",
  1286. fimc->index);
  1287. return 0;
  1288. err_pm:
  1289. pm_runtime_put(&pdev->dev);
  1290. err_sd:
  1291. fimc_lite_unregister_capture_subdev(fimc);
  1292. err_clk:
  1293. fimc_lite_clk_put(fimc);
  1294. return ret;
  1295. }
  1296. static int fimc_lite_runtime_resume(struct device *dev)
  1297. {
  1298. struct fimc_lite *fimc = dev_get_drvdata(dev);
  1299. clk_enable(fimc->clock);
  1300. return 0;
  1301. }
  1302. static int fimc_lite_runtime_suspend(struct device *dev)
  1303. {
  1304. struct fimc_lite *fimc = dev_get_drvdata(dev);
  1305. clk_disable(fimc->clock);
  1306. return 0;
  1307. }
  1308. #ifdef CONFIG_PM_SLEEP
  1309. static int fimc_lite_resume(struct device *dev)
  1310. {
  1311. struct fimc_lite *fimc = dev_get_drvdata(dev);
  1312. struct flite_buffer *buf;
  1313. unsigned long flags;
  1314. int i;
  1315. spin_lock_irqsave(&fimc->slock, flags);
  1316. if (!test_and_clear_bit(ST_LPM, &fimc->state) ||
  1317. !test_bit(ST_FLITE_IN_USE, &fimc->state)) {
  1318. spin_unlock_irqrestore(&fimc->slock, flags);
  1319. return 0;
  1320. }
  1321. flite_hw_reset(fimc);
  1322. spin_unlock_irqrestore(&fimc->slock, flags);
  1323. if (!test_and_clear_bit(ST_FLITE_SUSPENDED, &fimc->state))
  1324. return 0;
  1325. INIT_LIST_HEAD(&fimc->active_buf_q);
  1326. fimc_pipeline_call(fimc, open, &fimc->pipeline,
  1327. &fimc->vfd.entity, false);
  1328. fimc_lite_hw_init(fimc, fimc->out_path == FIMC_IO_ISP);
  1329. clear_bit(ST_FLITE_SUSPENDED, &fimc->state);
  1330. for (i = 0; i < fimc->reqbufs_count; i++) {
  1331. if (list_empty(&fimc->pending_buf_q))
  1332. break;
  1333. buf = fimc_lite_pending_queue_pop(fimc);
  1334. buffer_queue(&buf->vb);
  1335. }
  1336. return 0;
  1337. }
  1338. static int fimc_lite_suspend(struct device *dev)
  1339. {
  1340. struct fimc_lite *fimc = dev_get_drvdata(dev);
  1341. bool suspend = test_bit(ST_FLITE_IN_USE, &fimc->state);
  1342. int ret;
  1343. if (test_and_set_bit(ST_LPM, &fimc->state))
  1344. return 0;
  1345. ret = fimc_lite_stop_capture(fimc, suspend);
  1346. if (ret < 0 || !fimc_lite_active(fimc))
  1347. return ret;
  1348. return fimc_pipeline_call(fimc, close, &fimc->pipeline);
  1349. }
  1350. #endif /* CONFIG_PM_SLEEP */
  1351. static int __devexit fimc_lite_remove(struct platform_device *pdev)
  1352. {
  1353. struct fimc_lite *fimc = platform_get_drvdata(pdev);
  1354. struct device *dev = &pdev->dev;
  1355. pm_runtime_disable(dev);
  1356. pm_runtime_set_suspended(dev);
  1357. fimc_lite_unregister_capture_subdev(fimc);
  1358. vb2_dma_contig_cleanup_ctx(fimc->alloc_ctx);
  1359. fimc_lite_clk_put(fimc);
  1360. dev_info(dev, "Driver unloaded\n");
  1361. return 0;
  1362. }
  1363. static struct flite_variant fimc_lite0_variant_exynos4 = {
  1364. .max_width = 8192,
  1365. .max_height = 8192,
  1366. .out_width_align = 8,
  1367. .win_hor_offs_align = 2,
  1368. .out_hor_offs_align = 8,
  1369. };
  1370. /* EXYNOS4212, EXYNOS4412 */
  1371. static struct flite_drvdata fimc_lite_drvdata_exynos4 = {
  1372. .variant = {
  1373. [0] = &fimc_lite0_variant_exynos4,
  1374. [1] = &fimc_lite0_variant_exynos4,
  1375. },
  1376. };
  1377. static struct platform_device_id fimc_lite_driver_ids[] = {
  1378. {
  1379. .name = "exynos-fimc-lite",
  1380. .driver_data = (unsigned long)&fimc_lite_drvdata_exynos4,
  1381. },
  1382. { /* sentinel */ },
  1383. };
  1384. MODULE_DEVICE_TABLE(platform, fimc_lite_driver_ids);
  1385. static const struct dev_pm_ops fimc_lite_pm_ops = {
  1386. SET_SYSTEM_SLEEP_PM_OPS(fimc_lite_suspend, fimc_lite_resume)
  1387. SET_RUNTIME_PM_OPS(fimc_lite_runtime_suspend, fimc_lite_runtime_resume,
  1388. NULL)
  1389. };
  1390. static struct platform_driver fimc_lite_driver = {
  1391. .probe = fimc_lite_probe,
  1392. .remove = __devexit_p(fimc_lite_remove),
  1393. .id_table = fimc_lite_driver_ids,
  1394. .driver = {
  1395. .name = FIMC_LITE_DRV_NAME,
  1396. .owner = THIS_MODULE,
  1397. .pm = &fimc_lite_pm_ops,
  1398. }
  1399. };
  1400. module_platform_driver(fimc_lite_driver);
  1401. MODULE_LICENSE("GPL");
  1402. MODULE_ALIAS("platform:" FIMC_LITE_DRV_NAME);