mpc8544ds.dts 10 KB

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  1. /*
  2. * MPC8544 DS Device Tree Source
  3. *
  4. * Copyright 2007, 2008 Freescale Semiconductor Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. /dts-v1/;
  12. / {
  13. model = "MPC8544DS";
  14. compatible = "MPC8544DS", "MPC85xxDS";
  15. #address-cells = <1>;
  16. #size-cells = <1>;
  17. aliases {
  18. ethernet0 = &enet0;
  19. ethernet1 = &enet1;
  20. serial0 = &serial0;
  21. serial1 = &serial1;
  22. pci0 = &pci0;
  23. pci1 = &pci1;
  24. pci2 = &pci2;
  25. pci3 = &pci3;
  26. };
  27. cpus {
  28. #address-cells = <1>;
  29. #size-cells = <0>;
  30. PowerPC,8544@0 {
  31. device_type = "cpu";
  32. reg = <0x0>;
  33. d-cache-line-size = <32>; // 32 bytes
  34. i-cache-line-size = <32>; // 32 bytes
  35. d-cache-size = <0x8000>; // L1, 32K
  36. i-cache-size = <0x8000>; // L1, 32K
  37. timebase-frequency = <0>;
  38. bus-frequency = <0>;
  39. clock-frequency = <0>;
  40. next-level-cache = <&L2>;
  41. };
  42. };
  43. memory {
  44. device_type = "memory";
  45. reg = <0x0 0x0>; // Filled by U-Boot
  46. };
  47. soc8544@e0000000 {
  48. #address-cells = <1>;
  49. #size-cells = <1>;
  50. device_type = "soc";
  51. ranges = <0x0 0xe0000000 0x100000>;
  52. reg = <0xe0000000 0x1000>; // CCSRBAR 1M
  53. bus-frequency = <0>; // Filled out by uboot.
  54. memory-controller@2000 {
  55. compatible = "fsl,8544-memory-controller";
  56. reg = <0x2000 0x1000>;
  57. interrupt-parent = <&mpic>;
  58. interrupts = <18 2>;
  59. };
  60. L2: l2-cache-controller@20000 {
  61. compatible = "fsl,8544-l2-cache-controller";
  62. reg = <0x20000 0x1000>;
  63. cache-line-size = <32>; // 32 bytes
  64. cache-size = <0x40000>; // L2, 256K
  65. interrupt-parent = <&mpic>;
  66. interrupts = <16 2>;
  67. };
  68. i2c@3000 {
  69. #address-cells = <1>;
  70. #size-cells = <0>;
  71. cell-index = <0>;
  72. compatible = "fsl-i2c";
  73. reg = <0x3000 0x100>;
  74. interrupts = <43 2>;
  75. interrupt-parent = <&mpic>;
  76. dfsrr;
  77. };
  78. i2c@3100 {
  79. #address-cells = <1>;
  80. #size-cells = <0>;
  81. cell-index = <1>;
  82. compatible = "fsl-i2c";
  83. reg = <0x3100 0x100>;
  84. interrupts = <43 2>;
  85. interrupt-parent = <&mpic>;
  86. dfsrr;
  87. };
  88. mdio@24520 {
  89. #address-cells = <1>;
  90. #size-cells = <0>;
  91. compatible = "fsl,gianfar-mdio";
  92. reg = <0x24520 0x20>;
  93. phy0: ethernet-phy@0 {
  94. interrupt-parent = <&mpic>;
  95. interrupts = <10 1>;
  96. reg = <0x0>;
  97. device_type = "ethernet-phy";
  98. };
  99. phy1: ethernet-phy@1 {
  100. interrupt-parent = <&mpic>;
  101. interrupts = <10 1>;
  102. reg = <0x1>;
  103. device_type = "ethernet-phy";
  104. };
  105. };
  106. dma@21300 {
  107. #address-cells = <1>;
  108. #size-cells = <1>;
  109. compatible = "fsl,mpc8544-dma", "fsl,eloplus-dma";
  110. reg = <0x21300 0x4>;
  111. ranges = <0x0 0x21100 0x200>;
  112. cell-index = <0>;
  113. dma-channel@0 {
  114. compatible = "fsl,mpc8544-dma-channel",
  115. "fsl,eloplus-dma-channel";
  116. reg = <0x0 0x80>;
  117. cell-index = <0>;
  118. interrupt-parent = <&mpic>;
  119. interrupts = <20 2>;
  120. };
  121. dma-channel@80 {
  122. compatible = "fsl,mpc8544-dma-channel",
  123. "fsl,eloplus-dma-channel";
  124. reg = <0x80 0x80>;
  125. cell-index = <1>;
  126. interrupt-parent = <&mpic>;
  127. interrupts = <21 2>;
  128. };
  129. dma-channel@100 {
  130. compatible = "fsl,mpc8544-dma-channel",
  131. "fsl,eloplus-dma-channel";
  132. reg = <0x100 0x80>;
  133. cell-index = <2>;
  134. interrupt-parent = <&mpic>;
  135. interrupts = <22 2>;
  136. };
  137. dma-channel@180 {
  138. compatible = "fsl,mpc8544-dma-channel",
  139. "fsl,eloplus-dma-channel";
  140. reg = <0x180 0x80>;
  141. cell-index = <3>;
  142. interrupt-parent = <&mpic>;
  143. interrupts = <23 2>;
  144. };
  145. };
  146. enet0: ethernet@24000 {
  147. cell-index = <0>;
  148. device_type = "network";
  149. model = "TSEC";
  150. compatible = "gianfar";
  151. reg = <0x24000 0x1000>;
  152. local-mac-address = [ 00 00 00 00 00 00 ];
  153. interrupts = <29 2 30 2 34 2>;
  154. interrupt-parent = <&mpic>;
  155. phy-handle = <&phy0>;
  156. phy-connection-type = "rgmii-id";
  157. };
  158. enet1: ethernet@26000 {
  159. cell-index = <1>;
  160. device_type = "network";
  161. model = "TSEC";
  162. compatible = "gianfar";
  163. reg = <0x26000 0x1000>;
  164. local-mac-address = [ 00 00 00 00 00 00 ];
  165. interrupts = <31 2 32 2 33 2>;
  166. interrupt-parent = <&mpic>;
  167. phy-handle = <&phy1>;
  168. phy-connection-type = "rgmii-id";
  169. };
  170. serial0: serial@4500 {
  171. cell-index = <0>;
  172. device_type = "serial";
  173. compatible = "ns16550";
  174. reg = <0x4500 0x100>;
  175. clock-frequency = <0>;
  176. interrupts = <42 2>;
  177. interrupt-parent = <&mpic>;
  178. };
  179. serial1: serial@4600 {
  180. cell-index = <1>;
  181. device_type = "serial";
  182. compatible = "ns16550";
  183. reg = <0x4600 0x100>;
  184. clock-frequency = <0>;
  185. interrupts = <42 2>;
  186. interrupt-parent = <&mpic>;
  187. };
  188. global-utilities@e0000 { //global utilities block
  189. compatible = "fsl,mpc8548-guts";
  190. reg = <0xe0000 0x1000>;
  191. fsl,has-rstcr;
  192. };
  193. mpic: pic@40000 {
  194. interrupt-controller;
  195. #address-cells = <0>;
  196. #interrupt-cells = <2>;
  197. reg = <0x40000 0x40000>;
  198. compatible = "chrp,open-pic";
  199. device_type = "open-pic";
  200. };
  201. msi@41600 {
  202. compatible = "fsl,mpc8544-msi", "fsl,mpic-msi";
  203. reg = <0x41600 0x80>;
  204. msi-available-ranges = <0 0x100>;
  205. interrupts = <
  206. 0xe0 0
  207. 0xe1 0
  208. 0xe2 0
  209. 0xe3 0
  210. 0xe4 0
  211. 0xe5 0
  212. 0xe6 0
  213. 0xe7 0>;
  214. interrupt-parent = <&mpic>;
  215. };
  216. };
  217. pci0: pci@e0008000 {
  218. cell-index = <0>;
  219. compatible = "fsl,mpc8540-pci";
  220. device_type = "pci";
  221. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  222. interrupt-map = <
  223. /* IDSEL 0x11 J17 Slot 1 */
  224. 0x8800 0x0 0x0 0x1 &mpic 0x2 0x1
  225. 0x8800 0x0 0x0 0x2 &mpic 0x3 0x1
  226. 0x8800 0x0 0x0 0x3 &mpic 0x4 0x1
  227. 0x8800 0x0 0x0 0x4 &mpic 0x1 0x1
  228. /* IDSEL 0x12 J16 Slot 2 */
  229. 0x9000 0x0 0x0 0x1 &mpic 0x3 0x1
  230. 0x9000 0x0 0x0 0x2 &mpic 0x4 0x1
  231. 0x9000 0x0 0x0 0x3 &mpic 0x2 0x1
  232. 0x9000 0x0 0x0 0x4 &mpic 0x1 0x1>;
  233. interrupt-parent = <&mpic>;
  234. interrupts = <24 2>;
  235. bus-range = <0 255>;
  236. ranges = <0x2000000 0x0 0xc0000000 0xc0000000 0x0 0x20000000
  237. 0x1000000 0x0 0x0 0xe1000000 0x0 0x10000>;
  238. clock-frequency = <66666666>;
  239. #interrupt-cells = <1>;
  240. #size-cells = <2>;
  241. #address-cells = <3>;
  242. reg = <0xe0008000 0x1000>;
  243. };
  244. pci1: pcie@e0009000 {
  245. cell-index = <1>;
  246. compatible = "fsl,mpc8548-pcie";
  247. device_type = "pci";
  248. #interrupt-cells = <1>;
  249. #size-cells = <2>;
  250. #address-cells = <3>;
  251. reg = <0xe0009000 0x1000>;
  252. bus-range = <0 255>;
  253. ranges = <0x2000000 0x0 0x80000000 0x80000000 0x0 0x20000000
  254. 0x1000000 0x0 0x0 0xe1010000 0x0 0x10000>;
  255. clock-frequency = <33333333>;
  256. interrupt-parent = <&mpic>;
  257. interrupts = <26 2>;
  258. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  259. interrupt-map = <
  260. /* IDSEL 0x0 */
  261. 0000 0x0 0x0 0x1 &mpic 0x4 0x1
  262. 0000 0x0 0x0 0x2 &mpic 0x5 0x1
  263. 0000 0x0 0x0 0x3 &mpic 0x6 0x1
  264. 0000 0x0 0x0 0x4 &mpic 0x7 0x1
  265. >;
  266. pcie@0 {
  267. reg = <0x0 0x0 0x0 0x0 0x0>;
  268. #size-cells = <2>;
  269. #address-cells = <3>;
  270. device_type = "pci";
  271. ranges = <0x2000000 0x0 0x80000000
  272. 0x2000000 0x0 0x80000000
  273. 0x0 0x20000000
  274. 0x1000000 0x0 0x0
  275. 0x1000000 0x0 0x0
  276. 0x0 0x10000>;
  277. };
  278. };
  279. pci2: pcie@e000a000 {
  280. cell-index = <2>;
  281. compatible = "fsl,mpc8548-pcie";
  282. device_type = "pci";
  283. #interrupt-cells = <1>;
  284. #size-cells = <2>;
  285. #address-cells = <3>;
  286. reg = <0xe000a000 0x1000>;
  287. bus-range = <0 255>;
  288. ranges = <0x2000000 0x0 0xa0000000 0xa0000000 0x0 0x10000000
  289. 0x1000000 0x0 0x0 0xe1020000 0x0 0x10000>;
  290. clock-frequency = <33333333>;
  291. interrupt-parent = <&mpic>;
  292. interrupts = <25 2>;
  293. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  294. interrupt-map = <
  295. /* IDSEL 0x0 */
  296. 0000 0x0 0x0 0x1 &mpic 0x0 0x1
  297. 0000 0x0 0x0 0x2 &mpic 0x1 0x1
  298. 0000 0x0 0x0 0x3 &mpic 0x2 0x1
  299. 0000 0x0 0x0 0x4 &mpic 0x3 0x1
  300. >;
  301. pcie@0 {
  302. reg = <0x0 0x0 0x0 0x0 0x0>;
  303. #size-cells = <2>;
  304. #address-cells = <3>;
  305. device_type = "pci";
  306. ranges = <0x2000000 0x0 0xa0000000
  307. 0x2000000 0x0 0xa0000000
  308. 0x0 0x10000000
  309. 0x1000000 0x0 0x0
  310. 0x1000000 0x0 0x0
  311. 0x0 0x10000>;
  312. };
  313. };
  314. pci3: pcie@e000b000 {
  315. cell-index = <3>;
  316. compatible = "fsl,mpc8548-pcie";
  317. device_type = "pci";
  318. #interrupt-cells = <1>;
  319. #size-cells = <2>;
  320. #address-cells = <3>;
  321. reg = <0xe000b000 0x1000>;
  322. bus-range = <0 255>;
  323. ranges = <0x2000000 0x0 0xb0000000 0xb0000000 0x0 0x100000
  324. 0x1000000 0x0 0x0 0xb0100000 0x0 0x100000>;
  325. clock-frequency = <33333333>;
  326. interrupt-parent = <&mpic>;
  327. interrupts = <27 2>;
  328. interrupt-map-mask = <0xff00 0x0 0x0 0x1>;
  329. interrupt-map = <
  330. // IDSEL 0x1c USB
  331. 0xe000 0x0 0x0 0x1 &i8259 0xc 0x2
  332. 0xe100 0x0 0x0 0x2 &i8259 0x9 0x2
  333. 0xe200 0x0 0x0 0x3 &i8259 0xa 0x2
  334. 0xe300 0x0 0x0 0x4 &i8259 0xb 0x2
  335. // IDSEL 0x1d Audio
  336. 0xe800 0x0 0x0 0x1 &i8259 0x6 0x2
  337. // IDSEL 0x1e Legacy
  338. 0xf000 0x0 0x0 0x1 &i8259 0x7 0x2
  339. 0xf100 0x0 0x0 0x1 &i8259 0x7 0x2
  340. // IDSEL 0x1f IDE/SATA
  341. 0xf800 0x0 0x0 0x1 &i8259 0xe 0x2
  342. 0xf900 0x0 0x0 0x1 &i8259 0x5 0x2
  343. >;
  344. pcie@0 {
  345. reg = <0x0 0x0 0x0 0x0 0x0>;
  346. #size-cells = <2>;
  347. #address-cells = <3>;
  348. device_type = "pci";
  349. ranges = <0x2000000 0x0 0xb0000000
  350. 0x2000000 0x0 0xb0000000
  351. 0x0 0x100000
  352. 0x1000000 0x0 0x0
  353. 0x1000000 0x0 0x0
  354. 0x0 0x100000>;
  355. uli1575@0 {
  356. reg = <0x0 0x0 0x0 0x0 0x0>;
  357. #size-cells = <2>;
  358. #address-cells = <3>;
  359. ranges = <0x2000000 0x0 0xb0000000
  360. 0x2000000 0x0 0xb0000000
  361. 0x0 0x100000
  362. 0x1000000 0x0 0x0
  363. 0x1000000 0x0 0x0
  364. 0x0 0x100000>;
  365. isa@1e {
  366. device_type = "isa";
  367. #interrupt-cells = <2>;
  368. #size-cells = <1>;
  369. #address-cells = <2>;
  370. reg = <0xf000 0x0 0x0 0x0 0x0>;
  371. ranges = <0x1 0x0
  372. 0x1000000 0x0 0x0
  373. 0x1000>;
  374. interrupt-parent = <&i8259>;
  375. i8259: interrupt-controller@20 {
  376. reg = <0x1 0x20 0x2
  377. 0x1 0xa0 0x2
  378. 0x1 0x4d0 0x2>;
  379. interrupt-controller;
  380. device_type = "interrupt-controller";
  381. #address-cells = <0>;
  382. #interrupt-cells = <2>;
  383. compatible = "chrp,iic";
  384. interrupts = <9 2>;
  385. interrupt-parent = <&mpic>;
  386. };
  387. i8042@60 {
  388. #size-cells = <0>;
  389. #address-cells = <1>;
  390. reg = <0x1 0x60 0x1 0x1 0x64 0x1>;
  391. interrupts = <1 3 12 3>;
  392. interrupt-parent = <&i8259>;
  393. keyboard@0 {
  394. reg = <0x0>;
  395. compatible = "pnpPNP,303";
  396. };
  397. mouse@1 {
  398. reg = <0x1>;
  399. compatible = "pnpPNP,f03";
  400. };
  401. };
  402. rtc@70 {
  403. compatible = "pnpPNP,b00";
  404. reg = <0x1 0x70 0x2>;
  405. };
  406. gpio@400 {
  407. reg = <0x1 0x400 0x80>;
  408. };
  409. };
  410. };
  411. };
  412. };
  413. };