dm1105.c 29 KB

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  1. /*
  2. * dm1105.c - driver for DVB cards based on SDMC DM1105 PCI chip
  3. *
  4. * Copyright (C) 2008 Igor M. Liplianin <liplianin@me.by>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19. *
  20. */
  21. #include <linux/i2c.h>
  22. #include <linux/i2c-algo-bit.h>
  23. #include <linux/init.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/kernel.h>
  26. #include <linux/module.h>
  27. #include <linux/proc_fs.h>
  28. #include <linux/pci.h>
  29. #include <linux/dma-mapping.h>
  30. #include <linux/slab.h>
  31. #include <media/rc-core.h>
  32. #include "demux.h"
  33. #include "dmxdev.h"
  34. #include "dvb_demux.h"
  35. #include "dvb_frontend.h"
  36. #include "dvb_net.h"
  37. #include "dvbdev.h"
  38. #include "dvb-pll.h"
  39. #include "stv0299.h"
  40. #include "stv0288.h"
  41. #include "stb6000.h"
  42. #include "si21xx.h"
  43. #include "cx24116.h"
  44. #include "z0194a.h"
  45. #include "ts2020.h"
  46. #include "ds3000.h"
  47. #define MODULE_NAME "dm1105"
  48. #define UNSET (-1U)
  49. #define DM1105_BOARD_NOAUTO UNSET
  50. #define DM1105_BOARD_UNKNOWN 0
  51. #define DM1105_BOARD_DVBWORLD_2002 1
  52. #define DM1105_BOARD_DVBWORLD_2004 2
  53. #define DM1105_BOARD_AXESS_DM05 3
  54. #define DM1105_BOARD_UNBRANDED_I2C_ON_GPIO 4
  55. /* ----------------------------------------------- */
  56. /*
  57. * PCI ID's
  58. */
  59. #ifndef PCI_VENDOR_ID_TRIGEM
  60. #define PCI_VENDOR_ID_TRIGEM 0x109f
  61. #endif
  62. #ifndef PCI_VENDOR_ID_AXESS
  63. #define PCI_VENDOR_ID_AXESS 0x195d
  64. #endif
  65. #ifndef PCI_DEVICE_ID_DM1105
  66. #define PCI_DEVICE_ID_DM1105 0x036f
  67. #endif
  68. #ifndef PCI_DEVICE_ID_DW2002
  69. #define PCI_DEVICE_ID_DW2002 0x2002
  70. #endif
  71. #ifndef PCI_DEVICE_ID_DW2004
  72. #define PCI_DEVICE_ID_DW2004 0x2004
  73. #endif
  74. #ifndef PCI_DEVICE_ID_DM05
  75. #define PCI_DEVICE_ID_DM05 0x1105
  76. #endif
  77. /* ----------------------------------------------- */
  78. /* sdmc dm1105 registers */
  79. /* TS Control */
  80. #define DM1105_TSCTR 0x00
  81. #define DM1105_DTALENTH 0x04
  82. /* GPIO Interface */
  83. #define DM1105_GPIOVAL 0x08
  84. #define DM1105_GPIOCTR 0x0c
  85. /* PID serial number */
  86. #define DM1105_PIDN 0x10
  87. /* Odd-even secret key select */
  88. #define DM1105_CWSEL 0x14
  89. /* Host Command Interface */
  90. #define DM1105_HOST_CTR 0x18
  91. #define DM1105_HOST_AD 0x1c
  92. /* PCI Interface */
  93. #define DM1105_CR 0x30
  94. #define DM1105_RST 0x34
  95. #define DM1105_STADR 0x38
  96. #define DM1105_RLEN 0x3c
  97. #define DM1105_WRP 0x40
  98. #define DM1105_INTCNT 0x44
  99. #define DM1105_INTMAK 0x48
  100. #define DM1105_INTSTS 0x4c
  101. /* CW Value */
  102. #define DM1105_ODD 0x50
  103. #define DM1105_EVEN 0x58
  104. /* PID Value */
  105. #define DM1105_PID 0x60
  106. /* IR Control */
  107. #define DM1105_IRCTR 0x64
  108. #define DM1105_IRMODE 0x68
  109. #define DM1105_SYSTEMCODE 0x6c
  110. #define DM1105_IRCODE 0x70
  111. /* Unknown Values */
  112. #define DM1105_ENCRYPT 0x74
  113. #define DM1105_VER 0x7c
  114. /* I2C Interface */
  115. #define DM1105_I2CCTR 0x80
  116. #define DM1105_I2CSTS 0x81
  117. #define DM1105_I2CDAT 0x82
  118. #define DM1105_I2C_RA 0x83
  119. /* ----------------------------------------------- */
  120. /* Interrupt Mask Bits */
  121. #define INTMAK_TSIRQM 0x01
  122. #define INTMAK_HIRQM 0x04
  123. #define INTMAK_IRM 0x08
  124. #define INTMAK_ALLMASK (INTMAK_TSIRQM | \
  125. INTMAK_HIRQM | \
  126. INTMAK_IRM)
  127. #define INTMAK_NONEMASK 0x00
  128. /* Interrupt Status Bits */
  129. #define INTSTS_TSIRQ 0x01
  130. #define INTSTS_HIRQ 0x04
  131. #define INTSTS_IR 0x08
  132. /* IR Control Bits */
  133. #define DM1105_IR_EN 0x01
  134. #define DM1105_SYS_CHK 0x02
  135. #define DM1105_REP_FLG 0x08
  136. /* EEPROM addr */
  137. #define IIC_24C01_addr 0xa0
  138. /* Max board count */
  139. #define DM1105_MAX 0x04
  140. #define DRIVER_NAME "dm1105"
  141. #define DM1105_I2C_GPIO_NAME "dm1105-gpio"
  142. #define DM1105_DMA_PACKETS 47
  143. #define DM1105_DMA_PACKET_LENGTH (128*4)
  144. #define DM1105_DMA_BYTES (128 * 4 * DM1105_DMA_PACKETS)
  145. /* */
  146. #define GPIO08 (1 << 8)
  147. #define GPIO13 (1 << 13)
  148. #define GPIO14 (1 << 14)
  149. #define GPIO15 (1 << 15)
  150. #define GPIO16 (1 << 16)
  151. #define GPIO17 (1 << 17)
  152. #define GPIO_ALL 0x03ffff
  153. /* GPIO's for LNB power control */
  154. #define DM1105_LNB_MASK (GPIO_ALL & ~(GPIO14 | GPIO13))
  155. #define DM1105_LNB_OFF GPIO17
  156. #define DM1105_LNB_13V (GPIO16 | GPIO08)
  157. #define DM1105_LNB_18V GPIO08
  158. /* GPIO's for LNB power control for Axess DM05 */
  159. #define DM05_LNB_MASK (GPIO_ALL & ~(GPIO14 | GPIO13))
  160. #define DM05_LNB_OFF GPIO17/* actually 13v */
  161. #define DM05_LNB_13V GPIO17
  162. #define DM05_LNB_18V (GPIO17 | GPIO16)
  163. /* GPIO's for LNB power control for unbranded with I2C on GPIO */
  164. #define UNBR_LNB_MASK (GPIO17 | GPIO16)
  165. #define UNBR_LNB_OFF 0
  166. #define UNBR_LNB_13V GPIO17
  167. #define UNBR_LNB_18V (GPIO17 | GPIO16)
  168. static unsigned int card[] = {[0 ... 3] = UNSET };
  169. module_param_array(card, int, NULL, 0444);
  170. MODULE_PARM_DESC(card, "card type");
  171. static int ir_debug;
  172. module_param(ir_debug, int, 0644);
  173. MODULE_PARM_DESC(ir_debug, "enable debugging information for IR decoding");
  174. static unsigned int dm1105_devcount;
  175. DVB_DEFINE_MOD_OPT_ADAPTER_NR(adapter_nr);
  176. struct dm1105_board {
  177. char *name;
  178. struct {
  179. u32 mask, off, v13, v18;
  180. } lnb;
  181. u32 gpio_scl, gpio_sda;
  182. };
  183. struct dm1105_subid {
  184. u16 subvendor;
  185. u16 subdevice;
  186. u32 card;
  187. };
  188. static const struct dm1105_board dm1105_boards[] = {
  189. [DM1105_BOARD_UNKNOWN] = {
  190. .name = "UNKNOWN/GENERIC",
  191. .lnb = {
  192. .mask = DM1105_LNB_MASK,
  193. .off = DM1105_LNB_OFF,
  194. .v13 = DM1105_LNB_13V,
  195. .v18 = DM1105_LNB_18V,
  196. },
  197. },
  198. [DM1105_BOARD_DVBWORLD_2002] = {
  199. .name = "DVBWorld PCI 2002",
  200. .lnb = {
  201. .mask = DM1105_LNB_MASK,
  202. .off = DM1105_LNB_OFF,
  203. .v13 = DM1105_LNB_13V,
  204. .v18 = DM1105_LNB_18V,
  205. },
  206. },
  207. [DM1105_BOARD_DVBWORLD_2004] = {
  208. .name = "DVBWorld PCI 2004",
  209. .lnb = {
  210. .mask = DM1105_LNB_MASK,
  211. .off = DM1105_LNB_OFF,
  212. .v13 = DM1105_LNB_13V,
  213. .v18 = DM1105_LNB_18V,
  214. },
  215. },
  216. [DM1105_BOARD_AXESS_DM05] = {
  217. .name = "Axess/EasyTv DM05",
  218. .lnb = {
  219. .mask = DM05_LNB_MASK,
  220. .off = DM05_LNB_OFF,
  221. .v13 = DM05_LNB_13V,
  222. .v18 = DM05_LNB_18V,
  223. },
  224. },
  225. [DM1105_BOARD_UNBRANDED_I2C_ON_GPIO] = {
  226. .name = "Unbranded DM1105 with i2c on GPIOs",
  227. .lnb = {
  228. .mask = UNBR_LNB_MASK,
  229. .off = UNBR_LNB_OFF,
  230. .v13 = UNBR_LNB_13V,
  231. .v18 = UNBR_LNB_18V,
  232. },
  233. .gpio_scl = GPIO14,
  234. .gpio_sda = GPIO13,
  235. },
  236. };
  237. static const struct dm1105_subid dm1105_subids[] = {
  238. {
  239. .subvendor = 0x0000,
  240. .subdevice = 0x2002,
  241. .card = DM1105_BOARD_DVBWORLD_2002,
  242. }, {
  243. .subvendor = 0x0001,
  244. .subdevice = 0x2002,
  245. .card = DM1105_BOARD_DVBWORLD_2002,
  246. }, {
  247. .subvendor = 0x0000,
  248. .subdevice = 0x2004,
  249. .card = DM1105_BOARD_DVBWORLD_2004,
  250. }, {
  251. .subvendor = 0x0001,
  252. .subdevice = 0x2004,
  253. .card = DM1105_BOARD_DVBWORLD_2004,
  254. }, {
  255. .subvendor = 0x195d,
  256. .subdevice = 0x1105,
  257. .card = DM1105_BOARD_AXESS_DM05,
  258. },
  259. };
  260. static void dm1105_card_list(struct pci_dev *pci)
  261. {
  262. int i;
  263. if (0 == pci->subsystem_vendor &&
  264. 0 == pci->subsystem_device) {
  265. printk(KERN_ERR
  266. "dm1105: Your board has no valid PCI Subsystem ID\n"
  267. "dm1105: and thus can't be autodetected\n"
  268. "dm1105: Please pass card=<n> insmod option to\n"
  269. "dm1105: workaround that. Redirect complaints to\n"
  270. "dm1105: the vendor of the TV card. Best regards,\n"
  271. "dm1105: -- tux\n");
  272. } else {
  273. printk(KERN_ERR
  274. "dm1105: Your board isn't known (yet) to the driver.\n"
  275. "dm1105: You can try to pick one of the existing\n"
  276. "dm1105: card configs via card=<n> insmod option.\n"
  277. "dm1105: Updating to the latest version might help\n"
  278. "dm1105: as well.\n");
  279. }
  280. printk(KERN_ERR "Here is a list of valid choices for the card=<n> "
  281. "insmod option:\n");
  282. for (i = 0; i < ARRAY_SIZE(dm1105_boards); i++)
  283. printk(KERN_ERR "dm1105: card=%d -> %s\n",
  284. i, dm1105_boards[i].name);
  285. }
  286. /* infrared remote control */
  287. struct infrared {
  288. struct rc_dev *dev;
  289. char input_phys[32];
  290. struct work_struct work;
  291. u32 ir_command;
  292. };
  293. struct dm1105_dev {
  294. /* pci */
  295. struct pci_dev *pdev;
  296. u8 __iomem *io_mem;
  297. /* ir */
  298. struct infrared ir;
  299. /* dvb */
  300. struct dmx_frontend hw_frontend;
  301. struct dmx_frontend mem_frontend;
  302. struct dmxdev dmxdev;
  303. struct dvb_adapter dvb_adapter;
  304. struct dvb_demux demux;
  305. struct dvb_frontend *fe;
  306. struct dvb_net dvbnet;
  307. unsigned int full_ts_users;
  308. unsigned int boardnr;
  309. int nr;
  310. /* i2c */
  311. struct i2c_adapter i2c_adap;
  312. struct i2c_adapter i2c_bb_adap;
  313. struct i2c_algo_bit_data i2c_bit;
  314. /* irq */
  315. struct work_struct work;
  316. struct workqueue_struct *wq;
  317. char wqn[16];
  318. /* dma */
  319. dma_addr_t dma_addr;
  320. unsigned char *ts_buf;
  321. u32 wrp;
  322. u32 nextwrp;
  323. u32 buffer_size;
  324. unsigned int PacketErrorCount;
  325. unsigned int dmarst;
  326. spinlock_t lock;
  327. };
  328. #define dm_io_mem(reg) ((unsigned long)(&dev->io_mem[reg]))
  329. #define dm_readb(reg) inb(dm_io_mem(reg))
  330. #define dm_writeb(reg, value) outb((value), (dm_io_mem(reg)))
  331. #define dm_readw(reg) inw(dm_io_mem(reg))
  332. #define dm_writew(reg, value) outw((value), (dm_io_mem(reg)))
  333. #define dm_readl(reg) inl(dm_io_mem(reg))
  334. #define dm_writel(reg, value) outl((value), (dm_io_mem(reg)))
  335. #define dm_andorl(reg, mask, value) \
  336. outl((inl(dm_io_mem(reg)) & ~(mask)) |\
  337. ((value) & (mask)), (dm_io_mem(reg)))
  338. #define dm_setl(reg, bit) dm_andorl((reg), (bit), (bit))
  339. #define dm_clearl(reg, bit) dm_andorl((reg), (bit), 0)
  340. /* The chip has 18 GPIOs. In HOST mode GPIO's used as 15 bit address lines,
  341. so we can use only 3 GPIO's from GPIO15 to GPIO17.
  342. Here I don't check whether HOST is enebled as it is not implemented yet.
  343. */
  344. static void dm1105_gpio_set(struct dm1105_dev *dev, u32 mask)
  345. {
  346. if (mask & 0xfffc0000)
  347. printk(KERN_ERR "%s: Only 18 GPIO's are allowed\n", __func__);
  348. if (mask & 0x0003ffff)
  349. dm_setl(DM1105_GPIOVAL, mask & 0x0003ffff);
  350. }
  351. static void dm1105_gpio_clear(struct dm1105_dev *dev, u32 mask)
  352. {
  353. if (mask & 0xfffc0000)
  354. printk(KERN_ERR "%s: Only 18 GPIO's are allowed\n", __func__);
  355. if (mask & 0x0003ffff)
  356. dm_clearl(DM1105_GPIOVAL, mask & 0x0003ffff);
  357. }
  358. static void dm1105_gpio_andor(struct dm1105_dev *dev, u32 mask, u32 val)
  359. {
  360. if (mask & 0xfffc0000)
  361. printk(KERN_ERR "%s: Only 18 GPIO's are allowed\n", __func__);
  362. if (mask & 0x0003ffff)
  363. dm_andorl(DM1105_GPIOVAL, mask & 0x0003ffff, val);
  364. }
  365. static u32 dm1105_gpio_get(struct dm1105_dev *dev, u32 mask)
  366. {
  367. if (mask & 0xfffc0000)
  368. printk(KERN_ERR "%s: Only 18 GPIO's are allowed\n", __func__);
  369. if (mask & 0x0003ffff)
  370. return dm_readl(DM1105_GPIOVAL) & mask & 0x0003ffff;
  371. return 0;
  372. }
  373. static void dm1105_gpio_enable(struct dm1105_dev *dev, u32 mask, int asoutput)
  374. {
  375. if (mask & 0xfffc0000)
  376. printk(KERN_ERR "%s: Only 18 GPIO's are allowed\n", __func__);
  377. if ((mask & 0x0003ffff) && asoutput)
  378. dm_clearl(DM1105_GPIOCTR, mask & 0x0003ffff);
  379. else if ((mask & 0x0003ffff) && !asoutput)
  380. dm_setl(DM1105_GPIOCTR, mask & 0x0003ffff);
  381. }
  382. static void dm1105_setline(struct dm1105_dev *dev, u32 line, int state)
  383. {
  384. if (state)
  385. dm1105_gpio_enable(dev, line, 0);
  386. else {
  387. dm1105_gpio_enable(dev, line, 1);
  388. dm1105_gpio_clear(dev, line);
  389. }
  390. }
  391. static void dm1105_setsda(void *data, int state)
  392. {
  393. struct dm1105_dev *dev = data;
  394. dm1105_setline(dev, dm1105_boards[dev->boardnr].gpio_sda, state);
  395. }
  396. static void dm1105_setscl(void *data, int state)
  397. {
  398. struct dm1105_dev *dev = data;
  399. dm1105_setline(dev, dm1105_boards[dev->boardnr].gpio_scl, state);
  400. }
  401. static int dm1105_getsda(void *data)
  402. {
  403. struct dm1105_dev *dev = data;
  404. return dm1105_gpio_get(dev, dm1105_boards[dev->boardnr].gpio_sda)
  405. ? 1 : 0;
  406. }
  407. static int dm1105_getscl(void *data)
  408. {
  409. struct dm1105_dev *dev = data;
  410. return dm1105_gpio_get(dev, dm1105_boards[dev->boardnr].gpio_scl)
  411. ? 1 : 0;
  412. }
  413. static int dm1105_i2c_xfer(struct i2c_adapter *i2c_adap,
  414. struct i2c_msg *msgs, int num)
  415. {
  416. struct dm1105_dev *dev ;
  417. int addr, rc, i, j, k, len, byte, data;
  418. u8 status;
  419. dev = i2c_adap->algo_data;
  420. for (i = 0; i < num; i++) {
  421. dm_writeb(DM1105_I2CCTR, 0x00);
  422. if (msgs[i].flags & I2C_M_RD) {
  423. /* read bytes */
  424. addr = msgs[i].addr << 1;
  425. addr |= 1;
  426. dm_writeb(DM1105_I2CDAT, addr);
  427. for (byte = 0; byte < msgs[i].len; byte++)
  428. dm_writeb(DM1105_I2CDAT + byte + 1, 0);
  429. dm_writeb(DM1105_I2CCTR, 0x81 + msgs[i].len);
  430. for (j = 0; j < 55; j++) {
  431. mdelay(10);
  432. status = dm_readb(DM1105_I2CSTS);
  433. if ((status & 0xc0) == 0x40)
  434. break;
  435. }
  436. if (j >= 55)
  437. return -1;
  438. for (byte = 0; byte < msgs[i].len; byte++) {
  439. rc = dm_readb(DM1105_I2CDAT + byte + 1);
  440. if (rc < 0)
  441. goto err;
  442. msgs[i].buf[byte] = rc;
  443. }
  444. } else if ((msgs[i].buf[0] == 0xf7) && (msgs[i].addr == 0x55)) {
  445. /* prepaired for cx24116 firmware */
  446. /* Write in small blocks */
  447. len = msgs[i].len - 1;
  448. k = 1;
  449. do {
  450. dm_writeb(DM1105_I2CDAT, msgs[i].addr << 1);
  451. dm_writeb(DM1105_I2CDAT + 1, 0xf7);
  452. for (byte = 0; byte < (len > 48 ? 48 : len); byte++) {
  453. data = msgs[i].buf[k + byte];
  454. dm_writeb(DM1105_I2CDAT + byte + 2, data);
  455. }
  456. dm_writeb(DM1105_I2CCTR, 0x82 + (len > 48 ? 48 : len));
  457. for (j = 0; j < 25; j++) {
  458. mdelay(10);
  459. status = dm_readb(DM1105_I2CSTS);
  460. if ((status & 0xc0) == 0x40)
  461. break;
  462. }
  463. if (j >= 25)
  464. return -1;
  465. k += 48;
  466. len -= 48;
  467. } while (len > 0);
  468. } else {
  469. /* write bytes */
  470. dm_writeb(DM1105_I2CDAT, msgs[i].addr << 1);
  471. for (byte = 0; byte < msgs[i].len; byte++) {
  472. data = msgs[i].buf[byte];
  473. dm_writeb(DM1105_I2CDAT + byte + 1, data);
  474. }
  475. dm_writeb(DM1105_I2CCTR, 0x81 + msgs[i].len);
  476. for (j = 0; j < 25; j++) {
  477. mdelay(10);
  478. status = dm_readb(DM1105_I2CSTS);
  479. if ((status & 0xc0) == 0x40)
  480. break;
  481. }
  482. if (j >= 25)
  483. return -1;
  484. }
  485. }
  486. return num;
  487. err:
  488. return rc;
  489. }
  490. static u32 functionality(struct i2c_adapter *adap)
  491. {
  492. return I2C_FUNC_I2C;
  493. }
  494. static struct i2c_algorithm dm1105_algo = {
  495. .master_xfer = dm1105_i2c_xfer,
  496. .functionality = functionality,
  497. };
  498. static inline struct dm1105_dev *feed_to_dm1105_dev(struct dvb_demux_feed *feed)
  499. {
  500. return container_of(feed->demux, struct dm1105_dev, demux);
  501. }
  502. static inline struct dm1105_dev *frontend_to_dm1105_dev(struct dvb_frontend *fe)
  503. {
  504. return container_of(fe->dvb, struct dm1105_dev, dvb_adapter);
  505. }
  506. static int dm1105_set_voltage(struct dvb_frontend *fe, fe_sec_voltage_t voltage)
  507. {
  508. struct dm1105_dev *dev = frontend_to_dm1105_dev(fe);
  509. dm1105_gpio_enable(dev, dm1105_boards[dev->boardnr].lnb.mask, 1);
  510. if (voltage == SEC_VOLTAGE_18)
  511. dm1105_gpio_andor(dev,
  512. dm1105_boards[dev->boardnr].lnb.mask,
  513. dm1105_boards[dev->boardnr].lnb.v18);
  514. else if (voltage == SEC_VOLTAGE_13)
  515. dm1105_gpio_andor(dev,
  516. dm1105_boards[dev->boardnr].lnb.mask,
  517. dm1105_boards[dev->boardnr].lnb.v13);
  518. else
  519. dm1105_gpio_andor(dev,
  520. dm1105_boards[dev->boardnr].lnb.mask,
  521. dm1105_boards[dev->boardnr].lnb.off);
  522. return 0;
  523. }
  524. static void dm1105_set_dma_addr(struct dm1105_dev *dev)
  525. {
  526. dm_writel(DM1105_STADR, cpu_to_le32(dev->dma_addr));
  527. }
  528. static int __devinit dm1105_dma_map(struct dm1105_dev *dev)
  529. {
  530. dev->ts_buf = pci_alloc_consistent(dev->pdev,
  531. 6 * DM1105_DMA_BYTES,
  532. &dev->dma_addr);
  533. return !dev->ts_buf;
  534. }
  535. static void dm1105_dma_unmap(struct dm1105_dev *dev)
  536. {
  537. pci_free_consistent(dev->pdev,
  538. 6 * DM1105_DMA_BYTES,
  539. dev->ts_buf,
  540. dev->dma_addr);
  541. }
  542. static void dm1105_enable_irqs(struct dm1105_dev *dev)
  543. {
  544. dm_writeb(DM1105_INTMAK, INTMAK_ALLMASK);
  545. dm_writeb(DM1105_CR, 1);
  546. }
  547. static void dm1105_disable_irqs(struct dm1105_dev *dev)
  548. {
  549. dm_writeb(DM1105_INTMAK, INTMAK_IRM);
  550. dm_writeb(DM1105_CR, 0);
  551. }
  552. static int dm1105_start_feed(struct dvb_demux_feed *f)
  553. {
  554. struct dm1105_dev *dev = feed_to_dm1105_dev(f);
  555. if (dev->full_ts_users++ == 0)
  556. dm1105_enable_irqs(dev);
  557. return 0;
  558. }
  559. static int dm1105_stop_feed(struct dvb_demux_feed *f)
  560. {
  561. struct dm1105_dev *dev = feed_to_dm1105_dev(f);
  562. if (--dev->full_ts_users == 0)
  563. dm1105_disable_irqs(dev);
  564. return 0;
  565. }
  566. /* ir work handler */
  567. static void dm1105_emit_key(struct work_struct *work)
  568. {
  569. struct infrared *ir = container_of(work, struct infrared, work);
  570. u32 ircom = ir->ir_command;
  571. u8 data;
  572. if (ir_debug)
  573. printk(KERN_INFO "%s: received byte 0x%04x\n", __func__, ircom);
  574. data = (ircom >> 8) & 0x7f;
  575. rc_keydown(ir->dev, data, 0);
  576. }
  577. /* work handler */
  578. static void dm1105_dmx_buffer(struct work_struct *work)
  579. {
  580. struct dm1105_dev *dev = container_of(work, struct dm1105_dev, work);
  581. unsigned int nbpackets;
  582. u32 oldwrp = dev->wrp;
  583. u32 nextwrp = dev->nextwrp;
  584. if (!((dev->ts_buf[oldwrp] == 0x47) &&
  585. (dev->ts_buf[oldwrp + 188] == 0x47) &&
  586. (dev->ts_buf[oldwrp + 188 * 2] == 0x47))) {
  587. dev->PacketErrorCount++;
  588. /* bad packet found */
  589. if ((dev->PacketErrorCount >= 2) &&
  590. (dev->dmarst == 0)) {
  591. dm_writeb(DM1105_RST, 1);
  592. dev->wrp = 0;
  593. dev->PacketErrorCount = 0;
  594. dev->dmarst = 0;
  595. return;
  596. }
  597. }
  598. if (nextwrp < oldwrp) {
  599. memcpy(dev->ts_buf + dev->buffer_size, dev->ts_buf, nextwrp);
  600. nbpackets = ((dev->buffer_size - oldwrp) + nextwrp) / 188;
  601. } else
  602. nbpackets = (nextwrp - oldwrp) / 188;
  603. dev->wrp = nextwrp;
  604. dvb_dmx_swfilter_packets(&dev->demux, &dev->ts_buf[oldwrp], nbpackets);
  605. }
  606. static irqreturn_t dm1105_irq(int irq, void *dev_id)
  607. {
  608. struct dm1105_dev *dev = dev_id;
  609. /* Read-Write INSTS Ack's Interrupt for DM1105 chip 16.03.2008 */
  610. unsigned int intsts = dm_readb(DM1105_INTSTS);
  611. dm_writeb(DM1105_INTSTS, intsts);
  612. switch (intsts) {
  613. case INTSTS_TSIRQ:
  614. case (INTSTS_TSIRQ | INTSTS_IR):
  615. dev->nextwrp = dm_readl(DM1105_WRP) - dm_readl(DM1105_STADR);
  616. queue_work(dev->wq, &dev->work);
  617. break;
  618. case INTSTS_IR:
  619. dev->ir.ir_command = dm_readl(DM1105_IRCODE);
  620. schedule_work(&dev->ir.work);
  621. break;
  622. }
  623. return IRQ_HANDLED;
  624. }
  625. static int __devinit dm1105_ir_init(struct dm1105_dev *dm1105)
  626. {
  627. struct rc_dev *dev;
  628. int err = -ENOMEM;
  629. dev = rc_allocate_device();
  630. if (!dev)
  631. return -ENOMEM;
  632. snprintf(dm1105->ir.input_phys, sizeof(dm1105->ir.input_phys),
  633. "pci-%s/ir0", pci_name(dm1105->pdev));
  634. dev->driver_name = MODULE_NAME;
  635. dev->map_name = RC_MAP_DM1105_NEC;
  636. dev->driver_type = RC_DRIVER_SCANCODE;
  637. dev->input_name = "DVB on-card IR receiver";
  638. dev->input_phys = dm1105->ir.input_phys;
  639. dev->input_id.bustype = BUS_PCI;
  640. dev->input_id.version = 1;
  641. if (dm1105->pdev->subsystem_vendor) {
  642. dev->input_id.vendor = dm1105->pdev->subsystem_vendor;
  643. dev->input_id.product = dm1105->pdev->subsystem_device;
  644. } else {
  645. dev->input_id.vendor = dm1105->pdev->vendor;
  646. dev->input_id.product = dm1105->pdev->device;
  647. }
  648. dev->dev.parent = &dm1105->pdev->dev;
  649. INIT_WORK(&dm1105->ir.work, dm1105_emit_key);
  650. err = rc_register_device(dev);
  651. if (err < 0) {
  652. rc_free_device(dev);
  653. return err;
  654. }
  655. dm1105->ir.dev = dev;
  656. return 0;
  657. }
  658. static void __devexit dm1105_ir_exit(struct dm1105_dev *dm1105)
  659. {
  660. rc_unregister_device(dm1105->ir.dev);
  661. }
  662. static int __devinit dm1105_hw_init(struct dm1105_dev *dev)
  663. {
  664. dm1105_disable_irqs(dev);
  665. dm_writeb(DM1105_HOST_CTR, 0);
  666. /*DATALEN 188,*/
  667. dm_writeb(DM1105_DTALENTH, 188);
  668. /*TS_STRT TS_VALP MSBFIRST TS_MODE ALPAS TSPES*/
  669. dm_writew(DM1105_TSCTR, 0xc10a);
  670. /* map DMA and set address */
  671. dm1105_dma_map(dev);
  672. dm1105_set_dma_addr(dev);
  673. /* big buffer */
  674. dm_writel(DM1105_RLEN, 5 * DM1105_DMA_BYTES);
  675. dm_writeb(DM1105_INTCNT, 47);
  676. /* IR NEC mode enable */
  677. dm_writeb(DM1105_IRCTR, (DM1105_IR_EN | DM1105_SYS_CHK));
  678. dm_writeb(DM1105_IRMODE, 0);
  679. dm_writew(DM1105_SYSTEMCODE, 0);
  680. return 0;
  681. }
  682. static void dm1105_hw_exit(struct dm1105_dev *dev)
  683. {
  684. dm1105_disable_irqs(dev);
  685. /* IR disable */
  686. dm_writeb(DM1105_IRCTR, 0);
  687. dm_writeb(DM1105_INTMAK, INTMAK_NONEMASK);
  688. dm1105_dma_unmap(dev);
  689. }
  690. static struct stv0299_config sharp_z0194a_config = {
  691. .demod_address = 0x68,
  692. .inittab = sharp_z0194a_inittab,
  693. .mclk = 88000000UL,
  694. .invert = 1,
  695. .skip_reinit = 0,
  696. .lock_output = STV0299_LOCKOUTPUT_1,
  697. .volt13_op0_op1 = STV0299_VOLT13_OP1,
  698. .min_delay_ms = 100,
  699. .set_symbol_rate = sharp_z0194a_set_symbol_rate,
  700. };
  701. static struct stv0288_config earda_config = {
  702. .demod_address = 0x68,
  703. .min_delay_ms = 100,
  704. };
  705. static struct si21xx_config serit_config = {
  706. .demod_address = 0x68,
  707. .min_delay_ms = 100,
  708. };
  709. static struct cx24116_config serit_sp2633_config = {
  710. .demod_address = 0x55,
  711. };
  712. static struct ds3000_config dvbworld_ds3000_config = {
  713. .demod_address = 0x68,
  714. };
  715. static struct ts2020_config dvbworld_ts2020_config = {
  716. .tuner_address = 0x60,
  717. };
  718. static int __devinit frontend_init(struct dm1105_dev *dev)
  719. {
  720. int ret;
  721. switch (dev->boardnr) {
  722. case DM1105_BOARD_UNBRANDED_I2C_ON_GPIO:
  723. dm1105_gpio_enable(dev, GPIO15, 1);
  724. dm1105_gpio_clear(dev, GPIO15);
  725. msleep(100);
  726. dm1105_gpio_set(dev, GPIO15);
  727. msleep(200);
  728. dev->fe = dvb_attach(
  729. stv0299_attach, &sharp_z0194a_config,
  730. &dev->i2c_bb_adap);
  731. if (dev->fe) {
  732. dev->fe->ops.set_voltage = dm1105_set_voltage;
  733. dvb_attach(dvb_pll_attach, dev->fe, 0x60,
  734. &dev->i2c_bb_adap, DVB_PLL_OPERA1);
  735. break;
  736. }
  737. dev->fe = dvb_attach(
  738. stv0288_attach, &earda_config,
  739. &dev->i2c_bb_adap);
  740. if (dev->fe) {
  741. dev->fe->ops.set_voltage = dm1105_set_voltage;
  742. dvb_attach(stb6000_attach, dev->fe, 0x61,
  743. &dev->i2c_bb_adap);
  744. break;
  745. }
  746. dev->fe = dvb_attach(
  747. si21xx_attach, &serit_config,
  748. &dev->i2c_bb_adap);
  749. if (dev->fe)
  750. dev->fe->ops.set_voltage = dm1105_set_voltage;
  751. break;
  752. case DM1105_BOARD_DVBWORLD_2004:
  753. dev->fe = dvb_attach(
  754. cx24116_attach, &serit_sp2633_config,
  755. &dev->i2c_adap);
  756. if (dev->fe) {
  757. dev->fe->ops.set_voltage = dm1105_set_voltage;
  758. break;
  759. }
  760. dev->fe = dvb_attach(
  761. ds3000_attach, &dvbworld_ds3000_config,
  762. &dev->i2c_adap);
  763. if (dev->fe) {
  764. dvb_attach(ts2020_attach, dev->fe,
  765. &dvbworld_ts2020_config, &dev->i2c_adap);
  766. dev->fe->ops.set_voltage = dm1105_set_voltage;
  767. }
  768. break;
  769. case DM1105_BOARD_DVBWORLD_2002:
  770. case DM1105_BOARD_AXESS_DM05:
  771. default:
  772. dev->fe = dvb_attach(
  773. stv0299_attach, &sharp_z0194a_config,
  774. &dev->i2c_adap);
  775. if (dev->fe) {
  776. dev->fe->ops.set_voltage = dm1105_set_voltage;
  777. dvb_attach(dvb_pll_attach, dev->fe, 0x60,
  778. &dev->i2c_adap, DVB_PLL_OPERA1);
  779. break;
  780. }
  781. dev->fe = dvb_attach(
  782. stv0288_attach, &earda_config,
  783. &dev->i2c_adap);
  784. if (dev->fe) {
  785. dev->fe->ops.set_voltage = dm1105_set_voltage;
  786. dvb_attach(stb6000_attach, dev->fe, 0x61,
  787. &dev->i2c_adap);
  788. break;
  789. }
  790. dev->fe = dvb_attach(
  791. si21xx_attach, &serit_config,
  792. &dev->i2c_adap);
  793. if (dev->fe)
  794. dev->fe->ops.set_voltage = dm1105_set_voltage;
  795. }
  796. if (!dev->fe) {
  797. dev_err(&dev->pdev->dev, "could not attach frontend\n");
  798. return -ENODEV;
  799. }
  800. ret = dvb_register_frontend(&dev->dvb_adapter, dev->fe);
  801. if (ret < 0) {
  802. if (dev->fe->ops.release)
  803. dev->fe->ops.release(dev->fe);
  804. dev->fe = NULL;
  805. return ret;
  806. }
  807. return 0;
  808. }
  809. static void __devinit dm1105_read_mac(struct dm1105_dev *dev, u8 *mac)
  810. {
  811. static u8 command[1] = { 0x28 };
  812. struct i2c_msg msg[] = {
  813. {
  814. .addr = IIC_24C01_addr >> 1,
  815. .flags = 0,
  816. .buf = command,
  817. .len = 1
  818. }, {
  819. .addr = IIC_24C01_addr >> 1,
  820. .flags = I2C_M_RD,
  821. .buf = mac,
  822. .len = 6
  823. },
  824. };
  825. dm1105_i2c_xfer(&dev->i2c_adap, msg , 2);
  826. dev_info(&dev->pdev->dev, "MAC %pM\n", mac);
  827. }
  828. static int __devinit dm1105_probe(struct pci_dev *pdev,
  829. const struct pci_device_id *ent)
  830. {
  831. struct dm1105_dev *dev;
  832. struct dvb_adapter *dvb_adapter;
  833. struct dvb_demux *dvbdemux;
  834. struct dmx_demux *dmx;
  835. int ret = -ENOMEM;
  836. int i;
  837. dev = kzalloc(sizeof(struct dm1105_dev), GFP_KERNEL);
  838. if (!dev)
  839. return -ENOMEM;
  840. /* board config */
  841. dev->nr = dm1105_devcount;
  842. dev->boardnr = UNSET;
  843. if (card[dev->nr] < ARRAY_SIZE(dm1105_boards))
  844. dev->boardnr = card[dev->nr];
  845. for (i = 0; UNSET == dev->boardnr &&
  846. i < ARRAY_SIZE(dm1105_subids); i++)
  847. if (pdev->subsystem_vendor ==
  848. dm1105_subids[i].subvendor &&
  849. pdev->subsystem_device ==
  850. dm1105_subids[i].subdevice)
  851. dev->boardnr = dm1105_subids[i].card;
  852. if (UNSET == dev->boardnr) {
  853. dev->boardnr = DM1105_BOARD_UNKNOWN;
  854. dm1105_card_list(pdev);
  855. }
  856. dm1105_devcount++;
  857. dev->pdev = pdev;
  858. dev->buffer_size = 5 * DM1105_DMA_BYTES;
  859. dev->PacketErrorCount = 0;
  860. dev->dmarst = 0;
  861. ret = pci_enable_device(pdev);
  862. if (ret < 0)
  863. goto err_kfree;
  864. ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  865. if (ret < 0)
  866. goto err_pci_disable_device;
  867. pci_set_master(pdev);
  868. ret = pci_request_regions(pdev, DRIVER_NAME);
  869. if (ret < 0)
  870. goto err_pci_disable_device;
  871. dev->io_mem = pci_iomap(pdev, 0, pci_resource_len(pdev, 0));
  872. if (!dev->io_mem) {
  873. ret = -EIO;
  874. goto err_pci_release_regions;
  875. }
  876. spin_lock_init(&dev->lock);
  877. pci_set_drvdata(pdev, dev);
  878. ret = dm1105_hw_init(dev);
  879. if (ret < 0)
  880. goto err_pci_iounmap;
  881. /* i2c */
  882. i2c_set_adapdata(&dev->i2c_adap, dev);
  883. strcpy(dev->i2c_adap.name, DRIVER_NAME);
  884. dev->i2c_adap.owner = THIS_MODULE;
  885. dev->i2c_adap.dev.parent = &pdev->dev;
  886. dev->i2c_adap.algo = &dm1105_algo;
  887. dev->i2c_adap.algo_data = dev;
  888. ret = i2c_add_adapter(&dev->i2c_adap);
  889. if (ret < 0)
  890. goto err_dm1105_hw_exit;
  891. i2c_set_adapdata(&dev->i2c_bb_adap, dev);
  892. strcpy(dev->i2c_bb_adap.name, DM1105_I2C_GPIO_NAME);
  893. dev->i2c_bb_adap.owner = THIS_MODULE;
  894. dev->i2c_bb_adap.dev.parent = &pdev->dev;
  895. dev->i2c_bb_adap.algo_data = &dev->i2c_bit;
  896. dev->i2c_bit.data = dev;
  897. dev->i2c_bit.setsda = dm1105_setsda;
  898. dev->i2c_bit.setscl = dm1105_setscl;
  899. dev->i2c_bit.getsda = dm1105_getsda;
  900. dev->i2c_bit.getscl = dm1105_getscl;
  901. dev->i2c_bit.udelay = 10;
  902. dev->i2c_bit.timeout = 10;
  903. /* Raise SCL and SDA */
  904. dm1105_setsda(dev, 1);
  905. dm1105_setscl(dev, 1);
  906. ret = i2c_bit_add_bus(&dev->i2c_bb_adap);
  907. if (ret < 0)
  908. goto err_i2c_del_adapter;
  909. /* dvb */
  910. ret = dvb_register_adapter(&dev->dvb_adapter, DRIVER_NAME,
  911. THIS_MODULE, &pdev->dev, adapter_nr);
  912. if (ret < 0)
  913. goto err_i2c_del_adapters;
  914. dvb_adapter = &dev->dvb_adapter;
  915. dm1105_read_mac(dev, dvb_adapter->proposed_mac);
  916. dvbdemux = &dev->demux;
  917. dvbdemux->filternum = 256;
  918. dvbdemux->feednum = 256;
  919. dvbdemux->start_feed = dm1105_start_feed;
  920. dvbdemux->stop_feed = dm1105_stop_feed;
  921. dvbdemux->dmx.capabilities = (DMX_TS_FILTERING |
  922. DMX_SECTION_FILTERING | DMX_MEMORY_BASED_FILTERING);
  923. ret = dvb_dmx_init(dvbdemux);
  924. if (ret < 0)
  925. goto err_dvb_unregister_adapter;
  926. dmx = &dvbdemux->dmx;
  927. dev->dmxdev.filternum = 256;
  928. dev->dmxdev.demux = dmx;
  929. dev->dmxdev.capabilities = 0;
  930. ret = dvb_dmxdev_init(&dev->dmxdev, dvb_adapter);
  931. if (ret < 0)
  932. goto err_dvb_dmx_release;
  933. dev->hw_frontend.source = DMX_FRONTEND_0;
  934. ret = dmx->add_frontend(dmx, &dev->hw_frontend);
  935. if (ret < 0)
  936. goto err_dvb_dmxdev_release;
  937. dev->mem_frontend.source = DMX_MEMORY_FE;
  938. ret = dmx->add_frontend(dmx, &dev->mem_frontend);
  939. if (ret < 0)
  940. goto err_remove_hw_frontend;
  941. ret = dmx->connect_frontend(dmx, &dev->hw_frontend);
  942. if (ret < 0)
  943. goto err_remove_mem_frontend;
  944. ret = dvb_net_init(dvb_adapter, &dev->dvbnet, dmx);
  945. if (ret < 0)
  946. goto err_disconnect_frontend;
  947. ret = frontend_init(dev);
  948. if (ret < 0)
  949. goto err_dvb_net;
  950. dm1105_ir_init(dev);
  951. INIT_WORK(&dev->work, dm1105_dmx_buffer);
  952. sprintf(dev->wqn, "%s/%d", dvb_adapter->name, dvb_adapter->num);
  953. dev->wq = create_singlethread_workqueue(dev->wqn);
  954. if (!dev->wq) {
  955. ret = -ENOMEM;
  956. goto err_dvb_net;
  957. }
  958. ret = request_irq(pdev->irq, dm1105_irq, IRQF_SHARED,
  959. DRIVER_NAME, dev);
  960. if (ret < 0)
  961. goto err_workqueue;
  962. return 0;
  963. err_workqueue:
  964. destroy_workqueue(dev->wq);
  965. err_dvb_net:
  966. dvb_net_release(&dev->dvbnet);
  967. err_disconnect_frontend:
  968. dmx->disconnect_frontend(dmx);
  969. err_remove_mem_frontend:
  970. dmx->remove_frontend(dmx, &dev->mem_frontend);
  971. err_remove_hw_frontend:
  972. dmx->remove_frontend(dmx, &dev->hw_frontend);
  973. err_dvb_dmxdev_release:
  974. dvb_dmxdev_release(&dev->dmxdev);
  975. err_dvb_dmx_release:
  976. dvb_dmx_release(dvbdemux);
  977. err_dvb_unregister_adapter:
  978. dvb_unregister_adapter(dvb_adapter);
  979. err_i2c_del_adapters:
  980. i2c_del_adapter(&dev->i2c_bb_adap);
  981. err_i2c_del_adapter:
  982. i2c_del_adapter(&dev->i2c_adap);
  983. err_dm1105_hw_exit:
  984. dm1105_hw_exit(dev);
  985. err_pci_iounmap:
  986. pci_iounmap(pdev, dev->io_mem);
  987. err_pci_release_regions:
  988. pci_release_regions(pdev);
  989. err_pci_disable_device:
  990. pci_disable_device(pdev);
  991. err_kfree:
  992. pci_set_drvdata(pdev, NULL);
  993. kfree(dev);
  994. return ret;
  995. }
  996. static void __devexit dm1105_remove(struct pci_dev *pdev)
  997. {
  998. struct dm1105_dev *dev = pci_get_drvdata(pdev);
  999. struct dvb_adapter *dvb_adapter = &dev->dvb_adapter;
  1000. struct dvb_demux *dvbdemux = &dev->demux;
  1001. struct dmx_demux *dmx = &dvbdemux->dmx;
  1002. dm1105_ir_exit(dev);
  1003. dmx->close(dmx);
  1004. dvb_net_release(&dev->dvbnet);
  1005. if (dev->fe)
  1006. dvb_unregister_frontend(dev->fe);
  1007. dmx->disconnect_frontend(dmx);
  1008. dmx->remove_frontend(dmx, &dev->mem_frontend);
  1009. dmx->remove_frontend(dmx, &dev->hw_frontend);
  1010. dvb_dmxdev_release(&dev->dmxdev);
  1011. dvb_dmx_release(dvbdemux);
  1012. dvb_unregister_adapter(dvb_adapter);
  1013. if (&dev->i2c_adap)
  1014. i2c_del_adapter(&dev->i2c_adap);
  1015. dm1105_hw_exit(dev);
  1016. synchronize_irq(pdev->irq);
  1017. free_irq(pdev->irq, dev);
  1018. pci_iounmap(pdev, dev->io_mem);
  1019. pci_release_regions(pdev);
  1020. pci_disable_device(pdev);
  1021. pci_set_drvdata(pdev, NULL);
  1022. dm1105_devcount--;
  1023. kfree(dev);
  1024. }
  1025. static struct pci_device_id dm1105_id_table[] __devinitdata = {
  1026. {
  1027. .vendor = PCI_VENDOR_ID_TRIGEM,
  1028. .device = PCI_DEVICE_ID_DM1105,
  1029. .subvendor = PCI_ANY_ID,
  1030. .subdevice = PCI_ANY_ID,
  1031. }, {
  1032. .vendor = PCI_VENDOR_ID_AXESS,
  1033. .device = PCI_DEVICE_ID_DM05,
  1034. .subvendor = PCI_ANY_ID,
  1035. .subdevice = PCI_ANY_ID,
  1036. }, {
  1037. /* empty */
  1038. },
  1039. };
  1040. MODULE_DEVICE_TABLE(pci, dm1105_id_table);
  1041. static struct pci_driver dm1105_driver = {
  1042. .name = DRIVER_NAME,
  1043. .id_table = dm1105_id_table,
  1044. .probe = dm1105_probe,
  1045. .remove = __devexit_p(dm1105_remove),
  1046. };
  1047. static int __init dm1105_init(void)
  1048. {
  1049. return pci_register_driver(&dm1105_driver);
  1050. }
  1051. static void __exit dm1105_exit(void)
  1052. {
  1053. pci_unregister_driver(&dm1105_driver);
  1054. }
  1055. module_init(dm1105_init);
  1056. module_exit(dm1105_exit);
  1057. MODULE_AUTHOR("Igor M. Liplianin <liplianin@me.by>");
  1058. MODULE_DESCRIPTION("SDMC DM1105 DVB driver");
  1059. MODULE_LICENSE("GPL");