m66592-udc.c 43 KB

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  1. /*
  2. * M66592 UDC (USB gadget)
  3. *
  4. * Copyright (C) 2006-2007 Renesas Solutions Corp.
  5. *
  6. * Author : Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; version 2 of the License.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  20. *
  21. */
  22. #include <linux/module.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/delay.h>
  25. #include <linux/io.h>
  26. #include <linux/platform_device.h>
  27. #include <linux/slab.h>
  28. #include <linux/err.h>
  29. #include <linux/usb/ch9.h>
  30. #include <linux/usb/gadget.h>
  31. #include "m66592-udc.h"
  32. MODULE_DESCRIPTION("M66592 USB gadget driver");
  33. MODULE_LICENSE("GPL");
  34. MODULE_AUTHOR("Yoshihiro Shimoda");
  35. MODULE_ALIAS("platform:m66592_udc");
  36. #define DRIVER_VERSION "21 July 2009"
  37. static const char udc_name[] = "m66592_udc";
  38. static const char *m66592_ep_name[] = {
  39. "ep0", "ep1", "ep2", "ep3", "ep4", "ep5", "ep6", "ep7"
  40. };
  41. static void disable_controller(struct m66592 *m66592);
  42. static void irq_ep0_write(struct m66592_ep *ep, struct m66592_request *req);
  43. static void irq_packet_write(struct m66592_ep *ep, struct m66592_request *req);
  44. static int m66592_queue(struct usb_ep *_ep, struct usb_request *_req,
  45. gfp_t gfp_flags);
  46. static void transfer_complete(struct m66592_ep *ep,
  47. struct m66592_request *req, int status);
  48. /*-------------------------------------------------------------------------*/
  49. static inline u16 get_usb_speed(struct m66592 *m66592)
  50. {
  51. return (m66592_read(m66592, M66592_DVSTCTR) & M66592_RHST);
  52. }
  53. static void enable_pipe_irq(struct m66592 *m66592, u16 pipenum,
  54. unsigned long reg)
  55. {
  56. u16 tmp;
  57. tmp = m66592_read(m66592, M66592_INTENB0);
  58. m66592_bclr(m66592, M66592_BEMPE | M66592_NRDYE | M66592_BRDYE,
  59. M66592_INTENB0);
  60. m66592_bset(m66592, (1 << pipenum), reg);
  61. m66592_write(m66592, tmp, M66592_INTENB0);
  62. }
  63. static void disable_pipe_irq(struct m66592 *m66592, u16 pipenum,
  64. unsigned long reg)
  65. {
  66. u16 tmp;
  67. tmp = m66592_read(m66592, M66592_INTENB0);
  68. m66592_bclr(m66592, M66592_BEMPE | M66592_NRDYE | M66592_BRDYE,
  69. M66592_INTENB0);
  70. m66592_bclr(m66592, (1 << pipenum), reg);
  71. m66592_write(m66592, tmp, M66592_INTENB0);
  72. }
  73. static void m66592_usb_connect(struct m66592 *m66592)
  74. {
  75. m66592_bset(m66592, M66592_CTRE, M66592_INTENB0);
  76. m66592_bset(m66592, M66592_WDST | M66592_RDST | M66592_CMPL,
  77. M66592_INTENB0);
  78. m66592_bset(m66592, M66592_BEMPE | M66592_BRDYE, M66592_INTENB0);
  79. m66592_bset(m66592, M66592_DPRPU, M66592_SYSCFG);
  80. }
  81. static void m66592_usb_disconnect(struct m66592 *m66592)
  82. __releases(m66592->lock)
  83. __acquires(m66592->lock)
  84. {
  85. m66592_bclr(m66592, M66592_CTRE, M66592_INTENB0);
  86. m66592_bclr(m66592, M66592_WDST | M66592_RDST | M66592_CMPL,
  87. M66592_INTENB0);
  88. m66592_bclr(m66592, M66592_BEMPE | M66592_BRDYE, M66592_INTENB0);
  89. m66592_bclr(m66592, M66592_DPRPU, M66592_SYSCFG);
  90. m66592->gadget.speed = USB_SPEED_UNKNOWN;
  91. spin_unlock(&m66592->lock);
  92. m66592->driver->disconnect(&m66592->gadget);
  93. spin_lock(&m66592->lock);
  94. disable_controller(m66592);
  95. INIT_LIST_HEAD(&m66592->ep[0].queue);
  96. }
  97. static inline u16 control_reg_get_pid(struct m66592 *m66592, u16 pipenum)
  98. {
  99. u16 pid = 0;
  100. unsigned long offset;
  101. if (pipenum == 0)
  102. pid = m66592_read(m66592, M66592_DCPCTR) & M66592_PID;
  103. else if (pipenum < M66592_MAX_NUM_PIPE) {
  104. offset = get_pipectr_addr(pipenum);
  105. pid = m66592_read(m66592, offset) & M66592_PID;
  106. } else
  107. pr_err("unexpect pipe num (%d)\n", pipenum);
  108. return pid;
  109. }
  110. static inline void control_reg_set_pid(struct m66592 *m66592, u16 pipenum,
  111. u16 pid)
  112. {
  113. unsigned long offset;
  114. if (pipenum == 0)
  115. m66592_mdfy(m66592, pid, M66592_PID, M66592_DCPCTR);
  116. else if (pipenum < M66592_MAX_NUM_PIPE) {
  117. offset = get_pipectr_addr(pipenum);
  118. m66592_mdfy(m66592, pid, M66592_PID, offset);
  119. } else
  120. pr_err("unexpect pipe num (%d)\n", pipenum);
  121. }
  122. static inline void pipe_start(struct m66592 *m66592, u16 pipenum)
  123. {
  124. control_reg_set_pid(m66592, pipenum, M66592_PID_BUF);
  125. }
  126. static inline void pipe_stop(struct m66592 *m66592, u16 pipenum)
  127. {
  128. control_reg_set_pid(m66592, pipenum, M66592_PID_NAK);
  129. }
  130. static inline void pipe_stall(struct m66592 *m66592, u16 pipenum)
  131. {
  132. control_reg_set_pid(m66592, pipenum, M66592_PID_STALL);
  133. }
  134. static inline u16 control_reg_get(struct m66592 *m66592, u16 pipenum)
  135. {
  136. u16 ret = 0;
  137. unsigned long offset;
  138. if (pipenum == 0)
  139. ret = m66592_read(m66592, M66592_DCPCTR);
  140. else if (pipenum < M66592_MAX_NUM_PIPE) {
  141. offset = get_pipectr_addr(pipenum);
  142. ret = m66592_read(m66592, offset);
  143. } else
  144. pr_err("unexpect pipe num (%d)\n", pipenum);
  145. return ret;
  146. }
  147. static inline void control_reg_sqclr(struct m66592 *m66592, u16 pipenum)
  148. {
  149. unsigned long offset;
  150. pipe_stop(m66592, pipenum);
  151. if (pipenum == 0)
  152. m66592_bset(m66592, M66592_SQCLR, M66592_DCPCTR);
  153. else if (pipenum < M66592_MAX_NUM_PIPE) {
  154. offset = get_pipectr_addr(pipenum);
  155. m66592_bset(m66592, M66592_SQCLR, offset);
  156. } else
  157. pr_err("unexpect pipe num(%d)\n", pipenum);
  158. }
  159. static inline int get_buffer_size(struct m66592 *m66592, u16 pipenum)
  160. {
  161. u16 tmp;
  162. int size;
  163. if (pipenum == 0) {
  164. tmp = m66592_read(m66592, M66592_DCPCFG);
  165. if ((tmp & M66592_CNTMD) != 0)
  166. size = 256;
  167. else {
  168. tmp = m66592_read(m66592, M66592_DCPMAXP);
  169. size = tmp & M66592_MAXP;
  170. }
  171. } else {
  172. m66592_write(m66592, pipenum, M66592_PIPESEL);
  173. tmp = m66592_read(m66592, M66592_PIPECFG);
  174. if ((tmp & M66592_CNTMD) != 0) {
  175. tmp = m66592_read(m66592, M66592_PIPEBUF);
  176. size = ((tmp >> 10) + 1) * 64;
  177. } else {
  178. tmp = m66592_read(m66592, M66592_PIPEMAXP);
  179. size = tmp & M66592_MXPS;
  180. }
  181. }
  182. return size;
  183. }
  184. static inline void pipe_change(struct m66592 *m66592, u16 pipenum)
  185. {
  186. struct m66592_ep *ep = m66592->pipenum2ep[pipenum];
  187. unsigned short mbw;
  188. if (ep->use_dma)
  189. return;
  190. m66592_mdfy(m66592, pipenum, M66592_CURPIPE, ep->fifosel);
  191. ndelay(450);
  192. if (m66592->pdata->on_chip)
  193. mbw = M66592_MBW_32;
  194. else
  195. mbw = M66592_MBW_16;
  196. m66592_bset(m66592, mbw, ep->fifosel);
  197. }
  198. static int pipe_buffer_setting(struct m66592 *m66592,
  199. struct m66592_pipe_info *info)
  200. {
  201. u16 bufnum = 0, buf_bsize = 0;
  202. u16 pipecfg = 0;
  203. if (info->pipe == 0)
  204. return -EINVAL;
  205. m66592_write(m66592, info->pipe, M66592_PIPESEL);
  206. if (info->dir_in)
  207. pipecfg |= M66592_DIR;
  208. pipecfg |= info->type;
  209. pipecfg |= info->epnum;
  210. switch (info->type) {
  211. case M66592_INT:
  212. bufnum = 4 + (info->pipe - M66592_BASE_PIPENUM_INT);
  213. buf_bsize = 0;
  214. break;
  215. case M66592_BULK:
  216. /* isochronous pipes may be used as bulk pipes */
  217. if (info->pipe >= M66592_BASE_PIPENUM_BULK)
  218. bufnum = info->pipe - M66592_BASE_PIPENUM_BULK;
  219. else
  220. bufnum = info->pipe - M66592_BASE_PIPENUM_ISOC;
  221. bufnum = M66592_BASE_BUFNUM + (bufnum * 16);
  222. buf_bsize = 7;
  223. pipecfg |= M66592_DBLB;
  224. if (!info->dir_in)
  225. pipecfg |= M66592_SHTNAK;
  226. break;
  227. case M66592_ISO:
  228. bufnum = M66592_BASE_BUFNUM +
  229. (info->pipe - M66592_BASE_PIPENUM_ISOC) * 16;
  230. buf_bsize = 7;
  231. break;
  232. }
  233. if (buf_bsize && ((bufnum + 16) >= M66592_MAX_BUFNUM)) {
  234. pr_err("m66592 pipe memory is insufficient\n");
  235. return -ENOMEM;
  236. }
  237. m66592_write(m66592, pipecfg, M66592_PIPECFG);
  238. m66592_write(m66592, (buf_bsize << 10) | (bufnum), M66592_PIPEBUF);
  239. m66592_write(m66592, info->maxpacket, M66592_PIPEMAXP);
  240. if (info->interval)
  241. info->interval--;
  242. m66592_write(m66592, info->interval, M66592_PIPEPERI);
  243. return 0;
  244. }
  245. static void pipe_buffer_release(struct m66592 *m66592,
  246. struct m66592_pipe_info *info)
  247. {
  248. if (info->pipe == 0)
  249. return;
  250. if (is_bulk_pipe(info->pipe)) {
  251. m66592->bulk--;
  252. } else if (is_interrupt_pipe(info->pipe))
  253. m66592->interrupt--;
  254. else if (is_isoc_pipe(info->pipe)) {
  255. m66592->isochronous--;
  256. if (info->type == M66592_BULK)
  257. m66592->bulk--;
  258. } else
  259. pr_err("ep_release: unexpect pipenum (%d)\n",
  260. info->pipe);
  261. }
  262. static void pipe_initialize(struct m66592_ep *ep)
  263. {
  264. struct m66592 *m66592 = ep->m66592;
  265. unsigned short mbw;
  266. m66592_mdfy(m66592, 0, M66592_CURPIPE, ep->fifosel);
  267. m66592_write(m66592, M66592_ACLRM, ep->pipectr);
  268. m66592_write(m66592, 0, ep->pipectr);
  269. m66592_write(m66592, M66592_SQCLR, ep->pipectr);
  270. if (ep->use_dma) {
  271. m66592_mdfy(m66592, ep->pipenum, M66592_CURPIPE, ep->fifosel);
  272. ndelay(450);
  273. if (m66592->pdata->on_chip)
  274. mbw = M66592_MBW_32;
  275. else
  276. mbw = M66592_MBW_16;
  277. m66592_bset(m66592, mbw, ep->fifosel);
  278. }
  279. }
  280. static void m66592_ep_setting(struct m66592 *m66592, struct m66592_ep *ep,
  281. const struct usb_endpoint_descriptor *desc,
  282. u16 pipenum, int dma)
  283. {
  284. if ((pipenum != 0) && dma) {
  285. if (m66592->num_dma == 0) {
  286. m66592->num_dma++;
  287. ep->use_dma = 1;
  288. ep->fifoaddr = M66592_D0FIFO;
  289. ep->fifosel = M66592_D0FIFOSEL;
  290. ep->fifoctr = M66592_D0FIFOCTR;
  291. ep->fifotrn = M66592_D0FIFOTRN;
  292. } else if (!m66592->pdata->on_chip && m66592->num_dma == 1) {
  293. m66592->num_dma++;
  294. ep->use_dma = 1;
  295. ep->fifoaddr = M66592_D1FIFO;
  296. ep->fifosel = M66592_D1FIFOSEL;
  297. ep->fifoctr = M66592_D1FIFOCTR;
  298. ep->fifotrn = M66592_D1FIFOTRN;
  299. } else {
  300. ep->use_dma = 0;
  301. ep->fifoaddr = M66592_CFIFO;
  302. ep->fifosel = M66592_CFIFOSEL;
  303. ep->fifoctr = M66592_CFIFOCTR;
  304. ep->fifotrn = 0;
  305. }
  306. } else {
  307. ep->use_dma = 0;
  308. ep->fifoaddr = M66592_CFIFO;
  309. ep->fifosel = M66592_CFIFOSEL;
  310. ep->fifoctr = M66592_CFIFOCTR;
  311. ep->fifotrn = 0;
  312. }
  313. ep->pipectr = get_pipectr_addr(pipenum);
  314. ep->pipenum = pipenum;
  315. ep->ep.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
  316. m66592->pipenum2ep[pipenum] = ep;
  317. m66592->epaddr2ep[desc->bEndpointAddress&USB_ENDPOINT_NUMBER_MASK] = ep;
  318. INIT_LIST_HEAD(&ep->queue);
  319. }
  320. static void m66592_ep_release(struct m66592_ep *ep)
  321. {
  322. struct m66592 *m66592 = ep->m66592;
  323. u16 pipenum = ep->pipenum;
  324. if (pipenum == 0)
  325. return;
  326. if (ep->use_dma)
  327. m66592->num_dma--;
  328. ep->pipenum = 0;
  329. ep->busy = 0;
  330. ep->use_dma = 0;
  331. }
  332. static int alloc_pipe_config(struct m66592_ep *ep,
  333. const struct usb_endpoint_descriptor *desc)
  334. {
  335. struct m66592 *m66592 = ep->m66592;
  336. struct m66592_pipe_info info;
  337. int dma = 0;
  338. int *counter;
  339. int ret;
  340. ep->desc = desc;
  341. BUG_ON(ep->pipenum);
  342. switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
  343. case USB_ENDPOINT_XFER_BULK:
  344. if (m66592->bulk >= M66592_MAX_NUM_BULK) {
  345. if (m66592->isochronous >= M66592_MAX_NUM_ISOC) {
  346. pr_err("bulk pipe is insufficient\n");
  347. return -ENODEV;
  348. } else {
  349. info.pipe = M66592_BASE_PIPENUM_ISOC
  350. + m66592->isochronous;
  351. counter = &m66592->isochronous;
  352. }
  353. } else {
  354. info.pipe = M66592_BASE_PIPENUM_BULK + m66592->bulk;
  355. counter = &m66592->bulk;
  356. }
  357. info.type = M66592_BULK;
  358. dma = 1;
  359. break;
  360. case USB_ENDPOINT_XFER_INT:
  361. if (m66592->interrupt >= M66592_MAX_NUM_INT) {
  362. pr_err("interrupt pipe is insufficient\n");
  363. return -ENODEV;
  364. }
  365. info.pipe = M66592_BASE_PIPENUM_INT + m66592->interrupt;
  366. info.type = M66592_INT;
  367. counter = &m66592->interrupt;
  368. break;
  369. case USB_ENDPOINT_XFER_ISOC:
  370. if (m66592->isochronous >= M66592_MAX_NUM_ISOC) {
  371. pr_err("isochronous pipe is insufficient\n");
  372. return -ENODEV;
  373. }
  374. info.pipe = M66592_BASE_PIPENUM_ISOC + m66592->isochronous;
  375. info.type = M66592_ISO;
  376. counter = &m66592->isochronous;
  377. break;
  378. default:
  379. pr_err("unexpect xfer type\n");
  380. return -EINVAL;
  381. }
  382. ep->type = info.type;
  383. info.epnum = desc->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
  384. info.maxpacket = le16_to_cpu(desc->wMaxPacketSize);
  385. info.interval = desc->bInterval;
  386. if (desc->bEndpointAddress & USB_ENDPOINT_DIR_MASK)
  387. info.dir_in = 1;
  388. else
  389. info.dir_in = 0;
  390. ret = pipe_buffer_setting(m66592, &info);
  391. if (ret < 0) {
  392. pr_err("pipe_buffer_setting fail\n");
  393. return ret;
  394. }
  395. (*counter)++;
  396. if ((counter == &m66592->isochronous) && info.type == M66592_BULK)
  397. m66592->bulk++;
  398. m66592_ep_setting(m66592, ep, desc, info.pipe, dma);
  399. pipe_initialize(ep);
  400. return 0;
  401. }
  402. static int free_pipe_config(struct m66592_ep *ep)
  403. {
  404. struct m66592 *m66592 = ep->m66592;
  405. struct m66592_pipe_info info;
  406. info.pipe = ep->pipenum;
  407. info.type = ep->type;
  408. pipe_buffer_release(m66592, &info);
  409. m66592_ep_release(ep);
  410. return 0;
  411. }
  412. /*-------------------------------------------------------------------------*/
  413. static void pipe_irq_enable(struct m66592 *m66592, u16 pipenum)
  414. {
  415. enable_irq_ready(m66592, pipenum);
  416. enable_irq_nrdy(m66592, pipenum);
  417. }
  418. static void pipe_irq_disable(struct m66592 *m66592, u16 pipenum)
  419. {
  420. disable_irq_ready(m66592, pipenum);
  421. disable_irq_nrdy(m66592, pipenum);
  422. }
  423. /* if complete is true, gadget driver complete function is not call */
  424. static void control_end(struct m66592 *m66592, unsigned ccpl)
  425. {
  426. m66592->ep[0].internal_ccpl = ccpl;
  427. pipe_start(m66592, 0);
  428. m66592_bset(m66592, M66592_CCPL, M66592_DCPCTR);
  429. }
  430. static void start_ep0_write(struct m66592_ep *ep, struct m66592_request *req)
  431. {
  432. struct m66592 *m66592 = ep->m66592;
  433. pipe_change(m66592, ep->pipenum);
  434. m66592_mdfy(m66592, M66592_ISEL | M66592_PIPE0,
  435. (M66592_ISEL | M66592_CURPIPE),
  436. M66592_CFIFOSEL);
  437. m66592_write(m66592, M66592_BCLR, ep->fifoctr);
  438. if (req->req.length == 0) {
  439. m66592_bset(m66592, M66592_BVAL, ep->fifoctr);
  440. pipe_start(m66592, 0);
  441. transfer_complete(ep, req, 0);
  442. } else {
  443. m66592_write(m66592, ~M66592_BEMP0, M66592_BEMPSTS);
  444. irq_ep0_write(ep, req);
  445. }
  446. }
  447. static void start_packet_write(struct m66592_ep *ep, struct m66592_request *req)
  448. {
  449. struct m66592 *m66592 = ep->m66592;
  450. u16 tmp;
  451. pipe_change(m66592, ep->pipenum);
  452. disable_irq_empty(m66592, ep->pipenum);
  453. pipe_start(m66592, ep->pipenum);
  454. tmp = m66592_read(m66592, ep->fifoctr);
  455. if (unlikely((tmp & M66592_FRDY) == 0))
  456. pipe_irq_enable(m66592, ep->pipenum);
  457. else
  458. irq_packet_write(ep, req);
  459. }
  460. static void start_packet_read(struct m66592_ep *ep, struct m66592_request *req)
  461. {
  462. struct m66592 *m66592 = ep->m66592;
  463. u16 pipenum = ep->pipenum;
  464. if (ep->pipenum == 0) {
  465. m66592_mdfy(m66592, M66592_PIPE0,
  466. (M66592_ISEL | M66592_CURPIPE),
  467. M66592_CFIFOSEL);
  468. m66592_write(m66592, M66592_BCLR, ep->fifoctr);
  469. pipe_start(m66592, pipenum);
  470. pipe_irq_enable(m66592, pipenum);
  471. } else {
  472. if (ep->use_dma) {
  473. m66592_bset(m66592, M66592_TRCLR, ep->fifosel);
  474. pipe_change(m66592, pipenum);
  475. m66592_bset(m66592, M66592_TRENB, ep->fifosel);
  476. m66592_write(m66592,
  477. (req->req.length + ep->ep.maxpacket - 1)
  478. / ep->ep.maxpacket,
  479. ep->fifotrn);
  480. }
  481. pipe_start(m66592, pipenum); /* trigger once */
  482. pipe_irq_enable(m66592, pipenum);
  483. }
  484. }
  485. static void start_packet(struct m66592_ep *ep, struct m66592_request *req)
  486. {
  487. if (ep->desc->bEndpointAddress & USB_DIR_IN)
  488. start_packet_write(ep, req);
  489. else
  490. start_packet_read(ep, req);
  491. }
  492. static void start_ep0(struct m66592_ep *ep, struct m66592_request *req)
  493. {
  494. u16 ctsq;
  495. ctsq = m66592_read(ep->m66592, M66592_INTSTS0) & M66592_CTSQ;
  496. switch (ctsq) {
  497. case M66592_CS_RDDS:
  498. start_ep0_write(ep, req);
  499. break;
  500. case M66592_CS_WRDS:
  501. start_packet_read(ep, req);
  502. break;
  503. case M66592_CS_WRND:
  504. control_end(ep->m66592, 0);
  505. break;
  506. default:
  507. pr_err("start_ep0: unexpect ctsq(%x)\n", ctsq);
  508. break;
  509. }
  510. }
  511. static void init_controller(struct m66592 *m66592)
  512. {
  513. unsigned int endian;
  514. if (m66592->pdata->on_chip) {
  515. if (m66592->pdata->endian)
  516. endian = 0; /* big endian */
  517. else
  518. endian = M66592_LITTLE; /* little endian */
  519. m66592_bset(m66592, M66592_HSE, M66592_SYSCFG); /* High spd */
  520. m66592_bclr(m66592, M66592_USBE, M66592_SYSCFG);
  521. m66592_bclr(m66592, M66592_DPRPU, M66592_SYSCFG);
  522. m66592_bset(m66592, M66592_USBE, M66592_SYSCFG);
  523. /* This is a workaound for SH7722 2nd cut */
  524. m66592_bset(m66592, 0x8000, M66592_DVSTCTR);
  525. m66592_bset(m66592, 0x1000, M66592_TESTMODE);
  526. m66592_bclr(m66592, 0x8000, M66592_DVSTCTR);
  527. m66592_bset(m66592, M66592_INTL, M66592_INTENB1);
  528. m66592_write(m66592, 0, M66592_CFBCFG);
  529. m66592_write(m66592, 0, M66592_D0FBCFG);
  530. m66592_bset(m66592, endian, M66592_CFBCFG);
  531. m66592_bset(m66592, endian, M66592_D0FBCFG);
  532. } else {
  533. unsigned int clock, vif, irq_sense;
  534. if (m66592->pdata->endian)
  535. endian = M66592_BIGEND; /* big endian */
  536. else
  537. endian = 0; /* little endian */
  538. if (m66592->pdata->vif)
  539. vif = M66592_LDRV; /* 3.3v */
  540. else
  541. vif = 0; /* 1.5v */
  542. switch (m66592->pdata->xtal) {
  543. case M66592_PLATDATA_XTAL_12MHZ:
  544. clock = M66592_XTAL12;
  545. break;
  546. case M66592_PLATDATA_XTAL_24MHZ:
  547. clock = M66592_XTAL24;
  548. break;
  549. case M66592_PLATDATA_XTAL_48MHZ:
  550. clock = M66592_XTAL48;
  551. break;
  552. default:
  553. pr_warning("m66592-udc: xtal configuration error\n");
  554. clock = 0;
  555. }
  556. switch (m66592->irq_trigger) {
  557. case IRQF_TRIGGER_LOW:
  558. irq_sense = M66592_INTL;
  559. break;
  560. case IRQF_TRIGGER_FALLING:
  561. irq_sense = 0;
  562. break;
  563. default:
  564. pr_warning("m66592-udc: irq trigger config error\n");
  565. irq_sense = 0;
  566. }
  567. m66592_bset(m66592,
  568. (vif & M66592_LDRV) | (endian & M66592_BIGEND),
  569. M66592_PINCFG);
  570. m66592_bset(m66592, M66592_HSE, M66592_SYSCFG); /* High spd */
  571. m66592_mdfy(m66592, clock & M66592_XTAL, M66592_XTAL,
  572. M66592_SYSCFG);
  573. m66592_bclr(m66592, M66592_USBE, M66592_SYSCFG);
  574. m66592_bclr(m66592, M66592_DPRPU, M66592_SYSCFG);
  575. m66592_bset(m66592, M66592_USBE, M66592_SYSCFG);
  576. m66592_bset(m66592, M66592_XCKE, M66592_SYSCFG);
  577. msleep(3);
  578. m66592_bset(m66592, M66592_RCKE | M66592_PLLC, M66592_SYSCFG);
  579. msleep(1);
  580. m66592_bset(m66592, M66592_SCKE, M66592_SYSCFG);
  581. m66592_bset(m66592, irq_sense & M66592_INTL, M66592_INTENB1);
  582. m66592_write(m66592, M66592_BURST | M66592_CPU_ADR_RD_WR,
  583. M66592_DMA0CFG);
  584. }
  585. }
  586. static void disable_controller(struct m66592 *m66592)
  587. {
  588. m66592_bclr(m66592, M66592_UTST, M66592_TESTMODE);
  589. if (!m66592->pdata->on_chip) {
  590. m66592_bclr(m66592, M66592_SCKE, M66592_SYSCFG);
  591. udelay(1);
  592. m66592_bclr(m66592, M66592_PLLC, M66592_SYSCFG);
  593. udelay(1);
  594. m66592_bclr(m66592, M66592_RCKE, M66592_SYSCFG);
  595. udelay(1);
  596. m66592_bclr(m66592, M66592_XCKE, M66592_SYSCFG);
  597. }
  598. }
  599. static void m66592_start_xclock(struct m66592 *m66592)
  600. {
  601. u16 tmp;
  602. if (!m66592->pdata->on_chip) {
  603. tmp = m66592_read(m66592, M66592_SYSCFG);
  604. if (!(tmp & M66592_XCKE))
  605. m66592_bset(m66592, M66592_XCKE, M66592_SYSCFG);
  606. }
  607. }
  608. /*-------------------------------------------------------------------------*/
  609. static void transfer_complete(struct m66592_ep *ep,
  610. struct m66592_request *req, int status)
  611. __releases(m66592->lock)
  612. __acquires(m66592->lock)
  613. {
  614. int restart = 0;
  615. if (unlikely(ep->pipenum == 0)) {
  616. if (ep->internal_ccpl) {
  617. ep->internal_ccpl = 0;
  618. return;
  619. }
  620. }
  621. list_del_init(&req->queue);
  622. if (ep->m66592->gadget.speed == USB_SPEED_UNKNOWN)
  623. req->req.status = -ESHUTDOWN;
  624. else
  625. req->req.status = status;
  626. if (!list_empty(&ep->queue))
  627. restart = 1;
  628. spin_unlock(&ep->m66592->lock);
  629. req->req.complete(&ep->ep, &req->req);
  630. spin_lock(&ep->m66592->lock);
  631. if (restart) {
  632. req = list_entry(ep->queue.next, struct m66592_request, queue);
  633. if (ep->desc)
  634. start_packet(ep, req);
  635. }
  636. }
  637. static void irq_ep0_write(struct m66592_ep *ep, struct m66592_request *req)
  638. {
  639. int i;
  640. u16 tmp;
  641. unsigned bufsize;
  642. size_t size;
  643. void *buf;
  644. u16 pipenum = ep->pipenum;
  645. struct m66592 *m66592 = ep->m66592;
  646. pipe_change(m66592, pipenum);
  647. m66592_bset(m66592, M66592_ISEL, ep->fifosel);
  648. i = 0;
  649. do {
  650. tmp = m66592_read(m66592, ep->fifoctr);
  651. if (i++ > 100000) {
  652. pr_err("pipe0 is busy. maybe cpu i/o bus "
  653. "conflict. please power off this controller.");
  654. return;
  655. }
  656. ndelay(1);
  657. } while ((tmp & M66592_FRDY) == 0);
  658. /* prepare parameters */
  659. bufsize = get_buffer_size(m66592, pipenum);
  660. buf = req->req.buf + req->req.actual;
  661. size = min(bufsize, req->req.length - req->req.actual);
  662. /* write fifo */
  663. if (req->req.buf) {
  664. if (size > 0)
  665. m66592_write_fifo(m66592, ep, buf, size);
  666. if ((size == 0) || ((size % ep->ep.maxpacket) != 0))
  667. m66592_bset(m66592, M66592_BVAL, ep->fifoctr);
  668. }
  669. /* update parameters */
  670. req->req.actual += size;
  671. /* check transfer finish */
  672. if ((!req->req.zero && (req->req.actual == req->req.length))
  673. || (size % ep->ep.maxpacket)
  674. || (size == 0)) {
  675. disable_irq_ready(m66592, pipenum);
  676. disable_irq_empty(m66592, pipenum);
  677. } else {
  678. disable_irq_ready(m66592, pipenum);
  679. enable_irq_empty(m66592, pipenum);
  680. }
  681. pipe_start(m66592, pipenum);
  682. }
  683. static void irq_packet_write(struct m66592_ep *ep, struct m66592_request *req)
  684. {
  685. u16 tmp;
  686. unsigned bufsize;
  687. size_t size;
  688. void *buf;
  689. u16 pipenum = ep->pipenum;
  690. struct m66592 *m66592 = ep->m66592;
  691. pipe_change(m66592, pipenum);
  692. tmp = m66592_read(m66592, ep->fifoctr);
  693. if (unlikely((tmp & M66592_FRDY) == 0)) {
  694. pipe_stop(m66592, pipenum);
  695. pipe_irq_disable(m66592, pipenum);
  696. pr_err("write fifo not ready. pipnum=%d\n", pipenum);
  697. return;
  698. }
  699. /* prepare parameters */
  700. bufsize = get_buffer_size(m66592, pipenum);
  701. buf = req->req.buf + req->req.actual;
  702. size = min(bufsize, req->req.length - req->req.actual);
  703. /* write fifo */
  704. if (req->req.buf) {
  705. m66592_write_fifo(m66592, ep, buf, size);
  706. if ((size == 0)
  707. || ((size % ep->ep.maxpacket) != 0)
  708. || ((bufsize != ep->ep.maxpacket)
  709. && (bufsize > size)))
  710. m66592_bset(m66592, M66592_BVAL, ep->fifoctr);
  711. }
  712. /* update parameters */
  713. req->req.actual += size;
  714. /* check transfer finish */
  715. if ((!req->req.zero && (req->req.actual == req->req.length))
  716. || (size % ep->ep.maxpacket)
  717. || (size == 0)) {
  718. disable_irq_ready(m66592, pipenum);
  719. enable_irq_empty(m66592, pipenum);
  720. } else {
  721. disable_irq_empty(m66592, pipenum);
  722. pipe_irq_enable(m66592, pipenum);
  723. }
  724. }
  725. static void irq_packet_read(struct m66592_ep *ep, struct m66592_request *req)
  726. {
  727. u16 tmp;
  728. int rcv_len, bufsize, req_len;
  729. int size;
  730. void *buf;
  731. u16 pipenum = ep->pipenum;
  732. struct m66592 *m66592 = ep->m66592;
  733. int finish = 0;
  734. pipe_change(m66592, pipenum);
  735. tmp = m66592_read(m66592, ep->fifoctr);
  736. if (unlikely((tmp & M66592_FRDY) == 0)) {
  737. req->req.status = -EPIPE;
  738. pipe_stop(m66592, pipenum);
  739. pipe_irq_disable(m66592, pipenum);
  740. pr_err("read fifo not ready");
  741. return;
  742. }
  743. /* prepare parameters */
  744. rcv_len = tmp & M66592_DTLN;
  745. bufsize = get_buffer_size(m66592, pipenum);
  746. buf = req->req.buf + req->req.actual;
  747. req_len = req->req.length - req->req.actual;
  748. if (rcv_len < bufsize)
  749. size = min(rcv_len, req_len);
  750. else
  751. size = min(bufsize, req_len);
  752. /* update parameters */
  753. req->req.actual += size;
  754. /* check transfer finish */
  755. if ((!req->req.zero && (req->req.actual == req->req.length))
  756. || (size % ep->ep.maxpacket)
  757. || (size == 0)) {
  758. pipe_stop(m66592, pipenum);
  759. pipe_irq_disable(m66592, pipenum);
  760. finish = 1;
  761. }
  762. /* read fifo */
  763. if (req->req.buf) {
  764. if (size == 0)
  765. m66592_write(m66592, M66592_BCLR, ep->fifoctr);
  766. else
  767. m66592_read_fifo(m66592, ep->fifoaddr, buf, size);
  768. }
  769. if ((ep->pipenum != 0) && finish)
  770. transfer_complete(ep, req, 0);
  771. }
  772. static void irq_pipe_ready(struct m66592 *m66592, u16 status, u16 enb)
  773. {
  774. u16 check;
  775. u16 pipenum;
  776. struct m66592_ep *ep;
  777. struct m66592_request *req;
  778. if ((status & M66592_BRDY0) && (enb & M66592_BRDY0)) {
  779. m66592_write(m66592, ~M66592_BRDY0, M66592_BRDYSTS);
  780. m66592_mdfy(m66592, M66592_PIPE0, M66592_CURPIPE,
  781. M66592_CFIFOSEL);
  782. ep = &m66592->ep[0];
  783. req = list_entry(ep->queue.next, struct m66592_request, queue);
  784. irq_packet_read(ep, req);
  785. } else {
  786. for (pipenum = 1; pipenum < M66592_MAX_NUM_PIPE; pipenum++) {
  787. check = 1 << pipenum;
  788. if ((status & check) && (enb & check)) {
  789. m66592_write(m66592, ~check, M66592_BRDYSTS);
  790. ep = m66592->pipenum2ep[pipenum];
  791. req = list_entry(ep->queue.next,
  792. struct m66592_request, queue);
  793. if (ep->desc->bEndpointAddress & USB_DIR_IN)
  794. irq_packet_write(ep, req);
  795. else
  796. irq_packet_read(ep, req);
  797. }
  798. }
  799. }
  800. }
  801. static void irq_pipe_empty(struct m66592 *m66592, u16 status, u16 enb)
  802. {
  803. u16 tmp;
  804. u16 check;
  805. u16 pipenum;
  806. struct m66592_ep *ep;
  807. struct m66592_request *req;
  808. if ((status & M66592_BEMP0) && (enb & M66592_BEMP0)) {
  809. m66592_write(m66592, ~M66592_BEMP0, M66592_BEMPSTS);
  810. ep = &m66592->ep[0];
  811. req = list_entry(ep->queue.next, struct m66592_request, queue);
  812. irq_ep0_write(ep, req);
  813. } else {
  814. for (pipenum = 1; pipenum < M66592_MAX_NUM_PIPE; pipenum++) {
  815. check = 1 << pipenum;
  816. if ((status & check) && (enb & check)) {
  817. m66592_write(m66592, ~check, M66592_BEMPSTS);
  818. tmp = control_reg_get(m66592, pipenum);
  819. if ((tmp & M66592_INBUFM) == 0) {
  820. disable_irq_empty(m66592, pipenum);
  821. pipe_irq_disable(m66592, pipenum);
  822. pipe_stop(m66592, pipenum);
  823. ep = m66592->pipenum2ep[pipenum];
  824. req = list_entry(ep->queue.next,
  825. struct m66592_request,
  826. queue);
  827. if (!list_empty(&ep->queue))
  828. transfer_complete(ep, req, 0);
  829. }
  830. }
  831. }
  832. }
  833. }
  834. static void get_status(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
  835. __releases(m66592->lock)
  836. __acquires(m66592->lock)
  837. {
  838. struct m66592_ep *ep;
  839. u16 pid;
  840. u16 status = 0;
  841. u16 w_index = le16_to_cpu(ctrl->wIndex);
  842. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  843. case USB_RECIP_DEVICE:
  844. status = 1 << USB_DEVICE_SELF_POWERED;
  845. break;
  846. case USB_RECIP_INTERFACE:
  847. status = 0;
  848. break;
  849. case USB_RECIP_ENDPOINT:
  850. ep = m66592->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
  851. pid = control_reg_get_pid(m66592, ep->pipenum);
  852. if (pid == M66592_PID_STALL)
  853. status = 1 << USB_ENDPOINT_HALT;
  854. else
  855. status = 0;
  856. break;
  857. default:
  858. pipe_stall(m66592, 0);
  859. return; /* exit */
  860. }
  861. m66592->ep0_data = cpu_to_le16(status);
  862. m66592->ep0_req->buf = &m66592->ep0_data;
  863. m66592->ep0_req->length = 2;
  864. /* AV: what happens if we get called again before that gets through? */
  865. spin_unlock(&m66592->lock);
  866. m66592_queue(m66592->gadget.ep0, m66592->ep0_req, GFP_KERNEL);
  867. spin_lock(&m66592->lock);
  868. }
  869. static void clear_feature(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
  870. {
  871. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  872. case USB_RECIP_DEVICE:
  873. control_end(m66592, 1);
  874. break;
  875. case USB_RECIP_INTERFACE:
  876. control_end(m66592, 1);
  877. break;
  878. case USB_RECIP_ENDPOINT: {
  879. struct m66592_ep *ep;
  880. struct m66592_request *req;
  881. u16 w_index = le16_to_cpu(ctrl->wIndex);
  882. ep = m66592->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
  883. pipe_stop(m66592, ep->pipenum);
  884. control_reg_sqclr(m66592, ep->pipenum);
  885. control_end(m66592, 1);
  886. req = list_entry(ep->queue.next,
  887. struct m66592_request, queue);
  888. if (ep->busy) {
  889. ep->busy = 0;
  890. if (list_empty(&ep->queue))
  891. break;
  892. start_packet(ep, req);
  893. } else if (!list_empty(&ep->queue))
  894. pipe_start(m66592, ep->pipenum);
  895. }
  896. break;
  897. default:
  898. pipe_stall(m66592, 0);
  899. break;
  900. }
  901. }
  902. static void set_feature(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
  903. {
  904. u16 tmp;
  905. int timeout = 3000;
  906. switch (ctrl->bRequestType & USB_RECIP_MASK) {
  907. case USB_RECIP_DEVICE:
  908. switch (le16_to_cpu(ctrl->wValue)) {
  909. case USB_DEVICE_TEST_MODE:
  910. control_end(m66592, 1);
  911. /* Wait for the completion of status stage */
  912. do {
  913. tmp = m66592_read(m66592, M66592_INTSTS0) &
  914. M66592_CTSQ;
  915. udelay(1);
  916. } while (tmp != M66592_CS_IDST || timeout-- > 0);
  917. if (tmp == M66592_CS_IDST)
  918. m66592_bset(m66592,
  919. le16_to_cpu(ctrl->wIndex >> 8),
  920. M66592_TESTMODE);
  921. break;
  922. default:
  923. pipe_stall(m66592, 0);
  924. break;
  925. }
  926. break;
  927. case USB_RECIP_INTERFACE:
  928. control_end(m66592, 1);
  929. break;
  930. case USB_RECIP_ENDPOINT: {
  931. struct m66592_ep *ep;
  932. u16 w_index = le16_to_cpu(ctrl->wIndex);
  933. ep = m66592->epaddr2ep[w_index & USB_ENDPOINT_NUMBER_MASK];
  934. pipe_stall(m66592, ep->pipenum);
  935. control_end(m66592, 1);
  936. }
  937. break;
  938. default:
  939. pipe_stall(m66592, 0);
  940. break;
  941. }
  942. }
  943. /* if return value is true, call class driver's setup() */
  944. static int setup_packet(struct m66592 *m66592, struct usb_ctrlrequest *ctrl)
  945. {
  946. u16 *p = (u16 *)ctrl;
  947. unsigned long offset = M66592_USBREQ;
  948. int i, ret = 0;
  949. /* read fifo */
  950. m66592_write(m66592, ~M66592_VALID, M66592_INTSTS0);
  951. for (i = 0; i < 4; i++)
  952. p[i] = m66592_read(m66592, offset + i*2);
  953. /* check request */
  954. if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
  955. switch (ctrl->bRequest) {
  956. case USB_REQ_GET_STATUS:
  957. get_status(m66592, ctrl);
  958. break;
  959. case USB_REQ_CLEAR_FEATURE:
  960. clear_feature(m66592, ctrl);
  961. break;
  962. case USB_REQ_SET_FEATURE:
  963. set_feature(m66592, ctrl);
  964. break;
  965. default:
  966. ret = 1;
  967. break;
  968. }
  969. } else
  970. ret = 1;
  971. return ret;
  972. }
  973. static void m66592_update_usb_speed(struct m66592 *m66592)
  974. {
  975. u16 speed = get_usb_speed(m66592);
  976. switch (speed) {
  977. case M66592_HSMODE:
  978. m66592->gadget.speed = USB_SPEED_HIGH;
  979. break;
  980. case M66592_FSMODE:
  981. m66592->gadget.speed = USB_SPEED_FULL;
  982. break;
  983. default:
  984. m66592->gadget.speed = USB_SPEED_UNKNOWN;
  985. pr_err("USB speed unknown\n");
  986. }
  987. }
  988. static void irq_device_state(struct m66592 *m66592)
  989. {
  990. u16 dvsq;
  991. dvsq = m66592_read(m66592, M66592_INTSTS0) & M66592_DVSQ;
  992. m66592_write(m66592, ~M66592_DVST, M66592_INTSTS0);
  993. if (dvsq == M66592_DS_DFLT) { /* bus reset */
  994. m66592->driver->disconnect(&m66592->gadget);
  995. m66592_update_usb_speed(m66592);
  996. }
  997. if (m66592->old_dvsq == M66592_DS_CNFG && dvsq != M66592_DS_CNFG)
  998. m66592_update_usb_speed(m66592);
  999. if ((dvsq == M66592_DS_CNFG || dvsq == M66592_DS_ADDS)
  1000. && m66592->gadget.speed == USB_SPEED_UNKNOWN)
  1001. m66592_update_usb_speed(m66592);
  1002. m66592->old_dvsq = dvsq;
  1003. }
  1004. static void irq_control_stage(struct m66592 *m66592)
  1005. __releases(m66592->lock)
  1006. __acquires(m66592->lock)
  1007. {
  1008. struct usb_ctrlrequest ctrl;
  1009. u16 ctsq;
  1010. ctsq = m66592_read(m66592, M66592_INTSTS0) & M66592_CTSQ;
  1011. m66592_write(m66592, ~M66592_CTRT, M66592_INTSTS0);
  1012. switch (ctsq) {
  1013. case M66592_CS_IDST: {
  1014. struct m66592_ep *ep;
  1015. struct m66592_request *req;
  1016. ep = &m66592->ep[0];
  1017. req = list_entry(ep->queue.next, struct m66592_request, queue);
  1018. transfer_complete(ep, req, 0);
  1019. }
  1020. break;
  1021. case M66592_CS_RDDS:
  1022. case M66592_CS_WRDS:
  1023. case M66592_CS_WRND:
  1024. if (setup_packet(m66592, &ctrl)) {
  1025. spin_unlock(&m66592->lock);
  1026. if (m66592->driver->setup(&m66592->gadget, &ctrl) < 0)
  1027. pipe_stall(m66592, 0);
  1028. spin_lock(&m66592->lock);
  1029. }
  1030. break;
  1031. case M66592_CS_RDSS:
  1032. case M66592_CS_WRSS:
  1033. control_end(m66592, 0);
  1034. break;
  1035. default:
  1036. pr_err("ctrl_stage: unexpect ctsq(%x)\n", ctsq);
  1037. break;
  1038. }
  1039. }
  1040. static irqreturn_t m66592_irq(int irq, void *_m66592)
  1041. {
  1042. struct m66592 *m66592 = _m66592;
  1043. u16 intsts0;
  1044. u16 intenb0;
  1045. u16 brdysts, nrdysts, bempsts;
  1046. u16 brdyenb, nrdyenb, bempenb;
  1047. u16 savepipe;
  1048. u16 mask0;
  1049. spin_lock(&m66592->lock);
  1050. intsts0 = m66592_read(m66592, M66592_INTSTS0);
  1051. intenb0 = m66592_read(m66592, M66592_INTENB0);
  1052. if (m66592->pdata->on_chip && !intsts0 && !intenb0) {
  1053. /*
  1054. * When USB clock stops, it cannot read register. Even if a
  1055. * clock stops, the interrupt occurs. So this driver turn on
  1056. * a clock by this timing and do re-reading of register.
  1057. */
  1058. m66592_start_xclock(m66592);
  1059. intsts0 = m66592_read(m66592, M66592_INTSTS0);
  1060. intenb0 = m66592_read(m66592, M66592_INTENB0);
  1061. }
  1062. savepipe = m66592_read(m66592, M66592_CFIFOSEL);
  1063. mask0 = intsts0 & intenb0;
  1064. if (mask0) {
  1065. brdysts = m66592_read(m66592, M66592_BRDYSTS);
  1066. nrdysts = m66592_read(m66592, M66592_NRDYSTS);
  1067. bempsts = m66592_read(m66592, M66592_BEMPSTS);
  1068. brdyenb = m66592_read(m66592, M66592_BRDYENB);
  1069. nrdyenb = m66592_read(m66592, M66592_NRDYENB);
  1070. bempenb = m66592_read(m66592, M66592_BEMPENB);
  1071. if (mask0 & M66592_VBINT) {
  1072. m66592_write(m66592, 0xffff & ~M66592_VBINT,
  1073. M66592_INTSTS0);
  1074. m66592_start_xclock(m66592);
  1075. /* start vbus sampling */
  1076. m66592->old_vbus = m66592_read(m66592, M66592_INTSTS0)
  1077. & M66592_VBSTS;
  1078. m66592->scount = M66592_MAX_SAMPLING;
  1079. mod_timer(&m66592->timer,
  1080. jiffies + msecs_to_jiffies(50));
  1081. }
  1082. if (intsts0 & M66592_DVSQ)
  1083. irq_device_state(m66592);
  1084. if ((intsts0 & M66592_BRDY) && (intenb0 & M66592_BRDYE)
  1085. && (brdysts & brdyenb)) {
  1086. irq_pipe_ready(m66592, brdysts, brdyenb);
  1087. }
  1088. if ((intsts0 & M66592_BEMP) && (intenb0 & M66592_BEMPE)
  1089. && (bempsts & bempenb)) {
  1090. irq_pipe_empty(m66592, bempsts, bempenb);
  1091. }
  1092. if (intsts0 & M66592_CTRT)
  1093. irq_control_stage(m66592);
  1094. }
  1095. m66592_write(m66592, savepipe, M66592_CFIFOSEL);
  1096. spin_unlock(&m66592->lock);
  1097. return IRQ_HANDLED;
  1098. }
  1099. static void m66592_timer(unsigned long _m66592)
  1100. {
  1101. struct m66592 *m66592 = (struct m66592 *)_m66592;
  1102. unsigned long flags;
  1103. u16 tmp;
  1104. spin_lock_irqsave(&m66592->lock, flags);
  1105. tmp = m66592_read(m66592, M66592_SYSCFG);
  1106. if (!(tmp & M66592_RCKE)) {
  1107. m66592_bset(m66592, M66592_RCKE | M66592_PLLC, M66592_SYSCFG);
  1108. udelay(10);
  1109. m66592_bset(m66592, M66592_SCKE, M66592_SYSCFG);
  1110. }
  1111. if (m66592->scount > 0) {
  1112. tmp = m66592_read(m66592, M66592_INTSTS0) & M66592_VBSTS;
  1113. if (tmp == m66592->old_vbus) {
  1114. m66592->scount--;
  1115. if (m66592->scount == 0) {
  1116. if (tmp == M66592_VBSTS)
  1117. m66592_usb_connect(m66592);
  1118. else
  1119. m66592_usb_disconnect(m66592);
  1120. } else {
  1121. mod_timer(&m66592->timer,
  1122. jiffies + msecs_to_jiffies(50));
  1123. }
  1124. } else {
  1125. m66592->scount = M66592_MAX_SAMPLING;
  1126. m66592->old_vbus = tmp;
  1127. mod_timer(&m66592->timer,
  1128. jiffies + msecs_to_jiffies(50));
  1129. }
  1130. }
  1131. spin_unlock_irqrestore(&m66592->lock, flags);
  1132. }
  1133. /*-------------------------------------------------------------------------*/
  1134. static int m66592_enable(struct usb_ep *_ep,
  1135. const struct usb_endpoint_descriptor *desc)
  1136. {
  1137. struct m66592_ep *ep;
  1138. ep = container_of(_ep, struct m66592_ep, ep);
  1139. return alloc_pipe_config(ep, desc);
  1140. }
  1141. static int m66592_disable(struct usb_ep *_ep)
  1142. {
  1143. struct m66592_ep *ep;
  1144. struct m66592_request *req;
  1145. unsigned long flags;
  1146. ep = container_of(_ep, struct m66592_ep, ep);
  1147. BUG_ON(!ep);
  1148. while (!list_empty(&ep->queue)) {
  1149. req = list_entry(ep->queue.next, struct m66592_request, queue);
  1150. spin_lock_irqsave(&ep->m66592->lock, flags);
  1151. transfer_complete(ep, req, -ECONNRESET);
  1152. spin_unlock_irqrestore(&ep->m66592->lock, flags);
  1153. }
  1154. pipe_irq_disable(ep->m66592, ep->pipenum);
  1155. return free_pipe_config(ep);
  1156. }
  1157. static struct usb_request *m66592_alloc_request(struct usb_ep *_ep,
  1158. gfp_t gfp_flags)
  1159. {
  1160. struct m66592_request *req;
  1161. req = kzalloc(sizeof(struct m66592_request), gfp_flags);
  1162. if (!req)
  1163. return NULL;
  1164. INIT_LIST_HEAD(&req->queue);
  1165. return &req->req;
  1166. }
  1167. static void m66592_free_request(struct usb_ep *_ep, struct usb_request *_req)
  1168. {
  1169. struct m66592_request *req;
  1170. req = container_of(_req, struct m66592_request, req);
  1171. kfree(req);
  1172. }
  1173. static int m66592_queue(struct usb_ep *_ep, struct usb_request *_req,
  1174. gfp_t gfp_flags)
  1175. {
  1176. struct m66592_ep *ep;
  1177. struct m66592_request *req;
  1178. unsigned long flags;
  1179. int request = 0;
  1180. ep = container_of(_ep, struct m66592_ep, ep);
  1181. req = container_of(_req, struct m66592_request, req);
  1182. if (ep->m66592->gadget.speed == USB_SPEED_UNKNOWN)
  1183. return -ESHUTDOWN;
  1184. spin_lock_irqsave(&ep->m66592->lock, flags);
  1185. if (list_empty(&ep->queue))
  1186. request = 1;
  1187. list_add_tail(&req->queue, &ep->queue);
  1188. req->req.actual = 0;
  1189. req->req.status = -EINPROGRESS;
  1190. if (ep->desc == NULL) /* control */
  1191. start_ep0(ep, req);
  1192. else {
  1193. if (request && !ep->busy)
  1194. start_packet(ep, req);
  1195. }
  1196. spin_unlock_irqrestore(&ep->m66592->lock, flags);
  1197. return 0;
  1198. }
  1199. static int m66592_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  1200. {
  1201. struct m66592_ep *ep;
  1202. struct m66592_request *req;
  1203. unsigned long flags;
  1204. ep = container_of(_ep, struct m66592_ep, ep);
  1205. req = container_of(_req, struct m66592_request, req);
  1206. spin_lock_irqsave(&ep->m66592->lock, flags);
  1207. if (!list_empty(&ep->queue))
  1208. transfer_complete(ep, req, -ECONNRESET);
  1209. spin_unlock_irqrestore(&ep->m66592->lock, flags);
  1210. return 0;
  1211. }
  1212. static int m66592_set_halt(struct usb_ep *_ep, int value)
  1213. {
  1214. struct m66592_ep *ep;
  1215. struct m66592_request *req;
  1216. unsigned long flags;
  1217. int ret = 0;
  1218. ep = container_of(_ep, struct m66592_ep, ep);
  1219. req = list_entry(ep->queue.next, struct m66592_request, queue);
  1220. spin_lock_irqsave(&ep->m66592->lock, flags);
  1221. if (!list_empty(&ep->queue)) {
  1222. ret = -EAGAIN;
  1223. goto out;
  1224. }
  1225. if (value) {
  1226. ep->busy = 1;
  1227. pipe_stall(ep->m66592, ep->pipenum);
  1228. } else {
  1229. ep->busy = 0;
  1230. pipe_stop(ep->m66592, ep->pipenum);
  1231. }
  1232. out:
  1233. spin_unlock_irqrestore(&ep->m66592->lock, flags);
  1234. return ret;
  1235. }
  1236. static void m66592_fifo_flush(struct usb_ep *_ep)
  1237. {
  1238. struct m66592_ep *ep;
  1239. unsigned long flags;
  1240. ep = container_of(_ep, struct m66592_ep, ep);
  1241. spin_lock_irqsave(&ep->m66592->lock, flags);
  1242. if (list_empty(&ep->queue) && !ep->busy) {
  1243. pipe_stop(ep->m66592, ep->pipenum);
  1244. m66592_bclr(ep->m66592, M66592_BCLR, ep->fifoctr);
  1245. }
  1246. spin_unlock_irqrestore(&ep->m66592->lock, flags);
  1247. }
  1248. static struct usb_ep_ops m66592_ep_ops = {
  1249. .enable = m66592_enable,
  1250. .disable = m66592_disable,
  1251. .alloc_request = m66592_alloc_request,
  1252. .free_request = m66592_free_request,
  1253. .queue = m66592_queue,
  1254. .dequeue = m66592_dequeue,
  1255. .set_halt = m66592_set_halt,
  1256. .fifo_flush = m66592_fifo_flush,
  1257. };
  1258. /*-------------------------------------------------------------------------*/
  1259. static struct m66592 *the_controller;
  1260. static int m66592_start(struct usb_gadget_driver *driver,
  1261. int (*bind)(struct usb_gadget *))
  1262. {
  1263. struct m66592 *m66592 = the_controller;
  1264. int retval;
  1265. if (!driver
  1266. || driver->speed != USB_SPEED_HIGH
  1267. || !bind
  1268. || !driver->setup)
  1269. return -EINVAL;
  1270. if (!m66592)
  1271. return -ENODEV;
  1272. if (m66592->driver)
  1273. return -EBUSY;
  1274. /* hook up the driver */
  1275. driver->driver.bus = NULL;
  1276. m66592->driver = driver;
  1277. m66592->gadget.dev.driver = &driver->driver;
  1278. retval = device_add(&m66592->gadget.dev);
  1279. if (retval) {
  1280. pr_err("device_add error (%d)\n", retval);
  1281. goto error;
  1282. }
  1283. retval = bind(&m66592->gadget);
  1284. if (retval) {
  1285. pr_err("bind to driver error (%d)\n", retval);
  1286. device_del(&m66592->gadget.dev);
  1287. goto error;
  1288. }
  1289. m66592_bset(m66592, M66592_VBSE | M66592_URST, M66592_INTENB0);
  1290. if (m66592_read(m66592, M66592_INTSTS0) & M66592_VBSTS) {
  1291. m66592_start_xclock(m66592);
  1292. /* start vbus sampling */
  1293. m66592->old_vbus = m66592_read(m66592,
  1294. M66592_INTSTS0) & M66592_VBSTS;
  1295. m66592->scount = M66592_MAX_SAMPLING;
  1296. mod_timer(&m66592->timer, jiffies + msecs_to_jiffies(50));
  1297. }
  1298. return 0;
  1299. error:
  1300. m66592->driver = NULL;
  1301. m66592->gadget.dev.driver = NULL;
  1302. return retval;
  1303. }
  1304. static int m66592_stop(struct usb_gadget_driver *driver)
  1305. {
  1306. struct m66592 *m66592 = the_controller;
  1307. unsigned long flags;
  1308. if (driver != m66592->driver || !driver->unbind)
  1309. return -EINVAL;
  1310. spin_lock_irqsave(&m66592->lock, flags);
  1311. if (m66592->gadget.speed != USB_SPEED_UNKNOWN)
  1312. m66592_usb_disconnect(m66592);
  1313. spin_unlock_irqrestore(&m66592->lock, flags);
  1314. m66592_bclr(m66592, M66592_VBSE | M66592_URST, M66592_INTENB0);
  1315. driver->unbind(&m66592->gadget);
  1316. m66592->gadget.dev.driver = NULL;
  1317. init_controller(m66592);
  1318. disable_controller(m66592);
  1319. device_del(&m66592->gadget.dev);
  1320. m66592->driver = NULL;
  1321. return 0;
  1322. }
  1323. /*-------------------------------------------------------------------------*/
  1324. static int m66592_get_frame(struct usb_gadget *_gadget)
  1325. {
  1326. struct m66592 *m66592 = gadget_to_m66592(_gadget);
  1327. return m66592_read(m66592, M66592_FRMNUM) & 0x03FF;
  1328. }
  1329. static int m66592_pullup(struct usb_gadget *gadget, int is_on)
  1330. {
  1331. struct m66592 *m66592 = gadget_to_m66592(gadget);
  1332. unsigned long flags;
  1333. spin_lock_irqsave(&m66592->lock, flags);
  1334. if (is_on)
  1335. m66592_bset(m66592, M66592_DPRPU, M66592_SYSCFG);
  1336. else
  1337. m66592_bclr(m66592, M66592_DPRPU, M66592_SYSCFG);
  1338. spin_unlock_irqrestore(&m66592->lock, flags);
  1339. return 0;
  1340. }
  1341. static struct usb_gadget_ops m66592_gadget_ops = {
  1342. .get_frame = m66592_get_frame,
  1343. .start = m66592_start,
  1344. .stop = m66592_stop,
  1345. .pullup = m66592_pullup,
  1346. };
  1347. static int __exit m66592_remove(struct platform_device *pdev)
  1348. {
  1349. struct m66592 *m66592 = dev_get_drvdata(&pdev->dev);
  1350. usb_del_gadget_udc(&m66592->gadget);
  1351. del_timer_sync(&m66592->timer);
  1352. iounmap(m66592->reg);
  1353. free_irq(platform_get_irq(pdev, 0), m66592);
  1354. m66592_free_request(&m66592->ep[0].ep, m66592->ep0_req);
  1355. #ifdef CONFIG_HAVE_CLK
  1356. if (m66592->pdata->on_chip) {
  1357. clk_disable(m66592->clk);
  1358. clk_put(m66592->clk);
  1359. }
  1360. #endif
  1361. kfree(m66592);
  1362. return 0;
  1363. }
  1364. static void nop_completion(struct usb_ep *ep, struct usb_request *r)
  1365. {
  1366. }
  1367. static int __init m66592_probe(struct platform_device *pdev)
  1368. {
  1369. struct resource *res, *ires;
  1370. void __iomem *reg = NULL;
  1371. struct m66592 *m66592 = NULL;
  1372. #ifdef CONFIG_HAVE_CLK
  1373. char clk_name[8];
  1374. #endif
  1375. int ret = 0;
  1376. int i;
  1377. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1378. if (!res) {
  1379. ret = -ENODEV;
  1380. pr_err("platform_get_resource error.\n");
  1381. goto clean_up;
  1382. }
  1383. ires = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  1384. if (!ires) {
  1385. ret = -ENODEV;
  1386. dev_err(&pdev->dev,
  1387. "platform_get_resource IORESOURCE_IRQ error.\n");
  1388. goto clean_up;
  1389. }
  1390. reg = ioremap(res->start, resource_size(res));
  1391. if (reg == NULL) {
  1392. ret = -ENOMEM;
  1393. pr_err("ioremap error.\n");
  1394. goto clean_up;
  1395. }
  1396. if (pdev->dev.platform_data == NULL) {
  1397. dev_err(&pdev->dev, "no platform data\n");
  1398. ret = -ENODEV;
  1399. goto clean_up;
  1400. }
  1401. /* initialize ucd */
  1402. m66592 = kzalloc(sizeof(struct m66592), GFP_KERNEL);
  1403. if (m66592 == NULL) {
  1404. ret = -ENOMEM;
  1405. pr_err("kzalloc error\n");
  1406. goto clean_up;
  1407. }
  1408. m66592->pdata = pdev->dev.platform_data;
  1409. m66592->irq_trigger = ires->flags & IRQF_TRIGGER_MASK;
  1410. spin_lock_init(&m66592->lock);
  1411. dev_set_drvdata(&pdev->dev, m66592);
  1412. m66592->gadget.ops = &m66592_gadget_ops;
  1413. device_initialize(&m66592->gadget.dev);
  1414. dev_set_name(&m66592->gadget.dev, "gadget");
  1415. m66592->gadget.is_dualspeed = 1;
  1416. m66592->gadget.dev.parent = &pdev->dev;
  1417. m66592->gadget.dev.dma_mask = pdev->dev.dma_mask;
  1418. m66592->gadget.dev.release = pdev->dev.release;
  1419. m66592->gadget.name = udc_name;
  1420. init_timer(&m66592->timer);
  1421. m66592->timer.function = m66592_timer;
  1422. m66592->timer.data = (unsigned long)m66592;
  1423. m66592->reg = reg;
  1424. ret = request_irq(ires->start, m66592_irq, IRQF_DISABLED | IRQF_SHARED,
  1425. udc_name, m66592);
  1426. if (ret < 0) {
  1427. pr_err("request_irq error (%d)\n", ret);
  1428. goto clean_up;
  1429. }
  1430. #ifdef CONFIG_HAVE_CLK
  1431. if (m66592->pdata->on_chip) {
  1432. snprintf(clk_name, sizeof(clk_name), "usbf%d", pdev->id);
  1433. m66592->clk = clk_get(&pdev->dev, clk_name);
  1434. if (IS_ERR(m66592->clk)) {
  1435. dev_err(&pdev->dev, "cannot get clock \"%s\"\n",
  1436. clk_name);
  1437. ret = PTR_ERR(m66592->clk);
  1438. goto clean_up2;
  1439. }
  1440. clk_enable(m66592->clk);
  1441. }
  1442. #endif
  1443. INIT_LIST_HEAD(&m66592->gadget.ep_list);
  1444. m66592->gadget.ep0 = &m66592->ep[0].ep;
  1445. INIT_LIST_HEAD(&m66592->gadget.ep0->ep_list);
  1446. for (i = 0; i < M66592_MAX_NUM_PIPE; i++) {
  1447. struct m66592_ep *ep = &m66592->ep[i];
  1448. if (i != 0) {
  1449. INIT_LIST_HEAD(&m66592->ep[i].ep.ep_list);
  1450. list_add_tail(&m66592->ep[i].ep.ep_list,
  1451. &m66592->gadget.ep_list);
  1452. }
  1453. ep->m66592 = m66592;
  1454. INIT_LIST_HEAD(&ep->queue);
  1455. ep->ep.name = m66592_ep_name[i];
  1456. ep->ep.ops = &m66592_ep_ops;
  1457. ep->ep.maxpacket = 512;
  1458. }
  1459. m66592->ep[0].ep.maxpacket = 64;
  1460. m66592->ep[0].pipenum = 0;
  1461. m66592->ep[0].fifoaddr = M66592_CFIFO;
  1462. m66592->ep[0].fifosel = M66592_CFIFOSEL;
  1463. m66592->ep[0].fifoctr = M66592_CFIFOCTR;
  1464. m66592->ep[0].fifotrn = 0;
  1465. m66592->ep[0].pipectr = get_pipectr_addr(0);
  1466. m66592->pipenum2ep[0] = &m66592->ep[0];
  1467. m66592->epaddr2ep[0] = &m66592->ep[0];
  1468. the_controller = m66592;
  1469. m66592->ep0_req = m66592_alloc_request(&m66592->ep[0].ep, GFP_KERNEL);
  1470. if (m66592->ep0_req == NULL)
  1471. goto clean_up3;
  1472. m66592->ep0_req->complete = nop_completion;
  1473. init_controller(m66592);
  1474. ret = usb_add_gadget_udc(&pdev->dev, &m66592->gadget);
  1475. if (ret)
  1476. goto err_add_udc;
  1477. dev_info(&pdev->dev, "version %s\n", DRIVER_VERSION);
  1478. return 0;
  1479. err_add_udc:
  1480. m66592_free_request(&m66592->ep[0].ep, m66592->ep0_req);
  1481. clean_up3:
  1482. #ifdef CONFIG_HAVE_CLK
  1483. if (m66592->pdata->on_chip) {
  1484. clk_disable(m66592->clk);
  1485. clk_put(m66592->clk);
  1486. }
  1487. clean_up2:
  1488. #endif
  1489. free_irq(ires->start, m66592);
  1490. clean_up:
  1491. if (m66592) {
  1492. if (m66592->ep0_req)
  1493. m66592_free_request(&m66592->ep[0].ep, m66592->ep0_req);
  1494. kfree(m66592);
  1495. }
  1496. if (reg)
  1497. iounmap(reg);
  1498. return ret;
  1499. }
  1500. /*-------------------------------------------------------------------------*/
  1501. static struct platform_driver m66592_driver = {
  1502. .remove = __exit_p(m66592_remove),
  1503. .driver = {
  1504. .name = (char *) udc_name,
  1505. .owner = THIS_MODULE,
  1506. },
  1507. };
  1508. static int __init m66592_udc_init(void)
  1509. {
  1510. return platform_driver_probe(&m66592_driver, m66592_probe);
  1511. }
  1512. module_init(m66592_udc_init);
  1513. static void __exit m66592_udc_cleanup(void)
  1514. {
  1515. platform_driver_unregister(&m66592_driver);
  1516. }
  1517. module_exit(m66592_udc_cleanup);