langwell_udc.c 89 KB

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  1. /*
  2. * Intel Langwell USB Device Controller driver
  3. * Copyright (C) 2008-2009, Intel Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms and conditions of the GNU General Public License,
  7. * version 2, as published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc.,
  16. * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
  17. *
  18. */
  19. /* #undef DEBUG */
  20. /* #undef VERBOSE_DEBUG */
  21. #if defined(CONFIG_USB_LANGWELL_OTG)
  22. #define OTG_TRANSCEIVER
  23. #endif
  24. #include <linux/module.h>
  25. #include <linux/pci.h>
  26. #include <linux/dma-mapping.h>
  27. #include <linux/kernel.h>
  28. #include <linux/delay.h>
  29. #include <linux/ioport.h>
  30. #include <linux/sched.h>
  31. #include <linux/slab.h>
  32. #include <linux/errno.h>
  33. #include <linux/init.h>
  34. #include <linux/timer.h>
  35. #include <linux/list.h>
  36. #include <linux/interrupt.h>
  37. #include <linux/moduleparam.h>
  38. #include <linux/device.h>
  39. #include <linux/usb/ch9.h>
  40. #include <linux/usb/gadget.h>
  41. #include <linux/usb/otg.h>
  42. #include <linux/pm.h>
  43. #include <linux/io.h>
  44. #include <linux/irq.h>
  45. #include <asm/system.h>
  46. #include <asm/unaligned.h>
  47. #include "langwell_udc.h"
  48. #define DRIVER_DESC "Intel Langwell USB Device Controller driver"
  49. #define DRIVER_VERSION "16 May 2009"
  50. static const char driver_name[] = "langwell_udc";
  51. static const char driver_desc[] = DRIVER_DESC;
  52. /* controller device global variable */
  53. static struct langwell_udc *the_controller;
  54. /* for endpoint 0 operations */
  55. static const struct usb_endpoint_descriptor
  56. langwell_ep0_desc = {
  57. .bLength = USB_DT_ENDPOINT_SIZE,
  58. .bDescriptorType = USB_DT_ENDPOINT,
  59. .bEndpointAddress = 0,
  60. .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
  61. .wMaxPacketSize = EP0_MAX_PKT_SIZE,
  62. };
  63. /*-------------------------------------------------------------------------*/
  64. /* debugging */
  65. #ifdef VERBOSE_DEBUG
  66. static inline void print_all_registers(struct langwell_udc *dev)
  67. {
  68. int i;
  69. /* Capability Registers */
  70. dev_dbg(&dev->pdev->dev,
  71. "Capability Registers (offset: 0x%04x, length: 0x%08x)\n",
  72. CAP_REG_OFFSET, (u32)sizeof(struct langwell_cap_regs));
  73. dev_dbg(&dev->pdev->dev, "caplength=0x%02x\n",
  74. readb(&dev->cap_regs->caplength));
  75. dev_dbg(&dev->pdev->dev, "hciversion=0x%04x\n",
  76. readw(&dev->cap_regs->hciversion));
  77. dev_dbg(&dev->pdev->dev, "hcsparams=0x%08x\n",
  78. readl(&dev->cap_regs->hcsparams));
  79. dev_dbg(&dev->pdev->dev, "hccparams=0x%08x\n",
  80. readl(&dev->cap_regs->hccparams));
  81. dev_dbg(&dev->pdev->dev, "dciversion=0x%04x\n",
  82. readw(&dev->cap_regs->dciversion));
  83. dev_dbg(&dev->pdev->dev, "dccparams=0x%08x\n",
  84. readl(&dev->cap_regs->dccparams));
  85. /* Operational Registers */
  86. dev_dbg(&dev->pdev->dev,
  87. "Operational Registers (offset: 0x%04x, length: 0x%08x)\n",
  88. OP_REG_OFFSET, (u32)sizeof(struct langwell_op_regs));
  89. dev_dbg(&dev->pdev->dev, "extsts=0x%08x\n",
  90. readl(&dev->op_regs->extsts));
  91. dev_dbg(&dev->pdev->dev, "extintr=0x%08x\n",
  92. readl(&dev->op_regs->extintr));
  93. dev_dbg(&dev->pdev->dev, "usbcmd=0x%08x\n",
  94. readl(&dev->op_regs->usbcmd));
  95. dev_dbg(&dev->pdev->dev, "usbsts=0x%08x\n",
  96. readl(&dev->op_regs->usbsts));
  97. dev_dbg(&dev->pdev->dev, "usbintr=0x%08x\n",
  98. readl(&dev->op_regs->usbintr));
  99. dev_dbg(&dev->pdev->dev, "frindex=0x%08x\n",
  100. readl(&dev->op_regs->frindex));
  101. dev_dbg(&dev->pdev->dev, "ctrldssegment=0x%08x\n",
  102. readl(&dev->op_regs->ctrldssegment));
  103. dev_dbg(&dev->pdev->dev, "deviceaddr=0x%08x\n",
  104. readl(&dev->op_regs->deviceaddr));
  105. dev_dbg(&dev->pdev->dev, "endpointlistaddr=0x%08x\n",
  106. readl(&dev->op_regs->endpointlistaddr));
  107. dev_dbg(&dev->pdev->dev, "ttctrl=0x%08x\n",
  108. readl(&dev->op_regs->ttctrl));
  109. dev_dbg(&dev->pdev->dev, "burstsize=0x%08x\n",
  110. readl(&dev->op_regs->burstsize));
  111. dev_dbg(&dev->pdev->dev, "txfilltuning=0x%08x\n",
  112. readl(&dev->op_regs->txfilltuning));
  113. dev_dbg(&dev->pdev->dev, "txttfilltuning=0x%08x\n",
  114. readl(&dev->op_regs->txttfilltuning));
  115. dev_dbg(&dev->pdev->dev, "ic_usb=0x%08x\n",
  116. readl(&dev->op_regs->ic_usb));
  117. dev_dbg(&dev->pdev->dev, "ulpi_viewport=0x%08x\n",
  118. readl(&dev->op_regs->ulpi_viewport));
  119. dev_dbg(&dev->pdev->dev, "configflag=0x%08x\n",
  120. readl(&dev->op_regs->configflag));
  121. dev_dbg(&dev->pdev->dev, "portsc1=0x%08x\n",
  122. readl(&dev->op_regs->portsc1));
  123. dev_dbg(&dev->pdev->dev, "devlc=0x%08x\n",
  124. readl(&dev->op_regs->devlc));
  125. dev_dbg(&dev->pdev->dev, "otgsc=0x%08x\n",
  126. readl(&dev->op_regs->otgsc));
  127. dev_dbg(&dev->pdev->dev, "usbmode=0x%08x\n",
  128. readl(&dev->op_regs->usbmode));
  129. dev_dbg(&dev->pdev->dev, "endptnak=0x%08x\n",
  130. readl(&dev->op_regs->endptnak));
  131. dev_dbg(&dev->pdev->dev, "endptnaken=0x%08x\n",
  132. readl(&dev->op_regs->endptnaken));
  133. dev_dbg(&dev->pdev->dev, "endptsetupstat=0x%08x\n",
  134. readl(&dev->op_regs->endptsetupstat));
  135. dev_dbg(&dev->pdev->dev, "endptprime=0x%08x\n",
  136. readl(&dev->op_regs->endptprime));
  137. dev_dbg(&dev->pdev->dev, "endptflush=0x%08x\n",
  138. readl(&dev->op_regs->endptflush));
  139. dev_dbg(&dev->pdev->dev, "endptstat=0x%08x\n",
  140. readl(&dev->op_regs->endptstat));
  141. dev_dbg(&dev->pdev->dev, "endptcomplete=0x%08x\n",
  142. readl(&dev->op_regs->endptcomplete));
  143. for (i = 0; i < dev->ep_max / 2; i++) {
  144. dev_dbg(&dev->pdev->dev, "endptctrl[%d]=0x%08x\n",
  145. i, readl(&dev->op_regs->endptctrl[i]));
  146. }
  147. }
  148. #else
  149. #define print_all_registers(dev) do { } while (0)
  150. #endif /* VERBOSE_DEBUG */
  151. /*-------------------------------------------------------------------------*/
  152. #define is_in(ep) (((ep)->ep_num == 0) ? ((ep)->dev->ep0_dir == \
  153. USB_DIR_IN) : (usb_endpoint_dir_in((ep)->desc)))
  154. #define DIR_STRING(ep) (is_in(ep) ? "in" : "out")
  155. static char *type_string(const struct usb_endpoint_descriptor *desc)
  156. {
  157. switch (usb_endpoint_type(desc)) {
  158. case USB_ENDPOINT_XFER_BULK:
  159. return "bulk";
  160. case USB_ENDPOINT_XFER_ISOC:
  161. return "iso";
  162. case USB_ENDPOINT_XFER_INT:
  163. return "int";
  164. };
  165. return "control";
  166. }
  167. /* configure endpoint control registers */
  168. static void ep_reset(struct langwell_ep *ep, unsigned char ep_num,
  169. unsigned char is_in, unsigned char ep_type)
  170. {
  171. struct langwell_udc *dev;
  172. u32 endptctrl;
  173. dev = ep->dev;
  174. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  175. endptctrl = readl(&dev->op_regs->endptctrl[ep_num]);
  176. if (is_in) { /* TX */
  177. if (ep_num)
  178. endptctrl |= EPCTRL_TXR;
  179. endptctrl |= EPCTRL_TXE;
  180. endptctrl |= ep_type << EPCTRL_TXT_SHIFT;
  181. } else { /* RX */
  182. if (ep_num)
  183. endptctrl |= EPCTRL_RXR;
  184. endptctrl |= EPCTRL_RXE;
  185. endptctrl |= ep_type << EPCTRL_RXT_SHIFT;
  186. }
  187. writel(endptctrl, &dev->op_regs->endptctrl[ep_num]);
  188. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  189. }
  190. /* reset ep0 dQH and endptctrl */
  191. static void ep0_reset(struct langwell_udc *dev)
  192. {
  193. struct langwell_ep *ep;
  194. int i;
  195. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  196. /* ep0 in and out */
  197. for (i = 0; i < 2; i++) {
  198. ep = &dev->ep[i];
  199. ep->dev = dev;
  200. /* ep0 dQH */
  201. ep->dqh = &dev->ep_dqh[i];
  202. /* configure ep0 endpoint capabilities in dQH */
  203. ep->dqh->dqh_ios = 1;
  204. ep->dqh->dqh_mpl = EP0_MAX_PKT_SIZE;
  205. /* enable ep0-in HW zero length termination select */
  206. if (is_in(ep))
  207. ep->dqh->dqh_zlt = 0;
  208. ep->dqh->dqh_mult = 0;
  209. ep->dqh->dtd_next = DTD_TERM;
  210. /* configure ep0 control registers */
  211. ep_reset(&dev->ep[0], 0, i, USB_ENDPOINT_XFER_CONTROL);
  212. }
  213. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  214. }
  215. /*-------------------------------------------------------------------------*/
  216. /* endpoints operations */
  217. /* configure endpoint, making it usable */
  218. static int langwell_ep_enable(struct usb_ep *_ep,
  219. const struct usb_endpoint_descriptor *desc)
  220. {
  221. struct langwell_udc *dev;
  222. struct langwell_ep *ep;
  223. u16 max = 0;
  224. unsigned long flags;
  225. int i, retval = 0;
  226. unsigned char zlt, ios = 0, mult = 0;
  227. ep = container_of(_ep, struct langwell_ep, ep);
  228. dev = ep->dev;
  229. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  230. if (!_ep || !desc || ep->desc
  231. || desc->bDescriptorType != USB_DT_ENDPOINT)
  232. return -EINVAL;
  233. if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
  234. return -ESHUTDOWN;
  235. max = le16_to_cpu(desc->wMaxPacketSize);
  236. /*
  237. * disable HW zero length termination select
  238. * driver handles zero length packet through req->req.zero
  239. */
  240. zlt = 1;
  241. /*
  242. * sanity check type, direction, address, and then
  243. * initialize the endpoint capabilities fields in dQH
  244. */
  245. switch (usb_endpoint_type(desc)) {
  246. case USB_ENDPOINT_XFER_CONTROL:
  247. ios = 1;
  248. break;
  249. case USB_ENDPOINT_XFER_BULK:
  250. if ((dev->gadget.speed == USB_SPEED_HIGH
  251. && max != 512)
  252. || (dev->gadget.speed == USB_SPEED_FULL
  253. && max > 64)) {
  254. goto done;
  255. }
  256. break;
  257. case USB_ENDPOINT_XFER_INT:
  258. if (strstr(ep->ep.name, "-iso")) /* bulk is ok */
  259. goto done;
  260. switch (dev->gadget.speed) {
  261. case USB_SPEED_HIGH:
  262. if (max <= 1024)
  263. break;
  264. case USB_SPEED_FULL:
  265. if (max <= 64)
  266. break;
  267. default:
  268. if (max <= 8)
  269. break;
  270. goto done;
  271. }
  272. break;
  273. case USB_ENDPOINT_XFER_ISOC:
  274. if (strstr(ep->ep.name, "-bulk")
  275. || strstr(ep->ep.name, "-int"))
  276. goto done;
  277. switch (dev->gadget.speed) {
  278. case USB_SPEED_HIGH:
  279. if (max <= 1024)
  280. break;
  281. case USB_SPEED_FULL:
  282. if (max <= 1023)
  283. break;
  284. default:
  285. goto done;
  286. }
  287. /*
  288. * FIXME:
  289. * calculate transactions needed for high bandwidth iso
  290. */
  291. mult = (unsigned char)(1 + ((max >> 11) & 0x03));
  292. max = max & 0x8ff; /* bit 0~10 */
  293. /* 3 transactions at most */
  294. if (mult > 3)
  295. goto done;
  296. break;
  297. default:
  298. goto done;
  299. }
  300. spin_lock_irqsave(&dev->lock, flags);
  301. ep->ep.maxpacket = max;
  302. ep->desc = desc;
  303. ep->stopped = 0;
  304. ep->ep_num = usb_endpoint_num(desc);
  305. /* ep_type */
  306. ep->ep_type = usb_endpoint_type(desc);
  307. /* configure endpoint control registers */
  308. ep_reset(ep, ep->ep_num, is_in(ep), ep->ep_type);
  309. /* configure endpoint capabilities in dQH */
  310. i = ep->ep_num * 2 + is_in(ep);
  311. ep->dqh = &dev->ep_dqh[i];
  312. ep->dqh->dqh_ios = ios;
  313. ep->dqh->dqh_mpl = cpu_to_le16(max);
  314. ep->dqh->dqh_zlt = zlt;
  315. ep->dqh->dqh_mult = mult;
  316. ep->dqh->dtd_next = DTD_TERM;
  317. dev_dbg(&dev->pdev->dev, "enabled %s (ep%d%s-%s), max %04x\n",
  318. _ep->name,
  319. ep->ep_num,
  320. DIR_STRING(ep),
  321. type_string(desc),
  322. max);
  323. spin_unlock_irqrestore(&dev->lock, flags);
  324. done:
  325. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  326. return retval;
  327. }
  328. /*-------------------------------------------------------------------------*/
  329. /* retire a request */
  330. static void done(struct langwell_ep *ep, struct langwell_request *req,
  331. int status)
  332. {
  333. struct langwell_udc *dev = ep->dev;
  334. unsigned stopped = ep->stopped;
  335. struct langwell_dtd *curr_dtd, *next_dtd;
  336. int i;
  337. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  338. /* remove the req from ep->queue */
  339. list_del_init(&req->queue);
  340. if (req->req.status == -EINPROGRESS)
  341. req->req.status = status;
  342. else
  343. status = req->req.status;
  344. /* free dTD for the request */
  345. next_dtd = req->head;
  346. for (i = 0; i < req->dtd_count; i++) {
  347. curr_dtd = next_dtd;
  348. if (i != req->dtd_count - 1)
  349. next_dtd = curr_dtd->next_dtd_virt;
  350. dma_pool_free(dev->dtd_pool, curr_dtd, curr_dtd->dtd_dma);
  351. }
  352. if (req->mapped) {
  353. dma_unmap_single(&dev->pdev->dev,
  354. req->req.dma, req->req.length,
  355. is_in(ep) ? PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  356. req->req.dma = DMA_ADDR_INVALID;
  357. req->mapped = 0;
  358. } else
  359. dma_sync_single_for_cpu(&dev->pdev->dev, req->req.dma,
  360. req->req.length,
  361. is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  362. if (status != -ESHUTDOWN)
  363. dev_dbg(&dev->pdev->dev,
  364. "complete %s, req %p, stat %d, len %u/%u\n",
  365. ep->ep.name, &req->req, status,
  366. req->req.actual, req->req.length);
  367. /* don't modify queue heads during completion callback */
  368. ep->stopped = 1;
  369. spin_unlock(&dev->lock);
  370. /* complete routine from gadget driver */
  371. if (req->req.complete)
  372. req->req.complete(&ep->ep, &req->req);
  373. spin_lock(&dev->lock);
  374. ep->stopped = stopped;
  375. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  376. }
  377. static void langwell_ep_fifo_flush(struct usb_ep *_ep);
  378. /* delete all endpoint requests, called with spinlock held */
  379. static void nuke(struct langwell_ep *ep, int status)
  380. {
  381. /* called with spinlock held */
  382. ep->stopped = 1;
  383. /* endpoint fifo flush */
  384. if (&ep->ep && ep->desc)
  385. langwell_ep_fifo_flush(&ep->ep);
  386. while (!list_empty(&ep->queue)) {
  387. struct langwell_request *req = NULL;
  388. req = list_entry(ep->queue.next, struct langwell_request,
  389. queue);
  390. done(ep, req, status);
  391. }
  392. }
  393. /*-------------------------------------------------------------------------*/
  394. /* endpoint is no longer usable */
  395. static int langwell_ep_disable(struct usb_ep *_ep)
  396. {
  397. struct langwell_ep *ep;
  398. unsigned long flags;
  399. struct langwell_udc *dev;
  400. int ep_num;
  401. u32 endptctrl;
  402. ep = container_of(_ep, struct langwell_ep, ep);
  403. dev = ep->dev;
  404. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  405. if (!_ep || !ep->desc)
  406. return -EINVAL;
  407. spin_lock_irqsave(&dev->lock, flags);
  408. /* disable endpoint control register */
  409. ep_num = ep->ep_num;
  410. endptctrl = readl(&dev->op_regs->endptctrl[ep_num]);
  411. if (is_in(ep))
  412. endptctrl &= ~EPCTRL_TXE;
  413. else
  414. endptctrl &= ~EPCTRL_RXE;
  415. writel(endptctrl, &dev->op_regs->endptctrl[ep_num]);
  416. /* nuke all pending requests (does flush) */
  417. nuke(ep, -ESHUTDOWN);
  418. ep->desc = NULL;
  419. ep->stopped = 1;
  420. spin_unlock_irqrestore(&dev->lock, flags);
  421. dev_dbg(&dev->pdev->dev, "disabled %s\n", _ep->name);
  422. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  423. return 0;
  424. }
  425. /* allocate a request object to use with this endpoint */
  426. static struct usb_request *langwell_alloc_request(struct usb_ep *_ep,
  427. gfp_t gfp_flags)
  428. {
  429. struct langwell_ep *ep;
  430. struct langwell_udc *dev;
  431. struct langwell_request *req = NULL;
  432. if (!_ep)
  433. return NULL;
  434. ep = container_of(_ep, struct langwell_ep, ep);
  435. dev = ep->dev;
  436. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  437. req = kzalloc(sizeof(*req), gfp_flags);
  438. if (!req)
  439. return NULL;
  440. req->req.dma = DMA_ADDR_INVALID;
  441. INIT_LIST_HEAD(&req->queue);
  442. dev_vdbg(&dev->pdev->dev, "alloc request for %s\n", _ep->name);
  443. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  444. return &req->req;
  445. }
  446. /* free a request object */
  447. static void langwell_free_request(struct usb_ep *_ep,
  448. struct usb_request *_req)
  449. {
  450. struct langwell_ep *ep;
  451. struct langwell_udc *dev;
  452. struct langwell_request *req = NULL;
  453. ep = container_of(_ep, struct langwell_ep, ep);
  454. dev = ep->dev;
  455. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  456. if (!_ep || !_req)
  457. return;
  458. req = container_of(_req, struct langwell_request, req);
  459. WARN_ON(!list_empty(&req->queue));
  460. if (_req)
  461. kfree(req);
  462. dev_vdbg(&dev->pdev->dev, "free request for %s\n", _ep->name);
  463. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  464. }
  465. /*-------------------------------------------------------------------------*/
  466. /* queue dTD and PRIME endpoint */
  467. static int queue_dtd(struct langwell_ep *ep, struct langwell_request *req)
  468. {
  469. u32 bit_mask, usbcmd, endptstat, dtd_dma;
  470. u8 dtd_status;
  471. int i;
  472. struct langwell_dqh *dqh;
  473. struct langwell_udc *dev;
  474. dev = ep->dev;
  475. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  476. i = ep->ep_num * 2 + is_in(ep);
  477. dqh = &dev->ep_dqh[i];
  478. if (ep->ep_num)
  479. dev_vdbg(&dev->pdev->dev, "%s\n", ep->name);
  480. else
  481. /* ep0 */
  482. dev_vdbg(&dev->pdev->dev, "%s-%s\n", ep->name, DIR_STRING(ep));
  483. dev_vdbg(&dev->pdev->dev, "ep_dqh[%d] addr: 0x%p\n",
  484. i, &(dev->ep_dqh[i]));
  485. bit_mask = is_in(ep) ?
  486. (1 << (ep->ep_num + 16)) : (1 << (ep->ep_num));
  487. dev_vdbg(&dev->pdev->dev, "bit_mask = 0x%08x\n", bit_mask);
  488. /* check if the pipe is empty */
  489. if (!(list_empty(&ep->queue))) {
  490. /* add dTD to the end of linked list */
  491. struct langwell_request *lastreq;
  492. lastreq = list_entry(ep->queue.prev,
  493. struct langwell_request, queue);
  494. lastreq->tail->dtd_next =
  495. cpu_to_le32(req->head->dtd_dma & DTD_NEXT_MASK);
  496. /* read prime bit, if 1 goto out */
  497. if (readl(&dev->op_regs->endptprime) & bit_mask)
  498. goto out;
  499. do {
  500. /* set ATDTW bit in USBCMD */
  501. usbcmd = readl(&dev->op_regs->usbcmd);
  502. writel(usbcmd | CMD_ATDTW, &dev->op_regs->usbcmd);
  503. /* read correct status bit */
  504. endptstat = readl(&dev->op_regs->endptstat) & bit_mask;
  505. } while (!(readl(&dev->op_regs->usbcmd) & CMD_ATDTW));
  506. /* write ATDTW bit to 0 */
  507. usbcmd = readl(&dev->op_regs->usbcmd);
  508. writel(usbcmd & ~CMD_ATDTW, &dev->op_regs->usbcmd);
  509. if (endptstat)
  510. goto out;
  511. }
  512. /* write dQH next pointer and terminate bit to 0 */
  513. dtd_dma = req->head->dtd_dma & DTD_NEXT_MASK;
  514. dqh->dtd_next = cpu_to_le32(dtd_dma);
  515. /* clear active and halt bit */
  516. dtd_status = (u8) ~(DTD_STS_ACTIVE | DTD_STS_HALTED);
  517. dqh->dtd_status &= dtd_status;
  518. dev_vdbg(&dev->pdev->dev, "dqh->dtd_status = 0x%x\n", dqh->dtd_status);
  519. /* ensure that updates to the dQH will occur before priming */
  520. wmb();
  521. /* write 1 to endptprime register to PRIME endpoint */
  522. bit_mask = is_in(ep) ? (1 << (ep->ep_num + 16)) : (1 << ep->ep_num);
  523. dev_vdbg(&dev->pdev->dev, "endprime bit_mask = 0x%08x\n", bit_mask);
  524. writel(bit_mask, &dev->op_regs->endptprime);
  525. out:
  526. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  527. return 0;
  528. }
  529. /* fill in the dTD structure to build a transfer descriptor */
  530. static struct langwell_dtd *build_dtd(struct langwell_request *req,
  531. unsigned *length, dma_addr_t *dma, int *is_last)
  532. {
  533. u32 buf_ptr;
  534. struct langwell_dtd *dtd;
  535. struct langwell_udc *dev;
  536. int i;
  537. dev = req->ep->dev;
  538. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  539. /* the maximum transfer length, up to 16k bytes */
  540. *length = min(req->req.length - req->req.actual,
  541. (unsigned)DTD_MAX_TRANSFER_LENGTH);
  542. /* create dTD dma_pool resource */
  543. dtd = dma_pool_alloc(dev->dtd_pool, GFP_KERNEL, dma);
  544. if (dtd == NULL)
  545. return dtd;
  546. dtd->dtd_dma = *dma;
  547. /* initialize buffer page pointers */
  548. buf_ptr = (u32)(req->req.dma + req->req.actual);
  549. for (i = 0; i < 5; i++)
  550. dtd->dtd_buf[i] = cpu_to_le32(buf_ptr + i * PAGE_SIZE);
  551. req->req.actual += *length;
  552. /* fill in total bytes with transfer size */
  553. dtd->dtd_total = cpu_to_le16(*length);
  554. dev_vdbg(&dev->pdev->dev, "dtd->dtd_total = %d\n", dtd->dtd_total);
  555. /* set is_last flag if req->req.zero is set or not */
  556. if (req->req.zero) {
  557. if (*length == 0 || (*length % req->ep->ep.maxpacket) != 0)
  558. *is_last = 1;
  559. else
  560. *is_last = 0;
  561. } else if (req->req.length == req->req.actual) {
  562. *is_last = 1;
  563. } else
  564. *is_last = 0;
  565. if (*is_last == 0)
  566. dev_vdbg(&dev->pdev->dev, "multi-dtd request!\n");
  567. /* set interrupt on complete bit for the last dTD */
  568. if (*is_last && !req->req.no_interrupt)
  569. dtd->dtd_ioc = 1;
  570. /* set multiplier override 0 for non-ISO and non-TX endpoint */
  571. dtd->dtd_multo = 0;
  572. /* set the active bit of status field to 1 */
  573. dtd->dtd_status = DTD_STS_ACTIVE;
  574. dev_vdbg(&dev->pdev->dev, "dtd->dtd_status = 0x%02x\n",
  575. dtd->dtd_status);
  576. dev_vdbg(&dev->pdev->dev, "length = %d, dma addr= 0x%08x\n",
  577. *length, (int)*dma);
  578. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  579. return dtd;
  580. }
  581. /* generate dTD linked list for a request */
  582. static int req_to_dtd(struct langwell_request *req)
  583. {
  584. unsigned count;
  585. int is_last, is_first = 1;
  586. struct langwell_dtd *dtd, *last_dtd = NULL;
  587. struct langwell_udc *dev;
  588. dma_addr_t dma;
  589. dev = req->ep->dev;
  590. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  591. do {
  592. dtd = build_dtd(req, &count, &dma, &is_last);
  593. if (dtd == NULL)
  594. return -ENOMEM;
  595. if (is_first) {
  596. is_first = 0;
  597. req->head = dtd;
  598. } else {
  599. last_dtd->dtd_next = cpu_to_le32(dma);
  600. last_dtd->next_dtd_virt = dtd;
  601. }
  602. last_dtd = dtd;
  603. req->dtd_count++;
  604. } while (!is_last);
  605. /* set terminate bit to 1 for the last dTD */
  606. dtd->dtd_next = DTD_TERM;
  607. req->tail = dtd;
  608. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  609. return 0;
  610. }
  611. /*-------------------------------------------------------------------------*/
  612. /* queue (submits) an I/O requests to an endpoint */
  613. static int langwell_ep_queue(struct usb_ep *_ep, struct usb_request *_req,
  614. gfp_t gfp_flags)
  615. {
  616. struct langwell_request *req;
  617. struct langwell_ep *ep;
  618. struct langwell_udc *dev;
  619. unsigned long flags;
  620. int is_iso = 0, zlflag = 0;
  621. /* always require a cpu-view buffer */
  622. req = container_of(_req, struct langwell_request, req);
  623. ep = container_of(_ep, struct langwell_ep, ep);
  624. if (!_req || !_req->complete || !_req->buf
  625. || !list_empty(&req->queue)) {
  626. return -EINVAL;
  627. }
  628. if (unlikely(!_ep || !ep->desc))
  629. return -EINVAL;
  630. dev = ep->dev;
  631. req->ep = ep;
  632. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  633. if (usb_endpoint_xfer_isoc(ep->desc)) {
  634. if (req->req.length > ep->ep.maxpacket)
  635. return -EMSGSIZE;
  636. is_iso = 1;
  637. }
  638. if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN))
  639. return -ESHUTDOWN;
  640. /* set up dma mapping in case the caller didn't */
  641. if (_req->dma == DMA_ADDR_INVALID) {
  642. /* WORKAROUND: WARN_ON(size == 0) */
  643. if (_req->length == 0) {
  644. dev_vdbg(&dev->pdev->dev, "req->length: 0->1\n");
  645. zlflag = 1;
  646. _req->length++;
  647. }
  648. _req->dma = dma_map_single(&dev->pdev->dev,
  649. _req->buf, _req->length,
  650. is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  651. if (zlflag && (_req->length == 1)) {
  652. dev_vdbg(&dev->pdev->dev, "req->length: 1->0\n");
  653. zlflag = 0;
  654. _req->length = 0;
  655. }
  656. req->mapped = 1;
  657. dev_vdbg(&dev->pdev->dev, "req->mapped = 1\n");
  658. } else {
  659. dma_sync_single_for_device(&dev->pdev->dev,
  660. _req->dma, _req->length,
  661. is_in(ep) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
  662. req->mapped = 0;
  663. dev_vdbg(&dev->pdev->dev, "req->mapped = 0\n");
  664. }
  665. dev_dbg(&dev->pdev->dev,
  666. "%s queue req %p, len %u, buf %p, dma 0x%08x\n",
  667. _ep->name,
  668. _req, _req->length, _req->buf, (int)_req->dma);
  669. _req->status = -EINPROGRESS;
  670. _req->actual = 0;
  671. req->dtd_count = 0;
  672. spin_lock_irqsave(&dev->lock, flags);
  673. /* build and put dTDs to endpoint queue */
  674. if (!req_to_dtd(req)) {
  675. queue_dtd(ep, req);
  676. } else {
  677. spin_unlock_irqrestore(&dev->lock, flags);
  678. return -ENOMEM;
  679. }
  680. /* update ep0 state */
  681. if (ep->ep_num == 0)
  682. dev->ep0_state = DATA_STATE_XMIT;
  683. if (likely(req != NULL)) {
  684. list_add_tail(&req->queue, &ep->queue);
  685. dev_vdbg(&dev->pdev->dev, "list_add_tail()\n");
  686. }
  687. spin_unlock_irqrestore(&dev->lock, flags);
  688. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  689. return 0;
  690. }
  691. /* dequeue (cancels, unlinks) an I/O request from an endpoint */
  692. static int langwell_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
  693. {
  694. struct langwell_ep *ep;
  695. struct langwell_udc *dev;
  696. struct langwell_request *req;
  697. unsigned long flags;
  698. int stopped, ep_num, retval = 0;
  699. u32 endptctrl;
  700. ep = container_of(_ep, struct langwell_ep, ep);
  701. dev = ep->dev;
  702. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  703. if (!_ep || !ep->desc || !_req)
  704. return -EINVAL;
  705. if (!dev->driver)
  706. return -ESHUTDOWN;
  707. spin_lock_irqsave(&dev->lock, flags);
  708. stopped = ep->stopped;
  709. /* quiesce dma while we patch the queue */
  710. ep->stopped = 1;
  711. ep_num = ep->ep_num;
  712. /* disable endpoint control register */
  713. endptctrl = readl(&dev->op_regs->endptctrl[ep_num]);
  714. if (is_in(ep))
  715. endptctrl &= ~EPCTRL_TXE;
  716. else
  717. endptctrl &= ~EPCTRL_RXE;
  718. writel(endptctrl, &dev->op_regs->endptctrl[ep_num]);
  719. /* make sure it's still queued on this endpoint */
  720. list_for_each_entry(req, &ep->queue, queue) {
  721. if (&req->req == _req)
  722. break;
  723. }
  724. if (&req->req != _req) {
  725. retval = -EINVAL;
  726. goto done;
  727. }
  728. /* queue head may be partially complete. */
  729. if (ep->queue.next == &req->queue) {
  730. dev_dbg(&dev->pdev->dev, "unlink (%s) dma\n", _ep->name);
  731. _req->status = -ECONNRESET;
  732. langwell_ep_fifo_flush(&ep->ep);
  733. /* not the last request in endpoint queue */
  734. if (likely(ep->queue.next == &req->queue)) {
  735. struct langwell_dqh *dqh;
  736. struct langwell_request *next_req;
  737. dqh = ep->dqh;
  738. next_req = list_entry(req->queue.next,
  739. struct langwell_request, queue);
  740. /* point the dQH to the first dTD of next request */
  741. writel((u32) next_req->head, &dqh->dqh_current);
  742. }
  743. } else {
  744. struct langwell_request *prev_req;
  745. prev_req = list_entry(req->queue.prev,
  746. struct langwell_request, queue);
  747. writel(readl(&req->tail->dtd_next),
  748. &prev_req->tail->dtd_next);
  749. }
  750. done(ep, req, -ECONNRESET);
  751. done:
  752. /* enable endpoint again */
  753. endptctrl = readl(&dev->op_regs->endptctrl[ep_num]);
  754. if (is_in(ep))
  755. endptctrl |= EPCTRL_TXE;
  756. else
  757. endptctrl |= EPCTRL_RXE;
  758. writel(endptctrl, &dev->op_regs->endptctrl[ep_num]);
  759. ep->stopped = stopped;
  760. spin_unlock_irqrestore(&dev->lock, flags);
  761. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  762. return retval;
  763. }
  764. /*-------------------------------------------------------------------------*/
  765. /* endpoint set/clear halt */
  766. static void ep_set_halt(struct langwell_ep *ep, int value)
  767. {
  768. u32 endptctrl = 0;
  769. int ep_num;
  770. struct langwell_udc *dev = ep->dev;
  771. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  772. ep_num = ep->ep_num;
  773. endptctrl = readl(&dev->op_regs->endptctrl[ep_num]);
  774. /* value: 1 - set halt, 0 - clear halt */
  775. if (value) {
  776. /* set the stall bit */
  777. if (is_in(ep))
  778. endptctrl |= EPCTRL_TXS;
  779. else
  780. endptctrl |= EPCTRL_RXS;
  781. } else {
  782. /* clear the stall bit and reset data toggle */
  783. if (is_in(ep)) {
  784. endptctrl &= ~EPCTRL_TXS;
  785. endptctrl |= EPCTRL_TXR;
  786. } else {
  787. endptctrl &= ~EPCTRL_RXS;
  788. endptctrl |= EPCTRL_RXR;
  789. }
  790. }
  791. writel(endptctrl, &dev->op_regs->endptctrl[ep_num]);
  792. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  793. }
  794. /* set the endpoint halt feature */
  795. static int langwell_ep_set_halt(struct usb_ep *_ep, int value)
  796. {
  797. struct langwell_ep *ep;
  798. struct langwell_udc *dev;
  799. unsigned long flags;
  800. int retval = 0;
  801. ep = container_of(_ep, struct langwell_ep, ep);
  802. dev = ep->dev;
  803. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  804. if (!_ep || !ep->desc)
  805. return -EINVAL;
  806. if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)
  807. return -ESHUTDOWN;
  808. if (usb_endpoint_xfer_isoc(ep->desc))
  809. return -EOPNOTSUPP;
  810. spin_lock_irqsave(&dev->lock, flags);
  811. /*
  812. * attempt to halt IN ep will fail if any transfer requests
  813. * are still queue
  814. */
  815. if (!list_empty(&ep->queue) && is_in(ep) && value) {
  816. /* IN endpoint FIFO holds bytes */
  817. dev_dbg(&dev->pdev->dev, "%s FIFO holds bytes\n", _ep->name);
  818. retval = -EAGAIN;
  819. goto done;
  820. }
  821. /* endpoint set/clear halt */
  822. if (ep->ep_num) {
  823. ep_set_halt(ep, value);
  824. } else { /* endpoint 0 */
  825. dev->ep0_state = WAIT_FOR_SETUP;
  826. dev->ep0_dir = USB_DIR_OUT;
  827. }
  828. done:
  829. spin_unlock_irqrestore(&dev->lock, flags);
  830. dev_dbg(&dev->pdev->dev, "%s %s halt\n",
  831. _ep->name, value ? "set" : "clear");
  832. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  833. return retval;
  834. }
  835. /* set the halt feature and ignores clear requests */
  836. static int langwell_ep_set_wedge(struct usb_ep *_ep)
  837. {
  838. struct langwell_ep *ep;
  839. struct langwell_udc *dev;
  840. ep = container_of(_ep, struct langwell_ep, ep);
  841. dev = ep->dev;
  842. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  843. if (!_ep || !ep->desc)
  844. return -EINVAL;
  845. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  846. return usb_ep_set_halt(_ep);
  847. }
  848. /* flush contents of a fifo */
  849. static void langwell_ep_fifo_flush(struct usb_ep *_ep)
  850. {
  851. struct langwell_ep *ep;
  852. struct langwell_udc *dev;
  853. u32 flush_bit;
  854. unsigned long timeout;
  855. ep = container_of(_ep, struct langwell_ep, ep);
  856. dev = ep->dev;
  857. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  858. if (!_ep || !ep->desc) {
  859. dev_vdbg(&dev->pdev->dev, "ep or ep->desc is NULL\n");
  860. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  861. return;
  862. }
  863. dev_vdbg(&dev->pdev->dev, "%s-%s fifo flush\n",
  864. _ep->name, DIR_STRING(ep));
  865. /* flush endpoint buffer */
  866. if (ep->ep_num == 0)
  867. flush_bit = (1 << 16) | 1;
  868. else if (is_in(ep))
  869. flush_bit = 1 << (ep->ep_num + 16); /* TX */
  870. else
  871. flush_bit = 1 << ep->ep_num; /* RX */
  872. /* wait until flush complete */
  873. timeout = jiffies + FLUSH_TIMEOUT;
  874. do {
  875. writel(flush_bit, &dev->op_regs->endptflush);
  876. while (readl(&dev->op_regs->endptflush)) {
  877. if (time_after(jiffies, timeout)) {
  878. dev_err(&dev->pdev->dev, "ep flush timeout\n");
  879. goto done;
  880. }
  881. cpu_relax();
  882. }
  883. } while (readl(&dev->op_regs->endptstat) & flush_bit);
  884. done:
  885. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  886. }
  887. /* endpoints operations structure */
  888. static const struct usb_ep_ops langwell_ep_ops = {
  889. /* configure endpoint, making it usable */
  890. .enable = langwell_ep_enable,
  891. /* endpoint is no longer usable */
  892. .disable = langwell_ep_disable,
  893. /* allocate a request object to use with this endpoint */
  894. .alloc_request = langwell_alloc_request,
  895. /* free a request object */
  896. .free_request = langwell_free_request,
  897. /* queue (submits) an I/O requests to an endpoint */
  898. .queue = langwell_ep_queue,
  899. /* dequeue (cancels, unlinks) an I/O request from an endpoint */
  900. .dequeue = langwell_ep_dequeue,
  901. /* set the endpoint halt feature */
  902. .set_halt = langwell_ep_set_halt,
  903. /* set the halt feature and ignores clear requests */
  904. .set_wedge = langwell_ep_set_wedge,
  905. /* flush contents of a fifo */
  906. .fifo_flush = langwell_ep_fifo_flush,
  907. };
  908. /*-------------------------------------------------------------------------*/
  909. /* device controller usb_gadget_ops structure */
  910. /* returns the current frame number */
  911. static int langwell_get_frame(struct usb_gadget *_gadget)
  912. {
  913. struct langwell_udc *dev;
  914. u16 retval;
  915. if (!_gadget)
  916. return -ENODEV;
  917. dev = container_of(_gadget, struct langwell_udc, gadget);
  918. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  919. retval = readl(&dev->op_regs->frindex) & FRINDEX_MASK;
  920. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  921. return retval;
  922. }
  923. /* enter or exit PHY low power state */
  924. static void langwell_phy_low_power(struct langwell_udc *dev, bool flag)
  925. {
  926. u32 devlc;
  927. u8 devlc_byte2;
  928. dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
  929. devlc = readl(&dev->op_regs->devlc);
  930. dev_vdbg(&dev->pdev->dev, "devlc = 0x%08x\n", devlc);
  931. if (flag)
  932. devlc |= LPM_PHCD;
  933. else
  934. devlc &= ~LPM_PHCD;
  935. /* FIXME: workaround for Langwell A1/A2/A3 sighting */
  936. devlc_byte2 = (devlc >> 16) & 0xff;
  937. writeb(devlc_byte2, (u8 *)&dev->op_regs->devlc + 2);
  938. devlc = readl(&dev->op_regs->devlc);
  939. dev_vdbg(&dev->pdev->dev,
  940. "%s PHY low power suspend, devlc = 0x%08x\n",
  941. flag ? "enter" : "exit", devlc);
  942. }
  943. /* tries to wake up the host connected to this gadget */
  944. static int langwell_wakeup(struct usb_gadget *_gadget)
  945. {
  946. struct langwell_udc *dev;
  947. u32 portsc1;
  948. unsigned long flags;
  949. if (!_gadget)
  950. return 0;
  951. dev = container_of(_gadget, struct langwell_udc, gadget);
  952. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  953. /* remote wakeup feature not enabled by host */
  954. if (!dev->remote_wakeup) {
  955. dev_info(&dev->pdev->dev, "remote wakeup is disabled\n");
  956. return -ENOTSUPP;
  957. }
  958. spin_lock_irqsave(&dev->lock, flags);
  959. portsc1 = readl(&dev->op_regs->portsc1);
  960. if (!(portsc1 & PORTS_SUSP)) {
  961. spin_unlock_irqrestore(&dev->lock, flags);
  962. return 0;
  963. }
  964. /* LPM L1 to L0 or legacy remote wakeup */
  965. if (dev->lpm && dev->lpm_state == LPM_L1)
  966. dev_info(&dev->pdev->dev, "LPM L1 to L0 remote wakeup\n");
  967. else
  968. dev_info(&dev->pdev->dev, "device remote wakeup\n");
  969. /* exit PHY low power suspend */
  970. if (dev->pdev->device != 0x0829)
  971. langwell_phy_low_power(dev, 0);
  972. /* force port resume */
  973. portsc1 |= PORTS_FPR;
  974. writel(portsc1, &dev->op_regs->portsc1);
  975. spin_unlock_irqrestore(&dev->lock, flags);
  976. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  977. return 0;
  978. }
  979. /* notify controller that VBUS is powered or not */
  980. static int langwell_vbus_session(struct usb_gadget *_gadget, int is_active)
  981. {
  982. struct langwell_udc *dev;
  983. unsigned long flags;
  984. u32 usbcmd;
  985. if (!_gadget)
  986. return -ENODEV;
  987. dev = container_of(_gadget, struct langwell_udc, gadget);
  988. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  989. spin_lock_irqsave(&dev->lock, flags);
  990. dev_vdbg(&dev->pdev->dev, "VBUS status: %s\n",
  991. is_active ? "on" : "off");
  992. dev->vbus_active = (is_active != 0);
  993. if (dev->driver && dev->softconnected && dev->vbus_active) {
  994. usbcmd = readl(&dev->op_regs->usbcmd);
  995. usbcmd |= CMD_RUNSTOP;
  996. writel(usbcmd, &dev->op_regs->usbcmd);
  997. } else {
  998. usbcmd = readl(&dev->op_regs->usbcmd);
  999. usbcmd &= ~CMD_RUNSTOP;
  1000. writel(usbcmd, &dev->op_regs->usbcmd);
  1001. }
  1002. spin_unlock_irqrestore(&dev->lock, flags);
  1003. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1004. return 0;
  1005. }
  1006. /* constrain controller's VBUS power usage */
  1007. static int langwell_vbus_draw(struct usb_gadget *_gadget, unsigned mA)
  1008. {
  1009. struct langwell_udc *dev;
  1010. if (!_gadget)
  1011. return -ENODEV;
  1012. dev = container_of(_gadget, struct langwell_udc, gadget);
  1013. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  1014. if (dev->transceiver) {
  1015. dev_vdbg(&dev->pdev->dev, "otg_set_power\n");
  1016. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1017. return otg_set_power(dev->transceiver, mA);
  1018. }
  1019. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1020. return -ENOTSUPP;
  1021. }
  1022. /* D+ pullup, software-controlled connect/disconnect to USB host */
  1023. static int langwell_pullup(struct usb_gadget *_gadget, int is_on)
  1024. {
  1025. struct langwell_udc *dev;
  1026. u32 usbcmd;
  1027. unsigned long flags;
  1028. if (!_gadget)
  1029. return -ENODEV;
  1030. dev = container_of(_gadget, struct langwell_udc, gadget);
  1031. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  1032. spin_lock_irqsave(&dev->lock, flags);
  1033. dev->softconnected = (is_on != 0);
  1034. if (dev->driver && dev->softconnected && dev->vbus_active) {
  1035. usbcmd = readl(&dev->op_regs->usbcmd);
  1036. usbcmd |= CMD_RUNSTOP;
  1037. writel(usbcmd, &dev->op_regs->usbcmd);
  1038. } else {
  1039. usbcmd = readl(&dev->op_regs->usbcmd);
  1040. usbcmd &= ~CMD_RUNSTOP;
  1041. writel(usbcmd, &dev->op_regs->usbcmd);
  1042. }
  1043. spin_unlock_irqrestore(&dev->lock, flags);
  1044. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1045. return 0;
  1046. }
  1047. static int langwell_start(struct usb_gadget_driver *driver,
  1048. int (*bind)(struct usb_gadget *));
  1049. static int langwell_stop(struct usb_gadget_driver *driver);
  1050. /* device controller usb_gadget_ops structure */
  1051. static const struct usb_gadget_ops langwell_ops = {
  1052. /* returns the current frame number */
  1053. .get_frame = langwell_get_frame,
  1054. /* tries to wake up the host connected to this gadget */
  1055. .wakeup = langwell_wakeup,
  1056. /* set the device selfpowered feature, always selfpowered */
  1057. /* .set_selfpowered = langwell_set_selfpowered, */
  1058. /* notify controller that VBUS is powered or not */
  1059. .vbus_session = langwell_vbus_session,
  1060. /* constrain controller's VBUS power usage */
  1061. .vbus_draw = langwell_vbus_draw,
  1062. /* D+ pullup, software-controlled connect/disconnect to USB host */
  1063. .pullup = langwell_pullup,
  1064. .start = langwell_start,
  1065. .stop = langwell_stop,
  1066. };
  1067. /*-------------------------------------------------------------------------*/
  1068. /* device controller operations */
  1069. /* reset device controller */
  1070. static int langwell_udc_reset(struct langwell_udc *dev)
  1071. {
  1072. u32 usbcmd, usbmode, devlc, endpointlistaddr;
  1073. u8 devlc_byte0, devlc_byte2;
  1074. unsigned long timeout;
  1075. if (!dev)
  1076. return -EINVAL;
  1077. dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
  1078. /* set controller to stop state */
  1079. usbcmd = readl(&dev->op_regs->usbcmd);
  1080. usbcmd &= ~CMD_RUNSTOP;
  1081. writel(usbcmd, &dev->op_regs->usbcmd);
  1082. /* reset device controller */
  1083. usbcmd = readl(&dev->op_regs->usbcmd);
  1084. usbcmd |= CMD_RST;
  1085. writel(usbcmd, &dev->op_regs->usbcmd);
  1086. /* wait for reset to complete */
  1087. timeout = jiffies + RESET_TIMEOUT;
  1088. while (readl(&dev->op_regs->usbcmd) & CMD_RST) {
  1089. if (time_after(jiffies, timeout)) {
  1090. dev_err(&dev->pdev->dev, "device reset timeout\n");
  1091. return -ETIMEDOUT;
  1092. }
  1093. cpu_relax();
  1094. }
  1095. /* set controller to device mode */
  1096. usbmode = readl(&dev->op_regs->usbmode);
  1097. usbmode |= MODE_DEVICE;
  1098. /* turn setup lockout off, require setup tripwire in usbcmd */
  1099. usbmode |= MODE_SLOM;
  1100. writel(usbmode, &dev->op_regs->usbmode);
  1101. usbmode = readl(&dev->op_regs->usbmode);
  1102. dev_vdbg(&dev->pdev->dev, "usbmode=0x%08x\n", usbmode);
  1103. /* Write-Clear setup status */
  1104. writel(0, &dev->op_regs->usbsts);
  1105. /* if support USB LPM, ACK all LPM token */
  1106. if (dev->lpm) {
  1107. devlc = readl(&dev->op_regs->devlc);
  1108. dev_vdbg(&dev->pdev->dev, "devlc = 0x%08x\n", devlc);
  1109. /* FIXME: workaround for Langwell A1/A2/A3 sighting */
  1110. devlc &= ~LPM_STL; /* don't STALL LPM token */
  1111. devlc &= ~LPM_NYT_ACK; /* ACK LPM token */
  1112. devlc_byte0 = devlc & 0xff;
  1113. devlc_byte2 = (devlc >> 16) & 0xff;
  1114. writeb(devlc_byte0, (u8 *)&dev->op_regs->devlc);
  1115. writeb(devlc_byte2, (u8 *)&dev->op_regs->devlc + 2);
  1116. devlc = readl(&dev->op_regs->devlc);
  1117. dev_vdbg(&dev->pdev->dev,
  1118. "ACK LPM token, devlc = 0x%08x\n", devlc);
  1119. }
  1120. /* fill endpointlistaddr register */
  1121. endpointlistaddr = dev->ep_dqh_dma;
  1122. endpointlistaddr &= ENDPOINTLISTADDR_MASK;
  1123. writel(endpointlistaddr, &dev->op_regs->endpointlistaddr);
  1124. dev_vdbg(&dev->pdev->dev,
  1125. "dQH base (vir: %p, phy: 0x%08x), endpointlistaddr=0x%08x\n",
  1126. dev->ep_dqh, endpointlistaddr,
  1127. readl(&dev->op_regs->endpointlistaddr));
  1128. dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1129. return 0;
  1130. }
  1131. /* reinitialize device controller endpoints */
  1132. static int eps_reinit(struct langwell_udc *dev)
  1133. {
  1134. struct langwell_ep *ep;
  1135. char name[14];
  1136. int i;
  1137. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  1138. /* initialize ep0 */
  1139. ep = &dev->ep[0];
  1140. ep->dev = dev;
  1141. strncpy(ep->name, "ep0", sizeof(ep->name));
  1142. ep->ep.name = ep->name;
  1143. ep->ep.ops = &langwell_ep_ops;
  1144. ep->stopped = 0;
  1145. ep->ep.maxpacket = EP0_MAX_PKT_SIZE;
  1146. ep->ep_num = 0;
  1147. ep->desc = &langwell_ep0_desc;
  1148. INIT_LIST_HEAD(&ep->queue);
  1149. ep->ep_type = USB_ENDPOINT_XFER_CONTROL;
  1150. /* initialize other endpoints */
  1151. for (i = 2; i < dev->ep_max; i++) {
  1152. ep = &dev->ep[i];
  1153. if (i % 2)
  1154. snprintf(name, sizeof(name), "ep%din", i / 2);
  1155. else
  1156. snprintf(name, sizeof(name), "ep%dout", i / 2);
  1157. ep->dev = dev;
  1158. strncpy(ep->name, name, sizeof(ep->name));
  1159. ep->ep.name = ep->name;
  1160. ep->ep.ops = &langwell_ep_ops;
  1161. ep->stopped = 0;
  1162. ep->ep.maxpacket = (unsigned short) ~0;
  1163. ep->ep_num = i / 2;
  1164. INIT_LIST_HEAD(&ep->queue);
  1165. list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
  1166. }
  1167. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1168. return 0;
  1169. }
  1170. /* enable interrupt and set controller to run state */
  1171. static void langwell_udc_start(struct langwell_udc *dev)
  1172. {
  1173. u32 usbintr, usbcmd;
  1174. dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
  1175. /* enable interrupts */
  1176. usbintr = INTR_ULPIE /* ULPI */
  1177. | INTR_SLE /* suspend */
  1178. /* | INTR_SRE SOF received */
  1179. | INTR_URE /* USB reset */
  1180. | INTR_AAE /* async advance */
  1181. | INTR_SEE /* system error */
  1182. | INTR_FRE /* frame list rollover */
  1183. | INTR_PCE /* port change detect */
  1184. | INTR_UEE /* USB error interrupt */
  1185. | INTR_UE; /* USB interrupt */
  1186. writel(usbintr, &dev->op_regs->usbintr);
  1187. /* clear stopped bit */
  1188. dev->stopped = 0;
  1189. /* set controller to run */
  1190. usbcmd = readl(&dev->op_regs->usbcmd);
  1191. usbcmd |= CMD_RUNSTOP;
  1192. writel(usbcmd, &dev->op_regs->usbcmd);
  1193. dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1194. }
  1195. /* disable interrupt and set controller to stop state */
  1196. static void langwell_udc_stop(struct langwell_udc *dev)
  1197. {
  1198. u32 usbcmd;
  1199. dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
  1200. /* disable all interrupts */
  1201. writel(0, &dev->op_regs->usbintr);
  1202. /* set stopped bit */
  1203. dev->stopped = 1;
  1204. /* set controller to stop state */
  1205. usbcmd = readl(&dev->op_regs->usbcmd);
  1206. usbcmd &= ~CMD_RUNSTOP;
  1207. writel(usbcmd, &dev->op_regs->usbcmd);
  1208. dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1209. }
  1210. /* stop all USB activities */
  1211. static void stop_activity(struct langwell_udc *dev,
  1212. struct usb_gadget_driver *driver)
  1213. {
  1214. struct langwell_ep *ep;
  1215. dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
  1216. nuke(&dev->ep[0], -ESHUTDOWN);
  1217. list_for_each_entry(ep, &dev->gadget.ep_list, ep.ep_list) {
  1218. nuke(ep, -ESHUTDOWN);
  1219. }
  1220. /* report disconnect; the driver is already quiesced */
  1221. if (driver) {
  1222. spin_unlock(&dev->lock);
  1223. driver->disconnect(&dev->gadget);
  1224. spin_lock(&dev->lock);
  1225. }
  1226. dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1227. }
  1228. /*-------------------------------------------------------------------------*/
  1229. /* device "function" sysfs attribute file */
  1230. static ssize_t show_function(struct device *_dev,
  1231. struct device_attribute *attr, char *buf)
  1232. {
  1233. struct langwell_udc *dev = the_controller;
  1234. if (!dev->driver || !dev->driver->function
  1235. || strlen(dev->driver->function) > PAGE_SIZE)
  1236. return 0;
  1237. return scnprintf(buf, PAGE_SIZE, "%s\n", dev->driver->function);
  1238. }
  1239. static DEVICE_ATTR(function, S_IRUGO, show_function, NULL);
  1240. /* device "langwell_udc" sysfs attribute file */
  1241. static ssize_t show_langwell_udc(struct device *_dev,
  1242. struct device_attribute *attr, char *buf)
  1243. {
  1244. struct langwell_udc *dev = the_controller;
  1245. struct langwell_request *req;
  1246. struct langwell_ep *ep = NULL;
  1247. char *next;
  1248. unsigned size;
  1249. unsigned t;
  1250. unsigned i;
  1251. unsigned long flags;
  1252. u32 tmp_reg;
  1253. next = buf;
  1254. size = PAGE_SIZE;
  1255. spin_lock_irqsave(&dev->lock, flags);
  1256. /* driver basic information */
  1257. t = scnprintf(next, size,
  1258. DRIVER_DESC "\n"
  1259. "%s version: %s\n"
  1260. "Gadget driver: %s\n\n",
  1261. driver_name, DRIVER_VERSION,
  1262. dev->driver ? dev->driver->driver.name : "(none)");
  1263. size -= t;
  1264. next += t;
  1265. /* device registers */
  1266. tmp_reg = readl(&dev->op_regs->usbcmd);
  1267. t = scnprintf(next, size,
  1268. "USBCMD reg:\n"
  1269. "SetupTW: %d\n"
  1270. "Run/Stop: %s\n\n",
  1271. (tmp_reg & CMD_SUTW) ? 1 : 0,
  1272. (tmp_reg & CMD_RUNSTOP) ? "Run" : "Stop");
  1273. size -= t;
  1274. next += t;
  1275. tmp_reg = readl(&dev->op_regs->usbsts);
  1276. t = scnprintf(next, size,
  1277. "USB Status Reg:\n"
  1278. "Device Suspend: %d\n"
  1279. "Reset Received: %d\n"
  1280. "System Error: %s\n"
  1281. "USB Error Interrupt: %s\n\n",
  1282. (tmp_reg & STS_SLI) ? 1 : 0,
  1283. (tmp_reg & STS_URI) ? 1 : 0,
  1284. (tmp_reg & STS_SEI) ? "Error" : "No error",
  1285. (tmp_reg & STS_UEI) ? "Error detected" : "No error");
  1286. size -= t;
  1287. next += t;
  1288. tmp_reg = readl(&dev->op_regs->usbintr);
  1289. t = scnprintf(next, size,
  1290. "USB Intrrupt Enable Reg:\n"
  1291. "Sleep Enable: %d\n"
  1292. "SOF Received Enable: %d\n"
  1293. "Reset Enable: %d\n"
  1294. "System Error Enable: %d\n"
  1295. "Port Change Dectected Enable: %d\n"
  1296. "USB Error Intr Enable: %d\n"
  1297. "USB Intr Enable: %d\n\n",
  1298. (tmp_reg & INTR_SLE) ? 1 : 0,
  1299. (tmp_reg & INTR_SRE) ? 1 : 0,
  1300. (tmp_reg & INTR_URE) ? 1 : 0,
  1301. (tmp_reg & INTR_SEE) ? 1 : 0,
  1302. (tmp_reg & INTR_PCE) ? 1 : 0,
  1303. (tmp_reg & INTR_UEE) ? 1 : 0,
  1304. (tmp_reg & INTR_UE) ? 1 : 0);
  1305. size -= t;
  1306. next += t;
  1307. tmp_reg = readl(&dev->op_regs->frindex);
  1308. t = scnprintf(next, size,
  1309. "USB Frame Index Reg:\n"
  1310. "Frame Number is 0x%08x\n\n",
  1311. (tmp_reg & FRINDEX_MASK));
  1312. size -= t;
  1313. next += t;
  1314. tmp_reg = readl(&dev->op_regs->deviceaddr);
  1315. t = scnprintf(next, size,
  1316. "USB Device Address Reg:\n"
  1317. "Device Addr is 0x%x\n\n",
  1318. USBADR(tmp_reg));
  1319. size -= t;
  1320. next += t;
  1321. tmp_reg = readl(&dev->op_regs->endpointlistaddr);
  1322. t = scnprintf(next, size,
  1323. "USB Endpoint List Address Reg:\n"
  1324. "Endpoint List Pointer is 0x%x\n\n",
  1325. EPBASE(tmp_reg));
  1326. size -= t;
  1327. next += t;
  1328. tmp_reg = readl(&dev->op_regs->portsc1);
  1329. t = scnprintf(next, size,
  1330. "USB Port Status & Control Reg:\n"
  1331. "Port Reset: %s\n"
  1332. "Port Suspend Mode: %s\n"
  1333. "Over-current Change: %s\n"
  1334. "Port Enable/Disable Change: %s\n"
  1335. "Port Enabled/Disabled: %s\n"
  1336. "Current Connect Status: %s\n"
  1337. "LPM Suspend Status: %s\n\n",
  1338. (tmp_reg & PORTS_PR) ? "Reset" : "Not Reset",
  1339. (tmp_reg & PORTS_SUSP) ? "Suspend " : "Not Suspend",
  1340. (tmp_reg & PORTS_OCC) ? "Detected" : "No",
  1341. (tmp_reg & PORTS_PEC) ? "Changed" : "Not Changed",
  1342. (tmp_reg & PORTS_PE) ? "Enable" : "Not Correct",
  1343. (tmp_reg & PORTS_CCS) ? "Attached" : "Not Attached",
  1344. (tmp_reg & PORTS_SLP) ? "LPM L1" : "LPM L0");
  1345. size -= t;
  1346. next += t;
  1347. tmp_reg = readl(&dev->op_regs->devlc);
  1348. t = scnprintf(next, size,
  1349. "Device LPM Control Reg:\n"
  1350. "Parallel Transceiver : %d\n"
  1351. "Serial Transceiver : %d\n"
  1352. "Port Speed: %s\n"
  1353. "Port Force Full Speed Connenct: %s\n"
  1354. "PHY Low Power Suspend Clock: %s\n"
  1355. "BmAttributes: %d\n\n",
  1356. LPM_PTS(tmp_reg),
  1357. (tmp_reg & LPM_STS) ? 1 : 0,
  1358. ({
  1359. char *s;
  1360. switch (LPM_PSPD(tmp_reg)) {
  1361. case LPM_SPEED_FULL:
  1362. s = "Full Speed"; break;
  1363. case LPM_SPEED_LOW:
  1364. s = "Low Speed"; break;
  1365. case LPM_SPEED_HIGH:
  1366. s = "High Speed"; break;
  1367. default:
  1368. s = "Unknown Speed"; break;
  1369. }
  1370. s;
  1371. }),
  1372. (tmp_reg & LPM_PFSC) ? "Force Full Speed" : "Not Force",
  1373. (tmp_reg & LPM_PHCD) ? "Disabled" : "Enabled",
  1374. LPM_BA(tmp_reg));
  1375. size -= t;
  1376. next += t;
  1377. tmp_reg = readl(&dev->op_regs->usbmode);
  1378. t = scnprintf(next, size,
  1379. "USB Mode Reg:\n"
  1380. "Controller Mode is : %s\n\n", ({
  1381. char *s;
  1382. switch (MODE_CM(tmp_reg)) {
  1383. case MODE_IDLE:
  1384. s = "Idle"; break;
  1385. case MODE_DEVICE:
  1386. s = "Device Controller"; break;
  1387. case MODE_HOST:
  1388. s = "Host Controller"; break;
  1389. default:
  1390. s = "None"; break;
  1391. }
  1392. s;
  1393. }));
  1394. size -= t;
  1395. next += t;
  1396. tmp_reg = readl(&dev->op_regs->endptsetupstat);
  1397. t = scnprintf(next, size,
  1398. "Endpoint Setup Status Reg:\n"
  1399. "SETUP on ep 0x%04x\n\n",
  1400. tmp_reg & SETUPSTAT_MASK);
  1401. size -= t;
  1402. next += t;
  1403. for (i = 0; i < dev->ep_max / 2; i++) {
  1404. tmp_reg = readl(&dev->op_regs->endptctrl[i]);
  1405. t = scnprintf(next, size, "EP Ctrl Reg [%d]: 0x%08x\n",
  1406. i, tmp_reg);
  1407. size -= t;
  1408. next += t;
  1409. }
  1410. tmp_reg = readl(&dev->op_regs->endptprime);
  1411. t = scnprintf(next, size, "EP Prime Reg: 0x%08x\n\n", tmp_reg);
  1412. size -= t;
  1413. next += t;
  1414. /* langwell_udc, langwell_ep, langwell_request structure information */
  1415. ep = &dev->ep[0];
  1416. t = scnprintf(next, size, "%s MaxPacketSize: 0x%x, ep_num: %d\n",
  1417. ep->ep.name, ep->ep.maxpacket, ep->ep_num);
  1418. size -= t;
  1419. next += t;
  1420. if (list_empty(&ep->queue)) {
  1421. t = scnprintf(next, size, "its req queue is empty\n\n");
  1422. size -= t;
  1423. next += t;
  1424. } else {
  1425. list_for_each_entry(req, &ep->queue, queue) {
  1426. t = scnprintf(next, size,
  1427. "req %p actual 0x%x length 0x%x buf %p\n",
  1428. &req->req, req->req.actual,
  1429. req->req.length, req->req.buf);
  1430. size -= t;
  1431. next += t;
  1432. }
  1433. }
  1434. /* other gadget->eplist ep */
  1435. list_for_each_entry(ep, &dev->gadget.ep_list, ep.ep_list) {
  1436. if (ep->desc) {
  1437. t = scnprintf(next, size,
  1438. "\n%s MaxPacketSize: 0x%x, "
  1439. "ep_num: %d\n",
  1440. ep->ep.name, ep->ep.maxpacket,
  1441. ep->ep_num);
  1442. size -= t;
  1443. next += t;
  1444. if (list_empty(&ep->queue)) {
  1445. t = scnprintf(next, size,
  1446. "its req queue is empty\n\n");
  1447. size -= t;
  1448. next += t;
  1449. } else {
  1450. list_for_each_entry(req, &ep->queue, queue) {
  1451. t = scnprintf(next, size,
  1452. "req %p actual 0x%x length "
  1453. "0x%x buf %p\n",
  1454. &req->req, req->req.actual,
  1455. req->req.length, req->req.buf);
  1456. size -= t;
  1457. next += t;
  1458. }
  1459. }
  1460. }
  1461. }
  1462. spin_unlock_irqrestore(&dev->lock, flags);
  1463. return PAGE_SIZE - size;
  1464. }
  1465. static DEVICE_ATTR(langwell_udc, S_IRUGO, show_langwell_udc, NULL);
  1466. /* device "remote_wakeup" sysfs attribute file */
  1467. static ssize_t store_remote_wakeup(struct device *_dev,
  1468. struct device_attribute *attr, const char *buf, size_t count)
  1469. {
  1470. struct langwell_udc *dev = the_controller;
  1471. unsigned long flags;
  1472. ssize_t rc = count;
  1473. if (count > 2)
  1474. return -EINVAL;
  1475. if (count > 0 && buf[count-1] == '\n')
  1476. ((char *) buf)[count-1] = 0;
  1477. if (buf[0] != '1')
  1478. return -EINVAL;
  1479. /* force remote wakeup enabled in case gadget driver doesn't support */
  1480. spin_lock_irqsave(&dev->lock, flags);
  1481. dev->remote_wakeup = 1;
  1482. dev->dev_status |= (1 << USB_DEVICE_REMOTE_WAKEUP);
  1483. spin_unlock_irqrestore(&dev->lock, flags);
  1484. langwell_wakeup(&dev->gadget);
  1485. return rc;
  1486. }
  1487. static DEVICE_ATTR(remote_wakeup, S_IWUSR, NULL, store_remote_wakeup);
  1488. /*-------------------------------------------------------------------------*/
  1489. /*
  1490. * when a driver is successfully registered, it will receive
  1491. * control requests including set_configuration(), which enables
  1492. * non-control requests. then usb traffic follows until a
  1493. * disconnect is reported. then a host may connect again, or
  1494. * the driver might get unbound.
  1495. */
  1496. static int langwell_start(struct usb_gadget_driver *driver,
  1497. int (*bind)(struct usb_gadget *))
  1498. {
  1499. struct langwell_udc *dev = the_controller;
  1500. unsigned long flags;
  1501. int retval;
  1502. if (!dev)
  1503. return -ENODEV;
  1504. dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
  1505. if (dev->driver)
  1506. return -EBUSY;
  1507. spin_lock_irqsave(&dev->lock, flags);
  1508. /* hook up the driver ... */
  1509. driver->driver.bus = NULL;
  1510. dev->driver = driver;
  1511. dev->gadget.dev.driver = &driver->driver;
  1512. spin_unlock_irqrestore(&dev->lock, flags);
  1513. retval = bind(&dev->gadget);
  1514. if (retval) {
  1515. dev_dbg(&dev->pdev->dev, "bind to driver %s --> %d\n",
  1516. driver->driver.name, retval);
  1517. dev->driver = NULL;
  1518. dev->gadget.dev.driver = NULL;
  1519. return retval;
  1520. }
  1521. retval = device_create_file(&dev->pdev->dev, &dev_attr_function);
  1522. if (retval)
  1523. goto err_unbind;
  1524. dev->usb_state = USB_STATE_ATTACHED;
  1525. dev->ep0_state = WAIT_FOR_SETUP;
  1526. dev->ep0_dir = USB_DIR_OUT;
  1527. /* enable interrupt and set controller to run state */
  1528. if (dev->got_irq)
  1529. langwell_udc_start(dev);
  1530. dev_vdbg(&dev->pdev->dev,
  1531. "After langwell_udc_start(), print all registers:\n");
  1532. print_all_registers(dev);
  1533. dev_info(&dev->pdev->dev, "register driver: %s\n",
  1534. driver->driver.name);
  1535. dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1536. return 0;
  1537. err_unbind:
  1538. driver->unbind(&dev->gadget);
  1539. dev->gadget.dev.driver = NULL;
  1540. dev->driver = NULL;
  1541. dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1542. return retval;
  1543. }
  1544. /* unregister gadget driver */
  1545. static int langwell_stop(struct usb_gadget_driver *driver)
  1546. {
  1547. struct langwell_udc *dev = the_controller;
  1548. unsigned long flags;
  1549. if (!dev)
  1550. return -ENODEV;
  1551. dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
  1552. if (unlikely(!driver || !driver->unbind))
  1553. return -EINVAL;
  1554. /* exit PHY low power suspend */
  1555. if (dev->pdev->device != 0x0829)
  1556. langwell_phy_low_power(dev, 0);
  1557. /* unbind OTG transceiver */
  1558. if (dev->transceiver)
  1559. (void)otg_set_peripheral(dev->transceiver, 0);
  1560. /* disable interrupt and set controller to stop state */
  1561. langwell_udc_stop(dev);
  1562. dev->usb_state = USB_STATE_ATTACHED;
  1563. dev->ep0_state = WAIT_FOR_SETUP;
  1564. dev->ep0_dir = USB_DIR_OUT;
  1565. spin_lock_irqsave(&dev->lock, flags);
  1566. /* stop all usb activities */
  1567. dev->gadget.speed = USB_SPEED_UNKNOWN;
  1568. stop_activity(dev, driver);
  1569. spin_unlock_irqrestore(&dev->lock, flags);
  1570. /* unbind gadget driver */
  1571. driver->unbind(&dev->gadget);
  1572. dev->gadget.dev.driver = NULL;
  1573. dev->driver = NULL;
  1574. device_remove_file(&dev->pdev->dev, &dev_attr_function);
  1575. dev_info(&dev->pdev->dev, "unregistered driver '%s'\n",
  1576. driver->driver.name);
  1577. dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1578. return 0;
  1579. }
  1580. /*-------------------------------------------------------------------------*/
  1581. /*
  1582. * setup tripwire is used as a semaphore to ensure that the setup data
  1583. * payload is extracted from a dQH without being corrupted
  1584. */
  1585. static void setup_tripwire(struct langwell_udc *dev)
  1586. {
  1587. u32 usbcmd,
  1588. endptsetupstat;
  1589. unsigned long timeout;
  1590. struct langwell_dqh *dqh;
  1591. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  1592. /* ep0 OUT dQH */
  1593. dqh = &dev->ep_dqh[EP_DIR_OUT];
  1594. /* Write-Clear endptsetupstat */
  1595. endptsetupstat = readl(&dev->op_regs->endptsetupstat);
  1596. writel(endptsetupstat, &dev->op_regs->endptsetupstat);
  1597. /* wait until endptsetupstat is cleared */
  1598. timeout = jiffies + SETUPSTAT_TIMEOUT;
  1599. while (readl(&dev->op_regs->endptsetupstat)) {
  1600. if (time_after(jiffies, timeout)) {
  1601. dev_err(&dev->pdev->dev, "setup_tripwire timeout\n");
  1602. break;
  1603. }
  1604. cpu_relax();
  1605. }
  1606. /* while a hazard exists when setup packet arrives */
  1607. do {
  1608. /* set setup tripwire bit */
  1609. usbcmd = readl(&dev->op_regs->usbcmd);
  1610. writel(usbcmd | CMD_SUTW, &dev->op_regs->usbcmd);
  1611. /* copy the setup packet to local buffer */
  1612. memcpy(&dev->local_setup_buff, &dqh->dqh_setup, 8);
  1613. } while (!(readl(&dev->op_regs->usbcmd) & CMD_SUTW));
  1614. /* Write-Clear setup tripwire bit */
  1615. usbcmd = readl(&dev->op_regs->usbcmd);
  1616. writel(usbcmd & ~CMD_SUTW, &dev->op_regs->usbcmd);
  1617. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1618. }
  1619. /* protocol ep0 stall, will automatically be cleared on new transaction */
  1620. static void ep0_stall(struct langwell_udc *dev)
  1621. {
  1622. u32 endptctrl;
  1623. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  1624. /* set TX and RX to stall */
  1625. endptctrl = readl(&dev->op_regs->endptctrl[0]);
  1626. endptctrl |= EPCTRL_TXS | EPCTRL_RXS;
  1627. writel(endptctrl, &dev->op_regs->endptctrl[0]);
  1628. /* update ep0 state */
  1629. dev->ep0_state = WAIT_FOR_SETUP;
  1630. dev->ep0_dir = USB_DIR_OUT;
  1631. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1632. }
  1633. /* PRIME a status phase for ep0 */
  1634. static int prime_status_phase(struct langwell_udc *dev, int dir)
  1635. {
  1636. struct langwell_request *req;
  1637. struct langwell_ep *ep;
  1638. int status = 0;
  1639. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  1640. if (dir == EP_DIR_IN)
  1641. dev->ep0_dir = USB_DIR_IN;
  1642. else
  1643. dev->ep0_dir = USB_DIR_OUT;
  1644. ep = &dev->ep[0];
  1645. dev->ep0_state = WAIT_FOR_OUT_STATUS;
  1646. req = dev->status_req;
  1647. req->ep = ep;
  1648. req->req.length = 0;
  1649. req->req.status = -EINPROGRESS;
  1650. req->req.actual = 0;
  1651. req->req.complete = NULL;
  1652. req->dtd_count = 0;
  1653. if (!req_to_dtd(req))
  1654. status = queue_dtd(ep, req);
  1655. else
  1656. return -ENOMEM;
  1657. if (status)
  1658. dev_err(&dev->pdev->dev, "can't queue ep0 status request\n");
  1659. list_add_tail(&req->queue, &ep->queue);
  1660. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1661. return status;
  1662. }
  1663. /* SET_ADDRESS request routine */
  1664. static void set_address(struct langwell_udc *dev, u16 value,
  1665. u16 index, u16 length)
  1666. {
  1667. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  1668. /* save the new address to device struct */
  1669. dev->dev_addr = (u8) value;
  1670. dev_vdbg(&dev->pdev->dev, "dev->dev_addr = %d\n", dev->dev_addr);
  1671. /* update usb state */
  1672. dev->usb_state = USB_STATE_ADDRESS;
  1673. /* STATUS phase */
  1674. if (prime_status_phase(dev, EP_DIR_IN))
  1675. ep0_stall(dev);
  1676. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1677. }
  1678. /* return endpoint by windex */
  1679. static struct langwell_ep *get_ep_by_windex(struct langwell_udc *dev,
  1680. u16 wIndex)
  1681. {
  1682. struct langwell_ep *ep;
  1683. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  1684. if ((wIndex & USB_ENDPOINT_NUMBER_MASK) == 0)
  1685. return &dev->ep[0];
  1686. list_for_each_entry(ep, &dev->gadget.ep_list, ep.ep_list) {
  1687. u8 bEndpointAddress;
  1688. if (!ep->desc)
  1689. continue;
  1690. bEndpointAddress = ep->desc->bEndpointAddress;
  1691. if ((wIndex ^ bEndpointAddress) & USB_DIR_IN)
  1692. continue;
  1693. if ((wIndex & USB_ENDPOINT_NUMBER_MASK)
  1694. == (bEndpointAddress & USB_ENDPOINT_NUMBER_MASK))
  1695. return ep;
  1696. }
  1697. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1698. return NULL;
  1699. }
  1700. /* return whether endpoint is stalled, 0: not stalled; 1: stalled */
  1701. static int ep_is_stall(struct langwell_ep *ep)
  1702. {
  1703. struct langwell_udc *dev = ep->dev;
  1704. u32 endptctrl;
  1705. int retval;
  1706. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  1707. endptctrl = readl(&dev->op_regs->endptctrl[ep->ep_num]);
  1708. if (is_in(ep))
  1709. retval = endptctrl & EPCTRL_TXS ? 1 : 0;
  1710. else
  1711. retval = endptctrl & EPCTRL_RXS ? 1 : 0;
  1712. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1713. return retval;
  1714. }
  1715. /* GET_STATUS request routine */
  1716. static void get_status(struct langwell_udc *dev, u8 request_type, u16 value,
  1717. u16 index, u16 length)
  1718. {
  1719. struct langwell_request *req;
  1720. struct langwell_ep *ep;
  1721. u16 status_data = 0; /* 16 bits cpu view status data */
  1722. int status = 0;
  1723. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  1724. ep = &dev->ep[0];
  1725. if ((request_type & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
  1726. /* get device status */
  1727. status_data = dev->dev_status;
  1728. } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_INTERFACE) {
  1729. /* get interface status */
  1730. status_data = 0;
  1731. } else if ((request_type & USB_RECIP_MASK) == USB_RECIP_ENDPOINT) {
  1732. /* get endpoint status */
  1733. struct langwell_ep *epn;
  1734. epn = get_ep_by_windex(dev, index);
  1735. /* stall if endpoint doesn't exist */
  1736. if (!epn)
  1737. goto stall;
  1738. status_data = ep_is_stall(epn) << USB_ENDPOINT_HALT;
  1739. }
  1740. dev_dbg(&dev->pdev->dev, "get status data: 0x%04x\n", status_data);
  1741. dev->ep0_dir = USB_DIR_IN;
  1742. /* borrow the per device status_req */
  1743. req = dev->status_req;
  1744. /* fill in the reqest structure */
  1745. *((u16 *) req->req.buf) = cpu_to_le16(status_data);
  1746. req->ep = ep;
  1747. req->req.length = 2;
  1748. req->req.status = -EINPROGRESS;
  1749. req->req.actual = 0;
  1750. req->req.complete = NULL;
  1751. req->dtd_count = 0;
  1752. /* prime the data phase */
  1753. if (!req_to_dtd(req))
  1754. status = queue_dtd(ep, req);
  1755. else /* no mem */
  1756. goto stall;
  1757. if (status) {
  1758. dev_err(&dev->pdev->dev,
  1759. "response error on GET_STATUS request\n");
  1760. goto stall;
  1761. }
  1762. list_add_tail(&req->queue, &ep->queue);
  1763. dev->ep0_state = DATA_STATE_XMIT;
  1764. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1765. return;
  1766. stall:
  1767. ep0_stall(dev);
  1768. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1769. }
  1770. /* setup packet interrupt handler */
  1771. static void handle_setup_packet(struct langwell_udc *dev,
  1772. struct usb_ctrlrequest *setup)
  1773. {
  1774. u16 wValue = le16_to_cpu(setup->wValue);
  1775. u16 wIndex = le16_to_cpu(setup->wIndex);
  1776. u16 wLength = le16_to_cpu(setup->wLength);
  1777. u32 portsc1;
  1778. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  1779. /* ep0 fifo flush */
  1780. nuke(&dev->ep[0], -ESHUTDOWN);
  1781. dev_dbg(&dev->pdev->dev, "SETUP %02x.%02x v%04x i%04x l%04x\n",
  1782. setup->bRequestType, setup->bRequest,
  1783. wValue, wIndex, wLength);
  1784. /* RNDIS gadget delegate */
  1785. if ((setup->bRequestType == 0x21) && (setup->bRequest == 0x00)) {
  1786. /* USB_CDC_SEND_ENCAPSULATED_COMMAND */
  1787. goto delegate;
  1788. }
  1789. /* USB_CDC_GET_ENCAPSULATED_RESPONSE */
  1790. if ((setup->bRequestType == 0xa1) && (setup->bRequest == 0x01)) {
  1791. /* USB_CDC_GET_ENCAPSULATED_RESPONSE */
  1792. goto delegate;
  1793. }
  1794. /* We process some stardard setup requests here */
  1795. switch (setup->bRequest) {
  1796. case USB_REQ_GET_STATUS:
  1797. dev_dbg(&dev->pdev->dev, "SETUP: USB_REQ_GET_STATUS\n");
  1798. /* get status, DATA and STATUS phase */
  1799. if ((setup->bRequestType & (USB_DIR_IN | USB_TYPE_MASK))
  1800. != (USB_DIR_IN | USB_TYPE_STANDARD))
  1801. break;
  1802. get_status(dev, setup->bRequestType, wValue, wIndex, wLength);
  1803. goto end;
  1804. case USB_REQ_SET_ADDRESS:
  1805. dev_dbg(&dev->pdev->dev, "SETUP: USB_REQ_SET_ADDRESS\n");
  1806. /* STATUS phase */
  1807. if (setup->bRequestType != (USB_DIR_OUT | USB_TYPE_STANDARD
  1808. | USB_RECIP_DEVICE))
  1809. break;
  1810. set_address(dev, wValue, wIndex, wLength);
  1811. goto end;
  1812. case USB_REQ_CLEAR_FEATURE:
  1813. case USB_REQ_SET_FEATURE:
  1814. /* STATUS phase */
  1815. {
  1816. int rc = -EOPNOTSUPP;
  1817. if (setup->bRequest == USB_REQ_SET_FEATURE)
  1818. dev_dbg(&dev->pdev->dev,
  1819. "SETUP: USB_REQ_SET_FEATURE\n");
  1820. else if (setup->bRequest == USB_REQ_CLEAR_FEATURE)
  1821. dev_dbg(&dev->pdev->dev,
  1822. "SETUP: USB_REQ_CLEAR_FEATURE\n");
  1823. if ((setup->bRequestType & (USB_RECIP_MASK | USB_TYPE_MASK))
  1824. == (USB_RECIP_ENDPOINT | USB_TYPE_STANDARD)) {
  1825. struct langwell_ep *epn;
  1826. epn = get_ep_by_windex(dev, wIndex);
  1827. /* stall if endpoint doesn't exist */
  1828. if (!epn) {
  1829. ep0_stall(dev);
  1830. goto end;
  1831. }
  1832. if (wValue != 0 || wLength != 0
  1833. || epn->ep_num > dev->ep_max)
  1834. break;
  1835. spin_unlock(&dev->lock);
  1836. rc = langwell_ep_set_halt(&epn->ep,
  1837. (setup->bRequest == USB_REQ_SET_FEATURE)
  1838. ? 1 : 0);
  1839. spin_lock(&dev->lock);
  1840. } else if ((setup->bRequestType & (USB_RECIP_MASK
  1841. | USB_TYPE_MASK)) == (USB_RECIP_DEVICE
  1842. | USB_TYPE_STANDARD)) {
  1843. rc = 0;
  1844. switch (wValue) {
  1845. case USB_DEVICE_REMOTE_WAKEUP:
  1846. if (setup->bRequest == USB_REQ_SET_FEATURE) {
  1847. dev->remote_wakeup = 1;
  1848. dev->dev_status |= (1 << wValue);
  1849. } else {
  1850. dev->remote_wakeup = 0;
  1851. dev->dev_status &= ~(1 << wValue);
  1852. }
  1853. break;
  1854. case USB_DEVICE_TEST_MODE:
  1855. dev_dbg(&dev->pdev->dev, "SETUP: TEST MODE\n");
  1856. if ((wIndex & 0xff) ||
  1857. (dev->gadget.speed != USB_SPEED_HIGH))
  1858. ep0_stall(dev);
  1859. switch (wIndex >> 8) {
  1860. case TEST_J:
  1861. case TEST_K:
  1862. case TEST_SE0_NAK:
  1863. case TEST_PACKET:
  1864. case TEST_FORCE_EN:
  1865. if (prime_status_phase(dev, EP_DIR_IN))
  1866. ep0_stall(dev);
  1867. portsc1 = readl(&dev->op_regs->portsc1);
  1868. portsc1 |= (wIndex & 0xf00) << 8;
  1869. writel(portsc1, &dev->op_regs->portsc1);
  1870. goto end;
  1871. default:
  1872. rc = -EOPNOTSUPP;
  1873. }
  1874. break;
  1875. default:
  1876. rc = -EOPNOTSUPP;
  1877. break;
  1878. }
  1879. if (!gadget_is_otg(&dev->gadget))
  1880. break;
  1881. else if (setup->bRequest == USB_DEVICE_B_HNP_ENABLE) {
  1882. dev->gadget.b_hnp_enable = 1;
  1883. #ifdef OTG_TRANSCEIVER
  1884. if (!dev->lotg->otg.default_a)
  1885. dev->lotg->hsm.b_hnp_enable = 1;
  1886. #endif
  1887. } else if (setup->bRequest == USB_DEVICE_A_HNP_SUPPORT)
  1888. dev->gadget.a_hnp_support = 1;
  1889. else if (setup->bRequest ==
  1890. USB_DEVICE_A_ALT_HNP_SUPPORT)
  1891. dev->gadget.a_alt_hnp_support = 1;
  1892. else
  1893. break;
  1894. } else
  1895. break;
  1896. if (rc == 0) {
  1897. if (prime_status_phase(dev, EP_DIR_IN))
  1898. ep0_stall(dev);
  1899. }
  1900. goto end;
  1901. }
  1902. case USB_REQ_GET_DESCRIPTOR:
  1903. dev_dbg(&dev->pdev->dev,
  1904. "SETUP: USB_REQ_GET_DESCRIPTOR\n");
  1905. goto delegate;
  1906. case USB_REQ_SET_DESCRIPTOR:
  1907. dev_dbg(&dev->pdev->dev,
  1908. "SETUP: USB_REQ_SET_DESCRIPTOR unsupported\n");
  1909. goto delegate;
  1910. case USB_REQ_GET_CONFIGURATION:
  1911. dev_dbg(&dev->pdev->dev,
  1912. "SETUP: USB_REQ_GET_CONFIGURATION\n");
  1913. goto delegate;
  1914. case USB_REQ_SET_CONFIGURATION:
  1915. dev_dbg(&dev->pdev->dev,
  1916. "SETUP: USB_REQ_SET_CONFIGURATION\n");
  1917. goto delegate;
  1918. case USB_REQ_GET_INTERFACE:
  1919. dev_dbg(&dev->pdev->dev,
  1920. "SETUP: USB_REQ_GET_INTERFACE\n");
  1921. goto delegate;
  1922. case USB_REQ_SET_INTERFACE:
  1923. dev_dbg(&dev->pdev->dev,
  1924. "SETUP: USB_REQ_SET_INTERFACE\n");
  1925. goto delegate;
  1926. case USB_REQ_SYNCH_FRAME:
  1927. dev_dbg(&dev->pdev->dev,
  1928. "SETUP: USB_REQ_SYNCH_FRAME unsupported\n");
  1929. goto delegate;
  1930. default:
  1931. /* delegate USB standard requests to the gadget driver */
  1932. goto delegate;
  1933. delegate:
  1934. /* USB requests handled by gadget */
  1935. if (wLength) {
  1936. /* DATA phase from gadget, STATUS phase from udc */
  1937. dev->ep0_dir = (setup->bRequestType & USB_DIR_IN)
  1938. ? USB_DIR_IN : USB_DIR_OUT;
  1939. dev_vdbg(&dev->pdev->dev,
  1940. "dev->ep0_dir = 0x%x, wLength = %d\n",
  1941. dev->ep0_dir, wLength);
  1942. spin_unlock(&dev->lock);
  1943. if (dev->driver->setup(&dev->gadget,
  1944. &dev->local_setup_buff) < 0)
  1945. ep0_stall(dev);
  1946. spin_lock(&dev->lock);
  1947. dev->ep0_state = (setup->bRequestType & USB_DIR_IN)
  1948. ? DATA_STATE_XMIT : DATA_STATE_RECV;
  1949. } else {
  1950. /* no DATA phase, IN STATUS phase from gadget */
  1951. dev->ep0_dir = USB_DIR_IN;
  1952. dev_vdbg(&dev->pdev->dev,
  1953. "dev->ep0_dir = 0x%x, wLength = %d\n",
  1954. dev->ep0_dir, wLength);
  1955. spin_unlock(&dev->lock);
  1956. if (dev->driver->setup(&dev->gadget,
  1957. &dev->local_setup_buff) < 0)
  1958. ep0_stall(dev);
  1959. spin_lock(&dev->lock);
  1960. dev->ep0_state = WAIT_FOR_OUT_STATUS;
  1961. }
  1962. break;
  1963. }
  1964. end:
  1965. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  1966. }
  1967. /* transfer completion, process endpoint request and free the completed dTDs
  1968. * for this request
  1969. */
  1970. static int process_ep_req(struct langwell_udc *dev, int index,
  1971. struct langwell_request *curr_req)
  1972. {
  1973. struct langwell_dtd *curr_dtd;
  1974. struct langwell_dqh *curr_dqh;
  1975. int td_complete, actual, remaining_length;
  1976. int i, dir;
  1977. u8 dtd_status = 0;
  1978. int retval = 0;
  1979. curr_dqh = &dev->ep_dqh[index];
  1980. dir = index % 2;
  1981. curr_dtd = curr_req->head;
  1982. td_complete = 0;
  1983. actual = curr_req->req.length;
  1984. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  1985. for (i = 0; i < curr_req->dtd_count; i++) {
  1986. /* command execution states by dTD */
  1987. dtd_status = curr_dtd->dtd_status;
  1988. barrier();
  1989. remaining_length = le16_to_cpu(curr_dtd->dtd_total);
  1990. actual -= remaining_length;
  1991. if (!dtd_status) {
  1992. /* transfers completed successfully */
  1993. if (!remaining_length) {
  1994. td_complete++;
  1995. dev_vdbg(&dev->pdev->dev,
  1996. "dTD transmitted successfully\n");
  1997. } else {
  1998. if (dir) {
  1999. dev_vdbg(&dev->pdev->dev,
  2000. "TX dTD remains data\n");
  2001. retval = -EPROTO;
  2002. break;
  2003. } else {
  2004. td_complete++;
  2005. break;
  2006. }
  2007. }
  2008. } else {
  2009. /* transfers completed with errors */
  2010. if (dtd_status & DTD_STS_ACTIVE) {
  2011. dev_dbg(&dev->pdev->dev,
  2012. "dTD status ACTIVE dQH[%d]\n", index);
  2013. retval = 1;
  2014. return retval;
  2015. } else if (dtd_status & DTD_STS_HALTED) {
  2016. dev_err(&dev->pdev->dev,
  2017. "dTD error %08x dQH[%d]\n",
  2018. dtd_status, index);
  2019. /* clear the errors and halt condition */
  2020. curr_dqh->dtd_status = 0;
  2021. retval = -EPIPE;
  2022. break;
  2023. } else if (dtd_status & DTD_STS_DBE) {
  2024. dev_dbg(&dev->pdev->dev,
  2025. "data buffer (overflow) error\n");
  2026. retval = -EPROTO;
  2027. break;
  2028. } else if (dtd_status & DTD_STS_TRE) {
  2029. dev_dbg(&dev->pdev->dev,
  2030. "transaction(ISO) error\n");
  2031. retval = -EILSEQ;
  2032. break;
  2033. } else
  2034. dev_err(&dev->pdev->dev,
  2035. "unknown error (0x%x)!\n",
  2036. dtd_status);
  2037. }
  2038. if (i != curr_req->dtd_count - 1)
  2039. curr_dtd = (struct langwell_dtd *)
  2040. curr_dtd->next_dtd_virt;
  2041. }
  2042. if (retval)
  2043. return retval;
  2044. curr_req->req.actual = actual;
  2045. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2046. return 0;
  2047. }
  2048. /* complete DATA or STATUS phase of ep0 prime status phase if needed */
  2049. static void ep0_req_complete(struct langwell_udc *dev,
  2050. struct langwell_ep *ep0, struct langwell_request *req)
  2051. {
  2052. u32 new_addr;
  2053. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  2054. if (dev->usb_state == USB_STATE_ADDRESS) {
  2055. /* set the new address */
  2056. new_addr = (u32)dev->dev_addr;
  2057. writel(new_addr << USBADR_SHIFT, &dev->op_regs->deviceaddr);
  2058. new_addr = USBADR(readl(&dev->op_regs->deviceaddr));
  2059. dev_vdbg(&dev->pdev->dev, "new_addr = %d\n", new_addr);
  2060. }
  2061. done(ep0, req, 0);
  2062. switch (dev->ep0_state) {
  2063. case DATA_STATE_XMIT:
  2064. /* receive status phase */
  2065. if (prime_status_phase(dev, EP_DIR_OUT))
  2066. ep0_stall(dev);
  2067. break;
  2068. case DATA_STATE_RECV:
  2069. /* send status phase */
  2070. if (prime_status_phase(dev, EP_DIR_IN))
  2071. ep0_stall(dev);
  2072. break;
  2073. case WAIT_FOR_OUT_STATUS:
  2074. dev->ep0_state = WAIT_FOR_SETUP;
  2075. break;
  2076. case WAIT_FOR_SETUP:
  2077. dev_err(&dev->pdev->dev, "unexpect ep0 packets\n");
  2078. break;
  2079. default:
  2080. ep0_stall(dev);
  2081. break;
  2082. }
  2083. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2084. }
  2085. /* USB transfer completion interrupt */
  2086. static void handle_trans_complete(struct langwell_udc *dev)
  2087. {
  2088. u32 complete_bits;
  2089. int i, ep_num, dir, bit_mask, status;
  2090. struct langwell_ep *epn;
  2091. struct langwell_request *curr_req, *temp_req;
  2092. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  2093. complete_bits = readl(&dev->op_regs->endptcomplete);
  2094. dev_vdbg(&dev->pdev->dev, "endptcomplete register: 0x%08x\n",
  2095. complete_bits);
  2096. /* Write-Clear the bits in endptcomplete register */
  2097. writel(complete_bits, &dev->op_regs->endptcomplete);
  2098. if (!complete_bits) {
  2099. dev_dbg(&dev->pdev->dev, "complete_bits = 0\n");
  2100. goto done;
  2101. }
  2102. for (i = 0; i < dev->ep_max; i++) {
  2103. ep_num = i / 2;
  2104. dir = i % 2;
  2105. bit_mask = 1 << (ep_num + 16 * dir);
  2106. if (!(complete_bits & bit_mask))
  2107. continue;
  2108. /* ep0 */
  2109. if (i == 1)
  2110. epn = &dev->ep[0];
  2111. else
  2112. epn = &dev->ep[i];
  2113. if (epn->name == NULL) {
  2114. dev_warn(&dev->pdev->dev, "invalid endpoint\n");
  2115. continue;
  2116. }
  2117. if (i < 2)
  2118. /* ep0 in and out */
  2119. dev_dbg(&dev->pdev->dev, "%s-%s transfer completed\n",
  2120. epn->name,
  2121. is_in(epn) ? "in" : "out");
  2122. else
  2123. dev_dbg(&dev->pdev->dev, "%s transfer completed\n",
  2124. epn->name);
  2125. /* process the req queue until an uncomplete request */
  2126. list_for_each_entry_safe(curr_req, temp_req,
  2127. &epn->queue, queue) {
  2128. status = process_ep_req(dev, i, curr_req);
  2129. dev_vdbg(&dev->pdev->dev, "%s req status: %d\n",
  2130. epn->name, status);
  2131. if (status)
  2132. break;
  2133. /* write back status to req */
  2134. curr_req->req.status = status;
  2135. /* ep0 request completion */
  2136. if (ep_num == 0) {
  2137. ep0_req_complete(dev, epn, curr_req);
  2138. break;
  2139. } else {
  2140. done(epn, curr_req, status);
  2141. }
  2142. }
  2143. }
  2144. done:
  2145. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2146. }
  2147. /* port change detect interrupt handler */
  2148. static void handle_port_change(struct langwell_udc *dev)
  2149. {
  2150. u32 portsc1, devlc;
  2151. u32 speed;
  2152. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  2153. if (dev->bus_reset)
  2154. dev->bus_reset = 0;
  2155. portsc1 = readl(&dev->op_regs->portsc1);
  2156. devlc = readl(&dev->op_regs->devlc);
  2157. dev_vdbg(&dev->pdev->dev, "portsc1 = 0x%08x, devlc = 0x%08x\n",
  2158. portsc1, devlc);
  2159. /* bus reset is finished */
  2160. if (!(portsc1 & PORTS_PR)) {
  2161. /* get the speed */
  2162. speed = LPM_PSPD(devlc);
  2163. switch (speed) {
  2164. case LPM_SPEED_HIGH:
  2165. dev->gadget.speed = USB_SPEED_HIGH;
  2166. break;
  2167. case LPM_SPEED_FULL:
  2168. dev->gadget.speed = USB_SPEED_FULL;
  2169. break;
  2170. case LPM_SPEED_LOW:
  2171. dev->gadget.speed = USB_SPEED_LOW;
  2172. break;
  2173. default:
  2174. dev->gadget.speed = USB_SPEED_UNKNOWN;
  2175. break;
  2176. }
  2177. dev_vdbg(&dev->pdev->dev,
  2178. "speed = %d, dev->gadget.speed = %d\n",
  2179. speed, dev->gadget.speed);
  2180. }
  2181. /* LPM L0 to L1 */
  2182. if (dev->lpm && dev->lpm_state == LPM_L0)
  2183. if (portsc1 & PORTS_SUSP && portsc1 & PORTS_SLP) {
  2184. dev_info(&dev->pdev->dev, "LPM L0 to L1\n");
  2185. dev->lpm_state = LPM_L1;
  2186. }
  2187. /* LPM L1 to L0, force resume or remote wakeup finished */
  2188. if (dev->lpm && dev->lpm_state == LPM_L1)
  2189. if (!(portsc1 & PORTS_SUSP)) {
  2190. dev_info(&dev->pdev->dev, "LPM L1 to L0\n");
  2191. dev->lpm_state = LPM_L0;
  2192. }
  2193. /* update USB state */
  2194. if (!dev->resume_state)
  2195. dev->usb_state = USB_STATE_DEFAULT;
  2196. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2197. }
  2198. /* USB reset interrupt handler */
  2199. static void handle_usb_reset(struct langwell_udc *dev)
  2200. {
  2201. u32 deviceaddr,
  2202. endptsetupstat,
  2203. endptcomplete;
  2204. unsigned long timeout;
  2205. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  2206. /* Write-Clear the device address */
  2207. deviceaddr = readl(&dev->op_regs->deviceaddr);
  2208. writel(deviceaddr & ~USBADR_MASK, &dev->op_regs->deviceaddr);
  2209. dev->dev_addr = 0;
  2210. /* clear usb state */
  2211. dev->resume_state = 0;
  2212. /* LPM L1 to L0, reset */
  2213. if (dev->lpm)
  2214. dev->lpm_state = LPM_L0;
  2215. dev->ep0_dir = USB_DIR_OUT;
  2216. dev->ep0_state = WAIT_FOR_SETUP;
  2217. /* remote wakeup reset to 0 when the device is reset */
  2218. dev->remote_wakeup = 0;
  2219. dev->dev_status = 1 << USB_DEVICE_SELF_POWERED;
  2220. dev->gadget.b_hnp_enable = 0;
  2221. dev->gadget.a_hnp_support = 0;
  2222. dev->gadget.a_alt_hnp_support = 0;
  2223. /* Write-Clear all the setup token semaphores */
  2224. endptsetupstat = readl(&dev->op_regs->endptsetupstat);
  2225. writel(endptsetupstat, &dev->op_regs->endptsetupstat);
  2226. /* Write-Clear all the endpoint complete status bits */
  2227. endptcomplete = readl(&dev->op_regs->endptcomplete);
  2228. writel(endptcomplete, &dev->op_regs->endptcomplete);
  2229. /* wait until all endptprime bits cleared */
  2230. timeout = jiffies + PRIME_TIMEOUT;
  2231. while (readl(&dev->op_regs->endptprime)) {
  2232. if (time_after(jiffies, timeout)) {
  2233. dev_err(&dev->pdev->dev, "USB reset timeout\n");
  2234. break;
  2235. }
  2236. cpu_relax();
  2237. }
  2238. /* write 1s to endptflush register to clear any primed buffers */
  2239. writel((u32) ~0, &dev->op_regs->endptflush);
  2240. if (readl(&dev->op_regs->portsc1) & PORTS_PR) {
  2241. dev_vdbg(&dev->pdev->dev, "USB bus reset\n");
  2242. /* bus is reseting */
  2243. dev->bus_reset = 1;
  2244. /* reset all the queues, stop all USB activities */
  2245. stop_activity(dev, dev->driver);
  2246. dev->usb_state = USB_STATE_DEFAULT;
  2247. } else {
  2248. dev_vdbg(&dev->pdev->dev, "device controller reset\n");
  2249. /* controller reset */
  2250. langwell_udc_reset(dev);
  2251. /* reset all the queues, stop all USB activities */
  2252. stop_activity(dev, dev->driver);
  2253. /* reset ep0 dQH and endptctrl */
  2254. ep0_reset(dev);
  2255. /* enable interrupt and set controller to run state */
  2256. langwell_udc_start(dev);
  2257. dev->usb_state = USB_STATE_ATTACHED;
  2258. }
  2259. #ifdef OTG_TRANSCEIVER
  2260. /* refer to USB OTG 6.6.2.3 b_hnp_en is cleared */
  2261. if (!dev->lotg->otg.default_a)
  2262. dev->lotg->hsm.b_hnp_enable = 0;
  2263. #endif
  2264. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2265. }
  2266. /* USB bus suspend/resume interrupt */
  2267. static void handle_bus_suspend(struct langwell_udc *dev)
  2268. {
  2269. dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
  2270. dev->resume_state = dev->usb_state;
  2271. dev->usb_state = USB_STATE_SUSPENDED;
  2272. #ifdef OTG_TRANSCEIVER
  2273. if (dev->lotg->otg.default_a) {
  2274. if (dev->lotg->hsm.b_bus_suspend_vld == 1) {
  2275. dev->lotg->hsm.b_bus_suspend = 1;
  2276. /* notify transceiver the state changes */
  2277. if (spin_trylock(&dev->lotg->wq_lock)) {
  2278. langwell_update_transceiver();
  2279. spin_unlock(&dev->lotg->wq_lock);
  2280. }
  2281. }
  2282. dev->lotg->hsm.b_bus_suspend_vld++;
  2283. } else {
  2284. if (!dev->lotg->hsm.a_bus_suspend) {
  2285. dev->lotg->hsm.a_bus_suspend = 1;
  2286. /* notify transceiver the state changes */
  2287. if (spin_trylock(&dev->lotg->wq_lock)) {
  2288. langwell_update_transceiver();
  2289. spin_unlock(&dev->lotg->wq_lock);
  2290. }
  2291. }
  2292. }
  2293. #endif
  2294. /* report suspend to the driver */
  2295. if (dev->driver) {
  2296. if (dev->driver->suspend) {
  2297. spin_unlock(&dev->lock);
  2298. dev->driver->suspend(&dev->gadget);
  2299. spin_lock(&dev->lock);
  2300. dev_dbg(&dev->pdev->dev, "suspend %s\n",
  2301. dev->driver->driver.name);
  2302. }
  2303. }
  2304. /* enter PHY low power suspend */
  2305. if (dev->pdev->device != 0x0829)
  2306. langwell_phy_low_power(dev, 0);
  2307. dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2308. }
  2309. static void handle_bus_resume(struct langwell_udc *dev)
  2310. {
  2311. dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
  2312. dev->usb_state = dev->resume_state;
  2313. dev->resume_state = 0;
  2314. /* exit PHY low power suspend */
  2315. if (dev->pdev->device != 0x0829)
  2316. langwell_phy_low_power(dev, 0);
  2317. #ifdef OTG_TRANSCEIVER
  2318. if (dev->lotg->otg.default_a == 0)
  2319. dev->lotg->hsm.a_bus_suspend = 0;
  2320. #endif
  2321. /* report resume to the driver */
  2322. if (dev->driver) {
  2323. if (dev->driver->resume) {
  2324. spin_unlock(&dev->lock);
  2325. dev->driver->resume(&dev->gadget);
  2326. spin_lock(&dev->lock);
  2327. dev_dbg(&dev->pdev->dev, "resume %s\n",
  2328. dev->driver->driver.name);
  2329. }
  2330. }
  2331. dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2332. }
  2333. /* USB device controller interrupt handler */
  2334. static irqreturn_t langwell_irq(int irq, void *_dev)
  2335. {
  2336. struct langwell_udc *dev = _dev;
  2337. u32 usbsts,
  2338. usbintr,
  2339. irq_sts,
  2340. portsc1;
  2341. dev_vdbg(&dev->pdev->dev, "---> %s()\n", __func__);
  2342. if (dev->stopped) {
  2343. dev_vdbg(&dev->pdev->dev, "handle IRQ_NONE\n");
  2344. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2345. return IRQ_NONE;
  2346. }
  2347. spin_lock(&dev->lock);
  2348. /* USB status */
  2349. usbsts = readl(&dev->op_regs->usbsts);
  2350. /* USB interrupt enable */
  2351. usbintr = readl(&dev->op_regs->usbintr);
  2352. irq_sts = usbsts & usbintr;
  2353. dev_vdbg(&dev->pdev->dev,
  2354. "usbsts = 0x%08x, usbintr = 0x%08x, irq_sts = 0x%08x\n",
  2355. usbsts, usbintr, irq_sts);
  2356. if (!irq_sts) {
  2357. dev_vdbg(&dev->pdev->dev, "handle IRQ_NONE\n");
  2358. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2359. spin_unlock(&dev->lock);
  2360. return IRQ_NONE;
  2361. }
  2362. /* Write-Clear interrupt status bits */
  2363. writel(irq_sts, &dev->op_regs->usbsts);
  2364. /* resume from suspend */
  2365. portsc1 = readl(&dev->op_regs->portsc1);
  2366. if (dev->usb_state == USB_STATE_SUSPENDED)
  2367. if (!(portsc1 & PORTS_SUSP))
  2368. handle_bus_resume(dev);
  2369. /* USB interrupt */
  2370. if (irq_sts & STS_UI) {
  2371. dev_vdbg(&dev->pdev->dev, "USB interrupt\n");
  2372. /* setup packet received from ep0 */
  2373. if (readl(&dev->op_regs->endptsetupstat)
  2374. & EP0SETUPSTAT_MASK) {
  2375. dev_vdbg(&dev->pdev->dev,
  2376. "USB SETUP packet received interrupt\n");
  2377. /* setup tripwire semaphone */
  2378. setup_tripwire(dev);
  2379. handle_setup_packet(dev, &dev->local_setup_buff);
  2380. }
  2381. /* USB transfer completion */
  2382. if (readl(&dev->op_regs->endptcomplete)) {
  2383. dev_vdbg(&dev->pdev->dev,
  2384. "USB transfer completion interrupt\n");
  2385. handle_trans_complete(dev);
  2386. }
  2387. }
  2388. /* SOF received interrupt (for ISO transfer) */
  2389. if (irq_sts & STS_SRI) {
  2390. /* FIXME */
  2391. /* dev_vdbg(&dev->pdev->dev, "SOF received interrupt\n"); */
  2392. }
  2393. /* port change detect interrupt */
  2394. if (irq_sts & STS_PCI) {
  2395. dev_vdbg(&dev->pdev->dev, "port change detect interrupt\n");
  2396. handle_port_change(dev);
  2397. }
  2398. /* suspend interrrupt */
  2399. if (irq_sts & STS_SLI) {
  2400. dev_vdbg(&dev->pdev->dev, "suspend interrupt\n");
  2401. handle_bus_suspend(dev);
  2402. }
  2403. /* USB reset interrupt */
  2404. if (irq_sts & STS_URI) {
  2405. dev_vdbg(&dev->pdev->dev, "USB reset interrupt\n");
  2406. handle_usb_reset(dev);
  2407. }
  2408. /* USB error or system error interrupt */
  2409. if (irq_sts & (STS_UEI | STS_SEI)) {
  2410. /* FIXME */
  2411. dev_warn(&dev->pdev->dev, "error IRQ, irq_sts: %x\n", irq_sts);
  2412. }
  2413. spin_unlock(&dev->lock);
  2414. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2415. return IRQ_HANDLED;
  2416. }
  2417. /*-------------------------------------------------------------------------*/
  2418. /* release device structure */
  2419. static void gadget_release(struct device *_dev)
  2420. {
  2421. struct langwell_udc *dev = the_controller;
  2422. dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
  2423. complete(dev->done);
  2424. dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2425. kfree(dev);
  2426. }
  2427. /* enable SRAM caching if SRAM detected */
  2428. static void sram_init(struct langwell_udc *dev)
  2429. {
  2430. struct pci_dev *pdev = dev->pdev;
  2431. dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
  2432. dev->sram_addr = pci_resource_start(pdev, 1);
  2433. dev->sram_size = pci_resource_len(pdev, 1);
  2434. dev_info(&dev->pdev->dev, "Found private SRAM at %x size:%x\n",
  2435. dev->sram_addr, dev->sram_size);
  2436. dev->got_sram = 1;
  2437. if (pci_request_region(pdev, 1, kobject_name(&pdev->dev.kobj))) {
  2438. dev_warn(&dev->pdev->dev, "SRAM request failed\n");
  2439. dev->got_sram = 0;
  2440. } else if (!dma_declare_coherent_memory(&pdev->dev, dev->sram_addr,
  2441. dev->sram_addr, dev->sram_size, DMA_MEMORY_MAP)) {
  2442. dev_warn(&dev->pdev->dev, "SRAM DMA declare failed\n");
  2443. pci_release_region(pdev, 1);
  2444. dev->got_sram = 0;
  2445. }
  2446. dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2447. }
  2448. /* release SRAM caching */
  2449. static void sram_deinit(struct langwell_udc *dev)
  2450. {
  2451. struct pci_dev *pdev = dev->pdev;
  2452. dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
  2453. dma_release_declared_memory(&pdev->dev);
  2454. pci_release_region(pdev, 1);
  2455. dev->got_sram = 0;
  2456. dev_info(&dev->pdev->dev, "release SRAM caching\n");
  2457. dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2458. }
  2459. /* tear down the binding between this driver and the pci device */
  2460. static void langwell_udc_remove(struct pci_dev *pdev)
  2461. {
  2462. struct langwell_udc *dev = the_controller;
  2463. DECLARE_COMPLETION(done);
  2464. BUG_ON(dev->driver);
  2465. dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
  2466. dev->done = &done;
  2467. #ifndef OTG_TRANSCEIVER
  2468. /* free dTD dma_pool and dQH */
  2469. if (dev->dtd_pool)
  2470. dma_pool_destroy(dev->dtd_pool);
  2471. if (dev->ep_dqh)
  2472. dma_free_coherent(&pdev->dev, dev->ep_dqh_size,
  2473. dev->ep_dqh, dev->ep_dqh_dma);
  2474. /* release SRAM caching */
  2475. if (dev->has_sram && dev->got_sram)
  2476. sram_deinit(dev);
  2477. #endif
  2478. if (dev->status_req) {
  2479. kfree(dev->status_req->req.buf);
  2480. kfree(dev->status_req);
  2481. }
  2482. kfree(dev->ep);
  2483. /* disable IRQ handler */
  2484. if (dev->got_irq)
  2485. free_irq(pdev->irq, dev);
  2486. #ifndef OTG_TRANSCEIVER
  2487. if (dev->cap_regs)
  2488. iounmap(dev->cap_regs);
  2489. if (dev->region)
  2490. release_mem_region(pci_resource_start(pdev, 0),
  2491. pci_resource_len(pdev, 0));
  2492. if (dev->enabled)
  2493. pci_disable_device(pdev);
  2494. #else
  2495. if (dev->transceiver) {
  2496. otg_put_transceiver(dev->transceiver);
  2497. dev->transceiver = NULL;
  2498. dev->lotg = NULL;
  2499. }
  2500. #endif
  2501. dev->cap_regs = NULL;
  2502. dev_info(&dev->pdev->dev, "unbind\n");
  2503. dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2504. device_unregister(&dev->gadget.dev);
  2505. device_remove_file(&pdev->dev, &dev_attr_langwell_udc);
  2506. device_remove_file(&pdev->dev, &dev_attr_remote_wakeup);
  2507. #ifndef OTG_TRANSCEIVER
  2508. pci_set_drvdata(pdev, NULL);
  2509. #endif
  2510. /* free dev, wait for the release() finished */
  2511. wait_for_completion(&done);
  2512. the_controller = NULL;
  2513. }
  2514. /*
  2515. * wrap this driver around the specified device, but
  2516. * don't respond over USB until a gadget driver binds to us.
  2517. */
  2518. static int langwell_udc_probe(struct pci_dev *pdev,
  2519. const struct pci_device_id *id)
  2520. {
  2521. struct langwell_udc *dev;
  2522. #ifndef OTG_TRANSCEIVER
  2523. unsigned long resource, len;
  2524. #endif
  2525. void __iomem *base = NULL;
  2526. size_t size;
  2527. int retval;
  2528. if (the_controller) {
  2529. dev_warn(&pdev->dev, "ignoring\n");
  2530. return -EBUSY;
  2531. }
  2532. /* alloc, and start init */
  2533. dev = kzalloc(sizeof *dev, GFP_KERNEL);
  2534. if (dev == NULL) {
  2535. retval = -ENOMEM;
  2536. goto error;
  2537. }
  2538. /* initialize device spinlock */
  2539. spin_lock_init(&dev->lock);
  2540. dev->pdev = pdev;
  2541. dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
  2542. #ifdef OTG_TRANSCEIVER
  2543. /* PCI device is already enabled by otg_transceiver driver */
  2544. dev->enabled = 1;
  2545. /* mem region and register base */
  2546. dev->region = 1;
  2547. dev->transceiver = otg_get_transceiver();
  2548. dev->lotg = otg_to_langwell(dev->transceiver);
  2549. base = dev->lotg->regs;
  2550. #else
  2551. pci_set_drvdata(pdev, dev);
  2552. /* now all the pci goodies ... */
  2553. if (pci_enable_device(pdev) < 0) {
  2554. retval = -ENODEV;
  2555. goto error;
  2556. }
  2557. dev->enabled = 1;
  2558. /* control register: BAR 0 */
  2559. resource = pci_resource_start(pdev, 0);
  2560. len = pci_resource_len(pdev, 0);
  2561. if (!request_mem_region(resource, len, driver_name)) {
  2562. dev_err(&dev->pdev->dev, "controller already in use\n");
  2563. retval = -EBUSY;
  2564. goto error;
  2565. }
  2566. dev->region = 1;
  2567. base = ioremap_nocache(resource, len);
  2568. #endif
  2569. if (base == NULL) {
  2570. dev_err(&dev->pdev->dev, "can't map memory\n");
  2571. retval = -EFAULT;
  2572. goto error;
  2573. }
  2574. dev->cap_regs = (struct langwell_cap_regs __iomem *) base;
  2575. dev_vdbg(&dev->pdev->dev, "dev->cap_regs: %p\n", dev->cap_regs);
  2576. dev->op_regs = (struct langwell_op_regs __iomem *)
  2577. (base + OP_REG_OFFSET);
  2578. dev_vdbg(&dev->pdev->dev, "dev->op_regs: %p\n", dev->op_regs);
  2579. /* irq setup after old hardware is cleaned up */
  2580. if (!pdev->irq) {
  2581. dev_err(&dev->pdev->dev, "No IRQ. Check PCI setup!\n");
  2582. retval = -ENODEV;
  2583. goto error;
  2584. }
  2585. dev->has_sram = 1;
  2586. dev->got_sram = 0;
  2587. dev_vdbg(&dev->pdev->dev, "dev->has_sram: %d\n", dev->has_sram);
  2588. #ifndef OTG_TRANSCEIVER
  2589. /* enable SRAM caching if detected */
  2590. if (dev->has_sram && !dev->got_sram)
  2591. sram_init(dev);
  2592. dev_info(&dev->pdev->dev,
  2593. "irq %d, io mem: 0x%08lx, len: 0x%08lx, pci mem 0x%p\n",
  2594. pdev->irq, resource, len, base);
  2595. /* enables bus-mastering for device dev */
  2596. pci_set_master(pdev);
  2597. if (request_irq(pdev->irq, langwell_irq, IRQF_SHARED,
  2598. driver_name, dev) != 0) {
  2599. dev_err(&dev->pdev->dev,
  2600. "request interrupt %d failed\n", pdev->irq);
  2601. retval = -EBUSY;
  2602. goto error;
  2603. }
  2604. dev->got_irq = 1;
  2605. #endif
  2606. /* set stopped bit */
  2607. dev->stopped = 1;
  2608. /* capabilities and endpoint number */
  2609. dev->lpm = (readl(&dev->cap_regs->hccparams) & HCC_LEN) ? 1 : 0;
  2610. dev->dciversion = readw(&dev->cap_regs->dciversion);
  2611. dev->devcap = (readl(&dev->cap_regs->dccparams) & DEVCAP) ? 1 : 0;
  2612. dev_vdbg(&dev->pdev->dev, "dev->lpm: %d\n", dev->lpm);
  2613. dev_vdbg(&dev->pdev->dev, "dev->dciversion: 0x%04x\n",
  2614. dev->dciversion);
  2615. dev_vdbg(&dev->pdev->dev, "dccparams: 0x%08x\n",
  2616. readl(&dev->cap_regs->dccparams));
  2617. dev_vdbg(&dev->pdev->dev, "dev->devcap: %d\n", dev->devcap);
  2618. if (!dev->devcap) {
  2619. dev_err(&dev->pdev->dev, "can't support device mode\n");
  2620. retval = -ENODEV;
  2621. goto error;
  2622. }
  2623. /* a pair of endpoints (out/in) for each address */
  2624. dev->ep_max = DEN(readl(&dev->cap_regs->dccparams)) * 2;
  2625. dev_vdbg(&dev->pdev->dev, "dev->ep_max: %d\n", dev->ep_max);
  2626. /* allocate endpoints memory */
  2627. dev->ep = kzalloc(sizeof(struct langwell_ep) * dev->ep_max,
  2628. GFP_KERNEL);
  2629. if (!dev->ep) {
  2630. dev_err(&dev->pdev->dev, "allocate endpoints memory failed\n");
  2631. retval = -ENOMEM;
  2632. goto error;
  2633. }
  2634. /* allocate device dQH memory */
  2635. size = dev->ep_max * sizeof(struct langwell_dqh);
  2636. dev_vdbg(&dev->pdev->dev, "orig size = %zd\n", size);
  2637. if (size < DQH_ALIGNMENT)
  2638. size = DQH_ALIGNMENT;
  2639. else if ((size % DQH_ALIGNMENT) != 0) {
  2640. size += DQH_ALIGNMENT + 1;
  2641. size &= ~(DQH_ALIGNMENT - 1);
  2642. }
  2643. dev->ep_dqh = dma_alloc_coherent(&pdev->dev, size,
  2644. &dev->ep_dqh_dma, GFP_KERNEL);
  2645. if (!dev->ep_dqh) {
  2646. dev_err(&dev->pdev->dev, "allocate dQH memory failed\n");
  2647. retval = -ENOMEM;
  2648. goto error;
  2649. }
  2650. dev->ep_dqh_size = size;
  2651. dev_vdbg(&dev->pdev->dev, "ep_dqh_size = %zd\n", dev->ep_dqh_size);
  2652. /* initialize ep0 status request structure */
  2653. dev->status_req = kzalloc(sizeof(struct langwell_request), GFP_KERNEL);
  2654. if (!dev->status_req) {
  2655. dev_err(&dev->pdev->dev,
  2656. "allocate status_req memory failed\n");
  2657. retval = -ENOMEM;
  2658. goto error;
  2659. }
  2660. INIT_LIST_HEAD(&dev->status_req->queue);
  2661. /* allocate a small amount of memory to get valid address */
  2662. dev->status_req->req.buf = kmalloc(8, GFP_KERNEL);
  2663. dev->status_req->req.dma = virt_to_phys(dev->status_req->req.buf);
  2664. dev->resume_state = USB_STATE_NOTATTACHED;
  2665. dev->usb_state = USB_STATE_POWERED;
  2666. dev->ep0_dir = USB_DIR_OUT;
  2667. /* remote wakeup reset to 0 when the device is reset */
  2668. dev->remote_wakeup = 0;
  2669. dev->dev_status = 1 << USB_DEVICE_SELF_POWERED;
  2670. #ifndef OTG_TRANSCEIVER
  2671. /* reset device controller */
  2672. langwell_udc_reset(dev);
  2673. #endif
  2674. /* initialize gadget structure */
  2675. dev->gadget.ops = &langwell_ops; /* usb_gadget_ops */
  2676. dev->gadget.ep0 = &dev->ep[0].ep; /* gadget ep0 */
  2677. INIT_LIST_HEAD(&dev->gadget.ep_list); /* ep_list */
  2678. dev->gadget.speed = USB_SPEED_UNKNOWN; /* speed */
  2679. dev->gadget.is_dualspeed = 1; /* support dual speed */
  2680. #ifdef OTG_TRANSCEIVER
  2681. dev->gadget.is_otg = 1; /* support otg mode */
  2682. #endif
  2683. /* the "gadget" abstracts/virtualizes the controller */
  2684. dev_set_name(&dev->gadget.dev, "gadget");
  2685. dev->gadget.dev.parent = &pdev->dev;
  2686. dev->gadget.dev.dma_mask = pdev->dev.dma_mask;
  2687. dev->gadget.dev.release = gadget_release;
  2688. dev->gadget.name = driver_name; /* gadget name */
  2689. /* controller endpoints reinit */
  2690. eps_reinit(dev);
  2691. #ifndef OTG_TRANSCEIVER
  2692. /* reset ep0 dQH and endptctrl */
  2693. ep0_reset(dev);
  2694. #endif
  2695. /* create dTD dma_pool resource */
  2696. dev->dtd_pool = dma_pool_create("langwell_dtd",
  2697. &dev->pdev->dev,
  2698. sizeof(struct langwell_dtd),
  2699. DTD_ALIGNMENT,
  2700. DMA_BOUNDARY);
  2701. if (!dev->dtd_pool) {
  2702. retval = -ENOMEM;
  2703. goto error;
  2704. }
  2705. /* done */
  2706. dev_info(&dev->pdev->dev, "%s\n", driver_desc);
  2707. dev_info(&dev->pdev->dev, "irq %d, pci mem %p\n", pdev->irq, base);
  2708. dev_info(&dev->pdev->dev, "Driver version: " DRIVER_VERSION "\n");
  2709. dev_info(&dev->pdev->dev, "Support (max) %d endpoints\n", dev->ep_max);
  2710. dev_info(&dev->pdev->dev, "Device interface version: 0x%04x\n",
  2711. dev->dciversion);
  2712. dev_info(&dev->pdev->dev, "Controller mode: %s\n",
  2713. dev->devcap ? "Device" : "Host");
  2714. dev_info(&dev->pdev->dev, "Support USB LPM: %s\n",
  2715. dev->lpm ? "Yes" : "No");
  2716. dev_vdbg(&dev->pdev->dev,
  2717. "After langwell_udc_probe(), print all registers:\n");
  2718. print_all_registers(dev);
  2719. the_controller = dev;
  2720. retval = device_register(&dev->gadget.dev);
  2721. if (retval)
  2722. goto error;
  2723. retval = usb_add_gadget_udc(&pdev->dev, &dev->gadget);
  2724. if (retval)
  2725. goto error;
  2726. retval = device_create_file(&pdev->dev, &dev_attr_langwell_udc);
  2727. if (retval)
  2728. goto error;
  2729. retval = device_create_file(&pdev->dev, &dev_attr_remote_wakeup);
  2730. if (retval)
  2731. goto error_attr1;
  2732. dev_vdbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2733. return 0;
  2734. error_attr1:
  2735. device_remove_file(&pdev->dev, &dev_attr_langwell_udc);
  2736. error:
  2737. if (dev) {
  2738. dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2739. langwell_udc_remove(pdev);
  2740. }
  2741. return retval;
  2742. }
  2743. /* device controller suspend */
  2744. static int langwell_udc_suspend(struct pci_dev *pdev, pm_message_t state)
  2745. {
  2746. struct langwell_udc *dev = the_controller;
  2747. dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
  2748. usb_del_gadget_udc(&dev->gadget);
  2749. /* disable interrupt and set controller to stop state */
  2750. langwell_udc_stop(dev);
  2751. /* disable IRQ handler */
  2752. if (dev->got_irq)
  2753. free_irq(pdev->irq, dev);
  2754. dev->got_irq = 0;
  2755. /* save PCI state */
  2756. pci_save_state(pdev);
  2757. spin_lock_irq(&dev->lock);
  2758. /* stop all usb activities */
  2759. stop_activity(dev, dev->driver);
  2760. spin_unlock_irq(&dev->lock);
  2761. /* free dTD dma_pool and dQH */
  2762. if (dev->dtd_pool)
  2763. dma_pool_destroy(dev->dtd_pool);
  2764. if (dev->ep_dqh)
  2765. dma_free_coherent(&pdev->dev, dev->ep_dqh_size,
  2766. dev->ep_dqh, dev->ep_dqh_dma);
  2767. /* release SRAM caching */
  2768. if (dev->has_sram && dev->got_sram)
  2769. sram_deinit(dev);
  2770. /* set device power state */
  2771. pci_set_power_state(pdev, PCI_D3hot);
  2772. /* enter PHY low power suspend */
  2773. if (dev->pdev->device != 0x0829)
  2774. langwell_phy_low_power(dev, 1);
  2775. dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2776. return 0;
  2777. }
  2778. /* device controller resume */
  2779. static int langwell_udc_resume(struct pci_dev *pdev)
  2780. {
  2781. struct langwell_udc *dev = the_controller;
  2782. size_t size;
  2783. dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
  2784. /* exit PHY low power suspend */
  2785. if (dev->pdev->device != 0x0829)
  2786. langwell_phy_low_power(dev, 0);
  2787. /* set device D0 power state */
  2788. pci_set_power_state(pdev, PCI_D0);
  2789. /* enable SRAM caching if detected */
  2790. if (dev->has_sram && !dev->got_sram)
  2791. sram_init(dev);
  2792. /* allocate device dQH memory */
  2793. size = dev->ep_max * sizeof(struct langwell_dqh);
  2794. dev_vdbg(&dev->pdev->dev, "orig size = %zd\n", size);
  2795. if (size < DQH_ALIGNMENT)
  2796. size = DQH_ALIGNMENT;
  2797. else if ((size % DQH_ALIGNMENT) != 0) {
  2798. size += DQH_ALIGNMENT + 1;
  2799. size &= ~(DQH_ALIGNMENT - 1);
  2800. }
  2801. dev->ep_dqh = dma_alloc_coherent(&pdev->dev, size,
  2802. &dev->ep_dqh_dma, GFP_KERNEL);
  2803. if (!dev->ep_dqh) {
  2804. dev_err(&dev->pdev->dev, "allocate dQH memory failed\n");
  2805. return -ENOMEM;
  2806. }
  2807. dev->ep_dqh_size = size;
  2808. dev_vdbg(&dev->pdev->dev, "ep_dqh_size = %zd\n", dev->ep_dqh_size);
  2809. /* create dTD dma_pool resource */
  2810. dev->dtd_pool = dma_pool_create("langwell_dtd",
  2811. &dev->pdev->dev,
  2812. sizeof(struct langwell_dtd),
  2813. DTD_ALIGNMENT,
  2814. DMA_BOUNDARY);
  2815. if (!dev->dtd_pool)
  2816. return -ENOMEM;
  2817. /* restore PCI state */
  2818. pci_restore_state(pdev);
  2819. /* enable IRQ handler */
  2820. if (request_irq(pdev->irq, langwell_irq, IRQF_SHARED,
  2821. driver_name, dev) != 0) {
  2822. dev_err(&dev->pdev->dev, "request interrupt %d failed\n",
  2823. pdev->irq);
  2824. return -EBUSY;
  2825. }
  2826. dev->got_irq = 1;
  2827. /* reset and start controller to run state */
  2828. if (dev->stopped) {
  2829. /* reset device controller */
  2830. langwell_udc_reset(dev);
  2831. /* reset ep0 dQH and endptctrl */
  2832. ep0_reset(dev);
  2833. /* start device if gadget is loaded */
  2834. if (dev->driver)
  2835. langwell_udc_start(dev);
  2836. }
  2837. /* reset USB status */
  2838. dev->usb_state = USB_STATE_ATTACHED;
  2839. dev->ep0_state = WAIT_FOR_SETUP;
  2840. dev->ep0_dir = USB_DIR_OUT;
  2841. dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2842. return 0;
  2843. }
  2844. /* pci driver shutdown */
  2845. static void langwell_udc_shutdown(struct pci_dev *pdev)
  2846. {
  2847. struct langwell_udc *dev = the_controller;
  2848. u32 usbmode;
  2849. dev_dbg(&dev->pdev->dev, "---> %s()\n", __func__);
  2850. /* reset controller mode to IDLE */
  2851. usbmode = readl(&dev->op_regs->usbmode);
  2852. dev_dbg(&dev->pdev->dev, "usbmode = 0x%08x\n", usbmode);
  2853. usbmode &= (~3 | MODE_IDLE);
  2854. writel(usbmode, &dev->op_regs->usbmode);
  2855. dev_dbg(&dev->pdev->dev, "<--- %s()\n", __func__);
  2856. }
  2857. /*-------------------------------------------------------------------------*/
  2858. static const struct pci_device_id pci_ids[] = { {
  2859. .class = ((PCI_CLASS_SERIAL_USB << 8) | 0xfe),
  2860. .class_mask = ~0,
  2861. .vendor = 0x8086,
  2862. .device = 0x0811,
  2863. .subvendor = PCI_ANY_ID,
  2864. .subdevice = PCI_ANY_ID,
  2865. }, { /* end: all zeroes */ }
  2866. };
  2867. MODULE_DEVICE_TABLE(pci, pci_ids);
  2868. static struct pci_driver langwell_pci_driver = {
  2869. .name = (char *) driver_name,
  2870. .id_table = pci_ids,
  2871. .probe = langwell_udc_probe,
  2872. .remove = langwell_udc_remove,
  2873. /* device controller suspend/resume */
  2874. .suspend = langwell_udc_suspend,
  2875. .resume = langwell_udc_resume,
  2876. .shutdown = langwell_udc_shutdown,
  2877. };
  2878. static int __init init(void)
  2879. {
  2880. #ifdef OTG_TRANSCEIVER
  2881. return langwell_register_peripheral(&langwell_pci_driver);
  2882. #else
  2883. return pci_register_driver(&langwell_pci_driver);
  2884. #endif
  2885. }
  2886. module_init(init);
  2887. static void __exit cleanup(void)
  2888. {
  2889. #ifdef OTG_TRANSCEIVER
  2890. return langwell_unregister_peripheral(&langwell_pci_driver);
  2891. #else
  2892. pci_unregister_driver(&langwell_pci_driver);
  2893. #endif
  2894. }
  2895. module_exit(cleanup);
  2896. MODULE_DESCRIPTION(DRIVER_DESC);
  2897. MODULE_AUTHOR("Xiaochen Shen <xiaochen.shen@intel.com>");
  2898. MODULE_VERSION(DRIVER_VERSION);
  2899. MODULE_LICENSE("GPL");