system.h 14 KB

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  1. /*
  2. * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu>
  3. */
  4. #ifndef _ASM_POWERPC_SYSTEM_H
  5. #define _ASM_POWERPC_SYSTEM_H
  6. #include <linux/kernel.h>
  7. #include <linux/irqflags.h>
  8. #include <asm/hw_irq.h>
  9. /*
  10. * Memory barrier.
  11. * The sync instruction guarantees that all memory accesses initiated
  12. * by this processor have been performed (with respect to all other
  13. * mechanisms that access memory). The eieio instruction is a barrier
  14. * providing an ordering (separately) for (a) cacheable stores and (b)
  15. * loads and stores to non-cacheable memory (e.g. I/O devices).
  16. *
  17. * mb() prevents loads and stores being reordered across this point.
  18. * rmb() prevents loads being reordered across this point.
  19. * wmb() prevents stores being reordered across this point.
  20. * read_barrier_depends() prevents data-dependent loads being reordered
  21. * across this point (nop on PPC).
  22. *
  23. * *mb() variants without smp_ prefix must order all types of memory
  24. * operations with one another. sync is the only instruction sufficient
  25. * to do this.
  26. *
  27. * For the smp_ barriers, ordering is for cacheable memory operations
  28. * only. We have to use the sync instruction for smp_mb(), since lwsync
  29. * doesn't order loads with respect to previous stores. Lwsync can be
  30. * used for smp_rmb() and smp_wmb().
  31. *
  32. * However, on CPUs that don't support lwsync, lwsync actually maps to a
  33. * heavy-weight sync, so smp_wmb() can be a lighter-weight eieio.
  34. */
  35. #define mb() __asm__ __volatile__ ("sync" : : : "memory")
  36. #define rmb() __asm__ __volatile__ ("sync" : : : "memory")
  37. #define wmb() __asm__ __volatile__ ("sync" : : : "memory")
  38. #define read_barrier_depends() do { } while(0)
  39. #define set_mb(var, value) do { var = value; mb(); } while (0)
  40. #ifdef __KERNEL__
  41. #define AT_VECTOR_SIZE_ARCH 6 /* entries in ARCH_DLINFO */
  42. #ifdef CONFIG_SMP
  43. #ifdef __SUBARCH_HAS_LWSYNC
  44. # define SMPWMB LWSYNC
  45. #else
  46. # define SMPWMB eieio
  47. #endif
  48. #define smp_mb() mb()
  49. #define smp_rmb() __asm__ __volatile__ (stringify_in_c(LWSYNC) : : :"memory")
  50. #define smp_wmb() __asm__ __volatile__ (stringify_in_c(SMPWMB) : : :"memory")
  51. #define smp_read_barrier_depends() read_barrier_depends()
  52. #else
  53. #define smp_mb() barrier()
  54. #define smp_rmb() barrier()
  55. #define smp_wmb() barrier()
  56. #define smp_read_barrier_depends() do { } while(0)
  57. #endif /* CONFIG_SMP */
  58. /*
  59. * This is a barrier which prevents following instructions from being
  60. * started until the value of the argument x is known. For example, if
  61. * x is a variable loaded from memory, this prevents following
  62. * instructions from being executed until the load has been performed.
  63. */
  64. #define data_barrier(x) \
  65. asm volatile("twi 0,%0,0; isync" : : "r" (x) : "memory");
  66. struct task_struct;
  67. struct pt_regs;
  68. #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
  69. extern int (*__debugger)(struct pt_regs *regs);
  70. extern int (*__debugger_ipi)(struct pt_regs *regs);
  71. extern int (*__debugger_bpt)(struct pt_regs *regs);
  72. extern int (*__debugger_sstep)(struct pt_regs *regs);
  73. extern int (*__debugger_iabr_match)(struct pt_regs *regs);
  74. extern int (*__debugger_dabr_match)(struct pt_regs *regs);
  75. extern int (*__debugger_fault_handler)(struct pt_regs *regs);
  76. #define DEBUGGER_BOILERPLATE(__NAME) \
  77. static inline int __NAME(struct pt_regs *regs) \
  78. { \
  79. if (unlikely(__ ## __NAME)) \
  80. return __ ## __NAME(regs); \
  81. return 0; \
  82. }
  83. DEBUGGER_BOILERPLATE(debugger)
  84. DEBUGGER_BOILERPLATE(debugger_ipi)
  85. DEBUGGER_BOILERPLATE(debugger_bpt)
  86. DEBUGGER_BOILERPLATE(debugger_sstep)
  87. DEBUGGER_BOILERPLATE(debugger_iabr_match)
  88. DEBUGGER_BOILERPLATE(debugger_dabr_match)
  89. DEBUGGER_BOILERPLATE(debugger_fault_handler)
  90. #else
  91. static inline int debugger(struct pt_regs *regs) { return 0; }
  92. static inline int debugger_ipi(struct pt_regs *regs) { return 0; }
  93. static inline int debugger_bpt(struct pt_regs *regs) { return 0; }
  94. static inline int debugger_sstep(struct pt_regs *regs) { return 0; }
  95. static inline int debugger_iabr_match(struct pt_regs *regs) { return 0; }
  96. static inline int debugger_dabr_match(struct pt_regs *regs) { return 0; }
  97. static inline int debugger_fault_handler(struct pt_regs *regs) { return 0; }
  98. #endif
  99. extern int set_dabr(unsigned long dabr);
  100. #ifdef CONFIG_PPC_ADV_DEBUG_REGS
  101. extern void do_send_trap(struct pt_regs *regs, unsigned long address,
  102. unsigned long error_code, int signal_code, int brkpt);
  103. #else
  104. extern void do_dabr(struct pt_regs *regs, unsigned long address,
  105. unsigned long error_code);
  106. #endif
  107. extern void print_backtrace(unsigned long *);
  108. extern void flush_instruction_cache(void);
  109. extern void hard_reset_now(void);
  110. extern void poweroff_now(void);
  111. #ifdef CONFIG_6xx
  112. extern long _get_L2CR(void);
  113. extern long _get_L3CR(void);
  114. extern void _set_L2CR(unsigned long);
  115. extern void _set_L3CR(unsigned long);
  116. #else
  117. #define _get_L2CR() 0L
  118. #define _get_L3CR() 0L
  119. #define _set_L2CR(val) do { } while(0)
  120. #define _set_L3CR(val) do { } while(0)
  121. #endif
  122. extern void via_cuda_init(void);
  123. extern void read_rtc_time(void);
  124. extern void pmac_find_display(void);
  125. extern void giveup_fpu(struct task_struct *);
  126. extern void disable_kernel_fp(void);
  127. extern void enable_kernel_fp(void);
  128. extern void flush_fp_to_thread(struct task_struct *);
  129. extern void enable_kernel_altivec(void);
  130. extern void giveup_altivec(struct task_struct *);
  131. extern void load_up_altivec(struct task_struct *);
  132. extern int emulate_altivec(struct pt_regs *);
  133. extern void __giveup_vsx(struct task_struct *);
  134. extern void giveup_vsx(struct task_struct *);
  135. extern void enable_kernel_spe(void);
  136. extern void giveup_spe(struct task_struct *);
  137. extern void load_up_spe(struct task_struct *);
  138. extern int fix_alignment(struct pt_regs *);
  139. extern void cvt_fd(float *from, double *to);
  140. extern void cvt_df(double *from, float *to);
  141. #ifndef CONFIG_SMP
  142. extern void discard_lazy_cpu_state(void);
  143. #else
  144. static inline void discard_lazy_cpu_state(void)
  145. {
  146. }
  147. #endif
  148. #ifdef CONFIG_ALTIVEC
  149. extern void flush_altivec_to_thread(struct task_struct *);
  150. #else
  151. static inline void flush_altivec_to_thread(struct task_struct *t)
  152. {
  153. }
  154. #endif
  155. #ifdef CONFIG_VSX
  156. extern void flush_vsx_to_thread(struct task_struct *);
  157. #else
  158. static inline void flush_vsx_to_thread(struct task_struct *t)
  159. {
  160. }
  161. #endif
  162. #ifdef CONFIG_SPE
  163. extern void flush_spe_to_thread(struct task_struct *);
  164. #else
  165. static inline void flush_spe_to_thread(struct task_struct *t)
  166. {
  167. }
  168. #endif
  169. extern int call_rtas(const char *, int, int, unsigned long *, ...);
  170. extern void cacheable_memzero(void *p, unsigned int nb);
  171. extern void *cacheable_memcpy(void *, const void *, unsigned int);
  172. extern int do_page_fault(struct pt_regs *, unsigned long, unsigned long);
  173. extern void bad_page_fault(struct pt_regs *, unsigned long, int);
  174. extern int die(const char *, struct pt_regs *, long);
  175. extern void _exception(int, struct pt_regs *, int, unsigned long);
  176. extern void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
  177. #ifdef CONFIG_BOOKE_WDT
  178. extern u32 booke_wdt_enabled;
  179. extern u32 booke_wdt_period;
  180. #endif /* CONFIG_BOOKE_WDT */
  181. struct device_node;
  182. extern void note_scsi_host(struct device_node *, void *);
  183. extern struct task_struct *__switch_to(struct task_struct *,
  184. struct task_struct *);
  185. #define switch_to(prev, next, last) ((last) = __switch_to((prev), (next)))
  186. struct thread_struct;
  187. extern struct task_struct *_switch(struct thread_struct *prev,
  188. struct thread_struct *next);
  189. extern unsigned int rtas_data;
  190. extern int mem_init_done; /* set on boot once kmalloc can be called */
  191. extern int init_bootmem_done; /* set once bootmem is available */
  192. extern phys_addr_t memory_limit;
  193. extern unsigned long klimit;
  194. extern void *zalloc_maybe_bootmem(size_t size, gfp_t mask);
  195. extern int powersave_nap; /* set if nap mode can be used in idle loop */
  196. /*
  197. * Atomic exchange
  198. *
  199. * Changes the memory location '*ptr' to be val and returns
  200. * the previous value stored there.
  201. */
  202. static __always_inline unsigned long
  203. __xchg_u32(volatile void *p, unsigned long val)
  204. {
  205. unsigned long prev;
  206. __asm__ __volatile__(
  207. PPC_RELEASE_BARRIER
  208. "1: lwarx %0,0,%2 \n"
  209. PPC405_ERR77(0,%2)
  210. " stwcx. %3,0,%2 \n\
  211. bne- 1b"
  212. PPC_ACQUIRE_BARRIER
  213. : "=&r" (prev), "+m" (*(volatile unsigned int *)p)
  214. : "r" (p), "r" (val)
  215. : "cc", "memory");
  216. return prev;
  217. }
  218. /*
  219. * Atomic exchange
  220. *
  221. * Changes the memory location '*ptr' to be val and returns
  222. * the previous value stored there.
  223. */
  224. static __always_inline unsigned long
  225. __xchg_u32_local(volatile void *p, unsigned long val)
  226. {
  227. unsigned long prev;
  228. __asm__ __volatile__(
  229. "1: lwarx %0,0,%2 \n"
  230. PPC405_ERR77(0,%2)
  231. " stwcx. %3,0,%2 \n\
  232. bne- 1b"
  233. : "=&r" (prev), "+m" (*(volatile unsigned int *)p)
  234. : "r" (p), "r" (val)
  235. : "cc", "memory");
  236. return prev;
  237. }
  238. #ifdef CONFIG_PPC64
  239. static __always_inline unsigned long
  240. __xchg_u64(volatile void *p, unsigned long val)
  241. {
  242. unsigned long prev;
  243. __asm__ __volatile__(
  244. PPC_RELEASE_BARRIER
  245. "1: ldarx %0,0,%2 \n"
  246. PPC405_ERR77(0,%2)
  247. " stdcx. %3,0,%2 \n\
  248. bne- 1b"
  249. PPC_ACQUIRE_BARRIER
  250. : "=&r" (prev), "+m" (*(volatile unsigned long *)p)
  251. : "r" (p), "r" (val)
  252. : "cc", "memory");
  253. return prev;
  254. }
  255. static __always_inline unsigned long
  256. __xchg_u64_local(volatile void *p, unsigned long val)
  257. {
  258. unsigned long prev;
  259. __asm__ __volatile__(
  260. "1: ldarx %0,0,%2 \n"
  261. PPC405_ERR77(0,%2)
  262. " stdcx. %3,0,%2 \n\
  263. bne- 1b"
  264. : "=&r" (prev), "+m" (*(volatile unsigned long *)p)
  265. : "r" (p), "r" (val)
  266. : "cc", "memory");
  267. return prev;
  268. }
  269. #endif
  270. /*
  271. * This function doesn't exist, so you'll get a linker error
  272. * if something tries to do an invalid xchg().
  273. */
  274. extern void __xchg_called_with_bad_pointer(void);
  275. static __always_inline unsigned long
  276. __xchg(volatile void *ptr, unsigned long x, unsigned int size)
  277. {
  278. switch (size) {
  279. case 4:
  280. return __xchg_u32(ptr, x);
  281. #ifdef CONFIG_PPC64
  282. case 8:
  283. return __xchg_u64(ptr, x);
  284. #endif
  285. }
  286. __xchg_called_with_bad_pointer();
  287. return x;
  288. }
  289. static __always_inline unsigned long
  290. __xchg_local(volatile void *ptr, unsigned long x, unsigned int size)
  291. {
  292. switch (size) {
  293. case 4:
  294. return __xchg_u32_local(ptr, x);
  295. #ifdef CONFIG_PPC64
  296. case 8:
  297. return __xchg_u64_local(ptr, x);
  298. #endif
  299. }
  300. __xchg_called_with_bad_pointer();
  301. return x;
  302. }
  303. #define xchg(ptr,x) \
  304. ({ \
  305. __typeof__(*(ptr)) _x_ = (x); \
  306. (__typeof__(*(ptr))) __xchg((ptr), (unsigned long)_x_, sizeof(*(ptr))); \
  307. })
  308. #define xchg_local(ptr,x) \
  309. ({ \
  310. __typeof__(*(ptr)) _x_ = (x); \
  311. (__typeof__(*(ptr))) __xchg_local((ptr), \
  312. (unsigned long)_x_, sizeof(*(ptr))); \
  313. })
  314. /*
  315. * Compare and exchange - if *p == old, set it to new,
  316. * and return the old value of *p.
  317. */
  318. #define __HAVE_ARCH_CMPXCHG 1
  319. static __always_inline unsigned long
  320. __cmpxchg_u32(volatile unsigned int *p, unsigned long old, unsigned long new)
  321. {
  322. unsigned int prev;
  323. __asm__ __volatile__ (
  324. PPC_RELEASE_BARRIER
  325. "1: lwarx %0,0,%2 # __cmpxchg_u32\n\
  326. cmpw 0,%0,%3\n\
  327. bne- 2f\n"
  328. PPC405_ERR77(0,%2)
  329. " stwcx. %4,0,%2\n\
  330. bne- 1b"
  331. PPC_ACQUIRE_BARRIER
  332. "\n\
  333. 2:"
  334. : "=&r" (prev), "+m" (*p)
  335. : "r" (p), "r" (old), "r" (new)
  336. : "cc", "memory");
  337. return prev;
  338. }
  339. static __always_inline unsigned long
  340. __cmpxchg_u32_local(volatile unsigned int *p, unsigned long old,
  341. unsigned long new)
  342. {
  343. unsigned int prev;
  344. __asm__ __volatile__ (
  345. "1: lwarx %0,0,%2 # __cmpxchg_u32\n\
  346. cmpw 0,%0,%3\n\
  347. bne- 2f\n"
  348. PPC405_ERR77(0,%2)
  349. " stwcx. %4,0,%2\n\
  350. bne- 1b"
  351. "\n\
  352. 2:"
  353. : "=&r" (prev), "+m" (*p)
  354. : "r" (p), "r" (old), "r" (new)
  355. : "cc", "memory");
  356. return prev;
  357. }
  358. #ifdef CONFIG_PPC64
  359. static __always_inline unsigned long
  360. __cmpxchg_u64(volatile unsigned long *p, unsigned long old, unsigned long new)
  361. {
  362. unsigned long prev;
  363. __asm__ __volatile__ (
  364. PPC_RELEASE_BARRIER
  365. "1: ldarx %0,0,%2 # __cmpxchg_u64\n\
  366. cmpd 0,%0,%3\n\
  367. bne- 2f\n\
  368. stdcx. %4,0,%2\n\
  369. bne- 1b"
  370. PPC_ACQUIRE_BARRIER
  371. "\n\
  372. 2:"
  373. : "=&r" (prev), "+m" (*p)
  374. : "r" (p), "r" (old), "r" (new)
  375. : "cc", "memory");
  376. return prev;
  377. }
  378. static __always_inline unsigned long
  379. __cmpxchg_u64_local(volatile unsigned long *p, unsigned long old,
  380. unsigned long new)
  381. {
  382. unsigned long prev;
  383. __asm__ __volatile__ (
  384. "1: ldarx %0,0,%2 # __cmpxchg_u64\n\
  385. cmpd 0,%0,%3\n\
  386. bne- 2f\n\
  387. stdcx. %4,0,%2\n\
  388. bne- 1b"
  389. "\n\
  390. 2:"
  391. : "=&r" (prev), "+m" (*p)
  392. : "r" (p), "r" (old), "r" (new)
  393. : "cc", "memory");
  394. return prev;
  395. }
  396. #endif
  397. /* This function doesn't exist, so you'll get a linker error
  398. if something tries to do an invalid cmpxchg(). */
  399. extern void __cmpxchg_called_with_bad_pointer(void);
  400. static __always_inline unsigned long
  401. __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new,
  402. unsigned int size)
  403. {
  404. switch (size) {
  405. case 4:
  406. return __cmpxchg_u32(ptr, old, new);
  407. #ifdef CONFIG_PPC64
  408. case 8:
  409. return __cmpxchg_u64(ptr, old, new);
  410. #endif
  411. }
  412. __cmpxchg_called_with_bad_pointer();
  413. return old;
  414. }
  415. static __always_inline unsigned long
  416. __cmpxchg_local(volatile void *ptr, unsigned long old, unsigned long new,
  417. unsigned int size)
  418. {
  419. switch (size) {
  420. case 4:
  421. return __cmpxchg_u32_local(ptr, old, new);
  422. #ifdef CONFIG_PPC64
  423. case 8:
  424. return __cmpxchg_u64_local(ptr, old, new);
  425. #endif
  426. }
  427. __cmpxchg_called_with_bad_pointer();
  428. return old;
  429. }
  430. #define cmpxchg(ptr, o, n) \
  431. ({ \
  432. __typeof__(*(ptr)) _o_ = (o); \
  433. __typeof__(*(ptr)) _n_ = (n); \
  434. (__typeof__(*(ptr))) __cmpxchg((ptr), (unsigned long)_o_, \
  435. (unsigned long)_n_, sizeof(*(ptr))); \
  436. })
  437. #define cmpxchg_local(ptr, o, n) \
  438. ({ \
  439. __typeof__(*(ptr)) _o_ = (o); \
  440. __typeof__(*(ptr)) _n_ = (n); \
  441. (__typeof__(*(ptr))) __cmpxchg_local((ptr), (unsigned long)_o_, \
  442. (unsigned long)_n_, sizeof(*(ptr))); \
  443. })
  444. #ifdef CONFIG_PPC64
  445. /*
  446. * We handle most unaligned accesses in hardware. On the other hand
  447. * unaligned DMA can be very expensive on some ppc64 IO chips (it does
  448. * powers of 2 writes until it reaches sufficient alignment).
  449. *
  450. * Based on this we disable the IP header alignment in network drivers.
  451. */
  452. #define NET_IP_ALIGN 0
  453. #define cmpxchg64(ptr, o, n) \
  454. ({ \
  455. BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
  456. cmpxchg((ptr), (o), (n)); \
  457. })
  458. #define cmpxchg64_local(ptr, o, n) \
  459. ({ \
  460. BUILD_BUG_ON(sizeof(*(ptr)) != 8); \
  461. cmpxchg_local((ptr), (o), (n)); \
  462. })
  463. #else
  464. #include <asm-generic/cmpxchg-local.h>
  465. #define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
  466. #endif
  467. extern unsigned long arch_align_stack(unsigned long sp);
  468. /* Used in very early kernel initialization. */
  469. extern unsigned long reloc_offset(void);
  470. extern unsigned long add_reloc_offset(unsigned long);
  471. extern void reloc_got2(unsigned long);
  472. #define PTRRELOC(x) ((typeof(x)) add_reloc_offset((unsigned long)(x)))
  473. extern struct dentry *powerpc_debugfs_root;
  474. #endif /* __KERNEL__ */
  475. #endif /* _ASM_POWERPC_SYSTEM_H */