pm-sh7372.c 5.9 KB

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  1. /*
  2. * sh7372 Power management support
  3. *
  4. * Copyright (C) 2011 Magnus Damm
  5. *
  6. * This file is subject to the terms and conditions of the GNU General Public
  7. * License. See the file "COPYING" in the main directory of this archive
  8. * for more details.
  9. */
  10. #include <linux/pm.h>
  11. #include <linux/suspend.h>
  12. #include <linux/cpuidle.h>
  13. #include <linux/module.h>
  14. #include <linux/list.h>
  15. #include <linux/err.h>
  16. #include <linux/slab.h>
  17. #include <linux/pm_runtime.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/delay.h>
  20. #include <asm/system.h>
  21. #include <asm/io.h>
  22. #include <asm/tlbflush.h>
  23. #include <mach/common.h>
  24. #include <mach/sh7372.h>
  25. #define SMFRAM 0xe6a70000
  26. #define SYSTBCR 0xe6150024
  27. #define SBAR 0xe6180020
  28. #define APARMBAREA 0xe6f10020
  29. #define SPDCR 0xe6180008
  30. #define SWUCR 0xe6180014
  31. #define PSTR 0xe6180080
  32. #define PSTR_RETRIES 100
  33. #define PSTR_DELAY_US 10
  34. #ifdef CONFIG_PM
  35. static int pd_power_down(struct generic_pm_domain *genpd)
  36. {
  37. struct sh7372_pm_domain *sh7372_pd = to_sh7372_pd(genpd);
  38. unsigned int mask = 1 << sh7372_pd->bit_shift;
  39. if (__raw_readl(PSTR) & mask) {
  40. unsigned int retry_count;
  41. __raw_writel(mask, SPDCR);
  42. for (retry_count = PSTR_RETRIES; retry_count; retry_count--) {
  43. if (!(__raw_readl(SPDCR) & mask))
  44. break;
  45. cpu_relax();
  46. }
  47. }
  48. pr_debug("sh7372 power domain down 0x%08x -> PSTR = 0x%08x\n",
  49. mask, __raw_readl(PSTR));
  50. return 0;
  51. }
  52. static int pd_power_up(struct generic_pm_domain *genpd)
  53. {
  54. struct sh7372_pm_domain *sh7372_pd = to_sh7372_pd(genpd);
  55. unsigned int mask = 1 << sh7372_pd->bit_shift;
  56. unsigned int retry_count;
  57. int ret = 0;
  58. if (__raw_readl(PSTR) & mask)
  59. goto out;
  60. __raw_writel(mask, SWUCR);
  61. for (retry_count = 2 * PSTR_RETRIES; retry_count; retry_count--) {
  62. if (!(__raw_readl(SWUCR) & mask))
  63. goto out;
  64. if (retry_count > PSTR_RETRIES)
  65. udelay(PSTR_DELAY_US);
  66. else
  67. cpu_relax();
  68. }
  69. if (__raw_readl(SWUCR) & mask)
  70. ret = -EIO;
  71. out:
  72. pr_debug("sh7372 power domain up 0x%08x -> PSTR = 0x%08x\n",
  73. mask, __raw_readl(PSTR));
  74. return ret;
  75. }
  76. static int pd_power_up_a3rv(struct generic_pm_domain *genpd)
  77. {
  78. int ret = pd_power_up(genpd);
  79. /* force A4LC on after A3RV has been requested on */
  80. pm_genpd_poweron(&sh7372_a4lc.genpd);
  81. return ret;
  82. }
  83. static int pd_power_down_a3rv(struct generic_pm_domain *genpd)
  84. {
  85. int ret = pd_power_down(genpd);
  86. /* try to power down A4LC after A3RV is requested off */
  87. genpd_queue_power_off_work(&sh7372_a4lc.genpd);
  88. return ret;
  89. }
  90. static int pd_power_down_a4lc(struct generic_pm_domain *genpd)
  91. {
  92. /* only power down A4LC if A3RV is off */
  93. if (!(__raw_readl(PSTR) & (1 << sh7372_a3rv.bit_shift)))
  94. return pd_power_down(genpd);
  95. return -EBUSY;
  96. }
  97. static bool pd_active_wakeup(struct device *dev)
  98. {
  99. return true;
  100. }
  101. void sh7372_init_pm_domain(struct sh7372_pm_domain *sh7372_pd)
  102. {
  103. struct generic_pm_domain *genpd = &sh7372_pd->genpd;
  104. pm_genpd_init(genpd, NULL, false);
  105. genpd->stop_device = pm_clk_suspend;
  106. genpd->start_device = pm_clk_resume;
  107. genpd->active_wakeup = pd_active_wakeup;
  108. if (sh7372_pd == &sh7372_a4lc) {
  109. genpd->power_off = pd_power_down_a4lc;
  110. genpd->power_on = pd_power_up;
  111. } else if (sh7372_pd == &sh7372_a3rv) {
  112. genpd->power_off = pd_power_down_a3rv;
  113. genpd->power_on = pd_power_up_a3rv;
  114. } else {
  115. genpd->power_off = pd_power_down;
  116. genpd->power_on = pd_power_up;
  117. }
  118. genpd->power_on(&sh7372_pd->genpd);
  119. }
  120. void sh7372_add_device_to_domain(struct sh7372_pm_domain *sh7372_pd,
  121. struct platform_device *pdev)
  122. {
  123. struct device *dev = &pdev->dev;
  124. if (!dev->power.subsys_data) {
  125. pm_clk_init(dev);
  126. pm_clk_add(dev, NULL);
  127. }
  128. pm_genpd_add_device(&sh7372_pd->genpd, dev);
  129. }
  130. struct sh7372_pm_domain sh7372_a4lc = {
  131. .bit_shift = 1,
  132. };
  133. struct sh7372_pm_domain sh7372_a4mp = {
  134. .bit_shift = 2,
  135. };
  136. struct sh7372_pm_domain sh7372_d4 = {
  137. .bit_shift = 3,
  138. };
  139. struct sh7372_pm_domain sh7372_a3rv = {
  140. .bit_shift = 6,
  141. };
  142. struct sh7372_pm_domain sh7372_a3ri = {
  143. .bit_shift = 8,
  144. };
  145. struct sh7372_pm_domain sh7372_a3sg = {
  146. .bit_shift = 13,
  147. };
  148. #endif /* CONFIG_PM */
  149. static void sh7372_enter_core_standby(void)
  150. {
  151. void __iomem *smfram = (void __iomem *)SMFRAM;
  152. __raw_writel(0, APARMBAREA); /* translate 4k */
  153. __raw_writel(__pa(sh7372_cpu_resume), SBAR); /* set reset vector */
  154. __raw_writel(0x10, SYSTBCR); /* enable core standby */
  155. __raw_writel(0, smfram + 0x3c); /* clear page table address */
  156. sh7372_cpu_suspend();
  157. cpu_init();
  158. /* if page table address is non-NULL then we have been powered down */
  159. if (__raw_readl(smfram + 0x3c)) {
  160. __raw_writel(__raw_readl(smfram + 0x40),
  161. __va(__raw_readl(smfram + 0x3c)));
  162. flush_tlb_all();
  163. set_cr(__raw_readl(smfram + 0x38));
  164. }
  165. __raw_writel(0, SYSTBCR); /* disable core standby */
  166. __raw_writel(0, SBAR); /* disable reset vector translation */
  167. }
  168. #ifdef CONFIG_CPU_IDLE
  169. static void sh7372_cpuidle_setup(struct cpuidle_device *dev)
  170. {
  171. struct cpuidle_state *state;
  172. int i = dev->state_count;
  173. state = &dev->states[i];
  174. snprintf(state->name, CPUIDLE_NAME_LEN, "C2");
  175. strncpy(state->desc, "Core Standby Mode", CPUIDLE_DESC_LEN);
  176. state->exit_latency = 10;
  177. state->target_residency = 20 + 10;
  178. state->power_usage = 1; /* perhaps not */
  179. state->flags = 0;
  180. state->flags |= CPUIDLE_FLAG_TIME_VALID;
  181. shmobile_cpuidle_modes[i] = sh7372_enter_core_standby;
  182. dev->state_count = i + 1;
  183. }
  184. static void sh7372_cpuidle_init(void)
  185. {
  186. shmobile_cpuidle_setup = sh7372_cpuidle_setup;
  187. }
  188. #else
  189. static void sh7372_cpuidle_init(void) {}
  190. #endif
  191. #ifdef CONFIG_SUSPEND
  192. static int sh7372_enter_suspend(suspend_state_t suspend_state)
  193. {
  194. sh7372_enter_core_standby();
  195. return 0;
  196. }
  197. static void sh7372_suspend_init(void)
  198. {
  199. shmobile_suspend_ops.enter = sh7372_enter_suspend;
  200. }
  201. #else
  202. static void sh7372_suspend_init(void) {}
  203. #endif
  204. #define DBGREG1 0xe6100020
  205. #define DBGREG9 0xe6100040
  206. void __init sh7372_pm_init(void)
  207. {
  208. /* enable DBG hardware block to kick SYSC */
  209. __raw_writel(0x0000a500, DBGREG9);
  210. __raw_writel(0x0000a501, DBGREG9);
  211. __raw_writel(0x00000000, DBGREG1);
  212. sh7372_suspend_init();
  213. sh7372_cpuidle_init();
  214. }