tegra20.dtsi 2.6 KB

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  1. /include/ "skeleton.dtsi"
  2. / {
  3. compatible = "nvidia,tegra20";
  4. interrupt-parent = <&intc>;
  5. intc: interrupt-controller@50041000 {
  6. compatible = "nvidia,tegra20-gic";
  7. interrupt-controller;
  8. #interrupt-cells = <1>;
  9. reg = < 0x50041000 0x1000 >,
  10. < 0x50040100 0x0100 >;
  11. };
  12. i2c@7000c000 {
  13. #address-cells = <1>;
  14. #size-cells = <0>;
  15. compatible = "nvidia,tegra20-i2c";
  16. reg = <0x7000C000 0x100>;
  17. interrupts = < 70 >;
  18. };
  19. i2c@7000c400 {
  20. #address-cells = <1>;
  21. #size-cells = <0>;
  22. compatible = "nvidia,tegra20-i2c";
  23. reg = <0x7000C400 0x100>;
  24. interrupts = < 116 >;
  25. };
  26. i2c@7000c500 {
  27. #address-cells = <1>;
  28. #size-cells = <0>;
  29. compatible = "nvidia,tegra20-i2c";
  30. reg = <0x7000C500 0x100>;
  31. interrupts = < 124 >;
  32. };
  33. i2c@7000d000 {
  34. #address-cells = <1>;
  35. #size-cells = <0>;
  36. compatible = "nvidia,tegra20-i2c";
  37. reg = <0x7000D000 0x200>;
  38. interrupts = < 85 >;
  39. };
  40. i2s@70002800 {
  41. #address-cells = <1>;
  42. #size-cells = <0>;
  43. compatible = "nvidia,tegra20-i2s";
  44. reg = <0x70002800 0x200>;
  45. interrupts = < 45 >;
  46. dma-channel = < 2 >;
  47. };
  48. i2s@70002a00 {
  49. #address-cells = <1>;
  50. #size-cells = <0>;
  51. compatible = "nvidia,tegra20-i2s";
  52. reg = <0x70002a00 0x200>;
  53. interrupts = < 35 >;
  54. dma-channel = < 1 >;
  55. };
  56. das@70000c00 {
  57. #address-cells = <1>;
  58. #size-cells = <0>;
  59. compatible = "nvidia,tegra20-das";
  60. reg = <0x70000c00 0x80>;
  61. };
  62. gpio: gpio@6000d000 {
  63. compatible = "nvidia,tegra20-gpio";
  64. reg = < 0x6000d000 0x1000 >;
  65. interrupts = < 64 65 66 67 87 119 121 >;
  66. #gpio-cells = <2>;
  67. gpio-controller;
  68. };
  69. serial@70006000 {
  70. compatible = "nvidia,tegra20-uart";
  71. reg = <0x70006000 0x40>;
  72. reg-shift = <2>;
  73. interrupts = < 68 >;
  74. };
  75. serial@70006040 {
  76. compatible = "nvidia,tegra20-uart";
  77. reg = <0x70006040 0x40>;
  78. reg-shift = <2>;
  79. interrupts = < 69 >;
  80. };
  81. serial@70006200 {
  82. compatible = "nvidia,tegra20-uart";
  83. reg = <0x70006200 0x100>;
  84. reg-shift = <2>;
  85. interrupts = < 78 >;
  86. };
  87. serial@70006300 {
  88. compatible = "nvidia,tegra20-uart";
  89. reg = <0x70006300 0x100>;
  90. reg-shift = <2>;
  91. interrupts = < 122 >;
  92. };
  93. serial@70006400 {
  94. compatible = "nvidia,tegra20-uart";
  95. reg = <0x70006400 0x100>;
  96. reg-shift = <2>;
  97. interrupts = < 123 >;
  98. };
  99. sdhci@c8000000 {
  100. compatible = "nvidia,tegra20-sdhci";
  101. reg = <0xc8000000 0x200>;
  102. interrupts = < 46 >;
  103. };
  104. sdhci@c8000200 {
  105. compatible = "nvidia,tegra20-sdhci";
  106. reg = <0xc8000200 0x200>;
  107. interrupts = < 47 >;
  108. };
  109. sdhci@c8000400 {
  110. compatible = "nvidia,tegra20-sdhci";
  111. reg = <0xc8000400 0x200>;
  112. interrupts = < 51 >;
  113. };
  114. sdhci@c8000600 {
  115. compatible = "nvidia,tegra20-sdhci";
  116. reg = <0xc8000600 0x200>;
  117. interrupts = < 63 >;
  118. };
  119. };