cx88-dvb.c 23 KB

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  1. /*
  2. *
  3. * device driver for Conexant 2388x based TV cards
  4. * MPEG Transport Stream (DVB) routines
  5. *
  6. * (c) 2004, 2005 Chris Pascoe <c.pascoe@itee.uq.edu.au>
  7. * (c) 2004 Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22. */
  23. #include <linux/module.h>
  24. #include <linux/init.h>
  25. #include <linux/device.h>
  26. #include <linux/fs.h>
  27. #include <linux/kthread.h>
  28. #include <linux/file.h>
  29. #include <linux/suspend.h>
  30. #include "cx88.h"
  31. #include "dvb-pll.h"
  32. #include <media/v4l2-common.h>
  33. #include "mt352.h"
  34. #include "mt352_priv.h"
  35. #include "cx88-vp3054-i2c.h"
  36. #include "zl10353.h"
  37. #include "cx22702.h"
  38. #include "or51132.h"
  39. #include "lgdt330x.h"
  40. #include "s5h1409.h"
  41. #include "xc5000.h"
  42. #include "nxt200x.h"
  43. #include "cx24123.h"
  44. #include "isl6421.h"
  45. MODULE_DESCRIPTION("driver for cx2388x based DVB cards");
  46. MODULE_AUTHOR("Chris Pascoe <c.pascoe@itee.uq.edu.au>");
  47. MODULE_AUTHOR("Gerd Knorr <kraxel@bytesex.org> [SuSE Labs]");
  48. MODULE_LICENSE("GPL");
  49. static unsigned int debug = 0;
  50. module_param(debug, int, 0644);
  51. MODULE_PARM_DESC(debug,"enable debug messages [dvb]");
  52. #define dprintk(level,fmt, arg...) if (debug >= level) \
  53. printk(KERN_DEBUG "%s/2-dvb: " fmt, core->name, ## arg)
  54. /* ------------------------------------------------------------------ */
  55. static int dvb_buf_setup(struct videobuf_queue *q,
  56. unsigned int *count, unsigned int *size)
  57. {
  58. struct cx8802_dev *dev = q->priv_data;
  59. dev->ts_packet_size = 188 * 4;
  60. dev->ts_packet_count = 32;
  61. *size = dev->ts_packet_size * dev->ts_packet_count;
  62. *count = 32;
  63. return 0;
  64. }
  65. static int dvb_buf_prepare(struct videobuf_queue *q,
  66. struct videobuf_buffer *vb, enum v4l2_field field)
  67. {
  68. struct cx8802_dev *dev = q->priv_data;
  69. return cx8802_buf_prepare(q, dev, (struct cx88_buffer*)vb,field);
  70. }
  71. static void dvb_buf_queue(struct videobuf_queue *q, struct videobuf_buffer *vb)
  72. {
  73. struct cx8802_dev *dev = q->priv_data;
  74. cx8802_buf_queue(dev, (struct cx88_buffer*)vb);
  75. }
  76. static void dvb_buf_release(struct videobuf_queue *q,
  77. struct videobuf_buffer *vb)
  78. {
  79. cx88_free_buffer(q, (struct cx88_buffer*)vb);
  80. }
  81. static struct videobuf_queue_ops dvb_qops = {
  82. .buf_setup = dvb_buf_setup,
  83. .buf_prepare = dvb_buf_prepare,
  84. .buf_queue = dvb_buf_queue,
  85. .buf_release = dvb_buf_release,
  86. };
  87. /* ------------------------------------------------------------------ */
  88. static int cx88_dvb_bus_ctrl(struct dvb_frontend* fe, int acquire)
  89. {
  90. struct cx8802_dev *dev= fe->dvb->priv;
  91. struct cx8802_driver *drv = NULL;
  92. int ret = 0;
  93. drv = cx8802_get_driver(dev, CX88_MPEG_DVB);
  94. if (drv) {
  95. if (acquire)
  96. ret = drv->request_acquire(drv);
  97. else
  98. ret = drv->request_release(drv);
  99. }
  100. return ret;
  101. }
  102. /* ------------------------------------------------------------------ */
  103. static int dvico_fusionhdtv_demod_init(struct dvb_frontend* fe)
  104. {
  105. static u8 clock_config [] = { CLOCK_CTL, 0x38, 0x39 };
  106. static u8 reset [] = { RESET, 0x80 };
  107. static u8 adc_ctl_1_cfg [] = { ADC_CTL_1, 0x40 };
  108. static u8 agc_cfg [] = { AGC_TARGET, 0x24, 0x20 };
  109. static u8 gpp_ctl_cfg [] = { GPP_CTL, 0x33 };
  110. static u8 capt_range_cfg[] = { CAPT_RANGE, 0x32 };
  111. mt352_write(fe, clock_config, sizeof(clock_config));
  112. udelay(200);
  113. mt352_write(fe, reset, sizeof(reset));
  114. mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg));
  115. mt352_write(fe, agc_cfg, sizeof(agc_cfg));
  116. mt352_write(fe, gpp_ctl_cfg, sizeof(gpp_ctl_cfg));
  117. mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
  118. return 0;
  119. }
  120. static int dvico_dual_demod_init(struct dvb_frontend *fe)
  121. {
  122. static u8 clock_config [] = { CLOCK_CTL, 0x38, 0x38 };
  123. static u8 reset [] = { RESET, 0x80 };
  124. static u8 adc_ctl_1_cfg [] = { ADC_CTL_1, 0x40 };
  125. static u8 agc_cfg [] = { AGC_TARGET, 0x28, 0x20 };
  126. static u8 gpp_ctl_cfg [] = { GPP_CTL, 0x33 };
  127. static u8 capt_range_cfg[] = { CAPT_RANGE, 0x32 };
  128. mt352_write(fe, clock_config, sizeof(clock_config));
  129. udelay(200);
  130. mt352_write(fe, reset, sizeof(reset));
  131. mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg));
  132. mt352_write(fe, agc_cfg, sizeof(agc_cfg));
  133. mt352_write(fe, gpp_ctl_cfg, sizeof(gpp_ctl_cfg));
  134. mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
  135. return 0;
  136. }
  137. static int dntv_live_dvbt_demod_init(struct dvb_frontend* fe)
  138. {
  139. static u8 clock_config [] = { 0x89, 0x38, 0x39 };
  140. static u8 reset [] = { 0x50, 0x80 };
  141. static u8 adc_ctl_1_cfg [] = { 0x8E, 0x40 };
  142. static u8 agc_cfg [] = { 0x67, 0x10, 0x23, 0x00, 0xFF, 0xFF,
  143. 0x00, 0xFF, 0x00, 0x40, 0x40 };
  144. static u8 dntv_extra[] = { 0xB5, 0x7A };
  145. static u8 capt_range_cfg[] = { 0x75, 0x32 };
  146. mt352_write(fe, clock_config, sizeof(clock_config));
  147. udelay(2000);
  148. mt352_write(fe, reset, sizeof(reset));
  149. mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg));
  150. mt352_write(fe, agc_cfg, sizeof(agc_cfg));
  151. udelay(2000);
  152. mt352_write(fe, dntv_extra, sizeof(dntv_extra));
  153. mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
  154. return 0;
  155. }
  156. static struct mt352_config dvico_fusionhdtv = {
  157. .demod_address = 0x0f,
  158. .demod_init = dvico_fusionhdtv_demod_init,
  159. };
  160. static struct mt352_config dntv_live_dvbt_config = {
  161. .demod_address = 0x0f,
  162. .demod_init = dntv_live_dvbt_demod_init,
  163. };
  164. static struct mt352_config dvico_fusionhdtv_dual = {
  165. .demod_address = 0x0f,
  166. .demod_init = dvico_dual_demod_init,
  167. };
  168. #if defined(CONFIG_VIDEO_CX88_VP3054) || (defined(CONFIG_VIDEO_CX88_VP3054_MODULE) && defined(MODULE))
  169. static int dntv_live_dvbt_pro_demod_init(struct dvb_frontend* fe)
  170. {
  171. static u8 clock_config [] = { 0x89, 0x38, 0x38 };
  172. static u8 reset [] = { 0x50, 0x80 };
  173. static u8 adc_ctl_1_cfg [] = { 0x8E, 0x40 };
  174. static u8 agc_cfg [] = { 0x67, 0x10, 0x20, 0x00, 0xFF, 0xFF,
  175. 0x00, 0xFF, 0x00, 0x40, 0x40 };
  176. static u8 dntv_extra[] = { 0xB5, 0x7A };
  177. static u8 capt_range_cfg[] = { 0x75, 0x32 };
  178. mt352_write(fe, clock_config, sizeof(clock_config));
  179. udelay(2000);
  180. mt352_write(fe, reset, sizeof(reset));
  181. mt352_write(fe, adc_ctl_1_cfg, sizeof(adc_ctl_1_cfg));
  182. mt352_write(fe, agc_cfg, sizeof(agc_cfg));
  183. udelay(2000);
  184. mt352_write(fe, dntv_extra, sizeof(dntv_extra));
  185. mt352_write(fe, capt_range_cfg, sizeof(capt_range_cfg));
  186. return 0;
  187. }
  188. static struct mt352_config dntv_live_dvbt_pro_config = {
  189. .demod_address = 0x0f,
  190. .no_tuner = 1,
  191. .demod_init = dntv_live_dvbt_pro_demod_init,
  192. };
  193. #endif
  194. static struct zl10353_config dvico_fusionhdtv_hybrid = {
  195. .demod_address = 0x0f,
  196. .no_tuner = 1,
  197. };
  198. static struct zl10353_config dvico_fusionhdtv_plus_v1_1 = {
  199. .demod_address = 0x0f,
  200. };
  201. static struct cx22702_config connexant_refboard_config = {
  202. .demod_address = 0x43,
  203. .output_mode = CX22702_SERIAL_OUTPUT,
  204. };
  205. static struct cx22702_config hauppauge_hvr_config = {
  206. .demod_address = 0x63,
  207. .output_mode = CX22702_SERIAL_OUTPUT,
  208. };
  209. static int or51132_set_ts_param(struct dvb_frontend* fe, int is_punctured)
  210. {
  211. struct cx8802_dev *dev= fe->dvb->priv;
  212. dev->ts_gen_cntrl = is_punctured ? 0x04 : 0x00;
  213. return 0;
  214. }
  215. static struct or51132_config pchdtv_hd3000 = {
  216. .demod_address = 0x15,
  217. .set_ts_params = or51132_set_ts_param,
  218. };
  219. static int lgdt330x_pll_rf_set(struct dvb_frontend* fe, int index)
  220. {
  221. struct cx8802_dev *dev= fe->dvb->priv;
  222. struct cx88_core *core = dev->core;
  223. dprintk(1, "%s: index = %d\n", __FUNCTION__, index);
  224. if (index == 0)
  225. cx_clear(MO_GP0_IO, 8);
  226. else
  227. cx_set(MO_GP0_IO, 8);
  228. return 0;
  229. }
  230. static int lgdt330x_set_ts_param(struct dvb_frontend* fe, int is_punctured)
  231. {
  232. struct cx8802_dev *dev= fe->dvb->priv;
  233. if (is_punctured)
  234. dev->ts_gen_cntrl |= 0x04;
  235. else
  236. dev->ts_gen_cntrl &= ~0x04;
  237. return 0;
  238. }
  239. static struct lgdt330x_config fusionhdtv_3_gold = {
  240. .demod_address = 0x0e,
  241. .demod_chip = LGDT3302,
  242. .serial_mpeg = 0x04, /* TPSERIAL for 3302 in TOP_CONTROL */
  243. .set_ts_params = lgdt330x_set_ts_param,
  244. };
  245. static struct lgdt330x_config fusionhdtv_5_gold = {
  246. .demod_address = 0x0e,
  247. .demod_chip = LGDT3303,
  248. .serial_mpeg = 0x40, /* TPSERIAL for 3303 in TOP_CONTROL */
  249. .set_ts_params = lgdt330x_set_ts_param,
  250. };
  251. static struct lgdt330x_config pchdtv_hd5500 = {
  252. .demod_address = 0x59,
  253. .demod_chip = LGDT3303,
  254. .serial_mpeg = 0x40, /* TPSERIAL for 3303 in TOP_CONTROL */
  255. .set_ts_params = lgdt330x_set_ts_param,
  256. };
  257. static int nxt200x_set_ts_param(struct dvb_frontend* fe, int is_punctured)
  258. {
  259. struct cx8802_dev *dev= fe->dvb->priv;
  260. dev->ts_gen_cntrl = is_punctured ? 0x04 : 0x00;
  261. return 0;
  262. }
  263. static struct nxt200x_config ati_hdtvwonder = {
  264. .demod_address = 0x0a,
  265. .set_ts_params = nxt200x_set_ts_param,
  266. };
  267. static int cx24123_set_ts_param(struct dvb_frontend* fe,
  268. int is_punctured)
  269. {
  270. struct cx8802_dev *dev= fe->dvb->priv;
  271. dev->ts_gen_cntrl = 0x02;
  272. return 0;
  273. }
  274. static int kworld_dvbs_100_set_voltage(struct dvb_frontend* fe,
  275. fe_sec_voltage_t voltage)
  276. {
  277. struct cx8802_dev *dev= fe->dvb->priv;
  278. struct cx88_core *core = dev->core;
  279. if (voltage == SEC_VOLTAGE_OFF)
  280. cx_write(MO_GP0_IO, 0x000006fb);
  281. else
  282. cx_write(MO_GP0_IO, 0x000006f9);
  283. if (core->prev_set_voltage)
  284. return core->prev_set_voltage(fe, voltage);
  285. return 0;
  286. }
  287. static int geniatech_dvbs_set_voltage(struct dvb_frontend *fe,
  288. fe_sec_voltage_t voltage)
  289. {
  290. struct cx8802_dev *dev= fe->dvb->priv;
  291. struct cx88_core *core = dev->core;
  292. if (voltage == SEC_VOLTAGE_OFF) {
  293. dprintk(1,"LNB Voltage OFF\n");
  294. cx_write(MO_GP0_IO, 0x0000efff);
  295. }
  296. if (core->prev_set_voltage)
  297. return core->prev_set_voltage(fe, voltage);
  298. return 0;
  299. }
  300. static struct cx24123_config geniatech_dvbs_config = {
  301. .demod_address = 0x55,
  302. .set_ts_params = cx24123_set_ts_param,
  303. };
  304. static struct cx24123_config hauppauge_novas_config = {
  305. .demod_address = 0x55,
  306. .set_ts_params = cx24123_set_ts_param,
  307. };
  308. static struct cx24123_config kworld_dvbs_100_config = {
  309. .demod_address = 0x15,
  310. .set_ts_params = cx24123_set_ts_param,
  311. .lnb_polarity = 1,
  312. };
  313. static struct s5h1409_config pinnacle_pctv_hd_800i_config = {
  314. .demod_address = 0x32 >> 1,
  315. .output_mode = S5H1409_PARALLEL_OUTPUT,
  316. .gpio = S5H1409_GPIO_ON,
  317. .qam_if = 44000,
  318. .inversion = S5H1409_INVERSION_OFF,
  319. .status_mode = S5H1409_DEMODLOCKING,
  320. };
  321. static struct xc5000_config pinnacle_pctv_hd_800i_tuner_config = {
  322. .i2c_address = 0x64,
  323. .if_khz = 5380,
  324. .tuner_callback = cx88_tuner_callback,
  325. };
  326. static int dvb_register(struct cx8802_dev *dev)
  327. {
  328. /* init struct videobuf_dvb */
  329. dev->dvb.name = dev->core->name;
  330. dev->ts_gen_cntrl = 0x0c;
  331. /* init frontend */
  332. switch (dev->core->boardnr) {
  333. case CX88_BOARD_HAUPPAUGE_DVB_T1:
  334. dev->dvb.frontend = dvb_attach(cx22702_attach,
  335. &connexant_refboard_config,
  336. &dev->core->i2c_adap);
  337. if (dev->dvb.frontend != NULL) {
  338. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
  339. &dev->core->i2c_adap,
  340. DVB_PLL_THOMSON_DTT759X);
  341. }
  342. break;
  343. case CX88_BOARD_TERRATEC_CINERGY_1400_DVB_T1:
  344. case CX88_BOARD_CONEXANT_DVB_T1:
  345. case CX88_BOARD_KWORLD_DVB_T_CX22702:
  346. case CX88_BOARD_WINFAST_DTV1000:
  347. dev->dvb.frontend = dvb_attach(cx22702_attach,
  348. &connexant_refboard_config,
  349. &dev->core->i2c_adap);
  350. if (dev->dvb.frontend != NULL) {
  351. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x60,
  352. &dev->core->i2c_adap,
  353. DVB_PLL_THOMSON_DTT7579);
  354. }
  355. break;
  356. case CX88_BOARD_WINFAST_DTV2000H:
  357. case CX88_BOARD_HAUPPAUGE_HVR1100:
  358. case CX88_BOARD_HAUPPAUGE_HVR1100LP:
  359. case CX88_BOARD_HAUPPAUGE_HVR1300:
  360. case CX88_BOARD_HAUPPAUGE_HVR3000:
  361. dev->dvb.frontend = dvb_attach(cx22702_attach,
  362. &hauppauge_hvr_config,
  363. &dev->core->i2c_adap);
  364. if (dev->dvb.frontend != NULL) {
  365. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
  366. &dev->core->i2c_adap, DVB_PLL_FMD1216ME);
  367. }
  368. break;
  369. case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_PLUS:
  370. dev->dvb.frontend = dvb_attach(mt352_attach,
  371. &dvico_fusionhdtv,
  372. &dev->core->i2c_adap);
  373. if (dev->dvb.frontend != NULL) {
  374. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x60,
  375. NULL, DVB_PLL_THOMSON_DTT7579);
  376. break;
  377. }
  378. /* ZL10353 replaces MT352 on later cards */
  379. dev->dvb.frontend = dvb_attach(zl10353_attach,
  380. &dvico_fusionhdtv_plus_v1_1,
  381. &dev->core->i2c_adap);
  382. if (dev->dvb.frontend != NULL) {
  383. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x60,
  384. NULL, DVB_PLL_THOMSON_DTT7579);
  385. }
  386. break;
  387. case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL:
  388. /* The tin box says DEE1601, but it seems to be DTT7579
  389. * compatible, with a slightly different MT352 AGC gain. */
  390. dev->dvb.frontend = dvb_attach(mt352_attach,
  391. &dvico_fusionhdtv_dual,
  392. &dev->core->i2c_adap);
  393. if (dev->dvb.frontend != NULL) {
  394. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
  395. NULL, DVB_PLL_THOMSON_DTT7579);
  396. break;
  397. }
  398. /* ZL10353 replaces MT352 on later cards */
  399. dev->dvb.frontend = dvb_attach(zl10353_attach,
  400. &dvico_fusionhdtv_plus_v1_1,
  401. &dev->core->i2c_adap);
  402. if (dev->dvb.frontend != NULL) {
  403. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
  404. NULL, DVB_PLL_THOMSON_DTT7579);
  405. }
  406. break;
  407. case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T1:
  408. dev->dvb.frontend = dvb_attach(mt352_attach,
  409. &dvico_fusionhdtv,
  410. &dev->core->i2c_adap);
  411. if (dev->dvb.frontend != NULL) {
  412. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
  413. NULL, DVB_PLL_LG_Z201);
  414. }
  415. break;
  416. case CX88_BOARD_KWORLD_DVB_T:
  417. case CX88_BOARD_DNTV_LIVE_DVB_T:
  418. case CX88_BOARD_ADSTECH_DVB_T_PCI:
  419. dev->dvb.frontend = dvb_attach(mt352_attach,
  420. &dntv_live_dvbt_config,
  421. &dev->core->i2c_adap);
  422. if (dev->dvb.frontend != NULL) {
  423. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
  424. NULL, DVB_PLL_UNKNOWN_1);
  425. }
  426. break;
  427. case CX88_BOARD_DNTV_LIVE_DVB_T_PRO:
  428. #if defined(CONFIG_VIDEO_CX88_VP3054) || (defined(CONFIG_VIDEO_CX88_VP3054_MODULE) && defined(MODULE))
  429. /* MT352 is on a secondary I2C bus made from some GPIO lines */
  430. dev->dvb.frontend = dvb_attach(mt352_attach, &dntv_live_dvbt_pro_config,
  431. &dev->vp3054->adap);
  432. if (dev->dvb.frontend != NULL) {
  433. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
  434. &dev->core->i2c_adap, DVB_PLL_FMD1216ME);
  435. }
  436. #else
  437. printk(KERN_ERR "%s/2: built without vp3054 support\n", dev->core->name);
  438. #endif
  439. break;
  440. case CX88_BOARD_DVICO_FUSIONHDTV_DVB_T_HYBRID:
  441. dev->dvb.frontend = dvb_attach(zl10353_attach,
  442. &dvico_fusionhdtv_hybrid,
  443. &dev->core->i2c_adap);
  444. if (dev->dvb.frontend != NULL) {
  445. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
  446. &dev->core->i2c_adap,
  447. DVB_PLL_THOMSON_FE6600);
  448. }
  449. break;
  450. case CX88_BOARD_PCHDTV_HD3000:
  451. dev->dvb.frontend = dvb_attach(or51132_attach, &pchdtv_hd3000,
  452. &dev->core->i2c_adap);
  453. if (dev->dvb.frontend != NULL) {
  454. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
  455. &dev->core->i2c_adap,
  456. DVB_PLL_THOMSON_DTT761X);
  457. }
  458. break;
  459. case CX88_BOARD_DVICO_FUSIONHDTV_3_GOLD_Q:
  460. dev->ts_gen_cntrl = 0x08;
  461. {
  462. /* Do a hardware reset of chip before using it. */
  463. struct cx88_core *core = dev->core;
  464. cx_clear(MO_GP0_IO, 1);
  465. mdelay(100);
  466. cx_set(MO_GP0_IO, 1);
  467. mdelay(200);
  468. /* Select RF connector callback */
  469. fusionhdtv_3_gold.pll_rf_set = lgdt330x_pll_rf_set;
  470. dev->dvb.frontend = dvb_attach(lgdt330x_attach,
  471. &fusionhdtv_3_gold,
  472. &dev->core->i2c_adap);
  473. if (dev->dvb.frontend != NULL) {
  474. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
  475. &dev->core->i2c_adap,
  476. DVB_PLL_MICROTUNE_4042);
  477. }
  478. }
  479. break;
  480. case CX88_BOARD_DVICO_FUSIONHDTV_3_GOLD_T:
  481. dev->ts_gen_cntrl = 0x08;
  482. {
  483. /* Do a hardware reset of chip before using it. */
  484. struct cx88_core *core = dev->core;
  485. cx_clear(MO_GP0_IO, 1);
  486. mdelay(100);
  487. cx_set(MO_GP0_IO, 9);
  488. mdelay(200);
  489. dev->dvb.frontend = dvb_attach(lgdt330x_attach,
  490. &fusionhdtv_3_gold,
  491. &dev->core->i2c_adap);
  492. if (dev->dvb.frontend != NULL) {
  493. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
  494. &dev->core->i2c_adap,
  495. DVB_PLL_THOMSON_DTT761X);
  496. }
  497. }
  498. break;
  499. case CX88_BOARD_DVICO_FUSIONHDTV_5_GOLD:
  500. dev->ts_gen_cntrl = 0x08;
  501. {
  502. /* Do a hardware reset of chip before using it. */
  503. struct cx88_core *core = dev->core;
  504. cx_clear(MO_GP0_IO, 1);
  505. mdelay(100);
  506. cx_set(MO_GP0_IO, 1);
  507. mdelay(200);
  508. dev->dvb.frontend = dvb_attach(lgdt330x_attach,
  509. &fusionhdtv_5_gold,
  510. &dev->core->i2c_adap);
  511. if (dev->dvb.frontend != NULL) {
  512. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
  513. &dev->core->i2c_adap,
  514. DVB_PLL_LG_TDVS_H06XF);
  515. }
  516. }
  517. break;
  518. case CX88_BOARD_PCHDTV_HD5500:
  519. dev->ts_gen_cntrl = 0x08;
  520. {
  521. /* Do a hardware reset of chip before using it. */
  522. struct cx88_core *core = dev->core;
  523. cx_clear(MO_GP0_IO, 1);
  524. mdelay(100);
  525. cx_set(MO_GP0_IO, 1);
  526. mdelay(200);
  527. dev->dvb.frontend = dvb_attach(lgdt330x_attach,
  528. &pchdtv_hd5500,
  529. &dev->core->i2c_adap);
  530. if (dev->dvb.frontend != NULL) {
  531. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
  532. &dev->core->i2c_adap,
  533. DVB_PLL_LG_TDVS_H06XF);
  534. }
  535. }
  536. break;
  537. case CX88_BOARD_ATI_HDTVWONDER:
  538. dev->dvb.frontend = dvb_attach(nxt200x_attach,
  539. &ati_hdtvwonder,
  540. &dev->core->i2c_adap);
  541. if (dev->dvb.frontend != NULL) {
  542. dvb_attach(dvb_pll_attach, dev->dvb.frontend, 0x61,
  543. NULL, DVB_PLL_TUV1236D);
  544. }
  545. break;
  546. case CX88_BOARD_HAUPPAUGE_NOVASPLUS_S1:
  547. case CX88_BOARD_HAUPPAUGE_NOVASE2_S1:
  548. dev->dvb.frontend = dvb_attach(cx24123_attach,
  549. &hauppauge_novas_config,
  550. &dev->core->i2c_adap);
  551. if (dev->dvb.frontend) {
  552. dvb_attach(isl6421_attach, dev->dvb.frontend,
  553. &dev->core->i2c_adap, 0x08, 0x00, 0x00);
  554. }
  555. break;
  556. case CX88_BOARD_KWORLD_DVBS_100:
  557. dev->dvb.frontend = dvb_attach(cx24123_attach,
  558. &kworld_dvbs_100_config,
  559. &dev->core->i2c_adap);
  560. if (dev->dvb.frontend) {
  561. dev->core->prev_set_voltage = dev->dvb.frontend->ops.set_voltage;
  562. dev->dvb.frontend->ops.set_voltage = kworld_dvbs_100_set_voltage;
  563. }
  564. break;
  565. case CX88_BOARD_GENIATECH_DVBS:
  566. dev->dvb.frontend = dvb_attach(cx24123_attach,
  567. &geniatech_dvbs_config,
  568. &dev->core->i2c_adap);
  569. if (dev->dvb.frontend) {
  570. dev->core->prev_set_voltage = dev->dvb.frontend->ops.set_voltage;
  571. dev->dvb.frontend->ops.set_voltage = geniatech_dvbs_set_voltage;
  572. }
  573. break;
  574. case CX88_BOARD_PINNACLE_PCTV_HD_800i:
  575. /* Parallel mpeg data port and punctured clock mode */
  576. dev->ts_gen_cntrl = 0x04;
  577. dev->dvb.frontend = dvb_attach(s5h1409_attach,
  578. &pinnacle_pctv_hd_800i_config,
  579. &dev->core->i2c_adap);
  580. if (dev->dvb.frontend != NULL) {
  581. /* tuner_config.video_dev must point to
  582. * i2c_adap.algo_data
  583. */
  584. pinnacle_pctv_hd_800i_tuner_config.priv =
  585. dev->core->i2c_adap.algo_data;
  586. dvb_attach(xc5000_attach, dev->dvb.frontend,
  587. &dev->core->i2c_adap,
  588. &pinnacle_pctv_hd_800i_tuner_config);
  589. }
  590. break;
  591. default:
  592. printk(KERN_ERR "%s/2: The frontend of your DVB/ATSC card isn't supported yet\n",
  593. dev->core->name);
  594. break;
  595. }
  596. if (NULL == dev->dvb.frontend) {
  597. printk(KERN_ERR "%s/2: frontend initialization failed\n", dev->core->name);
  598. return -1;
  599. }
  600. /* Ensure all frontends negotiate bus access */
  601. dev->dvb.frontend->ops.ts_bus_ctrl = cx88_dvb_bus_ctrl;
  602. /* Put the analog decoder in standby to keep it quiet */
  603. cx88_call_i2c_clients (dev->core, TUNER_SET_STANDBY, NULL);
  604. /* register everything */
  605. return videobuf_dvb_register(&dev->dvb, THIS_MODULE, dev, &dev->pci->dev);
  606. }
  607. /* ----------------------------------------------------------- */
  608. /* CX8802 MPEG -> mini driver - We have been given the hardware */
  609. static int cx8802_dvb_advise_acquire(struct cx8802_driver *drv)
  610. {
  611. struct cx88_core *core = drv->core;
  612. int err = 0;
  613. dprintk( 1, "%s\n", __FUNCTION__);
  614. switch (core->boardnr) {
  615. case CX88_BOARD_HAUPPAUGE_HVR1300:
  616. /* We arrive here with either the cx23416 or the cx22702
  617. * on the bus. Take the bus from the cx23416 and enable the
  618. * cx22702 demod
  619. */
  620. cx_set(MO_GP0_IO, 0x00000080); /* cx22702 out of reset and enable */
  621. cx_clear(MO_GP0_IO, 0x00000004);
  622. udelay(1000);
  623. break;
  624. default:
  625. err = -ENODEV;
  626. }
  627. return err;
  628. }
  629. /* CX8802 MPEG -> mini driver - We no longer have the hardware */
  630. static int cx8802_dvb_advise_release(struct cx8802_driver *drv)
  631. {
  632. struct cx88_core *core = drv->core;
  633. int err = 0;
  634. dprintk( 1, "%s\n", __FUNCTION__);
  635. switch (core->boardnr) {
  636. case CX88_BOARD_HAUPPAUGE_HVR1300:
  637. /* Do Nothing, leave the cx22702 on the bus. */
  638. break;
  639. default:
  640. err = -ENODEV;
  641. }
  642. return err;
  643. }
  644. static int cx8802_dvb_probe(struct cx8802_driver *drv)
  645. {
  646. struct cx88_core *core = drv->core;
  647. struct cx8802_dev *dev = drv->core->dvbdev;
  648. int err;
  649. dprintk( 1, "%s\n", __FUNCTION__);
  650. dprintk( 1, " ->being probed by Card=%d Name=%s, PCI %02x:%02x\n",
  651. core->boardnr,
  652. core->name,
  653. core->pci_bus,
  654. core->pci_slot);
  655. err = -ENODEV;
  656. if (!(core->board.mpeg & CX88_MPEG_DVB))
  657. goto fail_core;
  658. /* If vp3054 isn't enabled, a stub will just return 0 */
  659. err = vp3054_i2c_probe(dev);
  660. if (0 != err)
  661. goto fail_core;
  662. /* dvb stuff */
  663. printk(KERN_INFO "%s/2: cx2388x based DVB/ATSC card\n", core->name);
  664. videobuf_queue_pci_init(&dev->dvb.dvbq, &dvb_qops,
  665. dev->pci, &dev->slock,
  666. V4L2_BUF_TYPE_VIDEO_CAPTURE,
  667. V4L2_FIELD_TOP,
  668. sizeof(struct cx88_buffer),
  669. dev);
  670. err = dvb_register(dev);
  671. if (err != 0)
  672. printk(KERN_ERR "%s/2: dvb_register failed (err = %d)\n",
  673. core->name, err);
  674. fail_core:
  675. return err;
  676. }
  677. static int cx8802_dvb_remove(struct cx8802_driver *drv)
  678. {
  679. struct cx8802_dev *dev = drv->core->dvbdev;
  680. /* dvb */
  681. videobuf_dvb_unregister(&dev->dvb);
  682. vp3054_i2c_remove(dev);
  683. return 0;
  684. }
  685. static struct cx8802_driver cx8802_dvb_driver = {
  686. .type_id = CX88_MPEG_DVB,
  687. .hw_access = CX8802_DRVCTL_SHARED,
  688. .probe = cx8802_dvb_probe,
  689. .remove = cx8802_dvb_remove,
  690. .advise_acquire = cx8802_dvb_advise_acquire,
  691. .advise_release = cx8802_dvb_advise_release,
  692. };
  693. static int dvb_init(void)
  694. {
  695. printk(KERN_INFO "cx88/2: cx2388x dvb driver version %d.%d.%d loaded\n",
  696. (CX88_VERSION_CODE >> 16) & 0xff,
  697. (CX88_VERSION_CODE >> 8) & 0xff,
  698. CX88_VERSION_CODE & 0xff);
  699. #ifdef SNAPSHOT
  700. printk(KERN_INFO "cx2388x: snapshot date %04d-%02d-%02d\n",
  701. SNAPSHOT/10000, (SNAPSHOT/100)%100, SNAPSHOT%100);
  702. #endif
  703. return cx8802_register_driver(&cx8802_dvb_driver);
  704. }
  705. static void dvb_fini(void)
  706. {
  707. cx8802_unregister_driver(&cx8802_dvb_driver);
  708. }
  709. module_init(dvb_init);
  710. module_exit(dvb_fini);
  711. /*
  712. * Local variables:
  713. * c-basic-offset: 8
  714. * compile-command: "make DVB=1"
  715. * End:
  716. */