twl4030.c 44 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015101610171018101910201021102210231024102510261027102810291030103110321033103410351036103710381039104010411042104310441045104610471048104910501051105210531054105510561057105810591060106110621063106410651066106710681069107010711072107310741075107610771078107910801081108210831084108510861087108810891090109110921093109410951096109710981099110011011102110311041105110611071108110911101111111211131114111511161117111811191120112111221123112411251126112711281129113011311132113311341135113611371138113911401141114211431144114511461147114811491150115111521153115411551156115711581159116011611162116311641165116611671168116911701171117211731174117511761177117811791180118111821183118411851186118711881189119011911192119311941195119611971198119912001201120212031204120512061207120812091210121112121213121412151216121712181219122012211222122312241225122612271228122912301231123212331234123512361237123812391240124112421243124412451246124712481249125012511252125312541255125612571258125912601261126212631264126512661267126812691270127112721273127412751276127712781279128012811282128312841285128612871288128912901291129212931294129512961297129812991300130113021303130413051306130713081309131013111312131313141315131613171318131913201321132213231324132513261327132813291330133113321333133413351336133713381339134013411342134313441345134613471348134913501351135213531354135513561357135813591360136113621363136413651366136713681369137013711372137313741375137613771378137913801381138213831384138513861387138813891390139113921393139413951396139713981399140014011402140314041405140614071408140914101411141214131414141514161417141814191420142114221423142414251426142714281429143014311432143314341435143614371438143914401441144214431444144514461447144814491450145114521453145414551456145714581459146014611462146314641465146614671468146914701471147214731474147514761477147814791480148114821483148414851486148714881489149014911492149314941495149614971498
  1. /*
  2. * ALSA SoC TWL4030 codec driver
  3. *
  4. * Author: Steve Sakoman, <steve@sakoman.com>
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * version 2 as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  13. * General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  18. * 02110-1301 USA
  19. *
  20. */
  21. #include <linux/module.h>
  22. #include <linux/moduleparam.h>
  23. #include <linux/init.h>
  24. #include <linux/delay.h>
  25. #include <linux/pm.h>
  26. #include <linux/i2c.h>
  27. #include <linux/platform_device.h>
  28. #include <linux/i2c/twl4030.h>
  29. #include <sound/core.h>
  30. #include <sound/pcm.h>
  31. #include <sound/pcm_params.h>
  32. #include <sound/soc.h>
  33. #include <sound/soc-dapm.h>
  34. #include <sound/initval.h>
  35. #include <sound/tlv.h>
  36. #include "twl4030.h"
  37. /*
  38. * twl4030 register cache & default register settings
  39. */
  40. static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
  41. 0x00, /* this register not used */
  42. 0x91, /* REG_CODEC_MODE (0x1) */
  43. 0xc3, /* REG_OPTION (0x2) */
  44. 0x00, /* REG_UNKNOWN (0x3) */
  45. 0x00, /* REG_MICBIAS_CTL (0x4) */
  46. 0x20, /* REG_ANAMICL (0x5) */
  47. 0x00, /* REG_ANAMICR (0x6) */
  48. 0x00, /* REG_AVADC_CTL (0x7) */
  49. 0x00, /* REG_ADCMICSEL (0x8) */
  50. 0x00, /* REG_DIGMIXING (0x9) */
  51. 0x0c, /* REG_ATXL1PGA (0xA) */
  52. 0x0c, /* REG_ATXR1PGA (0xB) */
  53. 0x00, /* REG_AVTXL2PGA (0xC) */
  54. 0x00, /* REG_AVTXR2PGA (0xD) */
  55. 0x01, /* REG_AUDIO_IF (0xE) */
  56. 0x00, /* REG_VOICE_IF (0xF) */
  57. 0x00, /* REG_ARXR1PGA (0x10) */
  58. 0x00, /* REG_ARXL1PGA (0x11) */
  59. 0x6c, /* REG_ARXR2PGA (0x12) */
  60. 0x6c, /* REG_ARXL2PGA (0x13) */
  61. 0x00, /* REG_VRXPGA (0x14) */
  62. 0x00, /* REG_VSTPGA (0x15) */
  63. 0x00, /* REG_VRX2ARXPGA (0x16) */
  64. 0x0c, /* REG_AVDAC_CTL (0x17) */
  65. 0x00, /* REG_ARX2VTXPGA (0x18) */
  66. 0x00, /* REG_ARXL1_APGA_CTL (0x19) */
  67. 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */
  68. 0x4b, /* REG_ARXL2_APGA_CTL (0x1B) */
  69. 0x4b, /* REG_ARXR2_APGA_CTL (0x1C) */
  70. 0x00, /* REG_ATX2ARXPGA (0x1D) */
  71. 0x00, /* REG_BT_IF (0x1E) */
  72. 0x00, /* REG_BTPGA (0x1F) */
  73. 0x00, /* REG_BTSTPGA (0x20) */
  74. 0x00, /* REG_EAR_CTL (0x21) */
  75. 0x24, /* REG_HS_SEL (0x22) */
  76. 0x0a, /* REG_HS_GAIN_SET (0x23) */
  77. 0x00, /* REG_HS_POPN_SET (0x24) */
  78. 0x00, /* REG_PREDL_CTL (0x25) */
  79. 0x00, /* REG_PREDR_CTL (0x26) */
  80. 0x00, /* REG_PRECKL_CTL (0x27) */
  81. 0x00, /* REG_PRECKR_CTL (0x28) */
  82. 0x00, /* REG_HFL_CTL (0x29) */
  83. 0x00, /* REG_HFR_CTL (0x2A) */
  84. 0x00, /* REG_ALC_CTL (0x2B) */
  85. 0x00, /* REG_ALC_SET1 (0x2C) */
  86. 0x00, /* REG_ALC_SET2 (0x2D) */
  87. 0x00, /* REG_BOOST_CTL (0x2E) */
  88. 0x00, /* REG_SOFTVOL_CTL (0x2F) */
  89. 0x00, /* REG_DTMF_FREQSEL (0x30) */
  90. 0x00, /* REG_DTMF_TONEXT1H (0x31) */
  91. 0x00, /* REG_DTMF_TONEXT1L (0x32) */
  92. 0x00, /* REG_DTMF_TONEXT2H (0x33) */
  93. 0x00, /* REG_DTMF_TONEXT2L (0x34) */
  94. 0x00, /* REG_DTMF_TONOFF (0x35) */
  95. 0x00, /* REG_DTMF_WANONOFF (0x36) */
  96. 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
  97. 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
  98. 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
  99. 0x16, /* REG_APLL_CTL (0x3A) */
  100. 0x00, /* REG_DTMF_CTL (0x3B) */
  101. 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */
  102. 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */
  103. 0x00, /* REG_MISC_SET_1 (0x3E) */
  104. 0x00, /* REG_PCMBTMUX (0x3F) */
  105. 0x00, /* not used (0x40) */
  106. 0x00, /* not used (0x41) */
  107. 0x00, /* not used (0x42) */
  108. 0x00, /* REG_RX_PATH_SEL (0x43) */
  109. 0x00, /* REG_VDL_APGA_CTL (0x44) */
  110. 0x00, /* REG_VIBRA_CTL (0x45) */
  111. 0x00, /* REG_VIBRA_SET (0x46) */
  112. 0x00, /* REG_VIBRA_PWM_SET (0x47) */
  113. 0x00, /* REG_ANAMIC_GAIN (0x48) */
  114. 0x00, /* REG_MISC_SET_2 (0x49) */
  115. };
  116. /* codec private data */
  117. struct twl4030_priv {
  118. unsigned int bypass_state;
  119. unsigned int codec_powered;
  120. unsigned int codec_muted;
  121. };
  122. /*
  123. * read twl4030 register cache
  124. */
  125. static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
  126. unsigned int reg)
  127. {
  128. u8 *cache = codec->reg_cache;
  129. if (reg >= TWL4030_CACHEREGNUM)
  130. return -EIO;
  131. return cache[reg];
  132. }
  133. /*
  134. * write twl4030 register cache
  135. */
  136. static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
  137. u8 reg, u8 value)
  138. {
  139. u8 *cache = codec->reg_cache;
  140. if (reg >= TWL4030_CACHEREGNUM)
  141. return;
  142. cache[reg] = value;
  143. }
  144. /*
  145. * write to the twl4030 register space
  146. */
  147. static int twl4030_write(struct snd_soc_codec *codec,
  148. unsigned int reg, unsigned int value)
  149. {
  150. twl4030_write_reg_cache(codec, reg, value);
  151. return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value, reg);
  152. }
  153. static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
  154. {
  155. struct twl4030_priv *twl4030 = codec->private_data;
  156. u8 mode;
  157. if (enable == twl4030->codec_powered)
  158. return;
  159. mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
  160. if (enable)
  161. mode |= TWL4030_CODECPDZ;
  162. else
  163. mode &= ~TWL4030_CODECPDZ;
  164. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  165. twl4030->codec_powered = enable;
  166. /* REVISIT: this delay is present in TI sample drivers */
  167. /* but there seems to be no TRM requirement for it */
  168. udelay(10);
  169. }
  170. static void twl4030_init_chip(struct snd_soc_codec *codec)
  171. {
  172. int i;
  173. /* clear CODECPDZ prior to setting register defaults */
  174. twl4030_codec_enable(codec, 0);
  175. /* set all audio section registers to reasonable defaults */
  176. for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
  177. twl4030_write(codec, i, twl4030_reg[i]);
  178. }
  179. static void twl4030_codec_mute(struct snd_soc_codec *codec, int mute)
  180. {
  181. struct twl4030_priv *twl4030 = codec->private_data;
  182. u8 reg_val;
  183. if (mute == twl4030->codec_muted)
  184. return;
  185. if (mute) {
  186. /* Bypass the reg_cache and mute the volumes
  187. * Headset mute is done in it's own event handler
  188. * Things to mute: Earpiece, PreDrivL/R, CarkitL/R
  189. */
  190. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_EAR_CTL);
  191. twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  192. reg_val & (~TWL4030_EAR_GAIN),
  193. TWL4030_REG_EAR_CTL);
  194. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PREDL_CTL);
  195. twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  196. reg_val & (~TWL4030_PREDL_GAIN),
  197. TWL4030_REG_PREDL_CTL);
  198. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PREDR_CTL);
  199. twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  200. reg_val & (~TWL4030_PREDR_GAIN),
  201. TWL4030_REG_PREDL_CTL);
  202. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PRECKL_CTL);
  203. twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  204. reg_val & (~TWL4030_PRECKL_GAIN),
  205. TWL4030_REG_PRECKL_CTL);
  206. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PRECKR_CTL);
  207. twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  208. reg_val & (~TWL4030_PRECKL_GAIN),
  209. TWL4030_REG_PRECKR_CTL);
  210. /* Disable PLL */
  211. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL);
  212. reg_val &= ~TWL4030_APLL_EN;
  213. twl4030_write(codec, TWL4030_REG_APLL_CTL, reg_val);
  214. } else {
  215. /* Restore the volumes
  216. * Headset mute is done in it's own event handler
  217. * Things to restore: Earpiece, PreDrivL/R, CarkitL/R
  218. */
  219. twl4030_write(codec, TWL4030_REG_EAR_CTL,
  220. twl4030_read_reg_cache(codec, TWL4030_REG_EAR_CTL));
  221. twl4030_write(codec, TWL4030_REG_PREDL_CTL,
  222. twl4030_read_reg_cache(codec, TWL4030_REG_PREDL_CTL));
  223. twl4030_write(codec, TWL4030_REG_PREDR_CTL,
  224. twl4030_read_reg_cache(codec, TWL4030_REG_PREDR_CTL));
  225. twl4030_write(codec, TWL4030_REG_PRECKL_CTL,
  226. twl4030_read_reg_cache(codec, TWL4030_REG_PRECKL_CTL));
  227. twl4030_write(codec, TWL4030_REG_PRECKR_CTL,
  228. twl4030_read_reg_cache(codec, TWL4030_REG_PRECKR_CTL));
  229. /* Enable PLL */
  230. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL);
  231. reg_val |= TWL4030_APLL_EN;
  232. twl4030_write(codec, TWL4030_REG_APLL_CTL, reg_val);
  233. }
  234. twl4030->codec_muted = mute;
  235. }
  236. static void twl4030_power_up(struct snd_soc_codec *codec)
  237. {
  238. struct twl4030_priv *twl4030 = codec->private_data;
  239. u8 anamicl, regmisc1, byte;
  240. int i = 0;
  241. if (twl4030->codec_powered)
  242. return;
  243. /* set CODECPDZ to turn on codec */
  244. twl4030_codec_enable(codec, 1);
  245. /* initiate offset cancellation */
  246. anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
  247. twl4030_write(codec, TWL4030_REG_ANAMICL,
  248. anamicl | TWL4030_CNCL_OFFSET_START);
  249. /* wait for offset cancellation to complete */
  250. do {
  251. /* this takes a little while, so don't slam i2c */
  252. udelay(2000);
  253. twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
  254. TWL4030_REG_ANAMICL);
  255. } while ((i++ < 100) &&
  256. ((byte & TWL4030_CNCL_OFFSET_START) ==
  257. TWL4030_CNCL_OFFSET_START));
  258. /* Make sure that the reg_cache has the same value as the HW */
  259. twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte);
  260. /* anti-pop when changing analog gain */
  261. regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
  262. twl4030_write(codec, TWL4030_REG_MISC_SET_1,
  263. regmisc1 | TWL4030_SMOOTH_ANAVOL_EN);
  264. /* toggle CODECPDZ as per TRM */
  265. twl4030_codec_enable(codec, 0);
  266. twl4030_codec_enable(codec, 1);
  267. }
  268. /*
  269. * Unconditional power down
  270. */
  271. static void twl4030_power_down(struct snd_soc_codec *codec)
  272. {
  273. /* power down */
  274. twl4030_codec_enable(codec, 0);
  275. }
  276. /* Earpiece */
  277. static const char *twl4030_earpiece_texts[] =
  278. {"Off", "DACL1", "DACL2", "DACR1"};
  279. static const unsigned int twl4030_earpiece_values[] =
  280. {0x0, 0x1, 0x2, 0x4};
  281. static const struct soc_enum twl4030_earpiece_enum =
  282. SOC_VALUE_ENUM_SINGLE(TWL4030_REG_EAR_CTL, 1, 0x7,
  283. ARRAY_SIZE(twl4030_earpiece_texts),
  284. twl4030_earpiece_texts,
  285. twl4030_earpiece_values);
  286. static const struct snd_kcontrol_new twl4030_dapm_earpiece_control =
  287. SOC_DAPM_VALUE_ENUM("Route", twl4030_earpiece_enum);
  288. /* PreDrive Left */
  289. static const char *twl4030_predrivel_texts[] =
  290. {"Off", "DACL1", "DACL2", "DACR2"};
  291. static const unsigned int twl4030_predrivel_values[] =
  292. {0x0, 0x1, 0x2, 0x4};
  293. static const struct soc_enum twl4030_predrivel_enum =
  294. SOC_VALUE_ENUM_SINGLE(TWL4030_REG_PREDL_CTL, 1, 0x7,
  295. ARRAY_SIZE(twl4030_predrivel_texts),
  296. twl4030_predrivel_texts,
  297. twl4030_predrivel_values);
  298. static const struct snd_kcontrol_new twl4030_dapm_predrivel_control =
  299. SOC_DAPM_VALUE_ENUM("Route", twl4030_predrivel_enum);
  300. /* PreDrive Right */
  301. static const char *twl4030_predriver_texts[] =
  302. {"Off", "DACR1", "DACR2", "DACL2"};
  303. static const unsigned int twl4030_predriver_values[] =
  304. {0x0, 0x1, 0x2, 0x4};
  305. static const struct soc_enum twl4030_predriver_enum =
  306. SOC_VALUE_ENUM_SINGLE(TWL4030_REG_PREDR_CTL, 1, 0x7,
  307. ARRAY_SIZE(twl4030_predriver_texts),
  308. twl4030_predriver_texts,
  309. twl4030_predriver_values);
  310. static const struct snd_kcontrol_new twl4030_dapm_predriver_control =
  311. SOC_DAPM_VALUE_ENUM("Route", twl4030_predriver_enum);
  312. /* Headset Left */
  313. static const char *twl4030_hsol_texts[] =
  314. {"Off", "DACL1", "DACL2"};
  315. static const struct soc_enum twl4030_hsol_enum =
  316. SOC_ENUM_SINGLE(TWL4030_REG_HS_SEL, 1,
  317. ARRAY_SIZE(twl4030_hsol_texts),
  318. twl4030_hsol_texts);
  319. static const struct snd_kcontrol_new twl4030_dapm_hsol_control =
  320. SOC_DAPM_ENUM("Route", twl4030_hsol_enum);
  321. /* Headset Right */
  322. static const char *twl4030_hsor_texts[] =
  323. {"Off", "DACR1", "DACR2"};
  324. static const struct soc_enum twl4030_hsor_enum =
  325. SOC_ENUM_SINGLE(TWL4030_REG_HS_SEL, 4,
  326. ARRAY_SIZE(twl4030_hsor_texts),
  327. twl4030_hsor_texts);
  328. static const struct snd_kcontrol_new twl4030_dapm_hsor_control =
  329. SOC_DAPM_ENUM("Route", twl4030_hsor_enum);
  330. /* Carkit Left */
  331. static const char *twl4030_carkitl_texts[] =
  332. {"Off", "DACL1", "DACL2"};
  333. static const struct soc_enum twl4030_carkitl_enum =
  334. SOC_ENUM_SINGLE(TWL4030_REG_PRECKL_CTL, 1,
  335. ARRAY_SIZE(twl4030_carkitl_texts),
  336. twl4030_carkitl_texts);
  337. static const struct snd_kcontrol_new twl4030_dapm_carkitl_control =
  338. SOC_DAPM_ENUM("Route", twl4030_carkitl_enum);
  339. /* Carkit Right */
  340. static const char *twl4030_carkitr_texts[] =
  341. {"Off", "DACR1", "DACR2"};
  342. static const struct soc_enum twl4030_carkitr_enum =
  343. SOC_ENUM_SINGLE(TWL4030_REG_PRECKR_CTL, 1,
  344. ARRAY_SIZE(twl4030_carkitr_texts),
  345. twl4030_carkitr_texts);
  346. static const struct snd_kcontrol_new twl4030_dapm_carkitr_control =
  347. SOC_DAPM_ENUM("Route", twl4030_carkitr_enum);
  348. /* Handsfree Left */
  349. static const char *twl4030_handsfreel_texts[] =
  350. {"Voice", "DACL1", "DACL2", "DACR2"};
  351. static const struct soc_enum twl4030_handsfreel_enum =
  352. SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
  353. ARRAY_SIZE(twl4030_handsfreel_texts),
  354. twl4030_handsfreel_texts);
  355. static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
  356. SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
  357. /* Handsfree Right */
  358. static const char *twl4030_handsfreer_texts[] =
  359. {"Voice", "DACR1", "DACR2", "DACL2"};
  360. static const struct soc_enum twl4030_handsfreer_enum =
  361. SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
  362. ARRAY_SIZE(twl4030_handsfreer_texts),
  363. twl4030_handsfreer_texts);
  364. static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
  365. SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
  366. /* Left analog microphone selection */
  367. static const char *twl4030_analoglmic_texts[] =
  368. {"Off", "Main mic", "Headset mic", "AUXL", "Carkit mic"};
  369. static const unsigned int twl4030_analoglmic_values[] =
  370. {0x0, 0x1, 0x2, 0x4, 0x8};
  371. static const struct soc_enum twl4030_analoglmic_enum =
  372. SOC_VALUE_ENUM_SINGLE(TWL4030_REG_ANAMICL, 0, 0xf,
  373. ARRAY_SIZE(twl4030_analoglmic_texts),
  374. twl4030_analoglmic_texts,
  375. twl4030_analoglmic_values);
  376. static const struct snd_kcontrol_new twl4030_dapm_analoglmic_control =
  377. SOC_DAPM_VALUE_ENUM("Route", twl4030_analoglmic_enum);
  378. /* Right analog microphone selection */
  379. static const char *twl4030_analogrmic_texts[] =
  380. {"Off", "Sub mic", "AUXR"};
  381. static const unsigned int twl4030_analogrmic_values[] =
  382. {0x0, 0x1, 0x4};
  383. static const struct soc_enum twl4030_analogrmic_enum =
  384. SOC_VALUE_ENUM_SINGLE(TWL4030_REG_ANAMICR, 0, 0x5,
  385. ARRAY_SIZE(twl4030_analogrmic_texts),
  386. twl4030_analogrmic_texts,
  387. twl4030_analogrmic_values);
  388. static const struct snd_kcontrol_new twl4030_dapm_analogrmic_control =
  389. SOC_DAPM_VALUE_ENUM("Route", twl4030_analogrmic_enum);
  390. /* TX1 L/R Analog/Digital microphone selection */
  391. static const char *twl4030_micpathtx1_texts[] =
  392. {"Analog", "Digimic0"};
  393. static const struct soc_enum twl4030_micpathtx1_enum =
  394. SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
  395. ARRAY_SIZE(twl4030_micpathtx1_texts),
  396. twl4030_micpathtx1_texts);
  397. static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
  398. SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
  399. /* TX2 L/R Analog/Digital microphone selection */
  400. static const char *twl4030_micpathtx2_texts[] =
  401. {"Analog", "Digimic1"};
  402. static const struct soc_enum twl4030_micpathtx2_enum =
  403. SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
  404. ARRAY_SIZE(twl4030_micpathtx2_texts),
  405. twl4030_micpathtx2_texts);
  406. static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
  407. SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
  408. /* Analog bypass for AudioR1 */
  409. static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control =
  410. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0);
  411. /* Analog bypass for AudioL1 */
  412. static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control =
  413. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0);
  414. /* Analog bypass for AudioR2 */
  415. static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control =
  416. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0);
  417. /* Analog bypass for AudioL2 */
  418. static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control =
  419. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0);
  420. static int micpath_event(struct snd_soc_dapm_widget *w,
  421. struct snd_kcontrol *kcontrol, int event)
  422. {
  423. struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
  424. unsigned char adcmicsel, micbias_ctl;
  425. adcmicsel = twl4030_read_reg_cache(w->codec, TWL4030_REG_ADCMICSEL);
  426. micbias_ctl = twl4030_read_reg_cache(w->codec, TWL4030_REG_MICBIAS_CTL);
  427. /* Prepare the bits for the given TX path:
  428. * shift_l == 0: TX1 microphone path
  429. * shift_l == 2: TX2 microphone path */
  430. if (e->shift_l) {
  431. /* TX2 microphone path */
  432. if (adcmicsel & TWL4030_TX2IN_SEL)
  433. micbias_ctl |= TWL4030_MICBIAS2_CTL; /* digimic */
  434. else
  435. micbias_ctl &= ~TWL4030_MICBIAS2_CTL;
  436. } else {
  437. /* TX1 microphone path */
  438. if (adcmicsel & TWL4030_TX1IN_SEL)
  439. micbias_ctl |= TWL4030_MICBIAS1_CTL; /* digimic */
  440. else
  441. micbias_ctl &= ~TWL4030_MICBIAS1_CTL;
  442. }
  443. twl4030_write(w->codec, TWL4030_REG_MICBIAS_CTL, micbias_ctl);
  444. return 0;
  445. }
  446. static int handsfree_event(struct snd_soc_dapm_widget *w,
  447. struct snd_kcontrol *kcontrol, int event)
  448. {
  449. struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
  450. unsigned char hs_ctl;
  451. hs_ctl = twl4030_read_reg_cache(w->codec, e->reg);
  452. if (hs_ctl & TWL4030_HF_CTL_REF_EN) {
  453. hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
  454. twl4030_write(w->codec, e->reg, hs_ctl);
  455. hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
  456. twl4030_write(w->codec, e->reg, hs_ctl);
  457. hs_ctl |= TWL4030_HF_CTL_HB_EN;
  458. twl4030_write(w->codec, e->reg, hs_ctl);
  459. } else {
  460. hs_ctl &= ~(TWL4030_HF_CTL_RAMP_EN | TWL4030_HF_CTL_LOOP_EN
  461. | TWL4030_HF_CTL_HB_EN);
  462. twl4030_write(w->codec, e->reg, hs_ctl);
  463. }
  464. return 0;
  465. }
  466. static int headsetl_event(struct snd_soc_dapm_widget *w,
  467. struct snd_kcontrol *kcontrol, int event)
  468. {
  469. unsigned char hs_gain, hs_pop;
  470. /* Save the current volume */
  471. hs_gain = twl4030_read_reg_cache(w->codec, TWL4030_REG_HS_GAIN_SET);
  472. switch (event) {
  473. case SND_SOC_DAPM_POST_PMU:
  474. /* Do the anti-pop/bias ramp enable according to the TRM */
  475. hs_pop = TWL4030_RAMP_DELAY_645MS;
  476. twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  477. hs_pop |= TWL4030_VMID_EN;
  478. twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  479. /* Is this needed? Can we just use whatever gain here? */
  480. twl4030_write(w->codec, TWL4030_REG_HS_GAIN_SET,
  481. (hs_gain & (~0x0f)) | 0x0a);
  482. hs_pop |= TWL4030_RAMP_EN;
  483. twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  484. /* Restore the original volume */
  485. twl4030_write(w->codec, TWL4030_REG_HS_GAIN_SET, hs_gain);
  486. break;
  487. case SND_SOC_DAPM_POST_PMD:
  488. /* Do the anti-pop/bias ramp disable according to the TRM */
  489. hs_pop = twl4030_read_reg_cache(w->codec,
  490. TWL4030_REG_HS_POPN_SET);
  491. hs_pop &= ~TWL4030_RAMP_EN;
  492. twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  493. /* Bypass the reg_cache to mute the headset */
  494. twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  495. hs_gain & (~0x0f),
  496. TWL4030_REG_HS_GAIN_SET);
  497. hs_pop &= ~TWL4030_VMID_EN;
  498. twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  499. break;
  500. }
  501. return 0;
  502. }
  503. static int bypass_event(struct snd_soc_dapm_widget *w,
  504. struct snd_kcontrol *kcontrol, int event)
  505. {
  506. struct soc_mixer_control *m =
  507. (struct soc_mixer_control *)w->kcontrols->private_value;
  508. struct twl4030_priv *twl4030 = w->codec->private_data;
  509. unsigned char reg;
  510. reg = twl4030_read_reg_cache(w->codec, m->reg);
  511. if (reg & (1 << m->shift))
  512. twl4030->bypass_state |=
  513. (1 << (m->reg - TWL4030_REG_ARXL1_APGA_CTL));
  514. else
  515. twl4030->bypass_state &=
  516. ~(1 << (m->reg - TWL4030_REG_ARXL1_APGA_CTL));
  517. if (w->codec->bias_level == SND_SOC_BIAS_STANDBY) {
  518. if (twl4030->bypass_state)
  519. twl4030_codec_mute(w->codec, 0);
  520. else
  521. twl4030_codec_mute(w->codec, 1);
  522. }
  523. return 0;
  524. }
  525. /*
  526. * Some of the gain controls in TWL (mostly those which are associated with
  527. * the outputs) are implemented in an interesting way:
  528. * 0x0 : Power down (mute)
  529. * 0x1 : 6dB
  530. * 0x2 : 0 dB
  531. * 0x3 : -6 dB
  532. * Inverting not going to help with these.
  533. * Custom volsw and volsw_2r get/put functions to handle these gain bits.
  534. */
  535. #define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
  536. xinvert, tlv_array) \
  537. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
  538. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  539. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  540. .tlv.p = (tlv_array), \
  541. .info = snd_soc_info_volsw, \
  542. .get = snd_soc_get_volsw_twl4030, \
  543. .put = snd_soc_put_volsw_twl4030, \
  544. .private_value = (unsigned long)&(struct soc_mixer_control) \
  545. {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
  546. .max = xmax, .invert = xinvert} }
  547. #define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
  548. xinvert, tlv_array) \
  549. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
  550. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  551. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  552. .tlv.p = (tlv_array), \
  553. .info = snd_soc_info_volsw_2r, \
  554. .get = snd_soc_get_volsw_r2_twl4030,\
  555. .put = snd_soc_put_volsw_r2_twl4030, \
  556. .private_value = (unsigned long)&(struct soc_mixer_control) \
  557. {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
  558. .rshift = xshift, .max = xmax, .invert = xinvert} }
  559. #define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
  560. SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
  561. xinvert, tlv_array)
  562. static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
  563. struct snd_ctl_elem_value *ucontrol)
  564. {
  565. struct soc_mixer_control *mc =
  566. (struct soc_mixer_control *)kcontrol->private_value;
  567. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  568. unsigned int reg = mc->reg;
  569. unsigned int shift = mc->shift;
  570. unsigned int rshift = mc->rshift;
  571. int max = mc->max;
  572. int mask = (1 << fls(max)) - 1;
  573. ucontrol->value.integer.value[0] =
  574. (snd_soc_read(codec, reg) >> shift) & mask;
  575. if (ucontrol->value.integer.value[0])
  576. ucontrol->value.integer.value[0] =
  577. max + 1 - ucontrol->value.integer.value[0];
  578. if (shift != rshift) {
  579. ucontrol->value.integer.value[1] =
  580. (snd_soc_read(codec, reg) >> rshift) & mask;
  581. if (ucontrol->value.integer.value[1])
  582. ucontrol->value.integer.value[1] =
  583. max + 1 - ucontrol->value.integer.value[1];
  584. }
  585. return 0;
  586. }
  587. static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
  588. struct snd_ctl_elem_value *ucontrol)
  589. {
  590. struct soc_mixer_control *mc =
  591. (struct soc_mixer_control *)kcontrol->private_value;
  592. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  593. unsigned int reg = mc->reg;
  594. unsigned int shift = mc->shift;
  595. unsigned int rshift = mc->rshift;
  596. int max = mc->max;
  597. int mask = (1 << fls(max)) - 1;
  598. unsigned short val, val2, val_mask;
  599. val = (ucontrol->value.integer.value[0] & mask);
  600. val_mask = mask << shift;
  601. if (val)
  602. val = max + 1 - val;
  603. val = val << shift;
  604. if (shift != rshift) {
  605. val2 = (ucontrol->value.integer.value[1] & mask);
  606. val_mask |= mask << rshift;
  607. if (val2)
  608. val2 = max + 1 - val2;
  609. val |= val2 << rshift;
  610. }
  611. return snd_soc_update_bits(codec, reg, val_mask, val);
  612. }
  613. static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
  614. struct snd_ctl_elem_value *ucontrol)
  615. {
  616. struct soc_mixer_control *mc =
  617. (struct soc_mixer_control *)kcontrol->private_value;
  618. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  619. unsigned int reg = mc->reg;
  620. unsigned int reg2 = mc->rreg;
  621. unsigned int shift = mc->shift;
  622. int max = mc->max;
  623. int mask = (1<<fls(max))-1;
  624. ucontrol->value.integer.value[0] =
  625. (snd_soc_read(codec, reg) >> shift) & mask;
  626. ucontrol->value.integer.value[1] =
  627. (snd_soc_read(codec, reg2) >> shift) & mask;
  628. if (ucontrol->value.integer.value[0])
  629. ucontrol->value.integer.value[0] =
  630. max + 1 - ucontrol->value.integer.value[0];
  631. if (ucontrol->value.integer.value[1])
  632. ucontrol->value.integer.value[1] =
  633. max + 1 - ucontrol->value.integer.value[1];
  634. return 0;
  635. }
  636. static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
  637. struct snd_ctl_elem_value *ucontrol)
  638. {
  639. struct soc_mixer_control *mc =
  640. (struct soc_mixer_control *)kcontrol->private_value;
  641. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  642. unsigned int reg = mc->reg;
  643. unsigned int reg2 = mc->rreg;
  644. unsigned int shift = mc->shift;
  645. int max = mc->max;
  646. int mask = (1 << fls(max)) - 1;
  647. int err;
  648. unsigned short val, val2, val_mask;
  649. val_mask = mask << shift;
  650. val = (ucontrol->value.integer.value[0] & mask);
  651. val2 = (ucontrol->value.integer.value[1] & mask);
  652. if (val)
  653. val = max + 1 - val;
  654. if (val2)
  655. val2 = max + 1 - val2;
  656. val = val << shift;
  657. val2 = val2 << shift;
  658. err = snd_soc_update_bits(codec, reg, val_mask, val);
  659. if (err < 0)
  660. return err;
  661. err = snd_soc_update_bits(codec, reg2, val_mask, val2);
  662. return err;
  663. }
  664. /*
  665. * FGAIN volume control:
  666. * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
  667. */
  668. static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
  669. /*
  670. * CGAIN volume control:
  671. * 0 dB to 12 dB in 6 dB steps
  672. * value 2 and 3 means 12 dB
  673. */
  674. static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
  675. /*
  676. * Analog playback gain
  677. * -24 dB to 12 dB in 2 dB steps
  678. */
  679. static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
  680. /*
  681. * Gain controls tied to outputs
  682. * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
  683. */
  684. static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
  685. /*
  686. * Capture gain after the ADCs
  687. * from 0 dB to 31 dB in 1 dB steps
  688. */
  689. static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
  690. /*
  691. * Gain control for input amplifiers
  692. * 0 dB to 30 dB in 6 dB steps
  693. */
  694. static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
  695. static const struct snd_kcontrol_new twl4030_snd_controls[] = {
  696. /* Common playback gain controls */
  697. SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
  698. TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
  699. 0, 0x3f, 0, digital_fine_tlv),
  700. SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
  701. TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
  702. 0, 0x3f, 0, digital_fine_tlv),
  703. SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
  704. TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
  705. 6, 0x2, 0, digital_coarse_tlv),
  706. SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
  707. TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
  708. 6, 0x2, 0, digital_coarse_tlv),
  709. SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
  710. TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
  711. 3, 0x12, 1, analog_tlv),
  712. SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
  713. TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
  714. 3, 0x12, 1, analog_tlv),
  715. SOC_DOUBLE_R("DAC1 Analog Playback Switch",
  716. TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
  717. 1, 1, 0),
  718. SOC_DOUBLE_R("DAC2 Analog Playback Switch",
  719. TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
  720. 1, 1, 0),
  721. /* Separate output gain controls */
  722. SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
  723. TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
  724. 4, 3, 0, output_tvl),
  725. SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
  726. TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
  727. SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
  728. TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
  729. 4, 3, 0, output_tvl),
  730. SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
  731. TWL4030_REG_EAR_CTL, 4, 3, 0, output_tvl),
  732. /* Common capture gain controls */
  733. SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
  734. TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
  735. 0, 0x1f, 0, digital_capture_tlv),
  736. SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
  737. TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
  738. 0, 0x1f, 0, digital_capture_tlv),
  739. SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
  740. 0, 3, 5, 0, input_gain_tlv),
  741. };
  742. static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
  743. /* Left channel inputs */
  744. SND_SOC_DAPM_INPUT("MAINMIC"),
  745. SND_SOC_DAPM_INPUT("HSMIC"),
  746. SND_SOC_DAPM_INPUT("AUXL"),
  747. SND_SOC_DAPM_INPUT("CARKITMIC"),
  748. /* Right channel inputs */
  749. SND_SOC_DAPM_INPUT("SUBMIC"),
  750. SND_SOC_DAPM_INPUT("AUXR"),
  751. /* Digital microphones (Stereo) */
  752. SND_SOC_DAPM_INPUT("DIGIMIC0"),
  753. SND_SOC_DAPM_INPUT("DIGIMIC1"),
  754. /* Outputs */
  755. SND_SOC_DAPM_OUTPUT("OUTL"),
  756. SND_SOC_DAPM_OUTPUT("OUTR"),
  757. SND_SOC_DAPM_OUTPUT("EARPIECE"),
  758. SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
  759. SND_SOC_DAPM_OUTPUT("PREDRIVER"),
  760. SND_SOC_DAPM_OUTPUT("HSOL"),
  761. SND_SOC_DAPM_OUTPUT("HSOR"),
  762. SND_SOC_DAPM_OUTPUT("CARKITL"),
  763. SND_SOC_DAPM_OUTPUT("CARKITR"),
  764. SND_SOC_DAPM_OUTPUT("HFL"),
  765. SND_SOC_DAPM_OUTPUT("HFR"),
  766. /* DACs */
  767. SND_SOC_DAPM_DAC("DAC Right1", "Right Front Playback",
  768. SND_SOC_NOPM, 0, 0),
  769. SND_SOC_DAPM_DAC("DAC Left1", "Left Front Playback",
  770. SND_SOC_NOPM, 0, 0),
  771. SND_SOC_DAPM_DAC("DAC Right2", "Right Rear Playback",
  772. SND_SOC_NOPM, 0, 0),
  773. SND_SOC_DAPM_DAC("DAC Left2", "Left Rear Playback",
  774. SND_SOC_NOPM, 0, 0),
  775. /* Analog PGAs */
  776. SND_SOC_DAPM_PGA("ARXR1_APGA", TWL4030_REG_ARXR1_APGA_CTL,
  777. 0, 0, NULL, 0),
  778. SND_SOC_DAPM_PGA("ARXL1_APGA", TWL4030_REG_ARXL1_APGA_CTL,
  779. 0, 0, NULL, 0),
  780. SND_SOC_DAPM_PGA("ARXR2_APGA", TWL4030_REG_ARXR2_APGA_CTL,
  781. 0, 0, NULL, 0),
  782. SND_SOC_DAPM_PGA("ARXL2_APGA", TWL4030_REG_ARXL2_APGA_CTL,
  783. 0, 0, NULL, 0),
  784. /* Analog bypasses */
  785. SND_SOC_DAPM_SWITCH_E("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,
  786. &twl4030_dapm_abypassr1_control, bypass_event,
  787. SND_SOC_DAPM_POST_REG),
  788. SND_SOC_DAPM_SWITCH_E("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0,
  789. &twl4030_dapm_abypassl1_control,
  790. bypass_event, SND_SOC_DAPM_POST_REG),
  791. SND_SOC_DAPM_SWITCH_E("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0,
  792. &twl4030_dapm_abypassr2_control,
  793. bypass_event, SND_SOC_DAPM_POST_REG),
  794. SND_SOC_DAPM_SWITCH_E("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0,
  795. &twl4030_dapm_abypassl2_control,
  796. bypass_event, SND_SOC_DAPM_POST_REG),
  797. SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer", TWL4030_REG_AVDAC_CTL,
  798. 0, 0, NULL, 0),
  799. SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer", TWL4030_REG_AVDAC_CTL,
  800. 1, 0, NULL, 0),
  801. SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer", TWL4030_REG_AVDAC_CTL,
  802. 2, 0, NULL, 0),
  803. SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer", TWL4030_REG_AVDAC_CTL,
  804. 3, 0, NULL, 0),
  805. /* Output MUX controls */
  806. /* Earpiece */
  807. SND_SOC_DAPM_VALUE_MUX("Earpiece Mux", SND_SOC_NOPM, 0, 0,
  808. &twl4030_dapm_earpiece_control),
  809. /* PreDrivL/R */
  810. SND_SOC_DAPM_VALUE_MUX("PredriveL Mux", SND_SOC_NOPM, 0, 0,
  811. &twl4030_dapm_predrivel_control),
  812. SND_SOC_DAPM_VALUE_MUX("PredriveR Mux", SND_SOC_NOPM, 0, 0,
  813. &twl4030_dapm_predriver_control),
  814. /* HeadsetL/R */
  815. SND_SOC_DAPM_MUX_E("HeadsetL Mux", SND_SOC_NOPM, 0, 0,
  816. &twl4030_dapm_hsol_control, headsetl_event,
  817. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  818. SND_SOC_DAPM_MUX("HeadsetR Mux", SND_SOC_NOPM, 0, 0,
  819. &twl4030_dapm_hsor_control),
  820. /* CarkitL/R */
  821. SND_SOC_DAPM_MUX("CarkitL Mux", SND_SOC_NOPM, 0, 0,
  822. &twl4030_dapm_carkitl_control),
  823. SND_SOC_DAPM_MUX("CarkitR Mux", SND_SOC_NOPM, 0, 0,
  824. &twl4030_dapm_carkitr_control),
  825. /* HandsfreeL/R */
  826. SND_SOC_DAPM_MUX_E("HandsfreeL Mux", TWL4030_REG_HFL_CTL, 5, 0,
  827. &twl4030_dapm_handsfreel_control, handsfree_event,
  828. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  829. SND_SOC_DAPM_MUX_E("HandsfreeR Mux", TWL4030_REG_HFR_CTL, 5, 0,
  830. &twl4030_dapm_handsfreer_control, handsfree_event,
  831. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  832. /* Introducing four virtual ADC, since TWL4030 have four channel for
  833. capture */
  834. SND_SOC_DAPM_ADC("ADC Virtual Left1", "Left Front Capture",
  835. SND_SOC_NOPM, 0, 0),
  836. SND_SOC_DAPM_ADC("ADC Virtual Right1", "Right Front Capture",
  837. SND_SOC_NOPM, 0, 0),
  838. SND_SOC_DAPM_ADC("ADC Virtual Left2", "Left Rear Capture",
  839. SND_SOC_NOPM, 0, 0),
  840. SND_SOC_DAPM_ADC("ADC Virtual Right2", "Right Rear Capture",
  841. SND_SOC_NOPM, 0, 0),
  842. /* Analog/Digital mic path selection.
  843. TX1 Left/Right: either analog Left/Right or Digimic0
  844. TX2 Left/Right: either analog Left/Right or Digimic1 */
  845. SND_SOC_DAPM_MUX_E("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
  846. &twl4030_dapm_micpathtx1_control, micpath_event,
  847. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
  848. SND_SOC_DAPM_POST_REG),
  849. SND_SOC_DAPM_MUX_E("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
  850. &twl4030_dapm_micpathtx2_control, micpath_event,
  851. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
  852. SND_SOC_DAPM_POST_REG),
  853. /* Analog input muxes with switch for the capture amplifiers */
  854. SND_SOC_DAPM_VALUE_MUX("Analog Left Capture Route",
  855. TWL4030_REG_ANAMICL, 4, 0, &twl4030_dapm_analoglmic_control),
  856. SND_SOC_DAPM_VALUE_MUX("Analog Right Capture Route",
  857. TWL4030_REG_ANAMICR, 4, 0, &twl4030_dapm_analogrmic_control),
  858. SND_SOC_DAPM_PGA("ADC Physical Left",
  859. TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),
  860. SND_SOC_DAPM_PGA("ADC Physical Right",
  861. TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0),
  862. SND_SOC_DAPM_PGA("Digimic0 Enable",
  863. TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0),
  864. SND_SOC_DAPM_PGA("Digimic1 Enable",
  865. TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0),
  866. SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0),
  867. SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0),
  868. SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0),
  869. };
  870. static const struct snd_soc_dapm_route intercon[] = {
  871. {"Analog L1 Playback Mixer", NULL, "DAC Left1"},
  872. {"Analog R1 Playback Mixer", NULL, "DAC Right1"},
  873. {"Analog L2 Playback Mixer", NULL, "DAC Left2"},
  874. {"Analog R2 Playback Mixer", NULL, "DAC Right2"},
  875. {"ARXL1_APGA", NULL, "Analog L1 Playback Mixer"},
  876. {"ARXR1_APGA", NULL, "Analog R1 Playback Mixer"},
  877. {"ARXL2_APGA", NULL, "Analog L2 Playback Mixer"},
  878. {"ARXR2_APGA", NULL, "Analog R2 Playback Mixer"},
  879. /* Internal playback routings */
  880. /* Earpiece */
  881. {"Earpiece Mux", "DACL1", "ARXL1_APGA"},
  882. {"Earpiece Mux", "DACL2", "ARXL2_APGA"},
  883. {"Earpiece Mux", "DACR1", "ARXR1_APGA"},
  884. /* PreDrivL */
  885. {"PredriveL Mux", "DACL1", "ARXL1_APGA"},
  886. {"PredriveL Mux", "DACL2", "ARXL2_APGA"},
  887. {"PredriveL Mux", "DACR2", "ARXR2_APGA"},
  888. /* PreDrivR */
  889. {"PredriveR Mux", "DACR1", "ARXR1_APGA"},
  890. {"PredriveR Mux", "DACR2", "ARXR2_APGA"},
  891. {"PredriveR Mux", "DACL2", "ARXL2_APGA"},
  892. /* HeadsetL */
  893. {"HeadsetL Mux", "DACL1", "ARXL1_APGA"},
  894. {"HeadsetL Mux", "DACL2", "ARXL2_APGA"},
  895. /* HeadsetR */
  896. {"HeadsetR Mux", "DACR1", "ARXR1_APGA"},
  897. {"HeadsetR Mux", "DACR2", "ARXR2_APGA"},
  898. /* CarkitL */
  899. {"CarkitL Mux", "DACL1", "ARXL1_APGA"},
  900. {"CarkitL Mux", "DACL2", "ARXL2_APGA"},
  901. /* CarkitR */
  902. {"CarkitR Mux", "DACR1", "ARXR1_APGA"},
  903. {"CarkitR Mux", "DACR2", "ARXR2_APGA"},
  904. /* HandsfreeL */
  905. {"HandsfreeL Mux", "DACL1", "ARXL1_APGA"},
  906. {"HandsfreeL Mux", "DACL2", "ARXL2_APGA"},
  907. {"HandsfreeL Mux", "DACR2", "ARXR2_APGA"},
  908. /* HandsfreeR */
  909. {"HandsfreeR Mux", "DACR1", "ARXR1_APGA"},
  910. {"HandsfreeR Mux", "DACR2", "ARXR2_APGA"},
  911. {"HandsfreeR Mux", "DACL2", "ARXL2_APGA"},
  912. /* outputs */
  913. {"OUTL", NULL, "ARXL2_APGA"},
  914. {"OUTR", NULL, "ARXR2_APGA"},
  915. {"EARPIECE", NULL, "Earpiece Mux"},
  916. {"PREDRIVEL", NULL, "PredriveL Mux"},
  917. {"PREDRIVER", NULL, "PredriveR Mux"},
  918. {"HSOL", NULL, "HeadsetL Mux"},
  919. {"HSOR", NULL, "HeadsetR Mux"},
  920. {"CARKITL", NULL, "CarkitL Mux"},
  921. {"CARKITR", NULL, "CarkitR Mux"},
  922. {"HFL", NULL, "HandsfreeL Mux"},
  923. {"HFR", NULL, "HandsfreeR Mux"},
  924. /* Capture path */
  925. {"Analog Left Capture Route", "Main mic", "MAINMIC"},
  926. {"Analog Left Capture Route", "Headset mic", "HSMIC"},
  927. {"Analog Left Capture Route", "AUXL", "AUXL"},
  928. {"Analog Left Capture Route", "Carkit mic", "CARKITMIC"},
  929. {"Analog Right Capture Route", "Sub mic", "SUBMIC"},
  930. {"Analog Right Capture Route", "AUXR", "AUXR"},
  931. {"ADC Physical Left", NULL, "Analog Left Capture Route"},
  932. {"ADC Physical Right", NULL, "Analog Right Capture Route"},
  933. {"Digimic0 Enable", NULL, "DIGIMIC0"},
  934. {"Digimic1 Enable", NULL, "DIGIMIC1"},
  935. /* TX1 Left capture path */
  936. {"TX1 Capture Route", "Analog", "ADC Physical Left"},
  937. {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
  938. /* TX1 Right capture path */
  939. {"TX1 Capture Route", "Analog", "ADC Physical Right"},
  940. {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
  941. /* TX2 Left capture path */
  942. {"TX2 Capture Route", "Analog", "ADC Physical Left"},
  943. {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
  944. /* TX2 Right capture path */
  945. {"TX2 Capture Route", "Analog", "ADC Physical Right"},
  946. {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
  947. {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
  948. {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
  949. {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
  950. {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
  951. /* Analog bypass routes */
  952. {"Right1 Analog Loopback", "Switch", "Analog Right Capture Route"},
  953. {"Left1 Analog Loopback", "Switch", "Analog Left Capture Route"},
  954. {"Right2 Analog Loopback", "Switch", "Analog Right Capture Route"},
  955. {"Left2 Analog Loopback", "Switch", "Analog Left Capture Route"},
  956. {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},
  957. {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"},
  958. {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},
  959. {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},
  960. };
  961. static int twl4030_add_widgets(struct snd_soc_codec *codec)
  962. {
  963. snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
  964. ARRAY_SIZE(twl4030_dapm_widgets));
  965. snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
  966. snd_soc_dapm_new_widgets(codec);
  967. return 0;
  968. }
  969. static int twl4030_set_bias_level(struct snd_soc_codec *codec,
  970. enum snd_soc_bias_level level)
  971. {
  972. struct twl4030_priv *twl4030 = codec->private_data;
  973. switch (level) {
  974. case SND_SOC_BIAS_ON:
  975. twl4030_codec_mute(codec, 0);
  976. break;
  977. case SND_SOC_BIAS_PREPARE:
  978. twl4030_power_up(codec);
  979. if (twl4030->bypass_state)
  980. twl4030_codec_mute(codec, 0);
  981. else
  982. twl4030_codec_mute(codec, 1);
  983. break;
  984. case SND_SOC_BIAS_STANDBY:
  985. twl4030_power_up(codec);
  986. if (twl4030->bypass_state)
  987. twl4030_codec_mute(codec, 0);
  988. else
  989. twl4030_codec_mute(codec, 1);
  990. break;
  991. case SND_SOC_BIAS_OFF:
  992. twl4030_power_down(codec);
  993. break;
  994. }
  995. codec->bias_level = level;
  996. return 0;
  997. }
  998. static int twl4030_hw_params(struct snd_pcm_substream *substream,
  999. struct snd_pcm_hw_params *params,
  1000. struct snd_soc_dai *dai)
  1001. {
  1002. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1003. struct snd_soc_device *socdev = rtd->socdev;
  1004. struct snd_soc_codec *codec = socdev->card->codec;
  1005. u8 mode, old_mode, format, old_format;
  1006. /* bit rate */
  1007. old_mode = twl4030_read_reg_cache(codec,
  1008. TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
  1009. mode = old_mode & ~TWL4030_APLL_RATE;
  1010. switch (params_rate(params)) {
  1011. case 8000:
  1012. mode |= TWL4030_APLL_RATE_8000;
  1013. break;
  1014. case 11025:
  1015. mode |= TWL4030_APLL_RATE_11025;
  1016. break;
  1017. case 12000:
  1018. mode |= TWL4030_APLL_RATE_12000;
  1019. break;
  1020. case 16000:
  1021. mode |= TWL4030_APLL_RATE_16000;
  1022. break;
  1023. case 22050:
  1024. mode |= TWL4030_APLL_RATE_22050;
  1025. break;
  1026. case 24000:
  1027. mode |= TWL4030_APLL_RATE_24000;
  1028. break;
  1029. case 32000:
  1030. mode |= TWL4030_APLL_RATE_32000;
  1031. break;
  1032. case 44100:
  1033. mode |= TWL4030_APLL_RATE_44100;
  1034. break;
  1035. case 48000:
  1036. mode |= TWL4030_APLL_RATE_48000;
  1037. break;
  1038. default:
  1039. printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
  1040. params_rate(params));
  1041. return -EINVAL;
  1042. }
  1043. if (mode != old_mode) {
  1044. /* change rate and set CODECPDZ */
  1045. twl4030_codec_enable(codec, 0);
  1046. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  1047. twl4030_codec_enable(codec, 1);
  1048. }
  1049. /* sample size */
  1050. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1051. format = old_format;
  1052. format &= ~TWL4030_DATA_WIDTH;
  1053. switch (params_format(params)) {
  1054. case SNDRV_PCM_FORMAT_S16_LE:
  1055. format |= TWL4030_DATA_WIDTH_16S_16W;
  1056. break;
  1057. case SNDRV_PCM_FORMAT_S24_LE:
  1058. format |= TWL4030_DATA_WIDTH_32S_24W;
  1059. break;
  1060. default:
  1061. printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
  1062. params_format(params));
  1063. return -EINVAL;
  1064. }
  1065. if (format != old_format) {
  1066. /* clear CODECPDZ before changing format (codec requirement) */
  1067. twl4030_codec_enable(codec, 0);
  1068. /* change format */
  1069. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  1070. /* set CODECPDZ afterwards */
  1071. twl4030_codec_enable(codec, 1);
  1072. }
  1073. return 0;
  1074. }
  1075. static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  1076. int clk_id, unsigned int freq, int dir)
  1077. {
  1078. struct snd_soc_codec *codec = codec_dai->codec;
  1079. u8 infreq;
  1080. switch (freq) {
  1081. case 19200000:
  1082. infreq = TWL4030_APLL_INFREQ_19200KHZ;
  1083. break;
  1084. case 26000000:
  1085. infreq = TWL4030_APLL_INFREQ_26000KHZ;
  1086. break;
  1087. case 38400000:
  1088. infreq = TWL4030_APLL_INFREQ_38400KHZ;
  1089. break;
  1090. default:
  1091. printk(KERN_ERR "TWL4030 set sysclk: unknown rate %d\n",
  1092. freq);
  1093. return -EINVAL;
  1094. }
  1095. infreq |= TWL4030_APLL_EN;
  1096. twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
  1097. return 0;
  1098. }
  1099. static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
  1100. unsigned int fmt)
  1101. {
  1102. struct snd_soc_codec *codec = codec_dai->codec;
  1103. u8 old_format, format;
  1104. /* get format */
  1105. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1106. format = old_format;
  1107. /* set master/slave audio interface */
  1108. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1109. case SND_SOC_DAIFMT_CBM_CFM:
  1110. format &= ~(TWL4030_AIF_SLAVE_EN);
  1111. format &= ~(TWL4030_CLK256FS_EN);
  1112. break;
  1113. case SND_SOC_DAIFMT_CBS_CFS:
  1114. format |= TWL4030_AIF_SLAVE_EN;
  1115. format |= TWL4030_CLK256FS_EN;
  1116. break;
  1117. default:
  1118. return -EINVAL;
  1119. }
  1120. /* interface format */
  1121. format &= ~TWL4030_AIF_FORMAT;
  1122. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  1123. case SND_SOC_DAIFMT_I2S:
  1124. format |= TWL4030_AIF_FORMAT_CODEC;
  1125. break;
  1126. default:
  1127. return -EINVAL;
  1128. }
  1129. if (format != old_format) {
  1130. /* clear CODECPDZ before changing format (codec requirement) */
  1131. twl4030_codec_enable(codec, 0);
  1132. /* change format */
  1133. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  1134. /* set CODECPDZ afterwards */
  1135. twl4030_codec_enable(codec, 1);
  1136. }
  1137. return 0;
  1138. }
  1139. #define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
  1140. #define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
  1141. struct snd_soc_dai twl4030_dai = {
  1142. .name = "twl4030",
  1143. .playback = {
  1144. .stream_name = "Playback",
  1145. .channels_min = 2,
  1146. .channels_max = 2,
  1147. .rates = TWL4030_RATES,
  1148. .formats = TWL4030_FORMATS,},
  1149. .capture = {
  1150. .stream_name = "Capture",
  1151. .channels_min = 2,
  1152. .channels_max = 2,
  1153. .rates = TWL4030_RATES,
  1154. .formats = TWL4030_FORMATS,},
  1155. .ops = {
  1156. .hw_params = twl4030_hw_params,
  1157. .set_sysclk = twl4030_set_dai_sysclk,
  1158. .set_fmt = twl4030_set_dai_fmt,
  1159. }
  1160. };
  1161. EXPORT_SYMBOL_GPL(twl4030_dai);
  1162. static int twl4030_suspend(struct platform_device *pdev, pm_message_t state)
  1163. {
  1164. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1165. struct snd_soc_codec *codec = socdev->card->codec;
  1166. twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
  1167. return 0;
  1168. }
  1169. static int twl4030_resume(struct platform_device *pdev)
  1170. {
  1171. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1172. struct snd_soc_codec *codec = socdev->card->codec;
  1173. twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  1174. twl4030_set_bias_level(codec, codec->suspend_bias_level);
  1175. return 0;
  1176. }
  1177. /*
  1178. * initialize the driver
  1179. * register the mixer and dsp interfaces with the kernel
  1180. */
  1181. static int twl4030_init(struct snd_soc_device *socdev)
  1182. {
  1183. struct snd_soc_codec *codec = socdev->card->codec;
  1184. int ret = 0;
  1185. printk(KERN_INFO "TWL4030 Audio Codec init \n");
  1186. codec->name = "twl4030";
  1187. codec->owner = THIS_MODULE;
  1188. codec->read = twl4030_read_reg_cache;
  1189. codec->write = twl4030_write;
  1190. codec->set_bias_level = twl4030_set_bias_level;
  1191. codec->dai = &twl4030_dai;
  1192. codec->num_dai = 1;
  1193. codec->reg_cache_size = sizeof(twl4030_reg);
  1194. codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
  1195. GFP_KERNEL);
  1196. if (codec->reg_cache == NULL)
  1197. return -ENOMEM;
  1198. /* register pcms */
  1199. ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
  1200. if (ret < 0) {
  1201. printk(KERN_ERR "twl4030: failed to create pcms\n");
  1202. goto pcm_err;
  1203. }
  1204. twl4030_init_chip(codec);
  1205. /* power on device */
  1206. twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  1207. snd_soc_add_controls(codec, twl4030_snd_controls,
  1208. ARRAY_SIZE(twl4030_snd_controls));
  1209. twl4030_add_widgets(codec);
  1210. ret = snd_soc_init_card(socdev);
  1211. if (ret < 0) {
  1212. printk(KERN_ERR "twl4030: failed to register card\n");
  1213. goto card_err;
  1214. }
  1215. return ret;
  1216. card_err:
  1217. snd_soc_free_pcms(socdev);
  1218. snd_soc_dapm_free(socdev);
  1219. pcm_err:
  1220. kfree(codec->reg_cache);
  1221. return ret;
  1222. }
  1223. static struct snd_soc_device *twl4030_socdev;
  1224. static int twl4030_probe(struct platform_device *pdev)
  1225. {
  1226. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1227. struct snd_soc_codec *codec;
  1228. struct twl4030_priv *twl4030;
  1229. codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
  1230. if (codec == NULL)
  1231. return -ENOMEM;
  1232. twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL);
  1233. if (twl4030 == NULL) {
  1234. kfree(codec);
  1235. return -ENOMEM;
  1236. }
  1237. codec->private_data = twl4030;
  1238. socdev->card->codec = codec;
  1239. mutex_init(&codec->mutex);
  1240. INIT_LIST_HEAD(&codec->dapm_widgets);
  1241. INIT_LIST_HEAD(&codec->dapm_paths);
  1242. twl4030_socdev = socdev;
  1243. twl4030_init(socdev);
  1244. return 0;
  1245. }
  1246. static int twl4030_remove(struct platform_device *pdev)
  1247. {
  1248. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1249. struct snd_soc_codec *codec = socdev->card->codec;
  1250. printk(KERN_INFO "TWL4030 Audio Codec remove\n");
  1251. twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
  1252. snd_soc_free_pcms(socdev);
  1253. snd_soc_dapm_free(socdev);
  1254. kfree(codec->private_data);
  1255. kfree(codec);
  1256. return 0;
  1257. }
  1258. struct snd_soc_codec_device soc_codec_dev_twl4030 = {
  1259. .probe = twl4030_probe,
  1260. .remove = twl4030_remove,
  1261. .suspend = twl4030_suspend,
  1262. .resume = twl4030_resume,
  1263. };
  1264. EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
  1265. static int __init twl4030_modinit(void)
  1266. {
  1267. return snd_soc_register_dai(&twl4030_dai);
  1268. }
  1269. module_init(twl4030_modinit);
  1270. static void __exit twl4030_exit(void)
  1271. {
  1272. snd_soc_unregister_dai(&twl4030_dai);
  1273. }
  1274. module_exit(twl4030_exit);
  1275. MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
  1276. MODULE_AUTHOR("Steve Sakoman");
  1277. MODULE_LICENSE("GPL");