ab8500-gpadc.c 24 KB

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  1. /*
  2. * Copyright (C) ST-Ericsson SA 2010
  3. *
  4. * License Terms: GNU General Public License v2
  5. * Author: Arun R Murthy <arun.murthy@stericsson.com>
  6. * Author: Daniel Willerud <daniel.willerud@stericsson.com>
  7. * Author: Johan Palsson <johan.palsson@stericsson.com>
  8. */
  9. #include <linux/init.h>
  10. #include <linux/module.h>
  11. #include <linux/device.h>
  12. #include <linux/interrupt.h>
  13. #include <linux/spinlock.h>
  14. #include <linux/delay.h>
  15. #include <linux/pm_runtime.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/completion.h>
  18. #include <linux/regulator/consumer.h>
  19. #include <linux/err.h>
  20. #include <linux/slab.h>
  21. #include <linux/list.h>
  22. #include <linux/mfd/abx500.h>
  23. #include <linux/mfd/abx500/ab8500.h>
  24. #include <linux/mfd/abx500/ab8500-gpadc.h>
  25. /*
  26. * GPADC register offsets
  27. * Bank : 0x0A
  28. */
  29. #define AB8500_GPADC_CTRL1_REG 0x00
  30. #define AB8500_GPADC_CTRL2_REG 0x01
  31. #define AB8500_GPADC_CTRL3_REG 0x02
  32. #define AB8500_GPADC_AUTO_TIMER_REG 0x03
  33. #define AB8500_GPADC_STAT_REG 0x04
  34. #define AB8500_GPADC_MANDATAL_REG 0x05
  35. #define AB8500_GPADC_MANDATAH_REG 0x06
  36. #define AB8500_GPADC_AUTODATAL_REG 0x07
  37. #define AB8500_GPADC_AUTODATAH_REG 0x08
  38. #define AB8500_GPADC_MUX_CTRL_REG 0x09
  39. /*
  40. * OTP register offsets
  41. * Bank : 0x15
  42. */
  43. #define AB8500_GPADC_CAL_1 0x0F
  44. #define AB8500_GPADC_CAL_2 0x10
  45. #define AB8500_GPADC_CAL_3 0x11
  46. #define AB8500_GPADC_CAL_4 0x12
  47. #define AB8500_GPADC_CAL_5 0x13
  48. #define AB8500_GPADC_CAL_6 0x14
  49. #define AB8500_GPADC_CAL_7 0x15
  50. /* gpadc constants */
  51. #define EN_VINTCORE12 0x04
  52. #define EN_VTVOUT 0x02
  53. #define EN_GPADC 0x01
  54. #define DIS_GPADC 0x00
  55. #define AVG_1 0x00
  56. #define AVG_4 0x20
  57. #define AVG_8 0x40
  58. #define AVG_16 0x60
  59. #define ADC_SW_CONV 0x04
  60. #define EN_ICHAR 0x80
  61. #define BTEMP_PULL_UP 0x08
  62. #define EN_BUF 0x40
  63. #define DIS_ZERO 0x00
  64. #define GPADC_BUSY 0x01
  65. #define EN_FALLING 0x10
  66. #define EN_TRIG_EDGE 0x02
  67. /* GPADC constants from AB8500 spec, UM0836 */
  68. #define ADC_RESOLUTION 1024
  69. #define ADC_CH_BTEMP_MIN 0
  70. #define ADC_CH_BTEMP_MAX 1350
  71. #define ADC_CH_DIETEMP_MIN 0
  72. #define ADC_CH_DIETEMP_MAX 1350
  73. #define ADC_CH_CHG_V_MIN 0
  74. #define ADC_CH_CHG_V_MAX 20030
  75. #define ADC_CH_ACCDET2_MIN 0
  76. #define ADC_CH_ACCDET2_MAX 2500
  77. #define ADC_CH_VBAT_MIN 2300
  78. #define ADC_CH_VBAT_MAX 4800
  79. #define ADC_CH_CHG_I_MIN 0
  80. #define ADC_CH_CHG_I_MAX 1500
  81. #define ADC_CH_BKBAT_MIN 0
  82. #define ADC_CH_BKBAT_MAX 3200
  83. /* This is used to not lose precision when dividing to get gain and offset */
  84. #define CALIB_SCALE 1000
  85. /* Time in ms before disabling regulator */
  86. #define GPADC_AUDOSUSPEND_DELAY 1
  87. #define CONVERSION_TIME 500 /* ms */
  88. enum cal_channels {
  89. ADC_INPUT_VMAIN = 0,
  90. ADC_INPUT_BTEMP,
  91. ADC_INPUT_VBAT,
  92. NBR_CAL_INPUTS,
  93. };
  94. /**
  95. * struct adc_cal_data - Table for storing gain and offset for the calibrated
  96. * ADC channels
  97. * @gain: Gain of the ADC channel
  98. * @offset: Offset of the ADC channel
  99. */
  100. struct adc_cal_data {
  101. u64 gain;
  102. u64 offset;
  103. };
  104. /**
  105. * struct ab8500_gpadc - AB8500 GPADC device information
  106. * @dev: pointer to the struct device
  107. * @node: a list of AB8500 GPADCs, hence prepared for
  108. reentrance
  109. * @parent: pointer to the struct ab8500
  110. * @ab8500_gpadc_complete: pointer to the struct completion, to indicate
  111. * the completion of gpadc conversion
  112. * @ab8500_gpadc_lock: structure of type mutex
  113. * @regu: pointer to the struct regulator
  114. * @irq_sw: interrupt number that is used by gpadc for Sw
  115. * conversion
  116. * @irq_hw: interrupt number that is used by gpadc for Hw
  117. * conversion
  118. * @cal_data array of ADC calibration data structs
  119. */
  120. struct ab8500_gpadc {
  121. struct device *dev;
  122. struct list_head node;
  123. struct ab8500 *parent;
  124. struct completion ab8500_gpadc_complete;
  125. struct mutex ab8500_gpadc_lock;
  126. struct regulator *regu;
  127. int irq_sw;
  128. int irq_hw;
  129. struct adc_cal_data cal_data[NBR_CAL_INPUTS];
  130. };
  131. static LIST_HEAD(ab8500_gpadc_list);
  132. /**
  133. * ab8500_gpadc_get() - returns a reference to the primary AB8500 GPADC
  134. * (i.e. the first GPADC in the instance list)
  135. */
  136. struct ab8500_gpadc *ab8500_gpadc_get(char *name)
  137. {
  138. struct ab8500_gpadc *gpadc;
  139. list_for_each_entry(gpadc, &ab8500_gpadc_list, node) {
  140. if (!strcmp(name, dev_name(gpadc->dev)))
  141. return gpadc;
  142. }
  143. return ERR_PTR(-ENOENT);
  144. }
  145. EXPORT_SYMBOL(ab8500_gpadc_get);
  146. /**
  147. * ab8500_gpadc_ad_to_voltage() - Convert a raw ADC value to a voltage
  148. */
  149. int ab8500_gpadc_ad_to_voltage(struct ab8500_gpadc *gpadc, u8 channel,
  150. int ad_value)
  151. {
  152. int res;
  153. switch (channel) {
  154. case MAIN_CHARGER_V:
  155. /* For some reason we don't have calibrated data */
  156. if (!gpadc->cal_data[ADC_INPUT_VMAIN].gain) {
  157. res = ADC_CH_CHG_V_MIN + (ADC_CH_CHG_V_MAX -
  158. ADC_CH_CHG_V_MIN) * ad_value /
  159. ADC_RESOLUTION;
  160. break;
  161. }
  162. /* Here we can use the calibrated data */
  163. res = (int) (ad_value * gpadc->cal_data[ADC_INPUT_VMAIN].gain +
  164. gpadc->cal_data[ADC_INPUT_VMAIN].offset) / CALIB_SCALE;
  165. break;
  166. case BAT_CTRL:
  167. case BTEMP_BALL:
  168. case ACC_DETECT1:
  169. case ADC_AUX1:
  170. case ADC_AUX2:
  171. /* For some reason we don't have calibrated data */
  172. if (!gpadc->cal_data[ADC_INPUT_BTEMP].gain) {
  173. res = ADC_CH_BTEMP_MIN + (ADC_CH_BTEMP_MAX -
  174. ADC_CH_BTEMP_MIN) * ad_value /
  175. ADC_RESOLUTION;
  176. break;
  177. }
  178. /* Here we can use the calibrated data */
  179. res = (int) (ad_value * gpadc->cal_data[ADC_INPUT_BTEMP].gain +
  180. gpadc->cal_data[ADC_INPUT_BTEMP].offset) / CALIB_SCALE;
  181. break;
  182. case MAIN_BAT_V:
  183. /* For some reason we don't have calibrated data */
  184. if (!gpadc->cal_data[ADC_INPUT_VBAT].gain) {
  185. res = ADC_CH_VBAT_MIN + (ADC_CH_VBAT_MAX -
  186. ADC_CH_VBAT_MIN) * ad_value /
  187. ADC_RESOLUTION;
  188. break;
  189. }
  190. /* Here we can use the calibrated data */
  191. res = (int) (ad_value * gpadc->cal_data[ADC_INPUT_VBAT].gain +
  192. gpadc->cal_data[ADC_INPUT_VBAT].offset) / CALIB_SCALE;
  193. break;
  194. case DIE_TEMP:
  195. res = ADC_CH_DIETEMP_MIN +
  196. (ADC_CH_DIETEMP_MAX - ADC_CH_DIETEMP_MIN) * ad_value /
  197. ADC_RESOLUTION;
  198. break;
  199. case ACC_DETECT2:
  200. res = ADC_CH_ACCDET2_MIN +
  201. (ADC_CH_ACCDET2_MAX - ADC_CH_ACCDET2_MIN) * ad_value /
  202. ADC_RESOLUTION;
  203. break;
  204. case VBUS_V:
  205. res = ADC_CH_CHG_V_MIN +
  206. (ADC_CH_CHG_V_MAX - ADC_CH_CHG_V_MIN) * ad_value /
  207. ADC_RESOLUTION;
  208. break;
  209. case MAIN_CHARGER_C:
  210. case USB_CHARGER_C:
  211. res = ADC_CH_CHG_I_MIN +
  212. (ADC_CH_CHG_I_MAX - ADC_CH_CHG_I_MIN) * ad_value /
  213. ADC_RESOLUTION;
  214. break;
  215. case BK_BAT_V:
  216. res = ADC_CH_BKBAT_MIN +
  217. (ADC_CH_BKBAT_MAX - ADC_CH_BKBAT_MIN) * ad_value /
  218. ADC_RESOLUTION;
  219. break;
  220. default:
  221. dev_err(gpadc->dev,
  222. "unknown channel, not possible to convert\n");
  223. res = -EINVAL;
  224. break;
  225. }
  226. return res;
  227. }
  228. EXPORT_SYMBOL(ab8500_gpadc_ad_to_voltage);
  229. /**
  230. * ab8500_gpadc_sw_hw_convert() - gpadc conversion
  231. * @channel: analog channel to be converted to digital data
  232. * @avg_sample: number of ADC sample to average
  233. * @trig_egde: selected ADC trig edge
  234. * @trig_timer: selected ADC trigger delay timer
  235. * @conv_type: selected conversion type (HW or SW conversion)
  236. *
  237. * This function converts the selected analog i/p to digital
  238. * data.
  239. */
  240. int ab8500_gpadc_sw_hw_convert(struct ab8500_gpadc *gpadc, u8 channel,
  241. u8 avg_sample, u8 trig_edge, u8 trig_timer, u8 conv_type)
  242. {
  243. int ad_value;
  244. int voltage;
  245. ad_value = ab8500_gpadc_read_raw(gpadc, channel, avg_sample,
  246. trig_edge, trig_timer, conv_type);
  247. /* On failure retry a second time */
  248. if (ad_value < 0)
  249. ad_value = ab8500_gpadc_read_raw(gpadc, channel, avg_sample,
  250. trig_edge, trig_timer, conv_type);
  251. if (ad_value < 0) {
  252. dev_err(gpadc->dev, "GPADC raw value failed ch: %d\n",
  253. channel);
  254. return ad_value;
  255. }
  256. voltage = ab8500_gpadc_ad_to_voltage(gpadc, channel, ad_value);
  257. if (voltage < 0)
  258. dev_err(gpadc->dev, "GPADC to voltage conversion failed ch:"
  259. " %d AD: 0x%x\n", channel, ad_value);
  260. return voltage;
  261. }
  262. EXPORT_SYMBOL(ab8500_gpadc_convert);
  263. /**
  264. * ab8500_gpadc_read_raw() - gpadc read
  265. * @channel: analog channel to be read
  266. * @avg_sample: number of ADC sample to average
  267. * @trig_edge: selected trig edge
  268. * @trig_timer: selected ADC trigger delay timer
  269. * @conv_type: selected conversion type (HW or SW conversion)
  270. *
  271. * This function obtains the raw ADC value for an hardware conversion,
  272. * this then needs to be converted by calling ab8500_gpadc_ad_to_voltage()
  273. */
  274. int ab8500_gpadc_read_raw(struct ab8500_gpadc *gpadc, u8 channel,
  275. u8 avg_sample, u8 trig_edge, u8 trig_timer, u8 conv_type)
  276. {
  277. int ret;
  278. int looplimit = 0;
  279. u8 val, low_data, high_data;
  280. if (!gpadc)
  281. return -ENODEV;
  282. mutex_lock(&gpadc->ab8500_gpadc_lock);
  283. /* Enable VTVout LDO this is required for GPADC */
  284. pm_runtime_get_sync(gpadc->dev);
  285. /* Check if ADC is not busy, lock and proceed */
  286. do {
  287. ret = abx500_get_register_interruptible(gpadc->dev,
  288. AB8500_GPADC, AB8500_GPADC_STAT_REG, &val);
  289. if (ret < 0)
  290. goto out;
  291. if (!(val & GPADC_BUSY))
  292. break;
  293. msleep(10);
  294. } while (++looplimit < 10);
  295. if (looplimit >= 10 && (val & GPADC_BUSY)) {
  296. dev_err(gpadc->dev, "gpadc_conversion: GPADC busy");
  297. ret = -EINVAL;
  298. goto out;
  299. }
  300. /* Enable GPADC */
  301. ret = abx500_mask_and_set_register_interruptible(gpadc->dev,
  302. AB8500_GPADC, AB8500_GPADC_CTRL1_REG, EN_GPADC, EN_GPADC);
  303. if (ret < 0) {
  304. dev_err(gpadc->dev, "gpadc_conversion: enable gpadc failed\n");
  305. goto out;
  306. }
  307. /* Select the channel source and set average samples */
  308. switch (avg_sample) {
  309. case SAMPLE_1:
  310. val = channel | AVG_1;
  311. break;
  312. case SAMPLE_4:
  313. val = channel | AVG_4;
  314. break;
  315. case SAMPLE_8:
  316. val = channel | AVG_8;
  317. break;
  318. default:
  319. val = channel | AVG_16;
  320. break;
  321. }
  322. if (conv_type == ADC_HW)
  323. ret = abx500_set_register_interruptible(gpadc->dev,
  324. AB8500_GPADC, AB8500_GPADC_CTRL3_REG, val);
  325. else
  326. ret = abx500_set_register_interruptible(gpadc->dev,
  327. AB8500_GPADC, AB8500_GPADC_CTRL2_REG, val);
  328. if (ret < 0) {
  329. dev_err(gpadc->dev,
  330. "gpadc_conversion: set avg samples failed\n");
  331. goto out;
  332. }
  333. /*
  334. * Enable ADC, buffering, select rising edge and enable ADC path
  335. * charging current sense if it needed, ABB 3.0 needs some special
  336. * treatment too.
  337. */
  338. if ((conv_type == ADC_HW) && (trig_edge)) {
  339. ret = abx500_mask_and_set_register_interruptible(gpadc->dev,
  340. AB8500_GPADC, AB8500_GPADC_CTRL1_REG,
  341. EN_FALLING, EN_FALLING);
  342. }
  343. switch (channel) {
  344. case MAIN_CHARGER_C:
  345. case USB_CHARGER_C:
  346. if (conv_type == ADC_HW)
  347. ret = abx500_mask_and_set_register_interruptible(
  348. gpadc->dev,
  349. AB8500_GPADC, AB8500_GPADC_CTRL1_REG,
  350. EN_BUF | EN_ICHAR | EN_TRIG_EDGE,
  351. EN_BUF | EN_ICHAR | EN_TRIG_EDGE);
  352. else
  353. ret = abx500_mask_and_set_register_interruptible(
  354. gpadc->dev,
  355. AB8500_GPADC, AB8500_GPADC_CTRL1_REG,
  356. EN_BUF | EN_ICHAR,
  357. EN_BUF | EN_ICHAR);
  358. break;
  359. case BTEMP_BALL:
  360. if (!is_ab8500_2p0_or_earlier(gpadc->parent)) {
  361. if (conv_type == ADC_HW)
  362. /* Turn on btemp pull-up on ABB 3.0 */
  363. ret = abx500_mask_and_set_register_interruptible
  364. (gpadc->dev,
  365. AB8500_GPADC, AB8500_GPADC_CTRL1_REG,
  366. EN_BUF | BTEMP_PULL_UP | EN_TRIG_EDGE,
  367. EN_BUF | BTEMP_PULL_UP | EN_TRIG_EDGE);
  368. else
  369. ret = abx500_mask_and_set_register_interruptible
  370. (gpadc->dev,
  371. AB8500_GPADC, AB8500_GPADC_CTRL1_REG,
  372. EN_BUF | BTEMP_PULL_UP,
  373. EN_BUF | BTEMP_PULL_UP);
  374. /*
  375. * Delay might be needed for ABB8500 cut 3.0, if not, remove
  376. * when hardware will be available
  377. */
  378. usleep_range(1000, 1000);
  379. break;
  380. }
  381. /* Intentional fallthrough */
  382. default:
  383. if (conv_type == ADC_HW)
  384. ret = abx500_mask_and_set_register_interruptible(
  385. gpadc->dev,
  386. AB8500_GPADC, AB8500_GPADC_CTRL1_REG,
  387. EN_BUF | EN_TRIG_EDGE,
  388. EN_BUF | EN_TRIG_EDGE);
  389. else
  390. ret = abx500_mask_and_set_register_interruptible(
  391. gpadc->dev,
  392. AB8500_GPADC,
  393. AB8500_GPADC_CTRL1_REG, EN_BUF, EN_BUF);
  394. break;
  395. }
  396. if (ret < 0) {
  397. dev_err(gpadc->dev,
  398. "gpadc_conversion: select falling edge failed\n");
  399. goto out;
  400. }
  401. /* Set trigger delay timer */
  402. if (conv_type == ADC_HW) {
  403. ret = abx500_set_register_interruptible(gpadc->dev,
  404. AB8500_GPADC, AB8500_GPADC_AUTO_TIMER_REG, trig_timer);
  405. if (ret < 0) {
  406. dev_err(gpadc->dev,
  407. "gpadc_conversion: trig timer failed\n");
  408. goto out;
  409. }
  410. }
  411. /* Start SW conversion */
  412. if (conv_type == ADC_SW) {
  413. ret = abx500_mask_and_set_register_interruptible(gpadc->dev,
  414. AB8500_GPADC, AB8500_GPADC_CTRL1_REG,
  415. ADC_SW_CONV, ADC_SW_CONV);
  416. if (ret < 0) {
  417. dev_err(gpadc->dev,
  418. "gpadc_conversion: start s/w conv failed\n");
  419. goto out;
  420. }
  421. }
  422. /* wait for completion of conversion */
  423. if (conv_type == ADC_HW) {
  424. if (!wait_for_completion_timeout(&gpadc->ab8500_gpadc_complete,
  425. 2*HZ)) {
  426. dev_err(gpadc->dev,
  427. "timeout didn't receive"
  428. " hw GPADC conv interrupt\n");
  429. ret = -EINVAL;
  430. goto out;
  431. }
  432. } else {
  433. if (!wait_for_completion_timeout(&gpadc->ab8500_gpadc_complete,
  434. msecs_to_jiffies(CONVERSION_TIME))) {
  435. dev_err(gpadc->dev,
  436. "timeout didn't receive"
  437. " sw GPADC conv interrupt\n");
  438. ret = -EINVAL;
  439. goto out;
  440. }
  441. }
  442. /* Read the converted RAW data */
  443. if (conv_type == ADC_HW) {
  444. ret = abx500_get_register_interruptible(gpadc->dev,
  445. AB8500_GPADC, AB8500_GPADC_AUTODATAL_REG, &low_data);
  446. if (ret < 0) {
  447. dev_err(gpadc->dev,
  448. "gpadc_conversion: read hw low data failed\n");
  449. goto out;
  450. }
  451. ret = abx500_get_register_interruptible(gpadc->dev,
  452. AB8500_GPADC, AB8500_GPADC_AUTODATAH_REG, &high_data);
  453. if (ret < 0) {
  454. dev_err(gpadc->dev,
  455. "gpadc_conversion: read hw high data failed\n");
  456. goto out;
  457. }
  458. } else {
  459. ret = abx500_get_register_interruptible(gpadc->dev,
  460. AB8500_GPADC, AB8500_GPADC_MANDATAL_REG, &low_data);
  461. if (ret < 0) {
  462. dev_err(gpadc->dev,
  463. "gpadc_conversion: read sw low data failed\n");
  464. goto out;
  465. }
  466. ret = abx500_get_register_interruptible(gpadc->dev,
  467. AB8500_GPADC, AB8500_GPADC_MANDATAH_REG, &high_data);
  468. if (ret < 0) {
  469. dev_err(gpadc->dev,
  470. "gpadc_conversion: read sw high data failed\n");
  471. goto out;
  472. }
  473. }
  474. /* Disable GPADC */
  475. ret = abx500_set_register_interruptible(gpadc->dev, AB8500_GPADC,
  476. AB8500_GPADC_CTRL1_REG, DIS_GPADC);
  477. if (ret < 0) {
  478. dev_err(gpadc->dev, "gpadc_conversion: disable gpadc failed\n");
  479. goto out;
  480. }
  481. /* Disable VTVout LDO this is required for GPADC */
  482. pm_runtime_mark_last_busy(gpadc->dev);
  483. pm_runtime_put_autosuspend(gpadc->dev);
  484. mutex_unlock(&gpadc->ab8500_gpadc_lock);
  485. return (high_data << 8) | low_data;
  486. out:
  487. /*
  488. * It has shown to be needed to turn off the GPADC if an error occurs,
  489. * otherwise we might have problem when waiting for the busy bit in the
  490. * GPADC status register to go low. In V1.1 there wait_for_completion
  491. * seems to timeout when waiting for an interrupt.. Not seen in V2.0
  492. */
  493. (void) abx500_set_register_interruptible(gpadc->dev, AB8500_GPADC,
  494. AB8500_GPADC_CTRL1_REG, DIS_GPADC);
  495. pm_runtime_put(gpadc->dev);
  496. mutex_unlock(&gpadc->ab8500_gpadc_lock);
  497. dev_err(gpadc->dev,
  498. "gpadc_conversion: Failed to AD convert channel %d\n", channel);
  499. return ret;
  500. }
  501. EXPORT_SYMBOL(ab8500_gpadc_read_raw);
  502. /**
  503. * ab8500_bm_gpadcconvend_handler() - isr for gpadc conversion completion
  504. * @irq: irq number
  505. * @data: pointer to the data passed during request irq
  506. *
  507. * This is a interrupt service routine for gpadc conversion completion.
  508. * Notifies the gpadc completion is completed and the converted raw value
  509. * can be read from the registers.
  510. * Returns IRQ status(IRQ_HANDLED)
  511. */
  512. static irqreturn_t ab8500_bm_gpadcconvend_handler(int irq, void *_gpadc)
  513. {
  514. struct ab8500_gpadc *gpadc = _gpadc;
  515. complete(&gpadc->ab8500_gpadc_complete);
  516. return IRQ_HANDLED;
  517. }
  518. static int otp_cal_regs[] = {
  519. AB8500_GPADC_CAL_1,
  520. AB8500_GPADC_CAL_2,
  521. AB8500_GPADC_CAL_3,
  522. AB8500_GPADC_CAL_4,
  523. AB8500_GPADC_CAL_5,
  524. AB8500_GPADC_CAL_6,
  525. AB8500_GPADC_CAL_7,
  526. };
  527. static void ab8500_gpadc_read_calibration_data(struct ab8500_gpadc *gpadc)
  528. {
  529. int i;
  530. int ret[ARRAY_SIZE(otp_cal_regs)];
  531. u8 gpadc_cal[ARRAY_SIZE(otp_cal_regs)];
  532. int vmain_high, vmain_low;
  533. int btemp_high, btemp_low;
  534. int vbat_high, vbat_low;
  535. /* First we read all OTP registers and store the error code */
  536. for (i = 0; i < ARRAY_SIZE(otp_cal_regs); i++) {
  537. ret[i] = abx500_get_register_interruptible(gpadc->dev,
  538. AB8500_OTP_EMUL, otp_cal_regs[i], &gpadc_cal[i]);
  539. if (ret[i] < 0)
  540. dev_err(gpadc->dev, "%s: read otp reg 0x%02x failed\n",
  541. __func__, otp_cal_regs[i]);
  542. }
  543. /*
  544. * The ADC calibration data is stored in OTP registers.
  545. * The layout of the calibration data is outlined below and a more
  546. * detailed description can be found in UM0836
  547. *
  548. * vm_h/l = vmain_high/low
  549. * bt_h/l = btemp_high/low
  550. * vb_h/l = vbat_high/low
  551. *
  552. * Data bits:
  553. * | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0
  554. * |.......|.......|.......|.......|.......|.......|.......|.......
  555. * | | vm_h9 | vm_h8
  556. * |.......|.......|.......|.......|.......|.......|.......|.......
  557. * | | vm_h7 | vm_h6 | vm_h5 | vm_h4 | vm_h3 | vm_h2
  558. * |.......|.......|.......|.......|.......|.......|.......|.......
  559. * | vm_h1 | vm_h0 | vm_l4 | vm_l3 | vm_l2 | vm_l1 | vm_l0 | bt_h9
  560. * |.......|.......|.......|.......|.......|.......|.......|.......
  561. * | bt_h8 | bt_h7 | bt_h6 | bt_h5 | bt_h4 | bt_h3 | bt_h2 | bt_h1
  562. * |.......|.......|.......|.......|.......|.......|.......|.......
  563. * | bt_h0 | bt_l4 | bt_l3 | bt_l2 | bt_l1 | bt_l0 | vb_h9 | vb_h8
  564. * |.......|.......|.......|.......|.......|.......|.......|.......
  565. * | vb_h7 | vb_h6 | vb_h5 | vb_h4 | vb_h3 | vb_h2 | vb_h1 | vb_h0
  566. * |.......|.......|.......|.......|.......|.......|.......|.......
  567. * | vb_l5 | vb_l4 | vb_l3 | vb_l2 | vb_l1 | vb_l0 |
  568. * |.......|.......|.......|.......|.......|.......|.......|.......
  569. *
  570. *
  571. * Ideal output ADC codes corresponding to injected input voltages
  572. * during manufacturing is:
  573. *
  574. * vmain_high: Vin = 19500mV / ADC ideal code = 997
  575. * vmain_low: Vin = 315mV / ADC ideal code = 16
  576. * btemp_high: Vin = 1300mV / ADC ideal code = 985
  577. * btemp_low: Vin = 21mV / ADC ideal code = 16
  578. * vbat_high: Vin = 4700mV / ADC ideal code = 982
  579. * vbat_low: Vin = 2380mV / ADC ideal code = 33
  580. */
  581. /* Calculate gain and offset for VMAIN if all reads succeeded */
  582. if (!(ret[0] < 0 || ret[1] < 0 || ret[2] < 0)) {
  583. vmain_high = (((gpadc_cal[0] & 0x03) << 8) |
  584. ((gpadc_cal[1] & 0x3F) << 2) |
  585. ((gpadc_cal[2] & 0xC0) >> 6));
  586. vmain_low = ((gpadc_cal[2] & 0x3E) >> 1);
  587. gpadc->cal_data[ADC_INPUT_VMAIN].gain = CALIB_SCALE *
  588. (19500 - 315) / (vmain_high - vmain_low);
  589. gpadc->cal_data[ADC_INPUT_VMAIN].offset = CALIB_SCALE * 19500 -
  590. (CALIB_SCALE * (19500 - 315) /
  591. (vmain_high - vmain_low)) * vmain_high;
  592. } else {
  593. gpadc->cal_data[ADC_INPUT_VMAIN].gain = 0;
  594. }
  595. /* Calculate gain and offset for BTEMP if all reads succeeded */
  596. if (!(ret[2] < 0 || ret[3] < 0 || ret[4] < 0)) {
  597. btemp_high = (((gpadc_cal[2] & 0x01) << 9) |
  598. (gpadc_cal[3] << 1) |
  599. ((gpadc_cal[4] & 0x80) >> 7));
  600. btemp_low = ((gpadc_cal[4] & 0x7C) >> 2);
  601. gpadc->cal_data[ADC_INPUT_BTEMP].gain =
  602. CALIB_SCALE * (1300 - 21) / (btemp_high - btemp_low);
  603. gpadc->cal_data[ADC_INPUT_BTEMP].offset = CALIB_SCALE * 1300 -
  604. (CALIB_SCALE * (1300 - 21) /
  605. (btemp_high - btemp_low)) * btemp_high;
  606. } else {
  607. gpadc->cal_data[ADC_INPUT_BTEMP].gain = 0;
  608. }
  609. /* Calculate gain and offset for VBAT if all reads succeeded */
  610. if (!(ret[4] < 0 || ret[5] < 0 || ret[6] < 0)) {
  611. vbat_high = (((gpadc_cal[4] & 0x03) << 8) | gpadc_cal[5]);
  612. vbat_low = ((gpadc_cal[6] & 0xFC) >> 2);
  613. gpadc->cal_data[ADC_INPUT_VBAT].gain = CALIB_SCALE *
  614. (4700 - 2380) / (vbat_high - vbat_low);
  615. gpadc->cal_data[ADC_INPUT_VBAT].offset = CALIB_SCALE * 4700 -
  616. (CALIB_SCALE * (4700 - 2380) /
  617. (vbat_high - vbat_low)) * vbat_high;
  618. } else {
  619. gpadc->cal_data[ADC_INPUT_VBAT].gain = 0;
  620. }
  621. dev_dbg(gpadc->dev, "VMAIN gain %llu offset %llu\n",
  622. gpadc->cal_data[ADC_INPUT_VMAIN].gain,
  623. gpadc->cal_data[ADC_INPUT_VMAIN].offset);
  624. dev_dbg(gpadc->dev, "BTEMP gain %llu offset %llu\n",
  625. gpadc->cal_data[ADC_INPUT_BTEMP].gain,
  626. gpadc->cal_data[ADC_INPUT_BTEMP].offset);
  627. dev_dbg(gpadc->dev, "VBAT gain %llu offset %llu\n",
  628. gpadc->cal_data[ADC_INPUT_VBAT].gain,
  629. gpadc->cal_data[ADC_INPUT_VBAT].offset);
  630. }
  631. static int ab8500_gpadc_runtime_suspend(struct device *dev)
  632. {
  633. struct ab8500_gpadc *gpadc = dev_get_drvdata(dev);
  634. regulator_disable(gpadc->regu);
  635. return 0;
  636. }
  637. static int ab8500_gpadc_runtime_resume(struct device *dev)
  638. {
  639. struct ab8500_gpadc *gpadc = dev_get_drvdata(dev);
  640. regulator_enable(gpadc->regu);
  641. return 0;
  642. }
  643. static int ab8500_gpadc_runtime_idle(struct device *dev)
  644. {
  645. pm_runtime_suspend(dev);
  646. return 0;
  647. }
  648. static int ab8500_gpadc_suspend(struct device *dev)
  649. {
  650. struct ab8500_gpadc *gpadc = dev_get_drvdata(dev);
  651. mutex_lock(&gpadc->ab8500_gpadc_lock);
  652. pm_runtime_get_sync(dev);
  653. regulator_disable(gpadc->regu);
  654. return 0;
  655. }
  656. static int ab8500_gpadc_resume(struct device *dev)
  657. {
  658. struct ab8500_gpadc *gpadc = dev_get_drvdata(dev);
  659. regulator_enable(gpadc->regu);
  660. pm_runtime_mark_last_busy(gpadc->dev);
  661. pm_runtime_put_autosuspend(gpadc->dev);
  662. mutex_unlock(&gpadc->ab8500_gpadc_lock);
  663. return 0;
  664. }
  665. static int ab8500_gpadc_probe(struct platform_device *pdev)
  666. {
  667. int ret = 0;
  668. struct ab8500_gpadc *gpadc;
  669. gpadc = kzalloc(sizeof(struct ab8500_gpadc), GFP_KERNEL);
  670. if (!gpadc) {
  671. dev_err(&pdev->dev, "Error: No memory\n");
  672. return -ENOMEM;
  673. }
  674. gpadc->irq_sw = platform_get_irq_byname(pdev, "SW_CONV_END");
  675. if (gpadc->irq_sw < 0) {
  676. dev_err(gpadc->dev, "failed to get platform irq-%d\n",
  677. gpadc->irq_sw);
  678. ret = gpadc->irq_sw;
  679. goto fail;
  680. }
  681. gpadc->irq_hw = platform_get_irq_byname(pdev, "HW_CONV_END");
  682. if (gpadc->irq_hw < 0) {
  683. dev_err(gpadc->dev, "failed to get platform irq-%d\n",
  684. gpadc->irq_hw);
  685. ret = gpadc->irq_hw;
  686. goto fail;
  687. }
  688. gpadc->dev = &pdev->dev;
  689. gpadc->parent = dev_get_drvdata(pdev->dev.parent);
  690. mutex_init(&gpadc->ab8500_gpadc_lock);
  691. /* Initialize completion used to notify completion of conversion */
  692. init_completion(&gpadc->ab8500_gpadc_complete);
  693. /* Register interrupts */
  694. ret = request_threaded_irq(gpadc->irq_sw, NULL,
  695. ab8500_bm_gpadcconvend_handler,
  696. IRQF_NO_SUSPEND | IRQF_SHARED, "ab8500-gpadc-sw", gpadc);
  697. if (ret < 0) {
  698. dev_err(gpadc->dev, "Failed to register interrupt, irq: %d\n",
  699. gpadc->irq_sw);
  700. goto fail;
  701. }
  702. ret = request_threaded_irq(gpadc->irq_hw, NULL,
  703. ab8500_bm_gpadcconvend_handler,
  704. IRQF_NO_SUSPEND | IRQF_SHARED, "ab8500-gpadc-hw", gpadc);
  705. if (ret < 0) {
  706. dev_err(gpadc->dev, "Failed to register interrupt, irq: %d\n",
  707. gpadc->irq_hw);
  708. goto fail;
  709. }
  710. /* VTVout LDO used to power up ab8500-GPADC */
  711. gpadc->regu = regulator_get(&pdev->dev, "vddadc");
  712. if (IS_ERR(gpadc->regu)) {
  713. ret = PTR_ERR(gpadc->regu);
  714. dev_err(gpadc->dev, "failed to get vtvout LDO\n");
  715. goto fail_irq;
  716. }
  717. platform_set_drvdata(pdev, gpadc);
  718. regulator_enable(gpadc->regu);
  719. pm_runtime_set_autosuspend_delay(gpadc->dev, GPADC_AUDOSUSPEND_DELAY);
  720. pm_runtime_use_autosuspend(gpadc->dev);
  721. pm_runtime_set_active(gpadc->dev);
  722. pm_runtime_enable(gpadc->dev);
  723. ab8500_gpadc_read_calibration_data(gpadc);
  724. list_add_tail(&gpadc->node, &ab8500_gpadc_list);
  725. dev_dbg(gpadc->dev, "probe success\n");
  726. return 0;
  727. fail_irq:
  728. free_irq(gpadc->irq_sw, gpadc);
  729. free_irq(gpadc->irq_hw, gpadc);
  730. fail:
  731. kfree(gpadc);
  732. gpadc = NULL;
  733. return ret;
  734. }
  735. static int ab8500_gpadc_remove(struct platform_device *pdev)
  736. {
  737. struct ab8500_gpadc *gpadc = platform_get_drvdata(pdev);
  738. /* remove this gpadc entry from the list */
  739. list_del(&gpadc->node);
  740. /* remove interrupt - completion of Sw ADC conversion */
  741. free_irq(gpadc->irq_sw, gpadc);
  742. free_irq(gpadc->irq_hw, gpadc);
  743. pm_runtime_get_sync(gpadc->dev);
  744. pm_runtime_disable(gpadc->dev);
  745. regulator_disable(gpadc->regu);
  746. pm_runtime_set_suspended(gpadc->dev);
  747. pm_runtime_put_noidle(gpadc->dev);
  748. kfree(gpadc);
  749. gpadc = NULL;
  750. return 0;
  751. }
  752. static const struct dev_pm_ops ab8500_gpadc_pm_ops = {
  753. SET_RUNTIME_PM_OPS(ab8500_gpadc_runtime_suspend,
  754. ab8500_gpadc_runtime_resume,
  755. ab8500_gpadc_runtime_idle)
  756. SET_SYSTEM_SLEEP_PM_OPS(ab8500_gpadc_suspend,
  757. ab8500_gpadc_resume)
  758. };
  759. static struct platform_driver ab8500_gpadc_driver = {
  760. .probe = ab8500_gpadc_probe,
  761. .remove = ab8500_gpadc_remove,
  762. .driver = {
  763. .name = "ab8500-gpadc",
  764. .owner = THIS_MODULE,
  765. .pm = &ab8500_gpadc_pm_ops,
  766. },
  767. };
  768. static int __init ab8500_gpadc_init(void)
  769. {
  770. return platform_driver_register(&ab8500_gpadc_driver);
  771. }
  772. static void __exit ab8500_gpadc_exit(void)
  773. {
  774. platform_driver_unregister(&ab8500_gpadc_driver);
  775. }
  776. subsys_initcall_sync(ab8500_gpadc_init);
  777. module_exit(ab8500_gpadc_exit);
  778. MODULE_LICENSE("GPL v2");
  779. MODULE_AUTHOR("Arun R Murthy, Daniel Willerud, Johan Palsson,"
  780. "M'boumba Cedric Madianga");
  781. MODULE_ALIAS("platform:ab8500_gpadc");
  782. MODULE_DESCRIPTION("AB8500 GPADC driver");