cirrusfb.c 89 KB

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  1. /*
  2. * drivers/video/cirrusfb.c - driver for Cirrus Logic chipsets
  3. *
  4. * Copyright 1999-2001 Jeff Garzik <jgarzik@pobox.com>
  5. *
  6. * Contributors (thanks, all!)
  7. *
  8. * David Eger:
  9. * Overhaul for Linux 2.6
  10. *
  11. * Jeff Rugen:
  12. * Major contributions; Motorola PowerStack (PPC and PCI) support,
  13. * GD54xx, 1280x1024 mode support, change MCLK based on VCLK.
  14. *
  15. * Geert Uytterhoeven:
  16. * Excellent code review.
  17. *
  18. * Lars Hecking:
  19. * Amiga updates and testing.
  20. *
  21. * Original cirrusfb author: Frank Neumann
  22. *
  23. * Based on retz3fb.c and cirrusfb.c:
  24. * Copyright (C) 1997 Jes Sorensen
  25. * Copyright (C) 1996 Frank Neumann
  26. *
  27. ***************************************************************
  28. *
  29. * Format this code with GNU indent '-kr -i8 -pcs' options.
  30. *
  31. * This file is subject to the terms and conditions of the GNU General Public
  32. * License. See the file COPYING in the main directory of this archive
  33. * for more details.
  34. *
  35. */
  36. #define CIRRUSFB_VERSION "2.0-pre2"
  37. #include <linux/module.h>
  38. #include <linux/kernel.h>
  39. #include <linux/errno.h>
  40. #include <linux/string.h>
  41. #include <linux/mm.h>
  42. #include <linux/slab.h>
  43. #include <linux/delay.h>
  44. #include <linux/fb.h>
  45. #include <linux/init.h>
  46. #include <linux/selection.h>
  47. #include <asm/pgtable.h>
  48. #ifdef CONFIG_ZORRO
  49. #include <linux/zorro.h>
  50. #endif
  51. #ifdef CONFIG_PCI
  52. #include <linux/pci.h>
  53. #endif
  54. #ifdef CONFIG_AMIGA
  55. #include <asm/amigahw.h>
  56. #endif
  57. #ifdef CONFIG_PPC_PREP
  58. #include <asm/machdep.h>
  59. #define isPReP machine_is(prep)
  60. #else
  61. #define isPReP 0
  62. #endif
  63. #include "video/vga.h"
  64. #include "video/cirrus.h"
  65. /*****************************************************************
  66. *
  67. * debugging and utility macros
  68. *
  69. */
  70. /* enable debug output? */
  71. /* #define CIRRUSFB_DEBUG 1 */
  72. /* disable runtime assertions? */
  73. /* #define CIRRUSFB_NDEBUG */
  74. /* debug output */
  75. #ifdef CIRRUSFB_DEBUG
  76. #define DPRINTK(fmt, args...) \
  77. printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
  78. #else
  79. #define DPRINTK(fmt, args...)
  80. #endif
  81. /* debugging assertions */
  82. #ifndef CIRRUSFB_NDEBUG
  83. #define assert(expr) \
  84. if (!(expr)) { \
  85. printk("Assertion failed! %s,%s,%s,line=%d\n", \
  86. #expr, __FILE__, __FUNCTION__, __LINE__); \
  87. }
  88. #else
  89. #define assert(expr)
  90. #endif
  91. #define MB_ (1024 * 1024)
  92. #define KB_ (1024)
  93. #define MAX_NUM_BOARDS 7
  94. /*****************************************************************
  95. *
  96. * chipset information
  97. *
  98. */
  99. /* board types */
  100. enum cirrus_board {
  101. BT_NONE = 0,
  102. BT_SD64,
  103. BT_PICCOLO,
  104. BT_PICASSO,
  105. BT_SPECTRUM,
  106. BT_PICASSO4, /* GD5446 */
  107. BT_ALPINE, /* GD543x/4x */
  108. BT_GD5480,
  109. BT_LAGUNA, /* GD546x */
  110. };
  111. /*
  112. * per-board-type information, used for enumerating and abstracting
  113. * chip-specific information
  114. * NOTE: MUST be in the same order as enum cirrus_board in order to
  115. * use direct indexing on this array
  116. * NOTE: '__initdata' cannot be used as some of this info
  117. * is required at runtime. Maybe separate into an init-only and
  118. * a run-time table?
  119. */
  120. static const struct cirrusfb_board_info_rec {
  121. char *name; /* ASCII name of chipset */
  122. long maxclock[5]; /* maximum video clock */
  123. /* for 1/4bpp, 8bpp 15/16bpp, 24bpp, 32bpp - numbers from xorg code */
  124. bool init_sr07 : 1; /* init SR07 during init_vgachip() */
  125. bool init_sr1f : 1; /* write SR1F during init_vgachip() */
  126. /* construct bit 19 of screen start address */
  127. bool scrn_start_bit19 : 1;
  128. /* initial SR07 value, then for each mode */
  129. unsigned char sr07;
  130. unsigned char sr07_1bpp;
  131. unsigned char sr07_1bpp_mux;
  132. unsigned char sr07_8bpp;
  133. unsigned char sr07_8bpp_mux;
  134. unsigned char sr1f; /* SR1F VGA initial register value */
  135. } cirrusfb_board_info[] = {
  136. [BT_SD64] = {
  137. .name = "CL SD64",
  138. .maxclock = {
  139. /* guess */
  140. /* the SD64/P4 have a higher max. videoclock */
  141. 140000, 140000, 140000, 140000, 140000,
  142. },
  143. .init_sr07 = true,
  144. .init_sr1f = true,
  145. .scrn_start_bit19 = true,
  146. .sr07 = 0xF0,
  147. .sr07_1bpp = 0xF0,
  148. .sr07_8bpp = 0xF1,
  149. .sr1f = 0x20
  150. },
  151. [BT_PICCOLO] = {
  152. .name = "CL Piccolo",
  153. .maxclock = {
  154. /* guess */
  155. 90000, 90000, 90000, 90000, 90000
  156. },
  157. .init_sr07 = true,
  158. .init_sr1f = true,
  159. .scrn_start_bit19 = false,
  160. .sr07 = 0x80,
  161. .sr07_1bpp = 0x80,
  162. .sr07_8bpp = 0x81,
  163. .sr1f = 0x22
  164. },
  165. [BT_PICASSO] = {
  166. .name = "CL Picasso",
  167. .maxclock = {
  168. /* guess */
  169. 90000, 90000, 90000, 90000, 90000
  170. },
  171. .init_sr07 = true,
  172. .init_sr1f = true,
  173. .scrn_start_bit19 = false,
  174. .sr07 = 0x20,
  175. .sr07_1bpp = 0x20,
  176. .sr07_8bpp = 0x21,
  177. .sr1f = 0x22
  178. },
  179. [BT_SPECTRUM] = {
  180. .name = "CL Spectrum",
  181. .maxclock = {
  182. /* guess */
  183. 90000, 90000, 90000, 90000, 90000
  184. },
  185. .init_sr07 = true,
  186. .init_sr1f = true,
  187. .scrn_start_bit19 = false,
  188. .sr07 = 0x80,
  189. .sr07_1bpp = 0x80,
  190. .sr07_8bpp = 0x81,
  191. .sr1f = 0x22
  192. },
  193. [BT_PICASSO4] = {
  194. .name = "CL Picasso4",
  195. .maxclock = {
  196. 135100, 135100, 85500, 85500, 0
  197. },
  198. .init_sr07 = true,
  199. .init_sr1f = false,
  200. .scrn_start_bit19 = true,
  201. .sr07 = 0x20,
  202. .sr07_1bpp = 0x20,
  203. .sr07_8bpp = 0x21,
  204. .sr1f = 0
  205. },
  206. [BT_ALPINE] = {
  207. .name = "CL Alpine",
  208. .maxclock = {
  209. /* for the GD5430. GD5446 can do more... */
  210. 85500, 85500, 50000, 28500, 0
  211. },
  212. .init_sr07 = true,
  213. .init_sr1f = true,
  214. .scrn_start_bit19 = true,
  215. .sr07 = 0xA0,
  216. .sr07_1bpp = 0xA1,
  217. .sr07_1bpp_mux = 0xA7,
  218. .sr07_8bpp = 0xA1,
  219. .sr07_8bpp_mux = 0xA7,
  220. .sr1f = 0x1C
  221. },
  222. [BT_GD5480] = {
  223. .name = "CL GD5480",
  224. .maxclock = {
  225. 135100, 200000, 200000, 135100, 135100
  226. },
  227. .init_sr07 = true,
  228. .init_sr1f = true,
  229. .scrn_start_bit19 = true,
  230. .sr07 = 0x10,
  231. .sr07_1bpp = 0x11,
  232. .sr07_8bpp = 0x11,
  233. .sr1f = 0x1C
  234. },
  235. [BT_LAGUNA] = {
  236. .name = "CL Laguna",
  237. .maxclock = {
  238. /* guess */
  239. 135100, 135100, 135100, 135100, 135100,
  240. },
  241. .init_sr07 = false,
  242. .init_sr1f = false,
  243. .scrn_start_bit19 = true,
  244. }
  245. };
  246. #ifdef CONFIG_PCI
  247. #define CHIP(id, btype) \
  248. { PCI_VENDOR_ID_CIRRUS, id, PCI_ANY_ID, PCI_ANY_ID, 0, 0, (btype) }
  249. static struct pci_device_id cirrusfb_pci_table[] = {
  250. CHIP(PCI_DEVICE_ID_CIRRUS_5436, BT_ALPINE),
  251. CHIP(PCI_DEVICE_ID_CIRRUS_5434_8, BT_ALPINE),
  252. CHIP(PCI_DEVICE_ID_CIRRUS_5434_4, BT_ALPINE),
  253. CHIP(PCI_DEVICE_ID_CIRRUS_5430, BT_ALPINE), /* GD-5440 is same id */
  254. CHIP(PCI_DEVICE_ID_CIRRUS_7543, BT_ALPINE),
  255. CHIP(PCI_DEVICE_ID_CIRRUS_7548, BT_ALPINE),
  256. CHIP(PCI_DEVICE_ID_CIRRUS_5480, BT_GD5480), /* MacPicasso likely */
  257. CHIP(PCI_DEVICE_ID_CIRRUS_5446, BT_PICASSO4), /* Picasso 4 is 5446 */
  258. CHIP(PCI_DEVICE_ID_CIRRUS_5462, BT_LAGUNA), /* CL Laguna */
  259. CHIP(PCI_DEVICE_ID_CIRRUS_5464, BT_LAGUNA), /* CL Laguna 3D */
  260. CHIP(PCI_DEVICE_ID_CIRRUS_5465, BT_LAGUNA), /* CL Laguna 3DA*/
  261. { 0, }
  262. };
  263. MODULE_DEVICE_TABLE(pci, cirrusfb_pci_table);
  264. #undef CHIP
  265. #endif /* CONFIG_PCI */
  266. #ifdef CONFIG_ZORRO
  267. static const struct zorro_device_id cirrusfb_zorro_table[] = {
  268. {
  269. .id = ZORRO_PROD_HELFRICH_SD64_RAM,
  270. .driver_data = BT_SD64,
  271. }, {
  272. .id = ZORRO_PROD_HELFRICH_PICCOLO_RAM,
  273. .driver_data = BT_PICCOLO,
  274. }, {
  275. .id = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_II_II_PLUS_RAM,
  276. .driver_data = BT_PICASSO,
  277. }, {
  278. .id = ZORRO_PROD_GVP_EGS_28_24_SPECTRUM_RAM,
  279. .driver_data = BT_SPECTRUM,
  280. }, {
  281. .id = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_IV_Z3,
  282. .driver_data = BT_PICASSO4,
  283. },
  284. { 0 }
  285. };
  286. static const struct {
  287. zorro_id id2;
  288. unsigned long size;
  289. } cirrusfb_zorro_table2[] = {
  290. [BT_SD64] = {
  291. .id2 = ZORRO_PROD_HELFRICH_SD64_REG,
  292. .size = 0x400000
  293. },
  294. [BT_PICCOLO] = {
  295. .id2 = ZORRO_PROD_HELFRICH_PICCOLO_REG,
  296. .size = 0x200000
  297. },
  298. [BT_PICASSO] = {
  299. .id2 = ZORRO_PROD_VILLAGE_TRONIC_PICASSO_II_II_PLUS_REG,
  300. .size = 0x200000
  301. },
  302. [BT_SPECTRUM] = {
  303. .id2 = ZORRO_PROD_GVP_EGS_28_24_SPECTRUM_REG,
  304. .size = 0x200000
  305. },
  306. [BT_PICASSO4] = {
  307. .id2 = 0,
  308. .size = 0x400000
  309. }
  310. };
  311. #endif /* CONFIG_ZORRO */
  312. struct cirrusfb_regs {
  313. __u32 line_length; /* in BYTES! */
  314. __u32 visual;
  315. __u32 type;
  316. long freq;
  317. long nom;
  318. long den;
  319. long div;
  320. long multiplexing;
  321. long mclk;
  322. long divMCLK;
  323. long HorizRes; /* The x resolution in pixel */
  324. long HorizTotal;
  325. long HorizDispEnd;
  326. long HorizBlankStart;
  327. long HorizBlankEnd;
  328. long HorizSyncStart;
  329. long HorizSyncEnd;
  330. long VertRes; /* the physical y resolution in scanlines */
  331. long VertTotal;
  332. long VertDispEnd;
  333. long VertSyncStart;
  334. long VertSyncEnd;
  335. long VertBlankStart;
  336. long VertBlankEnd;
  337. };
  338. #ifdef CIRRUSFB_DEBUG
  339. enum cirrusfb_dbg_reg_class {
  340. CRT,
  341. SEQ
  342. };
  343. #endif /* CIRRUSFB_DEBUG */
  344. /* info about board */
  345. struct cirrusfb_info {
  346. struct fb_info *info;
  347. u8 __iomem *fbmem;
  348. u8 __iomem *regbase;
  349. u8 __iomem *mem;
  350. unsigned long size;
  351. enum cirrus_board btype;
  352. unsigned char SFR; /* Shadow of special function register */
  353. unsigned long fbmem_phys;
  354. unsigned long fbregs_phys;
  355. struct cirrusfb_regs currentmode;
  356. int blank_mode;
  357. u32 pseudo_palette[16];
  358. struct { u8 red, green, blue, pad; } palette[256];
  359. #ifdef CONFIG_ZORRO
  360. struct zorro_dev *zdev;
  361. #endif
  362. #ifdef CONFIG_PCI
  363. struct pci_dev *pdev;
  364. #endif
  365. void (*unmap)(struct cirrusfb_info *cinfo);
  366. };
  367. static unsigned cirrusfb_def_mode = 1;
  368. static int noaccel;
  369. /*
  370. * Predefined Video Modes
  371. */
  372. static const struct {
  373. const char *name;
  374. struct fb_var_screeninfo var;
  375. } cirrusfb_predefined[] = {
  376. {
  377. /* autodetect mode */
  378. .name = "Autodetect",
  379. }, {
  380. /* 640x480, 31.25 kHz, 60 Hz, 25 MHz PixClock */
  381. .name = "640x480",
  382. .var = {
  383. .xres = 640,
  384. .yres = 480,
  385. .xres_virtual = 640,
  386. .yres_virtual = 480,
  387. .bits_per_pixel = 8,
  388. .red = { .length = 8 },
  389. .green = { .length = 8 },
  390. .blue = { .length = 8 },
  391. .width = -1,
  392. .height = -1,
  393. .pixclock = 40000,
  394. .left_margin = 48,
  395. .right_margin = 16,
  396. .upper_margin = 32,
  397. .lower_margin = 8,
  398. .hsync_len = 96,
  399. .vsync_len = 4,
  400. .sync = FB_SYNC_HOR_HIGH_ACT | FB_SYNC_VERT_HIGH_ACT,
  401. .vmode = FB_VMODE_NONINTERLACED
  402. }
  403. }, {
  404. /* 800x600, 48 kHz, 76 Hz, 50 MHz PixClock */
  405. .name = "800x600",
  406. .var = {
  407. .xres = 800,
  408. .yres = 600,
  409. .xres_virtual = 800,
  410. .yres_virtual = 600,
  411. .bits_per_pixel = 8,
  412. .red = { .length = 8 },
  413. .green = { .length = 8 },
  414. .blue = { .length = 8 },
  415. .width = -1,
  416. .height = -1,
  417. .pixclock = 20000,
  418. .left_margin = 128,
  419. .right_margin = 16,
  420. .upper_margin = 24,
  421. .lower_margin = 2,
  422. .hsync_len = 96,
  423. .vsync_len = 6,
  424. .vmode = FB_VMODE_NONINTERLACED
  425. }
  426. }, {
  427. /*
  428. * Modeline from XF86Config:
  429. * Mode "1024x768" 80 1024 1136 1340 1432 768 770 774 805
  430. */
  431. /* 1024x768, 55.8 kHz, 70 Hz, 80 MHz PixClock */
  432. .name = "1024x768",
  433. .var = {
  434. .xres = 1024,
  435. .yres = 768,
  436. .xres_virtual = 1024,
  437. .yres_virtual = 768,
  438. .bits_per_pixel = 8,
  439. .red = { .length = 8 },
  440. .green = { .length = 8 },
  441. .blue = { .length = 8 },
  442. .width = -1,
  443. .height = -1,
  444. .pixclock = 12500,
  445. .left_margin = 144,
  446. .right_margin = 32,
  447. .upper_margin = 30,
  448. .lower_margin = 2,
  449. .hsync_len = 192,
  450. .vsync_len = 6,
  451. .vmode = FB_VMODE_NONINTERLACED
  452. }
  453. }
  454. };
  455. #define NUM_TOTAL_MODES ARRAY_SIZE(cirrusfb_predefined)
  456. /****************************************************************************/
  457. /**** BEGIN PROTOTYPES ******************************************************/
  458. /*--- Interface used by the world ------------------------------------------*/
  459. static int cirrusfb_init(void);
  460. #ifndef MODULE
  461. static int cirrusfb_setup(char *options);
  462. #endif
  463. static int cirrusfb_open(struct fb_info *info, int user);
  464. static int cirrusfb_release(struct fb_info *info, int user);
  465. static int cirrusfb_setcolreg(unsigned regno, unsigned red, unsigned green,
  466. unsigned blue, unsigned transp,
  467. struct fb_info *info);
  468. static int cirrusfb_check_var(struct fb_var_screeninfo *var,
  469. struct fb_info *info);
  470. static int cirrusfb_set_par(struct fb_info *info);
  471. static int cirrusfb_pan_display(struct fb_var_screeninfo *var,
  472. struct fb_info *info);
  473. static int cirrusfb_blank(int blank_mode, struct fb_info *info);
  474. static void cirrusfb_fillrect(struct fb_info *info,
  475. const struct fb_fillrect *region);
  476. static void cirrusfb_copyarea(struct fb_info *info,
  477. const struct fb_copyarea *area);
  478. static void cirrusfb_imageblit(struct fb_info *info,
  479. const struct fb_image *image);
  480. /* function table of the above functions */
  481. static struct fb_ops cirrusfb_ops = {
  482. .owner = THIS_MODULE,
  483. .fb_open = cirrusfb_open,
  484. .fb_release = cirrusfb_release,
  485. .fb_setcolreg = cirrusfb_setcolreg,
  486. .fb_check_var = cirrusfb_check_var,
  487. .fb_set_par = cirrusfb_set_par,
  488. .fb_pan_display = cirrusfb_pan_display,
  489. .fb_blank = cirrusfb_blank,
  490. .fb_fillrect = cirrusfb_fillrect,
  491. .fb_copyarea = cirrusfb_copyarea,
  492. .fb_imageblit = cirrusfb_imageblit,
  493. };
  494. /*--- Hardware Specific Routines -------------------------------------------*/
  495. static int cirrusfb_decode_var(const struct fb_var_screeninfo *var,
  496. struct cirrusfb_regs *regs,
  497. const struct fb_info *info);
  498. /*--- Internal routines ----------------------------------------------------*/
  499. static void init_vgachip(struct cirrusfb_info *cinfo);
  500. static void switch_monitor(struct cirrusfb_info *cinfo, int on);
  501. static void WGen(const struct cirrusfb_info *cinfo,
  502. int regnum, unsigned char val);
  503. static unsigned char RGen(const struct cirrusfb_info *cinfo, int regnum);
  504. static void AttrOn(const struct cirrusfb_info *cinfo);
  505. static void WHDR(const struct cirrusfb_info *cinfo, unsigned char val);
  506. static void WSFR(struct cirrusfb_info *cinfo, unsigned char val);
  507. static void WSFR2(struct cirrusfb_info *cinfo, unsigned char val);
  508. static void WClut(struct cirrusfb_info *cinfo, unsigned char regnum,
  509. unsigned char red, unsigned char green, unsigned char blue);
  510. #if 0
  511. static void RClut(struct cirrusfb_info *cinfo, unsigned char regnum,
  512. unsigned char *red, unsigned char *green,
  513. unsigned char *blue);
  514. #endif
  515. static void cirrusfb_WaitBLT(u8 __iomem *regbase);
  516. static void cirrusfb_BitBLT(u8 __iomem *regbase, int bits_per_pixel,
  517. u_short curx, u_short cury,
  518. u_short destx, u_short desty,
  519. u_short width, u_short height,
  520. u_short line_length);
  521. static void cirrusfb_RectFill(u8 __iomem *regbase, int bits_per_pixel,
  522. u_short x, u_short y,
  523. u_short width, u_short height,
  524. u_char color, u_short line_length);
  525. static void bestclock(long freq, long *best,
  526. long *nom, long *den,
  527. long *div, long maxfreq);
  528. #ifdef CIRRUSFB_DEBUG
  529. static void cirrusfb_dump(void);
  530. static void cirrusfb_dbg_reg_dump(caddr_t regbase);
  531. static void cirrusfb_dbg_print_regs(caddr_t regbase,
  532. enum cirrusfb_dbg_reg_class reg_class, ...);
  533. static void cirrusfb_dbg_print_byte(const char *name, unsigned char val);
  534. #endif /* CIRRUSFB_DEBUG */
  535. /*** END PROTOTYPES ********************************************************/
  536. /*****************************************************************************/
  537. /*** BEGIN Interface Used by the World ***************************************/
  538. static int opencount;
  539. /*--- Open /dev/fbx ---------------------------------------------------------*/
  540. static int cirrusfb_open(struct fb_info *info, int user)
  541. {
  542. if (opencount++ == 0)
  543. switch_monitor(info->par, 1);
  544. return 0;
  545. }
  546. /*--- Close /dev/fbx --------------------------------------------------------*/
  547. static int cirrusfb_release(struct fb_info *info, int user)
  548. {
  549. if (--opencount == 0)
  550. switch_monitor(info->par, 0);
  551. return 0;
  552. }
  553. /**** END Interface used by the World *************************************/
  554. /****************************************************************************/
  555. /**** BEGIN Hardware specific Routines **************************************/
  556. /* Get a good MCLK value */
  557. static long cirrusfb_get_mclk(long freq, int bpp, long *div)
  558. {
  559. long mclk;
  560. assert(div != NULL);
  561. /* Calculate MCLK, in case VCLK is high enough to require > 50MHz.
  562. * Assume a 64-bit data path for now. The formula is:
  563. * ((B * PCLK * 2)/W) * 1.2
  564. * B = bytes per pixel, PCLK = pixclock, W = data width in bytes */
  565. mclk = ((bpp / 8) * freq * 2) / 4;
  566. mclk = (mclk * 12) / 10;
  567. if (mclk < 50000)
  568. mclk = 50000;
  569. DPRINTK("Use MCLK of %ld kHz\n", mclk);
  570. /* Calculate value for SR1F. Multiply by 2 so we can round up. */
  571. mclk = ((mclk * 16) / 14318);
  572. mclk = (mclk + 1) / 2;
  573. DPRINTK("Set SR1F[5:0] to 0x%lx\n", mclk);
  574. /* Determine if we should use MCLK instead of VCLK, and if so, what we
  575. * should divide it by to get VCLK */
  576. switch (freq) {
  577. case 24751 ... 25249:
  578. *div = 2;
  579. DPRINTK("Using VCLK = MCLK/2\n");
  580. break;
  581. case 49501 ... 50499:
  582. *div = 1;
  583. DPRINTK("Using VCLK = MCLK\n");
  584. break;
  585. default:
  586. *div = 0;
  587. break;
  588. }
  589. return mclk;
  590. }
  591. static int cirrusfb_check_var(struct fb_var_screeninfo *var,
  592. struct fb_info *info)
  593. {
  594. struct cirrusfb_info *cinfo = info->par;
  595. int nom, den; /* translyting from pixels->bytes */
  596. int yres, i;
  597. static struct { int xres, yres; } modes[] =
  598. { { 1600, 1280 },
  599. { 1280, 1024 },
  600. { 1024, 768 },
  601. { 800, 600 },
  602. { 640, 480 },
  603. { -1, -1 } };
  604. switch (var->bits_per_pixel) {
  605. case 0 ... 1:
  606. var->bits_per_pixel = 1;
  607. nom = 4;
  608. den = 8;
  609. break; /* 8 pixel per byte, only 1/4th of mem usable */
  610. case 2 ... 8:
  611. var->bits_per_pixel = 8;
  612. nom = 1;
  613. den = 1;
  614. break; /* 1 pixel == 1 byte */
  615. case 9 ... 16:
  616. var->bits_per_pixel = 16;
  617. nom = 2;
  618. den = 1;
  619. break; /* 2 bytes per pixel */
  620. case 17 ... 24:
  621. var->bits_per_pixel = 24;
  622. nom = 3;
  623. den = 1;
  624. break; /* 3 bytes per pixel */
  625. case 25 ... 32:
  626. var->bits_per_pixel = 32;
  627. nom = 4;
  628. den = 1;
  629. break; /* 4 bytes per pixel */
  630. default:
  631. printk(KERN_ERR "cirrusfb: mode %dx%dx%d rejected..."
  632. "color depth not supported.\n",
  633. var->xres, var->yres, var->bits_per_pixel);
  634. DPRINTK("EXIT - EINVAL error\n");
  635. return -EINVAL;
  636. }
  637. if (var->xres * nom / den * var->yres > cinfo->size) {
  638. printk(KERN_ERR "cirrusfb: mode %dx%dx%d rejected..."
  639. "resolution too high to fit into video memory!\n",
  640. var->xres, var->yres, var->bits_per_pixel);
  641. DPRINTK("EXIT - EINVAL error\n");
  642. return -EINVAL;
  643. }
  644. /* use highest possible virtual resolution */
  645. if (var->xres_virtual == -1 &&
  646. var->yres_virtual == -1) {
  647. printk(KERN_INFO
  648. "cirrusfb: using maximum available virtual resolution\n");
  649. for (i = 0; modes[i].xres != -1; i++) {
  650. if (modes[i].xres * nom / den * modes[i].yres < cinfo->size / 2)
  651. break;
  652. }
  653. if (modes[i].xres == -1) {
  654. printk(KERN_ERR "cirrusfb: could not find a virtual "
  655. "resolution that fits into video memory!!\n");
  656. DPRINTK("EXIT - EINVAL error\n");
  657. return -EINVAL;
  658. }
  659. var->xres_virtual = modes[i].xres;
  660. var->yres_virtual = modes[i].yres;
  661. printk(KERN_INFO "cirrusfb: virtual resolution set to "
  662. "maximum of %dx%d\n", var->xres_virtual,
  663. var->yres_virtual);
  664. }
  665. if (var->xres_virtual < var->xres)
  666. var->xres_virtual = var->xres;
  667. if (var->yres_virtual < var->yres)
  668. var->yres_virtual = var->yres;
  669. if (var->xoffset < 0)
  670. var->xoffset = 0;
  671. if (var->yoffset < 0)
  672. var->yoffset = 0;
  673. /* truncate xoffset and yoffset to maximum if too high */
  674. if (var->xoffset > var->xres_virtual - var->xres)
  675. var->xoffset = var->xres_virtual - var->xres - 1;
  676. if (var->yoffset > var->yres_virtual - var->yres)
  677. var->yoffset = var->yres_virtual - var->yres - 1;
  678. switch (var->bits_per_pixel) {
  679. case 1:
  680. var->red.offset = 0;
  681. var->red.length = 1;
  682. var->green.offset = 0;
  683. var->green.length = 1;
  684. var->blue.offset = 0;
  685. var->blue.length = 1;
  686. break;
  687. case 8:
  688. var->red.offset = 0;
  689. var->red.length = 6;
  690. var->green.offset = 0;
  691. var->green.length = 6;
  692. var->blue.offset = 0;
  693. var->blue.length = 6;
  694. break;
  695. case 16:
  696. if (isPReP) {
  697. var->red.offset = 2;
  698. var->green.offset = -3;
  699. var->blue.offset = 8;
  700. } else {
  701. var->red.offset = 10;
  702. var->green.offset = 5;
  703. var->blue.offset = 0;
  704. }
  705. var->red.length = 5;
  706. var->green.length = 5;
  707. var->blue.length = 5;
  708. break;
  709. case 24:
  710. if (isPReP) {
  711. var->red.offset = 8;
  712. var->green.offset = 16;
  713. var->blue.offset = 24;
  714. } else {
  715. var->red.offset = 16;
  716. var->green.offset = 8;
  717. var->blue.offset = 0;
  718. }
  719. var->red.length = 8;
  720. var->green.length = 8;
  721. var->blue.length = 8;
  722. break;
  723. case 32:
  724. if (isPReP) {
  725. var->red.offset = 8;
  726. var->green.offset = 16;
  727. var->blue.offset = 24;
  728. } else {
  729. var->red.offset = 16;
  730. var->green.offset = 8;
  731. var->blue.offset = 0;
  732. }
  733. var->red.length = 8;
  734. var->green.length = 8;
  735. var->blue.length = 8;
  736. break;
  737. default:
  738. DPRINTK("Unsupported bpp size: %d\n", var->bits_per_pixel);
  739. assert(false);
  740. /* should never occur */
  741. break;
  742. }
  743. var->red.msb_right =
  744. var->green.msb_right =
  745. var->blue.msb_right =
  746. var->transp.offset =
  747. var->transp.length =
  748. var->transp.msb_right = 0;
  749. yres = var->yres;
  750. if (var->vmode & FB_VMODE_DOUBLE)
  751. yres *= 2;
  752. else if (var->vmode & FB_VMODE_INTERLACED)
  753. yres = (yres + 1) / 2;
  754. if (yres >= 1280) {
  755. printk(KERN_ERR "cirrusfb: ERROR: VerticalTotal >= 1280; "
  756. "special treatment required! (TODO)\n");
  757. DPRINTK("EXIT - EINVAL error\n");
  758. return -EINVAL;
  759. }
  760. return 0;
  761. }
  762. static int cirrusfb_decode_var(const struct fb_var_screeninfo *var,
  763. struct cirrusfb_regs *regs,
  764. const struct fb_info *info)
  765. {
  766. long freq;
  767. long maxclock;
  768. int maxclockidx = 0;
  769. struct cirrusfb_info *cinfo = info->par;
  770. int xres, hfront, hsync, hback;
  771. int yres, vfront, vsync, vback;
  772. switch (var->bits_per_pixel) {
  773. case 1:
  774. regs->line_length = var->xres_virtual / 8;
  775. regs->visual = FB_VISUAL_MONO10;
  776. maxclockidx = 0;
  777. break;
  778. case 8:
  779. regs->line_length = var->xres_virtual;
  780. regs->visual = FB_VISUAL_PSEUDOCOLOR;
  781. maxclockidx = 1;
  782. break;
  783. case 16:
  784. regs->line_length = var->xres_virtual * 2;
  785. regs->visual = FB_VISUAL_DIRECTCOLOR;
  786. maxclockidx = 2;
  787. break;
  788. case 24:
  789. regs->line_length = var->xres_virtual * 3;
  790. regs->visual = FB_VISUAL_DIRECTCOLOR;
  791. maxclockidx = 3;
  792. break;
  793. case 32:
  794. regs->line_length = var->xres_virtual * 4;
  795. regs->visual = FB_VISUAL_DIRECTCOLOR;
  796. maxclockidx = 4;
  797. break;
  798. default:
  799. DPRINTK("Unsupported bpp size: %d\n", var->bits_per_pixel);
  800. assert(false);
  801. /* should never occur */
  802. break;
  803. }
  804. regs->type = FB_TYPE_PACKED_PIXELS;
  805. /* convert from ps to kHz */
  806. freq = 1000000000 / var->pixclock;
  807. DPRINTK("desired pixclock: %ld kHz\n", freq);
  808. maxclock = cirrusfb_board_info[cinfo->btype].maxclock[maxclockidx];
  809. regs->multiplexing = 0;
  810. /* If the frequency is greater than we can support, we might be able
  811. * to use multiplexing for the video mode */
  812. if (freq > maxclock) {
  813. switch (cinfo->btype) {
  814. case BT_ALPINE:
  815. case BT_GD5480:
  816. regs->multiplexing = 1;
  817. break;
  818. default:
  819. printk(KERN_ERR "cirrusfb: Frequency greater "
  820. "than maxclock (%ld kHz)\n", maxclock);
  821. DPRINTK("EXIT - return -EINVAL\n");
  822. return -EINVAL;
  823. }
  824. }
  825. #if 0
  826. /* TODO: If we have a 1MB 5434, we need to put ourselves in a mode where
  827. * the VCLK is double the pixel clock. */
  828. switch (var->bits_per_pixel) {
  829. case 16:
  830. case 32:
  831. if (regs->HorizRes <= 800)
  832. /* Xbh has this type of clock for 32-bit */
  833. freq /= 2;
  834. break;
  835. }
  836. #endif
  837. bestclock(freq, &regs->freq, &regs->nom, &regs->den, &regs->div,
  838. maxclock);
  839. regs->mclk = cirrusfb_get_mclk(freq, var->bits_per_pixel,
  840. &regs->divMCLK);
  841. xres = var->xres;
  842. hfront = var->right_margin;
  843. hsync = var->hsync_len;
  844. hback = var->left_margin;
  845. yres = var->yres;
  846. vfront = var->lower_margin;
  847. vsync = var->vsync_len;
  848. vback = var->upper_margin;
  849. if (var->vmode & FB_VMODE_DOUBLE) {
  850. yres *= 2;
  851. vfront *= 2;
  852. vsync *= 2;
  853. vback *= 2;
  854. } else if (var->vmode & FB_VMODE_INTERLACED) {
  855. yres = (yres + 1) / 2;
  856. vfront = (vfront + 1) / 2;
  857. vsync = (vsync + 1) / 2;
  858. vback = (vback + 1) / 2;
  859. }
  860. regs->HorizRes = xres;
  861. regs->HorizTotal = (xres + hfront + hsync + hback) / 8 - 5;
  862. regs->HorizDispEnd = xres / 8 - 1;
  863. regs->HorizBlankStart = xres / 8;
  864. /* does not count with "-5" */
  865. regs->HorizBlankEnd = regs->HorizTotal + 5;
  866. regs->HorizSyncStart = (xres + hfront) / 8 + 1;
  867. regs->HorizSyncEnd = (xres + hfront + hsync) / 8 + 1;
  868. regs->VertRes = yres;
  869. regs->VertTotal = yres + vfront + vsync + vback - 2;
  870. regs->VertDispEnd = yres - 1;
  871. regs->VertBlankStart = yres;
  872. regs->VertBlankEnd = regs->VertTotal;
  873. regs->VertSyncStart = yres + vfront - 1;
  874. regs->VertSyncEnd = yres + vfront + vsync - 1;
  875. if (regs->VertRes >= 1024) {
  876. regs->VertTotal /= 2;
  877. regs->VertSyncStart /= 2;
  878. regs->VertSyncEnd /= 2;
  879. regs->VertDispEnd /= 2;
  880. }
  881. if (regs->multiplexing) {
  882. regs->HorizTotal /= 2;
  883. regs->HorizSyncStart /= 2;
  884. regs->HorizSyncEnd /= 2;
  885. regs->HorizDispEnd /= 2;
  886. }
  887. return 0;
  888. }
  889. static void cirrusfb_set_mclk(const struct cirrusfb_info *cinfo, int val,
  890. int div)
  891. {
  892. assert(cinfo != NULL);
  893. if (div == 2) {
  894. /* VCLK = MCLK/2 */
  895. unsigned char old = vga_rseq(cinfo->regbase, CL_SEQR1E);
  896. vga_wseq(cinfo->regbase, CL_SEQR1E, old | 0x1);
  897. vga_wseq(cinfo->regbase, CL_SEQR1F, 0x40 | (val & 0x3f));
  898. } else if (div == 1) {
  899. /* VCLK = MCLK */
  900. unsigned char old = vga_rseq(cinfo->regbase, CL_SEQR1E);
  901. vga_wseq(cinfo->regbase, CL_SEQR1E, old & ~0x1);
  902. vga_wseq(cinfo->regbase, CL_SEQR1F, 0x40 | (val & 0x3f));
  903. } else {
  904. vga_wseq(cinfo->regbase, CL_SEQR1F, val & 0x3f);
  905. }
  906. }
  907. /*************************************************************************
  908. cirrusfb_set_par_foo()
  909. actually writes the values for a new video mode into the hardware,
  910. **************************************************************************/
  911. static int cirrusfb_set_par_foo(struct fb_info *info)
  912. {
  913. struct cirrusfb_info *cinfo = info->par;
  914. struct fb_var_screeninfo *var = &info->var;
  915. struct cirrusfb_regs regs;
  916. u8 __iomem *regbase = cinfo->regbase;
  917. unsigned char tmp;
  918. int offset = 0, err;
  919. const struct cirrusfb_board_info_rec *bi;
  920. DPRINTK("ENTER\n");
  921. DPRINTK("Requested mode: %dx%dx%d\n",
  922. var->xres, var->yres, var->bits_per_pixel);
  923. DPRINTK("pixclock: %d\n", var->pixclock);
  924. init_vgachip(cinfo);
  925. err = cirrusfb_decode_var(var, &regs, info);
  926. if (err) {
  927. /* should never happen */
  928. DPRINTK("mode change aborted. invalid var.\n");
  929. return -EINVAL;
  930. }
  931. bi = &cirrusfb_board_info[cinfo->btype];
  932. /* unlock register VGA_CRTC_H_TOTAL..CRT7 */
  933. vga_wcrt(regbase, VGA_CRTC_V_SYNC_END, 0x20); /* previously: 0x00) */
  934. /* if debugging is enabled, all parameters get output before writing */
  935. DPRINTK("CRT0: %ld\n", regs.HorizTotal);
  936. vga_wcrt(regbase, VGA_CRTC_H_TOTAL, regs.HorizTotal);
  937. DPRINTK("CRT1: %ld\n", regs.HorizDispEnd);
  938. vga_wcrt(regbase, VGA_CRTC_H_DISP, regs.HorizDispEnd);
  939. DPRINTK("CRT2: %ld\n", regs.HorizBlankStart);
  940. vga_wcrt(regbase, VGA_CRTC_H_BLANK_START, regs.HorizBlankStart);
  941. /* + 128: Compatible read */
  942. DPRINTK("CRT3: 128+%ld\n", regs.HorizBlankEnd % 32);
  943. vga_wcrt(regbase, VGA_CRTC_H_BLANK_END,
  944. 128 + (regs.HorizBlankEnd % 32));
  945. DPRINTK("CRT4: %ld\n", regs.HorizSyncStart);
  946. vga_wcrt(regbase, VGA_CRTC_H_SYNC_START, regs.HorizSyncStart);
  947. tmp = regs.HorizSyncEnd % 32;
  948. if (regs.HorizBlankEnd & 32)
  949. tmp += 128;
  950. DPRINTK("CRT5: %d\n", tmp);
  951. vga_wcrt(regbase, VGA_CRTC_H_SYNC_END, tmp);
  952. DPRINTK("CRT6: %ld\n", regs.VertTotal & 0xff);
  953. vga_wcrt(regbase, VGA_CRTC_V_TOTAL, (regs.VertTotal & 0xff));
  954. tmp = 16; /* LineCompare bit #9 */
  955. if (regs.VertTotal & 256)
  956. tmp |= 1;
  957. if (regs.VertDispEnd & 256)
  958. tmp |= 2;
  959. if (regs.VertSyncStart & 256)
  960. tmp |= 4;
  961. if (regs.VertBlankStart & 256)
  962. tmp |= 8;
  963. if (regs.VertTotal & 512)
  964. tmp |= 32;
  965. if (regs.VertDispEnd & 512)
  966. tmp |= 64;
  967. if (regs.VertSyncStart & 512)
  968. tmp |= 128;
  969. DPRINTK("CRT7: %d\n", tmp);
  970. vga_wcrt(regbase, VGA_CRTC_OVERFLOW, tmp);
  971. tmp = 0x40; /* LineCompare bit #8 */
  972. if (regs.VertBlankStart & 512)
  973. tmp |= 0x20;
  974. if (var->vmode & FB_VMODE_DOUBLE)
  975. tmp |= 0x80;
  976. DPRINTK("CRT9: %d\n", tmp);
  977. vga_wcrt(regbase, VGA_CRTC_MAX_SCAN, tmp);
  978. DPRINTK("CRT10: %ld\n", regs.VertSyncStart & 0xff);
  979. vga_wcrt(regbase, VGA_CRTC_V_SYNC_START, regs.VertSyncStart & 0xff);
  980. DPRINTK("CRT11: 64+32+%ld\n", regs.VertSyncEnd % 16);
  981. vga_wcrt(regbase, VGA_CRTC_V_SYNC_END, regs.VertSyncEnd % 16 + 64 + 32);
  982. DPRINTK("CRT12: %ld\n", regs.VertDispEnd & 0xff);
  983. vga_wcrt(regbase, VGA_CRTC_V_DISP_END, regs.VertDispEnd & 0xff);
  984. DPRINTK("CRT15: %ld\n", regs.VertBlankStart & 0xff);
  985. vga_wcrt(regbase, VGA_CRTC_V_BLANK_START, regs.VertBlankStart & 0xff);
  986. DPRINTK("CRT16: %ld\n", regs.VertBlankEnd & 0xff);
  987. vga_wcrt(regbase, VGA_CRTC_V_BLANK_END, regs.VertBlankEnd & 0xff);
  988. DPRINTK("CRT18: 0xff\n");
  989. vga_wcrt(regbase, VGA_CRTC_LINE_COMPARE, 0xff);
  990. tmp = 0;
  991. if (var->vmode & FB_VMODE_INTERLACED)
  992. tmp |= 1;
  993. if (regs.HorizBlankEnd & 64)
  994. tmp |= 16;
  995. if (regs.HorizBlankEnd & 128)
  996. tmp |= 32;
  997. if (regs.VertBlankEnd & 256)
  998. tmp |= 64;
  999. if (regs.VertBlankEnd & 512)
  1000. tmp |= 128;
  1001. DPRINTK("CRT1a: %d\n", tmp);
  1002. vga_wcrt(regbase, CL_CRT1A, tmp);
  1003. /* set VCLK0 */
  1004. /* hardware RefClock: 14.31818 MHz */
  1005. /* formula: VClk = (OSC * N) / (D * (1+P)) */
  1006. /* Example: VClk = (14.31818 * 91) / (23 * (1+1)) = 28.325 MHz */
  1007. vga_wseq(regbase, CL_SEQRB, regs.nom);
  1008. tmp = regs.den << 1;
  1009. if (regs.div != 0)
  1010. tmp |= 1;
  1011. /* 6 bit denom; ONLY 5434!!! (bugged me 10 days) */
  1012. if ((cinfo->btype == BT_SD64) ||
  1013. (cinfo->btype == BT_ALPINE) ||
  1014. (cinfo->btype == BT_GD5480))
  1015. tmp |= 0x80;
  1016. DPRINTK("CL_SEQR1B: %ld\n", (long) tmp);
  1017. vga_wseq(regbase, CL_SEQR1B, tmp);
  1018. if (regs.VertRes >= 1024)
  1019. /* 1280x1024 */
  1020. vga_wcrt(regbase, VGA_CRTC_MODE, 0xc7);
  1021. else
  1022. /* mode control: VGA_CRTC_START_HI enable, ROTATE(?), 16bit
  1023. * address wrap, no compat. */
  1024. vga_wcrt(regbase, VGA_CRTC_MODE, 0xc3);
  1025. /* HAEH? vga_wcrt(regbase, VGA_CRTC_V_SYNC_END, 0x20);
  1026. * previously: 0x00 unlock VGA_CRTC_H_TOTAL..CRT7 */
  1027. /* don't know if it would hurt to also program this if no interlaced */
  1028. /* mode is used, but I feel better this way.. :-) */
  1029. if (var->vmode & FB_VMODE_INTERLACED)
  1030. vga_wcrt(regbase, VGA_CRTC_REGS, regs.HorizTotal / 2);
  1031. else
  1032. vga_wcrt(regbase, VGA_CRTC_REGS, 0x00); /* interlace control */
  1033. vga_wseq(regbase, VGA_SEQ_CHARACTER_MAP, 0);
  1034. /* adjust horizontal/vertical sync type (low/high) */
  1035. /* enable display memory & CRTC I/O address for color mode */
  1036. tmp = 0x03;
  1037. if (var->sync & FB_SYNC_HOR_HIGH_ACT)
  1038. tmp |= 0x40;
  1039. if (var->sync & FB_SYNC_VERT_HIGH_ACT)
  1040. tmp |= 0x80;
  1041. WGen(cinfo, VGA_MIS_W, tmp);
  1042. /* Screen A Preset Row-Scan register */
  1043. vga_wcrt(regbase, VGA_CRTC_PRESET_ROW, 0);
  1044. /* text cursor on and start line */
  1045. vga_wcrt(regbase, VGA_CRTC_CURSOR_START, 0);
  1046. /* text cursor end line */
  1047. vga_wcrt(regbase, VGA_CRTC_CURSOR_END, 31);
  1048. /******************************************************
  1049. *
  1050. * 1 bpp
  1051. *
  1052. */
  1053. /* programming for different color depths */
  1054. if (var->bits_per_pixel == 1) {
  1055. DPRINTK("cirrusfb: preparing for 1 bit deep display\n");
  1056. vga_wgfx(regbase, VGA_GFX_MODE, 0); /* mode register */
  1057. /* SR07 */
  1058. switch (cinfo->btype) {
  1059. case BT_SD64:
  1060. case BT_PICCOLO:
  1061. case BT_PICASSO:
  1062. case BT_SPECTRUM:
  1063. case BT_PICASSO4:
  1064. case BT_ALPINE:
  1065. case BT_GD5480:
  1066. DPRINTK(" (for GD54xx)\n");
  1067. vga_wseq(regbase, CL_SEQR7,
  1068. regs.multiplexing ?
  1069. bi->sr07_1bpp_mux : bi->sr07_1bpp);
  1070. break;
  1071. case BT_LAGUNA:
  1072. DPRINTK(" (for GD546x)\n");
  1073. vga_wseq(regbase, CL_SEQR7,
  1074. vga_rseq(regbase, CL_SEQR7) & ~0x01);
  1075. break;
  1076. default:
  1077. printk(KERN_WARNING "cirrusfb: unknown Board\n");
  1078. break;
  1079. }
  1080. /* Extended Sequencer Mode */
  1081. switch (cinfo->btype) {
  1082. case BT_SD64:
  1083. /* setting the SEQRF on SD64 is not necessary
  1084. * (only during init)
  1085. */
  1086. DPRINTK("(for SD64)\n");
  1087. /* MCLK select */
  1088. vga_wseq(regbase, CL_SEQR1F, 0x1a);
  1089. break;
  1090. case BT_PICCOLO:
  1091. DPRINTK("(for Piccolo)\n");
  1092. /* ### ueberall 0x22? */
  1093. /* ##vorher 1c MCLK select */
  1094. vga_wseq(regbase, CL_SEQR1F, 0x22);
  1095. /* evtl d0 bei 1 bit? avoid FIFO underruns..? */
  1096. vga_wseq(regbase, CL_SEQRF, 0xb0);
  1097. break;
  1098. case BT_PICASSO:
  1099. DPRINTK("(for Picasso)\n");
  1100. /* ##vorher 22 MCLK select */
  1101. vga_wseq(regbase, CL_SEQR1F, 0x22);
  1102. /* ## vorher d0 avoid FIFO underruns..? */
  1103. vga_wseq(regbase, CL_SEQRF, 0xd0);
  1104. break;
  1105. case BT_SPECTRUM:
  1106. DPRINTK("(for Spectrum)\n");
  1107. /* ### ueberall 0x22? */
  1108. /* ##vorher 1c MCLK select */
  1109. vga_wseq(regbase, CL_SEQR1F, 0x22);
  1110. /* evtl d0? avoid FIFO underruns..? */
  1111. vga_wseq(regbase, CL_SEQRF, 0xb0);
  1112. break;
  1113. case BT_PICASSO4:
  1114. case BT_ALPINE:
  1115. case BT_GD5480:
  1116. case BT_LAGUNA:
  1117. DPRINTK(" (for GD54xx)\n");
  1118. /* do nothing */
  1119. break;
  1120. default:
  1121. printk(KERN_WARNING "cirrusfb: unknown Board\n");
  1122. break;
  1123. }
  1124. /* pixel mask: pass-through for first plane */
  1125. WGen(cinfo, VGA_PEL_MSK, 0x01);
  1126. if (regs.multiplexing)
  1127. /* hidden dac reg: 1280x1024 */
  1128. WHDR(cinfo, 0x4a);
  1129. else
  1130. /* hidden dac: nothing */
  1131. WHDR(cinfo, 0);
  1132. /* memory mode: odd/even, ext. memory */
  1133. vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, 0x06);
  1134. /* plane mask: only write to first plane */
  1135. vga_wseq(regbase, VGA_SEQ_PLANE_WRITE, 0x01);
  1136. offset = var->xres_virtual / 16;
  1137. }
  1138. /******************************************************
  1139. *
  1140. * 8 bpp
  1141. *
  1142. */
  1143. else if (var->bits_per_pixel == 8) {
  1144. DPRINTK("cirrusfb: preparing for 8 bit deep display\n");
  1145. switch (cinfo->btype) {
  1146. case BT_SD64:
  1147. case BT_PICCOLO:
  1148. case BT_PICASSO:
  1149. case BT_SPECTRUM:
  1150. case BT_PICASSO4:
  1151. case BT_ALPINE:
  1152. case BT_GD5480:
  1153. DPRINTK(" (for GD54xx)\n");
  1154. vga_wseq(regbase, CL_SEQR7,
  1155. regs.multiplexing ?
  1156. bi->sr07_8bpp_mux : bi->sr07_8bpp);
  1157. break;
  1158. case BT_LAGUNA:
  1159. DPRINTK(" (for GD546x)\n");
  1160. vga_wseq(regbase, CL_SEQR7,
  1161. vga_rseq(regbase, CL_SEQR7) | 0x01);
  1162. break;
  1163. default:
  1164. printk(KERN_WARNING "cirrusfb: unknown Board\n");
  1165. break;
  1166. }
  1167. switch (cinfo->btype) {
  1168. case BT_SD64:
  1169. /* MCLK select */
  1170. vga_wseq(regbase, CL_SEQR1F, 0x1d);
  1171. break;
  1172. case BT_PICCOLO:
  1173. /* ### vorher 1c MCLK select */
  1174. vga_wseq(regbase, CL_SEQR1F, 0x22);
  1175. /* Fast Page-Mode writes */
  1176. vga_wseq(regbase, CL_SEQRF, 0xb0);
  1177. break;
  1178. case BT_PICASSO:
  1179. /* ### vorher 1c MCLK select */
  1180. vga_wseq(regbase, CL_SEQR1F, 0x22);
  1181. /* Fast Page-Mode writes */
  1182. vga_wseq(regbase, CL_SEQRF, 0xb0);
  1183. break;
  1184. case BT_SPECTRUM:
  1185. /* ### vorher 1c MCLK select */
  1186. vga_wseq(regbase, CL_SEQR1F, 0x22);
  1187. /* Fast Page-Mode writes */
  1188. vga_wseq(regbase, CL_SEQRF, 0xb0);
  1189. break;
  1190. case BT_PICASSO4:
  1191. #ifdef CONFIG_ZORRO
  1192. /* ### INCOMPLETE!! */
  1193. vga_wseq(regbase, CL_SEQRF, 0xb8);
  1194. #endif
  1195. /* vga_wseq(regbase, CL_SEQR1F, 0x1c); */
  1196. break;
  1197. case BT_ALPINE:
  1198. DPRINTK(" (for GD543x)\n");
  1199. cirrusfb_set_mclk(cinfo, regs.mclk, regs.divMCLK);
  1200. /* We already set SRF and SR1F */
  1201. break;
  1202. case BT_GD5480:
  1203. case BT_LAGUNA:
  1204. DPRINTK(" (for GD54xx)\n");
  1205. /* do nothing */
  1206. break;
  1207. default:
  1208. printk(KERN_WARNING "cirrusfb: unknown Board\n");
  1209. break;
  1210. }
  1211. /* mode register: 256 color mode */
  1212. vga_wgfx(regbase, VGA_GFX_MODE, 64);
  1213. /* pixel mask: pass-through all planes */
  1214. WGen(cinfo, VGA_PEL_MSK, 0xff);
  1215. if (regs.multiplexing)
  1216. /* hidden dac reg: 1280x1024 */
  1217. WHDR(cinfo, 0x4a);
  1218. else
  1219. /* hidden dac: nothing */
  1220. WHDR(cinfo, 0);
  1221. /* memory mode: chain4, ext. memory */
  1222. vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, 0x0a);
  1223. /* plane mask: enable writing to all 4 planes */
  1224. vga_wseq(regbase, VGA_SEQ_PLANE_WRITE, 0xff);
  1225. offset = var->xres_virtual / 8;
  1226. }
  1227. /******************************************************
  1228. *
  1229. * 16 bpp
  1230. *
  1231. */
  1232. else if (var->bits_per_pixel == 16) {
  1233. DPRINTK("cirrusfb: preparing for 16 bit deep display\n");
  1234. switch (cinfo->btype) {
  1235. case BT_SD64:
  1236. /* Extended Sequencer Mode: 256c col. mode */
  1237. vga_wseq(regbase, CL_SEQR7, 0xf7);
  1238. /* MCLK select */
  1239. vga_wseq(regbase, CL_SEQR1F, 0x1e);
  1240. break;
  1241. case BT_PICCOLO:
  1242. vga_wseq(regbase, CL_SEQR7, 0x87);
  1243. /* Fast Page-Mode writes */
  1244. vga_wseq(regbase, CL_SEQRF, 0xb0);
  1245. /* MCLK select */
  1246. vga_wseq(regbase, CL_SEQR1F, 0x22);
  1247. break;
  1248. case BT_PICASSO:
  1249. vga_wseq(regbase, CL_SEQR7, 0x27);
  1250. /* Fast Page-Mode writes */
  1251. vga_wseq(regbase, CL_SEQRF, 0xb0);
  1252. /* MCLK select */
  1253. vga_wseq(regbase, CL_SEQR1F, 0x22);
  1254. break;
  1255. case BT_SPECTRUM:
  1256. vga_wseq(regbase, CL_SEQR7, 0x87);
  1257. /* Fast Page-Mode writes */
  1258. vga_wseq(regbase, CL_SEQRF, 0xb0);
  1259. /* MCLK select */
  1260. vga_wseq(regbase, CL_SEQR1F, 0x22);
  1261. break;
  1262. case BT_PICASSO4:
  1263. vga_wseq(regbase, CL_SEQR7, 0x27);
  1264. /* vga_wseq(regbase, CL_SEQR1F, 0x1c); */
  1265. break;
  1266. case BT_ALPINE:
  1267. DPRINTK(" (for GD543x)\n");
  1268. if (regs.HorizRes >= 1024)
  1269. vga_wseq(regbase, CL_SEQR7, 0xa7);
  1270. else
  1271. vga_wseq(regbase, CL_SEQR7, 0xa3);
  1272. cirrusfb_set_mclk(cinfo, regs.mclk, regs.divMCLK);
  1273. break;
  1274. case BT_GD5480:
  1275. DPRINTK(" (for GD5480)\n");
  1276. vga_wseq(regbase, CL_SEQR7, 0x17);
  1277. /* We already set SRF and SR1F */
  1278. break;
  1279. case BT_LAGUNA:
  1280. DPRINTK(" (for GD546x)\n");
  1281. vga_wseq(regbase, CL_SEQR7,
  1282. vga_rseq(regbase, CL_SEQR7) & ~0x01);
  1283. break;
  1284. default:
  1285. printk(KERN_WARNING "CIRRUSFB: unknown Board\n");
  1286. break;
  1287. }
  1288. /* mode register: 256 color mode */
  1289. vga_wgfx(regbase, VGA_GFX_MODE, 64);
  1290. /* pixel mask: pass-through all planes */
  1291. WGen(cinfo, VGA_PEL_MSK, 0xff);
  1292. #ifdef CONFIG_PCI
  1293. WHDR(cinfo, 0xc0); /* Copy Xbh */
  1294. #elif defined(CONFIG_ZORRO)
  1295. /* FIXME: CONFIG_PCI and CONFIG_ZORRO may be defined both */
  1296. WHDR(cinfo, 0xa0); /* hidden dac reg: nothing special */
  1297. #endif
  1298. /* memory mode: chain4, ext. memory */
  1299. vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, 0x0a);
  1300. /* plane mask: enable writing to all 4 planes */
  1301. vga_wseq(regbase, VGA_SEQ_PLANE_WRITE, 0xff);
  1302. offset = var->xres_virtual / 4;
  1303. }
  1304. /******************************************************
  1305. *
  1306. * 32 bpp
  1307. *
  1308. */
  1309. else if (var->bits_per_pixel == 32) {
  1310. DPRINTK("cirrusfb: preparing for 24/32 bit deep display\n");
  1311. switch (cinfo->btype) {
  1312. case BT_SD64:
  1313. /* Extended Sequencer Mode: 256c col. mode */
  1314. vga_wseq(regbase, CL_SEQR7, 0xf9);
  1315. /* MCLK select */
  1316. vga_wseq(regbase, CL_SEQR1F, 0x1e);
  1317. break;
  1318. case BT_PICCOLO:
  1319. vga_wseq(regbase, CL_SEQR7, 0x85);
  1320. /* Fast Page-Mode writes */
  1321. vga_wseq(regbase, CL_SEQRF, 0xb0);
  1322. /* MCLK select */
  1323. vga_wseq(regbase, CL_SEQR1F, 0x22);
  1324. break;
  1325. case BT_PICASSO:
  1326. vga_wseq(regbase, CL_SEQR7, 0x25);
  1327. /* Fast Page-Mode writes */
  1328. vga_wseq(regbase, CL_SEQRF, 0xb0);
  1329. /* MCLK select */
  1330. vga_wseq(regbase, CL_SEQR1F, 0x22);
  1331. break;
  1332. case BT_SPECTRUM:
  1333. vga_wseq(regbase, CL_SEQR7, 0x85);
  1334. /* Fast Page-Mode writes */
  1335. vga_wseq(regbase, CL_SEQRF, 0xb0);
  1336. /* MCLK select */
  1337. vga_wseq(regbase, CL_SEQR1F, 0x22);
  1338. break;
  1339. case BT_PICASSO4:
  1340. vga_wseq(regbase, CL_SEQR7, 0x25);
  1341. /* vga_wseq(regbase, CL_SEQR1F, 0x1c); */
  1342. break;
  1343. case BT_ALPINE:
  1344. DPRINTK(" (for GD543x)\n");
  1345. vga_wseq(regbase, CL_SEQR7, 0xa9);
  1346. cirrusfb_set_mclk(cinfo, regs.mclk, regs.divMCLK);
  1347. break;
  1348. case BT_GD5480:
  1349. DPRINTK(" (for GD5480)\n");
  1350. vga_wseq(regbase, CL_SEQR7, 0x19);
  1351. /* We already set SRF and SR1F */
  1352. break;
  1353. case BT_LAGUNA:
  1354. DPRINTK(" (for GD546x)\n");
  1355. vga_wseq(regbase, CL_SEQR7,
  1356. vga_rseq(regbase, CL_SEQR7) & ~0x01);
  1357. break;
  1358. default:
  1359. printk(KERN_WARNING "cirrusfb: unknown Board\n");
  1360. break;
  1361. }
  1362. /* mode register: 256 color mode */
  1363. vga_wgfx(regbase, VGA_GFX_MODE, 64);
  1364. /* pixel mask: pass-through all planes */
  1365. WGen(cinfo, VGA_PEL_MSK, 0xff);
  1366. /* hidden dac reg: 8-8-8 mode (24 or 32) */
  1367. WHDR(cinfo, 0xc5);
  1368. /* memory mode: chain4, ext. memory */
  1369. vga_wseq(regbase, VGA_SEQ_MEMORY_MODE, 0x0a);
  1370. /* plane mask: enable writing to all 4 planes */
  1371. vga_wseq(regbase, VGA_SEQ_PLANE_WRITE, 0xff);
  1372. offset = var->xres_virtual / 4;
  1373. }
  1374. /******************************************************
  1375. *
  1376. * unknown/unsupported bpp
  1377. *
  1378. */
  1379. else
  1380. printk(KERN_ERR "cirrusfb: What's this?? "
  1381. " requested color depth == %d.\n",
  1382. var->bits_per_pixel);
  1383. vga_wcrt(regbase, VGA_CRTC_OFFSET, offset & 0xff);
  1384. tmp = 0x22;
  1385. if (offset & 0x100)
  1386. tmp |= 0x10; /* offset overflow bit */
  1387. /* screen start addr #16-18, fastpagemode cycles */
  1388. vga_wcrt(regbase, CL_CRT1B, tmp);
  1389. if (cinfo->btype == BT_SD64 ||
  1390. cinfo->btype == BT_PICASSO4 ||
  1391. cinfo->btype == BT_ALPINE ||
  1392. cinfo->btype == BT_GD5480)
  1393. /* screen start address bit 19 */
  1394. vga_wcrt(regbase, CL_CRT1D, 0x00);
  1395. /* text cursor location high */
  1396. vga_wcrt(regbase, VGA_CRTC_CURSOR_HI, 0);
  1397. /* text cursor location low */
  1398. vga_wcrt(regbase, VGA_CRTC_CURSOR_LO, 0);
  1399. /* underline row scanline = at very bottom */
  1400. vga_wcrt(regbase, VGA_CRTC_UNDERLINE, 0);
  1401. /* controller mode */
  1402. vga_wattr(regbase, VGA_ATC_MODE, 1);
  1403. /* overscan (border) color */
  1404. vga_wattr(regbase, VGA_ATC_OVERSCAN, 0);
  1405. /* color plane enable */
  1406. vga_wattr(regbase, VGA_ATC_PLANE_ENABLE, 15);
  1407. /* pixel panning */
  1408. vga_wattr(regbase, CL_AR33, 0);
  1409. /* color select */
  1410. vga_wattr(regbase, VGA_ATC_COLOR_PAGE, 0);
  1411. /* [ EGS: SetOffset(); ] */
  1412. /* From SetOffset(): Turn on VideoEnable bit in Attribute controller */
  1413. AttrOn(cinfo);
  1414. /* set/reset register */
  1415. vga_wgfx(regbase, VGA_GFX_SR_VALUE, 0);
  1416. /* set/reset enable */
  1417. vga_wgfx(regbase, VGA_GFX_SR_ENABLE, 0);
  1418. /* color compare */
  1419. vga_wgfx(regbase, VGA_GFX_COMPARE_VALUE, 0);
  1420. /* data rotate */
  1421. vga_wgfx(regbase, VGA_GFX_DATA_ROTATE, 0);
  1422. /* read map select */
  1423. vga_wgfx(regbase, VGA_GFX_PLANE_READ, 0);
  1424. /* miscellaneous register */
  1425. vga_wgfx(regbase, VGA_GFX_MISC, 1);
  1426. /* color don't care */
  1427. vga_wgfx(regbase, VGA_GFX_COMPARE_MASK, 15);
  1428. /* bit mask */
  1429. vga_wgfx(regbase, VGA_GFX_BIT_MASK, 255);
  1430. /* graphics cursor attributes: nothing special */
  1431. vga_wseq(regbase, CL_SEQR12, 0x0);
  1432. /* finally, turn on everything - turn off "FullBandwidth" bit */
  1433. /* also, set "DotClock%2" bit where requested */
  1434. tmp = 0x01;
  1435. /*** FB_VMODE_CLOCK_HALVE in linux/fb.h not defined anymore ?
  1436. if (var->vmode & FB_VMODE_CLOCK_HALVE)
  1437. tmp |= 0x08;
  1438. */
  1439. vga_wseq(regbase, VGA_SEQ_CLOCK_MODE, tmp);
  1440. DPRINTK("CL_SEQR1: %d\n", tmp);
  1441. cinfo->currentmode = regs;
  1442. info->fix.type = regs.type;
  1443. info->fix.visual = regs.visual;
  1444. info->fix.line_length = regs.line_length;
  1445. /* pan to requested offset */
  1446. cirrusfb_pan_display(var, info);
  1447. #ifdef CIRRUSFB_DEBUG
  1448. cirrusfb_dump();
  1449. #endif
  1450. DPRINTK("EXIT\n");
  1451. return 0;
  1452. }
  1453. /* for some reason incomprehensible to me, cirrusfb requires that you write
  1454. * the registers twice for the settings to take..grr. -dte */
  1455. static int cirrusfb_set_par(struct fb_info *info)
  1456. {
  1457. cirrusfb_set_par_foo(info);
  1458. return cirrusfb_set_par_foo(info);
  1459. }
  1460. static int cirrusfb_setcolreg(unsigned regno, unsigned red, unsigned green,
  1461. unsigned blue, unsigned transp,
  1462. struct fb_info *info)
  1463. {
  1464. struct cirrusfb_info *cinfo = info->par;
  1465. if (regno > 255)
  1466. return -EINVAL;
  1467. if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
  1468. u32 v;
  1469. red >>= (16 - info->var.red.length);
  1470. green >>= (16 - info->var.green.length);
  1471. blue >>= (16 - info->var.blue.length);
  1472. if (regno >= 16)
  1473. return 1;
  1474. v = (red << info->var.red.offset) |
  1475. (green << info->var.green.offset) |
  1476. (blue << info->var.blue.offset);
  1477. switch (info->var.bits_per_pixel) {
  1478. case 8:
  1479. cinfo->pseudo_palette[regno] = v;
  1480. break;
  1481. case 16:
  1482. cinfo->pseudo_palette[regno] = v;
  1483. break;
  1484. case 24:
  1485. case 32:
  1486. cinfo->pseudo_palette[regno] = v;
  1487. break;
  1488. }
  1489. return 0;
  1490. }
  1491. cinfo->palette[regno].red = red;
  1492. cinfo->palette[regno].green = green;
  1493. cinfo->palette[regno].blue = blue;
  1494. if (info->var.bits_per_pixel == 8)
  1495. WClut(cinfo, regno, red >> 10, green >> 10, blue >> 10);
  1496. return 0;
  1497. }
  1498. /*************************************************************************
  1499. cirrusfb_pan_display()
  1500. performs display panning - provided hardware permits this
  1501. **************************************************************************/
  1502. static int cirrusfb_pan_display(struct fb_var_screeninfo *var,
  1503. struct fb_info *info)
  1504. {
  1505. int xoffset = 0;
  1506. int yoffset = 0;
  1507. unsigned long base;
  1508. unsigned char tmp = 0, tmp2 = 0, xpix;
  1509. struct cirrusfb_info *cinfo = info->par;
  1510. DPRINTK("ENTER\n");
  1511. DPRINTK("virtual offset: (%d,%d)\n", var->xoffset, var->yoffset);
  1512. /* no range checks for xoffset and yoffset, */
  1513. /* as fb_pan_display has already done this */
  1514. if (var->vmode & FB_VMODE_YWRAP)
  1515. return -EINVAL;
  1516. info->var.xoffset = var->xoffset;
  1517. info->var.yoffset = var->yoffset;
  1518. xoffset = var->xoffset * info->var.bits_per_pixel / 8;
  1519. yoffset = var->yoffset;
  1520. base = yoffset * cinfo->currentmode.line_length + xoffset;
  1521. if (info->var.bits_per_pixel == 1) {
  1522. /* base is already correct */
  1523. xpix = (unsigned char) (var->xoffset % 8);
  1524. } else {
  1525. base /= 4;
  1526. xpix = (unsigned char) ((xoffset % 4) * 2);
  1527. }
  1528. cirrusfb_WaitBLT(cinfo->regbase); /* make sure all the BLT's are done */
  1529. /* lower 8 + 8 bits of screen start address */
  1530. vga_wcrt(cinfo->regbase, VGA_CRTC_START_LO,
  1531. (unsigned char) (base & 0xff));
  1532. vga_wcrt(cinfo->regbase, VGA_CRTC_START_HI,
  1533. (unsigned char) (base >> 8));
  1534. /* construct bits 16, 17 and 18 of screen start address */
  1535. if (base & 0x10000)
  1536. tmp |= 0x01;
  1537. if (base & 0x20000)
  1538. tmp |= 0x04;
  1539. if (base & 0x40000)
  1540. tmp |= 0x08;
  1541. /* 0xf2 is %11110010, exclude tmp bits */
  1542. tmp2 = (vga_rcrt(cinfo->regbase, CL_CRT1B) & 0xf2) | tmp;
  1543. vga_wcrt(cinfo->regbase, CL_CRT1B, tmp2);
  1544. /* construct bit 19 of screen start address */
  1545. if (cirrusfb_board_info[cinfo->btype].scrn_start_bit19) {
  1546. tmp2 = 0;
  1547. if (base & 0x80000)
  1548. tmp2 = 0x80;
  1549. vga_wcrt(cinfo->regbase, CL_CRT1D, tmp2);
  1550. }
  1551. /* write pixel panning value to AR33; this does not quite work in 8bpp
  1552. *
  1553. * ### Piccolo..? Will this work?
  1554. */
  1555. if (info->var.bits_per_pixel == 1)
  1556. vga_wattr(cinfo->regbase, CL_AR33, xpix);
  1557. cirrusfb_WaitBLT(cinfo->regbase);
  1558. DPRINTK("EXIT\n");
  1559. return 0;
  1560. }
  1561. static int cirrusfb_blank(int blank_mode, struct fb_info *info)
  1562. {
  1563. /*
  1564. * Blank the screen if blank_mode != 0, else unblank. If blank == NULL
  1565. * then the caller blanks by setting the CLUT (Color Look Up Table)
  1566. * to all black. Return 0 if blanking succeeded, != 0 if un-/blanking
  1567. * failed due to e.g. a video mode which doesn't support it.
  1568. * Implements VESA suspend and powerdown modes on hardware that
  1569. * supports disabling hsync/vsync:
  1570. * blank_mode == 2: suspend vsync
  1571. * blank_mode == 3: suspend hsync
  1572. * blank_mode == 4: powerdown
  1573. */
  1574. unsigned char val;
  1575. struct cirrusfb_info *cinfo = info->par;
  1576. int current_mode = cinfo->blank_mode;
  1577. DPRINTK("ENTER, blank mode = %d\n", blank_mode);
  1578. if (info->state != FBINFO_STATE_RUNNING ||
  1579. current_mode == blank_mode) {
  1580. DPRINTK("EXIT, returning 0\n");
  1581. return 0;
  1582. }
  1583. /* Undo current */
  1584. if (current_mode == FB_BLANK_NORMAL ||
  1585. current_mode == FB_BLANK_UNBLANK) {
  1586. /* unblank the screen */
  1587. val = vga_rseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE);
  1588. /* clear "FullBandwidth" bit */
  1589. vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, val & 0xdf);
  1590. /* and undo VESA suspend trickery */
  1591. vga_wgfx(cinfo->regbase, CL_GRE, 0x00);
  1592. }
  1593. /* set new */
  1594. if (blank_mode > FB_BLANK_NORMAL) {
  1595. /* blank the screen */
  1596. val = vga_rseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE);
  1597. /* set "FullBandwidth" bit */
  1598. vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, val | 0x20);
  1599. }
  1600. switch (blank_mode) {
  1601. case FB_BLANK_UNBLANK:
  1602. case FB_BLANK_NORMAL:
  1603. break;
  1604. case FB_BLANK_VSYNC_SUSPEND:
  1605. vga_wgfx(cinfo->regbase, CL_GRE, 0x04);
  1606. break;
  1607. case FB_BLANK_HSYNC_SUSPEND:
  1608. vga_wgfx(cinfo->regbase, CL_GRE, 0x02);
  1609. break;
  1610. case FB_BLANK_POWERDOWN:
  1611. vga_wgfx(cinfo->regbase, CL_GRE, 0x06);
  1612. break;
  1613. default:
  1614. DPRINTK("EXIT, returning 1\n");
  1615. return 1;
  1616. }
  1617. cinfo->blank_mode = blank_mode;
  1618. DPRINTK("EXIT, returning 0\n");
  1619. /* Let fbcon do a soft blank for us */
  1620. return (blank_mode == FB_BLANK_NORMAL) ? 1 : 0;
  1621. }
  1622. /**** END Hardware specific Routines **************************************/
  1623. /****************************************************************************/
  1624. /**** BEGIN Internal Routines ***********************************************/
  1625. static void init_vgachip(struct cirrusfb_info *cinfo)
  1626. {
  1627. const struct cirrusfb_board_info_rec *bi;
  1628. DPRINTK("ENTER\n");
  1629. assert(cinfo != NULL);
  1630. bi = &cirrusfb_board_info[cinfo->btype];
  1631. /* reset board globally */
  1632. switch (cinfo->btype) {
  1633. case BT_PICCOLO:
  1634. WSFR(cinfo, 0x01);
  1635. udelay(500);
  1636. WSFR(cinfo, 0x51);
  1637. udelay(500);
  1638. break;
  1639. case BT_PICASSO:
  1640. WSFR2(cinfo, 0xff);
  1641. udelay(500);
  1642. break;
  1643. case BT_SD64:
  1644. case BT_SPECTRUM:
  1645. WSFR(cinfo, 0x1f);
  1646. udelay(500);
  1647. WSFR(cinfo, 0x4f);
  1648. udelay(500);
  1649. break;
  1650. case BT_PICASSO4:
  1651. /* disable flickerfixer */
  1652. vga_wcrt(cinfo->regbase, CL_CRT51, 0x00);
  1653. mdelay(100);
  1654. /* from Klaus' NetBSD driver: */
  1655. vga_wgfx(cinfo->regbase, CL_GR2F, 0x00);
  1656. /* put blitter into 542x compat */
  1657. vga_wgfx(cinfo->regbase, CL_GR33, 0x00);
  1658. /* mode */
  1659. vga_wgfx(cinfo->regbase, CL_GR31, 0x00);
  1660. break;
  1661. case BT_GD5480:
  1662. /* from Klaus' NetBSD driver: */
  1663. vga_wgfx(cinfo->regbase, CL_GR2F, 0x00);
  1664. break;
  1665. case BT_ALPINE:
  1666. /* Nothing to do to reset the board. */
  1667. break;
  1668. default:
  1669. printk(KERN_ERR "cirrusfb: Warning: Unknown board type\n");
  1670. break;
  1671. }
  1672. assert(cinfo->size > 0); /* make sure RAM size set by this point */
  1673. /* the P4 is not fully initialized here; I rely on it having been */
  1674. /* inited under AmigaOS already, which seems to work just fine */
  1675. /* (Klaus advised to do it this way) */
  1676. if (cinfo->btype != BT_PICASSO4) {
  1677. WGen(cinfo, CL_VSSM, 0x10); /* EGS: 0x16 */
  1678. WGen(cinfo, CL_POS102, 0x01);
  1679. WGen(cinfo, CL_VSSM, 0x08); /* EGS: 0x0e */
  1680. if (cinfo->btype != BT_SD64)
  1681. WGen(cinfo, CL_VSSM2, 0x01);
  1682. /* reset sequencer logic */
  1683. vga_wseq(cinfo->regbase, CL_SEQR0, 0x03);
  1684. /* FullBandwidth (video off) and 8/9 dot clock */
  1685. vga_wseq(cinfo->regbase, VGA_SEQ_CLOCK_MODE, 0x21);
  1686. /* polarity (-/-), disable access to display memory,
  1687. * VGA_CRTC_START_HI base address: color
  1688. */
  1689. WGen(cinfo, VGA_MIS_W, 0xc1);
  1690. /* "magic cookie" - doesn't make any sense to me.. */
  1691. /* vga_wgfx(cinfo->regbase, CL_GRA, 0xce); */
  1692. /* unlock all extension registers */
  1693. vga_wseq(cinfo->regbase, CL_SEQR6, 0x12);
  1694. /* reset blitter */
  1695. vga_wgfx(cinfo->regbase, CL_GR31, 0x04);
  1696. switch (cinfo->btype) {
  1697. case BT_GD5480:
  1698. vga_wseq(cinfo->regbase, CL_SEQRF, 0x98);
  1699. break;
  1700. case BT_ALPINE:
  1701. break;
  1702. case BT_SD64:
  1703. vga_wseq(cinfo->regbase, CL_SEQRF, 0xb8);
  1704. break;
  1705. default:
  1706. vga_wseq(cinfo->regbase, CL_SEQR16, 0x0f);
  1707. vga_wseq(cinfo->regbase, CL_SEQRF, 0xb0);
  1708. break;
  1709. }
  1710. }
  1711. /* plane mask: nothing */
  1712. vga_wseq(cinfo->regbase, VGA_SEQ_PLANE_WRITE, 0xff);
  1713. /* character map select: doesn't even matter in gx mode */
  1714. vga_wseq(cinfo->regbase, VGA_SEQ_CHARACTER_MAP, 0x00);
  1715. /* memory mode: chain-4, no odd/even, ext. memory */
  1716. vga_wseq(cinfo->regbase, VGA_SEQ_MEMORY_MODE, 0x0e);
  1717. /* controller-internal base address of video memory */
  1718. if (bi->init_sr07)
  1719. vga_wseq(cinfo->regbase, CL_SEQR7, bi->sr07);
  1720. /* vga_wseq(cinfo->regbase, CL_SEQR8, 0x00); */
  1721. /* EEPROM control: shouldn't be necessary to write to this at all.. */
  1722. /* graphics cursor X position (incomplete; position gives rem. 3 bits */
  1723. vga_wseq(cinfo->regbase, CL_SEQR10, 0x00);
  1724. /* graphics cursor Y position (..."... ) */
  1725. vga_wseq(cinfo->regbase, CL_SEQR11, 0x00);
  1726. /* graphics cursor attributes */
  1727. vga_wseq(cinfo->regbase, CL_SEQR12, 0x00);
  1728. /* graphics cursor pattern address */
  1729. vga_wseq(cinfo->regbase, CL_SEQR13, 0x00);
  1730. /* writing these on a P4 might give problems.. */
  1731. if (cinfo->btype != BT_PICASSO4) {
  1732. /* configuration readback and ext. color */
  1733. vga_wseq(cinfo->regbase, CL_SEQR17, 0x00);
  1734. /* signature generator */
  1735. vga_wseq(cinfo->regbase, CL_SEQR18, 0x02);
  1736. }
  1737. /* MCLK select etc. */
  1738. if (bi->init_sr1f)
  1739. vga_wseq(cinfo->regbase, CL_SEQR1F, bi->sr1f);
  1740. /* Screen A preset row scan: none */
  1741. vga_wcrt(cinfo->regbase, VGA_CRTC_PRESET_ROW, 0x00);
  1742. /* Text cursor start: disable text cursor */
  1743. vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_START, 0x20);
  1744. /* Text cursor end: - */
  1745. vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_END, 0x00);
  1746. /* Screen start address high: 0 */
  1747. vga_wcrt(cinfo->regbase, VGA_CRTC_START_HI, 0x00);
  1748. /* Screen start address low: 0 */
  1749. vga_wcrt(cinfo->regbase, VGA_CRTC_START_LO, 0x00);
  1750. /* text cursor location high: 0 */
  1751. vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_HI, 0x00);
  1752. /* text cursor location low: 0 */
  1753. vga_wcrt(cinfo->regbase, VGA_CRTC_CURSOR_LO, 0x00);
  1754. /* Underline Row scanline: - */
  1755. vga_wcrt(cinfo->regbase, VGA_CRTC_UNDERLINE, 0x00);
  1756. /* mode control: timing enable, byte mode, no compat modes */
  1757. vga_wcrt(cinfo->regbase, VGA_CRTC_MODE, 0xc3);
  1758. /* Line Compare: not needed */
  1759. vga_wcrt(cinfo->regbase, VGA_CRTC_LINE_COMPARE, 0x00);
  1760. /* ### add 0x40 for text modes with > 30 MHz pixclock */
  1761. /* ext. display controls: ext.adr. wrap */
  1762. vga_wcrt(cinfo->regbase, CL_CRT1B, 0x02);
  1763. /* Set/Reset registes: - */
  1764. vga_wgfx(cinfo->regbase, VGA_GFX_SR_VALUE, 0x00);
  1765. /* Set/Reset enable: - */
  1766. vga_wgfx(cinfo->regbase, VGA_GFX_SR_ENABLE, 0x00);
  1767. /* Color Compare: - */
  1768. vga_wgfx(cinfo->regbase, VGA_GFX_COMPARE_VALUE, 0x00);
  1769. /* Data Rotate: - */
  1770. vga_wgfx(cinfo->regbase, VGA_GFX_DATA_ROTATE, 0x00);
  1771. /* Read Map Select: - */
  1772. vga_wgfx(cinfo->regbase, VGA_GFX_PLANE_READ, 0x00);
  1773. /* Mode: conf. for 16/4/2 color mode, no odd/even, read/write mode 0 */
  1774. vga_wgfx(cinfo->regbase, VGA_GFX_MODE, 0x00);
  1775. /* Miscellaneous: memory map base address, graphics mode */
  1776. vga_wgfx(cinfo->regbase, VGA_GFX_MISC, 0x01);
  1777. /* Color Don't care: involve all planes */
  1778. vga_wgfx(cinfo->regbase, VGA_GFX_COMPARE_MASK, 0x0f);
  1779. /* Bit Mask: no mask at all */
  1780. vga_wgfx(cinfo->regbase, VGA_GFX_BIT_MASK, 0xff);
  1781. if (cinfo->btype == BT_ALPINE)
  1782. /* (5434 can't have bit 3 set for bitblt) */
  1783. vga_wgfx(cinfo->regbase, CL_GRB, 0x20);
  1784. else
  1785. /* Graphics controller mode extensions: finer granularity,
  1786. * 8byte data latches
  1787. */
  1788. vga_wgfx(cinfo->regbase, CL_GRB, 0x28);
  1789. vga_wgfx(cinfo->regbase, CL_GRC, 0xff); /* Color Key compare: - */
  1790. vga_wgfx(cinfo->regbase, CL_GRD, 0x00); /* Color Key compare mask: - */
  1791. vga_wgfx(cinfo->regbase, CL_GRE, 0x00); /* Miscellaneous control: - */
  1792. /* Background color byte 1: - */
  1793. /* vga_wgfx (cinfo->regbase, CL_GR10, 0x00); */
  1794. /* vga_wgfx (cinfo->regbase, CL_GR11, 0x00); */
  1795. /* Attribute Controller palette registers: "identity mapping" */
  1796. vga_wattr(cinfo->regbase, VGA_ATC_PALETTE0, 0x00);
  1797. vga_wattr(cinfo->regbase, VGA_ATC_PALETTE1, 0x01);
  1798. vga_wattr(cinfo->regbase, VGA_ATC_PALETTE2, 0x02);
  1799. vga_wattr(cinfo->regbase, VGA_ATC_PALETTE3, 0x03);
  1800. vga_wattr(cinfo->regbase, VGA_ATC_PALETTE4, 0x04);
  1801. vga_wattr(cinfo->regbase, VGA_ATC_PALETTE5, 0x05);
  1802. vga_wattr(cinfo->regbase, VGA_ATC_PALETTE6, 0x06);
  1803. vga_wattr(cinfo->regbase, VGA_ATC_PALETTE7, 0x07);
  1804. vga_wattr(cinfo->regbase, VGA_ATC_PALETTE8, 0x08);
  1805. vga_wattr(cinfo->regbase, VGA_ATC_PALETTE9, 0x09);
  1806. vga_wattr(cinfo->regbase, VGA_ATC_PALETTEA, 0x0a);
  1807. vga_wattr(cinfo->regbase, VGA_ATC_PALETTEB, 0x0b);
  1808. vga_wattr(cinfo->regbase, VGA_ATC_PALETTEC, 0x0c);
  1809. vga_wattr(cinfo->regbase, VGA_ATC_PALETTED, 0x0d);
  1810. vga_wattr(cinfo->regbase, VGA_ATC_PALETTEE, 0x0e);
  1811. vga_wattr(cinfo->regbase, VGA_ATC_PALETTEF, 0x0f);
  1812. /* Attribute Controller mode: graphics mode */
  1813. vga_wattr(cinfo->regbase, VGA_ATC_MODE, 0x01);
  1814. /* Overscan color reg.: reg. 0 */
  1815. vga_wattr(cinfo->regbase, VGA_ATC_OVERSCAN, 0x00);
  1816. /* Color Plane enable: Enable all 4 planes */
  1817. vga_wattr(cinfo->regbase, VGA_ATC_PLANE_ENABLE, 0x0f);
  1818. /* ### vga_wattr(cinfo->regbase, CL_AR33, 0x00); * Pixel Panning: - */
  1819. /* Color Select: - */
  1820. vga_wattr(cinfo->regbase, VGA_ATC_COLOR_PAGE, 0x00);
  1821. WGen(cinfo, VGA_PEL_MSK, 0xff); /* Pixel mask: no mask */
  1822. if (cinfo->btype != BT_ALPINE && cinfo->btype != BT_GD5480)
  1823. /* polarity (-/-), enable display mem,
  1824. * VGA_CRTC_START_HI i/o base = color
  1825. */
  1826. WGen(cinfo, VGA_MIS_W, 0xc3);
  1827. /* BLT Start/status: Blitter reset */
  1828. vga_wgfx(cinfo->regbase, CL_GR31, 0x04);
  1829. /* - " - : "end-of-reset" */
  1830. vga_wgfx(cinfo->regbase, CL_GR31, 0x00);
  1831. /* misc... */
  1832. WHDR(cinfo, 0); /* Hidden DAC register: - */
  1833. printk(KERN_DEBUG "cirrusfb: This board has %ld bytes of DRAM memory\n",
  1834. cinfo->size);
  1835. DPRINTK("EXIT\n");
  1836. return;
  1837. }
  1838. static void switch_monitor(struct cirrusfb_info *cinfo, int on)
  1839. {
  1840. #ifdef CONFIG_ZORRO /* only works on Zorro boards */
  1841. static int IsOn = 0; /* XXX not ok for multiple boards */
  1842. DPRINTK("ENTER\n");
  1843. if (cinfo->btype == BT_PICASSO4)
  1844. return; /* nothing to switch */
  1845. if (cinfo->btype == BT_ALPINE)
  1846. return; /* nothing to switch */
  1847. if (cinfo->btype == BT_GD5480)
  1848. return; /* nothing to switch */
  1849. if (cinfo->btype == BT_PICASSO) {
  1850. if ((on && !IsOn) || (!on && IsOn))
  1851. WSFR(cinfo, 0xff);
  1852. DPRINTK("EXIT\n");
  1853. return;
  1854. }
  1855. if (on) {
  1856. switch (cinfo->btype) {
  1857. case BT_SD64:
  1858. WSFR(cinfo, cinfo->SFR | 0x21);
  1859. break;
  1860. case BT_PICCOLO:
  1861. WSFR(cinfo, cinfo->SFR | 0x28);
  1862. break;
  1863. case BT_SPECTRUM:
  1864. WSFR(cinfo, 0x6f);
  1865. break;
  1866. default: /* do nothing */ break;
  1867. }
  1868. } else {
  1869. switch (cinfo->btype) {
  1870. case BT_SD64:
  1871. WSFR(cinfo, cinfo->SFR & 0xde);
  1872. break;
  1873. case BT_PICCOLO:
  1874. WSFR(cinfo, cinfo->SFR & 0xd7);
  1875. break;
  1876. case BT_SPECTRUM:
  1877. WSFR(cinfo, 0x4f);
  1878. break;
  1879. default: /* do nothing */ break;
  1880. }
  1881. }
  1882. DPRINTK("EXIT\n");
  1883. #endif /* CONFIG_ZORRO */
  1884. }
  1885. /******************************************/
  1886. /* Linux 2.6-style accelerated functions */
  1887. /******************************************/
  1888. static void cirrusfb_prim_fillrect(struct cirrusfb_info *cinfo,
  1889. const struct fb_fillrect *region)
  1890. {
  1891. int m; /* bytes per pixel */
  1892. u32 color = (cinfo->info->fix.visual == FB_VISUAL_TRUECOLOR) ?
  1893. cinfo->pseudo_palette[region->color] : region->color;
  1894. if (cinfo->info->var.bits_per_pixel == 1) {
  1895. cirrusfb_RectFill(cinfo->regbase,
  1896. cinfo->info->var.bits_per_pixel,
  1897. region->dx / 8, region->dy,
  1898. region->width / 8, region->height,
  1899. color,
  1900. cinfo->currentmode.line_length);
  1901. } else {
  1902. m = (cinfo->info->var.bits_per_pixel + 7) / 8;
  1903. cirrusfb_RectFill(cinfo->regbase,
  1904. cinfo->info->var.bits_per_pixel,
  1905. region->dx * m, region->dy,
  1906. region->width * m, region->height,
  1907. color,
  1908. cinfo->currentmode.line_length);
  1909. }
  1910. return;
  1911. }
  1912. static void cirrusfb_fillrect(struct fb_info *info,
  1913. const struct fb_fillrect *region)
  1914. {
  1915. struct cirrusfb_info *cinfo = info->par;
  1916. struct fb_fillrect modded;
  1917. int vxres, vyres;
  1918. if (info->state != FBINFO_STATE_RUNNING)
  1919. return;
  1920. if (info->flags & FBINFO_HWACCEL_DISABLED) {
  1921. cfb_fillrect(info, region);
  1922. return;
  1923. }
  1924. vxres = info->var.xres_virtual;
  1925. vyres = info->var.yres_virtual;
  1926. memcpy(&modded, region, sizeof(struct fb_fillrect));
  1927. if (!modded.width || !modded.height ||
  1928. modded.dx >= vxres || modded.dy >= vyres)
  1929. return;
  1930. if (modded.dx + modded.width > vxres)
  1931. modded.width = vxres - modded.dx;
  1932. if (modded.dy + modded.height > vyres)
  1933. modded.height = vyres - modded.dy;
  1934. cirrusfb_prim_fillrect(cinfo, &modded);
  1935. }
  1936. static void cirrusfb_prim_copyarea(struct cirrusfb_info *cinfo,
  1937. const struct fb_copyarea *area)
  1938. {
  1939. int m; /* bytes per pixel */
  1940. if (cinfo->info->var.bits_per_pixel == 1) {
  1941. cirrusfb_BitBLT(cinfo->regbase, cinfo->info->var.bits_per_pixel,
  1942. area->sx / 8, area->sy,
  1943. area->dx / 8, area->dy,
  1944. area->width / 8, area->height,
  1945. cinfo->currentmode.line_length);
  1946. } else {
  1947. m = (cinfo->info->var.bits_per_pixel + 7) / 8;
  1948. cirrusfb_BitBLT(cinfo->regbase, cinfo->info->var.bits_per_pixel,
  1949. area->sx * m, area->sy,
  1950. area->dx * m, area->dy,
  1951. area->width * m, area->height,
  1952. cinfo->currentmode.line_length);
  1953. }
  1954. return;
  1955. }
  1956. static void cirrusfb_copyarea(struct fb_info *info,
  1957. const struct fb_copyarea *area)
  1958. {
  1959. struct cirrusfb_info *cinfo = info->par;
  1960. struct fb_copyarea modded;
  1961. u32 vxres, vyres;
  1962. modded.sx = area->sx;
  1963. modded.sy = area->sy;
  1964. modded.dx = area->dx;
  1965. modded.dy = area->dy;
  1966. modded.width = area->width;
  1967. modded.height = area->height;
  1968. if (info->state != FBINFO_STATE_RUNNING)
  1969. return;
  1970. if (info->flags & FBINFO_HWACCEL_DISABLED) {
  1971. cfb_copyarea(info, area);
  1972. return;
  1973. }
  1974. vxres = info->var.xres_virtual;
  1975. vyres = info->var.yres_virtual;
  1976. if (!modded.width || !modded.height ||
  1977. modded.sx >= vxres || modded.sy >= vyres ||
  1978. modded.dx >= vxres || modded.dy >= vyres)
  1979. return;
  1980. if (modded.sx + modded.width > vxres)
  1981. modded.width = vxres - modded.sx;
  1982. if (modded.dx + modded.width > vxres)
  1983. modded.width = vxres - modded.dx;
  1984. if (modded.sy + modded.height > vyres)
  1985. modded.height = vyres - modded.sy;
  1986. if (modded.dy + modded.height > vyres)
  1987. modded.height = vyres - modded.dy;
  1988. cirrusfb_prim_copyarea(cinfo, &modded);
  1989. }
  1990. static void cirrusfb_imageblit(struct fb_info *info,
  1991. const struct fb_image *image)
  1992. {
  1993. struct cirrusfb_info *cinfo = info->par;
  1994. cirrusfb_WaitBLT(cinfo->regbase);
  1995. cfb_imageblit(info, image);
  1996. }
  1997. #ifdef CONFIG_PPC_PREP
  1998. #define PREP_VIDEO_BASE ((volatile unsigned long) 0xC0000000)
  1999. #define PREP_IO_BASE ((volatile unsigned char *) 0x80000000)
  2000. static void get_prep_addrs(unsigned long *display, unsigned long *registers)
  2001. {
  2002. DPRINTK("ENTER\n");
  2003. *display = PREP_VIDEO_BASE;
  2004. *registers = (unsigned long) PREP_IO_BASE;
  2005. DPRINTK("EXIT\n");
  2006. }
  2007. #endif /* CONFIG_PPC_PREP */
  2008. #ifdef CONFIG_PCI
  2009. static int release_io_ports;
  2010. /* Pulled the logic from XFree86 Cirrus driver to get the memory size,
  2011. * based on the DRAM bandwidth bit and DRAM bank switching bit. This
  2012. * works with 1MB, 2MB and 4MB configurations (which the Motorola boards
  2013. * seem to have. */
  2014. static unsigned int cirrusfb_get_memsize(u8 __iomem *regbase)
  2015. {
  2016. unsigned long mem;
  2017. unsigned char SRF;
  2018. DPRINTK("ENTER\n");
  2019. SRF = vga_rseq(regbase, CL_SEQRF);
  2020. switch ((SRF & 0x18)) {
  2021. case 0x08:
  2022. mem = 512 * 1024;
  2023. break;
  2024. case 0x10:
  2025. mem = 1024 * 1024;
  2026. break;
  2027. /* 64-bit DRAM data bus width; assume 2MB. Also indicates 2MB memory
  2028. * on the 5430.
  2029. */
  2030. case 0x18:
  2031. mem = 2048 * 1024;
  2032. break;
  2033. default:
  2034. printk(KERN_WARNING "CLgenfb: Unknown memory size!\n");
  2035. mem = 1024 * 1024;
  2036. }
  2037. if (SRF & 0x80)
  2038. /* If DRAM bank switching is enabled, there must be twice as much
  2039. * memory installed. (4MB on the 5434)
  2040. */
  2041. mem *= 2;
  2042. /* TODO: Handling of GD5446/5480 (see XF86 sources ...) */
  2043. DPRINTK("EXIT\n");
  2044. return mem;
  2045. }
  2046. static void get_pci_addrs(const struct pci_dev *pdev,
  2047. unsigned long *display, unsigned long *registers)
  2048. {
  2049. assert(pdev != NULL);
  2050. assert(display != NULL);
  2051. assert(registers != NULL);
  2052. DPRINTK("ENTER\n");
  2053. *display = 0;
  2054. *registers = 0;
  2055. /* This is a best-guess for now */
  2056. if (pci_resource_flags(pdev, 0) & IORESOURCE_IO) {
  2057. *display = pci_resource_start(pdev, 1);
  2058. *registers = pci_resource_start(pdev, 0);
  2059. } else {
  2060. *display = pci_resource_start(pdev, 0);
  2061. *registers = pci_resource_start(pdev, 1);
  2062. }
  2063. assert(*display != 0);
  2064. DPRINTK("EXIT\n");
  2065. }
  2066. static void cirrusfb_pci_unmap(struct cirrusfb_info *cinfo)
  2067. {
  2068. struct pci_dev *pdev = cinfo->pdev;
  2069. iounmap(cinfo->fbmem);
  2070. #if 0 /* if system didn't claim this region, we would... */
  2071. release_mem_region(0xA0000, 65535);
  2072. #endif
  2073. if (release_io_ports)
  2074. release_region(0x3C0, 32);
  2075. pci_release_regions(pdev);
  2076. framebuffer_release(cinfo->info);
  2077. }
  2078. #endif /* CONFIG_PCI */
  2079. #ifdef CONFIG_ZORRO
  2080. static void __devexit cirrusfb_zorro_unmap(struct cirrusfb_info *cinfo)
  2081. {
  2082. zorro_release_device(cinfo->zdev);
  2083. if (cinfo->btype == BT_PICASSO4) {
  2084. cinfo->regbase -= 0x600000;
  2085. iounmap((void *)cinfo->regbase);
  2086. iounmap((void *)cinfo->fbmem);
  2087. } else {
  2088. if (zorro_resource_start(cinfo->zdev) > 0x01000000)
  2089. iounmap((void *)cinfo->fbmem);
  2090. }
  2091. framebuffer_release(cinfo->info);
  2092. }
  2093. #endif /* CONFIG_ZORRO */
  2094. static int cirrusfb_set_fbinfo(struct cirrusfb_info *cinfo)
  2095. {
  2096. struct fb_info *info = cinfo->info;
  2097. struct fb_var_screeninfo *var = &info->var;
  2098. info->par = cinfo;
  2099. info->pseudo_palette = cinfo->pseudo_palette;
  2100. info->flags = FBINFO_DEFAULT
  2101. | FBINFO_HWACCEL_XPAN
  2102. | FBINFO_HWACCEL_YPAN
  2103. | FBINFO_HWACCEL_FILLRECT
  2104. | FBINFO_HWACCEL_COPYAREA;
  2105. if (noaccel)
  2106. info->flags |= FBINFO_HWACCEL_DISABLED;
  2107. info->fbops = &cirrusfb_ops;
  2108. info->screen_base = cinfo->fbmem;
  2109. if (cinfo->btype == BT_GD5480) {
  2110. if (var->bits_per_pixel == 16)
  2111. info->screen_base += 1 * MB_;
  2112. if (var->bits_per_pixel == 24 || var->bits_per_pixel == 32)
  2113. info->screen_base += 2 * MB_;
  2114. }
  2115. /* Fill fix common fields */
  2116. strlcpy(info->fix.id, cirrusfb_board_info[cinfo->btype].name,
  2117. sizeof(info->fix.id));
  2118. /* monochrome: only 1 memory plane */
  2119. /* 8 bit and above: Use whole memory area */
  2120. info->fix.smem_start = cinfo->fbmem_phys;
  2121. info->fix.smem_len =
  2122. (var->bits_per_pixel == 1) ? cinfo->size / 4 : cinfo->size;
  2123. info->fix.type = cinfo->currentmode.type;
  2124. info->fix.type_aux = 0;
  2125. info->fix.visual = cinfo->currentmode.visual;
  2126. info->fix.xpanstep = 1;
  2127. info->fix.ypanstep = 1;
  2128. info->fix.ywrapstep = 0;
  2129. info->fix.line_length = cinfo->currentmode.line_length;
  2130. /* FIXME: map region at 0xB8000 if available, fill in here */
  2131. info->fix.mmio_start = cinfo->fbregs_phys;
  2132. info->fix.mmio_len = 0;
  2133. info->fix.accel = FB_ACCEL_NONE;
  2134. fb_alloc_cmap(&info->cmap, 256, 0);
  2135. return 0;
  2136. }
  2137. static int cirrusfb_register(struct cirrusfb_info *cinfo)
  2138. {
  2139. struct fb_info *info;
  2140. int err;
  2141. enum cirrus_board btype;
  2142. DPRINTK("ENTER\n");
  2143. printk(KERN_INFO "cirrusfb: Driver for Cirrus Logic based "
  2144. "graphic boards, v" CIRRUSFB_VERSION "\n");
  2145. info = cinfo->info;
  2146. btype = cinfo->btype;
  2147. /* sanity checks */
  2148. assert(btype != BT_NONE);
  2149. DPRINTK("cirrusfb: (RAM start set to: 0x%p)\n", cinfo->fbmem);
  2150. /* Make pretend we've set the var so our structures are in a "good" */
  2151. /* state, even though we haven't written the mode to the hw yet... */
  2152. info->var = cirrusfb_predefined[cirrusfb_def_mode].var;
  2153. info->var.activate = FB_ACTIVATE_NOW;
  2154. err = cirrusfb_decode_var(&info->var, &cinfo->currentmode, info);
  2155. if (err < 0) {
  2156. /* should never happen */
  2157. DPRINTK("choking on default var... umm, no good.\n");
  2158. goto err_unmap_cirrusfb;
  2159. }
  2160. /* set all the vital stuff */
  2161. cirrusfb_set_fbinfo(cinfo);
  2162. err = register_framebuffer(info);
  2163. if (err < 0) {
  2164. printk(KERN_ERR "cirrusfb: could not register "
  2165. "fb device; err = %d!\n", err);
  2166. goto err_dealloc_cmap;
  2167. }
  2168. DPRINTK("EXIT, returning 0\n");
  2169. return 0;
  2170. err_dealloc_cmap:
  2171. fb_dealloc_cmap(&info->cmap);
  2172. err_unmap_cirrusfb:
  2173. cinfo->unmap(cinfo);
  2174. return err;
  2175. }
  2176. static void __devexit cirrusfb_cleanup(struct fb_info *info)
  2177. {
  2178. struct cirrusfb_info *cinfo = info->par;
  2179. DPRINTK("ENTER\n");
  2180. switch_monitor(cinfo, 0);
  2181. unregister_framebuffer(info);
  2182. fb_dealloc_cmap(&info->cmap);
  2183. printk("Framebuffer unregistered\n");
  2184. cinfo->unmap(cinfo);
  2185. DPRINTK("EXIT\n");
  2186. }
  2187. #ifdef CONFIG_PCI
  2188. static int cirrusfb_pci_register(struct pci_dev *pdev,
  2189. const struct pci_device_id *ent)
  2190. {
  2191. struct cirrusfb_info *cinfo;
  2192. struct fb_info *info;
  2193. enum cirrus_board btype;
  2194. unsigned long board_addr, board_size;
  2195. int ret;
  2196. ret = pci_enable_device(pdev);
  2197. if (ret < 0) {
  2198. printk(KERN_ERR "cirrusfb: Cannot enable PCI device\n");
  2199. goto err_out;
  2200. }
  2201. info = framebuffer_alloc(sizeof(struct cirrusfb_info), &pdev->dev);
  2202. if (!info) {
  2203. printk(KERN_ERR "cirrusfb: could not allocate memory\n");
  2204. ret = -ENOMEM;
  2205. goto err_disable;
  2206. }
  2207. cinfo = info->par;
  2208. cinfo->info = info;
  2209. cinfo->pdev = pdev;
  2210. cinfo->btype = btype = (enum cirrus_board) ent->driver_data;
  2211. DPRINTK(" Found PCI device, base address 0 is 0x%x, btype set to %d\n",
  2212. pdev->resource[0].start, btype);
  2213. DPRINTK(" base address 1 is 0x%x\n", pdev->resource[1].start);
  2214. if (isPReP) {
  2215. pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, 0x00000000);
  2216. #ifdef CONFIG_PPC_PREP
  2217. get_prep_addrs(&board_addr, &cinfo->fbregs_phys);
  2218. #endif
  2219. /* PReP dies if we ioremap the IO registers, but it works w/out... */
  2220. cinfo->regbase = (char __iomem *) cinfo->fbregs_phys;
  2221. } else {
  2222. DPRINTK("Attempt to get PCI info for Cirrus Graphics Card\n");
  2223. get_pci_addrs(pdev, &board_addr, &cinfo->fbregs_phys);
  2224. /* FIXME: this forces VGA. alternatives? */
  2225. cinfo->regbase = NULL;
  2226. }
  2227. DPRINTK("Board address: 0x%lx, register address: 0x%lx\n",
  2228. board_addr, cinfo->fbregs_phys);
  2229. board_size = (btype == BT_GD5480) ?
  2230. 32 * MB_ : cirrusfb_get_memsize(cinfo->regbase);
  2231. ret = pci_request_regions(pdev, "cirrusfb");
  2232. if (ret < 0) {
  2233. printk(KERN_ERR "cirrusfb: cannot reserve region 0x%lx, "
  2234. "abort\n",
  2235. board_addr);
  2236. goto err_release_fb;
  2237. }
  2238. #if 0 /* if the system didn't claim this region, we would... */
  2239. if (!request_mem_region(0xA0000, 65535, "cirrusfb")) {
  2240. printk(KERN_ERR "cirrusfb: cannot reserve region 0x%lx, abort\n"
  2241. ,
  2242. 0xA0000L);
  2243. ret = -EBUSY;
  2244. goto err_release_regions;
  2245. }
  2246. #endif
  2247. if (request_region(0x3C0, 32, "cirrusfb"))
  2248. release_io_ports = 1;
  2249. cinfo->fbmem = ioremap(board_addr, board_size);
  2250. if (!cinfo->fbmem) {
  2251. ret = -EIO;
  2252. goto err_release_legacy;
  2253. }
  2254. cinfo->fbmem_phys = board_addr;
  2255. cinfo->size = board_size;
  2256. cinfo->unmap = cirrusfb_pci_unmap;
  2257. printk(KERN_INFO " RAM (%lu kB) at 0xx%lx, ",
  2258. cinfo->size / KB_, board_addr);
  2259. printk(KERN_INFO "Cirrus Logic chipset on PCI bus\n");
  2260. pci_set_drvdata(pdev, info);
  2261. ret = cirrusfb_register(cinfo);
  2262. if (ret)
  2263. iounmap(cinfo->fbmem);
  2264. return ret;
  2265. err_release_legacy:
  2266. if (release_io_ports)
  2267. release_region(0x3C0, 32);
  2268. #if 0
  2269. release_mem_region(0xA0000, 65535);
  2270. err_release_regions:
  2271. #endif
  2272. pci_release_regions(pdev);
  2273. err_release_fb:
  2274. framebuffer_release(info);
  2275. err_disable:
  2276. err_out:
  2277. return ret;
  2278. }
  2279. static void __devexit cirrusfb_pci_unregister(struct pci_dev *pdev)
  2280. {
  2281. struct fb_info *info = pci_get_drvdata(pdev);
  2282. DPRINTK("ENTER\n");
  2283. cirrusfb_cleanup(info);
  2284. DPRINTK("EXIT\n");
  2285. }
  2286. static struct pci_driver cirrusfb_pci_driver = {
  2287. .name = "cirrusfb",
  2288. .id_table = cirrusfb_pci_table,
  2289. .probe = cirrusfb_pci_register,
  2290. .remove = __devexit_p(cirrusfb_pci_unregister),
  2291. #ifdef CONFIG_PM
  2292. #if 0
  2293. .suspend = cirrusfb_pci_suspend,
  2294. .resume = cirrusfb_pci_resume,
  2295. #endif
  2296. #endif
  2297. };
  2298. #endif /* CONFIG_PCI */
  2299. #ifdef CONFIG_ZORRO
  2300. static int cirrusfb_zorro_register(struct zorro_dev *z,
  2301. const struct zorro_device_id *ent)
  2302. {
  2303. struct cirrusfb_info *cinfo;
  2304. struct fb_info *info;
  2305. enum cirrus_board btype;
  2306. struct zorro_dev *z2 = NULL;
  2307. unsigned long board_addr, board_size, size;
  2308. int ret;
  2309. btype = ent->driver_data;
  2310. if (cirrusfb_zorro_table2[btype].id2)
  2311. z2 = zorro_find_device(cirrusfb_zorro_table2[btype].id2, NULL);
  2312. size = cirrusfb_zorro_table2[btype].size;
  2313. printk(KERN_INFO "cirrusfb: %s board detected; ",
  2314. cirrusfb_board_info[btype].name);
  2315. info = framebuffer_alloc(sizeof(struct cirrusfb_info), &z->dev);
  2316. if (!info) {
  2317. printk(KERN_ERR "cirrusfb: could not allocate memory\n");
  2318. ret = -ENOMEM;
  2319. goto err_out;
  2320. }
  2321. cinfo = info->par;
  2322. cinfo->info = info;
  2323. cinfo->btype = btype;
  2324. assert(z > 0);
  2325. assert(z2 >= 0);
  2326. assert(btype != BT_NONE);
  2327. cinfo->zdev = z;
  2328. board_addr = zorro_resource_start(z);
  2329. board_size = zorro_resource_len(z);
  2330. cinfo->size = size;
  2331. if (!zorro_request_device(z, "cirrusfb")) {
  2332. printk(KERN_ERR "cirrusfb: cannot reserve region 0x%lx, "
  2333. "abort\n",
  2334. board_addr);
  2335. ret = -EBUSY;
  2336. goto err_release_fb;
  2337. }
  2338. printk(" RAM (%lu MB) at $%lx, ", board_size / MB_, board_addr);
  2339. ret = -EIO;
  2340. if (btype == BT_PICASSO4) {
  2341. printk(KERN_INFO " REG at $%lx\n", board_addr + 0x600000);
  2342. /* To be precise, for the P4 this is not the */
  2343. /* begin of the board, but the begin of RAM. */
  2344. /* for P4, map in its address space in 2 chunks (### TEST! ) */
  2345. /* (note the ugly hardcoded 16M number) */
  2346. cinfo->regbase = ioremap(board_addr, 16777216);
  2347. if (!cinfo->regbase)
  2348. goto err_release_region;
  2349. DPRINTK("cirrusfb: Virtual address for board set to: $%p\n",
  2350. cinfo->regbase);
  2351. cinfo->regbase += 0x600000;
  2352. cinfo->fbregs_phys = board_addr + 0x600000;
  2353. cinfo->fbmem_phys = board_addr + 16777216;
  2354. cinfo->fbmem = ioremap(cinfo->fbmem_phys, 16777216);
  2355. if (!cinfo->fbmem)
  2356. goto err_unmap_regbase;
  2357. } else {
  2358. printk(KERN_INFO " REG at $%lx\n",
  2359. (unsigned long) z2->resource.start);
  2360. cinfo->fbmem_phys = board_addr;
  2361. if (board_addr > 0x01000000)
  2362. cinfo->fbmem = ioremap(board_addr, board_size);
  2363. else
  2364. cinfo->fbmem = (caddr_t) ZTWO_VADDR(board_addr);
  2365. if (!cinfo->fbmem)
  2366. goto err_release_region;
  2367. /* set address for REG area of board */
  2368. cinfo->regbase = (caddr_t) ZTWO_VADDR(z2->resource.start);
  2369. cinfo->fbregs_phys = z2->resource.start;
  2370. DPRINTK("cirrusfb: Virtual address for board set to: $%p\n",
  2371. cinfo->regbase);
  2372. }
  2373. cinfo->unmap = cirrusfb_zorro_unmap;
  2374. printk(KERN_INFO "Cirrus Logic chipset on Zorro bus\n");
  2375. zorro_set_drvdata(z, info);
  2376. ret = cirrusfb_register(cinfo);
  2377. if (ret) {
  2378. if (btype == BT_PICASSO4) {
  2379. iounmap(cinfo->fbmem);
  2380. iounmap(cinfo->regbase - 0x600000);
  2381. } else if (board_addr > 0x01000000)
  2382. iounmap(cinfo->fbmem);
  2383. }
  2384. return ret;
  2385. err_unmap_regbase:
  2386. /* Parental advisory: explicit hack */
  2387. iounmap(cinfo->regbase - 0x600000);
  2388. err_release_region:
  2389. release_region(board_addr, board_size);
  2390. err_release_fb:
  2391. framebuffer_release(info);
  2392. err_out:
  2393. return ret;
  2394. }
  2395. void __devexit cirrusfb_zorro_unregister(struct zorro_dev *z)
  2396. {
  2397. struct fb_info *info = zorro_get_drvdata(z);
  2398. DPRINTK("ENTER\n");
  2399. cirrusfb_cleanup(info);
  2400. DPRINTK("EXIT\n");
  2401. }
  2402. static struct zorro_driver cirrusfb_zorro_driver = {
  2403. .name = "cirrusfb",
  2404. .id_table = cirrusfb_zorro_table,
  2405. .probe = cirrusfb_zorro_register,
  2406. .remove = __devexit_p(cirrusfb_zorro_unregister),
  2407. };
  2408. #endif /* CONFIG_ZORRO */
  2409. static int __init cirrusfb_init(void)
  2410. {
  2411. int error = 0;
  2412. #ifndef MODULE
  2413. char *option = NULL;
  2414. if (fb_get_options("cirrusfb", &option))
  2415. return -ENODEV;
  2416. cirrusfb_setup(option);
  2417. #endif
  2418. #ifdef CONFIG_ZORRO
  2419. error |= zorro_register_driver(&cirrusfb_zorro_driver);
  2420. #endif
  2421. #ifdef CONFIG_PCI
  2422. error |= pci_register_driver(&cirrusfb_pci_driver);
  2423. #endif
  2424. return error;
  2425. }
  2426. #ifndef MODULE
  2427. static int __init cirrusfb_setup(char *options) {
  2428. char *this_opt, s[32];
  2429. int i;
  2430. DPRINTK("ENTER\n");
  2431. if (!options || !*options)
  2432. return 0;
  2433. while ((this_opt = strsep(&options, ",")) != NULL) {
  2434. if (!*this_opt) continue;
  2435. DPRINTK("cirrusfb_setup: option '%s'\n", this_opt);
  2436. for (i = 0; i < NUM_TOTAL_MODES; i++) {
  2437. sprintf(s, "mode:%s", cirrusfb_predefined[i].name);
  2438. if (strcmp(this_opt, s) == 0)
  2439. cirrusfb_def_mode = i;
  2440. }
  2441. if (!strcmp(this_opt, "noaccel"))
  2442. noaccel = 1;
  2443. }
  2444. return 0;
  2445. }
  2446. #endif
  2447. /*
  2448. * Modularization
  2449. */
  2450. MODULE_AUTHOR("Copyright 1999,2000 Jeff Garzik <jgarzik@pobox.com>");
  2451. MODULE_DESCRIPTION("Accelerated FBDev driver for Cirrus Logic chips");
  2452. MODULE_LICENSE("GPL");
  2453. static void __exit cirrusfb_exit(void)
  2454. {
  2455. #ifdef CONFIG_PCI
  2456. pci_unregister_driver(&cirrusfb_pci_driver);
  2457. #endif
  2458. #ifdef CONFIG_ZORRO
  2459. zorro_unregister_driver(&cirrusfb_zorro_driver);
  2460. #endif
  2461. }
  2462. module_init(cirrusfb_init);
  2463. #ifdef MODULE
  2464. module_exit(cirrusfb_exit);
  2465. #endif
  2466. /**********************************************************************/
  2467. /* about the following functions - I have used the same names for the */
  2468. /* functions as Markus Wild did in his Retina driver for NetBSD as */
  2469. /* they just made sense for this purpose. Apart from that, I wrote */
  2470. /* these functions myself. */
  2471. /**********************************************************************/
  2472. /*** WGen() - write into one of the external/general registers ***/
  2473. static void WGen(const struct cirrusfb_info *cinfo,
  2474. int regnum, unsigned char val)
  2475. {
  2476. unsigned long regofs = 0;
  2477. if (cinfo->btype == BT_PICASSO) {
  2478. /* Picasso II specific hack */
  2479. /* if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D ||
  2480. regnum == CL_VSSM2) */
  2481. if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D)
  2482. regofs = 0xfff;
  2483. }
  2484. vga_w(cinfo->regbase, regofs + regnum, val);
  2485. }
  2486. /*** RGen() - read out one of the external/general registers ***/
  2487. static unsigned char RGen(const struct cirrusfb_info *cinfo, int regnum)
  2488. {
  2489. unsigned long regofs = 0;
  2490. if (cinfo->btype == BT_PICASSO) {
  2491. /* Picasso II specific hack */
  2492. /* if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D ||
  2493. regnum == CL_VSSM2) */
  2494. if (regnum == VGA_PEL_IR || regnum == VGA_PEL_D)
  2495. regofs = 0xfff;
  2496. }
  2497. return vga_r(cinfo->regbase, regofs + regnum);
  2498. }
  2499. /*** AttrOn() - turn on VideoEnable for Attribute controller ***/
  2500. static void AttrOn(const struct cirrusfb_info *cinfo)
  2501. {
  2502. assert(cinfo != NULL);
  2503. DPRINTK("ENTER\n");
  2504. if (vga_rcrt(cinfo->regbase, CL_CRT24) & 0x80) {
  2505. /* if we're just in "write value" mode, write back the */
  2506. /* same value as before to not modify anything */
  2507. vga_w(cinfo->regbase, VGA_ATT_IW,
  2508. vga_r(cinfo->regbase, VGA_ATT_R));
  2509. }
  2510. /* turn on video bit */
  2511. /* vga_w(cinfo->regbase, VGA_ATT_IW, 0x20); */
  2512. vga_w(cinfo->regbase, VGA_ATT_IW, 0x33);
  2513. /* dummy write on Reg0 to be on "write index" mode next time */
  2514. vga_w(cinfo->regbase, VGA_ATT_IW, 0x00);
  2515. DPRINTK("EXIT\n");
  2516. }
  2517. /*** WHDR() - write into the Hidden DAC register ***/
  2518. /* as the HDR is the only extension register that requires special treatment
  2519. * (the other extension registers are accessible just like the "ordinary"
  2520. * registers of their functional group) here is a specialized routine for
  2521. * accessing the HDR
  2522. */
  2523. static void WHDR(const struct cirrusfb_info *cinfo, unsigned char val)
  2524. {
  2525. unsigned char dummy;
  2526. if (cinfo->btype == BT_PICASSO) {
  2527. /* Klaus' hint for correct access to HDR on some boards */
  2528. /* first write 0 to pixel mask (3c6) */
  2529. WGen(cinfo, VGA_PEL_MSK, 0x00);
  2530. udelay(200);
  2531. /* next read dummy from pixel address (3c8) */
  2532. dummy = RGen(cinfo, VGA_PEL_IW);
  2533. udelay(200);
  2534. }
  2535. /* now do the usual stuff to access the HDR */
  2536. dummy = RGen(cinfo, VGA_PEL_MSK);
  2537. udelay(200);
  2538. dummy = RGen(cinfo, VGA_PEL_MSK);
  2539. udelay(200);
  2540. dummy = RGen(cinfo, VGA_PEL_MSK);
  2541. udelay(200);
  2542. dummy = RGen(cinfo, VGA_PEL_MSK);
  2543. udelay(200);
  2544. WGen(cinfo, VGA_PEL_MSK, val);
  2545. udelay(200);
  2546. if (cinfo->btype == BT_PICASSO) {
  2547. /* now first reset HDR access counter */
  2548. dummy = RGen(cinfo, VGA_PEL_IW);
  2549. udelay(200);
  2550. /* and at the end, restore the mask value */
  2551. /* ## is this mask always 0xff? */
  2552. WGen(cinfo, VGA_PEL_MSK, 0xff);
  2553. udelay(200);
  2554. }
  2555. }
  2556. /*** WSFR() - write to the "special function register" (SFR) ***/
  2557. static void WSFR(struct cirrusfb_info *cinfo, unsigned char val)
  2558. {
  2559. #ifdef CONFIG_ZORRO
  2560. assert(cinfo->regbase != NULL);
  2561. cinfo->SFR = val;
  2562. z_writeb(val, cinfo->regbase + 0x8000);
  2563. #endif
  2564. }
  2565. /* The Picasso has a second register for switching the monitor bit */
  2566. static void WSFR2(struct cirrusfb_info *cinfo, unsigned char val)
  2567. {
  2568. #ifdef CONFIG_ZORRO
  2569. /* writing an arbitrary value to this one causes the monitor switcher */
  2570. /* to flip to Amiga display */
  2571. assert(cinfo->regbase != NULL);
  2572. cinfo->SFR = val;
  2573. z_writeb(val, cinfo->regbase + 0x9000);
  2574. #endif
  2575. }
  2576. /*** WClut - set CLUT entry (range: 0..63) ***/
  2577. static void WClut(struct cirrusfb_info *cinfo, unsigned char regnum, unsigned char red,
  2578. unsigned char green, unsigned char blue)
  2579. {
  2580. unsigned int data = VGA_PEL_D;
  2581. /* address write mode register is not translated.. */
  2582. vga_w(cinfo->regbase, VGA_PEL_IW, regnum);
  2583. if (cinfo->btype == BT_PICASSO || cinfo->btype == BT_PICASSO4 ||
  2584. cinfo->btype == BT_ALPINE || cinfo->btype == BT_GD5480) {
  2585. /* but DAC data register IS, at least for Picasso II */
  2586. if (cinfo->btype == BT_PICASSO)
  2587. data += 0xfff;
  2588. vga_w(cinfo->regbase, data, red);
  2589. vga_w(cinfo->regbase, data, green);
  2590. vga_w(cinfo->regbase, data, blue);
  2591. } else {
  2592. vga_w(cinfo->regbase, data, blue);
  2593. vga_w(cinfo->regbase, data, green);
  2594. vga_w(cinfo->regbase, data, red);
  2595. }
  2596. }
  2597. #if 0
  2598. /*** RClut - read CLUT entry (range 0..63) ***/
  2599. static void RClut(struct cirrusfb_info *cinfo, unsigned char regnum, unsigned char *red,
  2600. unsigned char *green, unsigned char *blue)
  2601. {
  2602. unsigned int data = VGA_PEL_D;
  2603. vga_w(cinfo->regbase, VGA_PEL_IR, regnum);
  2604. if (cinfo->btype == BT_PICASSO || cinfo->btype == BT_PICASSO4 ||
  2605. cinfo->btype == BT_ALPINE || cinfo->btype == BT_GD5480) {
  2606. if (cinfo->btype == BT_PICASSO)
  2607. data += 0xfff;
  2608. *red = vga_r(cinfo->regbase, data);
  2609. *green = vga_r(cinfo->regbase, data);
  2610. *blue = vga_r(cinfo->regbase, data);
  2611. } else {
  2612. *blue = vga_r(cinfo->regbase, data);
  2613. *green = vga_r(cinfo->regbase, data);
  2614. *red = vga_r(cinfo->regbase, data);
  2615. }
  2616. }
  2617. #endif
  2618. /*******************************************************************
  2619. cirrusfb_WaitBLT()
  2620. Wait for the BitBLT engine to complete a possible earlier job
  2621. *********************************************************************/
  2622. /* FIXME: use interrupts instead */
  2623. static void cirrusfb_WaitBLT(u8 __iomem *regbase)
  2624. {
  2625. /* now busy-wait until we're done */
  2626. while (vga_rgfx(regbase, CL_GR31) & 0x08)
  2627. /* do nothing */ ;
  2628. }
  2629. /*******************************************************************
  2630. cirrusfb_BitBLT()
  2631. perform accelerated "scrolling"
  2632. ********************************************************************/
  2633. static void cirrusfb_BitBLT(u8 __iomem *regbase, int bits_per_pixel,
  2634. u_short curx, u_short cury,
  2635. u_short destx, u_short desty,
  2636. u_short width, u_short height,
  2637. u_short line_length)
  2638. {
  2639. u_short nwidth, nheight;
  2640. u_long nsrc, ndest;
  2641. u_char bltmode;
  2642. DPRINTK("ENTER\n");
  2643. nwidth = width - 1;
  2644. nheight = height - 1;
  2645. bltmode = 0x00;
  2646. /* if source adr < dest addr, do the Blt backwards */
  2647. if (cury <= desty) {
  2648. if (cury == desty) {
  2649. /* if src and dest are on the same line, check x */
  2650. if (curx < destx)
  2651. bltmode |= 0x01;
  2652. } else
  2653. bltmode |= 0x01;
  2654. }
  2655. if (!bltmode) {
  2656. /* standard case: forward blitting */
  2657. nsrc = (cury * line_length) + curx;
  2658. ndest = (desty * line_length) + destx;
  2659. } else {
  2660. /* this means start addresses are at the end,
  2661. * counting backwards
  2662. */
  2663. nsrc = cury * line_length + curx +
  2664. nheight * line_length + nwidth;
  2665. ndest = desty * line_length + destx +
  2666. nheight * line_length + nwidth;
  2667. }
  2668. /*
  2669. run-down of registers to be programmed:
  2670. destination pitch
  2671. source pitch
  2672. BLT width/height
  2673. source start
  2674. destination start
  2675. BLT mode
  2676. BLT ROP
  2677. VGA_GFX_SR_VALUE / VGA_GFX_SR_ENABLE: "fill color"
  2678. start/stop
  2679. */
  2680. cirrusfb_WaitBLT(regbase);
  2681. /* pitch: set to line_length */
  2682. /* dest pitch low */
  2683. vga_wgfx(regbase, CL_GR24, line_length & 0xff);
  2684. /* dest pitch hi */
  2685. vga_wgfx(regbase, CL_GR25, line_length >> 8);
  2686. /* source pitch low */
  2687. vga_wgfx(regbase, CL_GR26, line_length & 0xff);
  2688. /* source pitch hi */
  2689. vga_wgfx(regbase, CL_GR27, line_length >> 8);
  2690. /* BLT width: actual number of pixels - 1 */
  2691. /* BLT width low */
  2692. vga_wgfx(regbase, CL_GR20, nwidth & 0xff);
  2693. /* BLT width hi */
  2694. vga_wgfx(regbase, CL_GR21, nwidth >> 8);
  2695. /* BLT height: actual number of lines -1 */
  2696. /* BLT height low */
  2697. vga_wgfx(regbase, CL_GR22, nheight & 0xff);
  2698. /* BLT width hi */
  2699. vga_wgfx(regbase, CL_GR23, nheight >> 8);
  2700. /* BLT destination */
  2701. /* BLT dest low */
  2702. vga_wgfx(regbase, CL_GR28, (u_char) (ndest & 0xff));
  2703. /* BLT dest mid */
  2704. vga_wgfx(regbase, CL_GR29, (u_char) (ndest >> 8));
  2705. /* BLT dest hi */
  2706. vga_wgfx(regbase, CL_GR2A, (u_char) (ndest >> 16));
  2707. /* BLT source */
  2708. /* BLT src low */
  2709. vga_wgfx(regbase, CL_GR2C, (u_char) (nsrc & 0xff));
  2710. /* BLT src mid */
  2711. vga_wgfx(regbase, CL_GR2D, (u_char) (nsrc >> 8));
  2712. /* BLT src hi */
  2713. vga_wgfx(regbase, CL_GR2E, (u_char) (nsrc >> 16));
  2714. /* BLT mode */
  2715. vga_wgfx(regbase, CL_GR30, bltmode); /* BLT mode */
  2716. /* BLT ROP: SrcCopy */
  2717. vga_wgfx(regbase, CL_GR32, 0x0d); /* BLT ROP */
  2718. /* and finally: GO! */
  2719. vga_wgfx(regbase, CL_GR31, 0x02); /* BLT Start/status */
  2720. DPRINTK("EXIT\n");
  2721. }
  2722. /*******************************************************************
  2723. cirrusfb_RectFill()
  2724. perform accelerated rectangle fill
  2725. ********************************************************************/
  2726. static void cirrusfb_RectFill(u8 __iomem *regbase, int bits_per_pixel,
  2727. u_short x, u_short y, u_short width, u_short height,
  2728. u_char color, u_short line_length)
  2729. {
  2730. u_short nwidth, nheight;
  2731. u_long ndest;
  2732. u_char op;
  2733. DPRINTK("ENTER\n");
  2734. nwidth = width - 1;
  2735. nheight = height - 1;
  2736. ndest = (y * line_length) + x;
  2737. cirrusfb_WaitBLT(regbase);
  2738. /* pitch: set to line_length */
  2739. vga_wgfx(regbase, CL_GR24, line_length & 0xff); /* dest pitch low */
  2740. vga_wgfx(regbase, CL_GR25, line_length >> 8); /* dest pitch hi */
  2741. vga_wgfx(regbase, CL_GR26, line_length & 0xff); /* source pitch low */
  2742. vga_wgfx(regbase, CL_GR27, line_length >> 8); /* source pitch hi */
  2743. /* BLT width: actual number of pixels - 1 */
  2744. vga_wgfx(regbase, CL_GR20, nwidth & 0xff); /* BLT width low */
  2745. vga_wgfx(regbase, CL_GR21, nwidth >> 8); /* BLT width hi */
  2746. /* BLT height: actual number of lines -1 */
  2747. vga_wgfx(regbase, CL_GR22, nheight & 0xff); /* BLT height low */
  2748. vga_wgfx(regbase, CL_GR23, nheight >> 8); /* BLT width hi */
  2749. /* BLT destination */
  2750. /* BLT dest low */
  2751. vga_wgfx(regbase, CL_GR28, (u_char) (ndest & 0xff));
  2752. /* BLT dest mid */
  2753. vga_wgfx(regbase, CL_GR29, (u_char) (ndest >> 8));
  2754. /* BLT dest hi */
  2755. vga_wgfx(regbase, CL_GR2A, (u_char) (ndest >> 16));
  2756. /* BLT source: set to 0 (is a dummy here anyway) */
  2757. vga_wgfx(regbase, CL_GR2C, 0x00); /* BLT src low */
  2758. vga_wgfx(regbase, CL_GR2D, 0x00); /* BLT src mid */
  2759. vga_wgfx(regbase, CL_GR2E, 0x00); /* BLT src hi */
  2760. /* This is a ColorExpand Blt, using the */
  2761. /* same color for foreground and background */
  2762. vga_wgfx(regbase, VGA_GFX_SR_VALUE, color); /* foreground color */
  2763. vga_wgfx(regbase, VGA_GFX_SR_ENABLE, color); /* background color */
  2764. op = 0xc0;
  2765. if (bits_per_pixel == 16) {
  2766. vga_wgfx(regbase, CL_GR10, color); /* foreground color */
  2767. vga_wgfx(regbase, CL_GR11, color); /* background color */
  2768. op = 0x50;
  2769. op = 0xd0;
  2770. } else if (bits_per_pixel == 32) {
  2771. vga_wgfx(regbase, CL_GR10, color); /* foreground color */
  2772. vga_wgfx(regbase, CL_GR11, color); /* background color */
  2773. vga_wgfx(regbase, CL_GR12, color); /* foreground color */
  2774. vga_wgfx(regbase, CL_GR13, color); /* background color */
  2775. vga_wgfx(regbase, CL_GR14, 0); /* foreground color */
  2776. vga_wgfx(regbase, CL_GR15, 0); /* background color */
  2777. op = 0x50;
  2778. op = 0xf0;
  2779. }
  2780. /* BLT mode: color expand, Enable 8x8 copy (faster?) */
  2781. vga_wgfx(regbase, CL_GR30, op); /* BLT mode */
  2782. /* BLT ROP: SrcCopy */
  2783. vga_wgfx(regbase, CL_GR32, 0x0d); /* BLT ROP */
  2784. /* and finally: GO! */
  2785. vga_wgfx(regbase, CL_GR31, 0x02); /* BLT Start/status */
  2786. DPRINTK("EXIT\n");
  2787. }
  2788. /**************************************************************************
  2789. * bestclock() - determine closest possible clock lower(?) than the
  2790. * desired pixel clock
  2791. **************************************************************************/
  2792. static void bestclock(long freq, long *best, long *nom,
  2793. long *den, long *div, long maxfreq)
  2794. {
  2795. long n, h, d, f;
  2796. assert(best != NULL);
  2797. assert(nom != NULL);
  2798. assert(den != NULL);
  2799. assert(div != NULL);
  2800. assert(maxfreq > 0);
  2801. *nom = 0;
  2802. *den = 0;
  2803. *div = 0;
  2804. DPRINTK("ENTER\n");
  2805. if (freq < 8000)
  2806. freq = 8000;
  2807. if (freq > maxfreq)
  2808. freq = maxfreq;
  2809. *best = 0;
  2810. f = freq * 10;
  2811. for (n = 32; n < 128; n++) {
  2812. d = (143181 * n) / f;
  2813. if ((d >= 7) && (d <= 63)) {
  2814. if (d > 31)
  2815. d = (d / 2) * 2;
  2816. h = (14318 * n) / d;
  2817. if (abs(h - freq) < abs(*best - freq)) {
  2818. *best = h;
  2819. *nom = n;
  2820. if (d < 32) {
  2821. *den = d;
  2822. *div = 0;
  2823. } else {
  2824. *den = d / 2;
  2825. *div = 1;
  2826. }
  2827. }
  2828. }
  2829. d = ((143181 * n) + f - 1) / f;
  2830. if ((d >= 7) && (d <= 63)) {
  2831. if (d > 31)
  2832. d = (d / 2) * 2;
  2833. h = (14318 * n) / d;
  2834. if (abs(h - freq) < abs(*best - freq)) {
  2835. *best = h;
  2836. *nom = n;
  2837. if (d < 32) {
  2838. *den = d;
  2839. *div = 0;
  2840. } else {
  2841. *den = d / 2;
  2842. *div = 1;
  2843. }
  2844. }
  2845. }
  2846. }
  2847. DPRINTK("Best possible values for given frequency:\n");
  2848. DPRINTK(" best: %ld kHz nom: %ld den: %ld div: %ld\n",
  2849. freq, *nom, *den, *div);
  2850. DPRINTK("EXIT\n");
  2851. }
  2852. /* -------------------------------------------------------------------------
  2853. *
  2854. * debugging functions
  2855. *
  2856. * -------------------------------------------------------------------------
  2857. */
  2858. #ifdef CIRRUSFB_DEBUG
  2859. /**
  2860. * cirrusfb_dbg_print_byte
  2861. * @name: name associated with byte value to be displayed
  2862. * @val: byte value to be displayed
  2863. *
  2864. * DESCRIPTION:
  2865. * Display an indented string, along with a hexidecimal byte value, and
  2866. * its decoded bits. Bits 7 through 0 are listed in left-to-right
  2867. * order.
  2868. */
  2869. static
  2870. void cirrusfb_dbg_print_byte(const char *name, unsigned char val)
  2871. {
  2872. DPRINTK("%8s = 0x%02X (bits 7-0: %c%c%c%c%c%c%c%c)\n",
  2873. name, val,
  2874. val & 0x80 ? '1' : '0',
  2875. val & 0x40 ? '1' : '0',
  2876. val & 0x20 ? '1' : '0',
  2877. val & 0x10 ? '1' : '0',
  2878. val & 0x08 ? '1' : '0',
  2879. val & 0x04 ? '1' : '0',
  2880. val & 0x02 ? '1' : '0',
  2881. val & 0x01 ? '1' : '0');
  2882. }
  2883. /**
  2884. * cirrusfb_dbg_print_regs
  2885. * @base: If using newmmio, the newmmio base address, otherwise %NULL
  2886. * @reg_class: type of registers to read: %CRT, or %SEQ
  2887. *
  2888. * DESCRIPTION:
  2889. * Dumps the given list of VGA CRTC registers. If @base is %NULL,
  2890. * old-style I/O ports are queried for information, otherwise MMIO is
  2891. * used at the given @base address to query the information.
  2892. */
  2893. static
  2894. void cirrusfb_dbg_print_regs(caddr_t regbase,
  2895. enum cirrusfb_dbg_reg_class reg_class, ...)
  2896. {
  2897. va_list list;
  2898. unsigned char val = 0;
  2899. unsigned reg;
  2900. char *name;
  2901. va_start(list, reg_class);
  2902. name = va_arg(list, char *);
  2903. while (name != NULL) {
  2904. reg = va_arg(list, int);
  2905. switch (reg_class) {
  2906. case CRT:
  2907. val = vga_rcrt(regbase, (unsigned char) reg);
  2908. break;
  2909. case SEQ:
  2910. val = vga_rseq(regbase, (unsigned char) reg);
  2911. break;
  2912. default:
  2913. /* should never occur */
  2914. assert(false);
  2915. break;
  2916. }
  2917. cirrusfb_dbg_print_byte(name, val);
  2918. name = va_arg(list, char *);
  2919. }
  2920. va_end(list);
  2921. }
  2922. /**
  2923. * cirrusfb_dump
  2924. * @cirrusfbinfo:
  2925. *
  2926. * DESCRIPTION:
  2927. */
  2928. static void cirrusfb_dump(void)
  2929. {
  2930. cirrusfb_dbg_reg_dump(NULL);
  2931. }
  2932. /**
  2933. * cirrusfb_dbg_reg_dump
  2934. * @base: If using newmmio, the newmmio base address, otherwise %NULL
  2935. *
  2936. * DESCRIPTION:
  2937. * Dumps a list of interesting VGA and CIRRUSFB registers. If @base is %NULL,
  2938. * old-style I/O ports are queried for information, otherwise MMIO is
  2939. * used at the given @base address to query the information.
  2940. */
  2941. static
  2942. void cirrusfb_dbg_reg_dump(caddr_t regbase)
  2943. {
  2944. DPRINTK("CIRRUSFB VGA CRTC register dump:\n");
  2945. cirrusfb_dbg_print_regs(regbase, CRT,
  2946. "CR00", 0x00,
  2947. "CR01", 0x01,
  2948. "CR02", 0x02,
  2949. "CR03", 0x03,
  2950. "CR04", 0x04,
  2951. "CR05", 0x05,
  2952. "CR06", 0x06,
  2953. "CR07", 0x07,
  2954. "CR08", 0x08,
  2955. "CR09", 0x09,
  2956. "CR0A", 0x0A,
  2957. "CR0B", 0x0B,
  2958. "CR0C", 0x0C,
  2959. "CR0D", 0x0D,
  2960. "CR0E", 0x0E,
  2961. "CR0F", 0x0F,
  2962. "CR10", 0x10,
  2963. "CR11", 0x11,
  2964. "CR12", 0x12,
  2965. "CR13", 0x13,
  2966. "CR14", 0x14,
  2967. "CR15", 0x15,
  2968. "CR16", 0x16,
  2969. "CR17", 0x17,
  2970. "CR18", 0x18,
  2971. "CR22", 0x22,
  2972. "CR24", 0x24,
  2973. "CR26", 0x26,
  2974. "CR2D", 0x2D,
  2975. "CR2E", 0x2E,
  2976. "CR2F", 0x2F,
  2977. "CR30", 0x30,
  2978. "CR31", 0x31,
  2979. "CR32", 0x32,
  2980. "CR33", 0x33,
  2981. "CR34", 0x34,
  2982. "CR35", 0x35,
  2983. "CR36", 0x36,
  2984. "CR37", 0x37,
  2985. "CR38", 0x38,
  2986. "CR39", 0x39,
  2987. "CR3A", 0x3A,
  2988. "CR3B", 0x3B,
  2989. "CR3C", 0x3C,
  2990. "CR3D", 0x3D,
  2991. "CR3E", 0x3E,
  2992. "CR3F", 0x3F,
  2993. NULL);
  2994. DPRINTK("\n");
  2995. DPRINTK("CIRRUSFB VGA SEQ register dump:\n");
  2996. cirrusfb_dbg_print_regs(regbase, SEQ,
  2997. "SR00", 0x00,
  2998. "SR01", 0x01,
  2999. "SR02", 0x02,
  3000. "SR03", 0x03,
  3001. "SR04", 0x04,
  3002. "SR08", 0x08,
  3003. "SR09", 0x09,
  3004. "SR0A", 0x0A,
  3005. "SR0B", 0x0B,
  3006. "SR0D", 0x0D,
  3007. "SR10", 0x10,
  3008. "SR11", 0x11,
  3009. "SR12", 0x12,
  3010. "SR13", 0x13,
  3011. "SR14", 0x14,
  3012. "SR15", 0x15,
  3013. "SR16", 0x16,
  3014. "SR17", 0x17,
  3015. "SR18", 0x18,
  3016. "SR19", 0x19,
  3017. "SR1A", 0x1A,
  3018. "SR1B", 0x1B,
  3019. "SR1C", 0x1C,
  3020. "SR1D", 0x1D,
  3021. "SR1E", 0x1E,
  3022. "SR1F", 0x1F,
  3023. NULL);
  3024. DPRINTK("\n");
  3025. }
  3026. #endif /* CIRRUSFB_DEBUG */