iwl-agn.c 105 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2009 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/kernel.h>
  30. #include <linux/module.h>
  31. #include <linux/init.h>
  32. #include <linux/pci.h>
  33. #include <linux/dma-mapping.h>
  34. #include <linux/delay.h>
  35. #include <linux/sched.h>
  36. #include <linux/skbuff.h>
  37. #include <linux/netdevice.h>
  38. #include <linux/wireless.h>
  39. #include <linux/firmware.h>
  40. #include <linux/etherdevice.h>
  41. #include <linux/if_arp.h>
  42. #include <net/mac80211.h>
  43. #include <asm/div64.h>
  44. #define DRV_NAME "iwlagn"
  45. #include "iwl-eeprom.h"
  46. #include "iwl-dev.h"
  47. #include "iwl-core.h"
  48. #include "iwl-io.h"
  49. #include "iwl-helpers.h"
  50. #include "iwl-sta.h"
  51. #include "iwl-calib.h"
  52. /******************************************************************************
  53. *
  54. * module boiler plate
  55. *
  56. ******************************************************************************/
  57. /*
  58. * module name, copyright, version, etc.
  59. */
  60. #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
  61. #ifdef CONFIG_IWLWIFI_DEBUG
  62. #define VD "d"
  63. #else
  64. #define VD
  65. #endif
  66. #ifdef CONFIG_IWLWIFI_SPECTRUM_MEASUREMENT
  67. #define VS "s"
  68. #else
  69. #define VS
  70. #endif
  71. #define DRV_VERSION IWLWIFI_VERSION VD VS
  72. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  73. MODULE_VERSION(DRV_VERSION);
  74. MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  75. MODULE_LICENSE("GPL");
  76. MODULE_ALIAS("iwl4965");
  77. /*************** STATION TABLE MANAGEMENT ****
  78. * mac80211 should be examined to determine if sta_info is duplicating
  79. * the functionality provided here
  80. */
  81. /**************************************************************/
  82. /**
  83. * iwl_commit_rxon - commit staging_rxon to hardware
  84. *
  85. * The RXON command in staging_rxon is committed to the hardware and
  86. * the active_rxon structure is updated with the new data. This
  87. * function correctly transitions out of the RXON_ASSOC_MSK state if
  88. * a HW tune is required based on the RXON structure changes.
  89. */
  90. int iwl_commit_rxon(struct iwl_priv *priv)
  91. {
  92. /* cast away the const for active_rxon in this function */
  93. struct iwl_rxon_cmd *active_rxon = (void *)&priv->active_rxon;
  94. int ret;
  95. bool new_assoc =
  96. !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK);
  97. if (!iwl_is_alive(priv))
  98. return -EBUSY;
  99. /* always get timestamp with Rx frame */
  100. priv->staging_rxon.flags |= RXON_FLG_TSF2HOST_MSK;
  101. ret = iwl_check_rxon_cmd(priv);
  102. if (ret) {
  103. IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n");
  104. return -EINVAL;
  105. }
  106. /*
  107. * receive commit_rxon request
  108. * abort any previous channel switch if still in process
  109. */
  110. if (priv->switch_rxon.switch_in_progress &&
  111. (priv->switch_rxon.channel != priv->staging_rxon.channel)) {
  112. IWL_DEBUG_11H(priv, "abort channel switch on %d\n",
  113. le16_to_cpu(priv->switch_rxon.channel));
  114. priv->switch_rxon.switch_in_progress = false;
  115. }
  116. /* If we don't need to send a full RXON, we can use
  117. * iwl_rxon_assoc_cmd which is used to reconfigure filter
  118. * and other flags for the current radio configuration. */
  119. if (!iwl_full_rxon_required(priv)) {
  120. ret = iwl_send_rxon_assoc(priv);
  121. if (ret) {
  122. IWL_ERR(priv, "Error setting RXON_ASSOC (%d)\n", ret);
  123. return ret;
  124. }
  125. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  126. iwl_print_rx_config_cmd(priv);
  127. return 0;
  128. }
  129. /* station table will be cleared */
  130. priv->assoc_station_added = 0;
  131. /* If we are currently associated and the new config requires
  132. * an RXON_ASSOC and the new config wants the associated mask enabled,
  133. * we must clear the associated from the active configuration
  134. * before we apply the new config */
  135. if (iwl_is_associated(priv) && new_assoc) {
  136. IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n");
  137. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  138. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  139. sizeof(struct iwl_rxon_cmd),
  140. &priv->active_rxon);
  141. /* If the mask clearing failed then we set
  142. * active_rxon back to what it was previously */
  143. if (ret) {
  144. active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK;
  145. IWL_ERR(priv, "Error clearing ASSOC_MSK (%d)\n", ret);
  146. return ret;
  147. }
  148. }
  149. IWL_DEBUG_INFO(priv, "Sending RXON\n"
  150. "* with%s RXON_FILTER_ASSOC_MSK\n"
  151. "* channel = %d\n"
  152. "* bssid = %pM\n",
  153. (new_assoc ? "" : "out"),
  154. le16_to_cpu(priv->staging_rxon.channel),
  155. priv->staging_rxon.bssid_addr);
  156. iwl_set_rxon_hwcrypto(priv, !priv->cfg->mod_params->sw_crypto);
  157. /* Apply the new configuration
  158. * RXON unassoc clears the station table in uCode, send it before
  159. * we add the bcast station. If assoc bit is set, we will send RXON
  160. * after having added the bcast and bssid station.
  161. */
  162. if (!new_assoc) {
  163. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  164. sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
  165. if (ret) {
  166. IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
  167. return ret;
  168. }
  169. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  170. }
  171. iwl_clear_stations_table(priv);
  172. priv->start_calib = 0;
  173. /* Add the broadcast address so we can send broadcast frames */
  174. iwl_add_bcast_station(priv);
  175. /* If we have set the ASSOC_MSK and we are in BSS mode then
  176. * add the IWL_AP_ID to the station rate table */
  177. if (new_assoc) {
  178. if (priv->iw_mode == NL80211_IFTYPE_STATION) {
  179. ret = iwl_rxon_add_station(priv,
  180. priv->active_rxon.bssid_addr, 1);
  181. if (ret == IWL_INVALID_STATION) {
  182. IWL_ERR(priv,
  183. "Error adding AP address for TX.\n");
  184. return -EIO;
  185. }
  186. priv->assoc_station_added = 1;
  187. if (priv->default_wep_key &&
  188. iwl_send_static_wepkey_cmd(priv, 0))
  189. IWL_ERR(priv,
  190. "Could not send WEP static key.\n");
  191. }
  192. /*
  193. * allow CTS-to-self if possible for new association.
  194. * this is relevant only for 5000 series and up,
  195. * but will not damage 4965
  196. */
  197. priv->staging_rxon.flags |= RXON_FLG_SELF_CTS_EN;
  198. /* Apply the new configuration
  199. * RXON assoc doesn't clear the station table in uCode,
  200. */
  201. ret = iwl_send_cmd_pdu(priv, REPLY_RXON,
  202. sizeof(struct iwl_rxon_cmd), &priv->staging_rxon);
  203. if (ret) {
  204. IWL_ERR(priv, "Error setting new RXON (%d)\n", ret);
  205. return ret;
  206. }
  207. memcpy(active_rxon, &priv->staging_rxon, sizeof(*active_rxon));
  208. }
  209. iwl_print_rx_config_cmd(priv);
  210. iwl_init_sensitivity(priv);
  211. /* If we issue a new RXON command which required a tune then we must
  212. * send a new TXPOWER command or we won't be able to Tx any frames */
  213. ret = iwl_set_tx_power(priv, priv->tx_power_user_lmt, true);
  214. if (ret) {
  215. IWL_ERR(priv, "Error sending TX power (%d)\n", ret);
  216. return ret;
  217. }
  218. return 0;
  219. }
  220. void iwl_update_chain_flags(struct iwl_priv *priv)
  221. {
  222. if (priv->cfg->ops->hcmd->set_rxon_chain)
  223. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  224. iwlcore_commit_rxon(priv);
  225. }
  226. static void iwl_clear_free_frames(struct iwl_priv *priv)
  227. {
  228. struct list_head *element;
  229. IWL_DEBUG_INFO(priv, "%d frames on pre-allocated heap on clear.\n",
  230. priv->frames_count);
  231. while (!list_empty(&priv->free_frames)) {
  232. element = priv->free_frames.next;
  233. list_del(element);
  234. kfree(list_entry(element, struct iwl_frame, list));
  235. priv->frames_count--;
  236. }
  237. if (priv->frames_count) {
  238. IWL_WARN(priv, "%d frames still in use. Did we lose one?\n",
  239. priv->frames_count);
  240. priv->frames_count = 0;
  241. }
  242. }
  243. static struct iwl_frame *iwl_get_free_frame(struct iwl_priv *priv)
  244. {
  245. struct iwl_frame *frame;
  246. struct list_head *element;
  247. if (list_empty(&priv->free_frames)) {
  248. frame = kzalloc(sizeof(*frame), GFP_KERNEL);
  249. if (!frame) {
  250. IWL_ERR(priv, "Could not allocate frame!\n");
  251. return NULL;
  252. }
  253. priv->frames_count++;
  254. return frame;
  255. }
  256. element = priv->free_frames.next;
  257. list_del(element);
  258. return list_entry(element, struct iwl_frame, list);
  259. }
  260. static void iwl_free_frame(struct iwl_priv *priv, struct iwl_frame *frame)
  261. {
  262. memset(frame, 0, sizeof(*frame));
  263. list_add(&frame->list, &priv->free_frames);
  264. }
  265. static u32 iwl_fill_beacon_frame(struct iwl_priv *priv,
  266. struct ieee80211_hdr *hdr,
  267. int left)
  268. {
  269. if (!iwl_is_associated(priv) || !priv->ibss_beacon ||
  270. ((priv->iw_mode != NL80211_IFTYPE_ADHOC) &&
  271. (priv->iw_mode != NL80211_IFTYPE_AP)))
  272. return 0;
  273. if (priv->ibss_beacon->len > left)
  274. return 0;
  275. memcpy(hdr, priv->ibss_beacon->data, priv->ibss_beacon->len);
  276. return priv->ibss_beacon->len;
  277. }
  278. /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
  279. static void iwl_set_beacon_tim(struct iwl_priv *priv,
  280. struct iwl_tx_beacon_cmd *tx_beacon_cmd,
  281. u8 *beacon, u32 frame_size)
  282. {
  283. u16 tim_idx;
  284. struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
  285. /*
  286. * The index is relative to frame start but we start looking at the
  287. * variable-length part of the beacon.
  288. */
  289. tim_idx = mgmt->u.beacon.variable - beacon;
  290. /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
  291. while ((tim_idx < (frame_size - 2)) &&
  292. (beacon[tim_idx] != WLAN_EID_TIM))
  293. tim_idx += beacon[tim_idx+1] + 2;
  294. /* If TIM field was found, set variables */
  295. if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
  296. tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
  297. tx_beacon_cmd->tim_size = beacon[tim_idx+1];
  298. } else
  299. IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
  300. }
  301. static unsigned int iwl_hw_get_beacon_cmd(struct iwl_priv *priv,
  302. struct iwl_frame *frame)
  303. {
  304. struct iwl_tx_beacon_cmd *tx_beacon_cmd;
  305. u32 frame_size;
  306. u32 rate_flags;
  307. u32 rate;
  308. /*
  309. * We have to set up the TX command, the TX Beacon command, and the
  310. * beacon contents.
  311. */
  312. /* Initialize memory */
  313. tx_beacon_cmd = &frame->u.beacon;
  314. memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
  315. /* Set up TX beacon contents */
  316. frame_size = iwl_fill_beacon_frame(priv, tx_beacon_cmd->frame,
  317. sizeof(frame->u) - sizeof(*tx_beacon_cmd));
  318. if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE))
  319. return 0;
  320. /* Set up TX command fields */
  321. tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
  322. tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id;
  323. tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  324. tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
  325. TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
  326. /* Set up TX beacon command fields */
  327. iwl_set_beacon_tim(priv, tx_beacon_cmd, (u8 *)tx_beacon_cmd->frame,
  328. frame_size);
  329. /* Set up packet rate and flags */
  330. rate = iwl_rate_get_lowest_plcp(priv);
  331. priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant);
  332. rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
  333. if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
  334. rate_flags |= RATE_MCS_CCK_MSK;
  335. tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
  336. rate_flags);
  337. return sizeof(*tx_beacon_cmd) + frame_size;
  338. }
  339. static int iwl_send_beacon_cmd(struct iwl_priv *priv)
  340. {
  341. struct iwl_frame *frame;
  342. unsigned int frame_size;
  343. int rc;
  344. frame = iwl_get_free_frame(priv);
  345. if (!frame) {
  346. IWL_ERR(priv, "Could not obtain free frame buffer for beacon "
  347. "command.\n");
  348. return -ENOMEM;
  349. }
  350. frame_size = iwl_hw_get_beacon_cmd(priv, frame);
  351. if (!frame_size) {
  352. IWL_ERR(priv, "Error configuring the beacon command\n");
  353. iwl_free_frame(priv, frame);
  354. return -EINVAL;
  355. }
  356. rc = iwl_send_cmd_pdu(priv, REPLY_TX_BEACON, frame_size,
  357. &frame->u.cmd[0]);
  358. iwl_free_frame(priv, frame);
  359. return rc;
  360. }
  361. static inline dma_addr_t iwl_tfd_tb_get_addr(struct iwl_tfd *tfd, u8 idx)
  362. {
  363. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  364. dma_addr_t addr = get_unaligned_le32(&tb->lo);
  365. if (sizeof(dma_addr_t) > sizeof(u32))
  366. addr |=
  367. ((dma_addr_t)(le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 16;
  368. return addr;
  369. }
  370. static inline u16 iwl_tfd_tb_get_len(struct iwl_tfd *tfd, u8 idx)
  371. {
  372. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  373. return le16_to_cpu(tb->hi_n_len) >> 4;
  374. }
  375. static inline void iwl_tfd_set_tb(struct iwl_tfd *tfd, u8 idx,
  376. dma_addr_t addr, u16 len)
  377. {
  378. struct iwl_tfd_tb *tb = &tfd->tbs[idx];
  379. u16 hi_n_len = len << 4;
  380. put_unaligned_le32(addr, &tb->lo);
  381. if (sizeof(dma_addr_t) > sizeof(u32))
  382. hi_n_len |= ((addr >> 16) >> 16) & 0xF;
  383. tb->hi_n_len = cpu_to_le16(hi_n_len);
  384. tfd->num_tbs = idx + 1;
  385. }
  386. static inline u8 iwl_tfd_get_num_tbs(struct iwl_tfd *tfd)
  387. {
  388. return tfd->num_tbs & 0x1f;
  389. }
  390. /**
  391. * iwl_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
  392. * @priv - driver private data
  393. * @txq - tx queue
  394. *
  395. * Does NOT advance any TFD circular buffer read/write indexes
  396. * Does NOT free the TFD itself (which is within circular buffer)
  397. */
  398. void iwl_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq)
  399. {
  400. struct iwl_tfd *tfd_tmp = (struct iwl_tfd *)txq->tfds;
  401. struct iwl_tfd *tfd;
  402. struct pci_dev *dev = priv->pci_dev;
  403. int index = txq->q.read_ptr;
  404. int i;
  405. int num_tbs;
  406. tfd = &tfd_tmp[index];
  407. /* Sanity check on number of chunks */
  408. num_tbs = iwl_tfd_get_num_tbs(tfd);
  409. if (num_tbs >= IWL_NUM_OF_TBS) {
  410. IWL_ERR(priv, "Too many chunks: %i\n", num_tbs);
  411. /* @todo issue fatal error, it is quite serious situation */
  412. return;
  413. }
  414. /* Unmap tx_cmd */
  415. if (num_tbs)
  416. pci_unmap_single(dev,
  417. pci_unmap_addr(&txq->meta[index], mapping),
  418. pci_unmap_len(&txq->meta[index], len),
  419. PCI_DMA_BIDIRECTIONAL);
  420. /* Unmap chunks, if any. */
  421. for (i = 1; i < num_tbs; i++) {
  422. pci_unmap_single(dev, iwl_tfd_tb_get_addr(tfd, i),
  423. iwl_tfd_tb_get_len(tfd, i), PCI_DMA_TODEVICE);
  424. if (txq->txb) {
  425. dev_kfree_skb(txq->txb[txq->q.read_ptr].skb[i - 1]);
  426. txq->txb[txq->q.read_ptr].skb[i - 1] = NULL;
  427. }
  428. }
  429. }
  430. int iwl_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv,
  431. struct iwl_tx_queue *txq,
  432. dma_addr_t addr, u16 len,
  433. u8 reset, u8 pad)
  434. {
  435. struct iwl_queue *q;
  436. struct iwl_tfd *tfd, *tfd_tmp;
  437. u32 num_tbs;
  438. q = &txq->q;
  439. tfd_tmp = (struct iwl_tfd *)txq->tfds;
  440. tfd = &tfd_tmp[q->write_ptr];
  441. if (reset)
  442. memset(tfd, 0, sizeof(*tfd));
  443. num_tbs = iwl_tfd_get_num_tbs(tfd);
  444. /* Each TFD can point to a maximum 20 Tx buffers */
  445. if (num_tbs >= IWL_NUM_OF_TBS) {
  446. IWL_ERR(priv, "Error can not send more than %d chunks\n",
  447. IWL_NUM_OF_TBS);
  448. return -EINVAL;
  449. }
  450. BUG_ON(addr & ~DMA_BIT_MASK(36));
  451. if (unlikely(addr & ~IWL_TX_DMA_MASK))
  452. IWL_ERR(priv, "Unaligned address = %llx\n",
  453. (unsigned long long)addr);
  454. iwl_tfd_set_tb(tfd, num_tbs, addr, len);
  455. return 0;
  456. }
  457. /*
  458. * Tell nic where to find circular buffer of Tx Frame Descriptors for
  459. * given Tx queue, and enable the DMA channel used for that queue.
  460. *
  461. * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
  462. * channels supported in hardware.
  463. */
  464. int iwl_hw_tx_queue_init(struct iwl_priv *priv,
  465. struct iwl_tx_queue *txq)
  466. {
  467. int txq_id = txq->q.id;
  468. /* Circular buffer (TFD queue in DRAM) physical base address */
  469. iwl_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
  470. txq->q.dma_addr >> 8);
  471. return 0;
  472. }
  473. /******************************************************************************
  474. *
  475. * Generic RX handler implementations
  476. *
  477. ******************************************************************************/
  478. static void iwl_rx_reply_alive(struct iwl_priv *priv,
  479. struct iwl_rx_mem_buffer *rxb)
  480. {
  481. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  482. struct iwl_alive_resp *palive;
  483. struct delayed_work *pwork;
  484. palive = &pkt->u.alive_frame;
  485. IWL_DEBUG_INFO(priv, "Alive ucode status 0x%08X revision "
  486. "0x%01X 0x%01X\n",
  487. palive->is_valid, palive->ver_type,
  488. palive->ver_subtype);
  489. if (palive->ver_subtype == INITIALIZE_SUBTYPE) {
  490. IWL_DEBUG_INFO(priv, "Initialization Alive received.\n");
  491. memcpy(&priv->card_alive_init,
  492. &pkt->u.alive_frame,
  493. sizeof(struct iwl_init_alive_resp));
  494. pwork = &priv->init_alive_start;
  495. } else {
  496. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  497. memcpy(&priv->card_alive, &pkt->u.alive_frame,
  498. sizeof(struct iwl_alive_resp));
  499. pwork = &priv->alive_start;
  500. }
  501. /* We delay the ALIVE response by 5ms to
  502. * give the HW RF Kill time to activate... */
  503. if (palive->is_valid == UCODE_VALID_OK)
  504. queue_delayed_work(priv->workqueue, pwork,
  505. msecs_to_jiffies(5));
  506. else
  507. IWL_WARN(priv, "uCode did not respond OK.\n");
  508. }
  509. static void iwl_bg_beacon_update(struct work_struct *work)
  510. {
  511. struct iwl_priv *priv =
  512. container_of(work, struct iwl_priv, beacon_update);
  513. struct sk_buff *beacon;
  514. /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
  515. beacon = ieee80211_beacon_get(priv->hw, priv->vif);
  516. if (!beacon) {
  517. IWL_ERR(priv, "update beacon failed\n");
  518. return;
  519. }
  520. mutex_lock(&priv->mutex);
  521. /* new beacon skb is allocated every time; dispose previous.*/
  522. if (priv->ibss_beacon)
  523. dev_kfree_skb(priv->ibss_beacon);
  524. priv->ibss_beacon = beacon;
  525. mutex_unlock(&priv->mutex);
  526. iwl_send_beacon_cmd(priv);
  527. }
  528. /**
  529. * iwl_bg_statistics_periodic - Timer callback to queue statistics
  530. *
  531. * This callback is provided in order to send a statistics request.
  532. *
  533. * This timer function is continually reset to execute within
  534. * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
  535. * was received. We need to ensure we receive the statistics in order
  536. * to update the temperature used for calibrating the TXPOWER.
  537. */
  538. static void iwl_bg_statistics_periodic(unsigned long data)
  539. {
  540. struct iwl_priv *priv = (struct iwl_priv *)data;
  541. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  542. return;
  543. /* dont send host command if rf-kill is on */
  544. if (!iwl_is_ready_rf(priv))
  545. return;
  546. iwl_send_statistics_request(priv, CMD_ASYNC, false);
  547. }
  548. static void iwl_rx_beacon_notif(struct iwl_priv *priv,
  549. struct iwl_rx_mem_buffer *rxb)
  550. {
  551. #ifdef CONFIG_IWLWIFI_DEBUG
  552. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  553. struct iwl4965_beacon_notif *beacon =
  554. (struct iwl4965_beacon_notif *)pkt->u.raw;
  555. u8 rate = iwl_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags);
  556. IWL_DEBUG_RX(priv, "beacon status %x retries %d iss %d "
  557. "tsf %d %d rate %d\n",
  558. le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK,
  559. beacon->beacon_notify_hdr.failure_frame,
  560. le32_to_cpu(beacon->ibss_mgr_status),
  561. le32_to_cpu(beacon->high_tsf),
  562. le32_to_cpu(beacon->low_tsf), rate);
  563. #endif
  564. if ((priv->iw_mode == NL80211_IFTYPE_AP) &&
  565. (!test_bit(STATUS_EXIT_PENDING, &priv->status)))
  566. queue_work(priv->workqueue, &priv->beacon_update);
  567. }
  568. /* Handle notification from uCode that card's power state is changing
  569. * due to software, hardware, or critical temperature RFKILL */
  570. static void iwl_rx_card_state_notif(struct iwl_priv *priv,
  571. struct iwl_rx_mem_buffer *rxb)
  572. {
  573. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  574. u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags);
  575. unsigned long status = priv->status;
  576. IWL_DEBUG_RF_KILL(priv, "Card state received: HW:%s SW:%s\n",
  577. (flags & HW_CARD_DISABLED) ? "Kill" : "On",
  578. (flags & SW_CARD_DISABLED) ? "Kill" : "On");
  579. if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED |
  580. RF_CARD_DISABLED)) {
  581. iwl_write32(priv, CSR_UCODE_DRV_GP1_SET,
  582. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  583. iwl_write_direct32(priv, HBUS_TARG_MBX_C,
  584. HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
  585. if (!(flags & RXON_CARD_DISABLED)) {
  586. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  587. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  588. iwl_write_direct32(priv, HBUS_TARG_MBX_C,
  589. HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED);
  590. }
  591. if (flags & RF_CARD_DISABLED)
  592. iwl_tt_enter_ct_kill(priv);
  593. }
  594. if (!(flags & RF_CARD_DISABLED))
  595. iwl_tt_exit_ct_kill(priv);
  596. if (flags & HW_CARD_DISABLED)
  597. set_bit(STATUS_RF_KILL_HW, &priv->status);
  598. else
  599. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  600. if (!(flags & RXON_CARD_DISABLED))
  601. iwl_scan_cancel(priv);
  602. if ((test_bit(STATUS_RF_KILL_HW, &status) !=
  603. test_bit(STATUS_RF_KILL_HW, &priv->status)))
  604. wiphy_rfkill_set_hw_state(priv->hw->wiphy,
  605. test_bit(STATUS_RF_KILL_HW, &priv->status));
  606. else
  607. wake_up_interruptible(&priv->wait_command_queue);
  608. }
  609. int iwl_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src)
  610. {
  611. if (src == IWL_PWR_SRC_VAUX) {
  612. if (pci_pme_capable(priv->pci_dev, PCI_D3cold))
  613. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  614. APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
  615. ~APMG_PS_CTRL_MSK_PWR_SRC);
  616. } else {
  617. iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  618. APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
  619. ~APMG_PS_CTRL_MSK_PWR_SRC);
  620. }
  621. return 0;
  622. }
  623. /**
  624. * iwl_setup_rx_handlers - Initialize Rx handler callbacks
  625. *
  626. * Setup the RX handlers for each of the reply types sent from the uCode
  627. * to the host.
  628. *
  629. * This function chains into the hardware specific files for them to setup
  630. * any hardware specific handlers as well.
  631. */
  632. static void iwl_setup_rx_handlers(struct iwl_priv *priv)
  633. {
  634. priv->rx_handlers[REPLY_ALIVE] = iwl_rx_reply_alive;
  635. priv->rx_handlers[REPLY_ERROR] = iwl_rx_reply_error;
  636. priv->rx_handlers[CHANNEL_SWITCH_NOTIFICATION] = iwl_rx_csa;
  637. priv->rx_handlers[PM_SLEEP_NOTIFICATION] = iwl_rx_pm_sleep_notif;
  638. priv->rx_handlers[PM_DEBUG_STATISTIC_NOTIFIC] =
  639. iwl_rx_pm_debug_statistics_notif;
  640. priv->rx_handlers[BEACON_NOTIFICATION] = iwl_rx_beacon_notif;
  641. /*
  642. * The same handler is used for both the REPLY to a discrete
  643. * statistics request from the host as well as for the periodic
  644. * statistics notifications (after received beacons) from the uCode.
  645. */
  646. priv->rx_handlers[REPLY_STATISTICS_CMD] = iwl_reply_statistics;
  647. priv->rx_handlers[STATISTICS_NOTIFICATION] = iwl_rx_statistics;
  648. iwl_setup_spectrum_handlers(priv);
  649. iwl_setup_rx_scan_handlers(priv);
  650. /* status change handler */
  651. priv->rx_handlers[CARD_STATE_NOTIFICATION] = iwl_rx_card_state_notif;
  652. priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
  653. iwl_rx_missed_beacon_notif;
  654. /* Rx handlers */
  655. priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl_rx_reply_rx_phy;
  656. priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl_rx_reply_rx;
  657. /* block ack */
  658. priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl_rx_reply_compressed_ba;
  659. /* Set up hardware specific Rx handlers */
  660. priv->cfg->ops->lib->rx_handler_setup(priv);
  661. }
  662. /**
  663. * iwl_rx_handle - Main entry function for receiving responses from uCode
  664. *
  665. * Uses the priv->rx_handlers callback function array to invoke
  666. * the appropriate handlers, including command responses,
  667. * frame-received notifications, and other notifications.
  668. */
  669. void iwl_rx_handle(struct iwl_priv *priv)
  670. {
  671. struct iwl_rx_mem_buffer *rxb;
  672. struct iwl_rx_packet *pkt;
  673. struct iwl_rx_queue *rxq = &priv->rxq;
  674. u32 r, i;
  675. int reclaim;
  676. unsigned long flags;
  677. u8 fill_rx = 0;
  678. u32 count = 8;
  679. int total_empty;
  680. /* uCode's read index (stored in shared DRAM) indicates the last Rx
  681. * buffer that the driver may process (last buffer filled by ucode). */
  682. r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
  683. i = rxq->read;
  684. /* Rx interrupt, but nothing sent from uCode */
  685. if (i == r)
  686. IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
  687. /* calculate total frames need to be restock after handling RX */
  688. total_empty = r - rxq->write_actual;
  689. if (total_empty < 0)
  690. total_empty += RX_QUEUE_SIZE;
  691. if (total_empty > (RX_QUEUE_SIZE / 2))
  692. fill_rx = 1;
  693. while (i != r) {
  694. rxb = rxq->queue[i];
  695. /* If an RXB doesn't have a Rx queue slot associated with it,
  696. * then a bug has been introduced in the queue refilling
  697. * routines -- catch it here */
  698. BUG_ON(rxb == NULL);
  699. rxq->queue[i] = NULL;
  700. pci_unmap_page(priv->pci_dev, rxb->page_dma,
  701. PAGE_SIZE << priv->hw_params.rx_page_order,
  702. PCI_DMA_FROMDEVICE);
  703. pkt = rxb_addr(rxb);
  704. trace_iwlwifi_dev_rx(priv, pkt,
  705. le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK);
  706. /* Reclaim a command buffer only if this packet is a response
  707. * to a (driver-originated) command.
  708. * If the packet (e.g. Rx frame) originated from uCode,
  709. * there is no command buffer to reclaim.
  710. * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
  711. * but apparently a few don't get set; catch them here. */
  712. reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
  713. (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
  714. (pkt->hdr.cmd != REPLY_RX) &&
  715. (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
  716. (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
  717. (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
  718. (pkt->hdr.cmd != REPLY_TX);
  719. /* Based on type of command response or notification,
  720. * handle those that need handling via function in
  721. * rx_handlers table. See iwl_setup_rx_handlers() */
  722. if (priv->rx_handlers[pkt->hdr.cmd]) {
  723. IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
  724. i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
  725. priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
  726. priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
  727. } else {
  728. /* No handling needed */
  729. IWL_DEBUG_RX(priv,
  730. "r %d i %d No handler needed for %s, 0x%02x\n",
  731. r, i, get_cmd_string(pkt->hdr.cmd),
  732. pkt->hdr.cmd);
  733. }
  734. /*
  735. * XXX: After here, we should always check rxb->page
  736. * against NULL before touching it or its virtual
  737. * memory (pkt). Because some rx_handler might have
  738. * already taken or freed the pages.
  739. */
  740. if (reclaim) {
  741. /* Invoke any callbacks, transfer the buffer to caller,
  742. * and fire off the (possibly) blocking iwl_send_cmd()
  743. * as we reclaim the driver command queue */
  744. if (rxb->page)
  745. iwl_tx_cmd_complete(priv, rxb);
  746. else
  747. IWL_WARN(priv, "Claim null rxb?\n");
  748. }
  749. /* Reuse the page if possible. For notification packets and
  750. * SKBs that fail to Rx correctly, add them back into the
  751. * rx_free list for reuse later. */
  752. spin_lock_irqsave(&rxq->lock, flags);
  753. if (rxb->page != NULL) {
  754. rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
  755. 0, PAGE_SIZE << priv->hw_params.rx_page_order,
  756. PCI_DMA_FROMDEVICE);
  757. list_add_tail(&rxb->list, &rxq->rx_free);
  758. rxq->free_count++;
  759. } else
  760. list_add_tail(&rxb->list, &rxq->rx_used);
  761. spin_unlock_irqrestore(&rxq->lock, flags);
  762. i = (i + 1) & RX_QUEUE_MASK;
  763. /* If there are a lot of unused frames,
  764. * restock the Rx queue so ucode wont assert. */
  765. if (fill_rx) {
  766. count++;
  767. if (count >= 8) {
  768. rxq->read = i;
  769. iwl_rx_replenish_now(priv);
  770. count = 0;
  771. }
  772. }
  773. }
  774. /* Backtrack one entry */
  775. rxq->read = i;
  776. if (fill_rx)
  777. iwl_rx_replenish_now(priv);
  778. else
  779. iwl_rx_queue_restock(priv);
  780. }
  781. /* call this function to flush any scheduled tasklet */
  782. static inline void iwl_synchronize_irq(struct iwl_priv *priv)
  783. {
  784. /* wait to make sure we flush pending tasklet*/
  785. synchronize_irq(priv->pci_dev->irq);
  786. tasklet_kill(&priv->irq_tasklet);
  787. }
  788. static void iwl_irq_tasklet_legacy(struct iwl_priv *priv)
  789. {
  790. u32 inta, handled = 0;
  791. u32 inta_fh;
  792. unsigned long flags;
  793. u32 i;
  794. #ifdef CONFIG_IWLWIFI_DEBUG
  795. u32 inta_mask;
  796. #endif
  797. spin_lock_irqsave(&priv->lock, flags);
  798. /* Ack/clear/reset pending uCode interrupts.
  799. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  800. * and will clear only when CSR_FH_INT_STATUS gets cleared. */
  801. inta = iwl_read32(priv, CSR_INT);
  802. iwl_write32(priv, CSR_INT, inta);
  803. /* Ack/clear/reset pending flow-handler (DMA) interrupts.
  804. * Any new interrupts that happen after this, either while we're
  805. * in this tasklet, or later, will show up in next ISR/tasklet. */
  806. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  807. iwl_write32(priv, CSR_FH_INT_STATUS, inta_fh);
  808. #ifdef CONFIG_IWLWIFI_DEBUG
  809. if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
  810. /* just for debug */
  811. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  812. IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x, fh 0x%08x\n",
  813. inta, inta_mask, inta_fh);
  814. }
  815. #endif
  816. spin_unlock_irqrestore(&priv->lock, flags);
  817. /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not
  818. * atomic, make sure that inta covers all the interrupts that
  819. * we've discovered, even if FH interrupt came in just after
  820. * reading CSR_INT. */
  821. if (inta_fh & CSR49_FH_INT_RX_MASK)
  822. inta |= CSR_INT_BIT_FH_RX;
  823. if (inta_fh & CSR49_FH_INT_TX_MASK)
  824. inta |= CSR_INT_BIT_FH_TX;
  825. /* Now service all interrupt bits discovered above. */
  826. if (inta & CSR_INT_BIT_HW_ERR) {
  827. IWL_ERR(priv, "Hardware error detected. Restarting.\n");
  828. /* Tell the device to stop sending interrupts */
  829. iwl_disable_interrupts(priv);
  830. priv->isr_stats.hw++;
  831. iwl_irq_handle_error(priv);
  832. handled |= CSR_INT_BIT_HW_ERR;
  833. return;
  834. }
  835. #ifdef CONFIG_IWLWIFI_DEBUG
  836. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  837. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  838. if (inta & CSR_INT_BIT_SCD) {
  839. IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
  840. "the frame/frames.\n");
  841. priv->isr_stats.sch++;
  842. }
  843. /* Alive notification via Rx interrupt will do the real work */
  844. if (inta & CSR_INT_BIT_ALIVE) {
  845. IWL_DEBUG_ISR(priv, "Alive interrupt\n");
  846. priv->isr_stats.alive++;
  847. }
  848. }
  849. #endif
  850. /* Safely ignore these bits for debug checks below */
  851. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  852. /* HW RF KILL switch toggled */
  853. if (inta & CSR_INT_BIT_RF_KILL) {
  854. int hw_rf_kill = 0;
  855. if (!(iwl_read32(priv, CSR_GP_CNTRL) &
  856. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  857. hw_rf_kill = 1;
  858. IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
  859. hw_rf_kill ? "disable radio" : "enable radio");
  860. priv->isr_stats.rfkill++;
  861. /* driver only loads ucode once setting the interface up.
  862. * the driver allows loading the ucode even if the radio
  863. * is killed. Hence update the killswitch state here. The
  864. * rfkill handler will care about restarting if needed.
  865. */
  866. if (!test_bit(STATUS_ALIVE, &priv->status)) {
  867. if (hw_rf_kill)
  868. set_bit(STATUS_RF_KILL_HW, &priv->status);
  869. else
  870. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  871. wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
  872. }
  873. handled |= CSR_INT_BIT_RF_KILL;
  874. }
  875. /* Chip got too hot and stopped itself */
  876. if (inta & CSR_INT_BIT_CT_KILL) {
  877. IWL_ERR(priv, "Microcode CT kill error detected.\n");
  878. priv->isr_stats.ctkill++;
  879. handled |= CSR_INT_BIT_CT_KILL;
  880. }
  881. /* Error detected by uCode */
  882. if (inta & CSR_INT_BIT_SW_ERR) {
  883. IWL_ERR(priv, "Microcode SW error detected. "
  884. " Restarting 0x%X.\n", inta);
  885. priv->isr_stats.sw++;
  886. priv->isr_stats.sw_err = inta;
  887. iwl_irq_handle_error(priv);
  888. handled |= CSR_INT_BIT_SW_ERR;
  889. }
  890. /*
  891. * uCode wakes up after power-down sleep.
  892. * Tell device about any new tx or host commands enqueued,
  893. * and about any Rx buffers made available while asleep.
  894. */
  895. if (inta & CSR_INT_BIT_WAKEUP) {
  896. IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
  897. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  898. for (i = 0; i < priv->hw_params.max_txq_num; i++)
  899. iwl_txq_update_write_ptr(priv, &priv->txq[i]);
  900. priv->isr_stats.wakeup++;
  901. handled |= CSR_INT_BIT_WAKEUP;
  902. }
  903. /* All uCode command responses, including Tx command responses,
  904. * Rx "responses" (frame-received notification), and other
  905. * notifications from uCode come through here*/
  906. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  907. iwl_rx_handle(priv);
  908. priv->isr_stats.rx++;
  909. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  910. }
  911. /* This "Tx" DMA channel is used only for loading uCode */
  912. if (inta & CSR_INT_BIT_FH_TX) {
  913. IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
  914. priv->isr_stats.tx++;
  915. handled |= CSR_INT_BIT_FH_TX;
  916. /* Wake up uCode load routine, now that load is complete */
  917. priv->ucode_write_complete = 1;
  918. wake_up_interruptible(&priv->wait_command_queue);
  919. }
  920. if (inta & ~handled) {
  921. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  922. priv->isr_stats.unhandled++;
  923. }
  924. if (inta & ~(priv->inta_mask)) {
  925. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  926. inta & ~priv->inta_mask);
  927. IWL_WARN(priv, " with FH_INT = 0x%08x\n", inta_fh);
  928. }
  929. /* Re-enable all interrupts */
  930. /* only Re-enable if diabled by irq */
  931. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  932. iwl_enable_interrupts(priv);
  933. #ifdef CONFIG_IWLWIFI_DEBUG
  934. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  935. inta = iwl_read32(priv, CSR_INT);
  936. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  937. inta_fh = iwl_read32(priv, CSR_FH_INT_STATUS);
  938. IWL_DEBUG_ISR(priv, "End inta 0x%08x, enabled 0x%08x, fh 0x%08x, "
  939. "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags);
  940. }
  941. #endif
  942. }
  943. /* tasklet for iwlagn interrupt */
  944. static void iwl_irq_tasklet(struct iwl_priv *priv)
  945. {
  946. u32 inta = 0;
  947. u32 handled = 0;
  948. unsigned long flags;
  949. u32 i;
  950. #ifdef CONFIG_IWLWIFI_DEBUG
  951. u32 inta_mask;
  952. #endif
  953. spin_lock_irqsave(&priv->lock, flags);
  954. /* Ack/clear/reset pending uCode interrupts.
  955. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  956. */
  957. iwl_write32(priv, CSR_INT, priv->inta);
  958. inta = priv->inta;
  959. #ifdef CONFIG_IWLWIFI_DEBUG
  960. if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
  961. /* just for debug */
  962. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  963. IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
  964. inta, inta_mask);
  965. }
  966. #endif
  967. spin_unlock_irqrestore(&priv->lock, flags);
  968. /* saved interrupt in inta variable now we can reset priv->inta */
  969. priv->inta = 0;
  970. /* Now service all interrupt bits discovered above. */
  971. if (inta & CSR_INT_BIT_HW_ERR) {
  972. IWL_ERR(priv, "Hardware error detected. Restarting.\n");
  973. /* Tell the device to stop sending interrupts */
  974. iwl_disable_interrupts(priv);
  975. priv->isr_stats.hw++;
  976. iwl_irq_handle_error(priv);
  977. handled |= CSR_INT_BIT_HW_ERR;
  978. return;
  979. }
  980. #ifdef CONFIG_IWLWIFI_DEBUG
  981. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  982. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  983. if (inta & CSR_INT_BIT_SCD) {
  984. IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
  985. "the frame/frames.\n");
  986. priv->isr_stats.sch++;
  987. }
  988. /* Alive notification via Rx interrupt will do the real work */
  989. if (inta & CSR_INT_BIT_ALIVE) {
  990. IWL_DEBUG_ISR(priv, "Alive interrupt\n");
  991. priv->isr_stats.alive++;
  992. }
  993. }
  994. #endif
  995. /* Safely ignore these bits for debug checks below */
  996. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  997. /* HW RF KILL switch toggled */
  998. if (inta & CSR_INT_BIT_RF_KILL) {
  999. int hw_rf_kill = 0;
  1000. if (!(iwl_read32(priv, CSR_GP_CNTRL) &
  1001. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  1002. hw_rf_kill = 1;
  1003. IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
  1004. hw_rf_kill ? "disable radio" : "enable radio");
  1005. priv->isr_stats.rfkill++;
  1006. /* driver only loads ucode once setting the interface up.
  1007. * the driver allows loading the ucode even if the radio
  1008. * is killed. Hence update the killswitch state here. The
  1009. * rfkill handler will care about restarting if needed.
  1010. */
  1011. if (!test_bit(STATUS_ALIVE, &priv->status)) {
  1012. if (hw_rf_kill)
  1013. set_bit(STATUS_RF_KILL_HW, &priv->status);
  1014. else
  1015. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  1016. wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
  1017. }
  1018. handled |= CSR_INT_BIT_RF_KILL;
  1019. }
  1020. /* Chip got too hot and stopped itself */
  1021. if (inta & CSR_INT_BIT_CT_KILL) {
  1022. IWL_ERR(priv, "Microcode CT kill error detected.\n");
  1023. priv->isr_stats.ctkill++;
  1024. handled |= CSR_INT_BIT_CT_KILL;
  1025. }
  1026. /* Error detected by uCode */
  1027. if (inta & CSR_INT_BIT_SW_ERR) {
  1028. IWL_ERR(priv, "Microcode SW error detected. "
  1029. " Restarting 0x%X.\n", inta);
  1030. priv->isr_stats.sw++;
  1031. priv->isr_stats.sw_err = inta;
  1032. iwl_irq_handle_error(priv);
  1033. handled |= CSR_INT_BIT_SW_ERR;
  1034. }
  1035. /* uCode wakes up after power-down sleep */
  1036. if (inta & CSR_INT_BIT_WAKEUP) {
  1037. IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
  1038. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  1039. for (i = 0; i < priv->hw_params.max_txq_num; i++)
  1040. iwl_txq_update_write_ptr(priv, &priv->txq[i]);
  1041. priv->isr_stats.wakeup++;
  1042. handled |= CSR_INT_BIT_WAKEUP;
  1043. }
  1044. /* All uCode command responses, including Tx command responses,
  1045. * Rx "responses" (frame-received notification), and other
  1046. * notifications from uCode come through here*/
  1047. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
  1048. CSR_INT_BIT_RX_PERIODIC)) {
  1049. IWL_DEBUG_ISR(priv, "Rx interrupt\n");
  1050. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  1051. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  1052. iwl_write32(priv, CSR_FH_INT_STATUS,
  1053. CSR49_FH_INT_RX_MASK);
  1054. }
  1055. if (inta & CSR_INT_BIT_RX_PERIODIC) {
  1056. handled |= CSR_INT_BIT_RX_PERIODIC;
  1057. iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
  1058. }
  1059. /* Sending RX interrupt require many steps to be done in the
  1060. * the device:
  1061. * 1- write interrupt to current index in ICT table.
  1062. * 2- dma RX frame.
  1063. * 3- update RX shared data to indicate last write index.
  1064. * 4- send interrupt.
  1065. * This could lead to RX race, driver could receive RX interrupt
  1066. * but the shared data changes does not reflect this;
  1067. * periodic interrupt will detect any dangling Rx activity.
  1068. */
  1069. /* Disable periodic interrupt; we use it as just a one-shot. */
  1070. iwl_write8(priv, CSR_INT_PERIODIC_REG,
  1071. CSR_INT_PERIODIC_DIS);
  1072. iwl_rx_handle(priv);
  1073. /*
  1074. * Enable periodic interrupt in 8 msec only if we received
  1075. * real RX interrupt (instead of just periodic int), to catch
  1076. * any dangling Rx interrupt. If it was just the periodic
  1077. * interrupt, there was no dangling Rx activity, and no need
  1078. * to extend the periodic interrupt; one-shot is enough.
  1079. */
  1080. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
  1081. iwl_write8(priv, CSR_INT_PERIODIC_REG,
  1082. CSR_INT_PERIODIC_ENA);
  1083. priv->isr_stats.rx++;
  1084. }
  1085. /* This "Tx" DMA channel is used only for loading uCode */
  1086. if (inta & CSR_INT_BIT_FH_TX) {
  1087. iwl_write32(priv, CSR_FH_INT_STATUS, CSR49_FH_INT_TX_MASK);
  1088. IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
  1089. priv->isr_stats.tx++;
  1090. handled |= CSR_INT_BIT_FH_TX;
  1091. /* Wake up uCode load routine, now that load is complete */
  1092. priv->ucode_write_complete = 1;
  1093. wake_up_interruptible(&priv->wait_command_queue);
  1094. }
  1095. if (inta & ~handled) {
  1096. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  1097. priv->isr_stats.unhandled++;
  1098. }
  1099. if (inta & ~(priv->inta_mask)) {
  1100. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  1101. inta & ~priv->inta_mask);
  1102. }
  1103. /* Re-enable all interrupts */
  1104. /* only Re-enable if diabled by irq */
  1105. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  1106. iwl_enable_interrupts(priv);
  1107. }
  1108. /******************************************************************************
  1109. *
  1110. * uCode download functions
  1111. *
  1112. ******************************************************************************/
  1113. static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
  1114. {
  1115. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_code);
  1116. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data);
  1117. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1118. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init);
  1119. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1120. iwl_free_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1121. }
  1122. static void iwl_nic_start(struct iwl_priv *priv)
  1123. {
  1124. /* Remove all resets to allow NIC to operate */
  1125. iwl_write32(priv, CSR_RESET, 0);
  1126. }
  1127. /**
  1128. * iwl_read_ucode - Read uCode images from disk file.
  1129. *
  1130. * Copy into buffers for card to fetch via bus-mastering
  1131. */
  1132. static int iwl_read_ucode(struct iwl_priv *priv)
  1133. {
  1134. struct iwl_ucode_header *ucode;
  1135. int ret = -EINVAL, index;
  1136. const struct firmware *ucode_raw;
  1137. const char *name_pre = priv->cfg->fw_name_pre;
  1138. const unsigned int api_max = priv->cfg->ucode_api_max;
  1139. const unsigned int api_min = priv->cfg->ucode_api_min;
  1140. char buf[25];
  1141. u8 *src;
  1142. size_t len;
  1143. u32 api_ver, build;
  1144. u32 inst_size, data_size, init_size, init_data_size, boot_size;
  1145. u16 eeprom_ver;
  1146. /* Ask kernel firmware_class module to get the boot firmware off disk.
  1147. * request_firmware() is synchronous, file is in memory on return. */
  1148. for (index = api_max; index >= api_min; index--) {
  1149. sprintf(buf, "%s%d%s", name_pre, index, ".ucode");
  1150. ret = request_firmware(&ucode_raw, buf, &priv->pci_dev->dev);
  1151. if (ret < 0) {
  1152. IWL_ERR(priv, "%s firmware file req failed: %d\n",
  1153. buf, ret);
  1154. if (ret == -ENOENT)
  1155. continue;
  1156. else
  1157. goto error;
  1158. } else {
  1159. if (index < api_max)
  1160. IWL_ERR(priv, "Loaded firmware %s, "
  1161. "which is deprecated. "
  1162. "Please use API v%u instead.\n",
  1163. buf, api_max);
  1164. IWL_DEBUG_INFO(priv, "Got firmware '%s' file (%zd bytes) from disk\n",
  1165. buf, ucode_raw->size);
  1166. break;
  1167. }
  1168. }
  1169. if (ret < 0)
  1170. goto error;
  1171. /* Make sure that we got at least the v1 header! */
  1172. if (ucode_raw->size < priv->cfg->ops->ucode->get_header_size(1)) {
  1173. IWL_ERR(priv, "File size way too small!\n");
  1174. ret = -EINVAL;
  1175. goto err_release;
  1176. }
  1177. /* Data from ucode file: header followed by uCode images */
  1178. ucode = (struct iwl_ucode_header *)ucode_raw->data;
  1179. priv->ucode_ver = le32_to_cpu(ucode->ver);
  1180. api_ver = IWL_UCODE_API(priv->ucode_ver);
  1181. build = priv->cfg->ops->ucode->get_build(ucode, api_ver);
  1182. inst_size = priv->cfg->ops->ucode->get_inst_size(ucode, api_ver);
  1183. data_size = priv->cfg->ops->ucode->get_data_size(ucode, api_ver);
  1184. init_size = priv->cfg->ops->ucode->get_init_size(ucode, api_ver);
  1185. init_data_size =
  1186. priv->cfg->ops->ucode->get_init_data_size(ucode, api_ver);
  1187. boot_size = priv->cfg->ops->ucode->get_boot_size(ucode, api_ver);
  1188. src = priv->cfg->ops->ucode->get_data(ucode, api_ver);
  1189. /* api_ver should match the api version forming part of the
  1190. * firmware filename ... but we don't check for that and only rely
  1191. * on the API version read from firmware header from here on forward */
  1192. if (api_ver < api_min || api_ver > api_max) {
  1193. IWL_ERR(priv, "Driver unable to support your firmware API. "
  1194. "Driver supports v%u, firmware is v%u.\n",
  1195. api_max, api_ver);
  1196. priv->ucode_ver = 0;
  1197. ret = -EINVAL;
  1198. goto err_release;
  1199. }
  1200. if (api_ver != api_max)
  1201. IWL_ERR(priv, "Firmware has old API version. Expected v%u, "
  1202. "got v%u. New firmware can be obtained "
  1203. "from http://www.intellinuxwireless.org.\n",
  1204. api_max, api_ver);
  1205. IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u\n",
  1206. IWL_UCODE_MAJOR(priv->ucode_ver),
  1207. IWL_UCODE_MINOR(priv->ucode_ver),
  1208. IWL_UCODE_API(priv->ucode_ver),
  1209. IWL_UCODE_SERIAL(priv->ucode_ver));
  1210. snprintf(priv->hw->wiphy->fw_version,
  1211. sizeof(priv->hw->wiphy->fw_version),
  1212. "%u.%u.%u.%u",
  1213. IWL_UCODE_MAJOR(priv->ucode_ver),
  1214. IWL_UCODE_MINOR(priv->ucode_ver),
  1215. IWL_UCODE_API(priv->ucode_ver),
  1216. IWL_UCODE_SERIAL(priv->ucode_ver));
  1217. if (build)
  1218. IWL_DEBUG_INFO(priv, "Build %u\n", build);
  1219. eeprom_ver = iwl_eeprom_query16(priv, EEPROM_VERSION);
  1220. IWL_DEBUG_INFO(priv, "NVM Type: %s, version: 0x%x\n",
  1221. (priv->nvm_device_type == NVM_DEVICE_TYPE_OTP)
  1222. ? "OTP" : "EEPROM", eeprom_ver);
  1223. IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
  1224. priv->ucode_ver);
  1225. IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %u\n",
  1226. inst_size);
  1227. IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %u\n",
  1228. data_size);
  1229. IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %u\n",
  1230. init_size);
  1231. IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %u\n",
  1232. init_data_size);
  1233. IWL_DEBUG_INFO(priv, "f/w package hdr boot inst size = %u\n",
  1234. boot_size);
  1235. /* Verify size of file vs. image size info in file's header */
  1236. if (ucode_raw->size !=
  1237. priv->cfg->ops->ucode->get_header_size(api_ver) +
  1238. inst_size + data_size + init_size +
  1239. init_data_size + boot_size) {
  1240. IWL_DEBUG_INFO(priv,
  1241. "uCode file size %d does not match expected size\n",
  1242. (int)ucode_raw->size);
  1243. ret = -EINVAL;
  1244. goto err_release;
  1245. }
  1246. /* Verify that uCode images will fit in card's SRAM */
  1247. if (inst_size > priv->hw_params.max_inst_size) {
  1248. IWL_DEBUG_INFO(priv, "uCode instr len %d too large to fit in\n",
  1249. inst_size);
  1250. ret = -EINVAL;
  1251. goto err_release;
  1252. }
  1253. if (data_size > priv->hw_params.max_data_size) {
  1254. IWL_DEBUG_INFO(priv, "uCode data len %d too large to fit in\n",
  1255. data_size);
  1256. ret = -EINVAL;
  1257. goto err_release;
  1258. }
  1259. if (init_size > priv->hw_params.max_inst_size) {
  1260. IWL_INFO(priv, "uCode init instr len %d too large to fit in\n",
  1261. init_size);
  1262. ret = -EINVAL;
  1263. goto err_release;
  1264. }
  1265. if (init_data_size > priv->hw_params.max_data_size) {
  1266. IWL_INFO(priv, "uCode init data len %d too large to fit in\n",
  1267. init_data_size);
  1268. ret = -EINVAL;
  1269. goto err_release;
  1270. }
  1271. if (boot_size > priv->hw_params.max_bsm_size) {
  1272. IWL_INFO(priv, "uCode boot instr len %d too large to fit in\n",
  1273. boot_size);
  1274. ret = -EINVAL;
  1275. goto err_release;
  1276. }
  1277. /* Allocate ucode buffers for card's bus-master loading ... */
  1278. /* Runtime instructions and 2 copies of data:
  1279. * 1) unmodified from disk
  1280. * 2) backup cache for save/restore during power-downs */
  1281. priv->ucode_code.len = inst_size;
  1282. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_code);
  1283. priv->ucode_data.len = data_size;
  1284. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data);
  1285. priv->ucode_data_backup.len = data_size;
  1286. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_data_backup);
  1287. if (!priv->ucode_code.v_addr || !priv->ucode_data.v_addr ||
  1288. !priv->ucode_data_backup.v_addr)
  1289. goto err_pci_alloc;
  1290. /* Initialization instructions and data */
  1291. if (init_size && init_data_size) {
  1292. priv->ucode_init.len = init_size;
  1293. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init);
  1294. priv->ucode_init_data.len = init_data_size;
  1295. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init_data);
  1296. if (!priv->ucode_init.v_addr || !priv->ucode_init_data.v_addr)
  1297. goto err_pci_alloc;
  1298. }
  1299. /* Bootstrap (instructions only, no data) */
  1300. if (boot_size) {
  1301. priv->ucode_boot.len = boot_size;
  1302. iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_boot);
  1303. if (!priv->ucode_boot.v_addr)
  1304. goto err_pci_alloc;
  1305. }
  1306. /* Copy images into buffers for card's bus-master reads ... */
  1307. /* Runtime instructions (first block of data in file) */
  1308. len = inst_size;
  1309. IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode instr len %Zd\n", len);
  1310. memcpy(priv->ucode_code.v_addr, src, len);
  1311. src += len;
  1312. IWL_DEBUG_INFO(priv, "uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n",
  1313. priv->ucode_code.v_addr, (u32)priv->ucode_code.p_addr);
  1314. /* Runtime data (2nd block)
  1315. * NOTE: Copy into backup buffer will be done in iwl_up() */
  1316. len = data_size;
  1317. IWL_DEBUG_INFO(priv, "Copying (but not loading) uCode data len %Zd\n", len);
  1318. memcpy(priv->ucode_data.v_addr, src, len);
  1319. memcpy(priv->ucode_data_backup.v_addr, src, len);
  1320. src += len;
  1321. /* Initialization instructions (3rd block) */
  1322. if (init_size) {
  1323. len = init_size;
  1324. IWL_DEBUG_INFO(priv, "Copying (but not loading) init instr len %Zd\n",
  1325. len);
  1326. memcpy(priv->ucode_init.v_addr, src, len);
  1327. src += len;
  1328. }
  1329. /* Initialization data (4th block) */
  1330. if (init_data_size) {
  1331. len = init_data_size;
  1332. IWL_DEBUG_INFO(priv, "Copying (but not loading) init data len %Zd\n",
  1333. len);
  1334. memcpy(priv->ucode_init_data.v_addr, src, len);
  1335. src += len;
  1336. }
  1337. /* Bootstrap instructions (5th block) */
  1338. len = boot_size;
  1339. IWL_DEBUG_INFO(priv, "Copying (but not loading) boot instr len %Zd\n", len);
  1340. memcpy(priv->ucode_boot.v_addr, src, len);
  1341. /* We have our copies now, allow OS release its copies */
  1342. release_firmware(ucode_raw);
  1343. return 0;
  1344. err_pci_alloc:
  1345. IWL_ERR(priv, "failed to allocate pci memory\n");
  1346. ret = -ENOMEM;
  1347. iwl_dealloc_ucode_pci(priv);
  1348. err_release:
  1349. release_firmware(ucode_raw);
  1350. error:
  1351. return ret;
  1352. }
  1353. static const char *desc_lookup_text[] = {
  1354. "OK",
  1355. "FAIL",
  1356. "BAD_PARAM",
  1357. "BAD_CHECKSUM",
  1358. "NMI_INTERRUPT_WDG",
  1359. "SYSASSERT",
  1360. "FATAL_ERROR",
  1361. "BAD_COMMAND",
  1362. "HW_ERROR_TUNE_LOCK",
  1363. "HW_ERROR_TEMPERATURE",
  1364. "ILLEGAL_CHAN_FREQ",
  1365. "VCC_NOT_STABLE",
  1366. "FH_ERROR",
  1367. "NMI_INTERRUPT_HOST",
  1368. "NMI_INTERRUPT_ACTION_PT",
  1369. "NMI_INTERRUPT_UNKNOWN",
  1370. "UCODE_VERSION_MISMATCH",
  1371. "HW_ERROR_ABS_LOCK",
  1372. "HW_ERROR_CAL_LOCK_FAIL",
  1373. "NMI_INTERRUPT_INST_ACTION_PT",
  1374. "NMI_INTERRUPT_DATA_ACTION_PT",
  1375. "NMI_TRM_HW_ER",
  1376. "NMI_INTERRUPT_TRM",
  1377. "NMI_INTERRUPT_BREAK_POINT"
  1378. "DEBUG_0",
  1379. "DEBUG_1",
  1380. "DEBUG_2",
  1381. "DEBUG_3",
  1382. "UNKNOWN"
  1383. };
  1384. static const char *desc_lookup(int i)
  1385. {
  1386. int max = ARRAY_SIZE(desc_lookup_text) - 1;
  1387. if (i < 0 || i > max)
  1388. i = max;
  1389. return desc_lookup_text[i];
  1390. }
  1391. #define ERROR_START_OFFSET (1 * sizeof(u32))
  1392. #define ERROR_ELEM_SIZE (7 * sizeof(u32))
  1393. void iwl_dump_nic_error_log(struct iwl_priv *priv)
  1394. {
  1395. u32 data2, line;
  1396. u32 desc, time, count, base, data1;
  1397. u32 blink1, blink2, ilink1, ilink2;
  1398. if (priv->ucode_type == UCODE_INIT)
  1399. base = le32_to_cpu(priv->card_alive_init.error_event_table_ptr);
  1400. else
  1401. base = le32_to_cpu(priv->card_alive.error_event_table_ptr);
  1402. if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  1403. IWL_ERR(priv,
  1404. "Not valid error log pointer 0x%08X for %s uCode\n",
  1405. base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
  1406. return;
  1407. }
  1408. count = iwl_read_targ_mem(priv, base);
  1409. if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) {
  1410. IWL_ERR(priv, "Start IWL Error Log Dump:\n");
  1411. IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
  1412. priv->status, count);
  1413. }
  1414. desc = iwl_read_targ_mem(priv, base + 1 * sizeof(u32));
  1415. blink1 = iwl_read_targ_mem(priv, base + 3 * sizeof(u32));
  1416. blink2 = iwl_read_targ_mem(priv, base + 4 * sizeof(u32));
  1417. ilink1 = iwl_read_targ_mem(priv, base + 5 * sizeof(u32));
  1418. ilink2 = iwl_read_targ_mem(priv, base + 6 * sizeof(u32));
  1419. data1 = iwl_read_targ_mem(priv, base + 7 * sizeof(u32));
  1420. data2 = iwl_read_targ_mem(priv, base + 8 * sizeof(u32));
  1421. line = iwl_read_targ_mem(priv, base + 9 * sizeof(u32));
  1422. time = iwl_read_targ_mem(priv, base + 11 * sizeof(u32));
  1423. trace_iwlwifi_dev_ucode_error(priv, desc, time, data1, data2, line,
  1424. blink1, blink2, ilink1, ilink2);
  1425. IWL_ERR(priv, "Desc Time "
  1426. "data1 data2 line\n");
  1427. IWL_ERR(priv, "%-28s (#%02d) %010u 0x%08X 0x%08X %u\n",
  1428. desc_lookup(desc), desc, time, data1, data2, line);
  1429. IWL_ERR(priv, "blink1 blink2 ilink1 ilink2\n");
  1430. IWL_ERR(priv, "0x%05X 0x%05X 0x%05X 0x%05X\n", blink1, blink2,
  1431. ilink1, ilink2);
  1432. }
  1433. #define EVENT_START_OFFSET (4 * sizeof(u32))
  1434. /**
  1435. * iwl_print_event_log - Dump error event log to syslog
  1436. *
  1437. */
  1438. static void iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
  1439. u32 num_events, u32 mode)
  1440. {
  1441. u32 i;
  1442. u32 base; /* SRAM byte address of event log header */
  1443. u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
  1444. u32 ptr; /* SRAM byte address of log data */
  1445. u32 ev, time, data; /* event log data */
  1446. unsigned long reg_flags;
  1447. if (num_events == 0)
  1448. return;
  1449. if (priv->ucode_type == UCODE_INIT)
  1450. base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
  1451. else
  1452. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  1453. if (mode == 0)
  1454. event_size = 2 * sizeof(u32);
  1455. else
  1456. event_size = 3 * sizeof(u32);
  1457. ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
  1458. /* Make sure device is powered up for SRAM reads */
  1459. spin_lock_irqsave(&priv->reg_lock, reg_flags);
  1460. iwl_grab_nic_access(priv);
  1461. /* Set starting address; reads will auto-increment */
  1462. _iwl_write_direct32(priv, HBUS_TARG_MEM_RADDR, ptr);
  1463. rmb();
  1464. /* "time" is actually "data" for mode 0 (no timestamp).
  1465. * place event id # at far right for easier visual parsing. */
  1466. for (i = 0; i < num_events; i++) {
  1467. ev = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1468. time = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1469. if (mode == 0) {
  1470. /* data, ev */
  1471. trace_iwlwifi_dev_ucode_event(priv, 0, time, ev);
  1472. IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n", time, ev);
  1473. } else {
  1474. data = _iwl_read_direct32(priv, HBUS_TARG_MEM_RDAT);
  1475. IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
  1476. time, data, ev);
  1477. trace_iwlwifi_dev_ucode_event(priv, time, data, ev);
  1478. }
  1479. }
  1480. /* Allow device to power down */
  1481. iwl_release_nic_access(priv);
  1482. spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
  1483. }
  1484. /**
  1485. * iwl_print_last_event_logs - Dump the newest # of event log to syslog
  1486. */
  1487. static void iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
  1488. u32 num_wraps, u32 next_entry,
  1489. u32 size, u32 mode)
  1490. {
  1491. /*
  1492. * display the newest DEFAULT_LOG_ENTRIES entries
  1493. * i.e the entries just before the next ont that uCode would fill.
  1494. */
  1495. if (num_wraps) {
  1496. if (next_entry < size) {
  1497. iwl_print_event_log(priv,
  1498. capacity - (size - next_entry),
  1499. size - next_entry, mode);
  1500. iwl_print_event_log(priv, 0,
  1501. next_entry, mode);
  1502. } else
  1503. iwl_print_event_log(priv, next_entry - size,
  1504. size, mode);
  1505. } else {
  1506. if (next_entry < size)
  1507. iwl_print_event_log(priv, 0, next_entry, mode);
  1508. else
  1509. iwl_print_event_log(priv, next_entry - size,
  1510. size, mode);
  1511. }
  1512. }
  1513. /* For sanity check only. Actual size is determined by uCode, typ. 512 */
  1514. #define MAX_EVENT_LOG_SIZE (512)
  1515. #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
  1516. void iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log)
  1517. {
  1518. u32 base; /* SRAM byte address of event log header */
  1519. u32 capacity; /* event log capacity in # entries */
  1520. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  1521. u32 num_wraps; /* # times uCode wrapped to top of log */
  1522. u32 next_entry; /* index of next entry to be written by uCode */
  1523. u32 size; /* # entries that we'll print */
  1524. if (priv->ucode_type == UCODE_INIT)
  1525. base = le32_to_cpu(priv->card_alive_init.log_event_table_ptr);
  1526. else
  1527. base = le32_to_cpu(priv->card_alive.log_event_table_ptr);
  1528. if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  1529. IWL_ERR(priv,
  1530. "Invalid event log pointer 0x%08X for %s uCode\n",
  1531. base, (priv->ucode_type == UCODE_INIT) ? "Init" : "RT");
  1532. return;
  1533. }
  1534. /* event log header */
  1535. capacity = iwl_read_targ_mem(priv, base);
  1536. mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
  1537. num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
  1538. next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
  1539. if (capacity > MAX_EVENT_LOG_SIZE) {
  1540. IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
  1541. capacity, MAX_EVENT_LOG_SIZE);
  1542. capacity = MAX_EVENT_LOG_SIZE;
  1543. }
  1544. if (next_entry > MAX_EVENT_LOG_SIZE) {
  1545. IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
  1546. next_entry, MAX_EVENT_LOG_SIZE);
  1547. next_entry = MAX_EVENT_LOG_SIZE;
  1548. }
  1549. size = num_wraps ? capacity : next_entry;
  1550. /* bail out if nothing in log */
  1551. if (size == 0) {
  1552. IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
  1553. return;
  1554. }
  1555. #ifdef CONFIG_IWLWIFI_DEBUG
  1556. if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
  1557. size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
  1558. ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
  1559. #else
  1560. size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
  1561. ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
  1562. #endif
  1563. IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
  1564. size);
  1565. #ifdef CONFIG_IWLWIFI_DEBUG
  1566. if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
  1567. /*
  1568. * if uCode has wrapped back to top of log,
  1569. * start at the oldest entry,
  1570. * i.e the next one that uCode would fill.
  1571. */
  1572. if (num_wraps)
  1573. iwl_print_event_log(priv, next_entry,
  1574. capacity - next_entry, mode);
  1575. /* (then/else) start at top of log */
  1576. iwl_print_event_log(priv, 0, next_entry, mode);
  1577. } else
  1578. iwl_print_last_event_logs(priv, capacity, num_wraps,
  1579. next_entry, size, mode);
  1580. #else
  1581. iwl_print_last_event_logs(priv, capacity, num_wraps,
  1582. next_entry, size, mode);
  1583. #endif
  1584. }
  1585. /**
  1586. * iwl_alive_start - called after REPLY_ALIVE notification received
  1587. * from protocol/runtime uCode (initialization uCode's
  1588. * Alive gets handled by iwl_init_alive_start()).
  1589. */
  1590. static void iwl_alive_start(struct iwl_priv *priv)
  1591. {
  1592. int ret = 0;
  1593. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  1594. if (priv->card_alive.is_valid != UCODE_VALID_OK) {
  1595. /* We had an error bringing up the hardware, so take it
  1596. * all the way back down so we can try again */
  1597. IWL_DEBUG_INFO(priv, "Alive failed.\n");
  1598. goto restart;
  1599. }
  1600. /* Initialize uCode has loaded Runtime uCode ... verify inst image.
  1601. * This is a paranoid check, because we would not have gotten the
  1602. * "runtime" alive if code weren't properly loaded. */
  1603. if (iwl_verify_ucode(priv)) {
  1604. /* Runtime instruction load was bad;
  1605. * take it all the way back down so we can try again */
  1606. IWL_DEBUG_INFO(priv, "Bad runtime uCode load.\n");
  1607. goto restart;
  1608. }
  1609. iwl_clear_stations_table(priv);
  1610. ret = priv->cfg->ops->lib->alive_notify(priv);
  1611. if (ret) {
  1612. IWL_WARN(priv,
  1613. "Could not complete ALIVE transition [ntf]: %d\n", ret);
  1614. goto restart;
  1615. }
  1616. /* After the ALIVE response, we can send host commands to the uCode */
  1617. set_bit(STATUS_ALIVE, &priv->status);
  1618. if (iwl_is_rfkill(priv))
  1619. return;
  1620. ieee80211_wake_queues(priv->hw);
  1621. priv->active_rate = priv->rates_mask;
  1622. priv->active_rate_basic = priv->rates_mask & IWL_BASIC_RATES_MASK;
  1623. /* Configure Tx antenna selection based on H/W config */
  1624. if (priv->cfg->ops->hcmd->set_tx_ant)
  1625. priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
  1626. if (iwl_is_associated(priv)) {
  1627. struct iwl_rxon_cmd *active_rxon =
  1628. (struct iwl_rxon_cmd *)&priv->active_rxon;
  1629. /* apply any changes in staging */
  1630. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  1631. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  1632. } else {
  1633. /* Initialize our rx_config data */
  1634. iwl_connection_init_rx_config(priv, priv->iw_mode);
  1635. if (priv->cfg->ops->hcmd->set_rxon_chain)
  1636. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  1637. memcpy(priv->staging_rxon.node_addr, priv->mac_addr, ETH_ALEN);
  1638. }
  1639. /* Configure Bluetooth device coexistence support */
  1640. iwl_send_bt_config(priv);
  1641. iwl_reset_run_time_calib(priv);
  1642. /* Configure the adapter for unassociated operation */
  1643. iwlcore_commit_rxon(priv);
  1644. /* At this point, the NIC is initialized and operational */
  1645. iwl_rf_kill_ct_config(priv);
  1646. iwl_leds_init(priv);
  1647. IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
  1648. set_bit(STATUS_READY, &priv->status);
  1649. wake_up_interruptible(&priv->wait_command_queue);
  1650. iwl_power_update_mode(priv, true);
  1651. /* reassociate for ADHOC mode */
  1652. if (priv->vif && (priv->iw_mode == NL80211_IFTYPE_ADHOC)) {
  1653. struct sk_buff *beacon = ieee80211_beacon_get(priv->hw,
  1654. priv->vif);
  1655. if (beacon)
  1656. iwl_mac_beacon_update(priv->hw, beacon);
  1657. }
  1658. if (test_and_clear_bit(STATUS_MODE_PENDING, &priv->status))
  1659. iwl_set_mode(priv, priv->iw_mode);
  1660. return;
  1661. restart:
  1662. queue_work(priv->workqueue, &priv->restart);
  1663. }
  1664. static void iwl_cancel_deferred_work(struct iwl_priv *priv);
  1665. static void __iwl_down(struct iwl_priv *priv)
  1666. {
  1667. unsigned long flags;
  1668. int exit_pending = test_bit(STATUS_EXIT_PENDING, &priv->status);
  1669. IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
  1670. if (!exit_pending)
  1671. set_bit(STATUS_EXIT_PENDING, &priv->status);
  1672. iwl_clear_stations_table(priv);
  1673. /* Unblock any waiting calls */
  1674. wake_up_interruptible_all(&priv->wait_command_queue);
  1675. /* Wipe out the EXIT_PENDING status bit if we are not actually
  1676. * exiting the module */
  1677. if (!exit_pending)
  1678. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  1679. /* stop and reset the on-board processor */
  1680. iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  1681. /* tell the device to stop sending interrupts */
  1682. spin_lock_irqsave(&priv->lock, flags);
  1683. iwl_disable_interrupts(priv);
  1684. spin_unlock_irqrestore(&priv->lock, flags);
  1685. iwl_synchronize_irq(priv);
  1686. if (priv->mac80211_registered)
  1687. ieee80211_stop_queues(priv->hw);
  1688. /* If we have not previously called iwl_init() then
  1689. * clear all bits but the RF Kill bit and return */
  1690. if (!iwl_is_init(priv)) {
  1691. priv->status = test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  1692. STATUS_RF_KILL_HW |
  1693. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  1694. STATUS_GEO_CONFIGURED |
  1695. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  1696. STATUS_EXIT_PENDING;
  1697. goto exit;
  1698. }
  1699. /* ...otherwise clear out all the status bits but the RF Kill
  1700. * bit and continue taking the NIC down. */
  1701. priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  1702. STATUS_RF_KILL_HW |
  1703. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  1704. STATUS_GEO_CONFIGURED |
  1705. test_bit(STATUS_FW_ERROR, &priv->status) <<
  1706. STATUS_FW_ERROR |
  1707. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  1708. STATUS_EXIT_PENDING;
  1709. /* device going down, Stop using ICT table */
  1710. iwl_disable_ict(priv);
  1711. iwl_txq_ctx_stop(priv);
  1712. iwl_rxq_stop(priv);
  1713. /* Power-down device's busmaster DMA clocks */
  1714. iwl_write_prph(priv, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT);
  1715. udelay(5);
  1716. /* Make sure (redundant) we've released our request to stay awake */
  1717. iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
  1718. /* Stop the device, and put it in low power state */
  1719. priv->cfg->ops->lib->apm_ops.stop(priv);
  1720. exit:
  1721. memset(&priv->card_alive, 0, sizeof(struct iwl_alive_resp));
  1722. if (priv->ibss_beacon)
  1723. dev_kfree_skb(priv->ibss_beacon);
  1724. priv->ibss_beacon = NULL;
  1725. /* clear out any free frames */
  1726. iwl_clear_free_frames(priv);
  1727. }
  1728. static void iwl_down(struct iwl_priv *priv)
  1729. {
  1730. mutex_lock(&priv->mutex);
  1731. __iwl_down(priv);
  1732. mutex_unlock(&priv->mutex);
  1733. iwl_cancel_deferred_work(priv);
  1734. }
  1735. #define HW_READY_TIMEOUT (50)
  1736. static int iwl_set_hw_ready(struct iwl_priv *priv)
  1737. {
  1738. int ret = 0;
  1739. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  1740. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
  1741. /* See if we got it */
  1742. ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
  1743. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
  1744. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
  1745. HW_READY_TIMEOUT);
  1746. if (ret != -ETIMEDOUT)
  1747. priv->hw_ready = true;
  1748. else
  1749. priv->hw_ready = false;
  1750. IWL_DEBUG_INFO(priv, "hardware %s\n",
  1751. (priv->hw_ready == 1) ? "ready" : "not ready");
  1752. return ret;
  1753. }
  1754. static int iwl_prepare_card_hw(struct iwl_priv *priv)
  1755. {
  1756. int ret = 0;
  1757. IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter \n");
  1758. ret = iwl_set_hw_ready(priv);
  1759. if (priv->hw_ready)
  1760. return ret;
  1761. /* If HW is not ready, prepare the conditions to check again */
  1762. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  1763. CSR_HW_IF_CONFIG_REG_PREPARE);
  1764. ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
  1765. ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
  1766. CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
  1767. /* HW should be ready by now, check again. */
  1768. if (ret != -ETIMEDOUT)
  1769. iwl_set_hw_ready(priv);
  1770. return ret;
  1771. }
  1772. #define MAX_HW_RESTARTS 5
  1773. static int __iwl_up(struct iwl_priv *priv)
  1774. {
  1775. int i;
  1776. int ret;
  1777. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  1778. IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
  1779. return -EIO;
  1780. }
  1781. if (!priv->ucode_data_backup.v_addr || !priv->ucode_data.v_addr) {
  1782. IWL_ERR(priv, "ucode not available for device bringup\n");
  1783. return -EIO;
  1784. }
  1785. iwl_prepare_card_hw(priv);
  1786. if (!priv->hw_ready) {
  1787. IWL_WARN(priv, "Exit HW not ready\n");
  1788. return -EIO;
  1789. }
  1790. /* If platform's RF_KILL switch is NOT set to KILL */
  1791. if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  1792. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  1793. else
  1794. set_bit(STATUS_RF_KILL_HW, &priv->status);
  1795. if (iwl_is_rfkill(priv)) {
  1796. wiphy_rfkill_set_hw_state(priv->hw->wiphy, true);
  1797. iwl_enable_interrupts(priv);
  1798. IWL_WARN(priv, "Radio disabled by HW RF Kill switch\n");
  1799. return 0;
  1800. }
  1801. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  1802. ret = iwl_hw_nic_init(priv);
  1803. if (ret) {
  1804. IWL_ERR(priv, "Unable to init nic\n");
  1805. return ret;
  1806. }
  1807. /* make sure rfkill handshake bits are cleared */
  1808. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1809. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  1810. CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED);
  1811. /* clear (again), then enable host interrupts */
  1812. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  1813. iwl_enable_interrupts(priv);
  1814. /* really make sure rfkill handshake bits are cleared */
  1815. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1816. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL);
  1817. /* Copy original ucode data image from disk into backup cache.
  1818. * This will be used to initialize the on-board processor's
  1819. * data SRAM for a clean start when the runtime program first loads. */
  1820. memcpy(priv->ucode_data_backup.v_addr, priv->ucode_data.v_addr,
  1821. priv->ucode_data.len);
  1822. for (i = 0; i < MAX_HW_RESTARTS; i++) {
  1823. iwl_clear_stations_table(priv);
  1824. /* load bootstrap state machine,
  1825. * load bootstrap program into processor's memory,
  1826. * prepare to load the "initialize" uCode */
  1827. ret = priv->cfg->ops->lib->load_ucode(priv);
  1828. if (ret) {
  1829. IWL_ERR(priv, "Unable to set up bootstrap uCode: %d\n",
  1830. ret);
  1831. continue;
  1832. }
  1833. /* start card; "initialize" will load runtime ucode */
  1834. iwl_nic_start(priv);
  1835. IWL_DEBUG_INFO(priv, DRV_NAME " is coming up\n");
  1836. return 0;
  1837. }
  1838. set_bit(STATUS_EXIT_PENDING, &priv->status);
  1839. __iwl_down(priv);
  1840. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  1841. /* tried to restart and config the device for as long as our
  1842. * patience could withstand */
  1843. IWL_ERR(priv, "Unable to initialize device after %d attempts.\n", i);
  1844. return -EIO;
  1845. }
  1846. /*****************************************************************************
  1847. *
  1848. * Workqueue callbacks
  1849. *
  1850. *****************************************************************************/
  1851. static void iwl_bg_init_alive_start(struct work_struct *data)
  1852. {
  1853. struct iwl_priv *priv =
  1854. container_of(data, struct iwl_priv, init_alive_start.work);
  1855. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1856. return;
  1857. mutex_lock(&priv->mutex);
  1858. priv->cfg->ops->lib->init_alive_start(priv);
  1859. mutex_unlock(&priv->mutex);
  1860. }
  1861. static void iwl_bg_alive_start(struct work_struct *data)
  1862. {
  1863. struct iwl_priv *priv =
  1864. container_of(data, struct iwl_priv, alive_start.work);
  1865. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1866. return;
  1867. /* enable dram interrupt */
  1868. iwl_reset_ict(priv);
  1869. mutex_lock(&priv->mutex);
  1870. iwl_alive_start(priv);
  1871. mutex_unlock(&priv->mutex);
  1872. }
  1873. static void iwl_bg_run_time_calib_work(struct work_struct *work)
  1874. {
  1875. struct iwl_priv *priv = container_of(work, struct iwl_priv,
  1876. run_time_calib_work);
  1877. mutex_lock(&priv->mutex);
  1878. if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
  1879. test_bit(STATUS_SCANNING, &priv->status)) {
  1880. mutex_unlock(&priv->mutex);
  1881. return;
  1882. }
  1883. if (priv->start_calib) {
  1884. iwl_chain_noise_calibration(priv, &priv->statistics);
  1885. iwl_sensitivity_calibration(priv, &priv->statistics);
  1886. }
  1887. mutex_unlock(&priv->mutex);
  1888. return;
  1889. }
  1890. static void iwl_bg_up(struct work_struct *data)
  1891. {
  1892. struct iwl_priv *priv = container_of(data, struct iwl_priv, up);
  1893. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1894. return;
  1895. mutex_lock(&priv->mutex);
  1896. __iwl_up(priv);
  1897. mutex_unlock(&priv->mutex);
  1898. }
  1899. static void iwl_bg_restart(struct work_struct *data)
  1900. {
  1901. struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
  1902. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1903. return;
  1904. if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
  1905. mutex_lock(&priv->mutex);
  1906. priv->vif = NULL;
  1907. priv->is_open = 0;
  1908. mutex_unlock(&priv->mutex);
  1909. iwl_down(priv);
  1910. ieee80211_restart_hw(priv->hw);
  1911. } else {
  1912. iwl_down(priv);
  1913. queue_work(priv->workqueue, &priv->up);
  1914. }
  1915. }
  1916. static void iwl_bg_rx_replenish(struct work_struct *data)
  1917. {
  1918. struct iwl_priv *priv =
  1919. container_of(data, struct iwl_priv, rx_replenish);
  1920. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1921. return;
  1922. mutex_lock(&priv->mutex);
  1923. iwl_rx_replenish(priv);
  1924. mutex_unlock(&priv->mutex);
  1925. }
  1926. #define IWL_DELAY_NEXT_SCAN (HZ*2)
  1927. void iwl_post_associate(struct iwl_priv *priv)
  1928. {
  1929. struct ieee80211_conf *conf = NULL;
  1930. int ret = 0;
  1931. unsigned long flags;
  1932. if (priv->iw_mode == NL80211_IFTYPE_AP) {
  1933. IWL_ERR(priv, "%s Should not be called in AP mode\n", __func__);
  1934. return;
  1935. }
  1936. IWL_DEBUG_ASSOC(priv, "Associated as %d to: %pM\n",
  1937. priv->assoc_id, priv->active_rxon.bssid_addr);
  1938. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1939. return;
  1940. if (!priv->vif || !priv->is_open)
  1941. return;
  1942. iwl_scan_cancel_timeout(priv, 200);
  1943. conf = ieee80211_get_hw_conf(priv->hw);
  1944. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  1945. iwlcore_commit_rxon(priv);
  1946. iwl_setup_rxon_timing(priv);
  1947. ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  1948. sizeof(priv->rxon_timing), &priv->rxon_timing);
  1949. if (ret)
  1950. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  1951. "Attempting to continue.\n");
  1952. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  1953. iwl_set_rxon_ht(priv, &priv->current_ht_config);
  1954. if (priv->cfg->ops->hcmd->set_rxon_chain)
  1955. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  1956. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  1957. IWL_DEBUG_ASSOC(priv, "assoc id %d beacon interval %d\n",
  1958. priv->assoc_id, priv->beacon_int);
  1959. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  1960. priv->staging_rxon.flags |= RXON_FLG_SHORT_PREAMBLE_MSK;
  1961. else
  1962. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_PREAMBLE_MSK;
  1963. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  1964. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_SLOT_TIME)
  1965. priv->staging_rxon.flags |= RXON_FLG_SHORT_SLOT_MSK;
  1966. else
  1967. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1968. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  1969. priv->staging_rxon.flags &= ~RXON_FLG_SHORT_SLOT_MSK;
  1970. }
  1971. iwlcore_commit_rxon(priv);
  1972. switch (priv->iw_mode) {
  1973. case NL80211_IFTYPE_STATION:
  1974. break;
  1975. case NL80211_IFTYPE_ADHOC:
  1976. /* assume default assoc id */
  1977. priv->assoc_id = 1;
  1978. iwl_rxon_add_station(priv, priv->bssid, 0);
  1979. iwl_send_beacon_cmd(priv);
  1980. break;
  1981. default:
  1982. IWL_ERR(priv, "%s Should not be called in %d mode\n",
  1983. __func__, priv->iw_mode);
  1984. break;
  1985. }
  1986. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  1987. priv->assoc_station_added = 1;
  1988. spin_lock_irqsave(&priv->lock, flags);
  1989. iwl_activate_qos(priv, 0);
  1990. spin_unlock_irqrestore(&priv->lock, flags);
  1991. /* the chain noise calibration will enabled PM upon completion
  1992. * If chain noise has already been run, then we need to enable
  1993. * power management here */
  1994. if (priv->chain_noise_data.state == IWL_CHAIN_NOISE_DONE)
  1995. iwl_power_update_mode(priv, false);
  1996. /* Enable Rx differential gain and sensitivity calibrations */
  1997. iwl_chain_noise_reset(priv);
  1998. priv->start_calib = 1;
  1999. }
  2000. /*****************************************************************************
  2001. *
  2002. * mac80211 entry point functions
  2003. *
  2004. *****************************************************************************/
  2005. #define UCODE_READY_TIMEOUT (4 * HZ)
  2006. /*
  2007. * Not a mac80211 entry point function, but it fits in with all the
  2008. * other mac80211 functions grouped here.
  2009. */
  2010. static int iwl_setup_mac(struct iwl_priv *priv)
  2011. {
  2012. int ret;
  2013. struct ieee80211_hw *hw = priv->hw;
  2014. hw->rate_control_algorithm = "iwl-agn-rs";
  2015. /* Tell mac80211 our characteristics */
  2016. hw->flags = IEEE80211_HW_SIGNAL_DBM |
  2017. IEEE80211_HW_NOISE_DBM |
  2018. IEEE80211_HW_AMPDU_AGGREGATION |
  2019. IEEE80211_HW_SPECTRUM_MGMT;
  2020. if (!priv->cfg->broken_powersave)
  2021. hw->flags |= IEEE80211_HW_SUPPORTS_PS |
  2022. IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
  2023. hw->sta_data_size = sizeof(struct iwl_station_priv);
  2024. hw->wiphy->interface_modes =
  2025. BIT(NL80211_IFTYPE_STATION) |
  2026. BIT(NL80211_IFTYPE_ADHOC);
  2027. hw->wiphy->flags |= WIPHY_FLAG_STRICT_REGULATORY |
  2028. WIPHY_FLAG_DISABLE_BEACON_HINTS;
  2029. /*
  2030. * For now, disable PS by default because it affects
  2031. * RX performance significantly.
  2032. */
  2033. hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
  2034. hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
  2035. /* we create the 802.11 header and a zero-length SSID element */
  2036. hw->wiphy->max_scan_ie_len = IWL_MAX_PROBE_REQUEST - 24 - 2;
  2037. /* Default value; 4 EDCA QOS priorities */
  2038. hw->queues = 4;
  2039. hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
  2040. if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
  2041. priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  2042. &priv->bands[IEEE80211_BAND_2GHZ];
  2043. if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
  2044. priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  2045. &priv->bands[IEEE80211_BAND_5GHZ];
  2046. ret = ieee80211_register_hw(priv->hw);
  2047. if (ret) {
  2048. IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
  2049. return ret;
  2050. }
  2051. priv->mac80211_registered = 1;
  2052. return 0;
  2053. }
  2054. static int iwl_mac_start(struct ieee80211_hw *hw)
  2055. {
  2056. struct iwl_priv *priv = hw->priv;
  2057. int ret;
  2058. IWL_DEBUG_MAC80211(priv, "enter\n");
  2059. /* we should be verifying the device is ready to be opened */
  2060. mutex_lock(&priv->mutex);
  2061. /* fetch ucode file from disk, alloc and copy to bus-master buffers ...
  2062. * ucode filename and max sizes are card-specific. */
  2063. if (!priv->ucode_code.len) {
  2064. ret = iwl_read_ucode(priv);
  2065. if (ret) {
  2066. IWL_ERR(priv, "Could not read microcode: %d\n", ret);
  2067. mutex_unlock(&priv->mutex);
  2068. return ret;
  2069. }
  2070. }
  2071. ret = __iwl_up(priv);
  2072. mutex_unlock(&priv->mutex);
  2073. if (ret)
  2074. return ret;
  2075. if (iwl_is_rfkill(priv))
  2076. goto out;
  2077. IWL_DEBUG_INFO(priv, "Start UP work done.\n");
  2078. /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from
  2079. * mac80211 will not be run successfully. */
  2080. ret = wait_event_interruptible_timeout(priv->wait_command_queue,
  2081. test_bit(STATUS_READY, &priv->status),
  2082. UCODE_READY_TIMEOUT);
  2083. if (!ret) {
  2084. if (!test_bit(STATUS_READY, &priv->status)) {
  2085. IWL_ERR(priv, "START_ALIVE timeout after %dms.\n",
  2086. jiffies_to_msecs(UCODE_READY_TIMEOUT));
  2087. return -ETIMEDOUT;
  2088. }
  2089. }
  2090. iwl_led_start(priv);
  2091. out:
  2092. priv->is_open = 1;
  2093. IWL_DEBUG_MAC80211(priv, "leave\n");
  2094. return 0;
  2095. }
  2096. static void iwl_mac_stop(struct ieee80211_hw *hw)
  2097. {
  2098. struct iwl_priv *priv = hw->priv;
  2099. IWL_DEBUG_MAC80211(priv, "enter\n");
  2100. if (!priv->is_open)
  2101. return;
  2102. priv->is_open = 0;
  2103. if (iwl_is_ready_rf(priv) || test_bit(STATUS_SCAN_HW, &priv->status)) {
  2104. /* stop mac, cancel any scan request and clear
  2105. * RXON_FILTER_ASSOC_MSK BIT
  2106. */
  2107. mutex_lock(&priv->mutex);
  2108. iwl_scan_cancel_timeout(priv, 100);
  2109. mutex_unlock(&priv->mutex);
  2110. }
  2111. iwl_down(priv);
  2112. flush_workqueue(priv->workqueue);
  2113. /* enable interrupts again in order to receive rfkill changes */
  2114. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  2115. iwl_enable_interrupts(priv);
  2116. IWL_DEBUG_MAC80211(priv, "leave\n");
  2117. }
  2118. static int iwl_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  2119. {
  2120. struct iwl_priv *priv = hw->priv;
  2121. IWL_DEBUG_MACDUMP(priv, "enter\n");
  2122. IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
  2123. ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
  2124. if (iwl_tx_skb(priv, skb))
  2125. dev_kfree_skb_any(skb);
  2126. IWL_DEBUG_MACDUMP(priv, "leave\n");
  2127. return NETDEV_TX_OK;
  2128. }
  2129. void iwl_config_ap(struct iwl_priv *priv)
  2130. {
  2131. int ret = 0;
  2132. unsigned long flags;
  2133. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2134. return;
  2135. /* The following should be done only at AP bring up */
  2136. if (!iwl_is_associated(priv)) {
  2137. /* RXON - unassoc (to set timing command) */
  2138. priv->staging_rxon.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2139. iwlcore_commit_rxon(priv);
  2140. /* RXON Timing */
  2141. iwl_setup_rxon_timing(priv);
  2142. ret = iwl_send_cmd_pdu(priv, REPLY_RXON_TIMING,
  2143. sizeof(priv->rxon_timing), &priv->rxon_timing);
  2144. if (ret)
  2145. IWL_WARN(priv, "REPLY_RXON_TIMING failed - "
  2146. "Attempting to continue.\n");
  2147. /* AP has all antennas */
  2148. priv->chain_noise_data.active_chains =
  2149. priv->hw_params.valid_rx_ant;
  2150. iwl_set_rxon_ht(priv, &priv->current_ht_config);
  2151. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2152. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2153. /* FIXME: what should be the assoc_id for AP? */
  2154. priv->staging_rxon.assoc_id = cpu_to_le16(priv->assoc_id);
  2155. if (priv->assoc_capability & WLAN_CAPABILITY_SHORT_PREAMBLE)
  2156. priv->staging_rxon.flags |=
  2157. RXON_FLG_SHORT_PREAMBLE_MSK;
  2158. else
  2159. priv->staging_rxon.flags &=
  2160. ~RXON_FLG_SHORT_PREAMBLE_MSK;
  2161. if (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) {
  2162. if (priv->assoc_capability &
  2163. WLAN_CAPABILITY_SHORT_SLOT_TIME)
  2164. priv->staging_rxon.flags |=
  2165. RXON_FLG_SHORT_SLOT_MSK;
  2166. else
  2167. priv->staging_rxon.flags &=
  2168. ~RXON_FLG_SHORT_SLOT_MSK;
  2169. if (priv->iw_mode == NL80211_IFTYPE_ADHOC)
  2170. priv->staging_rxon.flags &=
  2171. ~RXON_FLG_SHORT_SLOT_MSK;
  2172. }
  2173. /* restore RXON assoc */
  2174. priv->staging_rxon.filter_flags |= RXON_FILTER_ASSOC_MSK;
  2175. iwlcore_commit_rxon(priv);
  2176. iwl_reset_qos(priv);
  2177. spin_lock_irqsave(&priv->lock, flags);
  2178. iwl_activate_qos(priv, 1);
  2179. spin_unlock_irqrestore(&priv->lock, flags);
  2180. iwl_add_bcast_station(priv);
  2181. }
  2182. iwl_send_beacon_cmd(priv);
  2183. /* FIXME - we need to add code here to detect a totally new
  2184. * configuration, reset the AP, unassoc, rxon timing, assoc,
  2185. * clear sta table, add BCAST sta... */
  2186. }
  2187. static void iwl_mac_update_tkip_key(struct ieee80211_hw *hw,
  2188. struct ieee80211_key_conf *keyconf, const u8 *addr,
  2189. u32 iv32, u16 *phase1key)
  2190. {
  2191. struct iwl_priv *priv = hw->priv;
  2192. IWL_DEBUG_MAC80211(priv, "enter\n");
  2193. iwl_update_tkip_key(priv, keyconf, addr, iv32, phase1key);
  2194. IWL_DEBUG_MAC80211(priv, "leave\n");
  2195. }
  2196. static int iwl_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  2197. struct ieee80211_vif *vif,
  2198. struct ieee80211_sta *sta,
  2199. struct ieee80211_key_conf *key)
  2200. {
  2201. struct iwl_priv *priv = hw->priv;
  2202. const u8 *addr;
  2203. int ret;
  2204. u8 sta_id;
  2205. bool is_default_wep_key = false;
  2206. IWL_DEBUG_MAC80211(priv, "enter\n");
  2207. if (priv->cfg->mod_params->sw_crypto) {
  2208. IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
  2209. return -EOPNOTSUPP;
  2210. }
  2211. addr = sta ? sta->addr : iwl_bcast_addr;
  2212. sta_id = iwl_find_station(priv, addr);
  2213. if (sta_id == IWL_INVALID_STATION) {
  2214. IWL_DEBUG_MAC80211(priv, "leave - %pM not in station map.\n",
  2215. addr);
  2216. return -EINVAL;
  2217. }
  2218. mutex_lock(&priv->mutex);
  2219. iwl_scan_cancel_timeout(priv, 100);
  2220. mutex_unlock(&priv->mutex);
  2221. /* If we are getting WEP group key and we didn't receive any key mapping
  2222. * so far, we are in legacy wep mode (group key only), otherwise we are
  2223. * in 1X mode.
  2224. * In legacy wep mode, we use another host command to the uCode */
  2225. if (key->alg == ALG_WEP && sta_id == priv->hw_params.bcast_sta_id &&
  2226. priv->iw_mode != NL80211_IFTYPE_AP) {
  2227. if (cmd == SET_KEY)
  2228. is_default_wep_key = !priv->key_mapping_key;
  2229. else
  2230. is_default_wep_key =
  2231. (key->hw_key_idx == HW_KEY_DEFAULT);
  2232. }
  2233. switch (cmd) {
  2234. case SET_KEY:
  2235. if (is_default_wep_key)
  2236. ret = iwl_set_default_wep_key(priv, key);
  2237. else
  2238. ret = iwl_set_dynamic_key(priv, key, sta_id);
  2239. IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
  2240. break;
  2241. case DISABLE_KEY:
  2242. if (is_default_wep_key)
  2243. ret = iwl_remove_default_wep_key(priv, key);
  2244. else
  2245. ret = iwl_remove_dynamic_key(priv, key, sta_id);
  2246. IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
  2247. break;
  2248. default:
  2249. ret = -EINVAL;
  2250. }
  2251. IWL_DEBUG_MAC80211(priv, "leave\n");
  2252. return ret;
  2253. }
  2254. static int iwl_mac_ampdu_action(struct ieee80211_hw *hw,
  2255. struct ieee80211_vif *vif,
  2256. enum ieee80211_ampdu_mlme_action action,
  2257. struct ieee80211_sta *sta, u16 tid, u16 *ssn)
  2258. {
  2259. struct iwl_priv *priv = hw->priv;
  2260. int ret;
  2261. IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
  2262. sta->addr, tid);
  2263. if (!(priv->cfg->sku & IWL_SKU_N))
  2264. return -EACCES;
  2265. switch (action) {
  2266. case IEEE80211_AMPDU_RX_START:
  2267. IWL_DEBUG_HT(priv, "start Rx\n");
  2268. return iwl_sta_rx_agg_start(priv, sta->addr, tid, *ssn);
  2269. case IEEE80211_AMPDU_RX_STOP:
  2270. IWL_DEBUG_HT(priv, "stop Rx\n");
  2271. ret = iwl_sta_rx_agg_stop(priv, sta->addr, tid);
  2272. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2273. return 0;
  2274. else
  2275. return ret;
  2276. case IEEE80211_AMPDU_TX_START:
  2277. IWL_DEBUG_HT(priv, "start Tx\n");
  2278. return iwl_tx_agg_start(priv, sta->addr, tid, ssn);
  2279. case IEEE80211_AMPDU_TX_STOP:
  2280. IWL_DEBUG_HT(priv, "stop Tx\n");
  2281. ret = iwl_tx_agg_stop(priv, sta->addr, tid);
  2282. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2283. return 0;
  2284. else
  2285. return ret;
  2286. default:
  2287. IWL_DEBUG_HT(priv, "unknown\n");
  2288. return -EINVAL;
  2289. break;
  2290. }
  2291. return 0;
  2292. }
  2293. static int iwl_mac_get_stats(struct ieee80211_hw *hw,
  2294. struct ieee80211_low_level_stats *stats)
  2295. {
  2296. struct iwl_priv *priv = hw->priv;
  2297. priv = hw->priv;
  2298. IWL_DEBUG_MAC80211(priv, "enter\n");
  2299. IWL_DEBUG_MAC80211(priv, "leave\n");
  2300. return 0;
  2301. }
  2302. static void iwl_mac_sta_notify(struct ieee80211_hw *hw,
  2303. struct ieee80211_vif *vif,
  2304. enum sta_notify_cmd cmd,
  2305. struct ieee80211_sta *sta)
  2306. {
  2307. struct iwl_priv *priv = hw->priv;
  2308. struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
  2309. int sta_id;
  2310. /*
  2311. * TODO: We really should use this callback to
  2312. * actually maintain the station table in
  2313. * the device.
  2314. */
  2315. switch (cmd) {
  2316. case STA_NOTIFY_ADD:
  2317. atomic_set(&sta_priv->pending_frames, 0);
  2318. if (vif->type == NL80211_IFTYPE_AP)
  2319. sta_priv->client = true;
  2320. break;
  2321. case STA_NOTIFY_SLEEP:
  2322. WARN_ON(!sta_priv->client);
  2323. sta_priv->asleep = true;
  2324. if (atomic_read(&sta_priv->pending_frames) > 0)
  2325. ieee80211_sta_block_awake(hw, sta, true);
  2326. break;
  2327. case STA_NOTIFY_AWAKE:
  2328. WARN_ON(!sta_priv->client);
  2329. sta_priv->asleep = false;
  2330. sta_id = iwl_find_station(priv, sta->addr);
  2331. if (sta_id != IWL_INVALID_STATION)
  2332. iwl_sta_modify_ps_wake(priv, sta_id);
  2333. break;
  2334. default:
  2335. break;
  2336. }
  2337. }
  2338. /*****************************************************************************
  2339. *
  2340. * sysfs attributes
  2341. *
  2342. *****************************************************************************/
  2343. #ifdef CONFIG_IWLWIFI_DEBUG
  2344. /*
  2345. * The following adds a new attribute to the sysfs representation
  2346. * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
  2347. * used for controlling the debug level.
  2348. *
  2349. * See the level definitions in iwl for details.
  2350. *
  2351. * The debug_level being managed using sysfs below is a per device debug
  2352. * level that is used instead of the global debug level if it (the per
  2353. * device debug level) is set.
  2354. */
  2355. static ssize_t show_debug_level(struct device *d,
  2356. struct device_attribute *attr, char *buf)
  2357. {
  2358. struct iwl_priv *priv = dev_get_drvdata(d);
  2359. return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
  2360. }
  2361. static ssize_t store_debug_level(struct device *d,
  2362. struct device_attribute *attr,
  2363. const char *buf, size_t count)
  2364. {
  2365. struct iwl_priv *priv = dev_get_drvdata(d);
  2366. unsigned long val;
  2367. int ret;
  2368. ret = strict_strtoul(buf, 0, &val);
  2369. if (ret)
  2370. IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
  2371. else {
  2372. priv->debug_level = val;
  2373. if (iwl_alloc_traffic_mem(priv))
  2374. IWL_ERR(priv,
  2375. "Not enough memory to generate traffic log\n");
  2376. }
  2377. return strnlen(buf, count);
  2378. }
  2379. static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
  2380. show_debug_level, store_debug_level);
  2381. #endif /* CONFIG_IWLWIFI_DEBUG */
  2382. static ssize_t show_temperature(struct device *d,
  2383. struct device_attribute *attr, char *buf)
  2384. {
  2385. struct iwl_priv *priv = dev_get_drvdata(d);
  2386. if (!iwl_is_alive(priv))
  2387. return -EAGAIN;
  2388. return sprintf(buf, "%d\n", priv->temperature);
  2389. }
  2390. static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
  2391. static ssize_t show_tx_power(struct device *d,
  2392. struct device_attribute *attr, char *buf)
  2393. {
  2394. struct iwl_priv *priv = dev_get_drvdata(d);
  2395. if (!iwl_is_ready_rf(priv))
  2396. return sprintf(buf, "off\n");
  2397. else
  2398. return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
  2399. }
  2400. static ssize_t store_tx_power(struct device *d,
  2401. struct device_attribute *attr,
  2402. const char *buf, size_t count)
  2403. {
  2404. struct iwl_priv *priv = dev_get_drvdata(d);
  2405. unsigned long val;
  2406. int ret;
  2407. ret = strict_strtoul(buf, 10, &val);
  2408. if (ret)
  2409. IWL_INFO(priv, "%s is not in decimal form.\n", buf);
  2410. else {
  2411. ret = iwl_set_tx_power(priv, val, false);
  2412. if (ret)
  2413. IWL_ERR(priv, "failed setting tx power (0x%d).\n",
  2414. ret);
  2415. else
  2416. ret = count;
  2417. }
  2418. return ret;
  2419. }
  2420. static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
  2421. static ssize_t show_flags(struct device *d,
  2422. struct device_attribute *attr, char *buf)
  2423. {
  2424. struct iwl_priv *priv = dev_get_drvdata(d);
  2425. return sprintf(buf, "0x%04X\n", priv->active_rxon.flags);
  2426. }
  2427. static ssize_t store_flags(struct device *d,
  2428. struct device_attribute *attr,
  2429. const char *buf, size_t count)
  2430. {
  2431. struct iwl_priv *priv = dev_get_drvdata(d);
  2432. unsigned long val;
  2433. u32 flags;
  2434. int ret = strict_strtoul(buf, 0, &val);
  2435. if (ret)
  2436. return ret;
  2437. flags = (u32)val;
  2438. mutex_lock(&priv->mutex);
  2439. if (le32_to_cpu(priv->staging_rxon.flags) != flags) {
  2440. /* Cancel any currently running scans... */
  2441. if (iwl_scan_cancel_timeout(priv, 100))
  2442. IWL_WARN(priv, "Could not cancel scan.\n");
  2443. else {
  2444. IWL_DEBUG_INFO(priv, "Commit rxon.flags = 0x%04X\n", flags);
  2445. priv->staging_rxon.flags = cpu_to_le32(flags);
  2446. iwlcore_commit_rxon(priv);
  2447. }
  2448. }
  2449. mutex_unlock(&priv->mutex);
  2450. return count;
  2451. }
  2452. static DEVICE_ATTR(flags, S_IWUSR | S_IRUGO, show_flags, store_flags);
  2453. static ssize_t show_filter_flags(struct device *d,
  2454. struct device_attribute *attr, char *buf)
  2455. {
  2456. struct iwl_priv *priv = dev_get_drvdata(d);
  2457. return sprintf(buf, "0x%04X\n",
  2458. le32_to_cpu(priv->active_rxon.filter_flags));
  2459. }
  2460. static ssize_t store_filter_flags(struct device *d,
  2461. struct device_attribute *attr,
  2462. const char *buf, size_t count)
  2463. {
  2464. struct iwl_priv *priv = dev_get_drvdata(d);
  2465. unsigned long val;
  2466. u32 filter_flags;
  2467. int ret = strict_strtoul(buf, 0, &val);
  2468. if (ret)
  2469. return ret;
  2470. filter_flags = (u32)val;
  2471. mutex_lock(&priv->mutex);
  2472. if (le32_to_cpu(priv->staging_rxon.filter_flags) != filter_flags) {
  2473. /* Cancel any currently running scans... */
  2474. if (iwl_scan_cancel_timeout(priv, 100))
  2475. IWL_WARN(priv, "Could not cancel scan.\n");
  2476. else {
  2477. IWL_DEBUG_INFO(priv, "Committing rxon.filter_flags = "
  2478. "0x%04X\n", filter_flags);
  2479. priv->staging_rxon.filter_flags =
  2480. cpu_to_le32(filter_flags);
  2481. iwlcore_commit_rxon(priv);
  2482. }
  2483. }
  2484. mutex_unlock(&priv->mutex);
  2485. return count;
  2486. }
  2487. static DEVICE_ATTR(filter_flags, S_IWUSR | S_IRUGO, show_filter_flags,
  2488. store_filter_flags);
  2489. static ssize_t show_statistics(struct device *d,
  2490. struct device_attribute *attr, char *buf)
  2491. {
  2492. struct iwl_priv *priv = dev_get_drvdata(d);
  2493. u32 size = sizeof(struct iwl_notif_statistics);
  2494. u32 len = 0, ofs = 0;
  2495. u8 *data = (u8 *)&priv->statistics;
  2496. int rc = 0;
  2497. if (!iwl_is_alive(priv))
  2498. return -EAGAIN;
  2499. mutex_lock(&priv->mutex);
  2500. rc = iwl_send_statistics_request(priv, CMD_SYNC, false);
  2501. mutex_unlock(&priv->mutex);
  2502. if (rc) {
  2503. len = sprintf(buf,
  2504. "Error sending statistics request: 0x%08X\n", rc);
  2505. return len;
  2506. }
  2507. while (size && (PAGE_SIZE - len)) {
  2508. hex_dump_to_buffer(data + ofs, size, 16, 1, buf + len,
  2509. PAGE_SIZE - len, 1);
  2510. len = strlen(buf);
  2511. if (PAGE_SIZE - len)
  2512. buf[len++] = '\n';
  2513. ofs += 16;
  2514. size -= min(size, 16U);
  2515. }
  2516. return len;
  2517. }
  2518. static DEVICE_ATTR(statistics, S_IRUGO, show_statistics, NULL);
  2519. static ssize_t show_rts_ht_protection(struct device *d,
  2520. struct device_attribute *attr, char *buf)
  2521. {
  2522. struct iwl_priv *priv = dev_get_drvdata(d);
  2523. return sprintf(buf, "%s\n",
  2524. priv->cfg->use_rts_for_ht ? "RTS/CTS" : "CTS-to-self");
  2525. }
  2526. static ssize_t store_rts_ht_protection(struct device *d,
  2527. struct device_attribute *attr,
  2528. const char *buf, size_t count)
  2529. {
  2530. struct iwl_priv *priv = dev_get_drvdata(d);
  2531. unsigned long val;
  2532. int ret;
  2533. ret = strict_strtoul(buf, 10, &val);
  2534. if (ret)
  2535. IWL_INFO(priv, "Input is not in decimal form.\n");
  2536. else {
  2537. if (!iwl_is_associated(priv))
  2538. priv->cfg->use_rts_for_ht = val ? true : false;
  2539. else
  2540. IWL_ERR(priv, "Sta associated with AP - "
  2541. "Change protection mechanism is not allowed\n");
  2542. ret = count;
  2543. }
  2544. return ret;
  2545. }
  2546. static DEVICE_ATTR(rts_ht_protection, S_IWUSR | S_IRUGO,
  2547. show_rts_ht_protection, store_rts_ht_protection);
  2548. /*****************************************************************************
  2549. *
  2550. * driver setup and teardown
  2551. *
  2552. *****************************************************************************/
  2553. static void iwl_setup_deferred_work(struct iwl_priv *priv)
  2554. {
  2555. priv->workqueue = create_singlethread_workqueue(DRV_NAME);
  2556. init_waitqueue_head(&priv->wait_command_queue);
  2557. INIT_WORK(&priv->up, iwl_bg_up);
  2558. INIT_WORK(&priv->restart, iwl_bg_restart);
  2559. INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
  2560. INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
  2561. INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
  2562. INIT_DELAYED_WORK(&priv->init_alive_start, iwl_bg_init_alive_start);
  2563. INIT_DELAYED_WORK(&priv->alive_start, iwl_bg_alive_start);
  2564. iwl_setup_scan_deferred_work(priv);
  2565. if (priv->cfg->ops->lib->setup_deferred_work)
  2566. priv->cfg->ops->lib->setup_deferred_work(priv);
  2567. init_timer(&priv->statistics_periodic);
  2568. priv->statistics_periodic.data = (unsigned long)priv;
  2569. priv->statistics_periodic.function = iwl_bg_statistics_periodic;
  2570. if (!priv->cfg->use_isr_legacy)
  2571. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  2572. iwl_irq_tasklet, (unsigned long)priv);
  2573. else
  2574. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  2575. iwl_irq_tasklet_legacy, (unsigned long)priv);
  2576. }
  2577. static void iwl_cancel_deferred_work(struct iwl_priv *priv)
  2578. {
  2579. if (priv->cfg->ops->lib->cancel_deferred_work)
  2580. priv->cfg->ops->lib->cancel_deferred_work(priv);
  2581. cancel_delayed_work_sync(&priv->init_alive_start);
  2582. cancel_delayed_work(&priv->scan_check);
  2583. cancel_delayed_work(&priv->alive_start);
  2584. cancel_work_sync(&priv->beacon_update);
  2585. del_timer_sync(&priv->statistics_periodic);
  2586. }
  2587. static void iwl_init_hw_rates(struct iwl_priv *priv,
  2588. struct ieee80211_rate *rates)
  2589. {
  2590. int i;
  2591. for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
  2592. rates[i].bitrate = iwl_rates[i].ieee * 5;
  2593. rates[i].hw_value = i; /* Rate scaling will work on indexes */
  2594. rates[i].hw_value_short = i;
  2595. rates[i].flags = 0;
  2596. if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
  2597. /*
  2598. * If CCK != 1M then set short preamble rate flag.
  2599. */
  2600. rates[i].flags |=
  2601. (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
  2602. 0 : IEEE80211_RATE_SHORT_PREAMBLE;
  2603. }
  2604. }
  2605. }
  2606. static int iwl_init_drv(struct iwl_priv *priv)
  2607. {
  2608. int ret;
  2609. priv->ibss_beacon = NULL;
  2610. spin_lock_init(&priv->sta_lock);
  2611. spin_lock_init(&priv->hcmd_lock);
  2612. INIT_LIST_HEAD(&priv->free_frames);
  2613. mutex_init(&priv->mutex);
  2614. /* Clear the driver's (not device's) station table */
  2615. iwl_clear_stations_table(priv);
  2616. priv->ieee_channels = NULL;
  2617. priv->ieee_rates = NULL;
  2618. priv->band = IEEE80211_BAND_2GHZ;
  2619. priv->iw_mode = NL80211_IFTYPE_STATION;
  2620. /* Choose which receivers/antennas to use */
  2621. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2622. priv->cfg->ops->hcmd->set_rxon_chain(priv);
  2623. iwl_init_scan_params(priv);
  2624. iwl_reset_qos(priv);
  2625. priv->qos_data.qos_active = 0;
  2626. priv->qos_data.qos_cap.val = 0;
  2627. priv->rates_mask = IWL_RATES_MASK;
  2628. /* Set the tx_power_user_lmt to the lowest power level
  2629. * this value will get overwritten by channel max power avg
  2630. * from eeprom */
  2631. priv->tx_power_user_lmt = IWL_TX_POWER_TARGET_POWER_MIN;
  2632. ret = iwl_init_channel_map(priv);
  2633. if (ret) {
  2634. IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
  2635. goto err;
  2636. }
  2637. ret = iwlcore_init_geos(priv);
  2638. if (ret) {
  2639. IWL_ERR(priv, "initializing geos failed: %d\n", ret);
  2640. goto err_free_channel_map;
  2641. }
  2642. iwl_init_hw_rates(priv, priv->ieee_rates);
  2643. return 0;
  2644. err_free_channel_map:
  2645. iwl_free_channel_map(priv);
  2646. err:
  2647. return ret;
  2648. }
  2649. static void iwl_uninit_drv(struct iwl_priv *priv)
  2650. {
  2651. iwl_calib_free_results(priv);
  2652. iwlcore_free_geos(priv);
  2653. iwl_free_channel_map(priv);
  2654. kfree(priv->scan);
  2655. }
  2656. static struct attribute *iwl_sysfs_entries[] = {
  2657. &dev_attr_flags.attr,
  2658. &dev_attr_filter_flags.attr,
  2659. &dev_attr_statistics.attr,
  2660. &dev_attr_temperature.attr,
  2661. &dev_attr_tx_power.attr,
  2662. &dev_attr_rts_ht_protection.attr,
  2663. #ifdef CONFIG_IWLWIFI_DEBUG
  2664. &dev_attr_debug_level.attr,
  2665. #endif
  2666. NULL
  2667. };
  2668. static struct attribute_group iwl_attribute_group = {
  2669. .name = NULL, /* put in device directory */
  2670. .attrs = iwl_sysfs_entries,
  2671. };
  2672. static struct ieee80211_ops iwl_hw_ops = {
  2673. .tx = iwl_mac_tx,
  2674. .start = iwl_mac_start,
  2675. .stop = iwl_mac_stop,
  2676. .add_interface = iwl_mac_add_interface,
  2677. .remove_interface = iwl_mac_remove_interface,
  2678. .config = iwl_mac_config,
  2679. .configure_filter = iwl_configure_filter,
  2680. .set_key = iwl_mac_set_key,
  2681. .update_tkip_key = iwl_mac_update_tkip_key,
  2682. .get_stats = iwl_mac_get_stats,
  2683. .get_tx_stats = iwl_mac_get_tx_stats,
  2684. .conf_tx = iwl_mac_conf_tx,
  2685. .reset_tsf = iwl_mac_reset_tsf,
  2686. .bss_info_changed = iwl_bss_info_changed,
  2687. .ampdu_action = iwl_mac_ampdu_action,
  2688. .hw_scan = iwl_mac_hw_scan,
  2689. .sta_notify = iwl_mac_sta_notify,
  2690. };
  2691. static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  2692. {
  2693. int err = 0;
  2694. struct iwl_priv *priv;
  2695. struct ieee80211_hw *hw;
  2696. struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
  2697. unsigned long flags;
  2698. u16 pci_cmd;
  2699. /************************
  2700. * 1. Allocating HW data
  2701. ************************/
  2702. /* Disabling hardware scan means that mac80211 will perform scans
  2703. * "the hard way", rather than using device's scan. */
  2704. if (cfg->mod_params->disable_hw_scan) {
  2705. if (iwl_debug_level & IWL_DL_INFO)
  2706. dev_printk(KERN_DEBUG, &(pdev->dev),
  2707. "Disabling hw_scan\n");
  2708. iwl_hw_ops.hw_scan = NULL;
  2709. }
  2710. hw = iwl_alloc_all(cfg, &iwl_hw_ops);
  2711. if (!hw) {
  2712. err = -ENOMEM;
  2713. goto out;
  2714. }
  2715. priv = hw->priv;
  2716. /* At this point both hw and priv are allocated. */
  2717. SET_IEEE80211_DEV(hw, &pdev->dev);
  2718. IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
  2719. priv->cfg = cfg;
  2720. priv->pci_dev = pdev;
  2721. priv->inta_mask = CSR_INI_SET_MASK;
  2722. #ifdef CONFIG_IWLWIFI_DEBUG
  2723. atomic_set(&priv->restrict_refcnt, 0);
  2724. #endif
  2725. if (iwl_alloc_traffic_mem(priv))
  2726. IWL_ERR(priv, "Not enough memory to generate traffic log\n");
  2727. /**************************
  2728. * 2. Initializing PCI bus
  2729. **************************/
  2730. if (pci_enable_device(pdev)) {
  2731. err = -ENODEV;
  2732. goto out_ieee80211_free_hw;
  2733. }
  2734. pci_set_master(pdev);
  2735. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
  2736. if (!err)
  2737. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
  2738. if (err) {
  2739. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  2740. if (!err)
  2741. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
  2742. /* both attempts failed: */
  2743. if (err) {
  2744. IWL_WARN(priv, "No suitable DMA available.\n");
  2745. goto out_pci_disable_device;
  2746. }
  2747. }
  2748. err = pci_request_regions(pdev, DRV_NAME);
  2749. if (err)
  2750. goto out_pci_disable_device;
  2751. pci_set_drvdata(pdev, priv);
  2752. /***********************
  2753. * 3. Read REV register
  2754. ***********************/
  2755. priv->hw_base = pci_iomap(pdev, 0, 0);
  2756. if (!priv->hw_base) {
  2757. err = -ENODEV;
  2758. goto out_pci_release_regions;
  2759. }
  2760. IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
  2761. (unsigned long long) pci_resource_len(pdev, 0));
  2762. IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
  2763. /* these spin locks will be used in apm_ops.init and EEPROM access
  2764. * we should init now
  2765. */
  2766. spin_lock_init(&priv->reg_lock);
  2767. spin_lock_init(&priv->lock);
  2768. iwl_hw_detect(priv);
  2769. IWL_INFO(priv, "Detected Intel Wireless WiFi Link %s REV=0x%X\n",
  2770. priv->cfg->name, priv->hw_rev);
  2771. /* We disable the RETRY_TIMEOUT register (0x41) to keep
  2772. * PCI Tx retries from interfering with C3 CPU state */
  2773. pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
  2774. iwl_prepare_card_hw(priv);
  2775. if (!priv->hw_ready) {
  2776. IWL_WARN(priv, "Failed, HW not ready\n");
  2777. goto out_iounmap;
  2778. }
  2779. /*****************
  2780. * 4. Read EEPROM
  2781. *****************/
  2782. /* Read the EEPROM */
  2783. err = iwl_eeprom_init(priv);
  2784. if (err) {
  2785. IWL_ERR(priv, "Unable to init EEPROM\n");
  2786. goto out_iounmap;
  2787. }
  2788. err = iwl_eeprom_check_version(priv);
  2789. if (err)
  2790. goto out_free_eeprom;
  2791. /* extract MAC Address */
  2792. iwl_eeprom_get_mac(priv, priv->mac_addr);
  2793. IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->mac_addr);
  2794. SET_IEEE80211_PERM_ADDR(priv->hw, priv->mac_addr);
  2795. /************************
  2796. * 5. Setup HW constants
  2797. ************************/
  2798. if (iwl_set_hw_params(priv)) {
  2799. IWL_ERR(priv, "failed to set hw parameters\n");
  2800. goto out_free_eeprom;
  2801. }
  2802. /*******************
  2803. * 6. Setup priv
  2804. *******************/
  2805. err = iwl_init_drv(priv);
  2806. if (err)
  2807. goto out_free_eeprom;
  2808. /* At this point both hw and priv are initialized. */
  2809. /********************
  2810. * 7. Setup services
  2811. ********************/
  2812. spin_lock_irqsave(&priv->lock, flags);
  2813. iwl_disable_interrupts(priv);
  2814. spin_unlock_irqrestore(&priv->lock, flags);
  2815. pci_enable_msi(priv->pci_dev);
  2816. iwl_alloc_isr_ict(priv);
  2817. err = request_irq(priv->pci_dev->irq, priv->cfg->ops->lib->isr,
  2818. IRQF_SHARED, DRV_NAME, priv);
  2819. if (err) {
  2820. IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
  2821. goto out_disable_msi;
  2822. }
  2823. err = sysfs_create_group(&pdev->dev.kobj, &iwl_attribute_group);
  2824. if (err) {
  2825. IWL_ERR(priv, "failed to create sysfs device attributes\n");
  2826. goto out_free_irq;
  2827. }
  2828. iwl_setup_deferred_work(priv);
  2829. iwl_setup_rx_handlers(priv);
  2830. /**********************************
  2831. * 8. Setup and register mac80211
  2832. **********************************/
  2833. /* enable interrupts if needed: hw bug w/a */
  2834. pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
  2835. if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
  2836. pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
  2837. pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
  2838. }
  2839. iwl_enable_interrupts(priv);
  2840. err = iwl_setup_mac(priv);
  2841. if (err)
  2842. goto out_remove_sysfs;
  2843. err = iwl_dbgfs_register(priv, DRV_NAME);
  2844. if (err)
  2845. IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
  2846. /* If platform's RF_KILL switch is NOT set to KILL */
  2847. if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  2848. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  2849. else
  2850. set_bit(STATUS_RF_KILL_HW, &priv->status);
  2851. wiphy_rfkill_set_hw_state(priv->hw->wiphy,
  2852. test_bit(STATUS_RF_KILL_HW, &priv->status));
  2853. iwl_power_initialize(priv);
  2854. iwl_tt_initialize(priv);
  2855. return 0;
  2856. out_remove_sysfs:
  2857. destroy_workqueue(priv->workqueue);
  2858. priv->workqueue = NULL;
  2859. sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
  2860. out_free_irq:
  2861. free_irq(priv->pci_dev->irq, priv);
  2862. iwl_free_isr_ict(priv);
  2863. out_disable_msi:
  2864. pci_disable_msi(priv->pci_dev);
  2865. iwl_uninit_drv(priv);
  2866. out_free_eeprom:
  2867. iwl_eeprom_free(priv);
  2868. out_iounmap:
  2869. pci_iounmap(pdev, priv->hw_base);
  2870. out_pci_release_regions:
  2871. pci_set_drvdata(pdev, NULL);
  2872. pci_release_regions(pdev);
  2873. out_pci_disable_device:
  2874. pci_disable_device(pdev);
  2875. out_ieee80211_free_hw:
  2876. iwl_free_traffic_mem(priv);
  2877. ieee80211_free_hw(priv->hw);
  2878. out:
  2879. return err;
  2880. }
  2881. static void __devexit iwl_pci_remove(struct pci_dev *pdev)
  2882. {
  2883. struct iwl_priv *priv = pci_get_drvdata(pdev);
  2884. unsigned long flags;
  2885. if (!priv)
  2886. return;
  2887. IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
  2888. iwl_dbgfs_unregister(priv);
  2889. sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
  2890. /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
  2891. * to be called and iwl_down since we are removing the device
  2892. * we need to set STATUS_EXIT_PENDING bit.
  2893. */
  2894. set_bit(STATUS_EXIT_PENDING, &priv->status);
  2895. if (priv->mac80211_registered) {
  2896. ieee80211_unregister_hw(priv->hw);
  2897. priv->mac80211_registered = 0;
  2898. } else {
  2899. iwl_down(priv);
  2900. }
  2901. /*
  2902. * Make sure device is reset to low power before unloading driver.
  2903. * This may be redundant with iwl_down(), but there are paths to
  2904. * run iwl_down() without calling apm_ops.stop(), and there are
  2905. * paths to avoid running iwl_down() at all before leaving driver.
  2906. * This (inexpensive) call *makes sure* device is reset.
  2907. */
  2908. priv->cfg->ops->lib->apm_ops.stop(priv);
  2909. iwl_tt_exit(priv);
  2910. /* make sure we flush any pending irq or
  2911. * tasklet for the driver
  2912. */
  2913. spin_lock_irqsave(&priv->lock, flags);
  2914. iwl_disable_interrupts(priv);
  2915. spin_unlock_irqrestore(&priv->lock, flags);
  2916. iwl_synchronize_irq(priv);
  2917. iwl_dealloc_ucode_pci(priv);
  2918. if (priv->rxq.bd)
  2919. iwl_rx_queue_free(priv, &priv->rxq);
  2920. iwl_hw_txq_ctx_free(priv);
  2921. iwl_clear_stations_table(priv);
  2922. iwl_eeprom_free(priv);
  2923. /*netif_stop_queue(dev); */
  2924. flush_workqueue(priv->workqueue);
  2925. /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
  2926. * priv->workqueue... so we can't take down the workqueue
  2927. * until now... */
  2928. destroy_workqueue(priv->workqueue);
  2929. priv->workqueue = NULL;
  2930. iwl_free_traffic_mem(priv);
  2931. free_irq(priv->pci_dev->irq, priv);
  2932. pci_disable_msi(priv->pci_dev);
  2933. pci_iounmap(pdev, priv->hw_base);
  2934. pci_release_regions(pdev);
  2935. pci_disable_device(pdev);
  2936. pci_set_drvdata(pdev, NULL);
  2937. iwl_uninit_drv(priv);
  2938. iwl_free_isr_ict(priv);
  2939. if (priv->ibss_beacon)
  2940. dev_kfree_skb(priv->ibss_beacon);
  2941. ieee80211_free_hw(priv->hw);
  2942. }
  2943. /*****************************************************************************
  2944. *
  2945. * driver and module entry point
  2946. *
  2947. *****************************************************************************/
  2948. /* Hardware specific file defines the PCI IDs table for that hardware module */
  2949. static struct pci_device_id iwl_hw_card_ids[] = {
  2950. #ifdef CONFIG_IWL4965
  2951. {IWL_PCI_DEVICE(0x4229, PCI_ANY_ID, iwl4965_agn_cfg)},
  2952. {IWL_PCI_DEVICE(0x4230, PCI_ANY_ID, iwl4965_agn_cfg)},
  2953. #endif /* CONFIG_IWL4965 */
  2954. #ifdef CONFIG_IWL5000
  2955. /* 5100 Series WiFi */
  2956. {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
  2957. {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
  2958. {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
  2959. {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
  2960. {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
  2961. {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
  2962. {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
  2963. {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
  2964. {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
  2965. {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
  2966. {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
  2967. {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
  2968. {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
  2969. {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
  2970. {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
  2971. {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
  2972. {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
  2973. {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
  2974. {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
  2975. {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
  2976. {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
  2977. {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
  2978. {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
  2979. {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
  2980. /* 5300 Series WiFi */
  2981. {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
  2982. {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
  2983. {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
  2984. {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
  2985. {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
  2986. {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
  2987. {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
  2988. {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
  2989. {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
  2990. {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
  2991. {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
  2992. {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
  2993. /* 5350 Series WiFi/WiMax */
  2994. {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
  2995. {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
  2996. {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
  2997. /* 5150 Series Wifi/WiMax */
  2998. {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
  2999. {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
  3000. {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
  3001. {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
  3002. {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
  3003. {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
  3004. {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
  3005. {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
  3006. {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
  3007. {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
  3008. /* 6x00 Series */
  3009. {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
  3010. {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
  3011. {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
  3012. {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
  3013. {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
  3014. {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
  3015. {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
  3016. {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
  3017. {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
  3018. {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
  3019. /* 6x50 WiFi/WiMax Series */
  3020. {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
  3021. {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
  3022. {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
  3023. {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
  3024. {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
  3025. {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
  3026. /* 1000 Series WiFi */
  3027. {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
  3028. {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
  3029. {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
  3030. {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
  3031. {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
  3032. {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
  3033. {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
  3034. {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
  3035. {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
  3036. {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
  3037. {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
  3038. {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
  3039. #endif /* CONFIG_IWL5000 */
  3040. {0}
  3041. };
  3042. MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
  3043. static struct pci_driver iwl_driver = {
  3044. .name = DRV_NAME,
  3045. .id_table = iwl_hw_card_ids,
  3046. .probe = iwl_pci_probe,
  3047. .remove = __devexit_p(iwl_pci_remove),
  3048. #ifdef CONFIG_PM
  3049. .suspend = iwl_pci_suspend,
  3050. .resume = iwl_pci_resume,
  3051. #endif
  3052. };
  3053. static int __init iwl_init(void)
  3054. {
  3055. int ret;
  3056. printk(KERN_INFO DRV_NAME ": " DRV_DESCRIPTION ", " DRV_VERSION "\n");
  3057. printk(KERN_INFO DRV_NAME ": " DRV_COPYRIGHT "\n");
  3058. ret = iwlagn_rate_control_register();
  3059. if (ret) {
  3060. printk(KERN_ERR DRV_NAME
  3061. "Unable to register rate control algorithm: %d\n", ret);
  3062. return ret;
  3063. }
  3064. ret = pci_register_driver(&iwl_driver);
  3065. if (ret) {
  3066. printk(KERN_ERR DRV_NAME "Unable to initialize PCI module\n");
  3067. goto error_register;
  3068. }
  3069. return ret;
  3070. error_register:
  3071. iwlagn_rate_control_unregister();
  3072. return ret;
  3073. }
  3074. static void __exit iwl_exit(void)
  3075. {
  3076. pci_unregister_driver(&iwl_driver);
  3077. iwlagn_rate_control_unregister();
  3078. }
  3079. module_exit(iwl_exit);
  3080. module_init(iwl_init);
  3081. #ifdef CONFIG_IWLWIFI_DEBUG
  3082. module_param_named(debug50, iwl_debug_level, uint, S_IRUGO);
  3083. MODULE_PARM_DESC(debug50, "50XX debug output mask (deprecated)");
  3084. module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
  3085. MODULE_PARM_DESC(debug, "debug output mask");
  3086. #endif