r820t.c 54 KB

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  1. /*
  2. * Rafael Micro R820T driver
  3. *
  4. * Copyright (C) 2013 Mauro Carvalho Chehab <mchehab@redhat.com>
  5. *
  6. * This driver was written from scratch, based on an existing driver
  7. * that it is part of rtl-sdr git tree, released under GPLv2:
  8. * https://groups.google.com/forum/#!topic/ultra-cheap-sdr/Y3rBEOFtHug
  9. * https://github.com/n1gp/gr-baz
  10. *
  11. * From what I understood from the threads, the original driver was converted
  12. * to userspace from a Realtek tree. I couldn't find the original tree.
  13. * However, the original driver look awkward on my eyes. So, I decided to
  14. * write a new version from it from the scratch, while trying to reproduce
  15. * everything found there.
  16. *
  17. * TODO:
  18. * After locking, the original driver seems to have some routines to
  19. * improve reception. This was not implemented here yet.
  20. *
  21. * RF Gain set/get is not implemented.
  22. *
  23. * This program is free software; you can redistribute it and/or modify
  24. * it under the terms of the GNU General Public License as published by
  25. * the Free Software Foundation; either version 2 of the License, or
  26. * (at your option) any later version.
  27. *
  28. * This program is distributed in the hope that it will be useful,
  29. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  30. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  31. * GNU General Public License for more details.
  32. *
  33. */
  34. #include <linux/videodev2.h>
  35. #include <linux/mutex.h>
  36. #include <linux/slab.h>
  37. #include <linux/bitrev.h>
  38. #include "tuner-i2c.h"
  39. #include "r820t.h"
  40. /*
  41. * FIXME: I think that there are only 32 registers, but better safe than
  42. * sorry. After finishing the driver, we may review it.
  43. */
  44. #define REG_SHADOW_START 5
  45. #define NUM_REGS 27
  46. #define NUM_IMR 5
  47. #define IMR_TRIAL 9
  48. #define VER_NUM 49
  49. static int debug;
  50. module_param(debug, int, 0644);
  51. MODULE_PARM_DESC(debug, "enable verbose debug messages");
  52. static int no_imr_cal;
  53. module_param(no_imr_cal, int, 0444);
  54. MODULE_PARM_DESC(no_imr_cal, "Disable IMR calibration at module init");
  55. /*
  56. * enums and structures
  57. */
  58. enum xtal_cap_value {
  59. XTAL_LOW_CAP_30P = 0,
  60. XTAL_LOW_CAP_20P,
  61. XTAL_LOW_CAP_10P,
  62. XTAL_LOW_CAP_0P,
  63. XTAL_HIGH_CAP_0P
  64. };
  65. struct r820t_sect_type {
  66. u8 phase_y;
  67. u8 gain_x;
  68. u16 value;
  69. };
  70. struct r820t_priv {
  71. struct list_head hybrid_tuner_instance_list;
  72. const struct r820t_config *cfg;
  73. struct tuner_i2c_props i2c_props;
  74. struct mutex lock;
  75. u8 regs[NUM_REGS];
  76. u8 buf[NUM_REGS + 1];
  77. enum xtal_cap_value xtal_cap_sel;
  78. u16 pll; /* kHz */
  79. u32 int_freq;
  80. u8 fil_cal_code;
  81. bool imr_done;
  82. bool has_lock;
  83. bool init_done;
  84. struct r820t_sect_type imr_data[NUM_IMR];
  85. /* Store current mode */
  86. u32 delsys;
  87. enum v4l2_tuner_type type;
  88. v4l2_std_id std;
  89. u32 bw; /* in MHz */
  90. };
  91. struct r820t_freq_range {
  92. u32 freq;
  93. u8 open_d;
  94. u8 rf_mux_ploy;
  95. u8 tf_c;
  96. u8 xtal_cap20p;
  97. u8 xtal_cap10p;
  98. u8 xtal_cap0p;
  99. u8 imr_mem; /* Not used, currently */
  100. };
  101. #define VCO_POWER_REF 0x02
  102. #define DIP_FREQ 32000000
  103. /*
  104. * Static constants
  105. */
  106. static LIST_HEAD(hybrid_tuner_instance_list);
  107. static DEFINE_MUTEX(r820t_list_mutex);
  108. /* Those initial values start from REG_SHADOW_START */
  109. static const u8 r820t_init_array[NUM_REGS] = {
  110. 0x83, 0x32, 0x75, /* 05 to 07 */
  111. 0xc0, 0x40, 0xd6, 0x6c, /* 08 to 0b */
  112. 0xf5, 0x63, 0x75, 0x68, /* 0c to 0f */
  113. 0x6c, 0x83, 0x80, 0x00, /* 10 to 13 */
  114. 0x0f, 0x00, 0xc0, 0x30, /* 14 to 17 */
  115. 0x48, 0xcc, 0x60, 0x00, /* 18 to 1b */
  116. 0x54, 0xae, 0x4a, 0xc0 /* 1c to 1f */
  117. };
  118. /* Tuner frequency ranges */
  119. static const struct r820t_freq_range freq_ranges[] = {
  120. {
  121. .freq = 0,
  122. .open_d = 0x08, /* low */
  123. .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
  124. .tf_c = 0xdf, /* R27[7:0] band2,band0 */
  125. .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */
  126. .xtal_cap10p = 0x01,
  127. .xtal_cap0p = 0x00,
  128. .imr_mem = 0,
  129. }, {
  130. .freq = 50, /* Start freq, in MHz */
  131. .open_d = 0x08, /* low */
  132. .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
  133. .tf_c = 0xbe, /* R27[7:0] band4,band1 */
  134. .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */
  135. .xtal_cap10p = 0x01,
  136. .xtal_cap0p = 0x00,
  137. .imr_mem = 0,
  138. }, {
  139. .freq = 55, /* Start freq, in MHz */
  140. .open_d = 0x08, /* low */
  141. .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
  142. .tf_c = 0x8b, /* R27[7:0] band7,band4 */
  143. .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */
  144. .xtal_cap10p = 0x01,
  145. .xtal_cap0p = 0x00,
  146. .imr_mem = 0,
  147. }, {
  148. .freq = 60, /* Start freq, in MHz */
  149. .open_d = 0x08, /* low */
  150. .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
  151. .tf_c = 0x7b, /* R27[7:0] band8,band4 */
  152. .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */
  153. .xtal_cap10p = 0x01,
  154. .xtal_cap0p = 0x00,
  155. .imr_mem = 0,
  156. }, {
  157. .freq = 65, /* Start freq, in MHz */
  158. .open_d = 0x08, /* low */
  159. .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
  160. .tf_c = 0x69, /* R27[7:0] band9,band6 */
  161. .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */
  162. .xtal_cap10p = 0x01,
  163. .xtal_cap0p = 0x00,
  164. .imr_mem = 0,
  165. }, {
  166. .freq = 70, /* Start freq, in MHz */
  167. .open_d = 0x08, /* low */
  168. .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
  169. .tf_c = 0x58, /* R27[7:0] band10,band7 */
  170. .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */
  171. .xtal_cap10p = 0x01,
  172. .xtal_cap0p = 0x00,
  173. .imr_mem = 0,
  174. }, {
  175. .freq = 75, /* Start freq, in MHz */
  176. .open_d = 0x00, /* high */
  177. .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
  178. .tf_c = 0x44, /* R27[7:0] band11,band11 */
  179. .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */
  180. .xtal_cap10p = 0x01,
  181. .xtal_cap0p = 0x00,
  182. .imr_mem = 0,
  183. }, {
  184. .freq = 80, /* Start freq, in MHz */
  185. .open_d = 0x00, /* high */
  186. .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
  187. .tf_c = 0x44, /* R27[7:0] band11,band11 */
  188. .xtal_cap20p = 0x02, /* R16[1:0] 20pF (10) */
  189. .xtal_cap10p = 0x01,
  190. .xtal_cap0p = 0x00,
  191. .imr_mem = 0,
  192. }, {
  193. .freq = 90, /* Start freq, in MHz */
  194. .open_d = 0x00, /* high */
  195. .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
  196. .tf_c = 0x34, /* R27[7:0] band12,band11 */
  197. .xtal_cap20p = 0x01, /* R16[1:0] 10pF (01) */
  198. .xtal_cap10p = 0x01,
  199. .xtal_cap0p = 0x00,
  200. .imr_mem = 0,
  201. }, {
  202. .freq = 100, /* Start freq, in MHz */
  203. .open_d = 0x00, /* high */
  204. .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
  205. .tf_c = 0x34, /* R27[7:0] band12,band11 */
  206. .xtal_cap20p = 0x01, /* R16[1:0] 10pF (01) */
  207. .xtal_cap10p = 0x01,
  208. .xtal_cap0p = 0x00,
  209. .imr_mem = 0,
  210. }, {
  211. .freq = 110, /* Start freq, in MHz */
  212. .open_d = 0x00, /* high */
  213. .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
  214. .tf_c = 0x24, /* R27[7:0] band13,band11 */
  215. .xtal_cap20p = 0x01, /* R16[1:0] 10pF (01) */
  216. .xtal_cap10p = 0x01,
  217. .xtal_cap0p = 0x00,
  218. .imr_mem = 1,
  219. }, {
  220. .freq = 120, /* Start freq, in MHz */
  221. .open_d = 0x00, /* high */
  222. .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
  223. .tf_c = 0x24, /* R27[7:0] band13,band11 */
  224. .xtal_cap20p = 0x01, /* R16[1:0] 10pF (01) */
  225. .xtal_cap10p = 0x01,
  226. .xtal_cap0p = 0x00,
  227. .imr_mem = 1,
  228. }, {
  229. .freq = 140, /* Start freq, in MHz */
  230. .open_d = 0x00, /* high */
  231. .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
  232. .tf_c = 0x14, /* R27[7:0] band14,band11 */
  233. .xtal_cap20p = 0x01, /* R16[1:0] 10pF (01) */
  234. .xtal_cap10p = 0x01,
  235. .xtal_cap0p = 0x00,
  236. .imr_mem = 1,
  237. }, {
  238. .freq = 180, /* Start freq, in MHz */
  239. .open_d = 0x00, /* high */
  240. .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
  241. .tf_c = 0x13, /* R27[7:0] band14,band12 */
  242. .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */
  243. .xtal_cap10p = 0x00,
  244. .xtal_cap0p = 0x00,
  245. .imr_mem = 1,
  246. }, {
  247. .freq = 220, /* Start freq, in MHz */
  248. .open_d = 0x00, /* high */
  249. .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
  250. .tf_c = 0x13, /* R27[7:0] band14,band12 */
  251. .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */
  252. .xtal_cap10p = 0x00,
  253. .xtal_cap0p = 0x00,
  254. .imr_mem = 2,
  255. }, {
  256. .freq = 250, /* Start freq, in MHz */
  257. .open_d = 0x00, /* high */
  258. .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
  259. .tf_c = 0x11, /* R27[7:0] highest,highest */
  260. .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */
  261. .xtal_cap10p = 0x00,
  262. .xtal_cap0p = 0x00,
  263. .imr_mem = 2,
  264. }, {
  265. .freq = 280, /* Start freq, in MHz */
  266. .open_d = 0x00, /* high */
  267. .rf_mux_ploy = 0x02, /* R26[7:6]=0 (LPF) R26[1:0]=2 (low) */
  268. .tf_c = 0x00, /* R27[7:0] highest,highest */
  269. .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */
  270. .xtal_cap10p = 0x00,
  271. .xtal_cap0p = 0x00,
  272. .imr_mem = 2,
  273. }, {
  274. .freq = 310, /* Start freq, in MHz */
  275. .open_d = 0x00, /* high */
  276. .rf_mux_ploy = 0x41, /* R26[7:6]=1 (bypass) R26[1:0]=1 (middle) */
  277. .tf_c = 0x00, /* R27[7:0] highest,highest */
  278. .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */
  279. .xtal_cap10p = 0x00,
  280. .xtal_cap0p = 0x00,
  281. .imr_mem = 2,
  282. }, {
  283. .freq = 450, /* Start freq, in MHz */
  284. .open_d = 0x00, /* high */
  285. .rf_mux_ploy = 0x41, /* R26[7:6]=1 (bypass) R26[1:0]=1 (middle) */
  286. .tf_c = 0x00, /* R27[7:0] highest,highest */
  287. .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */
  288. .xtal_cap10p = 0x00,
  289. .xtal_cap0p = 0x00,
  290. .imr_mem = 3,
  291. }, {
  292. .freq = 588, /* Start freq, in MHz */
  293. .open_d = 0x00, /* high */
  294. .rf_mux_ploy = 0x40, /* R26[7:6]=1 (bypass) R26[1:0]=0 (highest) */
  295. .tf_c = 0x00, /* R27[7:0] highest,highest */
  296. .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */
  297. .xtal_cap10p = 0x00,
  298. .xtal_cap0p = 0x00,
  299. .imr_mem = 3,
  300. }, {
  301. .freq = 650, /* Start freq, in MHz */
  302. .open_d = 0x00, /* high */
  303. .rf_mux_ploy = 0x40, /* R26[7:6]=1 (bypass) R26[1:0]=0 (highest) */
  304. .tf_c = 0x00, /* R27[7:0] highest,highest */
  305. .xtal_cap20p = 0x00, /* R16[1:0] 0pF (00) */
  306. .xtal_cap10p = 0x00,
  307. .xtal_cap0p = 0x00,
  308. .imr_mem = 4,
  309. }
  310. };
  311. static int r820t_xtal_capacitor[][2] = {
  312. { 0x0b, XTAL_LOW_CAP_30P },
  313. { 0x02, XTAL_LOW_CAP_20P },
  314. { 0x01, XTAL_LOW_CAP_10P },
  315. { 0x00, XTAL_LOW_CAP_0P },
  316. { 0x10, XTAL_HIGH_CAP_0P },
  317. };
  318. /*
  319. * measured with a Racal 6103E GSM test set at 928 MHz with -60 dBm
  320. * input power, for raw results see:
  321. * http://steve-m.de/projects/rtl-sdr/gain_measurement/r820t/
  322. */
  323. static const int r820t_lna_gain_steps[] = {
  324. 0, 9, 13, 40, 38, 13, 31, 22, 26, 31, 26, 14, 19, 5, 35, 13
  325. };
  326. static const int r820t_mixer_gain_steps[] = {
  327. 0, 5, 10, 10, 19, 9, 10, 25, 17, 10, 8, 16, 13, 6, 3, -8
  328. };
  329. /*
  330. * I2C read/write code and shadow registers logic
  331. */
  332. static void shadow_store(struct r820t_priv *priv, u8 reg, const u8 *val,
  333. int len)
  334. {
  335. int r = reg - REG_SHADOW_START;
  336. if (r < 0) {
  337. len += r;
  338. r = 0;
  339. }
  340. if (len <= 0)
  341. return;
  342. if (len > NUM_REGS - r)
  343. len = NUM_REGS - r;
  344. tuner_dbg("%s: prev reg=%02x len=%d: %*ph\n",
  345. __func__, r + REG_SHADOW_START, len, len, val);
  346. memcpy(&priv->regs[r], val, len);
  347. }
  348. static int r820t_write(struct r820t_priv *priv, u8 reg, const u8 *val,
  349. int len)
  350. {
  351. int rc, size, pos = 0;
  352. /* Store the shadow registers */
  353. shadow_store(priv, reg, val, len);
  354. do {
  355. if (len > priv->cfg->max_i2c_msg_len - 1)
  356. size = priv->cfg->max_i2c_msg_len - 1;
  357. else
  358. size = len;
  359. /* Fill I2C buffer */
  360. priv->buf[0] = reg;
  361. memcpy(&priv->buf[1], &val[pos], size);
  362. rc = tuner_i2c_xfer_send(&priv->i2c_props, priv->buf, size + 1);
  363. if (rc != size + 1) {
  364. tuner_info("%s: i2c wr failed=%d reg=%02x len=%d: %*ph\n",
  365. __func__, rc, reg, size, size, &priv->buf[1]);
  366. if (rc < 0)
  367. return rc;
  368. return -EREMOTEIO;
  369. }
  370. tuner_dbg("%s: i2c wr reg=%02x len=%d: %*ph\n",
  371. __func__, reg, size, size, &priv->buf[1]);
  372. reg += size;
  373. len -= size;
  374. pos += size;
  375. } while (len > 0);
  376. return 0;
  377. }
  378. static int r820t_write_reg(struct r820t_priv *priv, u8 reg, u8 val)
  379. {
  380. return r820t_write(priv, reg, &val, 1);
  381. }
  382. static int r820t_read_cache_reg(struct r820t_priv *priv, int reg)
  383. {
  384. reg -= REG_SHADOW_START;
  385. if (reg >= 0 && reg < NUM_REGS)
  386. return priv->regs[reg];
  387. else
  388. return -EINVAL;
  389. }
  390. static int r820t_write_reg_mask(struct r820t_priv *priv, u8 reg, u8 val,
  391. u8 bit_mask)
  392. {
  393. int rc = r820t_read_cache_reg(priv, reg);
  394. if (rc < 0)
  395. return rc;
  396. val = (rc & ~bit_mask) | (val & bit_mask);
  397. return r820t_write(priv, reg, &val, 1);
  398. }
  399. static int r820t_read(struct r820t_priv *priv, u8 reg, u8 *val, int len)
  400. {
  401. int rc, i;
  402. u8 *p = &priv->buf[1];
  403. priv->buf[0] = reg;
  404. rc = tuner_i2c_xfer_send_recv(&priv->i2c_props, priv->buf, 1, p, len);
  405. if (rc != len) {
  406. tuner_info("%s: i2c rd failed=%d reg=%02x len=%d: %*ph\n",
  407. __func__, rc, reg, len, len, p);
  408. if (rc < 0)
  409. return rc;
  410. return -EREMOTEIO;
  411. }
  412. /* Copy data to the output buffer */
  413. for (i = 0; i < len; i++)
  414. val[i] = bitrev8(p[i]);
  415. tuner_dbg("%s: i2c rd reg=%02x len=%d: %*ph\n",
  416. __func__, reg, len, len, val);
  417. return 0;
  418. }
  419. /*
  420. * r820t tuning logic
  421. */
  422. static int r820t_set_mux(struct r820t_priv *priv, u32 freq)
  423. {
  424. const struct r820t_freq_range *range;
  425. int i, rc;
  426. u8 val, reg08, reg09;
  427. /* Get the proper frequency range */
  428. freq = freq / 1000000;
  429. for (i = 0; i < ARRAY_SIZE(freq_ranges) - 1; i++) {
  430. if (freq < freq_ranges[i + 1].freq)
  431. break;
  432. }
  433. range = &freq_ranges[i];
  434. tuner_dbg("set r820t range#%d for frequency %d MHz\n", i, freq);
  435. /* Open Drain */
  436. rc = r820t_write_reg_mask(priv, 0x17, range->open_d, 0x08);
  437. if (rc < 0)
  438. return rc;
  439. /* RF_MUX,Polymux */
  440. rc = r820t_write_reg_mask(priv, 0x1a, range->rf_mux_ploy, 0xc3);
  441. if (rc < 0)
  442. return rc;
  443. /* TF BAND */
  444. rc = r820t_write_reg(priv, 0x1b, range->tf_c);
  445. if (rc < 0)
  446. return rc;
  447. /* XTAL CAP & Drive */
  448. switch (priv->xtal_cap_sel) {
  449. case XTAL_LOW_CAP_30P:
  450. case XTAL_LOW_CAP_20P:
  451. val = range->xtal_cap20p | 0x08;
  452. break;
  453. case XTAL_LOW_CAP_10P:
  454. val = range->xtal_cap10p | 0x08;
  455. break;
  456. case XTAL_HIGH_CAP_0P:
  457. val = range->xtal_cap0p | 0x00;
  458. break;
  459. default:
  460. case XTAL_LOW_CAP_0P:
  461. val = range->xtal_cap0p | 0x08;
  462. break;
  463. }
  464. rc = r820t_write_reg_mask(priv, 0x10, val, 0x0b);
  465. if (rc < 0)
  466. return rc;
  467. if (priv->imr_done) {
  468. reg08 = priv->imr_data[range->imr_mem].gain_x;
  469. reg09 = priv->imr_data[range->imr_mem].phase_y;
  470. } else {
  471. reg08 = 0;
  472. reg09 = 0;
  473. }
  474. rc = r820t_write_reg_mask(priv, 0x08, reg08, 0x3f);
  475. if (rc < 0)
  476. return rc;
  477. rc = r820t_write_reg_mask(priv, 0x09, reg09, 0x3f);
  478. return rc;
  479. }
  480. static int r820t_set_pll(struct r820t_priv *priv, enum v4l2_tuner_type type,
  481. u32 freq)
  482. {
  483. u32 vco_freq;
  484. int rc, i;
  485. unsigned sleep_time = 10000;
  486. u32 vco_fra; /* VCO contribution by SDM (kHz) */
  487. u32 vco_min = 1770000;
  488. u32 vco_max = vco_min * 2;
  489. u32 pll_ref;
  490. u16 n_sdm = 2;
  491. u16 sdm = 0;
  492. u8 mix_div = 2;
  493. u8 div_buf = 0;
  494. u8 div_num = 0;
  495. u8 refdiv2 = 0;
  496. u8 ni, si, nint, vco_fine_tune, val;
  497. u8 data[5];
  498. /* Frequency in kHz */
  499. freq = freq / 1000;
  500. pll_ref = priv->cfg->xtal / 1000;
  501. #if 0
  502. /* Doesn't exist on rtl-sdk, and on field tests, caused troubles */
  503. if ((priv->cfg->rafael_chip == CHIP_R620D) ||
  504. (priv->cfg->rafael_chip == CHIP_R828D) ||
  505. (priv->cfg->rafael_chip == CHIP_R828)) {
  506. /* ref set refdiv2, reffreq = Xtal/2 on ATV application */
  507. if (type != V4L2_TUNER_DIGITAL_TV) {
  508. pll_ref /= 2;
  509. refdiv2 = 0x10;
  510. sleep_time = 20000;
  511. }
  512. } else {
  513. if (priv->cfg->xtal > 24000000) {
  514. pll_ref /= 2;
  515. refdiv2 = 0x10;
  516. }
  517. }
  518. #endif
  519. rc = r820t_write_reg_mask(priv, 0x10, refdiv2, 0x10);
  520. if (rc < 0)
  521. return rc;
  522. /* set pll autotune = 128kHz */
  523. rc = r820t_write_reg_mask(priv, 0x1a, 0x00, 0x0c);
  524. if (rc < 0)
  525. return rc;
  526. /* set VCO current = 100 */
  527. rc = r820t_write_reg_mask(priv, 0x12, 0x80, 0xe0);
  528. if (rc < 0)
  529. return rc;
  530. /* Calculate divider */
  531. while (mix_div <= 64) {
  532. if (((freq * mix_div) >= vco_min) &&
  533. ((freq * mix_div) < vco_max)) {
  534. div_buf = mix_div;
  535. while (div_buf > 2) {
  536. div_buf = div_buf >> 1;
  537. div_num++;
  538. }
  539. break;
  540. }
  541. mix_div = mix_div << 1;
  542. }
  543. rc = r820t_read(priv, 0x00, data, sizeof(data));
  544. if (rc < 0)
  545. return rc;
  546. vco_fine_tune = (data[4] & 0x30) >> 4;
  547. tuner_dbg("mix_div=%d div_num=%d vco_fine_tune=%d\n",
  548. mix_div, div_num, vco_fine_tune);
  549. /*
  550. * XXX: R828D/16MHz seems to have always vco_fine_tune=1.
  551. * Due to that, this calculation goes wrong.
  552. */
  553. if (priv->cfg->rafael_chip != CHIP_R828D) {
  554. if (vco_fine_tune > VCO_POWER_REF)
  555. div_num = div_num - 1;
  556. else if (vco_fine_tune < VCO_POWER_REF)
  557. div_num = div_num + 1;
  558. }
  559. rc = r820t_write_reg_mask(priv, 0x10, div_num << 5, 0xe0);
  560. if (rc < 0)
  561. return rc;
  562. vco_freq = freq * mix_div;
  563. nint = vco_freq / (2 * pll_ref);
  564. vco_fra = vco_freq - 2 * pll_ref * nint;
  565. /* boundary spur prevention */
  566. if (vco_fra < pll_ref / 64) {
  567. vco_fra = 0;
  568. } else if (vco_fra > pll_ref * 127 / 64) {
  569. vco_fra = 0;
  570. nint++;
  571. } else if ((vco_fra > pll_ref * 127 / 128) && (vco_fra < pll_ref)) {
  572. vco_fra = pll_ref * 127 / 128;
  573. } else if ((vco_fra > pll_ref) && (vco_fra < pll_ref * 129 / 128)) {
  574. vco_fra = pll_ref * 129 / 128;
  575. }
  576. ni = (nint - 13) / 4;
  577. si = nint - 4 * ni - 13;
  578. rc = r820t_write_reg(priv, 0x14, ni + (si << 6));
  579. if (rc < 0)
  580. return rc;
  581. /* pw_sdm */
  582. if (!vco_fra)
  583. val = 0x08;
  584. else
  585. val = 0x00;
  586. rc = r820t_write_reg_mask(priv, 0x12, val, 0x08);
  587. if (rc < 0)
  588. return rc;
  589. /* sdm calculator */
  590. while (vco_fra > 1) {
  591. if (vco_fra > (2 * pll_ref / n_sdm)) {
  592. sdm = sdm + 32768 / (n_sdm / 2);
  593. vco_fra = vco_fra - 2 * pll_ref / n_sdm;
  594. if (n_sdm >= 0x8000)
  595. break;
  596. }
  597. n_sdm = n_sdm << 1;
  598. }
  599. tuner_dbg("freq %d kHz, pll ref %d%s, sdm=0x%04x\n",
  600. freq, pll_ref, refdiv2 ? " / 2" : "", sdm);
  601. rc = r820t_write_reg(priv, 0x16, sdm >> 8);
  602. if (rc < 0)
  603. return rc;
  604. rc = r820t_write_reg(priv, 0x15, sdm & 0xff);
  605. if (rc < 0)
  606. return rc;
  607. for (i = 0; i < 2; i++) {
  608. usleep_range(sleep_time, sleep_time + 1000);
  609. /* Check if PLL has locked */
  610. rc = r820t_read(priv, 0x00, data, 3);
  611. if (rc < 0)
  612. return rc;
  613. if (data[2] & 0x40)
  614. break;
  615. if (!i) {
  616. /* Didn't lock. Increase VCO current */
  617. rc = r820t_write_reg_mask(priv, 0x12, 0x60, 0xe0);
  618. if (rc < 0)
  619. return rc;
  620. }
  621. }
  622. if (!(data[2] & 0x40)) {
  623. priv->has_lock = false;
  624. return 0;
  625. }
  626. priv->has_lock = true;
  627. tuner_dbg("tuner has lock at frequency %d kHz\n", freq);
  628. /* set pll autotune = 8kHz */
  629. rc = r820t_write_reg_mask(priv, 0x1a, 0x08, 0x08);
  630. return rc;
  631. }
  632. static int r820t_sysfreq_sel(struct r820t_priv *priv, u32 freq,
  633. enum v4l2_tuner_type type,
  634. v4l2_std_id std,
  635. u32 delsys)
  636. {
  637. int rc;
  638. u8 mixer_top, lna_top, cp_cur, div_buf_cur, lna_vth_l, mixer_vth_l;
  639. u8 air_cable1_in, cable2_in, pre_dect, lna_discharge, filter_cur;
  640. tuner_dbg("adjusting tuner parameters for the standard\n");
  641. switch (delsys) {
  642. case SYS_DVBT:
  643. if ((freq == 506000000) || (freq == 666000000) ||
  644. (freq == 818000000)) {
  645. mixer_top = 0x14; /* mixer top:14 , top-1, low-discharge */
  646. lna_top = 0xe5; /* detect bw 3, lna top:4, predet top:2 */
  647. cp_cur = 0x28; /* 101, 0.2 */
  648. div_buf_cur = 0x20; /* 10, 200u */
  649. } else {
  650. mixer_top = 0x24; /* mixer top:13 , top-1, low-discharge */
  651. lna_top = 0xe5; /* detect bw 3, lna top:4, predet top:2 */
  652. cp_cur = 0x38; /* 111, auto */
  653. div_buf_cur = 0x30; /* 11, 150u */
  654. }
  655. lna_vth_l = 0x53; /* lna vth 0.84 , vtl 0.64 */
  656. mixer_vth_l = 0x75; /* mixer vth 1.04, vtl 0.84 */
  657. air_cable1_in = 0x00;
  658. cable2_in = 0x00;
  659. pre_dect = 0x40;
  660. lna_discharge = 14;
  661. filter_cur = 0x40; /* 10, low */
  662. break;
  663. case SYS_DVBT2:
  664. mixer_top = 0x24; /* mixer top:13 , top-1, low-discharge */
  665. lna_top = 0xe5; /* detect bw 3, lna top:4, predet top:2 */
  666. lna_vth_l = 0x53; /* lna vth 0.84 , vtl 0.64 */
  667. mixer_vth_l = 0x75; /* mixer vth 1.04, vtl 0.84 */
  668. air_cable1_in = 0x00;
  669. cable2_in = 0x00;
  670. pre_dect = 0x40;
  671. lna_discharge = 14;
  672. cp_cur = 0x38; /* 111, auto */
  673. div_buf_cur = 0x30; /* 11, 150u */
  674. filter_cur = 0x40; /* 10, low */
  675. break;
  676. case SYS_ISDBT:
  677. mixer_top = 0x24; /* mixer top:13 , top-1, low-discharge */
  678. lna_top = 0xe5; /* detect bw 3, lna top:4, predet top:2 */
  679. lna_vth_l = 0x75; /* lna vth 1.04 , vtl 0.84 */
  680. mixer_vth_l = 0x75; /* mixer vth 1.04, vtl 0.84 */
  681. air_cable1_in = 0x00;
  682. cable2_in = 0x00;
  683. pre_dect = 0x40;
  684. lna_discharge = 14;
  685. cp_cur = 0x38; /* 111, auto */
  686. div_buf_cur = 0x30; /* 11, 150u */
  687. filter_cur = 0x40; /* 10, low */
  688. break;
  689. default: /* DVB-T 8M */
  690. mixer_top = 0x24; /* mixer top:13 , top-1, low-discharge */
  691. lna_top = 0xe5; /* detect bw 3, lna top:4, predet top:2 */
  692. lna_vth_l = 0x53; /* lna vth 0.84 , vtl 0.64 */
  693. mixer_vth_l = 0x75; /* mixer vth 1.04, vtl 0.84 */
  694. air_cable1_in = 0x00;
  695. cable2_in = 0x00;
  696. pre_dect = 0x40;
  697. lna_discharge = 14;
  698. cp_cur = 0x38; /* 111, auto */
  699. div_buf_cur = 0x30; /* 11, 150u */
  700. filter_cur = 0x40; /* 10, low */
  701. break;
  702. }
  703. if (priv->cfg->use_diplexer &&
  704. ((priv->cfg->rafael_chip == CHIP_R820T) ||
  705. (priv->cfg->rafael_chip == CHIP_R828S) ||
  706. (priv->cfg->rafael_chip == CHIP_R820C))) {
  707. if (freq > DIP_FREQ)
  708. air_cable1_in = 0x00;
  709. else
  710. air_cable1_in = 0x60;
  711. cable2_in = 0x00;
  712. }
  713. if (priv->cfg->use_predetect) {
  714. rc = r820t_write_reg_mask(priv, 0x06, pre_dect, 0x40);
  715. if (rc < 0)
  716. return rc;
  717. }
  718. rc = r820t_write_reg_mask(priv, 0x1d, lna_top, 0xc7);
  719. if (rc < 0)
  720. return rc;
  721. rc = r820t_write_reg_mask(priv, 0x1c, mixer_top, 0xf8);
  722. if (rc < 0)
  723. return rc;
  724. rc = r820t_write_reg(priv, 0x0d, lna_vth_l);
  725. if (rc < 0)
  726. return rc;
  727. rc = r820t_write_reg(priv, 0x0e, mixer_vth_l);
  728. if (rc < 0)
  729. return rc;
  730. /* Air-IN only for Astrometa */
  731. rc = r820t_write_reg_mask(priv, 0x05, air_cable1_in, 0x60);
  732. if (rc < 0)
  733. return rc;
  734. rc = r820t_write_reg_mask(priv, 0x06, cable2_in, 0x08);
  735. if (rc < 0)
  736. return rc;
  737. rc = r820t_write_reg_mask(priv, 0x11, cp_cur, 0x38);
  738. if (rc < 0)
  739. return rc;
  740. rc = r820t_write_reg_mask(priv, 0x17, div_buf_cur, 0x30);
  741. if (rc < 0)
  742. return rc;
  743. rc = r820t_write_reg_mask(priv, 0x0a, filter_cur, 0x60);
  744. if (rc < 0)
  745. return rc;
  746. /*
  747. * Original driver initializes regs 0x05 and 0x06 with the
  748. * same value again on this point. Probably, it is just an
  749. * error there
  750. */
  751. /*
  752. * Set LNA
  753. */
  754. tuner_dbg("adjusting LNA parameters\n");
  755. if (type != V4L2_TUNER_ANALOG_TV) {
  756. /* LNA TOP: lowest */
  757. rc = r820t_write_reg_mask(priv, 0x1d, 0, 0x38);
  758. if (rc < 0)
  759. return rc;
  760. /* 0: normal mode */
  761. rc = r820t_write_reg_mask(priv, 0x1c, 0, 0x04);
  762. if (rc < 0)
  763. return rc;
  764. /* 0: PRE_DECT off */
  765. rc = r820t_write_reg_mask(priv, 0x06, 0, 0x40);
  766. if (rc < 0)
  767. return rc;
  768. /* agc clk 250hz */
  769. rc = r820t_write_reg_mask(priv, 0x1a, 0x30, 0x30);
  770. if (rc < 0)
  771. return rc;
  772. msleep(250);
  773. /* write LNA TOP = 3 */
  774. rc = r820t_write_reg_mask(priv, 0x1d, 0x18, 0x38);
  775. if (rc < 0)
  776. return rc;
  777. /*
  778. * write discharge mode
  779. * FIXME: IMHO, the mask here is wrong, but it matches
  780. * what's there at the original driver
  781. */
  782. rc = r820t_write_reg_mask(priv, 0x1c, mixer_top, 0x04);
  783. if (rc < 0)
  784. return rc;
  785. /* LNA discharge current */
  786. rc = r820t_write_reg_mask(priv, 0x1e, lna_discharge, 0x1f);
  787. if (rc < 0)
  788. return rc;
  789. /* agc clk 60hz */
  790. rc = r820t_write_reg_mask(priv, 0x1a, 0x20, 0x30);
  791. if (rc < 0)
  792. return rc;
  793. } else {
  794. /* PRE_DECT off */
  795. rc = r820t_write_reg_mask(priv, 0x06, 0, 0x40);
  796. if (rc < 0)
  797. return rc;
  798. /* write LNA TOP */
  799. rc = r820t_write_reg_mask(priv, 0x1d, lna_top, 0x38);
  800. if (rc < 0)
  801. return rc;
  802. /*
  803. * write discharge mode
  804. * FIXME: IMHO, the mask here is wrong, but it matches
  805. * what's there at the original driver
  806. */
  807. rc = r820t_write_reg_mask(priv, 0x1c, mixer_top, 0x04);
  808. if (rc < 0)
  809. return rc;
  810. /* LNA discharge current */
  811. rc = r820t_write_reg_mask(priv, 0x1e, lna_discharge, 0x1f);
  812. if (rc < 0)
  813. return rc;
  814. /* agc clk 1Khz, external det1 cap 1u */
  815. rc = r820t_write_reg_mask(priv, 0x1a, 0x00, 0x30);
  816. if (rc < 0)
  817. return rc;
  818. rc = r820t_write_reg_mask(priv, 0x10, 0x00, 0x04);
  819. if (rc < 0)
  820. return rc;
  821. }
  822. return 0;
  823. }
  824. static int r820t_set_tv_standard(struct r820t_priv *priv,
  825. unsigned bw,
  826. enum v4l2_tuner_type type,
  827. v4l2_std_id std, u32 delsys)
  828. {
  829. int rc, i;
  830. u32 if_khz, filt_cal_lo;
  831. u8 data[5], val;
  832. u8 filt_gain, img_r, filt_q, hp_cor, ext_enable, loop_through;
  833. u8 lt_att, flt_ext_widest, polyfil_cur;
  834. bool need_calibration;
  835. tuner_dbg("selecting the delivery system\n");
  836. if (delsys == SYS_ISDBT) {
  837. if_khz = 4063;
  838. filt_cal_lo = 59000;
  839. filt_gain = 0x10; /* +3db, 6mhz on */
  840. img_r = 0x00; /* image negative */
  841. filt_q = 0x10; /* r10[4]:low q(1'b1) */
  842. hp_cor = 0x6a; /* 1.7m disable, +2cap, 1.25mhz */
  843. ext_enable = 0x40; /* r30[6], ext enable; r30[5]:0 ext at lna max */
  844. loop_through = 0x00; /* r5[7], lt on */
  845. lt_att = 0x00; /* r31[7], lt att enable */
  846. flt_ext_widest = 0x00; /* r15[7]: flt_ext_wide off */
  847. polyfil_cur = 0x60; /* r25[6:5]:min */
  848. } else {
  849. if (bw <= 6) {
  850. if_khz = 3570;
  851. filt_cal_lo = 56000; /* 52000->56000 */
  852. filt_gain = 0x10; /* +3db, 6mhz on */
  853. img_r = 0x00; /* image negative */
  854. filt_q = 0x10; /* r10[4]:low q(1'b1) */
  855. hp_cor = 0x6b; /* 1.7m disable, +2cap, 1.0mhz */
  856. ext_enable = 0x60; /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */
  857. loop_through = 0x00; /* r5[7], lt on */
  858. lt_att = 0x00; /* r31[7], lt att enable */
  859. flt_ext_widest = 0x00; /* r15[7]: flt_ext_wide off */
  860. polyfil_cur = 0x60; /* r25[6:5]:min */
  861. } else if (bw == 7) {
  862. #if 0
  863. /*
  864. * There are two 7 MHz tables defined on the original
  865. * driver, but just the second one seems to be visible
  866. * by rtl2832. Keep this one here commented, as it
  867. * might be needed in the future
  868. */
  869. if_khz = 4070;
  870. filt_cal_lo = 60000;
  871. filt_gain = 0x10; /* +3db, 6mhz on */
  872. img_r = 0x00; /* image negative */
  873. filt_q = 0x10; /* r10[4]:low q(1'b1) */
  874. hp_cor = 0x2b; /* 1.7m disable, +1cap, 1.0mhz */
  875. ext_enable = 0x60; /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */
  876. loop_through = 0x00; /* r5[7], lt on */
  877. lt_att = 0x00; /* r31[7], lt att enable */
  878. flt_ext_widest = 0x00; /* r15[7]: flt_ext_wide off */
  879. polyfil_cur = 0x60; /* r25[6:5]:min */
  880. #endif
  881. /* 7 MHz, second table */
  882. if_khz = 4570;
  883. filt_cal_lo = 63000;
  884. filt_gain = 0x10; /* +3db, 6mhz on */
  885. img_r = 0x00; /* image negative */
  886. filt_q = 0x10; /* r10[4]:low q(1'b1) */
  887. hp_cor = 0x2a; /* 1.7m disable, +1cap, 1.25mhz */
  888. ext_enable = 0x60; /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */
  889. loop_through = 0x00; /* r5[7], lt on */
  890. lt_att = 0x00; /* r31[7], lt att enable */
  891. flt_ext_widest = 0x00; /* r15[7]: flt_ext_wide off */
  892. polyfil_cur = 0x60; /* r25[6:5]:min */
  893. } else {
  894. if_khz = 4570;
  895. filt_cal_lo = 68500;
  896. filt_gain = 0x10; /* +3db, 6mhz on */
  897. img_r = 0x00; /* image negative */
  898. filt_q = 0x10; /* r10[4]:low q(1'b1) */
  899. hp_cor = 0x0b; /* 1.7m disable, +0cap, 1.0mhz */
  900. ext_enable = 0x60; /* r30[6]=1 ext enable; r30[5]:1 ext at lna max-1 */
  901. loop_through = 0x00; /* r5[7], lt on */
  902. lt_att = 0x00; /* r31[7], lt att enable */
  903. flt_ext_widest = 0x00; /* r15[7]: flt_ext_wide off */
  904. polyfil_cur = 0x60; /* r25[6:5]:min */
  905. }
  906. }
  907. /* Initialize the shadow registers */
  908. memcpy(priv->regs, r820t_init_array, sizeof(r820t_init_array));
  909. /* Init Flag & Xtal_check Result */
  910. if (priv->imr_done)
  911. val = 1 | priv->xtal_cap_sel << 1;
  912. else
  913. val = 0;
  914. rc = r820t_write_reg_mask(priv, 0x0c, val, 0x0f);
  915. if (rc < 0)
  916. return rc;
  917. /* version */
  918. rc = r820t_write_reg_mask(priv, 0x13, VER_NUM, 0x3f);
  919. if (rc < 0)
  920. return rc;
  921. /* for LT Gain test */
  922. if (type != V4L2_TUNER_ANALOG_TV) {
  923. rc = r820t_write_reg_mask(priv, 0x1d, 0x00, 0x38);
  924. if (rc < 0)
  925. return rc;
  926. usleep_range(1000, 2000);
  927. }
  928. priv->int_freq = if_khz * 1000;
  929. /* Check if standard changed. If so, filter calibration is needed */
  930. if (type != priv->type)
  931. need_calibration = true;
  932. else if ((type == V4L2_TUNER_ANALOG_TV) && (std != priv->std))
  933. need_calibration = true;
  934. else if ((type == V4L2_TUNER_DIGITAL_TV) &&
  935. ((delsys != priv->delsys) || bw != priv->bw))
  936. need_calibration = true;
  937. else
  938. need_calibration = false;
  939. if (need_calibration) {
  940. tuner_dbg("calibrating the tuner\n");
  941. for (i = 0; i < 2; i++) {
  942. /* Set filt_cap */
  943. rc = r820t_write_reg_mask(priv, 0x0b, hp_cor, 0x60);
  944. if (rc < 0)
  945. return rc;
  946. /* set cali clk =on */
  947. rc = r820t_write_reg_mask(priv, 0x0f, 0x04, 0x04);
  948. if (rc < 0)
  949. return rc;
  950. /* X'tal cap 0pF for PLL */
  951. rc = r820t_write_reg_mask(priv, 0x10, 0x00, 0x03);
  952. if (rc < 0)
  953. return rc;
  954. rc = r820t_set_pll(priv, type, filt_cal_lo * 1000);
  955. if (rc < 0 || !priv->has_lock)
  956. return rc;
  957. /* Start Trigger */
  958. rc = r820t_write_reg_mask(priv, 0x0b, 0x10, 0x10);
  959. if (rc < 0)
  960. return rc;
  961. usleep_range(1000, 2000);
  962. /* Stop Trigger */
  963. rc = r820t_write_reg_mask(priv, 0x0b, 0x00, 0x10);
  964. if (rc < 0)
  965. return rc;
  966. /* set cali clk =off */
  967. rc = r820t_write_reg_mask(priv, 0x0f, 0x00, 0x04);
  968. if (rc < 0)
  969. return rc;
  970. /* Check if calibration worked */
  971. rc = r820t_read(priv, 0x00, data, sizeof(data));
  972. if (rc < 0)
  973. return rc;
  974. priv->fil_cal_code = data[4] & 0x0f;
  975. if (priv->fil_cal_code && priv->fil_cal_code != 0x0f)
  976. break;
  977. }
  978. /* narrowest */
  979. if (priv->fil_cal_code == 0x0f)
  980. priv->fil_cal_code = 0;
  981. }
  982. rc = r820t_write_reg_mask(priv, 0x0a,
  983. filt_q | priv->fil_cal_code, 0x1f);
  984. if (rc < 0)
  985. return rc;
  986. /* Set BW, Filter_gain, & HP corner */
  987. rc = r820t_write_reg_mask(priv, 0x0b, hp_cor, 0xef);
  988. if (rc < 0)
  989. return rc;
  990. /* Set Img_R */
  991. rc = r820t_write_reg_mask(priv, 0x07, img_r, 0x80);
  992. if (rc < 0)
  993. return rc;
  994. /* Set filt_3dB, V6MHz */
  995. rc = r820t_write_reg_mask(priv, 0x06, filt_gain, 0x30);
  996. if (rc < 0)
  997. return rc;
  998. /* channel filter extension */
  999. rc = r820t_write_reg_mask(priv, 0x1e, ext_enable, 0x60);
  1000. if (rc < 0)
  1001. return rc;
  1002. /* Loop through */
  1003. rc = r820t_write_reg_mask(priv, 0x05, loop_through, 0x80);
  1004. if (rc < 0)
  1005. return rc;
  1006. /* Loop through attenuation */
  1007. rc = r820t_write_reg_mask(priv, 0x1f, lt_att, 0x80);
  1008. if (rc < 0)
  1009. return rc;
  1010. /* filter extension widest */
  1011. rc = r820t_write_reg_mask(priv, 0x0f, flt_ext_widest, 0x80);
  1012. if (rc < 0)
  1013. return rc;
  1014. /* RF poly filter current */
  1015. rc = r820t_write_reg_mask(priv, 0x19, polyfil_cur, 0x60);
  1016. if (rc < 0)
  1017. return rc;
  1018. /* Store current standard. If it changes, re-calibrate the tuner */
  1019. priv->delsys = delsys;
  1020. priv->type = type;
  1021. priv->std = std;
  1022. priv->bw = bw;
  1023. return 0;
  1024. }
  1025. static int r820t_read_gain(struct r820t_priv *priv)
  1026. {
  1027. u8 data[4];
  1028. int rc;
  1029. rc = r820t_read(priv, 0x00, data, sizeof(data));
  1030. if (rc < 0)
  1031. return rc;
  1032. return ((data[3] & 0x0f) << 1) + ((data[3] & 0xf0) >> 4);
  1033. }
  1034. #if 0
  1035. /* FIXME: This routine requires more testing */
  1036. static int r820t_set_gain_mode(struct r820t_priv *priv,
  1037. bool set_manual_gain,
  1038. int gain)
  1039. {
  1040. int rc;
  1041. if (set_manual_gain) {
  1042. int i, total_gain = 0;
  1043. uint8_t mix_index = 0, lna_index = 0;
  1044. u8 data[4];
  1045. /* LNA auto off */
  1046. rc = r820t_write_reg_mask(priv, 0x05, 0x10, 0x10);
  1047. if (rc < 0)
  1048. return rc;
  1049. /* Mixer auto off */
  1050. rc = r820t_write_reg_mask(priv, 0x07, 0, 0x10);
  1051. if (rc < 0)
  1052. return rc;
  1053. rc = r820t_read(priv, 0x00, data, sizeof(data));
  1054. if (rc < 0)
  1055. return rc;
  1056. /* set fixed VGA gain for now (16.3 dB) */
  1057. rc = r820t_write_reg_mask(priv, 0x0c, 0x08, 0x9f);
  1058. if (rc < 0)
  1059. return rc;
  1060. for (i = 0; i < 15; i++) {
  1061. if (total_gain >= gain)
  1062. break;
  1063. total_gain += r820t_lna_gain_steps[++lna_index];
  1064. if (total_gain >= gain)
  1065. break;
  1066. total_gain += r820t_mixer_gain_steps[++mix_index];
  1067. }
  1068. /* set LNA gain */
  1069. rc = r820t_write_reg_mask(priv, 0x05, lna_index, 0x0f);
  1070. if (rc < 0)
  1071. return rc;
  1072. /* set Mixer gain */
  1073. rc = r820t_write_reg_mask(priv, 0x07, mix_index, 0x0f);
  1074. if (rc < 0)
  1075. return rc;
  1076. } else {
  1077. /* LNA */
  1078. rc = r820t_write_reg_mask(priv, 0x05, 0, 0x10);
  1079. if (rc < 0)
  1080. return rc;
  1081. /* Mixer */
  1082. rc = r820t_write_reg_mask(priv, 0x07, 0x10, 0x10);
  1083. if (rc < 0)
  1084. return rc;
  1085. /* set fixed VGA gain for now (26.5 dB) */
  1086. rc = r820t_write_reg_mask(priv, 0x0c, 0x0b, 0x9f);
  1087. if (rc < 0)
  1088. return rc;
  1089. }
  1090. return 0;
  1091. }
  1092. #endif
  1093. static int generic_set_freq(struct dvb_frontend *fe,
  1094. u32 freq /* in HZ */,
  1095. unsigned bw,
  1096. enum v4l2_tuner_type type,
  1097. v4l2_std_id std, u32 delsys)
  1098. {
  1099. struct r820t_priv *priv = fe->tuner_priv;
  1100. int rc = -EINVAL;
  1101. u32 lo_freq;
  1102. tuner_dbg("should set frequency to %d kHz, bw %d MHz\n",
  1103. freq / 1000, bw);
  1104. rc = r820t_set_tv_standard(priv, bw, type, std, delsys);
  1105. if (rc < 0)
  1106. goto err;
  1107. if ((type == V4L2_TUNER_ANALOG_TV) && (std == V4L2_STD_SECAM_LC))
  1108. lo_freq = freq - priv->int_freq;
  1109. else
  1110. lo_freq = freq + priv->int_freq;
  1111. rc = r820t_set_mux(priv, lo_freq);
  1112. if (rc < 0)
  1113. goto err;
  1114. rc = r820t_set_pll(priv, type, lo_freq);
  1115. if (rc < 0 || !priv->has_lock)
  1116. goto err;
  1117. rc = r820t_sysfreq_sel(priv, freq, type, std, delsys);
  1118. if (rc < 0)
  1119. goto err;
  1120. tuner_dbg("%s: PLL locked on frequency %d Hz, gain=%d\n",
  1121. __func__, freq, r820t_read_gain(priv));
  1122. err:
  1123. if (rc < 0)
  1124. tuner_dbg("%s: failed=%d\n", __func__, rc);
  1125. return rc;
  1126. }
  1127. /*
  1128. * r820t standby logic
  1129. */
  1130. static int r820t_standby(struct r820t_priv *priv)
  1131. {
  1132. int rc;
  1133. /* If device was not initialized yet, don't need to standby */
  1134. if (!priv->init_done)
  1135. return 0;
  1136. rc = r820t_write_reg(priv, 0x06, 0xb1);
  1137. if (rc < 0)
  1138. return rc;
  1139. rc = r820t_write_reg(priv, 0x05, 0x03);
  1140. if (rc < 0)
  1141. return rc;
  1142. rc = r820t_write_reg(priv, 0x07, 0x3a);
  1143. if (rc < 0)
  1144. return rc;
  1145. rc = r820t_write_reg(priv, 0x08, 0x40);
  1146. if (rc < 0)
  1147. return rc;
  1148. rc = r820t_write_reg(priv, 0x09, 0xc0);
  1149. if (rc < 0)
  1150. return rc;
  1151. rc = r820t_write_reg(priv, 0x0a, 0x36);
  1152. if (rc < 0)
  1153. return rc;
  1154. rc = r820t_write_reg(priv, 0x0c, 0x35);
  1155. if (rc < 0)
  1156. return rc;
  1157. rc = r820t_write_reg(priv, 0x0f, 0x68);
  1158. if (rc < 0)
  1159. return rc;
  1160. rc = r820t_write_reg(priv, 0x11, 0x03);
  1161. if (rc < 0)
  1162. return rc;
  1163. rc = r820t_write_reg(priv, 0x17, 0xf4);
  1164. if (rc < 0)
  1165. return rc;
  1166. rc = r820t_write_reg(priv, 0x19, 0x0c);
  1167. /* Force initial calibration */
  1168. priv->type = -1;
  1169. return rc;
  1170. }
  1171. /*
  1172. * r820t device init logic
  1173. */
  1174. static int r820t_xtal_check(struct r820t_priv *priv)
  1175. {
  1176. int rc, i;
  1177. u8 data[3], val;
  1178. /* Initialize the shadow registers */
  1179. memcpy(priv->regs, r820t_init_array, sizeof(r820t_init_array));
  1180. /* cap 30pF & Drive Low */
  1181. rc = r820t_write_reg_mask(priv, 0x10, 0x0b, 0x0b);
  1182. if (rc < 0)
  1183. return rc;
  1184. /* set pll autotune = 128kHz */
  1185. rc = r820t_write_reg_mask(priv, 0x1a, 0x00, 0x0c);
  1186. if (rc < 0)
  1187. return rc;
  1188. /* set manual initial reg = 111111; */
  1189. rc = r820t_write_reg_mask(priv, 0x13, 0x7f, 0x7f);
  1190. if (rc < 0)
  1191. return rc;
  1192. /* set auto */
  1193. rc = r820t_write_reg_mask(priv, 0x13, 0x00, 0x40);
  1194. if (rc < 0)
  1195. return rc;
  1196. /* Try several xtal capacitor alternatives */
  1197. for (i = 0; i < ARRAY_SIZE(r820t_xtal_capacitor); i++) {
  1198. rc = r820t_write_reg_mask(priv, 0x10,
  1199. r820t_xtal_capacitor[i][0], 0x1b);
  1200. if (rc < 0)
  1201. return rc;
  1202. usleep_range(5000, 6000);
  1203. rc = r820t_read(priv, 0x00, data, sizeof(data));
  1204. if (rc < 0)
  1205. return rc;
  1206. if (!(data[2] & 0x40))
  1207. continue;
  1208. val = data[2] & 0x3f;
  1209. if (priv->cfg->xtal == 16000000 && (val > 29 || val < 23))
  1210. break;
  1211. if (val != 0x3f)
  1212. break;
  1213. }
  1214. if (i == ARRAY_SIZE(r820t_xtal_capacitor))
  1215. return -EINVAL;
  1216. return r820t_xtal_capacitor[i][1];
  1217. }
  1218. static int r820t_imr_prepare(struct r820t_priv *priv)
  1219. {
  1220. int rc;
  1221. /* Initialize the shadow registers */
  1222. memcpy(priv->regs, r820t_init_array, sizeof(r820t_init_array));
  1223. /* lna off (air-in off) */
  1224. rc = r820t_write_reg_mask(priv, 0x05, 0x20, 0x20);
  1225. if (rc < 0)
  1226. return rc;
  1227. /* mixer gain mode = manual */
  1228. rc = r820t_write_reg_mask(priv, 0x07, 0, 0x10);
  1229. if (rc < 0)
  1230. return rc;
  1231. /* filter corner = lowest */
  1232. rc = r820t_write_reg_mask(priv, 0x0a, 0x0f, 0x0f);
  1233. if (rc < 0)
  1234. return rc;
  1235. /* filter bw=+2cap, hp=5M */
  1236. rc = r820t_write_reg_mask(priv, 0x0b, 0x60, 0x6f);
  1237. if (rc < 0)
  1238. return rc;
  1239. /* adc=on, vga code mode, gain = 26.5dB */
  1240. rc = r820t_write_reg_mask(priv, 0x0c, 0x0b, 0x9f);
  1241. if (rc < 0)
  1242. return rc;
  1243. /* ring clk = on */
  1244. rc = r820t_write_reg_mask(priv, 0x0f, 0, 0x08);
  1245. if (rc < 0)
  1246. return rc;
  1247. /* ring power = on */
  1248. rc = r820t_write_reg_mask(priv, 0x18, 0x10, 0x10);
  1249. if (rc < 0)
  1250. return rc;
  1251. /* from ring = ring pll in */
  1252. rc = r820t_write_reg_mask(priv, 0x1c, 0x02, 0x02);
  1253. if (rc < 0)
  1254. return rc;
  1255. /* sw_pdect = det3 */
  1256. rc = r820t_write_reg_mask(priv, 0x1e, 0x80, 0x80);
  1257. if (rc < 0)
  1258. return rc;
  1259. /* Set filt_3dB */
  1260. rc = r820t_write_reg_mask(priv, 0x06, 0x20, 0x20);
  1261. return rc;
  1262. }
  1263. static int r820t_multi_read(struct r820t_priv *priv)
  1264. {
  1265. int rc, i;
  1266. u8 data[2], min = 0, max = 255, sum = 0;
  1267. usleep_range(5000, 6000);
  1268. for (i = 0; i < 6; i++) {
  1269. rc = r820t_read(priv, 0x00, data, sizeof(data));
  1270. if (rc < 0)
  1271. return rc;
  1272. sum += data[1];
  1273. if (data[1] < min)
  1274. min = data[1];
  1275. if (data[1] > max)
  1276. max = data[1];
  1277. }
  1278. rc = sum - max - min;
  1279. return rc;
  1280. }
  1281. static int r820t_imr_cross(struct r820t_priv *priv,
  1282. struct r820t_sect_type iq_point[3],
  1283. u8 *x_direct)
  1284. {
  1285. struct r820t_sect_type cross[5]; /* (0,0)(0,Q-1)(0,I-1)(Q-1,0)(I-1,0) */
  1286. struct r820t_sect_type tmp;
  1287. int i, rc;
  1288. u8 reg08, reg09;
  1289. reg08 = r820t_read_cache_reg(priv, 8) & 0xc0;
  1290. reg09 = r820t_read_cache_reg(priv, 9) & 0xc0;
  1291. tmp.gain_x = 0;
  1292. tmp.phase_y = 0;
  1293. tmp.value = 255;
  1294. for (i = 0; i < 5; i++) {
  1295. switch (i) {
  1296. case 0:
  1297. cross[i].gain_x = reg08;
  1298. cross[i].phase_y = reg09;
  1299. break;
  1300. case 1:
  1301. cross[i].gain_x = reg08; /* 0 */
  1302. cross[i].phase_y = reg09 + 1; /* Q-1 */
  1303. break;
  1304. case 2:
  1305. cross[i].gain_x = reg08; /* 0 */
  1306. cross[i].phase_y = (reg09 | 0x20) + 1; /* I-1 */
  1307. break;
  1308. case 3:
  1309. cross[i].gain_x = reg08 + 1; /* Q-1 */
  1310. cross[i].phase_y = reg09;
  1311. break;
  1312. default:
  1313. cross[i].gain_x = (reg08 | 0x20) + 1; /* I-1 */
  1314. cross[i].phase_y = reg09;
  1315. }
  1316. rc = r820t_write_reg(priv, 0x08, cross[i].gain_x);
  1317. if (rc < 0)
  1318. return rc;
  1319. rc = r820t_write_reg(priv, 0x09, cross[i].phase_y);
  1320. if (rc < 0)
  1321. return rc;
  1322. rc = r820t_multi_read(priv);
  1323. if (rc < 0)
  1324. return rc;
  1325. cross[i].value = rc;
  1326. if (cross[i].value < tmp.value)
  1327. memcpy(&tmp, &cross[i], sizeof(tmp));
  1328. }
  1329. if ((tmp.phase_y & 0x1f) == 1) { /* y-direction */
  1330. *x_direct = 0;
  1331. iq_point[0] = cross[0];
  1332. iq_point[1] = cross[1];
  1333. iq_point[2] = cross[2];
  1334. } else { /* (0,0) or x-direction */
  1335. *x_direct = 1;
  1336. iq_point[0] = cross[0];
  1337. iq_point[1] = cross[3];
  1338. iq_point[2] = cross[4];
  1339. }
  1340. return 0;
  1341. }
  1342. static void r820t_compre_cor(struct r820t_sect_type iq[3])
  1343. {
  1344. int i;
  1345. for (i = 3; i > 0; i--) {
  1346. if (iq[0].value > iq[i - 1].value)
  1347. swap(iq[0], iq[i - 1]);
  1348. }
  1349. }
  1350. static int r820t_compre_step(struct r820t_priv *priv,
  1351. struct r820t_sect_type iq[3], u8 reg)
  1352. {
  1353. int rc;
  1354. struct r820t_sect_type tmp;
  1355. /*
  1356. * Purpose: if (Gain<9 or Phase<9), Gain+1 or Phase+1 and compare
  1357. * with min value:
  1358. * new < min => update to min and continue
  1359. * new > min => Exit
  1360. */
  1361. /* min value already saved in iq[0] */
  1362. tmp.phase_y = iq[0].phase_y;
  1363. tmp.gain_x = iq[0].gain_x;
  1364. while (((tmp.gain_x & 0x1f) < IMR_TRIAL) &&
  1365. ((tmp.phase_y & 0x1f) < IMR_TRIAL)) {
  1366. if (reg == 0x08)
  1367. tmp.gain_x++;
  1368. else
  1369. tmp.phase_y++;
  1370. rc = r820t_write_reg(priv, 0x08, tmp.gain_x);
  1371. if (rc < 0)
  1372. return rc;
  1373. rc = r820t_write_reg(priv, 0x09, tmp.phase_y);
  1374. if (rc < 0)
  1375. return rc;
  1376. rc = r820t_multi_read(priv);
  1377. if (rc < 0)
  1378. return rc;
  1379. tmp.value = rc;
  1380. if (tmp.value <= iq[0].value) {
  1381. iq[0].gain_x = tmp.gain_x;
  1382. iq[0].phase_y = tmp.phase_y;
  1383. iq[0].value = tmp.value;
  1384. } else {
  1385. return 0;
  1386. }
  1387. }
  1388. return 0;
  1389. }
  1390. static int r820t_iq_tree(struct r820t_priv *priv,
  1391. struct r820t_sect_type iq[3],
  1392. u8 fix_val, u8 var_val, u8 fix_reg)
  1393. {
  1394. int rc, i;
  1395. u8 tmp, var_reg;
  1396. /*
  1397. * record IMC results by input gain/phase location then adjust
  1398. * gain or phase positive 1 step and negtive 1 step,
  1399. * both record results
  1400. */
  1401. if (fix_reg == 0x08)
  1402. var_reg = 0x09;
  1403. else
  1404. var_reg = 0x08;
  1405. for (i = 0; i < 3; i++) {
  1406. rc = r820t_write_reg(priv, fix_reg, fix_val);
  1407. if (rc < 0)
  1408. return rc;
  1409. rc = r820t_write_reg(priv, var_reg, var_val);
  1410. if (rc < 0)
  1411. return rc;
  1412. rc = r820t_multi_read(priv);
  1413. if (rc < 0)
  1414. return rc;
  1415. iq[i].value = rc;
  1416. if (fix_reg == 0x08) {
  1417. iq[i].gain_x = fix_val;
  1418. iq[i].phase_y = var_val;
  1419. } else {
  1420. iq[i].phase_y = fix_val;
  1421. iq[i].gain_x = var_val;
  1422. }
  1423. if (i == 0) { /* try right-side point */
  1424. var_val++;
  1425. } else if (i == 1) { /* try left-side point */
  1426. /* if absolute location is 1, change I/Q direction */
  1427. if ((var_val & 0x1f) < 0x02) {
  1428. tmp = 2 - (var_val & 0x1f);
  1429. /* b[5]:I/Q selection. 0:Q-path, 1:I-path */
  1430. if (var_val & 0x20) {
  1431. var_val &= 0xc0;
  1432. var_val |= tmp;
  1433. } else {
  1434. var_val |= 0x20 | tmp;
  1435. }
  1436. } else {
  1437. var_val -= 2;
  1438. }
  1439. }
  1440. }
  1441. return 0;
  1442. }
  1443. static int r820t_section(struct r820t_priv *priv,
  1444. struct r820t_sect_type *iq_point)
  1445. {
  1446. int rc;
  1447. struct r820t_sect_type compare_iq[3], compare_bet[3];
  1448. /* Try X-1 column and save min result to compare_bet[0] */
  1449. if (!(iq_point->gain_x & 0x1f))
  1450. compare_iq[0].gain_x = ((iq_point->gain_x) & 0xdf) + 1; /* Q-path, Gain=1 */
  1451. else
  1452. compare_iq[0].gain_x = iq_point->gain_x - 1; /* left point */
  1453. compare_iq[0].phase_y = iq_point->phase_y;
  1454. /* y-direction */
  1455. rc = r820t_iq_tree(priv, compare_iq, compare_iq[0].gain_x,
  1456. compare_iq[0].phase_y, 0x08);
  1457. if (rc < 0)
  1458. return rc;
  1459. r820t_compre_cor(compare_iq);
  1460. compare_bet[0] = compare_iq[0];
  1461. /* Try X column and save min result to compare_bet[1] */
  1462. compare_iq[0].gain_x = iq_point->gain_x;
  1463. compare_iq[0].phase_y = iq_point->phase_y;
  1464. rc = r820t_iq_tree(priv, compare_iq, compare_iq[0].gain_x,
  1465. compare_iq[0].phase_y, 0x08);
  1466. if (rc < 0)
  1467. return rc;
  1468. r820t_compre_cor(compare_iq);
  1469. compare_bet[1] = compare_iq[0];
  1470. /* Try X+1 column and save min result to compare_bet[2] */
  1471. if ((iq_point->gain_x & 0x1f) == 0x00)
  1472. compare_iq[0].gain_x = ((iq_point->gain_x) | 0x20) + 1; /* I-path, Gain=1 */
  1473. else
  1474. compare_iq[0].gain_x = iq_point->gain_x + 1;
  1475. compare_iq[0].phase_y = iq_point->phase_y;
  1476. rc = r820t_iq_tree(priv, compare_iq, compare_iq[0].gain_x,
  1477. compare_iq[0].phase_y, 0x08);
  1478. if (rc < 0)
  1479. return rc;
  1480. r820t_compre_cor(compare_iq);
  1481. compare_bet[2] = compare_iq[0];
  1482. r820t_compre_cor(compare_bet);
  1483. *iq_point = compare_bet[0];
  1484. return 0;
  1485. }
  1486. static int r820t_vga_adjust(struct r820t_priv *priv)
  1487. {
  1488. int rc;
  1489. u8 vga_count;
  1490. /* increase vga power to let image significant */
  1491. for (vga_count = 12; vga_count < 16; vga_count++) {
  1492. rc = r820t_write_reg_mask(priv, 0x0c, vga_count, 0x0f);
  1493. if (rc < 0)
  1494. return rc;
  1495. usleep_range(10000, 11000);
  1496. rc = r820t_multi_read(priv);
  1497. if (rc < 0)
  1498. return rc;
  1499. if (rc > 40 * 4)
  1500. break;
  1501. }
  1502. return 0;
  1503. }
  1504. static int r820t_iq(struct r820t_priv *priv, struct r820t_sect_type *iq_pont)
  1505. {
  1506. struct r820t_sect_type compare_iq[3];
  1507. int rc;
  1508. u8 x_direction = 0; /* 1:x, 0:y */
  1509. u8 dir_reg, other_reg;
  1510. r820t_vga_adjust(priv);
  1511. rc = r820t_imr_cross(priv, compare_iq, &x_direction);
  1512. if (rc < 0)
  1513. return rc;
  1514. if (x_direction == 1) {
  1515. dir_reg = 0x08;
  1516. other_reg = 0x09;
  1517. } else {
  1518. dir_reg = 0x09;
  1519. other_reg = 0x08;
  1520. }
  1521. /* compare and find min of 3 points. determine i/q direction */
  1522. r820t_compre_cor(compare_iq);
  1523. /* increase step to find min value of this direction */
  1524. rc = r820t_compre_step(priv, compare_iq, dir_reg);
  1525. if (rc < 0)
  1526. return rc;
  1527. /* the other direction */
  1528. rc = r820t_iq_tree(priv, compare_iq, compare_iq[0].gain_x,
  1529. compare_iq[0].phase_y, dir_reg);
  1530. if (rc < 0)
  1531. return rc;
  1532. /* compare and find min of 3 points. determine i/q direction */
  1533. r820t_compre_cor(compare_iq);
  1534. /* increase step to find min value on this direction */
  1535. rc = r820t_compre_step(priv, compare_iq, other_reg);
  1536. if (rc < 0)
  1537. return rc;
  1538. /* check 3 points again */
  1539. rc = r820t_iq_tree(priv, compare_iq, compare_iq[0].gain_x,
  1540. compare_iq[0].phase_y, other_reg);
  1541. if (rc < 0)
  1542. return rc;
  1543. r820t_compre_cor(compare_iq);
  1544. /* section-9 check */
  1545. rc = r820t_section(priv, compare_iq);
  1546. *iq_pont = compare_iq[0];
  1547. /* reset gain/phase control setting */
  1548. rc = r820t_write_reg_mask(priv, 0x08, 0, 0x3f);
  1549. if (rc < 0)
  1550. return rc;
  1551. rc = r820t_write_reg_mask(priv, 0x09, 0, 0x3f);
  1552. return rc;
  1553. }
  1554. static int r820t_f_imr(struct r820t_priv *priv, struct r820t_sect_type *iq_pont)
  1555. {
  1556. int rc;
  1557. r820t_vga_adjust(priv);
  1558. /*
  1559. * search surrounding points from previous point
  1560. * try (x-1), (x), (x+1) columns, and find min IMR result point
  1561. */
  1562. rc = r820t_section(priv, iq_pont);
  1563. if (rc < 0)
  1564. return rc;
  1565. return 0;
  1566. }
  1567. static int r820t_imr(struct r820t_priv *priv, unsigned imr_mem, bool im_flag)
  1568. {
  1569. struct r820t_sect_type imr_point;
  1570. int rc;
  1571. u32 ring_vco, ring_freq, ring_ref;
  1572. u8 n_ring, n;
  1573. int reg18, reg19, reg1f;
  1574. if (priv->cfg->xtal > 24000000)
  1575. ring_ref = priv->cfg->xtal / 2000;
  1576. else
  1577. ring_ref = priv->cfg->xtal / 1000;
  1578. n_ring = 15;
  1579. for (n = 0; n < 16; n++) {
  1580. if ((16 + n) * 8 * ring_ref >= 3100000) {
  1581. n_ring = n;
  1582. break;
  1583. }
  1584. }
  1585. reg18 = r820t_read_cache_reg(priv, 0x18);
  1586. reg19 = r820t_read_cache_reg(priv, 0x19);
  1587. reg1f = r820t_read_cache_reg(priv, 0x1f);
  1588. reg18 &= 0xf0; /* set ring[3:0] */
  1589. reg18 |= n_ring;
  1590. ring_vco = (16 + n_ring) * 8 * ring_ref;
  1591. reg18 &= 0xdf; /* clear ring_se23 */
  1592. reg19 &= 0xfc; /* clear ring_seldiv */
  1593. reg1f &= 0xfc; /* clear ring_att */
  1594. switch (imr_mem) {
  1595. case 0:
  1596. ring_freq = ring_vco / 48;
  1597. reg18 |= 0x20; /* ring_se23 = 1 */
  1598. reg19 |= 0x03; /* ring_seldiv = 3 */
  1599. reg1f |= 0x02; /* ring_att 10 */
  1600. break;
  1601. case 1:
  1602. ring_freq = ring_vco / 16;
  1603. reg18 |= 0x00; /* ring_se23 = 0 */
  1604. reg19 |= 0x02; /* ring_seldiv = 2 */
  1605. reg1f |= 0x00; /* pw_ring 00 */
  1606. break;
  1607. case 2:
  1608. ring_freq = ring_vco / 8;
  1609. reg18 |= 0x00; /* ring_se23 = 0 */
  1610. reg19 |= 0x01; /* ring_seldiv = 1 */
  1611. reg1f |= 0x03; /* pw_ring 11 */
  1612. break;
  1613. case 3:
  1614. ring_freq = ring_vco / 6;
  1615. reg18 |= 0x20; /* ring_se23 = 1 */
  1616. reg19 |= 0x00; /* ring_seldiv = 0 */
  1617. reg1f |= 0x03; /* pw_ring 11 */
  1618. break;
  1619. case 4:
  1620. ring_freq = ring_vco / 4;
  1621. reg18 |= 0x00; /* ring_se23 = 0 */
  1622. reg19 |= 0x00; /* ring_seldiv = 0 */
  1623. reg1f |= 0x01; /* pw_ring 01 */
  1624. break;
  1625. default:
  1626. ring_freq = ring_vco / 4;
  1627. reg18 |= 0x00; /* ring_se23 = 0 */
  1628. reg19 |= 0x00; /* ring_seldiv = 0 */
  1629. reg1f |= 0x01; /* pw_ring 01 */
  1630. break;
  1631. }
  1632. /* write pw_ring, n_ring, ringdiv2 registers */
  1633. /* n_ring, ring_se23 */
  1634. rc = r820t_write_reg(priv, 0x18, reg18);
  1635. if (rc < 0)
  1636. return rc;
  1637. /* ring_sediv */
  1638. rc = r820t_write_reg(priv, 0x19, reg19);
  1639. if (rc < 0)
  1640. return rc;
  1641. /* pw_ring */
  1642. rc = r820t_write_reg(priv, 0x1f, reg1f);
  1643. if (rc < 0)
  1644. return rc;
  1645. /* mux input freq ~ rf_in freq */
  1646. rc = r820t_set_mux(priv, (ring_freq - 5300) * 1000);
  1647. if (rc < 0)
  1648. return rc;
  1649. rc = r820t_set_pll(priv, V4L2_TUNER_DIGITAL_TV,
  1650. (ring_freq - 5300) * 1000);
  1651. if (!priv->has_lock)
  1652. rc = -EINVAL;
  1653. if (rc < 0)
  1654. return rc;
  1655. if (im_flag) {
  1656. rc = r820t_iq(priv, &imr_point);
  1657. } else {
  1658. imr_point.gain_x = priv->imr_data[3].gain_x;
  1659. imr_point.phase_y = priv->imr_data[3].phase_y;
  1660. imr_point.value = priv->imr_data[3].value;
  1661. rc = r820t_f_imr(priv, &imr_point);
  1662. }
  1663. if (rc < 0)
  1664. return rc;
  1665. /* save IMR value */
  1666. switch (imr_mem) {
  1667. case 0:
  1668. priv->imr_data[0].gain_x = imr_point.gain_x;
  1669. priv->imr_data[0].phase_y = imr_point.phase_y;
  1670. priv->imr_data[0].value = imr_point.value;
  1671. break;
  1672. case 1:
  1673. priv->imr_data[1].gain_x = imr_point.gain_x;
  1674. priv->imr_data[1].phase_y = imr_point.phase_y;
  1675. priv->imr_data[1].value = imr_point.value;
  1676. break;
  1677. case 2:
  1678. priv->imr_data[2].gain_x = imr_point.gain_x;
  1679. priv->imr_data[2].phase_y = imr_point.phase_y;
  1680. priv->imr_data[2].value = imr_point.value;
  1681. break;
  1682. case 3:
  1683. priv->imr_data[3].gain_x = imr_point.gain_x;
  1684. priv->imr_data[3].phase_y = imr_point.phase_y;
  1685. priv->imr_data[3].value = imr_point.value;
  1686. break;
  1687. case 4:
  1688. priv->imr_data[4].gain_x = imr_point.gain_x;
  1689. priv->imr_data[4].phase_y = imr_point.phase_y;
  1690. priv->imr_data[4].value = imr_point.value;
  1691. break;
  1692. default:
  1693. priv->imr_data[4].gain_x = imr_point.gain_x;
  1694. priv->imr_data[4].phase_y = imr_point.phase_y;
  1695. priv->imr_data[4].value = imr_point.value;
  1696. break;
  1697. }
  1698. return 0;
  1699. }
  1700. static int r820t_imr_callibrate(struct r820t_priv *priv)
  1701. {
  1702. int rc, i;
  1703. int xtal_cap = 0;
  1704. if (priv->init_done)
  1705. return 0;
  1706. /* Detect Xtal capacitance */
  1707. if ((priv->cfg->rafael_chip == CHIP_R820T) ||
  1708. (priv->cfg->rafael_chip == CHIP_R828S) ||
  1709. (priv->cfg->rafael_chip == CHIP_R820C)) {
  1710. priv->xtal_cap_sel = XTAL_HIGH_CAP_0P;
  1711. } else {
  1712. /* Initialize registers */
  1713. rc = r820t_write(priv, 0x05,
  1714. r820t_init_array, sizeof(r820t_init_array));
  1715. if (rc < 0)
  1716. return rc;
  1717. for (i = 0; i < 3; i++) {
  1718. rc = r820t_xtal_check(priv);
  1719. if (rc < 0)
  1720. return rc;
  1721. if (!i || rc > xtal_cap)
  1722. xtal_cap = rc;
  1723. }
  1724. priv->xtal_cap_sel = xtal_cap;
  1725. }
  1726. /*
  1727. * Disables IMR callibration. That emulates the same behaviour
  1728. * as what is done by rtl-sdr userspace library. Useful for testing
  1729. */
  1730. if (no_imr_cal) {
  1731. priv->init_done = true;
  1732. return 0;
  1733. }
  1734. /* Initialize registers */
  1735. rc = r820t_write(priv, 0x05,
  1736. r820t_init_array, sizeof(r820t_init_array));
  1737. if (rc < 0)
  1738. return rc;
  1739. rc = r820t_imr_prepare(priv);
  1740. if (rc < 0)
  1741. return rc;
  1742. rc = r820t_imr(priv, 3, true);
  1743. if (rc < 0)
  1744. return rc;
  1745. rc = r820t_imr(priv, 1, false);
  1746. if (rc < 0)
  1747. return rc;
  1748. rc = r820t_imr(priv, 0, false);
  1749. if (rc < 0)
  1750. return rc;
  1751. rc = r820t_imr(priv, 2, false);
  1752. if (rc < 0)
  1753. return rc;
  1754. rc = r820t_imr(priv, 4, false);
  1755. if (rc < 0)
  1756. return rc;
  1757. priv->init_done = true;
  1758. priv->imr_done = true;
  1759. return 0;
  1760. }
  1761. #if 0
  1762. /* Not used, for now */
  1763. static int r820t_gpio(struct r820t_priv *priv, bool enable)
  1764. {
  1765. return r820t_write_reg_mask(priv, 0x0f, enable ? 1 : 0, 0x01);
  1766. }
  1767. #endif
  1768. /*
  1769. * r820t frontend operations and tuner attach code
  1770. *
  1771. * All driver locks and i2c control are only in this part of the code
  1772. */
  1773. static int r820t_init(struct dvb_frontend *fe)
  1774. {
  1775. struct r820t_priv *priv = fe->tuner_priv;
  1776. int rc;
  1777. tuner_dbg("%s:\n", __func__);
  1778. mutex_lock(&priv->lock);
  1779. if (fe->ops.i2c_gate_ctrl)
  1780. fe->ops.i2c_gate_ctrl(fe, 1);
  1781. rc = r820t_imr_callibrate(priv);
  1782. if (rc < 0)
  1783. goto err;
  1784. /* Initialize registers */
  1785. rc = r820t_write(priv, 0x05,
  1786. r820t_init_array, sizeof(r820t_init_array));
  1787. err:
  1788. if (fe->ops.i2c_gate_ctrl)
  1789. fe->ops.i2c_gate_ctrl(fe, 0);
  1790. mutex_unlock(&priv->lock);
  1791. if (rc < 0)
  1792. tuner_dbg("%s: failed=%d\n", __func__, rc);
  1793. return rc;
  1794. }
  1795. static int r820t_sleep(struct dvb_frontend *fe)
  1796. {
  1797. struct r820t_priv *priv = fe->tuner_priv;
  1798. int rc;
  1799. tuner_dbg("%s:\n", __func__);
  1800. mutex_lock(&priv->lock);
  1801. if (fe->ops.i2c_gate_ctrl)
  1802. fe->ops.i2c_gate_ctrl(fe, 1);
  1803. rc = r820t_standby(priv);
  1804. if (fe->ops.i2c_gate_ctrl)
  1805. fe->ops.i2c_gate_ctrl(fe, 0);
  1806. mutex_unlock(&priv->lock);
  1807. tuner_dbg("%s: failed=%d\n", __func__, rc);
  1808. return rc;
  1809. }
  1810. static int r820t_set_analog_freq(struct dvb_frontend *fe,
  1811. struct analog_parameters *p)
  1812. {
  1813. struct r820t_priv *priv = fe->tuner_priv;
  1814. unsigned bw;
  1815. int rc;
  1816. tuner_dbg("%s called\n", __func__);
  1817. /* if std is not defined, choose one */
  1818. if (!p->std)
  1819. p->std = V4L2_STD_MN;
  1820. if ((p->std == V4L2_STD_PAL_M) || (p->std == V4L2_STD_NTSC))
  1821. bw = 6;
  1822. else
  1823. bw = 8;
  1824. mutex_lock(&priv->lock);
  1825. if (fe->ops.i2c_gate_ctrl)
  1826. fe->ops.i2c_gate_ctrl(fe, 1);
  1827. rc = generic_set_freq(fe, 62500l * p->frequency, bw,
  1828. V4L2_TUNER_ANALOG_TV, p->std, SYS_UNDEFINED);
  1829. if (fe->ops.i2c_gate_ctrl)
  1830. fe->ops.i2c_gate_ctrl(fe, 0);
  1831. mutex_unlock(&priv->lock);
  1832. return rc;
  1833. }
  1834. static int r820t_set_params(struct dvb_frontend *fe)
  1835. {
  1836. struct r820t_priv *priv = fe->tuner_priv;
  1837. struct dtv_frontend_properties *c = &fe->dtv_property_cache;
  1838. int rc;
  1839. unsigned bw;
  1840. tuner_dbg("%s: delivery_system=%d frequency=%d bandwidth_hz=%d\n",
  1841. __func__, c->delivery_system, c->frequency, c->bandwidth_hz);
  1842. mutex_lock(&priv->lock);
  1843. if (fe->ops.i2c_gate_ctrl)
  1844. fe->ops.i2c_gate_ctrl(fe, 1);
  1845. bw = (c->bandwidth_hz + 500000) / 1000000;
  1846. if (!bw)
  1847. bw = 8;
  1848. rc = generic_set_freq(fe, c->frequency, bw,
  1849. V4L2_TUNER_DIGITAL_TV, 0, c->delivery_system);
  1850. if (fe->ops.i2c_gate_ctrl)
  1851. fe->ops.i2c_gate_ctrl(fe, 0);
  1852. mutex_unlock(&priv->lock);
  1853. if (rc)
  1854. tuner_dbg("%s: failed=%d\n", __func__, rc);
  1855. return rc;
  1856. }
  1857. static int r820t_signal(struct dvb_frontend *fe, u16 *strength)
  1858. {
  1859. struct r820t_priv *priv = fe->tuner_priv;
  1860. int rc = 0;
  1861. mutex_lock(&priv->lock);
  1862. if (fe->ops.i2c_gate_ctrl)
  1863. fe->ops.i2c_gate_ctrl(fe, 1);
  1864. if (priv->has_lock) {
  1865. rc = r820t_read_gain(priv);
  1866. if (rc < 0)
  1867. goto err;
  1868. /* A higher gain at LNA means a lower signal strength */
  1869. *strength = (45 - rc) << 4 | 0xff;
  1870. if (*strength == 0xff)
  1871. *strength = 0;
  1872. } else {
  1873. *strength = 0;
  1874. }
  1875. err:
  1876. if (fe->ops.i2c_gate_ctrl)
  1877. fe->ops.i2c_gate_ctrl(fe, 0);
  1878. mutex_unlock(&priv->lock);
  1879. tuner_dbg("%s: %s, gain=%d strength=%d\n",
  1880. __func__,
  1881. priv->has_lock ? "PLL locked" : "no signal",
  1882. rc, *strength);
  1883. return 0;
  1884. }
  1885. static int r820t_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
  1886. {
  1887. struct r820t_priv *priv = fe->tuner_priv;
  1888. tuner_dbg("%s:\n", __func__);
  1889. *frequency = priv->int_freq;
  1890. return 0;
  1891. }
  1892. static int r820t_release(struct dvb_frontend *fe)
  1893. {
  1894. struct r820t_priv *priv = fe->tuner_priv;
  1895. tuner_dbg("%s:\n", __func__);
  1896. mutex_lock(&r820t_list_mutex);
  1897. if (priv)
  1898. hybrid_tuner_release_state(priv);
  1899. mutex_unlock(&r820t_list_mutex);
  1900. fe->tuner_priv = NULL;
  1901. return 0;
  1902. }
  1903. static const struct dvb_tuner_ops r820t_tuner_ops = {
  1904. .info = {
  1905. .name = "Rafael Micro R820T",
  1906. .frequency_min = 42000000,
  1907. .frequency_max = 1002000000,
  1908. },
  1909. .init = r820t_init,
  1910. .release = r820t_release,
  1911. .sleep = r820t_sleep,
  1912. .set_params = r820t_set_params,
  1913. .set_analog_params = r820t_set_analog_freq,
  1914. .get_if_frequency = r820t_get_if_frequency,
  1915. .get_rf_strength = r820t_signal,
  1916. };
  1917. struct dvb_frontend *r820t_attach(struct dvb_frontend *fe,
  1918. struct i2c_adapter *i2c,
  1919. const struct r820t_config *cfg)
  1920. {
  1921. struct r820t_priv *priv;
  1922. int rc = -ENODEV;
  1923. u8 data[5];
  1924. int instance;
  1925. mutex_lock(&r820t_list_mutex);
  1926. instance = hybrid_tuner_request_state(struct r820t_priv, priv,
  1927. hybrid_tuner_instance_list,
  1928. i2c, cfg->i2c_addr,
  1929. "r820t");
  1930. switch (instance) {
  1931. case 0:
  1932. /* memory allocation failure */
  1933. goto err_no_gate;
  1934. break;
  1935. case 1:
  1936. /* new tuner instance */
  1937. priv->cfg = cfg;
  1938. mutex_init(&priv->lock);
  1939. fe->tuner_priv = priv;
  1940. break;
  1941. case 2:
  1942. /* existing tuner instance */
  1943. fe->tuner_priv = priv;
  1944. break;
  1945. }
  1946. if (fe->ops.i2c_gate_ctrl)
  1947. fe->ops.i2c_gate_ctrl(fe, 1);
  1948. /* check if the tuner is there */
  1949. rc = r820t_read(priv, 0x00, data, sizeof(data));
  1950. if (rc < 0)
  1951. goto err;
  1952. rc = r820t_sleep(fe);
  1953. if (rc < 0)
  1954. goto err;
  1955. tuner_info("Rafael Micro r820t successfully identified\n");
  1956. if (fe->ops.i2c_gate_ctrl)
  1957. fe->ops.i2c_gate_ctrl(fe, 0);
  1958. mutex_unlock(&r820t_list_mutex);
  1959. memcpy(&fe->ops.tuner_ops, &r820t_tuner_ops,
  1960. sizeof(struct dvb_tuner_ops));
  1961. return fe;
  1962. err:
  1963. if (fe->ops.i2c_gate_ctrl)
  1964. fe->ops.i2c_gate_ctrl(fe, 0);
  1965. err_no_gate:
  1966. mutex_unlock(&r820t_list_mutex);
  1967. tuner_info("%s: failed=%d\n", __func__, rc);
  1968. r820t_release(fe);
  1969. return NULL;
  1970. }
  1971. EXPORT_SYMBOL_GPL(r820t_attach);
  1972. MODULE_DESCRIPTION("Rafael Micro r820t silicon tuner driver");
  1973. MODULE_AUTHOR("Mauro Carvalho Chehab <mchehab@redhat.com>");
  1974. MODULE_LICENSE("GPL");