be_main.c 142 KB

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  1. /**
  2. * Copyright (C) 2005 - 2011 Emulex
  3. * All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License version 2
  7. * as published by the Free Software Foundation. The full GNU General
  8. * Public License is included in this distribution in the file called COPYING.
  9. *
  10. * Written by: Jayamohan Kallickal (jayamohan.kallickal@emulex.com)
  11. *
  12. * Contact Information:
  13. * linux-drivers@emulex.com
  14. *
  15. * Emulex
  16. * 3333 Susan Street
  17. * Costa Mesa, CA 92626
  18. */
  19. #include <linux/reboot.h>
  20. #include <linux/delay.h>
  21. #include <linux/slab.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/blkdev.h>
  24. #include <linux/pci.h>
  25. #include <linux/string.h>
  26. #include <linux/kernel.h>
  27. #include <linux/semaphore.h>
  28. #include <linux/iscsi_boot_sysfs.h>
  29. #include <linux/module.h>
  30. #include <linux/bsg-lib.h>
  31. #include <scsi/libiscsi.h>
  32. #include <scsi/scsi_bsg_iscsi.h>
  33. #include <scsi/scsi_netlink.h>
  34. #include <scsi/scsi_transport_iscsi.h>
  35. #include <scsi/scsi_transport.h>
  36. #include <scsi/scsi_cmnd.h>
  37. #include <scsi/scsi_device.h>
  38. #include <scsi/scsi_host.h>
  39. #include <scsi/scsi.h>
  40. #include "be_main.h"
  41. #include "be_iscsi.h"
  42. #include "be_mgmt.h"
  43. #include "be_cmds.h"
  44. static unsigned int be_iopoll_budget = 10;
  45. static unsigned int be_max_phys_size = 64;
  46. static unsigned int enable_msix = 1;
  47. MODULE_DEVICE_TABLE(pci, beiscsi_pci_id_table);
  48. MODULE_DESCRIPTION(DRV_DESC " " BUILD_STR);
  49. MODULE_VERSION(BUILD_STR);
  50. MODULE_AUTHOR("Emulex Corporation");
  51. MODULE_LICENSE("GPL");
  52. module_param(be_iopoll_budget, int, 0);
  53. module_param(enable_msix, int, 0);
  54. module_param(be_max_phys_size, uint, S_IRUGO);
  55. MODULE_PARM_DESC(be_max_phys_size,
  56. "Maximum Size (In Kilobytes) of physically contiguous "
  57. "memory that can be allocated. Range is 16 - 128");
  58. #define beiscsi_disp_param(_name)\
  59. ssize_t \
  60. beiscsi_##_name##_disp(struct device *dev,\
  61. struct device_attribute *attrib, char *buf) \
  62. { \
  63. struct Scsi_Host *shost = class_to_shost(dev);\
  64. struct beiscsi_hba *phba = iscsi_host_priv(shost); \
  65. uint32_t param_val = 0; \
  66. param_val = phba->attr_##_name;\
  67. return snprintf(buf, PAGE_SIZE, "%d\n",\
  68. phba->attr_##_name);\
  69. }
  70. #define beiscsi_change_param(_name, _minval, _maxval, _defaval)\
  71. int \
  72. beiscsi_##_name##_change(struct beiscsi_hba *phba, uint32_t val)\
  73. {\
  74. if (val >= _minval && val <= _maxval) {\
  75. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,\
  76. "BA_%d : beiscsi_"#_name" updated "\
  77. "from 0x%x ==> 0x%x\n",\
  78. phba->attr_##_name, val); \
  79. phba->attr_##_name = val;\
  80. return 0;\
  81. } \
  82. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT, \
  83. "BA_%d beiscsi_"#_name" attribute "\
  84. "cannot be updated to 0x%x, "\
  85. "range allowed is ["#_minval" - "#_maxval"]\n", val);\
  86. return -EINVAL;\
  87. }
  88. #define beiscsi_store_param(_name) \
  89. ssize_t \
  90. beiscsi_##_name##_store(struct device *dev,\
  91. struct device_attribute *attr, const char *buf,\
  92. size_t count) \
  93. { \
  94. struct Scsi_Host *shost = class_to_shost(dev);\
  95. struct beiscsi_hba *phba = iscsi_host_priv(shost);\
  96. uint32_t param_val = 0;\
  97. if (!isdigit(buf[0]))\
  98. return -EINVAL;\
  99. if (sscanf(buf, "%i", &param_val) != 1)\
  100. return -EINVAL;\
  101. if (beiscsi_##_name##_change(phba, param_val) == 0) \
  102. return strlen(buf);\
  103. else \
  104. return -EINVAL;\
  105. }
  106. #define beiscsi_init_param(_name, _minval, _maxval, _defval) \
  107. int \
  108. beiscsi_##_name##_init(struct beiscsi_hba *phba, uint32_t val) \
  109. { \
  110. if (val >= _minval && val <= _maxval) {\
  111. phba->attr_##_name = val;\
  112. return 0;\
  113. } \
  114. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,\
  115. "BA_%d beiscsi_"#_name" attribute " \
  116. "cannot be updated to 0x%x, "\
  117. "range allowed is ["#_minval" - "#_maxval"]\n", val);\
  118. phba->attr_##_name = _defval;\
  119. return -EINVAL;\
  120. }
  121. #define BEISCSI_RW_ATTR(_name, _minval, _maxval, _defval, _descp) \
  122. static uint beiscsi_##_name = _defval;\
  123. module_param(beiscsi_##_name, uint, S_IRUGO);\
  124. MODULE_PARM_DESC(beiscsi_##_name, _descp);\
  125. beiscsi_disp_param(_name)\
  126. beiscsi_change_param(_name, _minval, _maxval, _defval)\
  127. beiscsi_store_param(_name)\
  128. beiscsi_init_param(_name, _minval, _maxval, _defval)\
  129. DEVICE_ATTR(beiscsi_##_name, S_IRUGO | S_IWUSR,\
  130. beiscsi_##_name##_disp, beiscsi_##_name##_store)
  131. /*
  132. * When new log level added update the
  133. * the MAX allowed value for log_enable
  134. */
  135. BEISCSI_RW_ATTR(log_enable, 0x00,
  136. 0xFF, 0x00, "Enable logging Bit Mask\n"
  137. "\t\t\t\tInitialization Events : 0x01\n"
  138. "\t\t\t\tMailbox Events : 0x02\n"
  139. "\t\t\t\tMiscellaneous Events : 0x04\n"
  140. "\t\t\t\tError Handling : 0x08\n"
  141. "\t\t\t\tIO Path Events : 0x10\n"
  142. "\t\t\t\tConfiguration Path : 0x20\n");
  143. DEVICE_ATTR(beiscsi_drvr_ver, S_IRUGO, beiscsi_drvr_ver_disp, NULL);
  144. struct device_attribute *beiscsi_attrs[] = {
  145. &dev_attr_beiscsi_log_enable,
  146. &dev_attr_beiscsi_drvr_ver,
  147. NULL,
  148. };
  149. static char const *cqe_desc[] = {
  150. "RESERVED_DESC",
  151. "SOL_CMD_COMPLETE",
  152. "SOL_CMD_KILLED_DATA_DIGEST_ERR",
  153. "CXN_KILLED_PDU_SIZE_EXCEEDS_DSL",
  154. "CXN_KILLED_BURST_LEN_MISMATCH",
  155. "CXN_KILLED_AHS_RCVD",
  156. "CXN_KILLED_HDR_DIGEST_ERR",
  157. "CXN_KILLED_UNKNOWN_HDR",
  158. "CXN_KILLED_STALE_ITT_TTT_RCVD",
  159. "CXN_KILLED_INVALID_ITT_TTT_RCVD",
  160. "CXN_KILLED_RST_RCVD",
  161. "CXN_KILLED_TIMED_OUT",
  162. "CXN_KILLED_RST_SENT",
  163. "CXN_KILLED_FIN_RCVD",
  164. "CXN_KILLED_BAD_UNSOL_PDU_RCVD",
  165. "CXN_KILLED_BAD_WRB_INDEX_ERROR",
  166. "CXN_KILLED_OVER_RUN_RESIDUAL",
  167. "CXN_KILLED_UNDER_RUN_RESIDUAL",
  168. "CMD_KILLED_INVALID_STATSN_RCVD",
  169. "CMD_KILLED_INVALID_R2T_RCVD",
  170. "CMD_CXN_KILLED_LUN_INVALID",
  171. "CMD_CXN_KILLED_ICD_INVALID",
  172. "CMD_CXN_KILLED_ITT_INVALID",
  173. "CMD_CXN_KILLED_SEQ_OUTOFORDER",
  174. "CMD_CXN_KILLED_INVALID_DATASN_RCVD",
  175. "CXN_INVALIDATE_NOTIFY",
  176. "CXN_INVALIDATE_INDEX_NOTIFY",
  177. "CMD_INVALIDATED_NOTIFY",
  178. "UNSOL_HDR_NOTIFY",
  179. "UNSOL_DATA_NOTIFY",
  180. "UNSOL_DATA_DIGEST_ERROR_NOTIFY",
  181. "DRIVERMSG_NOTIFY",
  182. "CXN_KILLED_CMND_DATA_NOT_ON_SAME_CONN",
  183. "SOL_CMD_KILLED_DIF_ERR",
  184. "CXN_KILLED_SYN_RCVD",
  185. "CXN_KILLED_IMM_DATA_RCVD"
  186. };
  187. static int beiscsi_slave_configure(struct scsi_device *sdev)
  188. {
  189. blk_queue_max_segment_size(sdev->request_queue, 65536);
  190. return 0;
  191. }
  192. static int beiscsi_eh_abort(struct scsi_cmnd *sc)
  193. {
  194. struct iscsi_cls_session *cls_session;
  195. struct iscsi_task *aborted_task = (struct iscsi_task *)sc->SCp.ptr;
  196. struct beiscsi_io_task *aborted_io_task;
  197. struct iscsi_conn *conn;
  198. struct beiscsi_conn *beiscsi_conn;
  199. struct beiscsi_hba *phba;
  200. struct iscsi_session *session;
  201. struct invalidate_command_table *inv_tbl;
  202. struct be_dma_mem nonemb_cmd;
  203. unsigned int cid, tag, num_invalidate;
  204. cls_session = starget_to_session(scsi_target(sc->device));
  205. session = cls_session->dd_data;
  206. spin_lock_bh(&session->lock);
  207. if (!aborted_task || !aborted_task->sc) {
  208. /* we raced */
  209. spin_unlock_bh(&session->lock);
  210. return SUCCESS;
  211. }
  212. aborted_io_task = aborted_task->dd_data;
  213. if (!aborted_io_task->scsi_cmnd) {
  214. /* raced or invalid command */
  215. spin_unlock_bh(&session->lock);
  216. return SUCCESS;
  217. }
  218. spin_unlock_bh(&session->lock);
  219. conn = aborted_task->conn;
  220. beiscsi_conn = conn->dd_data;
  221. phba = beiscsi_conn->phba;
  222. /* invalidate iocb */
  223. cid = beiscsi_conn->beiscsi_conn_cid;
  224. inv_tbl = phba->inv_tbl;
  225. memset(inv_tbl, 0x0, sizeof(*inv_tbl));
  226. inv_tbl->cid = cid;
  227. inv_tbl->icd = aborted_io_task->psgl_handle->sgl_index;
  228. num_invalidate = 1;
  229. nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
  230. sizeof(struct invalidate_commands_params_in),
  231. &nonemb_cmd.dma);
  232. if (nonemb_cmd.va == NULL) {
  233. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_EH,
  234. "BM_%d : Failed to allocate memory for"
  235. "mgmt_invalidate_icds\n");
  236. return FAILED;
  237. }
  238. nonemb_cmd.size = sizeof(struct invalidate_commands_params_in);
  239. tag = mgmt_invalidate_icds(phba, inv_tbl, num_invalidate,
  240. cid, &nonemb_cmd);
  241. if (!tag) {
  242. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_EH,
  243. "BM_%d : mgmt_invalidate_icds could not be"
  244. "submitted\n");
  245. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  246. nonemb_cmd.va, nonemb_cmd.dma);
  247. return FAILED;
  248. } else {
  249. wait_event_interruptible(phba->ctrl.mcc_wait[tag],
  250. phba->ctrl.mcc_numtag[tag]);
  251. free_mcc_tag(&phba->ctrl, tag);
  252. }
  253. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  254. nonemb_cmd.va, nonemb_cmd.dma);
  255. return iscsi_eh_abort(sc);
  256. }
  257. static int beiscsi_eh_device_reset(struct scsi_cmnd *sc)
  258. {
  259. struct iscsi_task *abrt_task;
  260. struct beiscsi_io_task *abrt_io_task;
  261. struct iscsi_conn *conn;
  262. struct beiscsi_conn *beiscsi_conn;
  263. struct beiscsi_hba *phba;
  264. struct iscsi_session *session;
  265. struct iscsi_cls_session *cls_session;
  266. struct invalidate_command_table *inv_tbl;
  267. struct be_dma_mem nonemb_cmd;
  268. unsigned int cid, tag, i, num_invalidate;
  269. /* invalidate iocbs */
  270. cls_session = starget_to_session(scsi_target(sc->device));
  271. session = cls_session->dd_data;
  272. spin_lock_bh(&session->lock);
  273. if (!session->leadconn || session->state != ISCSI_STATE_LOGGED_IN) {
  274. spin_unlock_bh(&session->lock);
  275. return FAILED;
  276. }
  277. conn = session->leadconn;
  278. beiscsi_conn = conn->dd_data;
  279. phba = beiscsi_conn->phba;
  280. cid = beiscsi_conn->beiscsi_conn_cid;
  281. inv_tbl = phba->inv_tbl;
  282. memset(inv_tbl, 0x0, sizeof(*inv_tbl) * BE2_CMDS_PER_CXN);
  283. num_invalidate = 0;
  284. for (i = 0; i < conn->session->cmds_max; i++) {
  285. abrt_task = conn->session->cmds[i];
  286. abrt_io_task = abrt_task->dd_data;
  287. if (!abrt_task->sc || abrt_task->state == ISCSI_TASK_FREE)
  288. continue;
  289. if (abrt_task->sc->device->lun != abrt_task->sc->device->lun)
  290. continue;
  291. inv_tbl->cid = cid;
  292. inv_tbl->icd = abrt_io_task->psgl_handle->sgl_index;
  293. num_invalidate++;
  294. inv_tbl++;
  295. }
  296. spin_unlock_bh(&session->lock);
  297. inv_tbl = phba->inv_tbl;
  298. nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
  299. sizeof(struct invalidate_commands_params_in),
  300. &nonemb_cmd.dma);
  301. if (nonemb_cmd.va == NULL) {
  302. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_EH,
  303. "BM_%d : Failed to allocate memory for"
  304. "mgmt_invalidate_icds\n");
  305. return FAILED;
  306. }
  307. nonemb_cmd.size = sizeof(struct invalidate_commands_params_in);
  308. memset(nonemb_cmd.va, 0, nonemb_cmd.size);
  309. tag = mgmt_invalidate_icds(phba, inv_tbl, num_invalidate,
  310. cid, &nonemb_cmd);
  311. if (!tag) {
  312. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_EH,
  313. "BM_%d : mgmt_invalidate_icds could not be"
  314. " submitted\n");
  315. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  316. nonemb_cmd.va, nonemb_cmd.dma);
  317. return FAILED;
  318. } else {
  319. wait_event_interruptible(phba->ctrl.mcc_wait[tag],
  320. phba->ctrl.mcc_numtag[tag]);
  321. free_mcc_tag(&phba->ctrl, tag);
  322. }
  323. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  324. nonemb_cmd.va, nonemb_cmd.dma);
  325. return iscsi_eh_device_reset(sc);
  326. }
  327. static ssize_t beiscsi_show_boot_tgt_info(void *data, int type, char *buf)
  328. {
  329. struct beiscsi_hba *phba = data;
  330. struct mgmt_session_info *boot_sess = &phba->boot_sess;
  331. struct mgmt_conn_info *boot_conn = &boot_sess->conn_list[0];
  332. char *str = buf;
  333. int rc;
  334. switch (type) {
  335. case ISCSI_BOOT_TGT_NAME:
  336. rc = sprintf(buf, "%.*s\n",
  337. (int)strlen(boot_sess->target_name),
  338. (char *)&boot_sess->target_name);
  339. break;
  340. case ISCSI_BOOT_TGT_IP_ADDR:
  341. if (boot_conn->dest_ipaddr.ip_type == 0x1)
  342. rc = sprintf(buf, "%pI4\n",
  343. (char *)&boot_conn->dest_ipaddr.addr);
  344. else
  345. rc = sprintf(str, "%pI6\n",
  346. (char *)&boot_conn->dest_ipaddr.addr);
  347. break;
  348. case ISCSI_BOOT_TGT_PORT:
  349. rc = sprintf(str, "%d\n", boot_conn->dest_port);
  350. break;
  351. case ISCSI_BOOT_TGT_CHAP_NAME:
  352. rc = sprintf(str, "%.*s\n",
  353. boot_conn->negotiated_login_options.auth_data.chap.
  354. target_chap_name_length,
  355. (char *)&boot_conn->negotiated_login_options.
  356. auth_data.chap.target_chap_name);
  357. break;
  358. case ISCSI_BOOT_TGT_CHAP_SECRET:
  359. rc = sprintf(str, "%.*s\n",
  360. boot_conn->negotiated_login_options.auth_data.chap.
  361. target_secret_length,
  362. (char *)&boot_conn->negotiated_login_options.
  363. auth_data.chap.target_secret);
  364. break;
  365. case ISCSI_BOOT_TGT_REV_CHAP_NAME:
  366. rc = sprintf(str, "%.*s\n",
  367. boot_conn->negotiated_login_options.auth_data.chap.
  368. intr_chap_name_length,
  369. (char *)&boot_conn->negotiated_login_options.
  370. auth_data.chap.intr_chap_name);
  371. break;
  372. case ISCSI_BOOT_TGT_REV_CHAP_SECRET:
  373. rc = sprintf(str, "%.*s\n",
  374. boot_conn->negotiated_login_options.auth_data.chap.
  375. intr_secret_length,
  376. (char *)&boot_conn->negotiated_login_options.
  377. auth_data.chap.intr_secret);
  378. break;
  379. case ISCSI_BOOT_TGT_FLAGS:
  380. rc = sprintf(str, "2\n");
  381. break;
  382. case ISCSI_BOOT_TGT_NIC_ASSOC:
  383. rc = sprintf(str, "0\n");
  384. break;
  385. default:
  386. rc = -ENOSYS;
  387. break;
  388. }
  389. return rc;
  390. }
  391. static ssize_t beiscsi_show_boot_ini_info(void *data, int type, char *buf)
  392. {
  393. struct beiscsi_hba *phba = data;
  394. char *str = buf;
  395. int rc;
  396. switch (type) {
  397. case ISCSI_BOOT_INI_INITIATOR_NAME:
  398. rc = sprintf(str, "%s\n", phba->boot_sess.initiator_iscsiname);
  399. break;
  400. default:
  401. rc = -ENOSYS;
  402. break;
  403. }
  404. return rc;
  405. }
  406. static ssize_t beiscsi_show_boot_eth_info(void *data, int type, char *buf)
  407. {
  408. struct beiscsi_hba *phba = data;
  409. char *str = buf;
  410. int rc;
  411. switch (type) {
  412. case ISCSI_BOOT_ETH_FLAGS:
  413. rc = sprintf(str, "2\n");
  414. break;
  415. case ISCSI_BOOT_ETH_INDEX:
  416. rc = sprintf(str, "0\n");
  417. break;
  418. case ISCSI_BOOT_ETH_MAC:
  419. rc = beiscsi_get_macaddr(str, phba);
  420. break;
  421. default:
  422. rc = -ENOSYS;
  423. break;
  424. }
  425. return rc;
  426. }
  427. static umode_t beiscsi_tgt_get_attr_visibility(void *data, int type)
  428. {
  429. umode_t rc;
  430. switch (type) {
  431. case ISCSI_BOOT_TGT_NAME:
  432. case ISCSI_BOOT_TGT_IP_ADDR:
  433. case ISCSI_BOOT_TGT_PORT:
  434. case ISCSI_BOOT_TGT_CHAP_NAME:
  435. case ISCSI_BOOT_TGT_CHAP_SECRET:
  436. case ISCSI_BOOT_TGT_REV_CHAP_NAME:
  437. case ISCSI_BOOT_TGT_REV_CHAP_SECRET:
  438. case ISCSI_BOOT_TGT_NIC_ASSOC:
  439. case ISCSI_BOOT_TGT_FLAGS:
  440. rc = S_IRUGO;
  441. break;
  442. default:
  443. rc = 0;
  444. break;
  445. }
  446. return rc;
  447. }
  448. static umode_t beiscsi_ini_get_attr_visibility(void *data, int type)
  449. {
  450. umode_t rc;
  451. switch (type) {
  452. case ISCSI_BOOT_INI_INITIATOR_NAME:
  453. rc = S_IRUGO;
  454. break;
  455. default:
  456. rc = 0;
  457. break;
  458. }
  459. return rc;
  460. }
  461. static umode_t beiscsi_eth_get_attr_visibility(void *data, int type)
  462. {
  463. umode_t rc;
  464. switch (type) {
  465. case ISCSI_BOOT_ETH_FLAGS:
  466. case ISCSI_BOOT_ETH_MAC:
  467. case ISCSI_BOOT_ETH_INDEX:
  468. rc = S_IRUGO;
  469. break;
  470. default:
  471. rc = 0;
  472. break;
  473. }
  474. return rc;
  475. }
  476. /*------------------- PCI Driver operations and data ----------------- */
  477. static DEFINE_PCI_DEVICE_TABLE(beiscsi_pci_id_table) = {
  478. { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID1) },
  479. { PCI_DEVICE(BE_VENDOR_ID, BE_DEVICE_ID2) },
  480. { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID1) },
  481. { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID2) },
  482. { PCI_DEVICE(BE_VENDOR_ID, OC_DEVICE_ID3) },
  483. { PCI_DEVICE(ELX_VENDOR_ID, OC_SKH_ID1) },
  484. { 0 }
  485. };
  486. MODULE_DEVICE_TABLE(pci, beiscsi_pci_id_table);
  487. static struct scsi_host_template beiscsi_sht = {
  488. .module = THIS_MODULE,
  489. .name = "Emulex 10Gbe open-iscsi Initiator Driver",
  490. .proc_name = DRV_NAME,
  491. .queuecommand = iscsi_queuecommand,
  492. .change_queue_depth = iscsi_change_queue_depth,
  493. .slave_configure = beiscsi_slave_configure,
  494. .target_alloc = iscsi_target_alloc,
  495. .eh_abort_handler = beiscsi_eh_abort,
  496. .eh_device_reset_handler = beiscsi_eh_device_reset,
  497. .eh_target_reset_handler = iscsi_eh_session_reset,
  498. .shost_attrs = beiscsi_attrs,
  499. .sg_tablesize = BEISCSI_SGLIST_ELEMENTS,
  500. .can_queue = BE2_IO_DEPTH,
  501. .this_id = -1,
  502. .max_sectors = BEISCSI_MAX_SECTORS,
  503. .cmd_per_lun = BEISCSI_CMD_PER_LUN,
  504. .use_clustering = ENABLE_CLUSTERING,
  505. .vendor_id = SCSI_NL_VID_TYPE_PCI | BE_VENDOR_ID,
  506. };
  507. static struct scsi_transport_template *beiscsi_scsi_transport;
  508. static struct beiscsi_hba *beiscsi_hba_alloc(struct pci_dev *pcidev)
  509. {
  510. struct beiscsi_hba *phba;
  511. struct Scsi_Host *shost;
  512. shost = iscsi_host_alloc(&beiscsi_sht, sizeof(*phba), 0);
  513. if (!shost) {
  514. dev_err(&pcidev->dev,
  515. "beiscsi_hba_alloc - iscsi_host_alloc failed\n");
  516. return NULL;
  517. }
  518. shost->dma_boundary = pcidev->dma_mask;
  519. shost->max_id = BE2_MAX_SESSIONS;
  520. shost->max_channel = 0;
  521. shost->max_cmd_len = BEISCSI_MAX_CMD_LEN;
  522. shost->max_lun = BEISCSI_NUM_MAX_LUN;
  523. shost->transportt = beiscsi_scsi_transport;
  524. phba = iscsi_host_priv(shost);
  525. memset(phba, 0, sizeof(*phba));
  526. phba->shost = shost;
  527. phba->pcidev = pci_dev_get(pcidev);
  528. pci_set_drvdata(pcidev, phba);
  529. phba->interface_handle = 0xFFFFFFFF;
  530. if (iscsi_host_add(shost, &phba->pcidev->dev))
  531. goto free_devices;
  532. return phba;
  533. free_devices:
  534. pci_dev_put(phba->pcidev);
  535. iscsi_host_free(phba->shost);
  536. return NULL;
  537. }
  538. static void beiscsi_unmap_pci_function(struct beiscsi_hba *phba)
  539. {
  540. if (phba->csr_va) {
  541. iounmap(phba->csr_va);
  542. phba->csr_va = NULL;
  543. }
  544. if (phba->db_va) {
  545. iounmap(phba->db_va);
  546. phba->db_va = NULL;
  547. }
  548. if (phba->pci_va) {
  549. iounmap(phba->pci_va);
  550. phba->pci_va = NULL;
  551. }
  552. }
  553. static int beiscsi_map_pci_bars(struct beiscsi_hba *phba,
  554. struct pci_dev *pcidev)
  555. {
  556. u8 __iomem *addr;
  557. int pcicfg_reg;
  558. addr = ioremap_nocache(pci_resource_start(pcidev, 2),
  559. pci_resource_len(pcidev, 2));
  560. if (addr == NULL)
  561. return -ENOMEM;
  562. phba->ctrl.csr = addr;
  563. phba->csr_va = addr;
  564. phba->csr_pa.u.a64.address = pci_resource_start(pcidev, 2);
  565. addr = ioremap_nocache(pci_resource_start(pcidev, 4), 128 * 1024);
  566. if (addr == NULL)
  567. goto pci_map_err;
  568. phba->ctrl.db = addr;
  569. phba->db_va = addr;
  570. phba->db_pa.u.a64.address = pci_resource_start(pcidev, 4);
  571. if (phba->generation == BE_GEN2)
  572. pcicfg_reg = 1;
  573. else
  574. pcicfg_reg = 0;
  575. addr = ioremap_nocache(pci_resource_start(pcidev, pcicfg_reg),
  576. pci_resource_len(pcidev, pcicfg_reg));
  577. if (addr == NULL)
  578. goto pci_map_err;
  579. phba->ctrl.pcicfg = addr;
  580. phba->pci_va = addr;
  581. phba->pci_pa.u.a64.address = pci_resource_start(pcidev, pcicfg_reg);
  582. return 0;
  583. pci_map_err:
  584. beiscsi_unmap_pci_function(phba);
  585. return -ENOMEM;
  586. }
  587. static int beiscsi_enable_pci(struct pci_dev *pcidev)
  588. {
  589. int ret;
  590. ret = pci_enable_device(pcidev);
  591. if (ret) {
  592. dev_err(&pcidev->dev,
  593. "beiscsi_enable_pci - enable device failed\n");
  594. return ret;
  595. }
  596. pci_set_master(pcidev);
  597. if (pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(64))) {
  598. ret = pci_set_consistent_dma_mask(pcidev, DMA_BIT_MASK(32));
  599. if (ret) {
  600. dev_err(&pcidev->dev, "Could not set PCI DMA Mask\n");
  601. pci_disable_device(pcidev);
  602. return ret;
  603. }
  604. }
  605. return 0;
  606. }
  607. static int be_ctrl_init(struct beiscsi_hba *phba, struct pci_dev *pdev)
  608. {
  609. struct be_ctrl_info *ctrl = &phba->ctrl;
  610. struct be_dma_mem *mbox_mem_alloc = &ctrl->mbox_mem_alloced;
  611. struct be_dma_mem *mbox_mem_align = &ctrl->mbox_mem;
  612. int status = 0;
  613. ctrl->pdev = pdev;
  614. status = beiscsi_map_pci_bars(phba, pdev);
  615. if (status)
  616. return status;
  617. mbox_mem_alloc->size = sizeof(struct be_mcc_mailbox) + 16;
  618. mbox_mem_alloc->va = pci_alloc_consistent(pdev,
  619. mbox_mem_alloc->size,
  620. &mbox_mem_alloc->dma);
  621. if (!mbox_mem_alloc->va) {
  622. beiscsi_unmap_pci_function(phba);
  623. return -ENOMEM;
  624. }
  625. mbox_mem_align->size = sizeof(struct be_mcc_mailbox);
  626. mbox_mem_align->va = PTR_ALIGN(mbox_mem_alloc->va, 16);
  627. mbox_mem_align->dma = PTR_ALIGN(mbox_mem_alloc->dma, 16);
  628. memset(mbox_mem_align->va, 0, sizeof(struct be_mcc_mailbox));
  629. spin_lock_init(&ctrl->mbox_lock);
  630. spin_lock_init(&phba->ctrl.mcc_lock);
  631. spin_lock_init(&phba->ctrl.mcc_cq_lock);
  632. return status;
  633. }
  634. static void beiscsi_get_params(struct beiscsi_hba *phba)
  635. {
  636. phba->params.ios_per_ctrl = (phba->fw_config.iscsi_icd_count
  637. - (phba->fw_config.iscsi_cid_count
  638. + BE2_TMFS
  639. + BE2_NOPOUT_REQ));
  640. phba->params.cxns_per_ctrl = phba->fw_config.iscsi_cid_count;
  641. phba->params.asyncpdus_per_ctrl = phba->fw_config.iscsi_cid_count * 2;
  642. phba->params.icds_per_ctrl = phba->fw_config.iscsi_icd_count;
  643. phba->params.num_sge_per_io = BE2_SGE;
  644. phba->params.defpdu_hdr_sz = BE2_DEFPDU_HDR_SZ;
  645. phba->params.defpdu_data_sz = BE2_DEFPDU_DATA_SZ;
  646. phba->params.eq_timer = 64;
  647. phba->params.num_eq_entries =
  648. (((BE2_CMDS_PER_CXN * 2 + phba->fw_config.iscsi_cid_count * 2
  649. + BE2_TMFS) / 512) + 1) * 512;
  650. phba->params.num_eq_entries = (phba->params.num_eq_entries < 1024)
  651. ? 1024 : phba->params.num_eq_entries;
  652. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  653. "BM_%d : phba->params.num_eq_entries=%d\n",
  654. phba->params.num_eq_entries);
  655. phba->params.num_cq_entries =
  656. (((BE2_CMDS_PER_CXN * 2 + phba->fw_config.iscsi_cid_count * 2
  657. + BE2_TMFS) / 512) + 1) * 512;
  658. phba->params.wrbs_per_cxn = 256;
  659. }
  660. static void hwi_ring_eq_db(struct beiscsi_hba *phba,
  661. unsigned int id, unsigned int clr_interrupt,
  662. unsigned int num_processed,
  663. unsigned char rearm, unsigned char event)
  664. {
  665. u32 val = 0;
  666. val |= id & DB_EQ_RING_ID_MASK;
  667. if (rearm)
  668. val |= 1 << DB_EQ_REARM_SHIFT;
  669. if (clr_interrupt)
  670. val |= 1 << DB_EQ_CLR_SHIFT;
  671. if (event)
  672. val |= 1 << DB_EQ_EVNT_SHIFT;
  673. val |= num_processed << DB_EQ_NUM_POPPED_SHIFT;
  674. iowrite32(val, phba->db_va + DB_EQ_OFFSET);
  675. }
  676. /**
  677. * be_isr_mcc - The isr routine of the driver.
  678. * @irq: Not used
  679. * @dev_id: Pointer to host adapter structure
  680. */
  681. static irqreturn_t be_isr_mcc(int irq, void *dev_id)
  682. {
  683. struct beiscsi_hba *phba;
  684. struct be_eq_entry *eqe = NULL;
  685. struct be_queue_info *eq;
  686. struct be_queue_info *mcc;
  687. unsigned int num_eq_processed;
  688. struct be_eq_obj *pbe_eq;
  689. unsigned long flags;
  690. pbe_eq = dev_id;
  691. eq = &pbe_eq->q;
  692. phba = pbe_eq->phba;
  693. mcc = &phba->ctrl.mcc_obj.cq;
  694. eqe = queue_tail_node(eq);
  695. num_eq_processed = 0;
  696. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  697. & EQE_VALID_MASK) {
  698. if (((eqe->dw[offsetof(struct amap_eq_entry,
  699. resource_id) / 32] &
  700. EQE_RESID_MASK) >> 16) == mcc->id) {
  701. spin_lock_irqsave(&phba->isr_lock, flags);
  702. pbe_eq->todo_mcc_cq = true;
  703. spin_unlock_irqrestore(&phba->isr_lock, flags);
  704. }
  705. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  706. queue_tail_inc(eq);
  707. eqe = queue_tail_node(eq);
  708. num_eq_processed++;
  709. }
  710. if (pbe_eq->todo_mcc_cq)
  711. queue_work(phba->wq, &pbe_eq->work_cqs);
  712. if (num_eq_processed)
  713. hwi_ring_eq_db(phba, eq->id, 1, num_eq_processed, 1, 1);
  714. return IRQ_HANDLED;
  715. }
  716. /**
  717. * be_isr_msix - The isr routine of the driver.
  718. * @irq: Not used
  719. * @dev_id: Pointer to host adapter structure
  720. */
  721. static irqreturn_t be_isr_msix(int irq, void *dev_id)
  722. {
  723. struct beiscsi_hba *phba;
  724. struct be_eq_entry *eqe = NULL;
  725. struct be_queue_info *eq;
  726. struct be_queue_info *cq;
  727. unsigned int num_eq_processed;
  728. struct be_eq_obj *pbe_eq;
  729. unsigned long flags;
  730. pbe_eq = dev_id;
  731. eq = &pbe_eq->q;
  732. cq = pbe_eq->cq;
  733. eqe = queue_tail_node(eq);
  734. phba = pbe_eq->phba;
  735. num_eq_processed = 0;
  736. if (blk_iopoll_enabled) {
  737. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  738. & EQE_VALID_MASK) {
  739. if (!blk_iopoll_sched_prep(&pbe_eq->iopoll))
  740. blk_iopoll_sched(&pbe_eq->iopoll);
  741. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  742. queue_tail_inc(eq);
  743. eqe = queue_tail_node(eq);
  744. num_eq_processed++;
  745. }
  746. } else {
  747. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  748. & EQE_VALID_MASK) {
  749. spin_lock_irqsave(&phba->isr_lock, flags);
  750. pbe_eq->todo_cq = true;
  751. spin_unlock_irqrestore(&phba->isr_lock, flags);
  752. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  753. queue_tail_inc(eq);
  754. eqe = queue_tail_node(eq);
  755. num_eq_processed++;
  756. }
  757. if (pbe_eq->todo_cq)
  758. queue_work(phba->wq, &pbe_eq->work_cqs);
  759. }
  760. if (num_eq_processed)
  761. hwi_ring_eq_db(phba, eq->id, 1, num_eq_processed, 0, 1);
  762. return IRQ_HANDLED;
  763. }
  764. /**
  765. * be_isr - The isr routine of the driver.
  766. * @irq: Not used
  767. * @dev_id: Pointer to host adapter structure
  768. */
  769. static irqreturn_t be_isr(int irq, void *dev_id)
  770. {
  771. struct beiscsi_hba *phba;
  772. struct hwi_controller *phwi_ctrlr;
  773. struct hwi_context_memory *phwi_context;
  774. struct be_eq_entry *eqe = NULL;
  775. struct be_queue_info *eq;
  776. struct be_queue_info *cq;
  777. struct be_queue_info *mcc;
  778. unsigned long flags, index;
  779. unsigned int num_mcceq_processed, num_ioeq_processed;
  780. struct be_ctrl_info *ctrl;
  781. struct be_eq_obj *pbe_eq;
  782. int isr;
  783. phba = dev_id;
  784. ctrl = &phba->ctrl;
  785. isr = ioread32(ctrl->csr + CEV_ISR0_OFFSET +
  786. (PCI_FUNC(ctrl->pdev->devfn) * CEV_ISR_SIZE));
  787. if (!isr)
  788. return IRQ_NONE;
  789. phwi_ctrlr = phba->phwi_ctrlr;
  790. phwi_context = phwi_ctrlr->phwi_ctxt;
  791. pbe_eq = &phwi_context->be_eq[0];
  792. eq = &phwi_context->be_eq[0].q;
  793. mcc = &phba->ctrl.mcc_obj.cq;
  794. index = 0;
  795. eqe = queue_tail_node(eq);
  796. num_ioeq_processed = 0;
  797. num_mcceq_processed = 0;
  798. if (blk_iopoll_enabled) {
  799. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  800. & EQE_VALID_MASK) {
  801. if (((eqe->dw[offsetof(struct amap_eq_entry,
  802. resource_id) / 32] &
  803. EQE_RESID_MASK) >> 16) == mcc->id) {
  804. spin_lock_irqsave(&phba->isr_lock, flags);
  805. pbe_eq->todo_mcc_cq = true;
  806. spin_unlock_irqrestore(&phba->isr_lock, flags);
  807. num_mcceq_processed++;
  808. } else {
  809. if (!blk_iopoll_sched_prep(&pbe_eq->iopoll))
  810. blk_iopoll_sched(&pbe_eq->iopoll);
  811. num_ioeq_processed++;
  812. }
  813. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  814. queue_tail_inc(eq);
  815. eqe = queue_tail_node(eq);
  816. }
  817. if (num_ioeq_processed || num_mcceq_processed) {
  818. if (pbe_eq->todo_mcc_cq)
  819. queue_work(phba->wq, &pbe_eq->work_cqs);
  820. if ((num_mcceq_processed) && (!num_ioeq_processed))
  821. hwi_ring_eq_db(phba, eq->id, 0,
  822. (num_ioeq_processed +
  823. num_mcceq_processed) , 1, 1);
  824. else
  825. hwi_ring_eq_db(phba, eq->id, 0,
  826. (num_ioeq_processed +
  827. num_mcceq_processed), 0, 1);
  828. return IRQ_HANDLED;
  829. } else
  830. return IRQ_NONE;
  831. } else {
  832. cq = &phwi_context->be_cq[0];
  833. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  834. & EQE_VALID_MASK) {
  835. if (((eqe->dw[offsetof(struct amap_eq_entry,
  836. resource_id) / 32] &
  837. EQE_RESID_MASK) >> 16) != cq->id) {
  838. spin_lock_irqsave(&phba->isr_lock, flags);
  839. pbe_eq->todo_mcc_cq = true;
  840. spin_unlock_irqrestore(&phba->isr_lock, flags);
  841. } else {
  842. spin_lock_irqsave(&phba->isr_lock, flags);
  843. pbe_eq->todo_cq = true;
  844. spin_unlock_irqrestore(&phba->isr_lock, flags);
  845. }
  846. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  847. queue_tail_inc(eq);
  848. eqe = queue_tail_node(eq);
  849. num_ioeq_processed++;
  850. }
  851. if (pbe_eq->todo_cq || pbe_eq->todo_mcc_cq)
  852. queue_work(phba->wq, &pbe_eq->work_cqs);
  853. if (num_ioeq_processed) {
  854. hwi_ring_eq_db(phba, eq->id, 0,
  855. num_ioeq_processed, 1, 1);
  856. return IRQ_HANDLED;
  857. } else
  858. return IRQ_NONE;
  859. }
  860. }
  861. static int beiscsi_init_irqs(struct beiscsi_hba *phba)
  862. {
  863. struct pci_dev *pcidev = phba->pcidev;
  864. struct hwi_controller *phwi_ctrlr;
  865. struct hwi_context_memory *phwi_context;
  866. int ret, msix_vec, i, j;
  867. phwi_ctrlr = phba->phwi_ctrlr;
  868. phwi_context = phwi_ctrlr->phwi_ctxt;
  869. if (phba->msix_enabled) {
  870. for (i = 0; i < phba->num_cpus; i++) {
  871. phba->msi_name[i] = kzalloc(BEISCSI_MSI_NAME,
  872. GFP_KERNEL);
  873. if (!phba->msi_name[i]) {
  874. ret = -ENOMEM;
  875. goto free_msix_irqs;
  876. }
  877. sprintf(phba->msi_name[i], "beiscsi_%02x_%02x",
  878. phba->shost->host_no, i);
  879. msix_vec = phba->msix_entries[i].vector;
  880. ret = request_irq(msix_vec, be_isr_msix, 0,
  881. phba->msi_name[i],
  882. &phwi_context->be_eq[i]);
  883. if (ret) {
  884. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  885. "BM_%d : beiscsi_init_irqs-Failed to"
  886. "register msix for i = %d\n",
  887. i);
  888. kfree(phba->msi_name[i]);
  889. goto free_msix_irqs;
  890. }
  891. }
  892. phba->msi_name[i] = kzalloc(BEISCSI_MSI_NAME, GFP_KERNEL);
  893. if (!phba->msi_name[i]) {
  894. ret = -ENOMEM;
  895. goto free_msix_irqs;
  896. }
  897. sprintf(phba->msi_name[i], "beiscsi_mcc_%02x",
  898. phba->shost->host_no);
  899. msix_vec = phba->msix_entries[i].vector;
  900. ret = request_irq(msix_vec, be_isr_mcc, 0, phba->msi_name[i],
  901. &phwi_context->be_eq[i]);
  902. if (ret) {
  903. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT ,
  904. "BM_%d : beiscsi_init_irqs-"
  905. "Failed to register beiscsi_msix_mcc\n");
  906. kfree(phba->msi_name[i]);
  907. goto free_msix_irqs;
  908. }
  909. } else {
  910. ret = request_irq(pcidev->irq, be_isr, IRQF_SHARED,
  911. "beiscsi", phba);
  912. if (ret) {
  913. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  914. "BM_%d : beiscsi_init_irqs-"
  915. "Failed to register irq\\n");
  916. return ret;
  917. }
  918. }
  919. return 0;
  920. free_msix_irqs:
  921. for (j = i - 1; j >= 0; j--) {
  922. kfree(phba->msi_name[j]);
  923. msix_vec = phba->msix_entries[j].vector;
  924. free_irq(msix_vec, &phwi_context->be_eq[j]);
  925. }
  926. return ret;
  927. }
  928. static void hwi_ring_cq_db(struct beiscsi_hba *phba,
  929. unsigned int id, unsigned int num_processed,
  930. unsigned char rearm, unsigned char event)
  931. {
  932. u32 val = 0;
  933. val |= id & DB_CQ_RING_ID_MASK;
  934. if (rearm)
  935. val |= 1 << DB_CQ_REARM_SHIFT;
  936. val |= num_processed << DB_CQ_NUM_POPPED_SHIFT;
  937. iowrite32(val, phba->db_va + DB_CQ_OFFSET);
  938. }
  939. static unsigned int
  940. beiscsi_process_async_pdu(struct beiscsi_conn *beiscsi_conn,
  941. struct beiscsi_hba *phba,
  942. unsigned short cid,
  943. struct pdu_base *ppdu,
  944. unsigned long pdu_len,
  945. void *pbuffer, unsigned long buf_len)
  946. {
  947. struct iscsi_conn *conn = beiscsi_conn->conn;
  948. struct iscsi_session *session = conn->session;
  949. struct iscsi_task *task;
  950. struct beiscsi_io_task *io_task;
  951. struct iscsi_hdr *login_hdr;
  952. switch (ppdu->dw[offsetof(struct amap_pdu_base, opcode) / 32] &
  953. PDUBASE_OPCODE_MASK) {
  954. case ISCSI_OP_NOOP_IN:
  955. pbuffer = NULL;
  956. buf_len = 0;
  957. break;
  958. case ISCSI_OP_ASYNC_EVENT:
  959. break;
  960. case ISCSI_OP_REJECT:
  961. WARN_ON(!pbuffer);
  962. WARN_ON(!(buf_len == 48));
  963. beiscsi_log(phba, KERN_ERR,
  964. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  965. "BM_%d : In ISCSI_OP_REJECT\n");
  966. break;
  967. case ISCSI_OP_LOGIN_RSP:
  968. case ISCSI_OP_TEXT_RSP:
  969. task = conn->login_task;
  970. io_task = task->dd_data;
  971. login_hdr = (struct iscsi_hdr *)ppdu;
  972. login_hdr->itt = io_task->libiscsi_itt;
  973. break;
  974. default:
  975. beiscsi_log(phba, KERN_WARNING,
  976. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  977. "BM_%d : Unrecognized opcode 0x%x in async msg\n",
  978. (ppdu->
  979. dw[offsetof(struct amap_pdu_base, opcode) / 32]
  980. & PDUBASE_OPCODE_MASK));
  981. return 1;
  982. }
  983. spin_lock_bh(&session->lock);
  984. __iscsi_complete_pdu(conn, (struct iscsi_hdr *)ppdu, pbuffer, buf_len);
  985. spin_unlock_bh(&session->lock);
  986. return 0;
  987. }
  988. static struct sgl_handle *alloc_io_sgl_handle(struct beiscsi_hba *phba)
  989. {
  990. struct sgl_handle *psgl_handle;
  991. if (phba->io_sgl_hndl_avbl) {
  992. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_IO,
  993. "BM_%d : In alloc_io_sgl_handle,"
  994. " io_sgl_alloc_index=%d\n",
  995. phba->io_sgl_alloc_index);
  996. psgl_handle = phba->io_sgl_hndl_base[phba->
  997. io_sgl_alloc_index];
  998. phba->io_sgl_hndl_base[phba->io_sgl_alloc_index] = NULL;
  999. phba->io_sgl_hndl_avbl--;
  1000. if (phba->io_sgl_alloc_index == (phba->params.
  1001. ios_per_ctrl - 1))
  1002. phba->io_sgl_alloc_index = 0;
  1003. else
  1004. phba->io_sgl_alloc_index++;
  1005. } else
  1006. psgl_handle = NULL;
  1007. return psgl_handle;
  1008. }
  1009. static void
  1010. free_io_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle)
  1011. {
  1012. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_IO,
  1013. "BM_%d : In free_,io_sgl_free_index=%d\n",
  1014. phba->io_sgl_free_index);
  1015. if (phba->io_sgl_hndl_base[phba->io_sgl_free_index]) {
  1016. /*
  1017. * this can happen if clean_task is called on a task that
  1018. * failed in xmit_task or alloc_pdu.
  1019. */
  1020. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_IO,
  1021. "BM_%d : Double Free in IO SGL io_sgl_free_index=%d,"
  1022. "value there=%p\n", phba->io_sgl_free_index,
  1023. phba->io_sgl_hndl_base
  1024. [phba->io_sgl_free_index]);
  1025. return;
  1026. }
  1027. phba->io_sgl_hndl_base[phba->io_sgl_free_index] = psgl_handle;
  1028. phba->io_sgl_hndl_avbl++;
  1029. if (phba->io_sgl_free_index == (phba->params.ios_per_ctrl - 1))
  1030. phba->io_sgl_free_index = 0;
  1031. else
  1032. phba->io_sgl_free_index++;
  1033. }
  1034. /**
  1035. * alloc_wrb_handle - To allocate a wrb handle
  1036. * @phba: The hba pointer
  1037. * @cid: The cid to use for allocation
  1038. *
  1039. * This happens under session_lock until submission to chip
  1040. */
  1041. struct wrb_handle *alloc_wrb_handle(struct beiscsi_hba *phba, unsigned int cid)
  1042. {
  1043. struct hwi_wrb_context *pwrb_context;
  1044. struct hwi_controller *phwi_ctrlr;
  1045. struct wrb_handle *pwrb_handle, *pwrb_handle_tmp;
  1046. phwi_ctrlr = phba->phwi_ctrlr;
  1047. pwrb_context = &phwi_ctrlr->wrb_context[cid];
  1048. if (pwrb_context->wrb_handles_available >= 2) {
  1049. pwrb_handle = pwrb_context->pwrb_handle_base[
  1050. pwrb_context->alloc_index];
  1051. pwrb_context->wrb_handles_available--;
  1052. if (pwrb_context->alloc_index ==
  1053. (phba->params.wrbs_per_cxn - 1))
  1054. pwrb_context->alloc_index = 0;
  1055. else
  1056. pwrb_context->alloc_index++;
  1057. pwrb_handle_tmp = pwrb_context->pwrb_handle_base[
  1058. pwrb_context->alloc_index];
  1059. pwrb_handle->nxt_wrb_index = pwrb_handle_tmp->wrb_index;
  1060. } else
  1061. pwrb_handle = NULL;
  1062. return pwrb_handle;
  1063. }
  1064. /**
  1065. * free_wrb_handle - To free the wrb handle back to pool
  1066. * @phba: The hba pointer
  1067. * @pwrb_context: The context to free from
  1068. * @pwrb_handle: The wrb_handle to free
  1069. *
  1070. * This happens under session_lock until submission to chip
  1071. */
  1072. static void
  1073. free_wrb_handle(struct beiscsi_hba *phba, struct hwi_wrb_context *pwrb_context,
  1074. struct wrb_handle *pwrb_handle)
  1075. {
  1076. pwrb_context->pwrb_handle_base[pwrb_context->free_index] = pwrb_handle;
  1077. pwrb_context->wrb_handles_available++;
  1078. if (pwrb_context->free_index == (phba->params.wrbs_per_cxn - 1))
  1079. pwrb_context->free_index = 0;
  1080. else
  1081. pwrb_context->free_index++;
  1082. beiscsi_log(phba, KERN_INFO,
  1083. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1084. "BM_%d : FREE WRB: pwrb_handle=%p free_index=0x%x"
  1085. "wrb_handles_available=%d\n",
  1086. pwrb_handle, pwrb_context->free_index,
  1087. pwrb_context->wrb_handles_available);
  1088. }
  1089. static struct sgl_handle *alloc_mgmt_sgl_handle(struct beiscsi_hba *phba)
  1090. {
  1091. struct sgl_handle *psgl_handle;
  1092. if (phba->eh_sgl_hndl_avbl) {
  1093. psgl_handle = phba->eh_sgl_hndl_base[phba->eh_sgl_alloc_index];
  1094. phba->eh_sgl_hndl_base[phba->eh_sgl_alloc_index] = NULL;
  1095. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_CONFIG,
  1096. "BM_%d : mgmt_sgl_alloc_index=%d=0x%x\n",
  1097. phba->eh_sgl_alloc_index,
  1098. phba->eh_sgl_alloc_index);
  1099. phba->eh_sgl_hndl_avbl--;
  1100. if (phba->eh_sgl_alloc_index ==
  1101. (phba->params.icds_per_ctrl - phba->params.ios_per_ctrl -
  1102. 1))
  1103. phba->eh_sgl_alloc_index = 0;
  1104. else
  1105. phba->eh_sgl_alloc_index++;
  1106. } else
  1107. psgl_handle = NULL;
  1108. return psgl_handle;
  1109. }
  1110. void
  1111. free_mgmt_sgl_handle(struct beiscsi_hba *phba, struct sgl_handle *psgl_handle)
  1112. {
  1113. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_CONFIG,
  1114. "BM_%d : In free_mgmt_sgl_handle,"
  1115. "eh_sgl_free_index=%d\n",
  1116. phba->eh_sgl_free_index);
  1117. if (phba->eh_sgl_hndl_base[phba->eh_sgl_free_index]) {
  1118. /*
  1119. * this can happen if clean_task is called on a task that
  1120. * failed in xmit_task or alloc_pdu.
  1121. */
  1122. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_CONFIG,
  1123. "BM_%d : Double Free in eh SGL ,"
  1124. "eh_sgl_free_index=%d\n",
  1125. phba->eh_sgl_free_index);
  1126. return;
  1127. }
  1128. phba->eh_sgl_hndl_base[phba->eh_sgl_free_index] = psgl_handle;
  1129. phba->eh_sgl_hndl_avbl++;
  1130. if (phba->eh_sgl_free_index ==
  1131. (phba->params.icds_per_ctrl - phba->params.ios_per_ctrl - 1))
  1132. phba->eh_sgl_free_index = 0;
  1133. else
  1134. phba->eh_sgl_free_index++;
  1135. }
  1136. static void
  1137. be_complete_io(struct beiscsi_conn *beiscsi_conn,
  1138. struct iscsi_task *task,
  1139. struct common_sol_cqe *csol_cqe)
  1140. {
  1141. struct beiscsi_io_task *io_task = task->dd_data;
  1142. struct be_status_bhs *sts_bhs =
  1143. (struct be_status_bhs *)io_task->cmd_bhs;
  1144. struct iscsi_conn *conn = beiscsi_conn->conn;
  1145. unsigned char *sense;
  1146. u32 resid = 0, exp_cmdsn, max_cmdsn;
  1147. u8 rsp, status, flags;
  1148. exp_cmdsn = csol_cqe->exp_cmdsn;
  1149. max_cmdsn = (csol_cqe->exp_cmdsn +
  1150. csol_cqe->cmd_wnd - 1);
  1151. rsp = csol_cqe->i_resp;
  1152. status = csol_cqe->i_sts;
  1153. flags = csol_cqe->i_flags;
  1154. resid = csol_cqe->res_cnt;
  1155. if (!task->sc) {
  1156. if (io_task->scsi_cmnd)
  1157. scsi_dma_unmap(io_task->scsi_cmnd);
  1158. return;
  1159. }
  1160. task->sc->result = (DID_OK << 16) | status;
  1161. if (rsp != ISCSI_STATUS_CMD_COMPLETED) {
  1162. task->sc->result = DID_ERROR << 16;
  1163. goto unmap;
  1164. }
  1165. /* bidi not initially supported */
  1166. if (flags & (ISCSI_FLAG_CMD_UNDERFLOW | ISCSI_FLAG_CMD_OVERFLOW)) {
  1167. if (!status && (flags & ISCSI_FLAG_CMD_OVERFLOW))
  1168. task->sc->result = DID_ERROR << 16;
  1169. if (flags & ISCSI_FLAG_CMD_UNDERFLOW) {
  1170. scsi_set_resid(task->sc, resid);
  1171. if (!status && (scsi_bufflen(task->sc) - resid <
  1172. task->sc->underflow))
  1173. task->sc->result = DID_ERROR << 16;
  1174. }
  1175. }
  1176. if (status == SAM_STAT_CHECK_CONDITION) {
  1177. u16 sense_len;
  1178. unsigned short *slen = (unsigned short *)sts_bhs->sense_info;
  1179. sense = sts_bhs->sense_info + sizeof(unsigned short);
  1180. sense_len = be16_to_cpu(*slen);
  1181. memcpy(task->sc->sense_buffer, sense,
  1182. min_t(u16, sense_len, SCSI_SENSE_BUFFERSIZE));
  1183. }
  1184. if (io_task->cmd_bhs->iscsi_hdr.flags & ISCSI_FLAG_CMD_READ)
  1185. conn->rxdata_octets += resid;
  1186. unmap:
  1187. scsi_dma_unmap(io_task->scsi_cmnd);
  1188. iscsi_complete_scsi_task(task, exp_cmdsn, max_cmdsn);
  1189. }
  1190. static void
  1191. be_complete_logout(struct beiscsi_conn *beiscsi_conn,
  1192. struct iscsi_task *task,
  1193. struct common_sol_cqe *csol_cqe)
  1194. {
  1195. struct iscsi_logout_rsp *hdr;
  1196. struct beiscsi_io_task *io_task = task->dd_data;
  1197. struct iscsi_conn *conn = beiscsi_conn->conn;
  1198. hdr = (struct iscsi_logout_rsp *)task->hdr;
  1199. hdr->opcode = ISCSI_OP_LOGOUT_RSP;
  1200. hdr->t2wait = 5;
  1201. hdr->t2retain = 0;
  1202. hdr->flags = csol_cqe->i_flags;
  1203. hdr->response = csol_cqe->i_resp;
  1204. hdr->exp_cmdsn = csol_cqe->exp_cmdsn;
  1205. hdr->max_cmdsn = (csol_cqe->exp_cmdsn + csol_cqe->cmd_wnd - 1);
  1206. hdr->dlength[0] = 0;
  1207. hdr->dlength[1] = 0;
  1208. hdr->dlength[2] = 0;
  1209. hdr->hlength = 0;
  1210. hdr->itt = io_task->libiscsi_itt;
  1211. __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0);
  1212. }
  1213. static void
  1214. be_complete_tmf(struct beiscsi_conn *beiscsi_conn,
  1215. struct iscsi_task *task,
  1216. struct common_sol_cqe *csol_cqe)
  1217. {
  1218. struct iscsi_tm_rsp *hdr;
  1219. struct iscsi_conn *conn = beiscsi_conn->conn;
  1220. struct beiscsi_io_task *io_task = task->dd_data;
  1221. hdr = (struct iscsi_tm_rsp *)task->hdr;
  1222. hdr->opcode = ISCSI_OP_SCSI_TMFUNC_RSP;
  1223. hdr->flags = csol_cqe->i_flags;
  1224. hdr->response = csol_cqe->i_resp;
  1225. hdr->exp_cmdsn = csol_cqe->exp_cmdsn;
  1226. hdr->max_cmdsn = (csol_cqe->exp_cmdsn +
  1227. csol_cqe->cmd_wnd - 1);
  1228. hdr->itt = io_task->libiscsi_itt;
  1229. __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0);
  1230. }
  1231. static void
  1232. hwi_complete_drvr_msgs(struct beiscsi_conn *beiscsi_conn,
  1233. struct beiscsi_hba *phba, struct sol_cqe *psol)
  1234. {
  1235. struct hwi_wrb_context *pwrb_context;
  1236. struct wrb_handle *pwrb_handle = NULL;
  1237. struct hwi_controller *phwi_ctrlr;
  1238. struct iscsi_task *task;
  1239. struct beiscsi_io_task *io_task;
  1240. struct iscsi_conn *conn = beiscsi_conn->conn;
  1241. struct iscsi_session *session = conn->session;
  1242. uint16_t wrb_index, cid;
  1243. phwi_ctrlr = phba->phwi_ctrlr;
  1244. if (chip_skh_r(phba->pcidev)) {
  1245. wrb_index = AMAP_GET_BITS(struct amap_it_dmsg_cqe_v2,
  1246. wrb_idx, psol);
  1247. cid = AMAP_GET_BITS(struct amap_it_dmsg_cqe_v2,
  1248. cid, psol);
  1249. } else {
  1250. wrb_index = AMAP_GET_BITS(struct amap_it_dmsg_cqe,
  1251. wrb_idx, psol);
  1252. cid = AMAP_GET_BITS(struct amap_it_dmsg_cqe,
  1253. cid, psol);
  1254. }
  1255. pwrb_context = &phwi_ctrlr->wrb_context[
  1256. cid - phba->fw_config.iscsi_cid_start];
  1257. pwrb_handle = pwrb_context->pwrb_handle_basestd[wrb_index];
  1258. task = pwrb_handle->pio_handle;
  1259. io_task = task->dd_data;
  1260. spin_lock_bh(&phba->mgmt_sgl_lock);
  1261. free_mgmt_sgl_handle(phba, io_task->psgl_handle);
  1262. spin_unlock_bh(&phba->mgmt_sgl_lock);
  1263. spin_lock_bh(&session->lock);
  1264. free_wrb_handle(phba, pwrb_context, pwrb_handle);
  1265. spin_unlock_bh(&session->lock);
  1266. }
  1267. static void
  1268. be_complete_nopin_resp(struct beiscsi_conn *beiscsi_conn,
  1269. struct iscsi_task *task,
  1270. struct common_sol_cqe *csol_cqe)
  1271. {
  1272. struct iscsi_nopin *hdr;
  1273. struct iscsi_conn *conn = beiscsi_conn->conn;
  1274. struct beiscsi_io_task *io_task = task->dd_data;
  1275. hdr = (struct iscsi_nopin *)task->hdr;
  1276. hdr->flags = csol_cqe->i_flags;
  1277. hdr->exp_cmdsn = cpu_to_be32(csol_cqe->exp_cmdsn);
  1278. hdr->max_cmdsn = be32_to_cpu(hdr->exp_cmdsn +
  1279. csol_cqe->cmd_wnd - 1);
  1280. hdr->opcode = ISCSI_OP_NOOP_IN;
  1281. hdr->itt = io_task->libiscsi_itt;
  1282. __iscsi_complete_pdu(conn, (struct iscsi_hdr *)hdr, NULL, 0);
  1283. }
  1284. static void adapter_get_sol_cqe(struct beiscsi_hba *phba,
  1285. struct sol_cqe *psol,
  1286. struct common_sol_cqe *csol_cqe)
  1287. {
  1288. if (chip_skh_r(phba->pcidev)) {
  1289. csol_cqe->exp_cmdsn = AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1290. i_exp_cmd_sn, psol);
  1291. csol_cqe->res_cnt = AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1292. i_res_cnt, psol);
  1293. csol_cqe->wrb_index = AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1294. wrb_index, psol);
  1295. csol_cqe->cid = AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1296. cid, psol);
  1297. csol_cqe->hw_sts = AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1298. hw_sts, psol);
  1299. csol_cqe->cmd_wnd = AMAP_GET_BITS(struct amap_sol_cqe,
  1300. i_cmd_wnd, psol);
  1301. if (AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1302. cmd_cmpl, psol))
  1303. csol_cqe->i_sts = AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1304. i_sts, psol);
  1305. else
  1306. csol_cqe->i_resp = AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1307. i_sts, psol);
  1308. if (AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1309. u, psol))
  1310. csol_cqe->i_flags = ISCSI_FLAG_CMD_UNDERFLOW;
  1311. if (AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1312. o, psol))
  1313. csol_cqe->i_flags |= ISCSI_FLAG_CMD_OVERFLOW;
  1314. } else {
  1315. csol_cqe->exp_cmdsn = AMAP_GET_BITS(struct amap_sol_cqe,
  1316. i_exp_cmd_sn, psol);
  1317. csol_cqe->res_cnt = AMAP_GET_BITS(struct amap_sol_cqe,
  1318. i_res_cnt, psol);
  1319. csol_cqe->cmd_wnd = AMAP_GET_BITS(struct amap_sol_cqe,
  1320. i_cmd_wnd, psol);
  1321. csol_cqe->wrb_index = AMAP_GET_BITS(struct amap_sol_cqe,
  1322. wrb_index, psol);
  1323. csol_cqe->cid = AMAP_GET_BITS(struct amap_sol_cqe,
  1324. cid, psol);
  1325. csol_cqe->hw_sts = AMAP_GET_BITS(struct amap_sol_cqe,
  1326. hw_sts, psol);
  1327. csol_cqe->i_resp = AMAP_GET_BITS(struct amap_sol_cqe,
  1328. i_resp, psol);
  1329. csol_cqe->i_sts = AMAP_GET_BITS(struct amap_sol_cqe,
  1330. i_sts, psol);
  1331. csol_cqe->i_flags = AMAP_GET_BITS(struct amap_sol_cqe,
  1332. i_flags, psol);
  1333. }
  1334. }
  1335. static void hwi_complete_cmd(struct beiscsi_conn *beiscsi_conn,
  1336. struct beiscsi_hba *phba, struct sol_cqe *psol)
  1337. {
  1338. struct hwi_wrb_context *pwrb_context;
  1339. struct wrb_handle *pwrb_handle;
  1340. struct iscsi_wrb *pwrb = NULL;
  1341. struct hwi_controller *phwi_ctrlr;
  1342. struct iscsi_task *task;
  1343. unsigned int type;
  1344. struct iscsi_conn *conn = beiscsi_conn->conn;
  1345. struct iscsi_session *session = conn->session;
  1346. struct common_sol_cqe csol_cqe = {0};
  1347. phwi_ctrlr = phba->phwi_ctrlr;
  1348. /* Copy the elements to a common structure */
  1349. adapter_get_sol_cqe(phba, psol, &csol_cqe);
  1350. pwrb_context = &phwi_ctrlr->wrb_context[
  1351. csol_cqe.cid - phba->fw_config.iscsi_cid_start];
  1352. pwrb_handle = pwrb_context->pwrb_handle_basestd[
  1353. csol_cqe.wrb_index];
  1354. task = pwrb_handle->pio_handle;
  1355. pwrb = pwrb_handle->pwrb;
  1356. type = ((struct beiscsi_io_task *)task->dd_data)->wrb_type;
  1357. spin_lock_bh(&session->lock);
  1358. switch (type) {
  1359. case HWH_TYPE_IO:
  1360. case HWH_TYPE_IO_RD:
  1361. if ((task->hdr->opcode & ISCSI_OPCODE_MASK) ==
  1362. ISCSI_OP_NOOP_OUT)
  1363. be_complete_nopin_resp(beiscsi_conn, task, &csol_cqe);
  1364. else
  1365. be_complete_io(beiscsi_conn, task, &csol_cqe);
  1366. break;
  1367. case HWH_TYPE_LOGOUT:
  1368. if ((task->hdr->opcode & ISCSI_OPCODE_MASK) == ISCSI_OP_LOGOUT)
  1369. be_complete_logout(beiscsi_conn, task, &csol_cqe);
  1370. else
  1371. be_complete_tmf(beiscsi_conn, task, &csol_cqe);
  1372. break;
  1373. case HWH_TYPE_LOGIN:
  1374. beiscsi_log(phba, KERN_ERR,
  1375. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  1376. "BM_%d :\t\t No HWH_TYPE_LOGIN Expected in"
  1377. " hwi_complete_cmd- Solicited path\n");
  1378. break;
  1379. case HWH_TYPE_NOP:
  1380. be_complete_nopin_resp(beiscsi_conn, task, &csol_cqe);
  1381. break;
  1382. default:
  1383. beiscsi_log(phba, KERN_WARNING,
  1384. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  1385. "BM_%d : In hwi_complete_cmd, unknown type = %d"
  1386. "wrb_index 0x%x CID 0x%x\n", type,
  1387. csol_cqe.wrb_index,
  1388. csol_cqe.cid);
  1389. break;
  1390. }
  1391. spin_unlock_bh(&session->lock);
  1392. }
  1393. static struct list_head *hwi_get_async_busy_list(struct hwi_async_pdu_context
  1394. *pasync_ctx, unsigned int is_header,
  1395. unsigned int host_write_ptr)
  1396. {
  1397. if (is_header)
  1398. return &pasync_ctx->async_entry[host_write_ptr].
  1399. header_busy_list;
  1400. else
  1401. return &pasync_ctx->async_entry[host_write_ptr].data_busy_list;
  1402. }
  1403. static struct async_pdu_handle *
  1404. hwi_get_async_handle(struct beiscsi_hba *phba,
  1405. struct beiscsi_conn *beiscsi_conn,
  1406. struct hwi_async_pdu_context *pasync_ctx,
  1407. struct i_t_dpdu_cqe *pdpdu_cqe, unsigned int *pcq_index)
  1408. {
  1409. struct be_bus_address phys_addr;
  1410. struct list_head *pbusy_list;
  1411. struct async_pdu_handle *pasync_handle = NULL;
  1412. unsigned char is_header = 0;
  1413. unsigned int index, dpl;
  1414. if (chip_skh_r(phba->pcidev)) {
  1415. dpl = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe_v2,
  1416. dpl, pdpdu_cqe);
  1417. index = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe_v2,
  1418. index, pdpdu_cqe);
  1419. } else {
  1420. dpl = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe,
  1421. dpl, pdpdu_cqe);
  1422. index = AMAP_GET_BITS(struct amap_i_t_dpdu_cqe,
  1423. index, pdpdu_cqe);
  1424. }
  1425. phys_addr.u.a32.address_lo =
  1426. (pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe,
  1427. db_addr_lo) / 32] - dpl);
  1428. phys_addr.u.a32.address_hi =
  1429. pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe,
  1430. db_addr_hi) / 32];
  1431. phys_addr.u.a64.address =
  1432. *((unsigned long long *)(&phys_addr.u.a64.address));
  1433. switch (pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe, code) / 32]
  1434. & PDUCQE_CODE_MASK) {
  1435. case UNSOL_HDR_NOTIFY:
  1436. is_header = 1;
  1437. pbusy_list = hwi_get_async_busy_list(pasync_ctx,
  1438. is_header, index);
  1439. break;
  1440. case UNSOL_DATA_NOTIFY:
  1441. pbusy_list = hwi_get_async_busy_list(pasync_ctx,
  1442. is_header, index);
  1443. break;
  1444. default:
  1445. pbusy_list = NULL;
  1446. beiscsi_log(phba, KERN_WARNING,
  1447. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1448. "BM_%d : Unexpected code=%d\n",
  1449. pdpdu_cqe->dw[offsetof(struct amap_i_t_dpdu_cqe,
  1450. code) / 32] & PDUCQE_CODE_MASK);
  1451. return NULL;
  1452. }
  1453. WARN_ON(list_empty(pbusy_list));
  1454. list_for_each_entry(pasync_handle, pbusy_list, link) {
  1455. if (pasync_handle->pa.u.a64.address == phys_addr.u.a64.address)
  1456. break;
  1457. }
  1458. WARN_ON(!pasync_handle);
  1459. pasync_handle->cri = (unsigned short)beiscsi_conn->beiscsi_conn_cid -
  1460. phba->fw_config.iscsi_cid_start;
  1461. pasync_handle->is_header = is_header;
  1462. pasync_handle->buffer_len = dpl;
  1463. *pcq_index = index;
  1464. return pasync_handle;
  1465. }
  1466. static unsigned int
  1467. hwi_update_async_writables(struct beiscsi_hba *phba,
  1468. struct hwi_async_pdu_context *pasync_ctx,
  1469. unsigned int is_header, unsigned int cq_index)
  1470. {
  1471. struct list_head *pbusy_list;
  1472. struct async_pdu_handle *pasync_handle;
  1473. unsigned int num_entries, writables = 0;
  1474. unsigned int *pep_read_ptr, *pwritables;
  1475. num_entries = pasync_ctx->num_entries;
  1476. if (is_header) {
  1477. pep_read_ptr = &pasync_ctx->async_header.ep_read_ptr;
  1478. pwritables = &pasync_ctx->async_header.writables;
  1479. } else {
  1480. pep_read_ptr = &pasync_ctx->async_data.ep_read_ptr;
  1481. pwritables = &pasync_ctx->async_data.writables;
  1482. }
  1483. while ((*pep_read_ptr) != cq_index) {
  1484. (*pep_read_ptr)++;
  1485. *pep_read_ptr = (*pep_read_ptr) % num_entries;
  1486. pbusy_list = hwi_get_async_busy_list(pasync_ctx, is_header,
  1487. *pep_read_ptr);
  1488. if (writables == 0)
  1489. WARN_ON(list_empty(pbusy_list));
  1490. if (!list_empty(pbusy_list)) {
  1491. pasync_handle = list_entry(pbusy_list->next,
  1492. struct async_pdu_handle,
  1493. link);
  1494. WARN_ON(!pasync_handle);
  1495. pasync_handle->consumed = 1;
  1496. }
  1497. writables++;
  1498. }
  1499. if (!writables) {
  1500. beiscsi_log(phba, KERN_ERR,
  1501. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  1502. "BM_%d : Duplicate notification received - index 0x%x!!\n",
  1503. cq_index);
  1504. WARN_ON(1);
  1505. }
  1506. *pwritables = *pwritables + writables;
  1507. return 0;
  1508. }
  1509. static void hwi_free_async_msg(struct beiscsi_hba *phba,
  1510. unsigned int cri)
  1511. {
  1512. struct hwi_controller *phwi_ctrlr;
  1513. struct hwi_async_pdu_context *pasync_ctx;
  1514. struct async_pdu_handle *pasync_handle, *tmp_handle;
  1515. struct list_head *plist;
  1516. phwi_ctrlr = phba->phwi_ctrlr;
  1517. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
  1518. plist = &pasync_ctx->async_entry[cri].wait_queue.list;
  1519. list_for_each_entry_safe(pasync_handle, tmp_handle, plist, link) {
  1520. list_del(&pasync_handle->link);
  1521. if (pasync_handle->is_header) {
  1522. list_add_tail(&pasync_handle->link,
  1523. &pasync_ctx->async_header.free_list);
  1524. pasync_ctx->async_header.free_entries++;
  1525. } else {
  1526. list_add_tail(&pasync_handle->link,
  1527. &pasync_ctx->async_data.free_list);
  1528. pasync_ctx->async_data.free_entries++;
  1529. }
  1530. }
  1531. INIT_LIST_HEAD(&pasync_ctx->async_entry[cri].wait_queue.list);
  1532. pasync_ctx->async_entry[cri].wait_queue.hdr_received = 0;
  1533. pasync_ctx->async_entry[cri].wait_queue.bytes_received = 0;
  1534. }
  1535. static struct phys_addr *
  1536. hwi_get_ring_address(struct hwi_async_pdu_context *pasync_ctx,
  1537. unsigned int is_header, unsigned int host_write_ptr)
  1538. {
  1539. struct phys_addr *pasync_sge = NULL;
  1540. if (is_header)
  1541. pasync_sge = pasync_ctx->async_header.ring_base;
  1542. else
  1543. pasync_sge = pasync_ctx->async_data.ring_base;
  1544. return pasync_sge + host_write_ptr;
  1545. }
  1546. static void hwi_post_async_buffers(struct beiscsi_hba *phba,
  1547. unsigned int is_header)
  1548. {
  1549. struct hwi_controller *phwi_ctrlr;
  1550. struct hwi_async_pdu_context *pasync_ctx;
  1551. struct async_pdu_handle *pasync_handle;
  1552. struct list_head *pfree_link, *pbusy_list;
  1553. struct phys_addr *pasync_sge;
  1554. unsigned int ring_id, num_entries;
  1555. unsigned int host_write_num;
  1556. unsigned int writables;
  1557. unsigned int i = 0;
  1558. u32 doorbell = 0;
  1559. phwi_ctrlr = phba->phwi_ctrlr;
  1560. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
  1561. num_entries = pasync_ctx->num_entries;
  1562. if (is_header) {
  1563. writables = min(pasync_ctx->async_header.writables,
  1564. pasync_ctx->async_header.free_entries);
  1565. pfree_link = pasync_ctx->async_header.free_list.next;
  1566. host_write_num = pasync_ctx->async_header.host_write_ptr;
  1567. ring_id = phwi_ctrlr->default_pdu_hdr.id;
  1568. } else {
  1569. writables = min(pasync_ctx->async_data.writables,
  1570. pasync_ctx->async_data.free_entries);
  1571. pfree_link = pasync_ctx->async_data.free_list.next;
  1572. host_write_num = pasync_ctx->async_data.host_write_ptr;
  1573. ring_id = phwi_ctrlr->default_pdu_data.id;
  1574. }
  1575. writables = (writables / 8) * 8;
  1576. if (writables) {
  1577. for (i = 0; i < writables; i++) {
  1578. pbusy_list =
  1579. hwi_get_async_busy_list(pasync_ctx, is_header,
  1580. host_write_num);
  1581. pasync_handle =
  1582. list_entry(pfree_link, struct async_pdu_handle,
  1583. link);
  1584. WARN_ON(!pasync_handle);
  1585. pasync_handle->consumed = 0;
  1586. pfree_link = pfree_link->next;
  1587. pasync_sge = hwi_get_ring_address(pasync_ctx,
  1588. is_header, host_write_num);
  1589. pasync_sge->hi = pasync_handle->pa.u.a32.address_lo;
  1590. pasync_sge->lo = pasync_handle->pa.u.a32.address_hi;
  1591. list_move(&pasync_handle->link, pbusy_list);
  1592. host_write_num++;
  1593. host_write_num = host_write_num % num_entries;
  1594. }
  1595. if (is_header) {
  1596. pasync_ctx->async_header.host_write_ptr =
  1597. host_write_num;
  1598. pasync_ctx->async_header.free_entries -= writables;
  1599. pasync_ctx->async_header.writables -= writables;
  1600. pasync_ctx->async_header.busy_entries += writables;
  1601. } else {
  1602. pasync_ctx->async_data.host_write_ptr = host_write_num;
  1603. pasync_ctx->async_data.free_entries -= writables;
  1604. pasync_ctx->async_data.writables -= writables;
  1605. pasync_ctx->async_data.busy_entries += writables;
  1606. }
  1607. doorbell |= ring_id & DB_DEF_PDU_RING_ID_MASK;
  1608. doorbell |= 1 << DB_DEF_PDU_REARM_SHIFT;
  1609. doorbell |= 0 << DB_DEF_PDU_EVENT_SHIFT;
  1610. doorbell |= (writables & DB_DEF_PDU_CQPROC_MASK)
  1611. << DB_DEF_PDU_CQPROC_SHIFT;
  1612. iowrite32(doorbell, phba->db_va + DB_RXULP0_OFFSET);
  1613. }
  1614. }
  1615. static void hwi_flush_default_pdu_buffer(struct beiscsi_hba *phba,
  1616. struct beiscsi_conn *beiscsi_conn,
  1617. struct i_t_dpdu_cqe *pdpdu_cqe)
  1618. {
  1619. struct hwi_controller *phwi_ctrlr;
  1620. struct hwi_async_pdu_context *pasync_ctx;
  1621. struct async_pdu_handle *pasync_handle = NULL;
  1622. unsigned int cq_index = -1;
  1623. phwi_ctrlr = phba->phwi_ctrlr;
  1624. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
  1625. pasync_handle = hwi_get_async_handle(phba, beiscsi_conn, pasync_ctx,
  1626. pdpdu_cqe, &cq_index);
  1627. BUG_ON(pasync_handle->is_header != 0);
  1628. if (pasync_handle->consumed == 0)
  1629. hwi_update_async_writables(phba, pasync_ctx,
  1630. pasync_handle->is_header, cq_index);
  1631. hwi_free_async_msg(phba, pasync_handle->cri);
  1632. hwi_post_async_buffers(phba, pasync_handle->is_header);
  1633. }
  1634. static unsigned int
  1635. hwi_fwd_async_msg(struct beiscsi_conn *beiscsi_conn,
  1636. struct beiscsi_hba *phba,
  1637. struct hwi_async_pdu_context *pasync_ctx, unsigned short cri)
  1638. {
  1639. struct list_head *plist;
  1640. struct async_pdu_handle *pasync_handle;
  1641. void *phdr = NULL;
  1642. unsigned int hdr_len = 0, buf_len = 0;
  1643. unsigned int status, index = 0, offset = 0;
  1644. void *pfirst_buffer = NULL;
  1645. unsigned int num_buf = 0;
  1646. plist = &pasync_ctx->async_entry[cri].wait_queue.list;
  1647. list_for_each_entry(pasync_handle, plist, link) {
  1648. if (index == 0) {
  1649. phdr = pasync_handle->pbuffer;
  1650. hdr_len = pasync_handle->buffer_len;
  1651. } else {
  1652. buf_len = pasync_handle->buffer_len;
  1653. if (!num_buf) {
  1654. pfirst_buffer = pasync_handle->pbuffer;
  1655. num_buf++;
  1656. }
  1657. memcpy(pfirst_buffer + offset,
  1658. pasync_handle->pbuffer, buf_len);
  1659. offset += buf_len;
  1660. }
  1661. index++;
  1662. }
  1663. status = beiscsi_process_async_pdu(beiscsi_conn, phba,
  1664. (beiscsi_conn->beiscsi_conn_cid -
  1665. phba->fw_config.iscsi_cid_start),
  1666. phdr, hdr_len, pfirst_buffer,
  1667. offset);
  1668. hwi_free_async_msg(phba, cri);
  1669. return 0;
  1670. }
  1671. static unsigned int
  1672. hwi_gather_async_pdu(struct beiscsi_conn *beiscsi_conn,
  1673. struct beiscsi_hba *phba,
  1674. struct async_pdu_handle *pasync_handle)
  1675. {
  1676. struct hwi_async_pdu_context *pasync_ctx;
  1677. struct hwi_controller *phwi_ctrlr;
  1678. unsigned int bytes_needed = 0, status = 0;
  1679. unsigned short cri = pasync_handle->cri;
  1680. struct pdu_base *ppdu;
  1681. phwi_ctrlr = phba->phwi_ctrlr;
  1682. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
  1683. list_del(&pasync_handle->link);
  1684. if (pasync_handle->is_header) {
  1685. pasync_ctx->async_header.busy_entries--;
  1686. if (pasync_ctx->async_entry[cri].wait_queue.hdr_received) {
  1687. hwi_free_async_msg(phba, cri);
  1688. BUG();
  1689. }
  1690. pasync_ctx->async_entry[cri].wait_queue.bytes_received = 0;
  1691. pasync_ctx->async_entry[cri].wait_queue.hdr_received = 1;
  1692. pasync_ctx->async_entry[cri].wait_queue.hdr_len =
  1693. (unsigned short)pasync_handle->buffer_len;
  1694. list_add_tail(&pasync_handle->link,
  1695. &pasync_ctx->async_entry[cri].wait_queue.list);
  1696. ppdu = pasync_handle->pbuffer;
  1697. bytes_needed = ((((ppdu->dw[offsetof(struct amap_pdu_base,
  1698. data_len_hi) / 32] & PDUBASE_DATALENHI_MASK) << 8) &
  1699. 0xFFFF0000) | ((be16_to_cpu((ppdu->
  1700. dw[offsetof(struct amap_pdu_base, data_len_lo) / 32]
  1701. & PDUBASE_DATALENLO_MASK) >> 16)) & 0x0000FFFF));
  1702. if (status == 0) {
  1703. pasync_ctx->async_entry[cri].wait_queue.bytes_needed =
  1704. bytes_needed;
  1705. if (bytes_needed == 0)
  1706. status = hwi_fwd_async_msg(beiscsi_conn, phba,
  1707. pasync_ctx, cri);
  1708. }
  1709. } else {
  1710. pasync_ctx->async_data.busy_entries--;
  1711. if (pasync_ctx->async_entry[cri].wait_queue.hdr_received) {
  1712. list_add_tail(&pasync_handle->link,
  1713. &pasync_ctx->async_entry[cri].wait_queue.
  1714. list);
  1715. pasync_ctx->async_entry[cri].wait_queue.
  1716. bytes_received +=
  1717. (unsigned short)pasync_handle->buffer_len;
  1718. if (pasync_ctx->async_entry[cri].wait_queue.
  1719. bytes_received >=
  1720. pasync_ctx->async_entry[cri].wait_queue.
  1721. bytes_needed)
  1722. status = hwi_fwd_async_msg(beiscsi_conn, phba,
  1723. pasync_ctx, cri);
  1724. }
  1725. }
  1726. return status;
  1727. }
  1728. static void hwi_process_default_pdu_ring(struct beiscsi_conn *beiscsi_conn,
  1729. struct beiscsi_hba *phba,
  1730. struct i_t_dpdu_cqe *pdpdu_cqe)
  1731. {
  1732. struct hwi_controller *phwi_ctrlr;
  1733. struct hwi_async_pdu_context *pasync_ctx;
  1734. struct async_pdu_handle *pasync_handle = NULL;
  1735. unsigned int cq_index = -1;
  1736. phwi_ctrlr = phba->phwi_ctrlr;
  1737. pasync_ctx = HWI_GET_ASYNC_PDU_CTX(phwi_ctrlr);
  1738. pasync_handle = hwi_get_async_handle(phba, beiscsi_conn, pasync_ctx,
  1739. pdpdu_cqe, &cq_index);
  1740. if (pasync_handle->consumed == 0)
  1741. hwi_update_async_writables(phba, pasync_ctx,
  1742. pasync_handle->is_header, cq_index);
  1743. hwi_gather_async_pdu(beiscsi_conn, phba, pasync_handle);
  1744. hwi_post_async_buffers(phba, pasync_handle->is_header);
  1745. }
  1746. static void beiscsi_process_mcc_isr(struct beiscsi_hba *phba)
  1747. {
  1748. struct be_queue_info *mcc_cq;
  1749. struct be_mcc_compl *mcc_compl;
  1750. unsigned int num_processed = 0;
  1751. mcc_cq = &phba->ctrl.mcc_obj.cq;
  1752. mcc_compl = queue_tail_node(mcc_cq);
  1753. mcc_compl->flags = le32_to_cpu(mcc_compl->flags);
  1754. while (mcc_compl->flags & CQE_FLAGS_VALID_MASK) {
  1755. if (num_processed >= 32) {
  1756. hwi_ring_cq_db(phba, mcc_cq->id,
  1757. num_processed, 0, 0);
  1758. num_processed = 0;
  1759. }
  1760. if (mcc_compl->flags & CQE_FLAGS_ASYNC_MASK) {
  1761. /* Interpret flags as an async trailer */
  1762. if (is_link_state_evt(mcc_compl->flags))
  1763. /* Interpret compl as a async link evt */
  1764. beiscsi_async_link_state_process(phba,
  1765. (struct be_async_event_link_state *) mcc_compl);
  1766. else
  1767. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_MBOX,
  1768. "BM_%d : Unsupported Async Event, flags"
  1769. " = 0x%08x\n",
  1770. mcc_compl->flags);
  1771. } else if (mcc_compl->flags & CQE_FLAGS_COMPLETED_MASK) {
  1772. be_mcc_compl_process_isr(&phba->ctrl, mcc_compl);
  1773. atomic_dec(&phba->ctrl.mcc_obj.q.used);
  1774. }
  1775. mcc_compl->flags = 0;
  1776. queue_tail_inc(mcc_cq);
  1777. mcc_compl = queue_tail_node(mcc_cq);
  1778. mcc_compl->flags = le32_to_cpu(mcc_compl->flags);
  1779. num_processed++;
  1780. }
  1781. if (num_processed > 0)
  1782. hwi_ring_cq_db(phba, mcc_cq->id, num_processed, 1, 0);
  1783. }
  1784. /**
  1785. * beiscsi_process_cq()- Process the Completion Queue
  1786. * @pbe_eq: Event Q on which the Completion has come
  1787. *
  1788. * return
  1789. * Number of Completion Entries processed.
  1790. **/
  1791. static unsigned int beiscsi_process_cq(struct be_eq_obj *pbe_eq)
  1792. {
  1793. struct be_queue_info *cq;
  1794. struct sol_cqe *sol;
  1795. struct dmsg_cqe *dmsg;
  1796. unsigned int num_processed = 0;
  1797. unsigned int tot_nump = 0;
  1798. unsigned short code = 0, cid = 0;
  1799. struct beiscsi_conn *beiscsi_conn;
  1800. struct beiscsi_endpoint *beiscsi_ep;
  1801. struct iscsi_endpoint *ep;
  1802. struct beiscsi_hba *phba;
  1803. cq = pbe_eq->cq;
  1804. sol = queue_tail_node(cq);
  1805. phba = pbe_eq->phba;
  1806. while (sol->dw[offsetof(struct amap_sol_cqe, valid) / 32] &
  1807. CQE_VALID_MASK) {
  1808. be_dws_le_to_cpu(sol, sizeof(struct sol_cqe));
  1809. code = (sol->dw[offsetof(struct amap_sol_cqe, code) /
  1810. 32] & CQE_CODE_MASK);
  1811. /* Get the CID */
  1812. if (chip_skh_r(phba->pcidev)) {
  1813. if ((code == DRIVERMSG_NOTIFY) ||
  1814. (code == UNSOL_HDR_NOTIFY) ||
  1815. (code == UNSOL_DATA_NOTIFY))
  1816. cid = AMAP_GET_BITS(
  1817. struct amap_i_t_dpdu_cqe_v2,
  1818. cid, sol);
  1819. else
  1820. cid = AMAP_GET_BITS(struct amap_sol_cqe_v2,
  1821. cid, sol);
  1822. } else
  1823. cid = AMAP_GET_BITS(struct amap_sol_cqe, cid, sol);
  1824. ep = phba->ep_array[cid - phba->fw_config.iscsi_cid_start];
  1825. beiscsi_ep = ep->dd_data;
  1826. beiscsi_conn = beiscsi_ep->conn;
  1827. if (num_processed >= 32) {
  1828. hwi_ring_cq_db(phba, cq->id,
  1829. num_processed, 0, 0);
  1830. tot_nump += num_processed;
  1831. num_processed = 0;
  1832. }
  1833. switch (code) {
  1834. case SOL_CMD_COMPLETE:
  1835. hwi_complete_cmd(beiscsi_conn, phba, sol);
  1836. break;
  1837. case DRIVERMSG_NOTIFY:
  1838. beiscsi_log(phba, KERN_INFO,
  1839. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1840. "BM_%d : Received %s[%d] on CID : %d\n",
  1841. cqe_desc[code], code, cid);
  1842. dmsg = (struct dmsg_cqe *)sol;
  1843. hwi_complete_drvr_msgs(beiscsi_conn, phba, sol);
  1844. break;
  1845. case UNSOL_HDR_NOTIFY:
  1846. beiscsi_log(phba, KERN_INFO,
  1847. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1848. "BM_%d : Received %s[%d] on CID : %d\n",
  1849. cqe_desc[code], code, cid);
  1850. hwi_process_default_pdu_ring(beiscsi_conn, phba,
  1851. (struct i_t_dpdu_cqe *)sol);
  1852. break;
  1853. case UNSOL_DATA_NOTIFY:
  1854. beiscsi_log(phba, KERN_INFO,
  1855. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  1856. "BM_%d : Received %s[%d] on CID : %d\n",
  1857. cqe_desc[code], code, cid);
  1858. hwi_process_default_pdu_ring(beiscsi_conn, phba,
  1859. (struct i_t_dpdu_cqe *)sol);
  1860. break;
  1861. case CXN_INVALIDATE_INDEX_NOTIFY:
  1862. case CMD_INVALIDATED_NOTIFY:
  1863. case CXN_INVALIDATE_NOTIFY:
  1864. beiscsi_log(phba, KERN_ERR,
  1865. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1866. "BM_%d : Ignoring %s[%d] on CID : %d\n",
  1867. cqe_desc[code], code, cid);
  1868. break;
  1869. case SOL_CMD_KILLED_DATA_DIGEST_ERR:
  1870. case CMD_KILLED_INVALID_STATSN_RCVD:
  1871. case CMD_KILLED_INVALID_R2T_RCVD:
  1872. case CMD_CXN_KILLED_LUN_INVALID:
  1873. case CMD_CXN_KILLED_ICD_INVALID:
  1874. case CMD_CXN_KILLED_ITT_INVALID:
  1875. case CMD_CXN_KILLED_SEQ_OUTOFORDER:
  1876. case CMD_CXN_KILLED_INVALID_DATASN_RCVD:
  1877. beiscsi_log(phba, KERN_ERR,
  1878. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  1879. "BM_%d : Cmd Notification %s[%d] on CID : %d\n",
  1880. cqe_desc[code], code, cid);
  1881. break;
  1882. case UNSOL_DATA_DIGEST_ERROR_NOTIFY:
  1883. beiscsi_log(phba, KERN_ERR,
  1884. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1885. "BM_%d : Dropping %s[%d] on DPDU ring on CID : %d\n",
  1886. cqe_desc[code], code, cid);
  1887. hwi_flush_default_pdu_buffer(phba, beiscsi_conn,
  1888. (struct i_t_dpdu_cqe *) sol);
  1889. break;
  1890. case CXN_KILLED_PDU_SIZE_EXCEEDS_DSL:
  1891. case CXN_KILLED_BURST_LEN_MISMATCH:
  1892. case CXN_KILLED_AHS_RCVD:
  1893. case CXN_KILLED_HDR_DIGEST_ERR:
  1894. case CXN_KILLED_UNKNOWN_HDR:
  1895. case CXN_KILLED_STALE_ITT_TTT_RCVD:
  1896. case CXN_KILLED_INVALID_ITT_TTT_RCVD:
  1897. case CXN_KILLED_TIMED_OUT:
  1898. case CXN_KILLED_FIN_RCVD:
  1899. case CXN_KILLED_RST_SENT:
  1900. case CXN_KILLED_RST_RCVD:
  1901. case CXN_KILLED_BAD_UNSOL_PDU_RCVD:
  1902. case CXN_KILLED_BAD_WRB_INDEX_ERROR:
  1903. case CXN_KILLED_OVER_RUN_RESIDUAL:
  1904. case CXN_KILLED_UNDER_RUN_RESIDUAL:
  1905. case CXN_KILLED_CMND_DATA_NOT_ON_SAME_CONN:
  1906. beiscsi_log(phba, KERN_ERR,
  1907. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1908. "BM_%d : Event %s[%d] received on CID : %d\n",
  1909. cqe_desc[code], code, cid);
  1910. if (beiscsi_conn)
  1911. iscsi_conn_failure(beiscsi_conn->conn,
  1912. ISCSI_ERR_CONN_FAILED);
  1913. break;
  1914. default:
  1915. beiscsi_log(phba, KERN_ERR,
  1916. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  1917. "BM_%d : Invalid CQE Event Received Code : %d"
  1918. "CID 0x%x...\n",
  1919. code, cid);
  1920. break;
  1921. }
  1922. AMAP_SET_BITS(struct amap_sol_cqe, valid, sol, 0);
  1923. queue_tail_inc(cq);
  1924. sol = queue_tail_node(cq);
  1925. num_processed++;
  1926. }
  1927. if (num_processed > 0) {
  1928. tot_nump += num_processed;
  1929. hwi_ring_cq_db(phba, cq->id, num_processed, 1, 0);
  1930. }
  1931. return tot_nump;
  1932. }
  1933. void beiscsi_process_all_cqs(struct work_struct *work)
  1934. {
  1935. unsigned long flags;
  1936. struct hwi_controller *phwi_ctrlr;
  1937. struct hwi_context_memory *phwi_context;
  1938. struct beiscsi_hba *phba;
  1939. struct be_eq_obj *pbe_eq =
  1940. container_of(work, struct be_eq_obj, work_cqs);
  1941. phba = pbe_eq->phba;
  1942. phwi_ctrlr = phba->phwi_ctrlr;
  1943. phwi_context = phwi_ctrlr->phwi_ctxt;
  1944. if (pbe_eq->todo_mcc_cq) {
  1945. spin_lock_irqsave(&phba->isr_lock, flags);
  1946. pbe_eq->todo_mcc_cq = false;
  1947. spin_unlock_irqrestore(&phba->isr_lock, flags);
  1948. beiscsi_process_mcc_isr(phba);
  1949. }
  1950. if (pbe_eq->todo_cq) {
  1951. spin_lock_irqsave(&phba->isr_lock, flags);
  1952. pbe_eq->todo_cq = false;
  1953. spin_unlock_irqrestore(&phba->isr_lock, flags);
  1954. beiscsi_process_cq(pbe_eq);
  1955. }
  1956. /* rearm EQ for further interrupts */
  1957. hwi_ring_eq_db(phba, pbe_eq->q.id, 0, 0, 1, 1);
  1958. }
  1959. static int be_iopoll(struct blk_iopoll *iop, int budget)
  1960. {
  1961. static unsigned int ret;
  1962. struct beiscsi_hba *phba;
  1963. struct be_eq_obj *pbe_eq;
  1964. pbe_eq = container_of(iop, struct be_eq_obj, iopoll);
  1965. ret = beiscsi_process_cq(pbe_eq);
  1966. if (ret < budget) {
  1967. phba = pbe_eq->phba;
  1968. blk_iopoll_complete(iop);
  1969. beiscsi_log(phba, KERN_INFO,
  1970. BEISCSI_LOG_CONFIG | BEISCSI_LOG_IO,
  1971. "BM_%d : rearm pbe_eq->q.id =%d\n",
  1972. pbe_eq->q.id);
  1973. hwi_ring_eq_db(phba, pbe_eq->q.id, 0, 0, 1, 1);
  1974. }
  1975. return ret;
  1976. }
  1977. static void
  1978. hwi_write_sgl_v2(struct iscsi_wrb *pwrb, struct scatterlist *sg,
  1979. unsigned int num_sg, struct beiscsi_io_task *io_task)
  1980. {
  1981. struct iscsi_sge *psgl;
  1982. unsigned int sg_len, index;
  1983. unsigned int sge_len = 0;
  1984. unsigned long long addr;
  1985. struct scatterlist *l_sg;
  1986. unsigned int offset;
  1987. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, iscsi_bhs_addr_lo, pwrb,
  1988. io_task->bhs_pa.u.a32.address_lo);
  1989. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, iscsi_bhs_addr_hi, pwrb,
  1990. io_task->bhs_pa.u.a32.address_hi);
  1991. l_sg = sg;
  1992. for (index = 0; (index < num_sg) && (index < 2); index++,
  1993. sg = sg_next(sg)) {
  1994. if (index == 0) {
  1995. sg_len = sg_dma_len(sg);
  1996. addr = (u64) sg_dma_address(sg);
  1997. AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
  1998. sge0_addr_lo, pwrb,
  1999. lower_32_bits(addr));
  2000. AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
  2001. sge0_addr_hi, pwrb,
  2002. upper_32_bits(addr));
  2003. AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
  2004. sge0_len, pwrb,
  2005. sg_len);
  2006. sge_len = sg_len;
  2007. } else {
  2008. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_r2t_offset,
  2009. pwrb, sge_len);
  2010. sg_len = sg_dma_len(sg);
  2011. addr = (u64) sg_dma_address(sg);
  2012. AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
  2013. sge1_addr_lo, pwrb,
  2014. lower_32_bits(addr));
  2015. AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
  2016. sge1_addr_hi, pwrb,
  2017. upper_32_bits(addr));
  2018. AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
  2019. sge1_len, pwrb,
  2020. sg_len);
  2021. }
  2022. }
  2023. psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag;
  2024. memset(psgl, 0, sizeof(*psgl) * BE2_SGE);
  2025. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len - 2);
  2026. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  2027. io_task->bhs_pa.u.a32.address_hi);
  2028. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  2029. io_task->bhs_pa.u.a32.address_lo);
  2030. if (num_sg == 1) {
  2031. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge0_last, pwrb,
  2032. 1);
  2033. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_last, pwrb,
  2034. 0);
  2035. } else if (num_sg == 2) {
  2036. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge0_last, pwrb,
  2037. 0);
  2038. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_last, pwrb,
  2039. 1);
  2040. } else {
  2041. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge0_last, pwrb,
  2042. 0);
  2043. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sge1_last, pwrb,
  2044. 0);
  2045. }
  2046. sg = l_sg;
  2047. psgl++;
  2048. psgl++;
  2049. offset = 0;
  2050. for (index = 0; index < num_sg; index++, sg = sg_next(sg), psgl++) {
  2051. sg_len = sg_dma_len(sg);
  2052. addr = (u64) sg_dma_address(sg);
  2053. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  2054. lower_32_bits(addr));
  2055. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  2056. upper_32_bits(addr));
  2057. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, sg_len);
  2058. AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, offset);
  2059. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0);
  2060. offset += sg_len;
  2061. }
  2062. psgl--;
  2063. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1);
  2064. }
  2065. static void
  2066. hwi_write_sgl(struct iscsi_wrb *pwrb, struct scatterlist *sg,
  2067. unsigned int num_sg, struct beiscsi_io_task *io_task)
  2068. {
  2069. struct iscsi_sge *psgl;
  2070. unsigned int sg_len, index;
  2071. unsigned int sge_len = 0;
  2072. unsigned long long addr;
  2073. struct scatterlist *l_sg;
  2074. unsigned int offset;
  2075. AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_lo, pwrb,
  2076. io_task->bhs_pa.u.a32.address_lo);
  2077. AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_hi, pwrb,
  2078. io_task->bhs_pa.u.a32.address_hi);
  2079. l_sg = sg;
  2080. for (index = 0; (index < num_sg) && (index < 2); index++,
  2081. sg = sg_next(sg)) {
  2082. if (index == 0) {
  2083. sg_len = sg_dma_len(sg);
  2084. addr = (u64) sg_dma_address(sg);
  2085. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_lo, pwrb,
  2086. ((u32)(addr & 0xFFFFFFFF)));
  2087. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_hi, pwrb,
  2088. ((u32)(addr >> 32)));
  2089. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_len, pwrb,
  2090. sg_len);
  2091. sge_len = sg_len;
  2092. } else {
  2093. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_r2t_offset,
  2094. pwrb, sge_len);
  2095. sg_len = sg_dma_len(sg);
  2096. addr = (u64) sg_dma_address(sg);
  2097. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_addr_lo, pwrb,
  2098. ((u32)(addr & 0xFFFFFFFF)));
  2099. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_addr_hi, pwrb,
  2100. ((u32)(addr >> 32)));
  2101. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_len, pwrb,
  2102. sg_len);
  2103. }
  2104. }
  2105. psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag;
  2106. memset(psgl, 0, sizeof(*psgl) * BE2_SGE);
  2107. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len - 2);
  2108. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  2109. io_task->bhs_pa.u.a32.address_hi);
  2110. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  2111. io_task->bhs_pa.u.a32.address_lo);
  2112. if (num_sg == 1) {
  2113. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb,
  2114. 1);
  2115. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb,
  2116. 0);
  2117. } else if (num_sg == 2) {
  2118. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb,
  2119. 0);
  2120. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb,
  2121. 1);
  2122. } else {
  2123. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb,
  2124. 0);
  2125. AMAP_SET_BITS(struct amap_iscsi_wrb, sge1_last, pwrb,
  2126. 0);
  2127. }
  2128. sg = l_sg;
  2129. psgl++;
  2130. psgl++;
  2131. offset = 0;
  2132. for (index = 0; index < num_sg; index++, sg = sg_next(sg), psgl++) {
  2133. sg_len = sg_dma_len(sg);
  2134. addr = (u64) sg_dma_address(sg);
  2135. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  2136. (addr & 0xFFFFFFFF));
  2137. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  2138. (addr >> 32));
  2139. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, sg_len);
  2140. AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, offset);
  2141. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0);
  2142. offset += sg_len;
  2143. }
  2144. psgl--;
  2145. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1);
  2146. }
  2147. /**
  2148. * hwi_write_buffer()- Populate the WRB with task info
  2149. * @pwrb: ptr to the WRB entry
  2150. * @task: iscsi task which is to be executed
  2151. **/
  2152. static void hwi_write_buffer(struct iscsi_wrb *pwrb, struct iscsi_task *task)
  2153. {
  2154. struct iscsi_sge *psgl;
  2155. struct beiscsi_io_task *io_task = task->dd_data;
  2156. struct beiscsi_conn *beiscsi_conn = io_task->conn;
  2157. struct beiscsi_hba *phba = beiscsi_conn->phba;
  2158. uint8_t dsp_value = 0;
  2159. io_task->bhs_len = sizeof(struct be_nonio_bhs) - 2;
  2160. AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_lo, pwrb,
  2161. io_task->bhs_pa.u.a32.address_lo);
  2162. AMAP_SET_BITS(struct amap_iscsi_wrb, iscsi_bhs_addr_hi, pwrb,
  2163. io_task->bhs_pa.u.a32.address_hi);
  2164. if (task->data) {
  2165. /* Check for the data_count */
  2166. dsp_value = (task->data_count) ? 1 : 0;
  2167. if (chip_skh_r(phba->pcidev))
  2168. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, dsp,
  2169. pwrb, dsp_value);
  2170. else
  2171. AMAP_SET_BITS(struct amap_iscsi_wrb, dsp,
  2172. pwrb, dsp_value);
  2173. /* Map addr only if there is data_count */
  2174. if (dsp_value) {
  2175. io_task->mtask_addr = pci_map_single(phba->pcidev,
  2176. task->data,
  2177. task->data_count,
  2178. PCI_DMA_TODEVICE);
  2179. io_task->mtask_data_count = task->data_count;
  2180. } else
  2181. io_task->mtask_addr = 0;
  2182. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_lo, pwrb,
  2183. lower_32_bits(io_task->mtask_addr));
  2184. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_addr_hi, pwrb,
  2185. upper_32_bits(io_task->mtask_addr));
  2186. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_len, pwrb,
  2187. task->data_count);
  2188. AMAP_SET_BITS(struct amap_iscsi_wrb, sge0_last, pwrb, 1);
  2189. } else {
  2190. AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 0);
  2191. io_task->mtask_addr = 0;
  2192. }
  2193. psgl = (struct iscsi_sge *)io_task->psgl_handle->pfrag;
  2194. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, io_task->bhs_len);
  2195. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  2196. io_task->bhs_pa.u.a32.address_hi);
  2197. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  2198. io_task->bhs_pa.u.a32.address_lo);
  2199. if (task->data) {
  2200. psgl++;
  2201. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl, 0);
  2202. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl, 0);
  2203. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, 0);
  2204. AMAP_SET_BITS(struct amap_iscsi_sge, sge_offset, psgl, 0);
  2205. AMAP_SET_BITS(struct amap_iscsi_sge, rsvd0, psgl, 0);
  2206. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 0);
  2207. psgl++;
  2208. if (task->data) {
  2209. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, psgl,
  2210. lower_32_bits(io_task->mtask_addr));
  2211. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, psgl,
  2212. upper_32_bits(io_task->mtask_addr));
  2213. }
  2214. AMAP_SET_BITS(struct amap_iscsi_sge, len, psgl, 0x106);
  2215. }
  2216. AMAP_SET_BITS(struct amap_iscsi_sge, last_sge, psgl, 1);
  2217. }
  2218. static void beiscsi_find_mem_req(struct beiscsi_hba *phba)
  2219. {
  2220. unsigned int num_cq_pages, num_async_pdu_buf_pages;
  2221. unsigned int num_async_pdu_data_pages, wrb_sz_per_cxn;
  2222. unsigned int num_async_pdu_buf_sgl_pages, num_async_pdu_data_sgl_pages;
  2223. num_cq_pages = PAGES_REQUIRED(phba->params.num_cq_entries * \
  2224. sizeof(struct sol_cqe));
  2225. num_async_pdu_buf_pages =
  2226. PAGES_REQUIRED(phba->params.asyncpdus_per_ctrl * \
  2227. phba->params.defpdu_hdr_sz);
  2228. num_async_pdu_buf_sgl_pages =
  2229. PAGES_REQUIRED(phba->params.asyncpdus_per_ctrl * \
  2230. sizeof(struct phys_addr));
  2231. num_async_pdu_data_pages =
  2232. PAGES_REQUIRED(phba->params.asyncpdus_per_ctrl * \
  2233. phba->params.defpdu_data_sz);
  2234. num_async_pdu_data_sgl_pages =
  2235. PAGES_REQUIRED(phba->params.asyncpdus_per_ctrl * \
  2236. sizeof(struct phys_addr));
  2237. phba->params.hwi_ws_sz = sizeof(struct hwi_controller);
  2238. phba->mem_req[ISCSI_MEM_GLOBAL_HEADER] = 2 *
  2239. BE_ISCSI_PDU_HEADER_SIZE;
  2240. phba->mem_req[HWI_MEM_ADDN_CONTEXT] =
  2241. sizeof(struct hwi_context_memory);
  2242. phba->mem_req[HWI_MEM_WRB] = sizeof(struct iscsi_wrb)
  2243. * (phba->params.wrbs_per_cxn)
  2244. * phba->params.cxns_per_ctrl;
  2245. wrb_sz_per_cxn = sizeof(struct wrb_handle) *
  2246. (phba->params.wrbs_per_cxn);
  2247. phba->mem_req[HWI_MEM_WRBH] = roundup_pow_of_two((wrb_sz_per_cxn) *
  2248. phba->params.cxns_per_ctrl);
  2249. phba->mem_req[HWI_MEM_SGLH] = sizeof(struct sgl_handle) *
  2250. phba->params.icds_per_ctrl;
  2251. phba->mem_req[HWI_MEM_SGE] = sizeof(struct iscsi_sge) *
  2252. phba->params.num_sge_per_io * phba->params.icds_per_ctrl;
  2253. phba->mem_req[HWI_MEM_ASYNC_HEADER_BUF] =
  2254. num_async_pdu_buf_pages * PAGE_SIZE;
  2255. phba->mem_req[HWI_MEM_ASYNC_DATA_BUF] =
  2256. num_async_pdu_data_pages * PAGE_SIZE;
  2257. phba->mem_req[HWI_MEM_ASYNC_HEADER_RING] =
  2258. num_async_pdu_buf_sgl_pages * PAGE_SIZE;
  2259. phba->mem_req[HWI_MEM_ASYNC_DATA_RING] =
  2260. num_async_pdu_data_sgl_pages * PAGE_SIZE;
  2261. phba->mem_req[HWI_MEM_ASYNC_HEADER_HANDLE] =
  2262. phba->params.asyncpdus_per_ctrl *
  2263. sizeof(struct async_pdu_handle);
  2264. phba->mem_req[HWI_MEM_ASYNC_DATA_HANDLE] =
  2265. phba->params.asyncpdus_per_ctrl *
  2266. sizeof(struct async_pdu_handle);
  2267. phba->mem_req[HWI_MEM_ASYNC_PDU_CONTEXT] =
  2268. sizeof(struct hwi_async_pdu_context) +
  2269. (phba->params.cxns_per_ctrl * sizeof(struct hwi_async_entry));
  2270. }
  2271. static int beiscsi_alloc_mem(struct beiscsi_hba *phba)
  2272. {
  2273. struct be_mem_descriptor *mem_descr;
  2274. dma_addr_t bus_add;
  2275. struct mem_array *mem_arr, *mem_arr_orig;
  2276. unsigned int i, j, alloc_size, curr_alloc_size;
  2277. phba->phwi_ctrlr = kzalloc(phba->params.hwi_ws_sz, GFP_KERNEL);
  2278. if (!phba->phwi_ctrlr)
  2279. return -ENOMEM;
  2280. phba->init_mem = kcalloc(SE_MEM_MAX, sizeof(*mem_descr),
  2281. GFP_KERNEL);
  2282. if (!phba->init_mem) {
  2283. kfree(phba->phwi_ctrlr);
  2284. return -ENOMEM;
  2285. }
  2286. mem_arr_orig = kmalloc(sizeof(*mem_arr_orig) * BEISCSI_MAX_FRAGS_INIT,
  2287. GFP_KERNEL);
  2288. if (!mem_arr_orig) {
  2289. kfree(phba->init_mem);
  2290. kfree(phba->phwi_ctrlr);
  2291. return -ENOMEM;
  2292. }
  2293. mem_descr = phba->init_mem;
  2294. for (i = 0; i < SE_MEM_MAX; i++) {
  2295. j = 0;
  2296. mem_arr = mem_arr_orig;
  2297. alloc_size = phba->mem_req[i];
  2298. memset(mem_arr, 0, sizeof(struct mem_array) *
  2299. BEISCSI_MAX_FRAGS_INIT);
  2300. curr_alloc_size = min(be_max_phys_size * 1024, alloc_size);
  2301. do {
  2302. mem_arr->virtual_address = pci_alloc_consistent(
  2303. phba->pcidev,
  2304. curr_alloc_size,
  2305. &bus_add);
  2306. if (!mem_arr->virtual_address) {
  2307. if (curr_alloc_size <= BE_MIN_MEM_SIZE)
  2308. goto free_mem;
  2309. if (curr_alloc_size -
  2310. rounddown_pow_of_two(curr_alloc_size))
  2311. curr_alloc_size = rounddown_pow_of_two
  2312. (curr_alloc_size);
  2313. else
  2314. curr_alloc_size = curr_alloc_size / 2;
  2315. } else {
  2316. mem_arr->bus_address.u.
  2317. a64.address = (__u64) bus_add;
  2318. mem_arr->size = curr_alloc_size;
  2319. alloc_size -= curr_alloc_size;
  2320. curr_alloc_size = min(be_max_phys_size *
  2321. 1024, alloc_size);
  2322. j++;
  2323. mem_arr++;
  2324. }
  2325. } while (alloc_size);
  2326. mem_descr->num_elements = j;
  2327. mem_descr->size_in_bytes = phba->mem_req[i];
  2328. mem_descr->mem_array = kmalloc(sizeof(*mem_arr) * j,
  2329. GFP_KERNEL);
  2330. if (!mem_descr->mem_array)
  2331. goto free_mem;
  2332. memcpy(mem_descr->mem_array, mem_arr_orig,
  2333. sizeof(struct mem_array) * j);
  2334. mem_descr++;
  2335. }
  2336. kfree(mem_arr_orig);
  2337. return 0;
  2338. free_mem:
  2339. mem_descr->num_elements = j;
  2340. while ((i) || (j)) {
  2341. for (j = mem_descr->num_elements; j > 0; j--) {
  2342. pci_free_consistent(phba->pcidev,
  2343. mem_descr->mem_array[j - 1].size,
  2344. mem_descr->mem_array[j - 1].
  2345. virtual_address,
  2346. (unsigned long)mem_descr->
  2347. mem_array[j - 1].
  2348. bus_address.u.a64.address);
  2349. }
  2350. if (i) {
  2351. i--;
  2352. kfree(mem_descr->mem_array);
  2353. mem_descr--;
  2354. }
  2355. }
  2356. kfree(mem_arr_orig);
  2357. kfree(phba->init_mem);
  2358. kfree(phba->phwi_ctrlr);
  2359. return -ENOMEM;
  2360. }
  2361. static int beiscsi_get_memory(struct beiscsi_hba *phba)
  2362. {
  2363. beiscsi_find_mem_req(phba);
  2364. return beiscsi_alloc_mem(phba);
  2365. }
  2366. static void iscsi_init_global_templates(struct beiscsi_hba *phba)
  2367. {
  2368. struct pdu_data_out *pdata_out;
  2369. struct pdu_nop_out *pnop_out;
  2370. struct be_mem_descriptor *mem_descr;
  2371. mem_descr = phba->init_mem;
  2372. mem_descr += ISCSI_MEM_GLOBAL_HEADER;
  2373. pdata_out =
  2374. (struct pdu_data_out *)mem_descr->mem_array[0].virtual_address;
  2375. memset(pdata_out, 0, BE_ISCSI_PDU_HEADER_SIZE);
  2376. AMAP_SET_BITS(struct amap_pdu_data_out, opcode, pdata_out,
  2377. IIOC_SCSI_DATA);
  2378. pnop_out =
  2379. (struct pdu_nop_out *)((unsigned char *)mem_descr->mem_array[0].
  2380. virtual_address + BE_ISCSI_PDU_HEADER_SIZE);
  2381. memset(pnop_out, 0, BE_ISCSI_PDU_HEADER_SIZE);
  2382. AMAP_SET_BITS(struct amap_pdu_nop_out, ttt, pnop_out, 0xFFFFFFFF);
  2383. AMAP_SET_BITS(struct amap_pdu_nop_out, f_bit, pnop_out, 1);
  2384. AMAP_SET_BITS(struct amap_pdu_nop_out, i_bit, pnop_out, 0);
  2385. }
  2386. static int beiscsi_init_wrb_handle(struct beiscsi_hba *phba)
  2387. {
  2388. struct be_mem_descriptor *mem_descr_wrbh, *mem_descr_wrb;
  2389. struct wrb_handle *pwrb_handle = NULL;
  2390. struct hwi_controller *phwi_ctrlr;
  2391. struct hwi_wrb_context *pwrb_context;
  2392. struct iscsi_wrb *pwrb = NULL;
  2393. unsigned int num_cxn_wrbh = 0;
  2394. unsigned int num_cxn_wrb = 0, j, idx = 0, index;
  2395. mem_descr_wrbh = phba->init_mem;
  2396. mem_descr_wrbh += HWI_MEM_WRBH;
  2397. mem_descr_wrb = phba->init_mem;
  2398. mem_descr_wrb += HWI_MEM_WRB;
  2399. phwi_ctrlr = phba->phwi_ctrlr;
  2400. for (index = 0; index < phba->params.cxns_per_ctrl * 2; index += 2) {
  2401. pwrb_context = &phwi_ctrlr->wrb_context[index];
  2402. pwrb_context->pwrb_handle_base =
  2403. kzalloc(sizeof(struct wrb_handle *) *
  2404. phba->params.wrbs_per_cxn, GFP_KERNEL);
  2405. if (!pwrb_context->pwrb_handle_base) {
  2406. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2407. "BM_%d : Mem Alloc Failed. Failing to load\n");
  2408. goto init_wrb_hndl_failed;
  2409. }
  2410. pwrb_context->pwrb_handle_basestd =
  2411. kzalloc(sizeof(struct wrb_handle *) *
  2412. phba->params.wrbs_per_cxn, GFP_KERNEL);
  2413. if (!pwrb_context->pwrb_handle_basestd) {
  2414. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2415. "BM_%d : Mem Alloc Failed. Failing to load\n");
  2416. goto init_wrb_hndl_failed;
  2417. }
  2418. if (!num_cxn_wrbh) {
  2419. pwrb_handle =
  2420. mem_descr_wrbh->mem_array[idx].virtual_address;
  2421. num_cxn_wrbh = ((mem_descr_wrbh->mem_array[idx].size) /
  2422. ((sizeof(struct wrb_handle)) *
  2423. phba->params.wrbs_per_cxn));
  2424. idx++;
  2425. }
  2426. pwrb_context->alloc_index = 0;
  2427. pwrb_context->wrb_handles_available = 0;
  2428. pwrb_context->free_index = 0;
  2429. if (num_cxn_wrbh) {
  2430. for (j = 0; j < phba->params.wrbs_per_cxn; j++) {
  2431. pwrb_context->pwrb_handle_base[j] = pwrb_handle;
  2432. pwrb_context->pwrb_handle_basestd[j] =
  2433. pwrb_handle;
  2434. pwrb_context->wrb_handles_available++;
  2435. pwrb_handle->wrb_index = j;
  2436. pwrb_handle++;
  2437. }
  2438. num_cxn_wrbh--;
  2439. }
  2440. }
  2441. idx = 0;
  2442. for (index = 0; index < phba->params.cxns_per_ctrl * 2; index += 2) {
  2443. pwrb_context = &phwi_ctrlr->wrb_context[index];
  2444. if (!num_cxn_wrb) {
  2445. pwrb = mem_descr_wrb->mem_array[idx].virtual_address;
  2446. num_cxn_wrb = (mem_descr_wrb->mem_array[idx].size) /
  2447. ((sizeof(struct iscsi_wrb) *
  2448. phba->params.wrbs_per_cxn));
  2449. idx++;
  2450. }
  2451. if (num_cxn_wrb) {
  2452. for (j = 0; j < phba->params.wrbs_per_cxn; j++) {
  2453. pwrb_handle = pwrb_context->pwrb_handle_base[j];
  2454. pwrb_handle->pwrb = pwrb;
  2455. pwrb++;
  2456. }
  2457. num_cxn_wrb--;
  2458. }
  2459. }
  2460. return 0;
  2461. init_wrb_hndl_failed:
  2462. for (j = index; j > 0; j--) {
  2463. pwrb_context = &phwi_ctrlr->wrb_context[j];
  2464. kfree(pwrb_context->pwrb_handle_base);
  2465. kfree(pwrb_context->pwrb_handle_basestd);
  2466. }
  2467. return -ENOMEM;
  2468. }
  2469. static void hwi_init_async_pdu_ctx(struct beiscsi_hba *phba)
  2470. {
  2471. struct hwi_controller *phwi_ctrlr;
  2472. struct hba_parameters *p = &phba->params;
  2473. struct hwi_async_pdu_context *pasync_ctx;
  2474. struct async_pdu_handle *pasync_header_h, *pasync_data_h;
  2475. unsigned int index, idx, num_per_mem, num_async_data;
  2476. struct be_mem_descriptor *mem_descr;
  2477. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2478. mem_descr += HWI_MEM_ASYNC_PDU_CONTEXT;
  2479. phwi_ctrlr = phba->phwi_ctrlr;
  2480. phwi_ctrlr->phwi_ctxt->pasync_ctx = (struct hwi_async_pdu_context *)
  2481. mem_descr->mem_array[0].virtual_address;
  2482. pasync_ctx = phwi_ctrlr->phwi_ctxt->pasync_ctx;
  2483. memset(pasync_ctx, 0, sizeof(*pasync_ctx));
  2484. pasync_ctx->num_entries = p->asyncpdus_per_ctrl;
  2485. pasync_ctx->buffer_size = p->defpdu_hdr_sz;
  2486. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2487. mem_descr += HWI_MEM_ASYNC_HEADER_BUF;
  2488. if (mem_descr->mem_array[0].virtual_address) {
  2489. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2490. "BM_%d : hwi_init_async_pdu_ctx"
  2491. " HWI_MEM_ASYNC_HEADER_BUF va=%p\n",
  2492. mem_descr->mem_array[0].virtual_address);
  2493. } else
  2494. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  2495. "BM_%d : No Virtual address\n");
  2496. pasync_ctx->async_header.va_base =
  2497. mem_descr->mem_array[0].virtual_address;
  2498. pasync_ctx->async_header.pa_base.u.a64.address =
  2499. mem_descr->mem_array[0].bus_address.u.a64.address;
  2500. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2501. mem_descr += HWI_MEM_ASYNC_HEADER_RING;
  2502. if (mem_descr->mem_array[0].virtual_address) {
  2503. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2504. "BM_%d : hwi_init_async_pdu_ctx"
  2505. " HWI_MEM_ASYNC_HEADER_RING va=%p\n",
  2506. mem_descr->mem_array[0].virtual_address);
  2507. } else
  2508. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  2509. "BM_%d : No Virtual address\n");
  2510. pasync_ctx->async_header.ring_base =
  2511. mem_descr->mem_array[0].virtual_address;
  2512. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2513. mem_descr += HWI_MEM_ASYNC_HEADER_HANDLE;
  2514. if (mem_descr->mem_array[0].virtual_address) {
  2515. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2516. "BM_%d : hwi_init_async_pdu_ctx"
  2517. " HWI_MEM_ASYNC_HEADER_HANDLE va=%p\n",
  2518. mem_descr->mem_array[0].virtual_address);
  2519. } else
  2520. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  2521. "BM_%d : No Virtual address\n");
  2522. pasync_ctx->async_header.handle_base =
  2523. mem_descr->mem_array[0].virtual_address;
  2524. pasync_ctx->async_header.writables = 0;
  2525. INIT_LIST_HEAD(&pasync_ctx->async_header.free_list);
  2526. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2527. mem_descr += HWI_MEM_ASYNC_DATA_RING;
  2528. if (mem_descr->mem_array[0].virtual_address) {
  2529. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2530. "BM_%d : hwi_init_async_pdu_ctx"
  2531. " HWI_MEM_ASYNC_DATA_RING va=%p\n",
  2532. mem_descr->mem_array[0].virtual_address);
  2533. } else
  2534. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  2535. "BM_%d : No Virtual address\n");
  2536. pasync_ctx->async_data.ring_base =
  2537. mem_descr->mem_array[0].virtual_address;
  2538. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2539. mem_descr += HWI_MEM_ASYNC_DATA_HANDLE;
  2540. if (!mem_descr->mem_array[0].virtual_address)
  2541. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  2542. "BM_%d : No Virtual address\n");
  2543. pasync_ctx->async_data.handle_base =
  2544. mem_descr->mem_array[0].virtual_address;
  2545. pasync_ctx->async_data.writables = 0;
  2546. INIT_LIST_HEAD(&pasync_ctx->async_data.free_list);
  2547. pasync_header_h =
  2548. (struct async_pdu_handle *)pasync_ctx->async_header.handle_base;
  2549. pasync_data_h =
  2550. (struct async_pdu_handle *)pasync_ctx->async_data.handle_base;
  2551. mem_descr = (struct be_mem_descriptor *)phba->init_mem;
  2552. mem_descr += HWI_MEM_ASYNC_DATA_BUF;
  2553. if (mem_descr->mem_array[0].virtual_address) {
  2554. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2555. "BM_%d : hwi_init_async_pdu_ctx"
  2556. " HWI_MEM_ASYNC_DATA_BUF va=%p\n",
  2557. mem_descr->mem_array[0].virtual_address);
  2558. } else
  2559. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  2560. "BM_%d : No Virtual address\n");
  2561. idx = 0;
  2562. pasync_ctx->async_data.va_base =
  2563. mem_descr->mem_array[idx].virtual_address;
  2564. pasync_ctx->async_data.pa_base.u.a64.address =
  2565. mem_descr->mem_array[idx].bus_address.u.a64.address;
  2566. num_async_data = ((mem_descr->mem_array[idx].size) /
  2567. phba->params.defpdu_data_sz);
  2568. num_per_mem = 0;
  2569. for (index = 0; index < p->asyncpdus_per_ctrl; index++) {
  2570. pasync_header_h->cri = -1;
  2571. pasync_header_h->index = (char)index;
  2572. INIT_LIST_HEAD(&pasync_header_h->link);
  2573. pasync_header_h->pbuffer =
  2574. (void *)((unsigned long)
  2575. (pasync_ctx->async_header.va_base) +
  2576. (p->defpdu_hdr_sz * index));
  2577. pasync_header_h->pa.u.a64.address =
  2578. pasync_ctx->async_header.pa_base.u.a64.address +
  2579. (p->defpdu_hdr_sz * index);
  2580. list_add_tail(&pasync_header_h->link,
  2581. &pasync_ctx->async_header.free_list);
  2582. pasync_header_h++;
  2583. pasync_ctx->async_header.free_entries++;
  2584. pasync_ctx->async_header.writables++;
  2585. INIT_LIST_HEAD(&pasync_ctx->async_entry[index].wait_queue.list);
  2586. INIT_LIST_HEAD(&pasync_ctx->async_entry[index].
  2587. header_busy_list);
  2588. pasync_data_h->cri = -1;
  2589. pasync_data_h->index = (char)index;
  2590. INIT_LIST_HEAD(&pasync_data_h->link);
  2591. if (!num_async_data) {
  2592. num_per_mem = 0;
  2593. idx++;
  2594. pasync_ctx->async_data.va_base =
  2595. mem_descr->mem_array[idx].virtual_address;
  2596. pasync_ctx->async_data.pa_base.u.a64.address =
  2597. mem_descr->mem_array[idx].
  2598. bus_address.u.a64.address;
  2599. num_async_data = ((mem_descr->mem_array[idx].size) /
  2600. phba->params.defpdu_data_sz);
  2601. }
  2602. pasync_data_h->pbuffer =
  2603. (void *)((unsigned long)
  2604. (pasync_ctx->async_data.va_base) +
  2605. (p->defpdu_data_sz * num_per_mem));
  2606. pasync_data_h->pa.u.a64.address =
  2607. pasync_ctx->async_data.pa_base.u.a64.address +
  2608. (p->defpdu_data_sz * num_per_mem);
  2609. num_per_mem++;
  2610. num_async_data--;
  2611. list_add_tail(&pasync_data_h->link,
  2612. &pasync_ctx->async_data.free_list);
  2613. pasync_data_h++;
  2614. pasync_ctx->async_data.free_entries++;
  2615. pasync_ctx->async_data.writables++;
  2616. INIT_LIST_HEAD(&pasync_ctx->async_entry[index].data_busy_list);
  2617. }
  2618. pasync_ctx->async_header.host_write_ptr = 0;
  2619. pasync_ctx->async_header.ep_read_ptr = -1;
  2620. pasync_ctx->async_data.host_write_ptr = 0;
  2621. pasync_ctx->async_data.ep_read_ptr = -1;
  2622. }
  2623. static int
  2624. be_sgl_create_contiguous(void *virtual_address,
  2625. u64 physical_address, u32 length,
  2626. struct be_dma_mem *sgl)
  2627. {
  2628. WARN_ON(!virtual_address);
  2629. WARN_ON(!physical_address);
  2630. WARN_ON(!length > 0);
  2631. WARN_ON(!sgl);
  2632. sgl->va = virtual_address;
  2633. sgl->dma = (unsigned long)physical_address;
  2634. sgl->size = length;
  2635. return 0;
  2636. }
  2637. static void be_sgl_destroy_contiguous(struct be_dma_mem *sgl)
  2638. {
  2639. memset(sgl, 0, sizeof(*sgl));
  2640. }
  2641. static void
  2642. hwi_build_be_sgl_arr(struct beiscsi_hba *phba,
  2643. struct mem_array *pmem, struct be_dma_mem *sgl)
  2644. {
  2645. if (sgl->va)
  2646. be_sgl_destroy_contiguous(sgl);
  2647. be_sgl_create_contiguous(pmem->virtual_address,
  2648. pmem->bus_address.u.a64.address,
  2649. pmem->size, sgl);
  2650. }
  2651. static void
  2652. hwi_build_be_sgl_by_offset(struct beiscsi_hba *phba,
  2653. struct mem_array *pmem, struct be_dma_mem *sgl)
  2654. {
  2655. if (sgl->va)
  2656. be_sgl_destroy_contiguous(sgl);
  2657. be_sgl_create_contiguous((unsigned char *)pmem->virtual_address,
  2658. pmem->bus_address.u.a64.address,
  2659. pmem->size, sgl);
  2660. }
  2661. static int be_fill_queue(struct be_queue_info *q,
  2662. u16 len, u16 entry_size, void *vaddress)
  2663. {
  2664. struct be_dma_mem *mem = &q->dma_mem;
  2665. memset(q, 0, sizeof(*q));
  2666. q->len = len;
  2667. q->entry_size = entry_size;
  2668. mem->size = len * entry_size;
  2669. mem->va = vaddress;
  2670. if (!mem->va)
  2671. return -ENOMEM;
  2672. memset(mem->va, 0, mem->size);
  2673. return 0;
  2674. }
  2675. static int beiscsi_create_eqs(struct beiscsi_hba *phba,
  2676. struct hwi_context_memory *phwi_context)
  2677. {
  2678. unsigned int i, num_eq_pages;
  2679. int ret = 0, eq_for_mcc;
  2680. struct be_queue_info *eq;
  2681. struct be_dma_mem *mem;
  2682. void *eq_vaddress;
  2683. dma_addr_t paddr;
  2684. num_eq_pages = PAGES_REQUIRED(phba->params.num_eq_entries * \
  2685. sizeof(struct be_eq_entry));
  2686. if (phba->msix_enabled)
  2687. eq_for_mcc = 1;
  2688. else
  2689. eq_for_mcc = 0;
  2690. for (i = 0; i < (phba->num_cpus + eq_for_mcc); i++) {
  2691. eq = &phwi_context->be_eq[i].q;
  2692. mem = &eq->dma_mem;
  2693. phwi_context->be_eq[i].phba = phba;
  2694. eq_vaddress = pci_alloc_consistent(phba->pcidev,
  2695. num_eq_pages * PAGE_SIZE,
  2696. &paddr);
  2697. if (!eq_vaddress)
  2698. goto create_eq_error;
  2699. mem->va = eq_vaddress;
  2700. ret = be_fill_queue(eq, phba->params.num_eq_entries,
  2701. sizeof(struct be_eq_entry), eq_vaddress);
  2702. if (ret) {
  2703. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2704. "BM_%d : be_fill_queue Failed for EQ\n");
  2705. goto create_eq_error;
  2706. }
  2707. mem->dma = paddr;
  2708. ret = beiscsi_cmd_eq_create(&phba->ctrl, eq,
  2709. phwi_context->cur_eqd);
  2710. if (ret) {
  2711. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2712. "BM_%d : beiscsi_cmd_eq_create"
  2713. "Failed for EQ\n");
  2714. goto create_eq_error;
  2715. }
  2716. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2717. "BM_%d : eqid = %d\n",
  2718. phwi_context->be_eq[i].q.id);
  2719. }
  2720. return 0;
  2721. create_eq_error:
  2722. for (i = 0; i < (phba->num_cpus + eq_for_mcc); i++) {
  2723. eq = &phwi_context->be_eq[i].q;
  2724. mem = &eq->dma_mem;
  2725. if (mem->va)
  2726. pci_free_consistent(phba->pcidev, num_eq_pages
  2727. * PAGE_SIZE,
  2728. mem->va, mem->dma);
  2729. }
  2730. return ret;
  2731. }
  2732. static int beiscsi_create_cqs(struct beiscsi_hba *phba,
  2733. struct hwi_context_memory *phwi_context)
  2734. {
  2735. unsigned int i, num_cq_pages;
  2736. int ret = 0;
  2737. struct be_queue_info *cq, *eq;
  2738. struct be_dma_mem *mem;
  2739. struct be_eq_obj *pbe_eq;
  2740. void *cq_vaddress;
  2741. dma_addr_t paddr;
  2742. num_cq_pages = PAGES_REQUIRED(phba->params.num_cq_entries * \
  2743. sizeof(struct sol_cqe));
  2744. for (i = 0; i < phba->num_cpus; i++) {
  2745. cq = &phwi_context->be_cq[i];
  2746. eq = &phwi_context->be_eq[i].q;
  2747. pbe_eq = &phwi_context->be_eq[i];
  2748. pbe_eq->cq = cq;
  2749. pbe_eq->phba = phba;
  2750. mem = &cq->dma_mem;
  2751. cq_vaddress = pci_alloc_consistent(phba->pcidev,
  2752. num_cq_pages * PAGE_SIZE,
  2753. &paddr);
  2754. if (!cq_vaddress)
  2755. goto create_cq_error;
  2756. ret = be_fill_queue(cq, phba->params.num_cq_entries,
  2757. sizeof(struct sol_cqe), cq_vaddress);
  2758. if (ret) {
  2759. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2760. "BM_%d : be_fill_queue Failed "
  2761. "for ISCSI CQ\n");
  2762. goto create_cq_error;
  2763. }
  2764. mem->dma = paddr;
  2765. ret = beiscsi_cmd_cq_create(&phba->ctrl, cq, eq, false,
  2766. false, 0);
  2767. if (ret) {
  2768. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2769. "BM_%d : beiscsi_cmd_eq_create"
  2770. "Failed for ISCSI CQ\n");
  2771. goto create_cq_error;
  2772. }
  2773. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2774. "BM_%d : iscsi cq_id is %d for eq_id %d\n"
  2775. "iSCSI CQ CREATED\n", cq->id, eq->id);
  2776. }
  2777. return 0;
  2778. create_cq_error:
  2779. for (i = 0; i < phba->num_cpus; i++) {
  2780. cq = &phwi_context->be_cq[i];
  2781. mem = &cq->dma_mem;
  2782. if (mem->va)
  2783. pci_free_consistent(phba->pcidev, num_cq_pages
  2784. * PAGE_SIZE,
  2785. mem->va, mem->dma);
  2786. }
  2787. return ret;
  2788. }
  2789. static int
  2790. beiscsi_create_def_hdr(struct beiscsi_hba *phba,
  2791. struct hwi_context_memory *phwi_context,
  2792. struct hwi_controller *phwi_ctrlr,
  2793. unsigned int def_pdu_ring_sz)
  2794. {
  2795. unsigned int idx;
  2796. int ret;
  2797. struct be_queue_info *dq, *cq;
  2798. struct be_dma_mem *mem;
  2799. struct be_mem_descriptor *mem_descr;
  2800. void *dq_vaddress;
  2801. idx = 0;
  2802. dq = &phwi_context->be_def_hdrq;
  2803. cq = &phwi_context->be_cq[0];
  2804. mem = &dq->dma_mem;
  2805. mem_descr = phba->init_mem;
  2806. mem_descr += HWI_MEM_ASYNC_HEADER_RING;
  2807. dq_vaddress = mem_descr->mem_array[idx].virtual_address;
  2808. ret = be_fill_queue(dq, mem_descr->mem_array[0].size /
  2809. sizeof(struct phys_addr),
  2810. sizeof(struct phys_addr), dq_vaddress);
  2811. if (ret) {
  2812. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2813. "BM_%d : be_fill_queue Failed for DEF PDU HDR\n");
  2814. return ret;
  2815. }
  2816. mem->dma = (unsigned long)mem_descr->mem_array[idx].
  2817. bus_address.u.a64.address;
  2818. ret = be_cmd_create_default_pdu_queue(&phba->ctrl, cq, dq,
  2819. def_pdu_ring_sz,
  2820. phba->params.defpdu_hdr_sz);
  2821. if (ret) {
  2822. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2823. "BM_%d : be_cmd_create_default_pdu_queue Failed DEFHDR\n");
  2824. return ret;
  2825. }
  2826. phwi_ctrlr->default_pdu_hdr.id = phwi_context->be_def_hdrq.id;
  2827. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2828. "BM_%d : iscsi def pdu id is %d\n",
  2829. phwi_context->be_def_hdrq.id);
  2830. hwi_post_async_buffers(phba, 1);
  2831. return 0;
  2832. }
  2833. static int
  2834. beiscsi_create_def_data(struct beiscsi_hba *phba,
  2835. struct hwi_context_memory *phwi_context,
  2836. struct hwi_controller *phwi_ctrlr,
  2837. unsigned int def_pdu_ring_sz)
  2838. {
  2839. unsigned int idx;
  2840. int ret;
  2841. struct be_queue_info *dataq, *cq;
  2842. struct be_dma_mem *mem;
  2843. struct be_mem_descriptor *mem_descr;
  2844. void *dq_vaddress;
  2845. idx = 0;
  2846. dataq = &phwi_context->be_def_dataq;
  2847. cq = &phwi_context->be_cq[0];
  2848. mem = &dataq->dma_mem;
  2849. mem_descr = phba->init_mem;
  2850. mem_descr += HWI_MEM_ASYNC_DATA_RING;
  2851. dq_vaddress = mem_descr->mem_array[idx].virtual_address;
  2852. ret = be_fill_queue(dataq, mem_descr->mem_array[0].size /
  2853. sizeof(struct phys_addr),
  2854. sizeof(struct phys_addr), dq_vaddress);
  2855. if (ret) {
  2856. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2857. "BM_%d : be_fill_queue Failed for DEF PDU DATA\n");
  2858. return ret;
  2859. }
  2860. mem->dma = (unsigned long)mem_descr->mem_array[idx].
  2861. bus_address.u.a64.address;
  2862. ret = be_cmd_create_default_pdu_queue(&phba->ctrl, cq, dataq,
  2863. def_pdu_ring_sz,
  2864. phba->params.defpdu_data_sz);
  2865. if (ret) {
  2866. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2867. "BM_%d be_cmd_create_default_pdu_queue"
  2868. " Failed for DEF PDU DATA\n");
  2869. return ret;
  2870. }
  2871. phwi_ctrlr->default_pdu_data.id = phwi_context->be_def_dataq.id;
  2872. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2873. "BM_%d : iscsi def data id is %d\n",
  2874. phwi_context->be_def_dataq.id);
  2875. hwi_post_async_buffers(phba, 0);
  2876. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2877. "BM_%d : DEFAULT PDU DATA RING CREATED\n");
  2878. return 0;
  2879. }
  2880. static int
  2881. beiscsi_post_pages(struct beiscsi_hba *phba)
  2882. {
  2883. struct be_mem_descriptor *mem_descr;
  2884. struct mem_array *pm_arr;
  2885. unsigned int page_offset, i;
  2886. struct be_dma_mem sgl;
  2887. int status;
  2888. mem_descr = phba->init_mem;
  2889. mem_descr += HWI_MEM_SGE;
  2890. pm_arr = mem_descr->mem_array;
  2891. page_offset = (sizeof(struct iscsi_sge) * phba->params.num_sge_per_io *
  2892. phba->fw_config.iscsi_icd_start) / PAGE_SIZE;
  2893. for (i = 0; i < mem_descr->num_elements; i++) {
  2894. hwi_build_be_sgl_arr(phba, pm_arr, &sgl);
  2895. status = be_cmd_iscsi_post_sgl_pages(&phba->ctrl, &sgl,
  2896. page_offset,
  2897. (pm_arr->size / PAGE_SIZE));
  2898. page_offset += pm_arr->size / PAGE_SIZE;
  2899. if (status != 0) {
  2900. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2901. "BM_%d : post sgl failed.\n");
  2902. return status;
  2903. }
  2904. pm_arr++;
  2905. }
  2906. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  2907. "BM_%d : POSTED PAGES\n");
  2908. return 0;
  2909. }
  2910. static void be_queue_free(struct beiscsi_hba *phba, struct be_queue_info *q)
  2911. {
  2912. struct be_dma_mem *mem = &q->dma_mem;
  2913. if (mem->va) {
  2914. pci_free_consistent(phba->pcidev, mem->size,
  2915. mem->va, mem->dma);
  2916. mem->va = NULL;
  2917. }
  2918. }
  2919. static int be_queue_alloc(struct beiscsi_hba *phba, struct be_queue_info *q,
  2920. u16 len, u16 entry_size)
  2921. {
  2922. struct be_dma_mem *mem = &q->dma_mem;
  2923. memset(q, 0, sizeof(*q));
  2924. q->len = len;
  2925. q->entry_size = entry_size;
  2926. mem->size = len * entry_size;
  2927. mem->va = pci_alloc_consistent(phba->pcidev, mem->size, &mem->dma);
  2928. if (!mem->va)
  2929. return -ENOMEM;
  2930. memset(mem->va, 0, mem->size);
  2931. return 0;
  2932. }
  2933. static int
  2934. beiscsi_create_wrb_rings(struct beiscsi_hba *phba,
  2935. struct hwi_context_memory *phwi_context,
  2936. struct hwi_controller *phwi_ctrlr)
  2937. {
  2938. unsigned int wrb_mem_index, offset, size, num_wrb_rings;
  2939. u64 pa_addr_lo;
  2940. unsigned int idx, num, i;
  2941. struct mem_array *pwrb_arr;
  2942. void *wrb_vaddr;
  2943. struct be_dma_mem sgl;
  2944. struct be_mem_descriptor *mem_descr;
  2945. int status;
  2946. idx = 0;
  2947. mem_descr = phba->init_mem;
  2948. mem_descr += HWI_MEM_WRB;
  2949. pwrb_arr = kmalloc(sizeof(*pwrb_arr) * phba->params.cxns_per_ctrl,
  2950. GFP_KERNEL);
  2951. if (!pwrb_arr) {
  2952. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2953. "BM_%d : Memory alloc failed in create wrb ring.\n");
  2954. return -ENOMEM;
  2955. }
  2956. wrb_vaddr = mem_descr->mem_array[idx].virtual_address;
  2957. pa_addr_lo = mem_descr->mem_array[idx].bus_address.u.a64.address;
  2958. num_wrb_rings = mem_descr->mem_array[idx].size /
  2959. (phba->params.wrbs_per_cxn * sizeof(struct iscsi_wrb));
  2960. for (num = 0; num < phba->params.cxns_per_ctrl; num++) {
  2961. if (num_wrb_rings) {
  2962. pwrb_arr[num].virtual_address = wrb_vaddr;
  2963. pwrb_arr[num].bus_address.u.a64.address = pa_addr_lo;
  2964. pwrb_arr[num].size = phba->params.wrbs_per_cxn *
  2965. sizeof(struct iscsi_wrb);
  2966. wrb_vaddr += pwrb_arr[num].size;
  2967. pa_addr_lo += pwrb_arr[num].size;
  2968. num_wrb_rings--;
  2969. } else {
  2970. idx++;
  2971. wrb_vaddr = mem_descr->mem_array[idx].virtual_address;
  2972. pa_addr_lo = mem_descr->mem_array[idx].\
  2973. bus_address.u.a64.address;
  2974. num_wrb_rings = mem_descr->mem_array[idx].size /
  2975. (phba->params.wrbs_per_cxn *
  2976. sizeof(struct iscsi_wrb));
  2977. pwrb_arr[num].virtual_address = wrb_vaddr;
  2978. pwrb_arr[num].bus_address.u.a64.address\
  2979. = pa_addr_lo;
  2980. pwrb_arr[num].size = phba->params.wrbs_per_cxn *
  2981. sizeof(struct iscsi_wrb);
  2982. wrb_vaddr += pwrb_arr[num].size;
  2983. pa_addr_lo += pwrb_arr[num].size;
  2984. num_wrb_rings--;
  2985. }
  2986. }
  2987. for (i = 0; i < phba->params.cxns_per_ctrl; i++) {
  2988. wrb_mem_index = 0;
  2989. offset = 0;
  2990. size = 0;
  2991. hwi_build_be_sgl_by_offset(phba, &pwrb_arr[i], &sgl);
  2992. status = be_cmd_wrbq_create(&phba->ctrl, &sgl,
  2993. &phwi_context->be_wrbq[i]);
  2994. if (status != 0) {
  2995. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  2996. "BM_%d : wrbq create failed.");
  2997. kfree(pwrb_arr);
  2998. return status;
  2999. }
  3000. phwi_ctrlr->wrb_context[i * 2].cid = phwi_context->be_wrbq[i].
  3001. id;
  3002. }
  3003. kfree(pwrb_arr);
  3004. return 0;
  3005. }
  3006. static void free_wrb_handles(struct beiscsi_hba *phba)
  3007. {
  3008. unsigned int index;
  3009. struct hwi_controller *phwi_ctrlr;
  3010. struct hwi_wrb_context *pwrb_context;
  3011. phwi_ctrlr = phba->phwi_ctrlr;
  3012. for (index = 0; index < phba->params.cxns_per_ctrl * 2; index += 2) {
  3013. pwrb_context = &phwi_ctrlr->wrb_context[index];
  3014. kfree(pwrb_context->pwrb_handle_base);
  3015. kfree(pwrb_context->pwrb_handle_basestd);
  3016. }
  3017. }
  3018. static void be_mcc_queues_destroy(struct beiscsi_hba *phba)
  3019. {
  3020. struct be_queue_info *q;
  3021. struct be_ctrl_info *ctrl = &phba->ctrl;
  3022. q = &phba->ctrl.mcc_obj.q;
  3023. if (q->created)
  3024. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_MCCQ);
  3025. be_queue_free(phba, q);
  3026. q = &phba->ctrl.mcc_obj.cq;
  3027. if (q->created)
  3028. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_CQ);
  3029. be_queue_free(phba, q);
  3030. }
  3031. static void hwi_cleanup(struct beiscsi_hba *phba)
  3032. {
  3033. struct be_queue_info *q;
  3034. struct be_ctrl_info *ctrl = &phba->ctrl;
  3035. struct hwi_controller *phwi_ctrlr;
  3036. struct hwi_context_memory *phwi_context;
  3037. int i, eq_num;
  3038. phwi_ctrlr = phba->phwi_ctrlr;
  3039. phwi_context = phwi_ctrlr->phwi_ctxt;
  3040. for (i = 0; i < phba->params.cxns_per_ctrl; i++) {
  3041. q = &phwi_context->be_wrbq[i];
  3042. if (q->created)
  3043. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_WRBQ);
  3044. }
  3045. free_wrb_handles(phba);
  3046. q = &phwi_context->be_def_hdrq;
  3047. if (q->created)
  3048. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_DPDUQ);
  3049. q = &phwi_context->be_def_dataq;
  3050. if (q->created)
  3051. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_DPDUQ);
  3052. beiscsi_cmd_q_destroy(ctrl, NULL, QTYPE_SGL);
  3053. for (i = 0; i < (phba->num_cpus); i++) {
  3054. q = &phwi_context->be_cq[i];
  3055. if (q->created)
  3056. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_CQ);
  3057. }
  3058. if (phba->msix_enabled)
  3059. eq_num = 1;
  3060. else
  3061. eq_num = 0;
  3062. for (i = 0; i < (phba->num_cpus + eq_num); i++) {
  3063. q = &phwi_context->be_eq[i].q;
  3064. if (q->created)
  3065. beiscsi_cmd_q_destroy(ctrl, q, QTYPE_EQ);
  3066. }
  3067. be_mcc_queues_destroy(phba);
  3068. }
  3069. static int be_mcc_queues_create(struct beiscsi_hba *phba,
  3070. struct hwi_context_memory *phwi_context)
  3071. {
  3072. struct be_queue_info *q, *cq;
  3073. struct be_ctrl_info *ctrl = &phba->ctrl;
  3074. /* Alloc MCC compl queue */
  3075. cq = &phba->ctrl.mcc_obj.cq;
  3076. if (be_queue_alloc(phba, cq, MCC_CQ_LEN,
  3077. sizeof(struct be_mcc_compl)))
  3078. goto err;
  3079. /* Ask BE to create MCC compl queue; */
  3080. if (phba->msix_enabled) {
  3081. if (beiscsi_cmd_cq_create(ctrl, cq, &phwi_context->be_eq
  3082. [phba->num_cpus].q, false, true, 0))
  3083. goto mcc_cq_free;
  3084. } else {
  3085. if (beiscsi_cmd_cq_create(ctrl, cq, &phwi_context->be_eq[0].q,
  3086. false, true, 0))
  3087. goto mcc_cq_free;
  3088. }
  3089. /* Alloc MCC queue */
  3090. q = &phba->ctrl.mcc_obj.q;
  3091. if (be_queue_alloc(phba, q, MCC_Q_LEN, sizeof(struct be_mcc_wrb)))
  3092. goto mcc_cq_destroy;
  3093. /* Ask BE to create MCC queue */
  3094. if (beiscsi_cmd_mccq_create(phba, q, cq))
  3095. goto mcc_q_free;
  3096. return 0;
  3097. mcc_q_free:
  3098. be_queue_free(phba, q);
  3099. mcc_cq_destroy:
  3100. beiscsi_cmd_q_destroy(ctrl, cq, QTYPE_CQ);
  3101. mcc_cq_free:
  3102. be_queue_free(phba, cq);
  3103. err:
  3104. return -ENOMEM;
  3105. }
  3106. /**
  3107. * find_num_cpus()- Get the CPU online count
  3108. * @phba: ptr to priv structure
  3109. *
  3110. * CPU count is used for creating EQ.
  3111. **/
  3112. static void find_num_cpus(struct beiscsi_hba *phba)
  3113. {
  3114. int num_cpus = 0;
  3115. num_cpus = num_online_cpus();
  3116. switch (phba->generation) {
  3117. case BE_GEN2:
  3118. case BE_GEN3:
  3119. phba->num_cpus = (num_cpus > BEISCSI_MAX_NUM_CPUS) ?
  3120. BEISCSI_MAX_NUM_CPUS : num_cpus;
  3121. break;
  3122. case BE_GEN4:
  3123. phba->num_cpus = (num_cpus > OC_SKH_MAX_NUM_CPUS) ?
  3124. OC_SKH_MAX_NUM_CPUS : num_cpus;
  3125. break;
  3126. default:
  3127. phba->num_cpus = 1;
  3128. }
  3129. }
  3130. static int hwi_init_port(struct beiscsi_hba *phba)
  3131. {
  3132. struct hwi_controller *phwi_ctrlr;
  3133. struct hwi_context_memory *phwi_context;
  3134. unsigned int def_pdu_ring_sz;
  3135. struct be_ctrl_info *ctrl = &phba->ctrl;
  3136. int status;
  3137. def_pdu_ring_sz =
  3138. phba->params.asyncpdus_per_ctrl * sizeof(struct phys_addr);
  3139. phwi_ctrlr = phba->phwi_ctrlr;
  3140. phwi_context = phwi_ctrlr->phwi_ctxt;
  3141. phwi_context->max_eqd = 0;
  3142. phwi_context->min_eqd = 0;
  3143. phwi_context->cur_eqd = 64;
  3144. be_cmd_fw_initialize(&phba->ctrl);
  3145. status = beiscsi_create_eqs(phba, phwi_context);
  3146. if (status != 0) {
  3147. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3148. "BM_%d : EQ not created\n");
  3149. goto error;
  3150. }
  3151. status = be_mcc_queues_create(phba, phwi_context);
  3152. if (status != 0)
  3153. goto error;
  3154. status = mgmt_check_supported_fw(ctrl, phba);
  3155. if (status != 0) {
  3156. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3157. "BM_%d : Unsupported fw version\n");
  3158. goto error;
  3159. }
  3160. status = beiscsi_create_cqs(phba, phwi_context);
  3161. if (status != 0) {
  3162. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3163. "BM_%d : CQ not created\n");
  3164. goto error;
  3165. }
  3166. status = beiscsi_create_def_hdr(phba, phwi_context, phwi_ctrlr,
  3167. def_pdu_ring_sz);
  3168. if (status != 0) {
  3169. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3170. "BM_%d : Default Header not created\n");
  3171. goto error;
  3172. }
  3173. status = beiscsi_create_def_data(phba, phwi_context,
  3174. phwi_ctrlr, def_pdu_ring_sz);
  3175. if (status != 0) {
  3176. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3177. "BM_%d : Default Data not created\n");
  3178. goto error;
  3179. }
  3180. status = beiscsi_post_pages(phba);
  3181. if (status != 0) {
  3182. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3183. "BM_%d : Post SGL Pages Failed\n");
  3184. goto error;
  3185. }
  3186. status = beiscsi_create_wrb_rings(phba, phwi_context, phwi_ctrlr);
  3187. if (status != 0) {
  3188. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3189. "BM_%d : WRB Rings not created\n");
  3190. goto error;
  3191. }
  3192. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3193. "BM_%d : hwi_init_port success\n");
  3194. return 0;
  3195. error:
  3196. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3197. "BM_%d : hwi_init_port failed");
  3198. hwi_cleanup(phba);
  3199. return status;
  3200. }
  3201. static int hwi_init_controller(struct beiscsi_hba *phba)
  3202. {
  3203. struct hwi_controller *phwi_ctrlr;
  3204. phwi_ctrlr = phba->phwi_ctrlr;
  3205. if (1 == phba->init_mem[HWI_MEM_ADDN_CONTEXT].num_elements) {
  3206. phwi_ctrlr->phwi_ctxt = (struct hwi_context_memory *)phba->
  3207. init_mem[HWI_MEM_ADDN_CONTEXT].mem_array[0].virtual_address;
  3208. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3209. "BM_%d : phwi_ctrlr->phwi_ctxt=%p\n",
  3210. phwi_ctrlr->phwi_ctxt);
  3211. } else {
  3212. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3213. "BM_%d : HWI_MEM_ADDN_CONTEXT is more "
  3214. "than one element.Failing to load\n");
  3215. return -ENOMEM;
  3216. }
  3217. iscsi_init_global_templates(phba);
  3218. if (beiscsi_init_wrb_handle(phba))
  3219. return -ENOMEM;
  3220. hwi_init_async_pdu_ctx(phba);
  3221. if (hwi_init_port(phba) != 0) {
  3222. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3223. "BM_%d : hwi_init_controller failed\n");
  3224. return -ENOMEM;
  3225. }
  3226. return 0;
  3227. }
  3228. static void beiscsi_free_mem(struct beiscsi_hba *phba)
  3229. {
  3230. struct be_mem_descriptor *mem_descr;
  3231. int i, j;
  3232. mem_descr = phba->init_mem;
  3233. i = 0;
  3234. j = 0;
  3235. for (i = 0; i < SE_MEM_MAX; i++) {
  3236. for (j = mem_descr->num_elements; j > 0; j--) {
  3237. pci_free_consistent(phba->pcidev,
  3238. mem_descr->mem_array[j - 1].size,
  3239. mem_descr->mem_array[j - 1].virtual_address,
  3240. (unsigned long)mem_descr->mem_array[j - 1].
  3241. bus_address.u.a64.address);
  3242. }
  3243. kfree(mem_descr->mem_array);
  3244. mem_descr++;
  3245. }
  3246. kfree(phba->init_mem);
  3247. kfree(phba->phwi_ctrlr);
  3248. }
  3249. static int beiscsi_init_controller(struct beiscsi_hba *phba)
  3250. {
  3251. int ret = -ENOMEM;
  3252. ret = beiscsi_get_memory(phba);
  3253. if (ret < 0) {
  3254. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3255. "BM_%d : beiscsi_dev_probe -"
  3256. "Failed in beiscsi_alloc_memory\n");
  3257. return ret;
  3258. }
  3259. ret = hwi_init_controller(phba);
  3260. if (ret)
  3261. goto free_init;
  3262. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3263. "BM_%d : Return success from beiscsi_init_controller");
  3264. return 0;
  3265. free_init:
  3266. beiscsi_free_mem(phba);
  3267. return ret;
  3268. }
  3269. static int beiscsi_init_sgl_handle(struct beiscsi_hba *phba)
  3270. {
  3271. struct be_mem_descriptor *mem_descr_sglh, *mem_descr_sg;
  3272. struct sgl_handle *psgl_handle;
  3273. struct iscsi_sge *pfrag;
  3274. unsigned int arr_index, i, idx;
  3275. phba->io_sgl_hndl_avbl = 0;
  3276. phba->eh_sgl_hndl_avbl = 0;
  3277. mem_descr_sglh = phba->init_mem;
  3278. mem_descr_sglh += HWI_MEM_SGLH;
  3279. if (1 == mem_descr_sglh->num_elements) {
  3280. phba->io_sgl_hndl_base = kzalloc(sizeof(struct sgl_handle *) *
  3281. phba->params.ios_per_ctrl,
  3282. GFP_KERNEL);
  3283. if (!phba->io_sgl_hndl_base) {
  3284. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3285. "BM_%d : Mem Alloc Failed. Failing to load\n");
  3286. return -ENOMEM;
  3287. }
  3288. phba->eh_sgl_hndl_base = kzalloc(sizeof(struct sgl_handle *) *
  3289. (phba->params.icds_per_ctrl -
  3290. phba->params.ios_per_ctrl),
  3291. GFP_KERNEL);
  3292. if (!phba->eh_sgl_hndl_base) {
  3293. kfree(phba->io_sgl_hndl_base);
  3294. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3295. "BM_%d : Mem Alloc Failed. Failing to load\n");
  3296. return -ENOMEM;
  3297. }
  3298. } else {
  3299. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3300. "BM_%d : HWI_MEM_SGLH is more than one element."
  3301. "Failing to load\n");
  3302. return -ENOMEM;
  3303. }
  3304. arr_index = 0;
  3305. idx = 0;
  3306. while (idx < mem_descr_sglh->num_elements) {
  3307. psgl_handle = mem_descr_sglh->mem_array[idx].virtual_address;
  3308. for (i = 0; i < (mem_descr_sglh->mem_array[idx].size /
  3309. sizeof(struct sgl_handle)); i++) {
  3310. if (arr_index < phba->params.ios_per_ctrl) {
  3311. phba->io_sgl_hndl_base[arr_index] = psgl_handle;
  3312. phba->io_sgl_hndl_avbl++;
  3313. arr_index++;
  3314. } else {
  3315. phba->eh_sgl_hndl_base[arr_index -
  3316. phba->params.ios_per_ctrl] =
  3317. psgl_handle;
  3318. arr_index++;
  3319. phba->eh_sgl_hndl_avbl++;
  3320. }
  3321. psgl_handle++;
  3322. }
  3323. idx++;
  3324. }
  3325. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3326. "BM_%d : phba->io_sgl_hndl_avbl=%d"
  3327. "phba->eh_sgl_hndl_avbl=%d\n",
  3328. phba->io_sgl_hndl_avbl,
  3329. phba->eh_sgl_hndl_avbl);
  3330. mem_descr_sg = phba->init_mem;
  3331. mem_descr_sg += HWI_MEM_SGE;
  3332. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3333. "\n BM_%d : mem_descr_sg->num_elements=%d\n",
  3334. mem_descr_sg->num_elements);
  3335. arr_index = 0;
  3336. idx = 0;
  3337. while (idx < mem_descr_sg->num_elements) {
  3338. pfrag = mem_descr_sg->mem_array[idx].virtual_address;
  3339. for (i = 0;
  3340. i < (mem_descr_sg->mem_array[idx].size) /
  3341. (sizeof(struct iscsi_sge) * phba->params.num_sge_per_io);
  3342. i++) {
  3343. if (arr_index < phba->params.ios_per_ctrl)
  3344. psgl_handle = phba->io_sgl_hndl_base[arr_index];
  3345. else
  3346. psgl_handle = phba->eh_sgl_hndl_base[arr_index -
  3347. phba->params.ios_per_ctrl];
  3348. psgl_handle->pfrag = pfrag;
  3349. AMAP_SET_BITS(struct amap_iscsi_sge, addr_hi, pfrag, 0);
  3350. AMAP_SET_BITS(struct amap_iscsi_sge, addr_lo, pfrag, 0);
  3351. pfrag += phba->params.num_sge_per_io;
  3352. psgl_handle->sgl_index =
  3353. phba->fw_config.iscsi_icd_start + arr_index++;
  3354. }
  3355. idx++;
  3356. }
  3357. phba->io_sgl_free_index = 0;
  3358. phba->io_sgl_alloc_index = 0;
  3359. phba->eh_sgl_free_index = 0;
  3360. phba->eh_sgl_alloc_index = 0;
  3361. return 0;
  3362. }
  3363. static int hba_setup_cid_tbls(struct beiscsi_hba *phba)
  3364. {
  3365. int i, new_cid;
  3366. phba->cid_array = kzalloc(sizeof(void *) * phba->params.cxns_per_ctrl,
  3367. GFP_KERNEL);
  3368. if (!phba->cid_array) {
  3369. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3370. "BM_%d : Failed to allocate memory in "
  3371. "hba_setup_cid_tbls\n");
  3372. return -ENOMEM;
  3373. }
  3374. phba->ep_array = kzalloc(sizeof(struct iscsi_endpoint *) *
  3375. phba->params.cxns_per_ctrl * 2, GFP_KERNEL);
  3376. if (!phba->ep_array) {
  3377. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3378. "BM_%d : Failed to allocate memory in "
  3379. "hba_setup_cid_tbls\n");
  3380. kfree(phba->cid_array);
  3381. return -ENOMEM;
  3382. }
  3383. new_cid = phba->fw_config.iscsi_cid_start;
  3384. for (i = 0; i < phba->params.cxns_per_ctrl; i++) {
  3385. phba->cid_array[i] = new_cid;
  3386. new_cid += 2;
  3387. }
  3388. phba->avlbl_cids = phba->params.cxns_per_ctrl;
  3389. return 0;
  3390. }
  3391. static void hwi_enable_intr(struct beiscsi_hba *phba)
  3392. {
  3393. struct be_ctrl_info *ctrl = &phba->ctrl;
  3394. struct hwi_controller *phwi_ctrlr;
  3395. struct hwi_context_memory *phwi_context;
  3396. struct be_queue_info *eq;
  3397. u8 __iomem *addr;
  3398. u32 reg, i;
  3399. u32 enabled;
  3400. phwi_ctrlr = phba->phwi_ctrlr;
  3401. phwi_context = phwi_ctrlr->phwi_ctxt;
  3402. addr = (u8 __iomem *) ((u8 __iomem *) ctrl->pcicfg +
  3403. PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET);
  3404. reg = ioread32(addr);
  3405. enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  3406. if (!enabled) {
  3407. reg |= MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  3408. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3409. "BM_%d : reg =x%08x addr=%p\n", reg, addr);
  3410. iowrite32(reg, addr);
  3411. }
  3412. if (!phba->msix_enabled) {
  3413. eq = &phwi_context->be_eq[0].q;
  3414. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3415. "BM_%d : eq->id=%d\n", eq->id);
  3416. hwi_ring_eq_db(phba, eq->id, 0, 0, 1, 1);
  3417. } else {
  3418. for (i = 0; i <= phba->num_cpus; i++) {
  3419. eq = &phwi_context->be_eq[i].q;
  3420. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  3421. "BM_%d : eq->id=%d\n", eq->id);
  3422. hwi_ring_eq_db(phba, eq->id, 0, 0, 1, 1);
  3423. }
  3424. }
  3425. }
  3426. static void hwi_disable_intr(struct beiscsi_hba *phba)
  3427. {
  3428. struct be_ctrl_info *ctrl = &phba->ctrl;
  3429. u8 __iomem *addr = ctrl->pcicfg + PCICFG_MEMBAR_CTRL_INT_CTRL_OFFSET;
  3430. u32 reg = ioread32(addr);
  3431. u32 enabled = reg & MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  3432. if (enabled) {
  3433. reg &= ~MEMBAR_CTRL_INT_CTRL_HOSTINTR_MASK;
  3434. iowrite32(reg, addr);
  3435. } else
  3436. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  3437. "BM_%d : In hwi_disable_intr, Already Disabled\n");
  3438. }
  3439. /**
  3440. * beiscsi_get_boot_info()- Get the boot session info
  3441. * @phba: The device priv structure instance
  3442. *
  3443. * Get the boot target info and store in driver priv structure
  3444. *
  3445. * return values
  3446. * Success: 0
  3447. * Failure: Non-Zero Value
  3448. **/
  3449. static int beiscsi_get_boot_info(struct beiscsi_hba *phba)
  3450. {
  3451. struct be_cmd_get_session_resp *session_resp;
  3452. struct be_mcc_wrb *wrb;
  3453. struct be_dma_mem nonemb_cmd;
  3454. unsigned int tag, wrb_num;
  3455. unsigned short status, extd_status;
  3456. unsigned int s_handle;
  3457. struct be_queue_info *mccq = &phba->ctrl.mcc_obj.q;
  3458. int ret = -ENOMEM;
  3459. /* Get the session handle of the boot target */
  3460. ret = be_mgmt_get_boot_shandle(phba, &s_handle);
  3461. if (ret) {
  3462. beiscsi_log(phba, KERN_ERR,
  3463. BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG,
  3464. "BM_%d : No boot session\n");
  3465. return ret;
  3466. }
  3467. nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
  3468. sizeof(*session_resp),
  3469. &nonemb_cmd.dma);
  3470. if (nonemb_cmd.va == NULL) {
  3471. beiscsi_log(phba, KERN_ERR,
  3472. BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG,
  3473. "BM_%d : Failed to allocate memory for"
  3474. "beiscsi_get_session_info\n");
  3475. return -ENOMEM;
  3476. }
  3477. memset(nonemb_cmd.va, 0, sizeof(*session_resp));
  3478. tag = mgmt_get_session_info(phba, s_handle,
  3479. &nonemb_cmd);
  3480. if (!tag) {
  3481. beiscsi_log(phba, KERN_ERR,
  3482. BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG,
  3483. "BM_%d : beiscsi_get_session_info"
  3484. " Failed\n");
  3485. goto boot_freemem;
  3486. } else
  3487. wait_event_interruptible(phba->ctrl.mcc_wait[tag],
  3488. phba->ctrl.mcc_numtag[tag]);
  3489. wrb_num = (phba->ctrl.mcc_numtag[tag] & 0x00FF0000) >> 16;
  3490. extd_status = (phba->ctrl.mcc_numtag[tag] & 0x0000FF00) >> 8;
  3491. status = phba->ctrl.mcc_numtag[tag] & 0x000000FF;
  3492. if (status || extd_status) {
  3493. beiscsi_log(phba, KERN_ERR,
  3494. BEISCSI_LOG_INIT | BEISCSI_LOG_CONFIG,
  3495. "BM_%d : beiscsi_get_session_info Failed"
  3496. " status = %d extd_status = %d\n",
  3497. status, extd_status);
  3498. free_mcc_tag(&phba->ctrl, tag);
  3499. goto boot_freemem;
  3500. }
  3501. wrb = queue_get_wrb(mccq, wrb_num);
  3502. free_mcc_tag(&phba->ctrl, tag);
  3503. session_resp = nonemb_cmd.va ;
  3504. memcpy(&phba->boot_sess, &session_resp->session_info,
  3505. sizeof(struct mgmt_session_info));
  3506. ret = 0;
  3507. boot_freemem:
  3508. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  3509. nonemb_cmd.va, nonemb_cmd.dma);
  3510. return ret;
  3511. }
  3512. static void beiscsi_boot_release(void *data)
  3513. {
  3514. struct beiscsi_hba *phba = data;
  3515. scsi_host_put(phba->shost);
  3516. }
  3517. static int beiscsi_setup_boot_info(struct beiscsi_hba *phba)
  3518. {
  3519. struct iscsi_boot_kobj *boot_kobj;
  3520. /* get boot info using mgmt cmd */
  3521. if (beiscsi_get_boot_info(phba))
  3522. /* Try to see if we can carry on without this */
  3523. return 0;
  3524. phba->boot_kset = iscsi_boot_create_host_kset(phba->shost->host_no);
  3525. if (!phba->boot_kset)
  3526. return -ENOMEM;
  3527. /* get a ref because the show function will ref the phba */
  3528. if (!scsi_host_get(phba->shost))
  3529. goto free_kset;
  3530. boot_kobj = iscsi_boot_create_target(phba->boot_kset, 0, phba,
  3531. beiscsi_show_boot_tgt_info,
  3532. beiscsi_tgt_get_attr_visibility,
  3533. beiscsi_boot_release);
  3534. if (!boot_kobj)
  3535. goto put_shost;
  3536. if (!scsi_host_get(phba->shost))
  3537. goto free_kset;
  3538. boot_kobj = iscsi_boot_create_initiator(phba->boot_kset, 0, phba,
  3539. beiscsi_show_boot_ini_info,
  3540. beiscsi_ini_get_attr_visibility,
  3541. beiscsi_boot_release);
  3542. if (!boot_kobj)
  3543. goto put_shost;
  3544. if (!scsi_host_get(phba->shost))
  3545. goto free_kset;
  3546. boot_kobj = iscsi_boot_create_ethernet(phba->boot_kset, 0, phba,
  3547. beiscsi_show_boot_eth_info,
  3548. beiscsi_eth_get_attr_visibility,
  3549. beiscsi_boot_release);
  3550. if (!boot_kobj)
  3551. goto put_shost;
  3552. return 0;
  3553. put_shost:
  3554. scsi_host_put(phba->shost);
  3555. free_kset:
  3556. iscsi_boot_destroy_kset(phba->boot_kset);
  3557. return -ENOMEM;
  3558. }
  3559. static int beiscsi_init_port(struct beiscsi_hba *phba)
  3560. {
  3561. int ret;
  3562. ret = beiscsi_init_controller(phba);
  3563. if (ret < 0) {
  3564. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3565. "BM_%d : beiscsi_dev_probe - Failed in"
  3566. "beiscsi_init_controller\n");
  3567. return ret;
  3568. }
  3569. ret = beiscsi_init_sgl_handle(phba);
  3570. if (ret < 0) {
  3571. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3572. "BM_%d : beiscsi_dev_probe - Failed in"
  3573. "beiscsi_init_sgl_handle\n");
  3574. goto do_cleanup_ctrlr;
  3575. }
  3576. if (hba_setup_cid_tbls(phba)) {
  3577. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  3578. "BM_%d : Failed in hba_setup_cid_tbls\n");
  3579. kfree(phba->io_sgl_hndl_base);
  3580. kfree(phba->eh_sgl_hndl_base);
  3581. goto do_cleanup_ctrlr;
  3582. }
  3583. return ret;
  3584. do_cleanup_ctrlr:
  3585. hwi_cleanup(phba);
  3586. return ret;
  3587. }
  3588. static void hwi_purge_eq(struct beiscsi_hba *phba)
  3589. {
  3590. struct hwi_controller *phwi_ctrlr;
  3591. struct hwi_context_memory *phwi_context;
  3592. struct be_queue_info *eq;
  3593. struct be_eq_entry *eqe = NULL;
  3594. int i, eq_msix;
  3595. unsigned int num_processed;
  3596. phwi_ctrlr = phba->phwi_ctrlr;
  3597. phwi_context = phwi_ctrlr->phwi_ctxt;
  3598. if (phba->msix_enabled)
  3599. eq_msix = 1;
  3600. else
  3601. eq_msix = 0;
  3602. for (i = 0; i < (phba->num_cpus + eq_msix); i++) {
  3603. eq = &phwi_context->be_eq[i].q;
  3604. eqe = queue_tail_node(eq);
  3605. num_processed = 0;
  3606. while (eqe->dw[offsetof(struct amap_eq_entry, valid) / 32]
  3607. & EQE_VALID_MASK) {
  3608. AMAP_SET_BITS(struct amap_eq_entry, valid, eqe, 0);
  3609. queue_tail_inc(eq);
  3610. eqe = queue_tail_node(eq);
  3611. num_processed++;
  3612. }
  3613. if (num_processed)
  3614. hwi_ring_eq_db(phba, eq->id, 1, num_processed, 1, 1);
  3615. }
  3616. }
  3617. static void beiscsi_clean_port(struct beiscsi_hba *phba)
  3618. {
  3619. int mgmt_status;
  3620. mgmt_status = mgmt_epfw_cleanup(phba, CMD_CONNECTION_CHUTE_0);
  3621. if (mgmt_status)
  3622. beiscsi_log(phba, KERN_WARNING, BEISCSI_LOG_INIT,
  3623. "BM_%d : mgmt_epfw_cleanup FAILED\n");
  3624. hwi_purge_eq(phba);
  3625. hwi_cleanup(phba);
  3626. kfree(phba->io_sgl_hndl_base);
  3627. kfree(phba->eh_sgl_hndl_base);
  3628. kfree(phba->cid_array);
  3629. kfree(phba->ep_array);
  3630. }
  3631. /**
  3632. * beiscsi_cleanup_task()- Free driver resources of the task
  3633. * @task: ptr to the iscsi task
  3634. *
  3635. **/
  3636. static void beiscsi_cleanup_task(struct iscsi_task *task)
  3637. {
  3638. struct beiscsi_io_task *io_task = task->dd_data;
  3639. struct iscsi_conn *conn = task->conn;
  3640. struct beiscsi_conn *beiscsi_conn = conn->dd_data;
  3641. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3642. struct beiscsi_session *beiscsi_sess = beiscsi_conn->beiscsi_sess;
  3643. struct hwi_wrb_context *pwrb_context;
  3644. struct hwi_controller *phwi_ctrlr;
  3645. phwi_ctrlr = phba->phwi_ctrlr;
  3646. pwrb_context = &phwi_ctrlr->wrb_context[beiscsi_conn->beiscsi_conn_cid
  3647. - phba->fw_config.iscsi_cid_start];
  3648. if (io_task->cmd_bhs) {
  3649. pci_pool_free(beiscsi_sess->bhs_pool, io_task->cmd_bhs,
  3650. io_task->bhs_pa.u.a64.address);
  3651. io_task->cmd_bhs = NULL;
  3652. }
  3653. if (task->sc) {
  3654. if (io_task->pwrb_handle) {
  3655. free_wrb_handle(phba, pwrb_context,
  3656. io_task->pwrb_handle);
  3657. io_task->pwrb_handle = NULL;
  3658. }
  3659. if (io_task->psgl_handle) {
  3660. spin_lock(&phba->io_sgl_lock);
  3661. free_io_sgl_handle(phba, io_task->psgl_handle);
  3662. spin_unlock(&phba->io_sgl_lock);
  3663. io_task->psgl_handle = NULL;
  3664. }
  3665. } else {
  3666. if (!beiscsi_conn->login_in_progress) {
  3667. if (io_task->pwrb_handle) {
  3668. free_wrb_handle(phba, pwrb_context,
  3669. io_task->pwrb_handle);
  3670. io_task->pwrb_handle = NULL;
  3671. }
  3672. if (io_task->psgl_handle) {
  3673. spin_lock(&phba->mgmt_sgl_lock);
  3674. free_mgmt_sgl_handle(phba,
  3675. io_task->psgl_handle);
  3676. spin_unlock(&phba->mgmt_sgl_lock);
  3677. io_task->psgl_handle = NULL;
  3678. }
  3679. if (io_task->mtask_addr) {
  3680. pci_unmap_single(phba->pcidev,
  3681. io_task->mtask_addr,
  3682. io_task->mtask_data_count,
  3683. PCI_DMA_TODEVICE);
  3684. io_task->mtask_addr = 0;
  3685. }
  3686. }
  3687. }
  3688. }
  3689. void
  3690. beiscsi_offload_connection(struct beiscsi_conn *beiscsi_conn,
  3691. struct beiscsi_offload_params *params)
  3692. {
  3693. struct wrb_handle *pwrb_handle;
  3694. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3695. struct iscsi_task *task = beiscsi_conn->task;
  3696. struct iscsi_session *session = task->conn->session;
  3697. u32 doorbell = 0;
  3698. /*
  3699. * We can always use 0 here because it is reserved by libiscsi for
  3700. * login/startup related tasks.
  3701. */
  3702. beiscsi_conn->login_in_progress = 0;
  3703. spin_lock_bh(&session->lock);
  3704. beiscsi_cleanup_task(task);
  3705. spin_unlock_bh(&session->lock);
  3706. pwrb_handle = alloc_wrb_handle(phba, (beiscsi_conn->beiscsi_conn_cid -
  3707. phba->fw_config.iscsi_cid_start));
  3708. /* Check for the adapter family */
  3709. if (chip_skh_r(phba->pcidev))
  3710. beiscsi_offload_cxn_v2(params, pwrb_handle);
  3711. else
  3712. beiscsi_offload_cxn_v0(params, pwrb_handle,
  3713. phba->init_mem);
  3714. be_dws_le_to_cpu(pwrb_handle->pwrb,
  3715. sizeof(struct iscsi_target_context_update_wrb));
  3716. doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK;
  3717. doorbell |= (pwrb_handle->wrb_index & DB_DEF_PDU_WRB_INDEX_MASK)
  3718. << DB_DEF_PDU_WRB_INDEX_SHIFT;
  3719. doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
  3720. iowrite32(doorbell, phba->db_va + DB_TXULP0_OFFSET);
  3721. }
  3722. static void beiscsi_parse_pdu(struct iscsi_conn *conn, itt_t itt,
  3723. int *index, int *age)
  3724. {
  3725. *index = (int)itt;
  3726. if (age)
  3727. *age = conn->session->age;
  3728. }
  3729. /**
  3730. * beiscsi_alloc_pdu - allocates pdu and related resources
  3731. * @task: libiscsi task
  3732. * @opcode: opcode of pdu for task
  3733. *
  3734. * This is called with the session lock held. It will allocate
  3735. * the wrb and sgl if needed for the command. And it will prep
  3736. * the pdu's itt. beiscsi_parse_pdu will later translate
  3737. * the pdu itt to the libiscsi task itt.
  3738. */
  3739. static int beiscsi_alloc_pdu(struct iscsi_task *task, uint8_t opcode)
  3740. {
  3741. struct beiscsi_io_task *io_task = task->dd_data;
  3742. struct iscsi_conn *conn = task->conn;
  3743. struct beiscsi_conn *beiscsi_conn = conn->dd_data;
  3744. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3745. struct hwi_wrb_context *pwrb_context;
  3746. struct hwi_controller *phwi_ctrlr;
  3747. itt_t itt;
  3748. struct beiscsi_session *beiscsi_sess = beiscsi_conn->beiscsi_sess;
  3749. dma_addr_t paddr;
  3750. io_task->cmd_bhs = pci_pool_alloc(beiscsi_sess->bhs_pool,
  3751. GFP_ATOMIC, &paddr);
  3752. if (!io_task->cmd_bhs)
  3753. return -ENOMEM;
  3754. io_task->bhs_pa.u.a64.address = paddr;
  3755. io_task->libiscsi_itt = (itt_t)task->itt;
  3756. io_task->conn = beiscsi_conn;
  3757. task->hdr = (struct iscsi_hdr *)&io_task->cmd_bhs->iscsi_hdr;
  3758. task->hdr_max = sizeof(struct be_cmd_bhs);
  3759. io_task->psgl_handle = NULL;
  3760. io_task->pwrb_handle = NULL;
  3761. if (task->sc) {
  3762. spin_lock(&phba->io_sgl_lock);
  3763. io_task->psgl_handle = alloc_io_sgl_handle(phba);
  3764. spin_unlock(&phba->io_sgl_lock);
  3765. if (!io_task->psgl_handle) {
  3766. beiscsi_log(phba, KERN_ERR,
  3767. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  3768. "BM_%d : Alloc of IO_SGL_ICD Failed"
  3769. "for the CID : %d\n",
  3770. beiscsi_conn->beiscsi_conn_cid);
  3771. goto free_hndls;
  3772. }
  3773. io_task->pwrb_handle = alloc_wrb_handle(phba,
  3774. beiscsi_conn->beiscsi_conn_cid -
  3775. phba->fw_config.iscsi_cid_start);
  3776. if (!io_task->pwrb_handle) {
  3777. beiscsi_log(phba, KERN_ERR,
  3778. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  3779. "BM_%d : Alloc of WRB_HANDLE Failed"
  3780. "for the CID : %d\n",
  3781. beiscsi_conn->beiscsi_conn_cid);
  3782. goto free_io_hndls;
  3783. }
  3784. } else {
  3785. io_task->scsi_cmnd = NULL;
  3786. if ((opcode & ISCSI_OPCODE_MASK) == ISCSI_OP_LOGIN) {
  3787. if (!beiscsi_conn->login_in_progress) {
  3788. spin_lock(&phba->mgmt_sgl_lock);
  3789. io_task->psgl_handle = (struct sgl_handle *)
  3790. alloc_mgmt_sgl_handle(phba);
  3791. spin_unlock(&phba->mgmt_sgl_lock);
  3792. if (!io_task->psgl_handle) {
  3793. beiscsi_log(phba, KERN_ERR,
  3794. BEISCSI_LOG_IO |
  3795. BEISCSI_LOG_CONFIG,
  3796. "BM_%d : Alloc of MGMT_SGL_ICD Failed"
  3797. "for the CID : %d\n",
  3798. beiscsi_conn->
  3799. beiscsi_conn_cid);
  3800. goto free_hndls;
  3801. }
  3802. beiscsi_conn->login_in_progress = 1;
  3803. beiscsi_conn->plogin_sgl_handle =
  3804. io_task->psgl_handle;
  3805. io_task->pwrb_handle =
  3806. alloc_wrb_handle(phba,
  3807. beiscsi_conn->beiscsi_conn_cid -
  3808. phba->fw_config.iscsi_cid_start);
  3809. if (!io_task->pwrb_handle) {
  3810. beiscsi_log(phba, KERN_ERR,
  3811. BEISCSI_LOG_IO |
  3812. BEISCSI_LOG_CONFIG,
  3813. "BM_%d : Alloc of WRB_HANDLE Failed"
  3814. "for the CID : %d\n",
  3815. beiscsi_conn->
  3816. beiscsi_conn_cid);
  3817. goto free_mgmt_hndls;
  3818. }
  3819. beiscsi_conn->plogin_wrb_handle =
  3820. io_task->pwrb_handle;
  3821. } else {
  3822. io_task->psgl_handle =
  3823. beiscsi_conn->plogin_sgl_handle;
  3824. io_task->pwrb_handle =
  3825. beiscsi_conn->plogin_wrb_handle;
  3826. }
  3827. beiscsi_conn->task = task;
  3828. } else {
  3829. spin_lock(&phba->mgmt_sgl_lock);
  3830. io_task->psgl_handle = alloc_mgmt_sgl_handle(phba);
  3831. spin_unlock(&phba->mgmt_sgl_lock);
  3832. if (!io_task->psgl_handle) {
  3833. beiscsi_log(phba, KERN_ERR,
  3834. BEISCSI_LOG_IO |
  3835. BEISCSI_LOG_CONFIG,
  3836. "BM_%d : Alloc of MGMT_SGL_ICD Failed"
  3837. "for the CID : %d\n",
  3838. beiscsi_conn->
  3839. beiscsi_conn_cid);
  3840. goto free_hndls;
  3841. }
  3842. io_task->pwrb_handle =
  3843. alloc_wrb_handle(phba,
  3844. beiscsi_conn->beiscsi_conn_cid -
  3845. phba->fw_config.iscsi_cid_start);
  3846. if (!io_task->pwrb_handle) {
  3847. beiscsi_log(phba, KERN_ERR,
  3848. BEISCSI_LOG_IO | BEISCSI_LOG_CONFIG,
  3849. "BM_%d : Alloc of WRB_HANDLE Failed"
  3850. "for the CID : %d\n",
  3851. beiscsi_conn->beiscsi_conn_cid);
  3852. goto free_mgmt_hndls;
  3853. }
  3854. }
  3855. }
  3856. itt = (itt_t) cpu_to_be32(((unsigned int)io_task->pwrb_handle->
  3857. wrb_index << 16) | (unsigned int)
  3858. (io_task->psgl_handle->sgl_index));
  3859. io_task->pwrb_handle->pio_handle = task;
  3860. io_task->cmd_bhs->iscsi_hdr.itt = itt;
  3861. return 0;
  3862. free_io_hndls:
  3863. spin_lock(&phba->io_sgl_lock);
  3864. free_io_sgl_handle(phba, io_task->psgl_handle);
  3865. spin_unlock(&phba->io_sgl_lock);
  3866. goto free_hndls;
  3867. free_mgmt_hndls:
  3868. spin_lock(&phba->mgmt_sgl_lock);
  3869. free_mgmt_sgl_handle(phba, io_task->psgl_handle);
  3870. spin_unlock(&phba->mgmt_sgl_lock);
  3871. free_hndls:
  3872. phwi_ctrlr = phba->phwi_ctrlr;
  3873. pwrb_context = &phwi_ctrlr->wrb_context[
  3874. beiscsi_conn->beiscsi_conn_cid -
  3875. phba->fw_config.iscsi_cid_start];
  3876. if (io_task->pwrb_handle)
  3877. free_wrb_handle(phba, pwrb_context, io_task->pwrb_handle);
  3878. io_task->pwrb_handle = NULL;
  3879. pci_pool_free(beiscsi_sess->bhs_pool, io_task->cmd_bhs,
  3880. io_task->bhs_pa.u.a64.address);
  3881. io_task->cmd_bhs = NULL;
  3882. return -ENOMEM;
  3883. }
  3884. int beiscsi_iotask_v2(struct iscsi_task *task, struct scatterlist *sg,
  3885. unsigned int num_sg, unsigned int xferlen,
  3886. unsigned int writedir)
  3887. {
  3888. struct beiscsi_io_task *io_task = task->dd_data;
  3889. struct iscsi_conn *conn = task->conn;
  3890. struct beiscsi_conn *beiscsi_conn = conn->dd_data;
  3891. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3892. struct iscsi_wrb *pwrb = NULL;
  3893. unsigned int doorbell = 0;
  3894. pwrb = io_task->pwrb_handle->pwrb;
  3895. memset(pwrb, 0, sizeof(*pwrb));
  3896. io_task->cmd_bhs->iscsi_hdr.exp_statsn = 0;
  3897. io_task->bhs_len = sizeof(struct be_cmd_bhs);
  3898. if (writedir) {
  3899. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, type, pwrb,
  3900. INI_WR_CMD);
  3901. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, dsp, pwrb, 1);
  3902. } else {
  3903. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, type, pwrb,
  3904. INI_RD_CMD);
  3905. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, dsp, pwrb, 0);
  3906. }
  3907. io_task->wrb_type = AMAP_GET_BITS(struct amap_iscsi_wrb_v2,
  3908. type, pwrb);
  3909. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, lun, pwrb,
  3910. cpu_to_be16(*(unsigned short *)
  3911. &io_task->cmd_bhs->iscsi_hdr.lun));
  3912. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, r2t_exp_dtl, pwrb, xferlen);
  3913. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, wrb_idx, pwrb,
  3914. io_task->pwrb_handle->wrb_index);
  3915. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, cmdsn_itt, pwrb,
  3916. be32_to_cpu(task->cmdsn));
  3917. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sgl_idx, pwrb,
  3918. io_task->psgl_handle->sgl_index);
  3919. hwi_write_sgl_v2(pwrb, sg, num_sg, io_task);
  3920. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, ptr2nextwrb, pwrb,
  3921. io_task->pwrb_handle->nxt_wrb_index);
  3922. be_dws_le_to_cpu(pwrb, sizeof(struct iscsi_wrb));
  3923. doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK;
  3924. doorbell |= (io_task->pwrb_handle->wrb_index &
  3925. DB_DEF_PDU_WRB_INDEX_MASK) <<
  3926. DB_DEF_PDU_WRB_INDEX_SHIFT;
  3927. doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
  3928. iowrite32(doorbell, phba->db_va + DB_TXULP0_OFFSET);
  3929. return 0;
  3930. }
  3931. static int beiscsi_iotask(struct iscsi_task *task, struct scatterlist *sg,
  3932. unsigned int num_sg, unsigned int xferlen,
  3933. unsigned int writedir)
  3934. {
  3935. struct beiscsi_io_task *io_task = task->dd_data;
  3936. struct iscsi_conn *conn = task->conn;
  3937. struct beiscsi_conn *beiscsi_conn = conn->dd_data;
  3938. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3939. struct iscsi_wrb *pwrb = NULL;
  3940. unsigned int doorbell = 0;
  3941. pwrb = io_task->pwrb_handle->pwrb;
  3942. io_task->cmd_bhs->iscsi_hdr.exp_statsn = 0;
  3943. io_task->bhs_len = sizeof(struct be_cmd_bhs);
  3944. if (writedir) {
  3945. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  3946. INI_WR_CMD);
  3947. AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 1);
  3948. } else {
  3949. AMAP_SET_BITS(struct amap_iscsi_wrb, type, pwrb,
  3950. INI_RD_CMD);
  3951. AMAP_SET_BITS(struct amap_iscsi_wrb, dsp, pwrb, 0);
  3952. }
  3953. io_task->wrb_type = AMAP_GET_BITS(struct amap_iscsi_wrb,
  3954. type, pwrb);
  3955. AMAP_SET_BITS(struct amap_iscsi_wrb, lun, pwrb,
  3956. cpu_to_be16(*(unsigned short *)
  3957. &io_task->cmd_bhs->iscsi_hdr.lun));
  3958. AMAP_SET_BITS(struct amap_iscsi_wrb, r2t_exp_dtl, pwrb, xferlen);
  3959. AMAP_SET_BITS(struct amap_iscsi_wrb, wrb_idx, pwrb,
  3960. io_task->pwrb_handle->wrb_index);
  3961. AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb,
  3962. be32_to_cpu(task->cmdsn));
  3963. AMAP_SET_BITS(struct amap_iscsi_wrb, sgl_icd_idx, pwrb,
  3964. io_task->psgl_handle->sgl_index);
  3965. hwi_write_sgl(pwrb, sg, num_sg, io_task);
  3966. AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb, pwrb,
  3967. io_task->pwrb_handle->nxt_wrb_index);
  3968. be_dws_le_to_cpu(pwrb, sizeof(struct iscsi_wrb));
  3969. doorbell |= beiscsi_conn->beiscsi_conn_cid & DB_WRB_POST_CID_MASK;
  3970. doorbell |= (io_task->pwrb_handle->wrb_index &
  3971. DB_DEF_PDU_WRB_INDEX_MASK) << DB_DEF_PDU_WRB_INDEX_SHIFT;
  3972. doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
  3973. iowrite32(doorbell, phba->db_va + DB_TXULP0_OFFSET);
  3974. return 0;
  3975. }
  3976. static int beiscsi_mtask(struct iscsi_task *task)
  3977. {
  3978. struct beiscsi_io_task *io_task = task->dd_data;
  3979. struct iscsi_conn *conn = task->conn;
  3980. struct beiscsi_conn *beiscsi_conn = conn->dd_data;
  3981. struct beiscsi_hba *phba = beiscsi_conn->phba;
  3982. struct iscsi_wrb *pwrb = NULL;
  3983. unsigned int doorbell = 0;
  3984. unsigned int cid;
  3985. unsigned int pwrb_typeoffset = 0;
  3986. cid = beiscsi_conn->beiscsi_conn_cid;
  3987. pwrb = io_task->pwrb_handle->pwrb;
  3988. memset(pwrb, 0, sizeof(*pwrb));
  3989. if (chip_skh_r(phba->pcidev)) {
  3990. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, cmdsn_itt, pwrb,
  3991. be32_to_cpu(task->cmdsn));
  3992. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, wrb_idx, pwrb,
  3993. io_task->pwrb_handle->wrb_index);
  3994. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, sgl_idx, pwrb,
  3995. io_task->psgl_handle->sgl_index);
  3996. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, r2t_exp_dtl, pwrb,
  3997. task->data_count);
  3998. AMAP_SET_BITS(struct amap_iscsi_wrb_v2, ptr2nextwrb, pwrb,
  3999. io_task->pwrb_handle->nxt_wrb_index);
  4000. pwrb_typeoffset = SKH_WRB_TYPE_OFFSET;
  4001. } else {
  4002. AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb,
  4003. be32_to_cpu(task->cmdsn));
  4004. AMAP_SET_BITS(struct amap_iscsi_wrb, wrb_idx, pwrb,
  4005. io_task->pwrb_handle->wrb_index);
  4006. AMAP_SET_BITS(struct amap_iscsi_wrb, sgl_icd_idx, pwrb,
  4007. io_task->psgl_handle->sgl_index);
  4008. AMAP_SET_BITS(struct amap_iscsi_wrb, r2t_exp_dtl, pwrb,
  4009. task->data_count);
  4010. AMAP_SET_BITS(struct amap_iscsi_wrb, ptr2nextwrb, pwrb,
  4011. io_task->pwrb_handle->nxt_wrb_index);
  4012. pwrb_typeoffset = BE_WRB_TYPE_OFFSET;
  4013. }
  4014. switch (task->hdr->opcode & ISCSI_OPCODE_MASK) {
  4015. case ISCSI_OP_LOGIN:
  4016. AMAP_SET_BITS(struct amap_iscsi_wrb, cmdsn_itt, pwrb, 1);
  4017. ADAPTER_SET_WRB_TYPE(pwrb, TGT_DM_CMD, pwrb_typeoffset);
  4018. hwi_write_buffer(pwrb, task);
  4019. break;
  4020. case ISCSI_OP_NOOP_OUT:
  4021. if (task->hdr->ttt != ISCSI_RESERVED_TAG) {
  4022. ADAPTER_SET_WRB_TYPE(pwrb, TGT_DM_CMD, pwrb_typeoffset);
  4023. if (chip_skh_r(phba->pcidev))
  4024. AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
  4025. dmsg, pwrb, 1);
  4026. else
  4027. AMAP_SET_BITS(struct amap_iscsi_wrb,
  4028. dmsg, pwrb, 1);
  4029. } else {
  4030. ADAPTER_SET_WRB_TYPE(pwrb, INI_RD_CMD, pwrb_typeoffset);
  4031. if (chip_skh_r(phba->pcidev))
  4032. AMAP_SET_BITS(struct amap_iscsi_wrb_v2,
  4033. dmsg, pwrb, 0);
  4034. else
  4035. AMAP_SET_BITS(struct amap_iscsi_wrb,
  4036. dmsg, pwrb, 0);
  4037. }
  4038. hwi_write_buffer(pwrb, task);
  4039. break;
  4040. case ISCSI_OP_TEXT:
  4041. ADAPTER_SET_WRB_TYPE(pwrb, TGT_DM_CMD, pwrb_typeoffset);
  4042. hwi_write_buffer(pwrb, task);
  4043. break;
  4044. case ISCSI_OP_SCSI_TMFUNC:
  4045. ADAPTER_SET_WRB_TYPE(pwrb, INI_TMF_CMD, pwrb_typeoffset);
  4046. hwi_write_buffer(pwrb, task);
  4047. break;
  4048. case ISCSI_OP_LOGOUT:
  4049. ADAPTER_SET_WRB_TYPE(pwrb, HWH_TYPE_LOGOUT, pwrb_typeoffset);
  4050. hwi_write_buffer(pwrb, task);
  4051. break;
  4052. default:
  4053. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
  4054. "BM_%d : opcode =%d Not supported\n",
  4055. task->hdr->opcode & ISCSI_OPCODE_MASK);
  4056. return -EINVAL;
  4057. }
  4058. /* Set the task type */
  4059. io_task->wrb_type = (chip_skh_r(phba->pcidev)) ?
  4060. AMAP_GET_BITS(struct amap_iscsi_wrb_v2, type, pwrb) :
  4061. AMAP_GET_BITS(struct amap_iscsi_wrb, type, pwrb);
  4062. doorbell |= cid & DB_WRB_POST_CID_MASK;
  4063. doorbell |= (io_task->pwrb_handle->wrb_index &
  4064. DB_DEF_PDU_WRB_INDEX_MASK) << DB_DEF_PDU_WRB_INDEX_SHIFT;
  4065. doorbell |= 1 << DB_DEF_PDU_NUM_POSTED_SHIFT;
  4066. iowrite32(doorbell, phba->db_va + DB_TXULP0_OFFSET);
  4067. return 0;
  4068. }
  4069. static int beiscsi_task_xmit(struct iscsi_task *task)
  4070. {
  4071. struct beiscsi_io_task *io_task = task->dd_data;
  4072. struct scsi_cmnd *sc = task->sc;
  4073. struct beiscsi_hba *phba = NULL;
  4074. struct scatterlist *sg;
  4075. int num_sg;
  4076. unsigned int writedir = 0, xferlen = 0;
  4077. phba = ((struct beiscsi_conn *)task->conn->dd_data)->phba;
  4078. if (!sc)
  4079. return beiscsi_mtask(task);
  4080. io_task->scsi_cmnd = sc;
  4081. num_sg = scsi_dma_map(sc);
  4082. if (num_sg < 0) {
  4083. struct iscsi_conn *conn = task->conn;
  4084. struct beiscsi_hba *phba = NULL;
  4085. phba = ((struct beiscsi_conn *)conn->dd_data)->phba;
  4086. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_IO,
  4087. "BM_%d : scsi_dma_map Failed\n");
  4088. return num_sg;
  4089. }
  4090. xferlen = scsi_bufflen(sc);
  4091. sg = scsi_sglist(sc);
  4092. if (sc->sc_data_direction == DMA_TO_DEVICE)
  4093. writedir = 1;
  4094. else
  4095. writedir = 0;
  4096. return phba->iotask_fn(task, sg, num_sg, xferlen, writedir);
  4097. }
  4098. /**
  4099. * beiscsi_bsg_request - handle bsg request from ISCSI transport
  4100. * @job: job to handle
  4101. */
  4102. static int beiscsi_bsg_request(struct bsg_job *job)
  4103. {
  4104. struct Scsi_Host *shost;
  4105. struct beiscsi_hba *phba;
  4106. struct iscsi_bsg_request *bsg_req = job->request;
  4107. int rc = -EINVAL;
  4108. unsigned int tag;
  4109. struct be_dma_mem nonemb_cmd;
  4110. struct be_cmd_resp_hdr *resp;
  4111. struct iscsi_bsg_reply *bsg_reply = job->reply;
  4112. unsigned short status, extd_status;
  4113. shost = iscsi_job_to_shost(job);
  4114. phba = iscsi_host_priv(shost);
  4115. switch (bsg_req->msgcode) {
  4116. case ISCSI_BSG_HST_VENDOR:
  4117. nonemb_cmd.va = pci_alloc_consistent(phba->ctrl.pdev,
  4118. job->request_payload.payload_len,
  4119. &nonemb_cmd.dma);
  4120. if (nonemb_cmd.va == NULL) {
  4121. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
  4122. "BM_%d : Failed to allocate memory for "
  4123. "beiscsi_bsg_request\n");
  4124. return -ENOMEM;
  4125. }
  4126. tag = mgmt_vendor_specific_fw_cmd(&phba->ctrl, phba, job,
  4127. &nonemb_cmd);
  4128. if (!tag) {
  4129. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
  4130. "BM_%d : MBX Tag Allocation Failed\n");
  4131. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  4132. nonemb_cmd.va, nonemb_cmd.dma);
  4133. return -EAGAIN;
  4134. } else
  4135. wait_event_interruptible(phba->ctrl.mcc_wait[tag],
  4136. phba->ctrl.mcc_numtag[tag]);
  4137. extd_status = (phba->ctrl.mcc_numtag[tag] & 0x0000FF00) >> 8;
  4138. status = phba->ctrl.mcc_numtag[tag] & 0x000000FF;
  4139. free_mcc_tag(&phba->ctrl, tag);
  4140. resp = (struct be_cmd_resp_hdr *)nonemb_cmd.va;
  4141. sg_copy_from_buffer(job->reply_payload.sg_list,
  4142. job->reply_payload.sg_cnt,
  4143. nonemb_cmd.va, (resp->response_length
  4144. + sizeof(*resp)));
  4145. bsg_reply->reply_payload_rcv_len = resp->response_length;
  4146. bsg_reply->result = status;
  4147. bsg_job_done(job, bsg_reply->result,
  4148. bsg_reply->reply_payload_rcv_len);
  4149. pci_free_consistent(phba->ctrl.pdev, nonemb_cmd.size,
  4150. nonemb_cmd.va, nonemb_cmd.dma);
  4151. if (status || extd_status) {
  4152. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
  4153. "BM_%d : MBX Cmd Failed"
  4154. " status = %d extd_status = %d\n",
  4155. status, extd_status);
  4156. return -EIO;
  4157. } else {
  4158. rc = 0;
  4159. }
  4160. break;
  4161. default:
  4162. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_CONFIG,
  4163. "BM_%d : Unsupported bsg command: 0x%x\n",
  4164. bsg_req->msgcode);
  4165. break;
  4166. }
  4167. return rc;
  4168. }
  4169. void beiscsi_hba_attrs_init(struct beiscsi_hba *phba)
  4170. {
  4171. /* Set the logging parameter */
  4172. beiscsi_log_enable_init(phba, beiscsi_log_enable);
  4173. }
  4174. /*
  4175. * beiscsi_quiesce()- Cleanup Driver resources
  4176. * @phba: Instance Priv structure
  4177. *
  4178. * Free the OS and HW resources held by the driver
  4179. **/
  4180. static void beiscsi_quiesce(struct beiscsi_hba *phba)
  4181. {
  4182. struct hwi_controller *phwi_ctrlr;
  4183. struct hwi_context_memory *phwi_context;
  4184. struct be_eq_obj *pbe_eq;
  4185. unsigned int i, msix_vec;
  4186. phwi_ctrlr = phba->phwi_ctrlr;
  4187. phwi_context = phwi_ctrlr->phwi_ctxt;
  4188. hwi_disable_intr(phba);
  4189. if (phba->msix_enabled) {
  4190. for (i = 0; i <= phba->num_cpus; i++) {
  4191. msix_vec = phba->msix_entries[i].vector;
  4192. free_irq(msix_vec, &phwi_context->be_eq[i]);
  4193. kfree(phba->msi_name[i]);
  4194. }
  4195. } else
  4196. if (phba->pcidev->irq)
  4197. free_irq(phba->pcidev->irq, phba);
  4198. pci_disable_msix(phba->pcidev);
  4199. destroy_workqueue(phba->wq);
  4200. if (blk_iopoll_enabled)
  4201. for (i = 0; i < phba->num_cpus; i++) {
  4202. pbe_eq = &phwi_context->be_eq[i];
  4203. blk_iopoll_disable(&pbe_eq->iopoll);
  4204. }
  4205. beiscsi_clean_port(phba);
  4206. beiscsi_free_mem(phba);
  4207. beiscsi_unmap_pci_function(phba);
  4208. pci_free_consistent(phba->pcidev,
  4209. phba->ctrl.mbox_mem_alloced.size,
  4210. phba->ctrl.mbox_mem_alloced.va,
  4211. phba->ctrl.mbox_mem_alloced.dma);
  4212. }
  4213. static void beiscsi_remove(struct pci_dev *pcidev)
  4214. {
  4215. struct beiscsi_hba *phba = NULL;
  4216. phba = pci_get_drvdata(pcidev);
  4217. if (!phba) {
  4218. dev_err(&pcidev->dev, "beiscsi_remove called with no phba\n");
  4219. return;
  4220. }
  4221. beiscsi_destroy_def_ifaces(phba);
  4222. beiscsi_quiesce(phba);
  4223. iscsi_boot_destroy_kset(phba->boot_kset);
  4224. iscsi_host_remove(phba->shost);
  4225. pci_dev_put(phba->pcidev);
  4226. iscsi_host_free(phba->shost);
  4227. pci_disable_device(pcidev);
  4228. }
  4229. static void beiscsi_shutdown(struct pci_dev *pcidev)
  4230. {
  4231. struct beiscsi_hba *phba = NULL;
  4232. phba = (struct beiscsi_hba *)pci_get_drvdata(pcidev);
  4233. if (!phba) {
  4234. dev_err(&pcidev->dev, "beiscsi_shutdown called with no phba\n");
  4235. return;
  4236. }
  4237. beiscsi_quiesce(phba);
  4238. pci_disable_device(pcidev);
  4239. }
  4240. static void beiscsi_msix_enable(struct beiscsi_hba *phba)
  4241. {
  4242. int i, status;
  4243. for (i = 0; i <= phba->num_cpus; i++)
  4244. phba->msix_entries[i].entry = i;
  4245. status = pci_enable_msix(phba->pcidev, phba->msix_entries,
  4246. (phba->num_cpus + 1));
  4247. if (!status)
  4248. phba->msix_enabled = true;
  4249. return;
  4250. }
  4251. static int __devinit beiscsi_dev_probe(struct pci_dev *pcidev,
  4252. const struct pci_device_id *id)
  4253. {
  4254. struct beiscsi_hba *phba = NULL;
  4255. struct hwi_controller *phwi_ctrlr;
  4256. struct hwi_context_memory *phwi_context;
  4257. struct be_eq_obj *pbe_eq;
  4258. int ret, i;
  4259. ret = beiscsi_enable_pci(pcidev);
  4260. if (ret < 0) {
  4261. dev_err(&pcidev->dev,
  4262. "beiscsi_dev_probe - Failed to enable pci device\n");
  4263. return ret;
  4264. }
  4265. phba = beiscsi_hba_alloc(pcidev);
  4266. if (!phba) {
  4267. dev_err(&pcidev->dev,
  4268. "beiscsi_dev_probe - Failed in beiscsi_hba_alloc\n");
  4269. goto disable_pci;
  4270. }
  4271. /* Initialize Driver configuration Paramters */
  4272. beiscsi_hba_attrs_init(phba);
  4273. switch (pcidev->device) {
  4274. case BE_DEVICE_ID1:
  4275. case OC_DEVICE_ID1:
  4276. case OC_DEVICE_ID2:
  4277. phba->generation = BE_GEN2;
  4278. phba->iotask_fn = beiscsi_iotask;
  4279. break;
  4280. case BE_DEVICE_ID2:
  4281. case OC_DEVICE_ID3:
  4282. phba->generation = BE_GEN3;
  4283. phba->iotask_fn = beiscsi_iotask;
  4284. break;
  4285. case OC_SKH_ID1:
  4286. phba->generation = BE_GEN4;
  4287. phba->iotask_fn = beiscsi_iotask_v2;
  4288. default:
  4289. phba->generation = 0;
  4290. }
  4291. if (enable_msix)
  4292. find_num_cpus(phba);
  4293. else
  4294. phba->num_cpus = 1;
  4295. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  4296. "BM_%d : num_cpus = %d\n",
  4297. phba->num_cpus);
  4298. if (enable_msix) {
  4299. beiscsi_msix_enable(phba);
  4300. if (!phba->msix_enabled)
  4301. phba->num_cpus = 1;
  4302. }
  4303. ret = be_ctrl_init(phba, pcidev);
  4304. if (ret) {
  4305. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4306. "BM_%d : beiscsi_dev_probe-"
  4307. "Failed in be_ctrl_init\n");
  4308. goto hba_free;
  4309. }
  4310. ret = beiscsi_cmd_reset_function(phba);
  4311. if (ret) {
  4312. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4313. "BM_%d : Reset Failed. Aborting Crashdump\n");
  4314. goto hba_free;
  4315. }
  4316. ret = be_chk_reset_complete(phba);
  4317. if (ret) {
  4318. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4319. "BM_%d : Failed to get out of reset."
  4320. "Aborting Crashdump\n");
  4321. goto hba_free;
  4322. }
  4323. spin_lock_init(&phba->io_sgl_lock);
  4324. spin_lock_init(&phba->mgmt_sgl_lock);
  4325. spin_lock_init(&phba->isr_lock);
  4326. ret = mgmt_get_fw_config(&phba->ctrl, phba);
  4327. if (ret != 0) {
  4328. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4329. "BM_%d : Error getting fw config\n");
  4330. goto free_port;
  4331. }
  4332. phba->shost->max_id = phba->fw_config.iscsi_cid_count;
  4333. beiscsi_get_params(phba);
  4334. phba->shost->can_queue = phba->params.ios_per_ctrl;
  4335. ret = beiscsi_init_port(phba);
  4336. if (ret < 0) {
  4337. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4338. "BM_%d : beiscsi_dev_probe-"
  4339. "Failed in beiscsi_init_port\n");
  4340. goto free_port;
  4341. }
  4342. for (i = 0; i < MAX_MCC_CMD ; i++) {
  4343. init_waitqueue_head(&phba->ctrl.mcc_wait[i + 1]);
  4344. phba->ctrl.mcc_tag[i] = i + 1;
  4345. phba->ctrl.mcc_numtag[i + 1] = 0;
  4346. phba->ctrl.mcc_tag_available++;
  4347. }
  4348. phba->ctrl.mcc_alloc_index = phba->ctrl.mcc_free_index = 0;
  4349. snprintf(phba->wq_name, sizeof(phba->wq_name), "beiscsi_%02x_wq",
  4350. phba->shost->host_no);
  4351. phba->wq = alloc_workqueue(phba->wq_name, WQ_MEM_RECLAIM, 1);
  4352. if (!phba->wq) {
  4353. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4354. "BM_%d : beiscsi_dev_probe-"
  4355. "Failed to allocate work queue\n");
  4356. goto free_twq;
  4357. }
  4358. phwi_ctrlr = phba->phwi_ctrlr;
  4359. phwi_context = phwi_ctrlr->phwi_ctxt;
  4360. if (blk_iopoll_enabled) {
  4361. for (i = 0; i < phba->num_cpus; i++) {
  4362. pbe_eq = &phwi_context->be_eq[i];
  4363. blk_iopoll_init(&pbe_eq->iopoll, be_iopoll_budget,
  4364. be_iopoll);
  4365. blk_iopoll_enable(&pbe_eq->iopoll);
  4366. }
  4367. i = (phba->msix_enabled) ? i : 0;
  4368. /* Work item for MCC handling */
  4369. pbe_eq = &phwi_context->be_eq[i];
  4370. INIT_WORK(&pbe_eq->work_cqs, beiscsi_process_all_cqs);
  4371. } else {
  4372. if (phba->msix_enabled) {
  4373. for (i = 0; i <= phba->num_cpus; i++) {
  4374. pbe_eq = &phwi_context->be_eq[i];
  4375. INIT_WORK(&pbe_eq->work_cqs,
  4376. beiscsi_process_all_cqs);
  4377. }
  4378. } else {
  4379. pbe_eq = &phwi_context->be_eq[0];
  4380. INIT_WORK(&pbe_eq->work_cqs,
  4381. beiscsi_process_all_cqs);
  4382. }
  4383. }
  4384. ret = beiscsi_init_irqs(phba);
  4385. if (ret < 0) {
  4386. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4387. "BM_%d : beiscsi_dev_probe-"
  4388. "Failed to beiscsi_init_irqs\n");
  4389. goto free_blkenbld;
  4390. }
  4391. hwi_enable_intr(phba);
  4392. if (beiscsi_setup_boot_info(phba))
  4393. /*
  4394. * log error but continue, because we may not be using
  4395. * iscsi boot.
  4396. */
  4397. beiscsi_log(phba, KERN_ERR, BEISCSI_LOG_INIT,
  4398. "BM_%d : Could not set up "
  4399. "iSCSI boot info.\n");
  4400. beiscsi_create_def_ifaces(phba);
  4401. beiscsi_log(phba, KERN_INFO, BEISCSI_LOG_INIT,
  4402. "\n\n\n BM_%d : SUCCESS - DRIVER LOADED\n\n\n");
  4403. return 0;
  4404. free_blkenbld:
  4405. destroy_workqueue(phba->wq);
  4406. if (blk_iopoll_enabled)
  4407. for (i = 0; i < phba->num_cpus; i++) {
  4408. pbe_eq = &phwi_context->be_eq[i];
  4409. blk_iopoll_disable(&pbe_eq->iopoll);
  4410. }
  4411. free_twq:
  4412. beiscsi_clean_port(phba);
  4413. beiscsi_free_mem(phba);
  4414. free_port:
  4415. pci_free_consistent(phba->pcidev,
  4416. phba->ctrl.mbox_mem_alloced.size,
  4417. phba->ctrl.mbox_mem_alloced.va,
  4418. phba->ctrl.mbox_mem_alloced.dma);
  4419. beiscsi_unmap_pci_function(phba);
  4420. hba_free:
  4421. if (phba->msix_enabled)
  4422. pci_disable_msix(phba->pcidev);
  4423. iscsi_host_remove(phba->shost);
  4424. pci_dev_put(phba->pcidev);
  4425. iscsi_host_free(phba->shost);
  4426. disable_pci:
  4427. pci_disable_device(pcidev);
  4428. return ret;
  4429. }
  4430. struct iscsi_transport beiscsi_iscsi_transport = {
  4431. .owner = THIS_MODULE,
  4432. .name = DRV_NAME,
  4433. .caps = CAP_RECOVERY_L0 | CAP_HDRDGST | CAP_TEXT_NEGO |
  4434. CAP_MULTI_R2T | CAP_DATADGST | CAP_DATA_PATH_OFFLOAD,
  4435. .create_session = beiscsi_session_create,
  4436. .destroy_session = beiscsi_session_destroy,
  4437. .create_conn = beiscsi_conn_create,
  4438. .bind_conn = beiscsi_conn_bind,
  4439. .destroy_conn = iscsi_conn_teardown,
  4440. .attr_is_visible = be2iscsi_attr_is_visible,
  4441. .set_iface_param = be2iscsi_iface_set_param,
  4442. .get_iface_param = be2iscsi_iface_get_param,
  4443. .set_param = beiscsi_set_param,
  4444. .get_conn_param = iscsi_conn_get_param,
  4445. .get_session_param = iscsi_session_get_param,
  4446. .get_host_param = beiscsi_get_host_param,
  4447. .start_conn = beiscsi_conn_start,
  4448. .stop_conn = iscsi_conn_stop,
  4449. .send_pdu = iscsi_conn_send_pdu,
  4450. .xmit_task = beiscsi_task_xmit,
  4451. .cleanup_task = beiscsi_cleanup_task,
  4452. .alloc_pdu = beiscsi_alloc_pdu,
  4453. .parse_pdu_itt = beiscsi_parse_pdu,
  4454. .get_stats = beiscsi_conn_get_stats,
  4455. .get_ep_param = beiscsi_ep_get_param,
  4456. .ep_connect = beiscsi_ep_connect,
  4457. .ep_poll = beiscsi_ep_poll,
  4458. .ep_disconnect = beiscsi_ep_disconnect,
  4459. .session_recovery_timedout = iscsi_session_recovery_timedout,
  4460. .bsg_request = beiscsi_bsg_request,
  4461. };
  4462. static struct pci_driver beiscsi_pci_driver = {
  4463. .name = DRV_NAME,
  4464. .probe = beiscsi_dev_probe,
  4465. .remove = beiscsi_remove,
  4466. .shutdown = beiscsi_shutdown,
  4467. .id_table = beiscsi_pci_id_table
  4468. };
  4469. static int __init beiscsi_module_init(void)
  4470. {
  4471. int ret;
  4472. beiscsi_scsi_transport =
  4473. iscsi_register_transport(&beiscsi_iscsi_transport);
  4474. if (!beiscsi_scsi_transport) {
  4475. printk(KERN_ERR
  4476. "beiscsi_module_init - Unable to register beiscsi transport.\n");
  4477. return -ENOMEM;
  4478. }
  4479. printk(KERN_INFO "In beiscsi_module_init, tt=%p\n",
  4480. &beiscsi_iscsi_transport);
  4481. ret = pci_register_driver(&beiscsi_pci_driver);
  4482. if (ret) {
  4483. printk(KERN_ERR
  4484. "beiscsi_module_init - Unable to register beiscsi pci driver.\n");
  4485. goto unregister_iscsi_transport;
  4486. }
  4487. return 0;
  4488. unregister_iscsi_transport:
  4489. iscsi_unregister_transport(&beiscsi_iscsi_transport);
  4490. return ret;
  4491. }
  4492. static void __exit beiscsi_module_exit(void)
  4493. {
  4494. pci_unregister_driver(&beiscsi_pci_driver);
  4495. iscsi_unregister_transport(&beiscsi_iscsi_transport);
  4496. }
  4497. module_init(beiscsi_module_init);
  4498. module_exit(beiscsi_module_exit);