svm.c 111 KB

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  1. /*
  2. * Kernel-based Virtual Machine driver for Linux
  3. *
  4. * AMD SVM support
  5. *
  6. * Copyright (C) 2006 Qumranet, Inc.
  7. * Copyright 2010 Red Hat, Inc. and/or its affiliates.
  8. *
  9. * Authors:
  10. * Yaniv Kamay <yaniv@qumranet.com>
  11. * Avi Kivity <avi@qumranet.com>
  12. *
  13. * This work is licensed under the terms of the GNU GPL, version 2. See
  14. * the COPYING file in the top-level directory.
  15. *
  16. */
  17. #include <linux/kvm_host.h>
  18. #include "irq.h"
  19. #include "mmu.h"
  20. #include "kvm_cache_regs.h"
  21. #include "x86.h"
  22. #include "cpuid.h"
  23. #include <linux/module.h>
  24. #include <linux/mod_devicetable.h>
  25. #include <linux/kernel.h>
  26. #include <linux/vmalloc.h>
  27. #include <linux/highmem.h>
  28. #include <linux/sched.h>
  29. #include <linux/ftrace_event.h>
  30. #include <linux/slab.h>
  31. #include <asm/perf_event.h>
  32. #include <asm/tlbflush.h>
  33. #include <asm/desc.h>
  34. #include <asm/kvm_para.h>
  35. #include <asm/virtext.h>
  36. #include "trace.h"
  37. #define __ex(x) __kvm_handle_fault_on_reboot(x)
  38. MODULE_AUTHOR("Qumranet");
  39. MODULE_LICENSE("GPL");
  40. static const struct x86_cpu_id svm_cpu_id[] = {
  41. X86_FEATURE_MATCH(X86_FEATURE_SVM),
  42. {}
  43. };
  44. MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
  45. #define IOPM_ALLOC_ORDER 2
  46. #define MSRPM_ALLOC_ORDER 1
  47. #define SEG_TYPE_LDT 2
  48. #define SEG_TYPE_BUSY_TSS16 3
  49. #define SVM_FEATURE_NPT (1 << 0)
  50. #define SVM_FEATURE_LBRV (1 << 1)
  51. #define SVM_FEATURE_SVML (1 << 2)
  52. #define SVM_FEATURE_NRIP (1 << 3)
  53. #define SVM_FEATURE_TSC_RATE (1 << 4)
  54. #define SVM_FEATURE_VMCB_CLEAN (1 << 5)
  55. #define SVM_FEATURE_FLUSH_ASID (1 << 6)
  56. #define SVM_FEATURE_DECODE_ASSIST (1 << 7)
  57. #define SVM_FEATURE_PAUSE_FILTER (1 << 10)
  58. #define NESTED_EXIT_HOST 0 /* Exit handled on host level */
  59. #define NESTED_EXIT_DONE 1 /* Exit caused nested vmexit */
  60. #define NESTED_EXIT_CONTINUE 2 /* Further checks needed */
  61. #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  62. #define TSC_RATIO_RSVD 0xffffff0000000000ULL
  63. #define TSC_RATIO_MIN 0x0000000000000001ULL
  64. #define TSC_RATIO_MAX 0x000000ffffffffffULL
  65. static bool erratum_383_found __read_mostly;
  66. static const u32 host_save_user_msrs[] = {
  67. #ifdef CONFIG_X86_64
  68. MSR_STAR, MSR_LSTAR, MSR_CSTAR, MSR_SYSCALL_MASK, MSR_KERNEL_GS_BASE,
  69. MSR_FS_BASE,
  70. #endif
  71. MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
  72. };
  73. #define NR_HOST_SAVE_USER_MSRS ARRAY_SIZE(host_save_user_msrs)
  74. struct kvm_vcpu;
  75. struct nested_state {
  76. struct vmcb *hsave;
  77. u64 hsave_msr;
  78. u64 vm_cr_msr;
  79. u64 vmcb;
  80. /* These are the merged vectors */
  81. u32 *msrpm;
  82. /* gpa pointers to the real vectors */
  83. u64 vmcb_msrpm;
  84. u64 vmcb_iopm;
  85. /* A VMEXIT is required but not yet emulated */
  86. bool exit_required;
  87. /* cache for intercepts of the guest */
  88. u32 intercept_cr;
  89. u32 intercept_dr;
  90. u32 intercept_exceptions;
  91. u64 intercept;
  92. /* Nested Paging related state */
  93. u64 nested_cr3;
  94. };
  95. #define MSRPM_OFFSETS 16
  96. static u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
  97. /*
  98. * Set osvw_len to higher value when updated Revision Guides
  99. * are published and we know what the new status bits are
  100. */
  101. static uint64_t osvw_len = 4, osvw_status;
  102. struct vcpu_svm {
  103. struct kvm_vcpu vcpu;
  104. struct vmcb *vmcb;
  105. unsigned long vmcb_pa;
  106. struct svm_cpu_data *svm_data;
  107. uint64_t asid_generation;
  108. uint64_t sysenter_esp;
  109. uint64_t sysenter_eip;
  110. u64 next_rip;
  111. u64 host_user_msrs[NR_HOST_SAVE_USER_MSRS];
  112. struct {
  113. u16 fs;
  114. u16 gs;
  115. u16 ldt;
  116. u64 gs_base;
  117. } host;
  118. u32 *msrpm;
  119. ulong nmi_iret_rip;
  120. struct nested_state nested;
  121. bool nmi_singlestep;
  122. unsigned int3_injected;
  123. unsigned long int3_rip;
  124. u32 apf_reason;
  125. u64 tsc_ratio;
  126. };
  127. static DEFINE_PER_CPU(u64, current_tsc_ratio);
  128. #define TSC_RATIO_DEFAULT 0x0100000000ULL
  129. #define MSR_INVALID 0xffffffffU
  130. static const struct svm_direct_access_msrs {
  131. u32 index; /* Index of the MSR */
  132. bool always; /* True if intercept is always on */
  133. } direct_access_msrs[] = {
  134. { .index = MSR_STAR, .always = true },
  135. { .index = MSR_IA32_SYSENTER_CS, .always = true },
  136. #ifdef CONFIG_X86_64
  137. { .index = MSR_GS_BASE, .always = true },
  138. { .index = MSR_FS_BASE, .always = true },
  139. { .index = MSR_KERNEL_GS_BASE, .always = true },
  140. { .index = MSR_LSTAR, .always = true },
  141. { .index = MSR_CSTAR, .always = true },
  142. { .index = MSR_SYSCALL_MASK, .always = true },
  143. #endif
  144. { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
  145. { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
  146. { .index = MSR_IA32_LASTINTFROMIP, .always = false },
  147. { .index = MSR_IA32_LASTINTTOIP, .always = false },
  148. { .index = MSR_INVALID, .always = false },
  149. };
  150. /* enable NPT for AMD64 and X86 with PAE */
  151. #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
  152. static bool npt_enabled = true;
  153. #else
  154. static bool npt_enabled;
  155. #endif
  156. /* allow nested paging (virtualized MMU) for all guests */
  157. static int npt = true;
  158. module_param(npt, int, S_IRUGO);
  159. /* allow nested virtualization in KVM/SVM */
  160. static int nested = true;
  161. module_param(nested, int, S_IRUGO);
  162. static void svm_flush_tlb(struct kvm_vcpu *vcpu);
  163. static void svm_complete_interrupts(struct vcpu_svm *svm);
  164. static int nested_svm_exit_handled(struct vcpu_svm *svm);
  165. static int nested_svm_intercept(struct vcpu_svm *svm);
  166. static int nested_svm_vmexit(struct vcpu_svm *svm);
  167. static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
  168. bool has_error_code, u32 error_code);
  169. static u64 __scale_tsc(u64 ratio, u64 tsc);
  170. enum {
  171. VMCB_INTERCEPTS, /* Intercept vectors, TSC offset,
  172. pause filter count */
  173. VMCB_PERM_MAP, /* IOPM Base and MSRPM Base */
  174. VMCB_ASID, /* ASID */
  175. VMCB_INTR, /* int_ctl, int_vector */
  176. VMCB_NPT, /* npt_en, nCR3, gPAT */
  177. VMCB_CR, /* CR0, CR3, CR4, EFER */
  178. VMCB_DR, /* DR6, DR7 */
  179. VMCB_DT, /* GDT, IDT */
  180. VMCB_SEG, /* CS, DS, SS, ES, CPL */
  181. VMCB_CR2, /* CR2 only */
  182. VMCB_LBR, /* DBGCTL, BR_FROM, BR_TO, LAST_EX_FROM, LAST_EX_TO */
  183. VMCB_DIRTY_MAX,
  184. };
  185. /* TPR and CR2 are always written before VMRUN */
  186. #define VMCB_ALWAYS_DIRTY_MASK ((1U << VMCB_INTR) | (1U << VMCB_CR2))
  187. static inline void mark_all_dirty(struct vmcb *vmcb)
  188. {
  189. vmcb->control.clean = 0;
  190. }
  191. static inline void mark_all_clean(struct vmcb *vmcb)
  192. {
  193. vmcb->control.clean = ((1 << VMCB_DIRTY_MAX) - 1)
  194. & ~VMCB_ALWAYS_DIRTY_MASK;
  195. }
  196. static inline void mark_dirty(struct vmcb *vmcb, int bit)
  197. {
  198. vmcb->control.clean &= ~(1 << bit);
  199. }
  200. static inline struct vcpu_svm *to_svm(struct kvm_vcpu *vcpu)
  201. {
  202. return container_of(vcpu, struct vcpu_svm, vcpu);
  203. }
  204. static void recalc_intercepts(struct vcpu_svm *svm)
  205. {
  206. struct vmcb_control_area *c, *h;
  207. struct nested_state *g;
  208. mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
  209. if (!is_guest_mode(&svm->vcpu))
  210. return;
  211. c = &svm->vmcb->control;
  212. h = &svm->nested.hsave->control;
  213. g = &svm->nested;
  214. c->intercept_cr = h->intercept_cr | g->intercept_cr;
  215. c->intercept_dr = h->intercept_dr | g->intercept_dr;
  216. c->intercept_exceptions = h->intercept_exceptions | g->intercept_exceptions;
  217. c->intercept = h->intercept | g->intercept;
  218. }
  219. static inline struct vmcb *get_host_vmcb(struct vcpu_svm *svm)
  220. {
  221. if (is_guest_mode(&svm->vcpu))
  222. return svm->nested.hsave;
  223. else
  224. return svm->vmcb;
  225. }
  226. static inline void set_cr_intercept(struct vcpu_svm *svm, int bit)
  227. {
  228. struct vmcb *vmcb = get_host_vmcb(svm);
  229. vmcb->control.intercept_cr |= (1U << bit);
  230. recalc_intercepts(svm);
  231. }
  232. static inline void clr_cr_intercept(struct vcpu_svm *svm, int bit)
  233. {
  234. struct vmcb *vmcb = get_host_vmcb(svm);
  235. vmcb->control.intercept_cr &= ~(1U << bit);
  236. recalc_intercepts(svm);
  237. }
  238. static inline bool is_cr_intercept(struct vcpu_svm *svm, int bit)
  239. {
  240. struct vmcb *vmcb = get_host_vmcb(svm);
  241. return vmcb->control.intercept_cr & (1U << bit);
  242. }
  243. static inline void set_dr_intercept(struct vcpu_svm *svm, int bit)
  244. {
  245. struct vmcb *vmcb = get_host_vmcb(svm);
  246. vmcb->control.intercept_dr |= (1U << bit);
  247. recalc_intercepts(svm);
  248. }
  249. static inline void clr_dr_intercept(struct vcpu_svm *svm, int bit)
  250. {
  251. struct vmcb *vmcb = get_host_vmcb(svm);
  252. vmcb->control.intercept_dr &= ~(1U << bit);
  253. recalc_intercepts(svm);
  254. }
  255. static inline void set_exception_intercept(struct vcpu_svm *svm, int bit)
  256. {
  257. struct vmcb *vmcb = get_host_vmcb(svm);
  258. vmcb->control.intercept_exceptions |= (1U << bit);
  259. recalc_intercepts(svm);
  260. }
  261. static inline void clr_exception_intercept(struct vcpu_svm *svm, int bit)
  262. {
  263. struct vmcb *vmcb = get_host_vmcb(svm);
  264. vmcb->control.intercept_exceptions &= ~(1U << bit);
  265. recalc_intercepts(svm);
  266. }
  267. static inline void set_intercept(struct vcpu_svm *svm, int bit)
  268. {
  269. struct vmcb *vmcb = get_host_vmcb(svm);
  270. vmcb->control.intercept |= (1ULL << bit);
  271. recalc_intercepts(svm);
  272. }
  273. static inline void clr_intercept(struct vcpu_svm *svm, int bit)
  274. {
  275. struct vmcb *vmcb = get_host_vmcb(svm);
  276. vmcb->control.intercept &= ~(1ULL << bit);
  277. recalc_intercepts(svm);
  278. }
  279. static inline void enable_gif(struct vcpu_svm *svm)
  280. {
  281. svm->vcpu.arch.hflags |= HF_GIF_MASK;
  282. }
  283. static inline void disable_gif(struct vcpu_svm *svm)
  284. {
  285. svm->vcpu.arch.hflags &= ~HF_GIF_MASK;
  286. }
  287. static inline bool gif_set(struct vcpu_svm *svm)
  288. {
  289. return !!(svm->vcpu.arch.hflags & HF_GIF_MASK);
  290. }
  291. static unsigned long iopm_base;
  292. struct kvm_ldttss_desc {
  293. u16 limit0;
  294. u16 base0;
  295. unsigned base1:8, type:5, dpl:2, p:1;
  296. unsigned limit1:4, zero0:3, g:1, base2:8;
  297. u32 base3;
  298. u32 zero1;
  299. } __attribute__((packed));
  300. struct svm_cpu_data {
  301. int cpu;
  302. u64 asid_generation;
  303. u32 max_asid;
  304. u32 next_asid;
  305. struct kvm_ldttss_desc *tss_desc;
  306. struct page *save_area;
  307. };
  308. static DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
  309. struct svm_init_data {
  310. int cpu;
  311. int r;
  312. };
  313. static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
  314. #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
  315. #define MSRS_RANGE_SIZE 2048
  316. #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
  317. static u32 svm_msrpm_offset(u32 msr)
  318. {
  319. u32 offset;
  320. int i;
  321. for (i = 0; i < NUM_MSR_MAPS; i++) {
  322. if (msr < msrpm_ranges[i] ||
  323. msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
  324. continue;
  325. offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
  326. offset += (i * MSRS_RANGE_SIZE); /* add range offset */
  327. /* Now we have the u8 offset - but need the u32 offset */
  328. return offset / 4;
  329. }
  330. /* MSR not in any range */
  331. return MSR_INVALID;
  332. }
  333. #define MAX_INST_SIZE 15
  334. static inline void clgi(void)
  335. {
  336. asm volatile (__ex(SVM_CLGI));
  337. }
  338. static inline void stgi(void)
  339. {
  340. asm volatile (__ex(SVM_STGI));
  341. }
  342. static inline void invlpga(unsigned long addr, u32 asid)
  343. {
  344. asm volatile (__ex(SVM_INVLPGA) : : "a"(addr), "c"(asid));
  345. }
  346. static int get_npt_level(void)
  347. {
  348. #ifdef CONFIG_X86_64
  349. return PT64_ROOT_LEVEL;
  350. #else
  351. return PT32E_ROOT_LEVEL;
  352. #endif
  353. }
  354. static void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
  355. {
  356. vcpu->arch.efer = efer;
  357. if (!npt_enabled && !(efer & EFER_LMA))
  358. efer &= ~EFER_LME;
  359. to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
  360. mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
  361. }
  362. static int is_external_interrupt(u32 info)
  363. {
  364. info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
  365. return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
  366. }
  367. static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
  368. {
  369. struct vcpu_svm *svm = to_svm(vcpu);
  370. u32 ret = 0;
  371. if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
  372. ret |= KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
  373. return ret & mask;
  374. }
  375. static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
  376. {
  377. struct vcpu_svm *svm = to_svm(vcpu);
  378. if (mask == 0)
  379. svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
  380. else
  381. svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
  382. }
  383. static void skip_emulated_instruction(struct kvm_vcpu *vcpu)
  384. {
  385. struct vcpu_svm *svm = to_svm(vcpu);
  386. if (svm->vmcb->control.next_rip != 0)
  387. svm->next_rip = svm->vmcb->control.next_rip;
  388. if (!svm->next_rip) {
  389. if (emulate_instruction(vcpu, EMULTYPE_SKIP) !=
  390. EMULATE_DONE)
  391. printk(KERN_DEBUG "%s: NOP\n", __func__);
  392. return;
  393. }
  394. if (svm->next_rip - kvm_rip_read(vcpu) > MAX_INST_SIZE)
  395. printk(KERN_ERR "%s: ip 0x%lx next 0x%llx\n",
  396. __func__, kvm_rip_read(vcpu), svm->next_rip);
  397. kvm_rip_write(vcpu, svm->next_rip);
  398. svm_set_interrupt_shadow(vcpu, 0);
  399. }
  400. static void svm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr,
  401. bool has_error_code, u32 error_code,
  402. bool reinject)
  403. {
  404. struct vcpu_svm *svm = to_svm(vcpu);
  405. /*
  406. * If we are within a nested VM we'd better #VMEXIT and let the guest
  407. * handle the exception
  408. */
  409. if (!reinject &&
  410. nested_svm_check_exception(svm, nr, has_error_code, error_code))
  411. return;
  412. if (nr == BP_VECTOR && !static_cpu_has(X86_FEATURE_NRIPS)) {
  413. unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
  414. /*
  415. * For guest debugging where we have to reinject #BP if some
  416. * INT3 is guest-owned:
  417. * Emulate nRIP by moving RIP forward. Will fail if injection
  418. * raises a fault that is not intercepted. Still better than
  419. * failing in all cases.
  420. */
  421. skip_emulated_instruction(&svm->vcpu);
  422. rip = kvm_rip_read(&svm->vcpu);
  423. svm->int3_rip = rip + svm->vmcb->save.cs.base;
  424. svm->int3_injected = rip - old_rip;
  425. }
  426. svm->vmcb->control.event_inj = nr
  427. | SVM_EVTINJ_VALID
  428. | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
  429. | SVM_EVTINJ_TYPE_EXEPT;
  430. svm->vmcb->control.event_inj_err = error_code;
  431. }
  432. static void svm_init_erratum_383(void)
  433. {
  434. u32 low, high;
  435. int err;
  436. u64 val;
  437. if (!cpu_has_amd_erratum(amd_erratum_383))
  438. return;
  439. /* Use _safe variants to not break nested virtualization */
  440. val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
  441. if (err)
  442. return;
  443. val |= (1ULL << 47);
  444. low = lower_32_bits(val);
  445. high = upper_32_bits(val);
  446. native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
  447. erratum_383_found = true;
  448. }
  449. static void svm_init_osvw(struct kvm_vcpu *vcpu)
  450. {
  451. /*
  452. * Guests should see errata 400 and 415 as fixed (assuming that
  453. * HLT and IO instructions are intercepted).
  454. */
  455. vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
  456. vcpu->arch.osvw.status = osvw_status & ~(6ULL);
  457. /*
  458. * By increasing VCPU's osvw.length to 3 we are telling the guest that
  459. * all osvw.status bits inside that length, including bit 0 (which is
  460. * reserved for erratum 298), are valid. However, if host processor's
  461. * osvw_len is 0 then osvw_status[0] carries no information. We need to
  462. * be conservative here and therefore we tell the guest that erratum 298
  463. * is present (because we really don't know).
  464. */
  465. if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
  466. vcpu->arch.osvw.status |= 1;
  467. }
  468. static int has_svm(void)
  469. {
  470. const char *msg;
  471. if (!cpu_has_svm(&msg)) {
  472. printk(KERN_INFO "has_svm: %s\n", msg);
  473. return 0;
  474. }
  475. return 1;
  476. }
  477. static void svm_hardware_disable(void *garbage)
  478. {
  479. /* Make sure we clean up behind us */
  480. if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
  481. wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
  482. cpu_svm_disable();
  483. amd_pmu_disable_virt();
  484. }
  485. static int svm_hardware_enable(void *garbage)
  486. {
  487. struct svm_cpu_data *sd;
  488. uint64_t efer;
  489. struct desc_ptr gdt_descr;
  490. struct desc_struct *gdt;
  491. int me = raw_smp_processor_id();
  492. rdmsrl(MSR_EFER, efer);
  493. if (efer & EFER_SVME)
  494. return -EBUSY;
  495. if (!has_svm()) {
  496. pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
  497. return -EINVAL;
  498. }
  499. sd = per_cpu(svm_data, me);
  500. if (!sd) {
  501. pr_err("%s: svm_data is NULL on %d\n", __func__, me);
  502. return -EINVAL;
  503. }
  504. sd->asid_generation = 1;
  505. sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
  506. sd->next_asid = sd->max_asid + 1;
  507. native_store_gdt(&gdt_descr);
  508. gdt = (struct desc_struct *)gdt_descr.address;
  509. sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
  510. wrmsrl(MSR_EFER, efer | EFER_SVME);
  511. wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
  512. if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
  513. wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
  514. __get_cpu_var(current_tsc_ratio) = TSC_RATIO_DEFAULT;
  515. }
  516. /*
  517. * Get OSVW bits.
  518. *
  519. * Note that it is possible to have a system with mixed processor
  520. * revisions and therefore different OSVW bits. If bits are not the same
  521. * on different processors then choose the worst case (i.e. if erratum
  522. * is present on one processor and not on another then assume that the
  523. * erratum is present everywhere).
  524. */
  525. if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
  526. uint64_t len, status = 0;
  527. int err;
  528. len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
  529. if (!err)
  530. status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
  531. &err);
  532. if (err)
  533. osvw_status = osvw_len = 0;
  534. else {
  535. if (len < osvw_len)
  536. osvw_len = len;
  537. osvw_status |= status;
  538. osvw_status &= (1ULL << osvw_len) - 1;
  539. }
  540. } else
  541. osvw_status = osvw_len = 0;
  542. svm_init_erratum_383();
  543. amd_pmu_enable_virt();
  544. return 0;
  545. }
  546. static void svm_cpu_uninit(int cpu)
  547. {
  548. struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
  549. if (!sd)
  550. return;
  551. per_cpu(svm_data, raw_smp_processor_id()) = NULL;
  552. __free_page(sd->save_area);
  553. kfree(sd);
  554. }
  555. static int svm_cpu_init(int cpu)
  556. {
  557. struct svm_cpu_data *sd;
  558. int r;
  559. sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
  560. if (!sd)
  561. return -ENOMEM;
  562. sd->cpu = cpu;
  563. sd->save_area = alloc_page(GFP_KERNEL);
  564. r = -ENOMEM;
  565. if (!sd->save_area)
  566. goto err_1;
  567. per_cpu(svm_data, cpu) = sd;
  568. return 0;
  569. err_1:
  570. kfree(sd);
  571. return r;
  572. }
  573. static bool valid_msr_intercept(u32 index)
  574. {
  575. int i;
  576. for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
  577. if (direct_access_msrs[i].index == index)
  578. return true;
  579. return false;
  580. }
  581. static void set_msr_interception(u32 *msrpm, unsigned msr,
  582. int read, int write)
  583. {
  584. u8 bit_read, bit_write;
  585. unsigned long tmp;
  586. u32 offset;
  587. /*
  588. * If this warning triggers extend the direct_access_msrs list at the
  589. * beginning of the file
  590. */
  591. WARN_ON(!valid_msr_intercept(msr));
  592. offset = svm_msrpm_offset(msr);
  593. bit_read = 2 * (msr & 0x0f);
  594. bit_write = 2 * (msr & 0x0f) + 1;
  595. tmp = msrpm[offset];
  596. BUG_ON(offset == MSR_INVALID);
  597. read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
  598. write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
  599. msrpm[offset] = tmp;
  600. }
  601. static void svm_vcpu_init_msrpm(u32 *msrpm)
  602. {
  603. int i;
  604. memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
  605. for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
  606. if (!direct_access_msrs[i].always)
  607. continue;
  608. set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
  609. }
  610. }
  611. static void add_msr_offset(u32 offset)
  612. {
  613. int i;
  614. for (i = 0; i < MSRPM_OFFSETS; ++i) {
  615. /* Offset already in list? */
  616. if (msrpm_offsets[i] == offset)
  617. return;
  618. /* Slot used by another offset? */
  619. if (msrpm_offsets[i] != MSR_INVALID)
  620. continue;
  621. /* Add offset to list */
  622. msrpm_offsets[i] = offset;
  623. return;
  624. }
  625. /*
  626. * If this BUG triggers the msrpm_offsets table has an overflow. Just
  627. * increase MSRPM_OFFSETS in this case.
  628. */
  629. BUG();
  630. }
  631. static void init_msrpm_offsets(void)
  632. {
  633. int i;
  634. memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
  635. for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
  636. u32 offset;
  637. offset = svm_msrpm_offset(direct_access_msrs[i].index);
  638. BUG_ON(offset == MSR_INVALID);
  639. add_msr_offset(offset);
  640. }
  641. }
  642. static void svm_enable_lbrv(struct vcpu_svm *svm)
  643. {
  644. u32 *msrpm = svm->msrpm;
  645. svm->vmcb->control.lbr_ctl = 1;
  646. set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
  647. set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
  648. set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
  649. set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
  650. }
  651. static void svm_disable_lbrv(struct vcpu_svm *svm)
  652. {
  653. u32 *msrpm = svm->msrpm;
  654. svm->vmcb->control.lbr_ctl = 0;
  655. set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
  656. set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
  657. set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
  658. set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
  659. }
  660. static __init int svm_hardware_setup(void)
  661. {
  662. int cpu;
  663. struct page *iopm_pages;
  664. void *iopm_va;
  665. int r;
  666. iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
  667. if (!iopm_pages)
  668. return -ENOMEM;
  669. iopm_va = page_address(iopm_pages);
  670. memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
  671. iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
  672. init_msrpm_offsets();
  673. if (boot_cpu_has(X86_FEATURE_NX))
  674. kvm_enable_efer_bits(EFER_NX);
  675. if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
  676. kvm_enable_efer_bits(EFER_FFXSR);
  677. if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
  678. u64 max;
  679. kvm_has_tsc_control = true;
  680. /*
  681. * Make sure the user can only configure tsc_khz values that
  682. * fit into a signed integer.
  683. * A min value is not calculated needed because it will always
  684. * be 1 on all machines and a value of 0 is used to disable
  685. * tsc-scaling for the vcpu.
  686. */
  687. max = min(0x7fffffffULL, __scale_tsc(tsc_khz, TSC_RATIO_MAX));
  688. kvm_max_guest_tsc_khz = max;
  689. }
  690. if (nested) {
  691. printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
  692. kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
  693. }
  694. for_each_possible_cpu(cpu) {
  695. r = svm_cpu_init(cpu);
  696. if (r)
  697. goto err;
  698. }
  699. if (!boot_cpu_has(X86_FEATURE_NPT))
  700. npt_enabled = false;
  701. if (npt_enabled && !npt) {
  702. printk(KERN_INFO "kvm: Nested Paging disabled\n");
  703. npt_enabled = false;
  704. }
  705. if (npt_enabled) {
  706. printk(KERN_INFO "kvm: Nested Paging enabled\n");
  707. kvm_enable_tdp();
  708. } else
  709. kvm_disable_tdp();
  710. return 0;
  711. err:
  712. __free_pages(iopm_pages, IOPM_ALLOC_ORDER);
  713. iopm_base = 0;
  714. return r;
  715. }
  716. static __exit void svm_hardware_unsetup(void)
  717. {
  718. int cpu;
  719. for_each_possible_cpu(cpu)
  720. svm_cpu_uninit(cpu);
  721. __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
  722. iopm_base = 0;
  723. }
  724. static void init_seg(struct vmcb_seg *seg)
  725. {
  726. seg->selector = 0;
  727. seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
  728. SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
  729. seg->limit = 0xffff;
  730. seg->base = 0;
  731. }
  732. static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
  733. {
  734. seg->selector = 0;
  735. seg->attrib = SVM_SELECTOR_P_MASK | type;
  736. seg->limit = 0xffff;
  737. seg->base = 0;
  738. }
  739. static u64 __scale_tsc(u64 ratio, u64 tsc)
  740. {
  741. u64 mult, frac, _tsc;
  742. mult = ratio >> 32;
  743. frac = ratio & ((1ULL << 32) - 1);
  744. _tsc = tsc;
  745. _tsc *= mult;
  746. _tsc += (tsc >> 32) * frac;
  747. _tsc += ((tsc & ((1ULL << 32) - 1)) * frac) >> 32;
  748. return _tsc;
  749. }
  750. static u64 svm_scale_tsc(struct kvm_vcpu *vcpu, u64 tsc)
  751. {
  752. struct vcpu_svm *svm = to_svm(vcpu);
  753. u64 _tsc = tsc;
  754. if (svm->tsc_ratio != TSC_RATIO_DEFAULT)
  755. _tsc = __scale_tsc(svm->tsc_ratio, tsc);
  756. return _tsc;
  757. }
  758. static void svm_set_tsc_khz(struct kvm_vcpu *vcpu, u32 user_tsc_khz, bool scale)
  759. {
  760. struct vcpu_svm *svm = to_svm(vcpu);
  761. u64 ratio;
  762. u64 khz;
  763. /* Guest TSC same frequency as host TSC? */
  764. if (!scale) {
  765. svm->tsc_ratio = TSC_RATIO_DEFAULT;
  766. return;
  767. }
  768. /* TSC scaling supported? */
  769. if (!boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
  770. if (user_tsc_khz > tsc_khz) {
  771. vcpu->arch.tsc_catchup = 1;
  772. vcpu->arch.tsc_always_catchup = 1;
  773. } else
  774. WARN(1, "user requested TSC rate below hardware speed\n");
  775. return;
  776. }
  777. khz = user_tsc_khz;
  778. /* TSC scaling required - calculate ratio */
  779. ratio = khz << 32;
  780. do_div(ratio, tsc_khz);
  781. if (ratio == 0 || ratio & TSC_RATIO_RSVD) {
  782. WARN_ONCE(1, "Invalid TSC ratio - virtual-tsc-khz=%u\n",
  783. user_tsc_khz);
  784. return;
  785. }
  786. svm->tsc_ratio = ratio;
  787. }
  788. static u64 svm_read_tsc_offset(struct kvm_vcpu *vcpu)
  789. {
  790. struct vcpu_svm *svm = to_svm(vcpu);
  791. return svm->vmcb->control.tsc_offset;
  792. }
  793. static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
  794. {
  795. struct vcpu_svm *svm = to_svm(vcpu);
  796. u64 g_tsc_offset = 0;
  797. if (is_guest_mode(vcpu)) {
  798. g_tsc_offset = svm->vmcb->control.tsc_offset -
  799. svm->nested.hsave->control.tsc_offset;
  800. svm->nested.hsave->control.tsc_offset = offset;
  801. }
  802. svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
  803. mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
  804. }
  805. static void svm_adjust_tsc_offset(struct kvm_vcpu *vcpu, s64 adjustment, bool host)
  806. {
  807. struct vcpu_svm *svm = to_svm(vcpu);
  808. WARN_ON(adjustment < 0);
  809. if (host)
  810. adjustment = svm_scale_tsc(vcpu, adjustment);
  811. svm->vmcb->control.tsc_offset += adjustment;
  812. if (is_guest_mode(vcpu))
  813. svm->nested.hsave->control.tsc_offset += adjustment;
  814. mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
  815. }
  816. static u64 svm_compute_tsc_offset(struct kvm_vcpu *vcpu, u64 target_tsc)
  817. {
  818. u64 tsc;
  819. tsc = svm_scale_tsc(vcpu, native_read_tsc());
  820. return target_tsc - tsc;
  821. }
  822. static void init_vmcb(struct vcpu_svm *svm)
  823. {
  824. struct vmcb_control_area *control = &svm->vmcb->control;
  825. struct vmcb_save_area *save = &svm->vmcb->save;
  826. svm->vcpu.fpu_active = 1;
  827. svm->vcpu.arch.hflags = 0;
  828. set_cr_intercept(svm, INTERCEPT_CR0_READ);
  829. set_cr_intercept(svm, INTERCEPT_CR3_READ);
  830. set_cr_intercept(svm, INTERCEPT_CR4_READ);
  831. set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
  832. set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
  833. set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
  834. set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
  835. set_dr_intercept(svm, INTERCEPT_DR0_READ);
  836. set_dr_intercept(svm, INTERCEPT_DR1_READ);
  837. set_dr_intercept(svm, INTERCEPT_DR2_READ);
  838. set_dr_intercept(svm, INTERCEPT_DR3_READ);
  839. set_dr_intercept(svm, INTERCEPT_DR4_READ);
  840. set_dr_intercept(svm, INTERCEPT_DR5_READ);
  841. set_dr_intercept(svm, INTERCEPT_DR6_READ);
  842. set_dr_intercept(svm, INTERCEPT_DR7_READ);
  843. set_dr_intercept(svm, INTERCEPT_DR0_WRITE);
  844. set_dr_intercept(svm, INTERCEPT_DR1_WRITE);
  845. set_dr_intercept(svm, INTERCEPT_DR2_WRITE);
  846. set_dr_intercept(svm, INTERCEPT_DR3_WRITE);
  847. set_dr_intercept(svm, INTERCEPT_DR4_WRITE);
  848. set_dr_intercept(svm, INTERCEPT_DR5_WRITE);
  849. set_dr_intercept(svm, INTERCEPT_DR6_WRITE);
  850. set_dr_intercept(svm, INTERCEPT_DR7_WRITE);
  851. set_exception_intercept(svm, PF_VECTOR);
  852. set_exception_intercept(svm, UD_VECTOR);
  853. set_exception_intercept(svm, MC_VECTOR);
  854. set_intercept(svm, INTERCEPT_INTR);
  855. set_intercept(svm, INTERCEPT_NMI);
  856. set_intercept(svm, INTERCEPT_SMI);
  857. set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
  858. set_intercept(svm, INTERCEPT_RDPMC);
  859. set_intercept(svm, INTERCEPT_CPUID);
  860. set_intercept(svm, INTERCEPT_INVD);
  861. set_intercept(svm, INTERCEPT_HLT);
  862. set_intercept(svm, INTERCEPT_INVLPG);
  863. set_intercept(svm, INTERCEPT_INVLPGA);
  864. set_intercept(svm, INTERCEPT_IOIO_PROT);
  865. set_intercept(svm, INTERCEPT_MSR_PROT);
  866. set_intercept(svm, INTERCEPT_TASK_SWITCH);
  867. set_intercept(svm, INTERCEPT_SHUTDOWN);
  868. set_intercept(svm, INTERCEPT_VMRUN);
  869. set_intercept(svm, INTERCEPT_VMMCALL);
  870. set_intercept(svm, INTERCEPT_VMLOAD);
  871. set_intercept(svm, INTERCEPT_VMSAVE);
  872. set_intercept(svm, INTERCEPT_STGI);
  873. set_intercept(svm, INTERCEPT_CLGI);
  874. set_intercept(svm, INTERCEPT_SKINIT);
  875. set_intercept(svm, INTERCEPT_WBINVD);
  876. set_intercept(svm, INTERCEPT_MONITOR);
  877. set_intercept(svm, INTERCEPT_MWAIT);
  878. set_intercept(svm, INTERCEPT_XSETBV);
  879. control->iopm_base_pa = iopm_base;
  880. control->msrpm_base_pa = __pa(svm->msrpm);
  881. control->int_ctl = V_INTR_MASKING_MASK;
  882. init_seg(&save->es);
  883. init_seg(&save->ss);
  884. init_seg(&save->ds);
  885. init_seg(&save->fs);
  886. init_seg(&save->gs);
  887. save->cs.selector = 0xf000;
  888. save->cs.base = 0xffff0000;
  889. /* Executable/Readable Code Segment */
  890. save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
  891. SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
  892. save->cs.limit = 0xffff;
  893. save->gdtr.limit = 0xffff;
  894. save->idtr.limit = 0xffff;
  895. init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
  896. init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
  897. svm_set_efer(&svm->vcpu, 0);
  898. save->dr6 = 0xffff0ff0;
  899. kvm_set_rflags(&svm->vcpu, 2);
  900. save->rip = 0x0000fff0;
  901. svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
  902. /*
  903. * This is the guest-visible cr0 value.
  904. * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
  905. */
  906. svm->vcpu.arch.cr0 = 0;
  907. (void)kvm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
  908. save->cr4 = X86_CR4_PAE;
  909. /* rdx = ?? */
  910. if (npt_enabled) {
  911. /* Setup VMCB for Nested Paging */
  912. control->nested_ctl = 1;
  913. clr_intercept(svm, INTERCEPT_INVLPG);
  914. clr_exception_intercept(svm, PF_VECTOR);
  915. clr_cr_intercept(svm, INTERCEPT_CR3_READ);
  916. clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
  917. save->g_pat = 0x0007040600070406ULL;
  918. save->cr3 = 0;
  919. save->cr4 = 0;
  920. }
  921. svm->asid_generation = 0;
  922. svm->nested.vmcb = 0;
  923. svm->vcpu.arch.hflags = 0;
  924. if (boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
  925. control->pause_filter_count = 3000;
  926. set_intercept(svm, INTERCEPT_PAUSE);
  927. }
  928. mark_all_dirty(svm->vmcb);
  929. enable_gif(svm);
  930. }
  931. static void svm_vcpu_reset(struct kvm_vcpu *vcpu)
  932. {
  933. struct vcpu_svm *svm = to_svm(vcpu);
  934. u32 dummy;
  935. u32 eax = 1;
  936. init_vmcb(svm);
  937. kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy);
  938. kvm_register_write(vcpu, VCPU_REGS_RDX, eax);
  939. }
  940. static struct kvm_vcpu *svm_create_vcpu(struct kvm *kvm, unsigned int id)
  941. {
  942. struct vcpu_svm *svm;
  943. struct page *page;
  944. struct page *msrpm_pages;
  945. struct page *hsave_page;
  946. struct page *nested_msrpm_pages;
  947. int err;
  948. svm = kmem_cache_zalloc(kvm_vcpu_cache, GFP_KERNEL);
  949. if (!svm) {
  950. err = -ENOMEM;
  951. goto out;
  952. }
  953. svm->tsc_ratio = TSC_RATIO_DEFAULT;
  954. err = kvm_vcpu_init(&svm->vcpu, kvm, id);
  955. if (err)
  956. goto free_svm;
  957. err = -ENOMEM;
  958. page = alloc_page(GFP_KERNEL);
  959. if (!page)
  960. goto uninit;
  961. msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
  962. if (!msrpm_pages)
  963. goto free_page1;
  964. nested_msrpm_pages = alloc_pages(GFP_KERNEL, MSRPM_ALLOC_ORDER);
  965. if (!nested_msrpm_pages)
  966. goto free_page2;
  967. hsave_page = alloc_page(GFP_KERNEL);
  968. if (!hsave_page)
  969. goto free_page3;
  970. svm->nested.hsave = page_address(hsave_page);
  971. svm->msrpm = page_address(msrpm_pages);
  972. svm_vcpu_init_msrpm(svm->msrpm);
  973. svm->nested.msrpm = page_address(nested_msrpm_pages);
  974. svm_vcpu_init_msrpm(svm->nested.msrpm);
  975. svm->vmcb = page_address(page);
  976. clear_page(svm->vmcb);
  977. svm->vmcb_pa = page_to_pfn(page) << PAGE_SHIFT;
  978. svm->asid_generation = 0;
  979. init_vmcb(svm);
  980. svm->vcpu.arch.apic_base = 0xfee00000 | MSR_IA32_APICBASE_ENABLE;
  981. if (kvm_vcpu_is_bsp(&svm->vcpu))
  982. svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
  983. svm_init_osvw(&svm->vcpu);
  984. return &svm->vcpu;
  985. free_page3:
  986. __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
  987. free_page2:
  988. __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
  989. free_page1:
  990. __free_page(page);
  991. uninit:
  992. kvm_vcpu_uninit(&svm->vcpu);
  993. free_svm:
  994. kmem_cache_free(kvm_vcpu_cache, svm);
  995. out:
  996. return ERR_PTR(err);
  997. }
  998. static void svm_free_vcpu(struct kvm_vcpu *vcpu)
  999. {
  1000. struct vcpu_svm *svm = to_svm(vcpu);
  1001. __free_page(pfn_to_page(svm->vmcb_pa >> PAGE_SHIFT));
  1002. __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
  1003. __free_page(virt_to_page(svm->nested.hsave));
  1004. __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
  1005. kvm_vcpu_uninit(vcpu);
  1006. kmem_cache_free(kvm_vcpu_cache, svm);
  1007. }
  1008. static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
  1009. {
  1010. struct vcpu_svm *svm = to_svm(vcpu);
  1011. int i;
  1012. if (unlikely(cpu != vcpu->cpu)) {
  1013. svm->asid_generation = 0;
  1014. mark_all_dirty(svm->vmcb);
  1015. }
  1016. #ifdef CONFIG_X86_64
  1017. rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
  1018. #endif
  1019. savesegment(fs, svm->host.fs);
  1020. savesegment(gs, svm->host.gs);
  1021. svm->host.ldt = kvm_read_ldt();
  1022. for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
  1023. rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
  1024. if (static_cpu_has(X86_FEATURE_TSCRATEMSR) &&
  1025. svm->tsc_ratio != __get_cpu_var(current_tsc_ratio)) {
  1026. __get_cpu_var(current_tsc_ratio) = svm->tsc_ratio;
  1027. wrmsrl(MSR_AMD64_TSC_RATIO, svm->tsc_ratio);
  1028. }
  1029. }
  1030. static void svm_vcpu_put(struct kvm_vcpu *vcpu)
  1031. {
  1032. struct vcpu_svm *svm = to_svm(vcpu);
  1033. int i;
  1034. ++vcpu->stat.host_state_reload;
  1035. kvm_load_ldt(svm->host.ldt);
  1036. #ifdef CONFIG_X86_64
  1037. loadsegment(fs, svm->host.fs);
  1038. wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gs);
  1039. load_gs_index(svm->host.gs);
  1040. #else
  1041. #ifdef CONFIG_X86_32_LAZY_GS
  1042. loadsegment(gs, svm->host.gs);
  1043. #endif
  1044. #endif
  1045. for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
  1046. wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
  1047. }
  1048. static void svm_update_cpl(struct kvm_vcpu *vcpu)
  1049. {
  1050. struct vcpu_svm *svm = to_svm(vcpu);
  1051. int cpl;
  1052. if (!is_protmode(vcpu))
  1053. cpl = 0;
  1054. else if (svm->vmcb->save.rflags & X86_EFLAGS_VM)
  1055. cpl = 3;
  1056. else
  1057. cpl = svm->vmcb->save.cs.selector & 0x3;
  1058. svm->vmcb->save.cpl = cpl;
  1059. }
  1060. static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
  1061. {
  1062. return to_svm(vcpu)->vmcb->save.rflags;
  1063. }
  1064. static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
  1065. {
  1066. unsigned long old_rflags = to_svm(vcpu)->vmcb->save.rflags;
  1067. to_svm(vcpu)->vmcb->save.rflags = rflags;
  1068. if ((old_rflags ^ rflags) & X86_EFLAGS_VM)
  1069. svm_update_cpl(vcpu);
  1070. }
  1071. static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
  1072. {
  1073. switch (reg) {
  1074. case VCPU_EXREG_PDPTR:
  1075. BUG_ON(!npt_enabled);
  1076. load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
  1077. break;
  1078. default:
  1079. BUG();
  1080. }
  1081. }
  1082. static void svm_set_vintr(struct vcpu_svm *svm)
  1083. {
  1084. set_intercept(svm, INTERCEPT_VINTR);
  1085. }
  1086. static void svm_clear_vintr(struct vcpu_svm *svm)
  1087. {
  1088. clr_intercept(svm, INTERCEPT_VINTR);
  1089. }
  1090. static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
  1091. {
  1092. struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
  1093. switch (seg) {
  1094. case VCPU_SREG_CS: return &save->cs;
  1095. case VCPU_SREG_DS: return &save->ds;
  1096. case VCPU_SREG_ES: return &save->es;
  1097. case VCPU_SREG_FS: return &save->fs;
  1098. case VCPU_SREG_GS: return &save->gs;
  1099. case VCPU_SREG_SS: return &save->ss;
  1100. case VCPU_SREG_TR: return &save->tr;
  1101. case VCPU_SREG_LDTR: return &save->ldtr;
  1102. }
  1103. BUG();
  1104. return NULL;
  1105. }
  1106. static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
  1107. {
  1108. struct vmcb_seg *s = svm_seg(vcpu, seg);
  1109. return s->base;
  1110. }
  1111. static void svm_get_segment(struct kvm_vcpu *vcpu,
  1112. struct kvm_segment *var, int seg)
  1113. {
  1114. struct vmcb_seg *s = svm_seg(vcpu, seg);
  1115. var->base = s->base;
  1116. var->limit = s->limit;
  1117. var->selector = s->selector;
  1118. var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
  1119. var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
  1120. var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
  1121. var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
  1122. var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
  1123. var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
  1124. var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
  1125. var->g = (s->attrib >> SVM_SELECTOR_G_SHIFT) & 1;
  1126. /*
  1127. * AMD's VMCB does not have an explicit unusable field, so emulate it
  1128. * for cross vendor migration purposes by "not present"
  1129. */
  1130. var->unusable = !var->present || (var->type == 0);
  1131. switch (seg) {
  1132. case VCPU_SREG_CS:
  1133. /*
  1134. * SVM always stores 0 for the 'G' bit in the CS selector in
  1135. * the VMCB on a VMEXIT. This hurts cross-vendor migration:
  1136. * Intel's VMENTRY has a check on the 'G' bit.
  1137. */
  1138. var->g = s->limit > 0xfffff;
  1139. break;
  1140. case VCPU_SREG_TR:
  1141. /*
  1142. * Work around a bug where the busy flag in the tr selector
  1143. * isn't exposed
  1144. */
  1145. var->type |= 0x2;
  1146. break;
  1147. case VCPU_SREG_DS:
  1148. case VCPU_SREG_ES:
  1149. case VCPU_SREG_FS:
  1150. case VCPU_SREG_GS:
  1151. /*
  1152. * The accessed bit must always be set in the segment
  1153. * descriptor cache, although it can be cleared in the
  1154. * descriptor, the cached bit always remains at 1. Since
  1155. * Intel has a check on this, set it here to support
  1156. * cross-vendor migration.
  1157. */
  1158. if (!var->unusable)
  1159. var->type |= 0x1;
  1160. break;
  1161. case VCPU_SREG_SS:
  1162. /*
  1163. * On AMD CPUs sometimes the DB bit in the segment
  1164. * descriptor is left as 1, although the whole segment has
  1165. * been made unusable. Clear it here to pass an Intel VMX
  1166. * entry check when cross vendor migrating.
  1167. */
  1168. if (var->unusable)
  1169. var->db = 0;
  1170. break;
  1171. }
  1172. }
  1173. static int svm_get_cpl(struct kvm_vcpu *vcpu)
  1174. {
  1175. struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
  1176. return save->cpl;
  1177. }
  1178. static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
  1179. {
  1180. struct vcpu_svm *svm = to_svm(vcpu);
  1181. dt->size = svm->vmcb->save.idtr.limit;
  1182. dt->address = svm->vmcb->save.idtr.base;
  1183. }
  1184. static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
  1185. {
  1186. struct vcpu_svm *svm = to_svm(vcpu);
  1187. svm->vmcb->save.idtr.limit = dt->size;
  1188. svm->vmcb->save.idtr.base = dt->address ;
  1189. mark_dirty(svm->vmcb, VMCB_DT);
  1190. }
  1191. static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
  1192. {
  1193. struct vcpu_svm *svm = to_svm(vcpu);
  1194. dt->size = svm->vmcb->save.gdtr.limit;
  1195. dt->address = svm->vmcb->save.gdtr.base;
  1196. }
  1197. static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
  1198. {
  1199. struct vcpu_svm *svm = to_svm(vcpu);
  1200. svm->vmcb->save.gdtr.limit = dt->size;
  1201. svm->vmcb->save.gdtr.base = dt->address ;
  1202. mark_dirty(svm->vmcb, VMCB_DT);
  1203. }
  1204. static void svm_decache_cr0_guest_bits(struct kvm_vcpu *vcpu)
  1205. {
  1206. }
  1207. static void svm_decache_cr3(struct kvm_vcpu *vcpu)
  1208. {
  1209. }
  1210. static void svm_decache_cr4_guest_bits(struct kvm_vcpu *vcpu)
  1211. {
  1212. }
  1213. static void update_cr0_intercept(struct vcpu_svm *svm)
  1214. {
  1215. ulong gcr0 = svm->vcpu.arch.cr0;
  1216. u64 *hcr0 = &svm->vmcb->save.cr0;
  1217. if (!svm->vcpu.fpu_active)
  1218. *hcr0 |= SVM_CR0_SELECTIVE_MASK;
  1219. else
  1220. *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
  1221. | (gcr0 & SVM_CR0_SELECTIVE_MASK);
  1222. mark_dirty(svm->vmcb, VMCB_CR);
  1223. if (gcr0 == *hcr0 && svm->vcpu.fpu_active) {
  1224. clr_cr_intercept(svm, INTERCEPT_CR0_READ);
  1225. clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
  1226. } else {
  1227. set_cr_intercept(svm, INTERCEPT_CR0_READ);
  1228. set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
  1229. }
  1230. }
  1231. static void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
  1232. {
  1233. struct vcpu_svm *svm = to_svm(vcpu);
  1234. #ifdef CONFIG_X86_64
  1235. if (vcpu->arch.efer & EFER_LME) {
  1236. if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
  1237. vcpu->arch.efer |= EFER_LMA;
  1238. svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
  1239. }
  1240. if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
  1241. vcpu->arch.efer &= ~EFER_LMA;
  1242. svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
  1243. }
  1244. }
  1245. #endif
  1246. vcpu->arch.cr0 = cr0;
  1247. if (!npt_enabled)
  1248. cr0 |= X86_CR0_PG | X86_CR0_WP;
  1249. if (!vcpu->fpu_active)
  1250. cr0 |= X86_CR0_TS;
  1251. /*
  1252. * re-enable caching here because the QEMU bios
  1253. * does not do it - this results in some delay at
  1254. * reboot
  1255. */
  1256. cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
  1257. svm->vmcb->save.cr0 = cr0;
  1258. mark_dirty(svm->vmcb, VMCB_CR);
  1259. update_cr0_intercept(svm);
  1260. }
  1261. static int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
  1262. {
  1263. unsigned long host_cr4_mce = read_cr4() & X86_CR4_MCE;
  1264. unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
  1265. if (cr4 & X86_CR4_VMXE)
  1266. return 1;
  1267. if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
  1268. svm_flush_tlb(vcpu);
  1269. vcpu->arch.cr4 = cr4;
  1270. if (!npt_enabled)
  1271. cr4 |= X86_CR4_PAE;
  1272. cr4 |= host_cr4_mce;
  1273. to_svm(vcpu)->vmcb->save.cr4 = cr4;
  1274. mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
  1275. return 0;
  1276. }
  1277. static void svm_set_segment(struct kvm_vcpu *vcpu,
  1278. struct kvm_segment *var, int seg)
  1279. {
  1280. struct vcpu_svm *svm = to_svm(vcpu);
  1281. struct vmcb_seg *s = svm_seg(vcpu, seg);
  1282. s->base = var->base;
  1283. s->limit = var->limit;
  1284. s->selector = var->selector;
  1285. if (var->unusable)
  1286. s->attrib = 0;
  1287. else {
  1288. s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
  1289. s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
  1290. s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
  1291. s->attrib |= (var->present & 1) << SVM_SELECTOR_P_SHIFT;
  1292. s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
  1293. s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
  1294. s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
  1295. s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
  1296. }
  1297. if (seg == VCPU_SREG_CS)
  1298. svm_update_cpl(vcpu);
  1299. mark_dirty(svm->vmcb, VMCB_SEG);
  1300. }
  1301. static void update_db_bp_intercept(struct kvm_vcpu *vcpu)
  1302. {
  1303. struct vcpu_svm *svm = to_svm(vcpu);
  1304. clr_exception_intercept(svm, DB_VECTOR);
  1305. clr_exception_intercept(svm, BP_VECTOR);
  1306. if (svm->nmi_singlestep)
  1307. set_exception_intercept(svm, DB_VECTOR);
  1308. if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
  1309. if (vcpu->guest_debug &
  1310. (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP))
  1311. set_exception_intercept(svm, DB_VECTOR);
  1312. if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
  1313. set_exception_intercept(svm, BP_VECTOR);
  1314. } else
  1315. vcpu->guest_debug = 0;
  1316. }
  1317. static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
  1318. {
  1319. if (sd->next_asid > sd->max_asid) {
  1320. ++sd->asid_generation;
  1321. sd->next_asid = 1;
  1322. svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
  1323. }
  1324. svm->asid_generation = sd->asid_generation;
  1325. svm->vmcb->control.asid = sd->next_asid++;
  1326. mark_dirty(svm->vmcb, VMCB_ASID);
  1327. }
  1328. static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
  1329. {
  1330. struct vcpu_svm *svm = to_svm(vcpu);
  1331. svm->vmcb->save.dr7 = value;
  1332. mark_dirty(svm->vmcb, VMCB_DR);
  1333. }
  1334. static int pf_interception(struct vcpu_svm *svm)
  1335. {
  1336. u64 fault_address = svm->vmcb->control.exit_info_2;
  1337. u32 error_code;
  1338. int r = 1;
  1339. switch (svm->apf_reason) {
  1340. default:
  1341. error_code = svm->vmcb->control.exit_info_1;
  1342. trace_kvm_page_fault(fault_address, error_code);
  1343. if (!npt_enabled && kvm_event_needs_reinjection(&svm->vcpu))
  1344. kvm_mmu_unprotect_page_virt(&svm->vcpu, fault_address);
  1345. r = kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
  1346. svm->vmcb->control.insn_bytes,
  1347. svm->vmcb->control.insn_len);
  1348. break;
  1349. case KVM_PV_REASON_PAGE_NOT_PRESENT:
  1350. svm->apf_reason = 0;
  1351. local_irq_disable();
  1352. kvm_async_pf_task_wait(fault_address);
  1353. local_irq_enable();
  1354. break;
  1355. case KVM_PV_REASON_PAGE_READY:
  1356. svm->apf_reason = 0;
  1357. local_irq_disable();
  1358. kvm_async_pf_task_wake(fault_address);
  1359. local_irq_enable();
  1360. break;
  1361. }
  1362. return r;
  1363. }
  1364. static int db_interception(struct vcpu_svm *svm)
  1365. {
  1366. struct kvm_run *kvm_run = svm->vcpu.run;
  1367. if (!(svm->vcpu.guest_debug &
  1368. (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
  1369. !svm->nmi_singlestep) {
  1370. kvm_queue_exception(&svm->vcpu, DB_VECTOR);
  1371. return 1;
  1372. }
  1373. if (svm->nmi_singlestep) {
  1374. svm->nmi_singlestep = false;
  1375. if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP))
  1376. svm->vmcb->save.rflags &=
  1377. ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
  1378. update_db_bp_intercept(&svm->vcpu);
  1379. }
  1380. if (svm->vcpu.guest_debug &
  1381. (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
  1382. kvm_run->exit_reason = KVM_EXIT_DEBUG;
  1383. kvm_run->debug.arch.pc =
  1384. svm->vmcb->save.cs.base + svm->vmcb->save.rip;
  1385. kvm_run->debug.arch.exception = DB_VECTOR;
  1386. return 0;
  1387. }
  1388. return 1;
  1389. }
  1390. static int bp_interception(struct vcpu_svm *svm)
  1391. {
  1392. struct kvm_run *kvm_run = svm->vcpu.run;
  1393. kvm_run->exit_reason = KVM_EXIT_DEBUG;
  1394. kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
  1395. kvm_run->debug.arch.exception = BP_VECTOR;
  1396. return 0;
  1397. }
  1398. static int ud_interception(struct vcpu_svm *svm)
  1399. {
  1400. int er;
  1401. er = emulate_instruction(&svm->vcpu, EMULTYPE_TRAP_UD);
  1402. if (er != EMULATE_DONE)
  1403. kvm_queue_exception(&svm->vcpu, UD_VECTOR);
  1404. return 1;
  1405. }
  1406. static void svm_fpu_activate(struct kvm_vcpu *vcpu)
  1407. {
  1408. struct vcpu_svm *svm = to_svm(vcpu);
  1409. clr_exception_intercept(svm, NM_VECTOR);
  1410. svm->vcpu.fpu_active = 1;
  1411. update_cr0_intercept(svm);
  1412. }
  1413. static int nm_interception(struct vcpu_svm *svm)
  1414. {
  1415. svm_fpu_activate(&svm->vcpu);
  1416. return 1;
  1417. }
  1418. static bool is_erratum_383(void)
  1419. {
  1420. int err, i;
  1421. u64 value;
  1422. if (!erratum_383_found)
  1423. return false;
  1424. value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
  1425. if (err)
  1426. return false;
  1427. /* Bit 62 may or may not be set for this mce */
  1428. value &= ~(1ULL << 62);
  1429. if (value != 0xb600000000010015ULL)
  1430. return false;
  1431. /* Clear MCi_STATUS registers */
  1432. for (i = 0; i < 6; ++i)
  1433. native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
  1434. value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
  1435. if (!err) {
  1436. u32 low, high;
  1437. value &= ~(1ULL << 2);
  1438. low = lower_32_bits(value);
  1439. high = upper_32_bits(value);
  1440. native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
  1441. }
  1442. /* Flush tlb to evict multi-match entries */
  1443. __flush_tlb_all();
  1444. return true;
  1445. }
  1446. static void svm_handle_mce(struct vcpu_svm *svm)
  1447. {
  1448. if (is_erratum_383()) {
  1449. /*
  1450. * Erratum 383 triggered. Guest state is corrupt so kill the
  1451. * guest.
  1452. */
  1453. pr_err("KVM: Guest triggered AMD Erratum 383\n");
  1454. kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
  1455. return;
  1456. }
  1457. /*
  1458. * On an #MC intercept the MCE handler is not called automatically in
  1459. * the host. So do it by hand here.
  1460. */
  1461. asm volatile (
  1462. "int $0x12\n");
  1463. /* not sure if we ever come back to this point */
  1464. return;
  1465. }
  1466. static int mc_interception(struct vcpu_svm *svm)
  1467. {
  1468. return 1;
  1469. }
  1470. static int shutdown_interception(struct vcpu_svm *svm)
  1471. {
  1472. struct kvm_run *kvm_run = svm->vcpu.run;
  1473. /*
  1474. * VMCB is undefined after a SHUTDOWN intercept
  1475. * so reinitialize it.
  1476. */
  1477. clear_page(svm->vmcb);
  1478. init_vmcb(svm);
  1479. kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
  1480. return 0;
  1481. }
  1482. static int io_interception(struct vcpu_svm *svm)
  1483. {
  1484. struct kvm_vcpu *vcpu = &svm->vcpu;
  1485. u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
  1486. int size, in, string;
  1487. unsigned port;
  1488. ++svm->vcpu.stat.io_exits;
  1489. string = (io_info & SVM_IOIO_STR_MASK) != 0;
  1490. in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
  1491. if (string || in)
  1492. return emulate_instruction(vcpu, 0) == EMULATE_DONE;
  1493. port = io_info >> 16;
  1494. size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
  1495. svm->next_rip = svm->vmcb->control.exit_info_2;
  1496. skip_emulated_instruction(&svm->vcpu);
  1497. return kvm_fast_pio_out(vcpu, size, port);
  1498. }
  1499. static int nmi_interception(struct vcpu_svm *svm)
  1500. {
  1501. return 1;
  1502. }
  1503. static int intr_interception(struct vcpu_svm *svm)
  1504. {
  1505. ++svm->vcpu.stat.irq_exits;
  1506. return 1;
  1507. }
  1508. static int nop_on_interception(struct vcpu_svm *svm)
  1509. {
  1510. return 1;
  1511. }
  1512. static int halt_interception(struct vcpu_svm *svm)
  1513. {
  1514. svm->next_rip = kvm_rip_read(&svm->vcpu) + 1;
  1515. skip_emulated_instruction(&svm->vcpu);
  1516. return kvm_emulate_halt(&svm->vcpu);
  1517. }
  1518. static int vmmcall_interception(struct vcpu_svm *svm)
  1519. {
  1520. svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
  1521. skip_emulated_instruction(&svm->vcpu);
  1522. kvm_emulate_hypercall(&svm->vcpu);
  1523. return 1;
  1524. }
  1525. static unsigned long nested_svm_get_tdp_cr3(struct kvm_vcpu *vcpu)
  1526. {
  1527. struct vcpu_svm *svm = to_svm(vcpu);
  1528. return svm->nested.nested_cr3;
  1529. }
  1530. static u64 nested_svm_get_tdp_pdptr(struct kvm_vcpu *vcpu, int index)
  1531. {
  1532. struct vcpu_svm *svm = to_svm(vcpu);
  1533. u64 cr3 = svm->nested.nested_cr3;
  1534. u64 pdpte;
  1535. int ret;
  1536. ret = kvm_read_guest_page(vcpu->kvm, gpa_to_gfn(cr3), &pdpte,
  1537. offset_in_page(cr3) + index * 8, 8);
  1538. if (ret)
  1539. return 0;
  1540. return pdpte;
  1541. }
  1542. static void nested_svm_set_tdp_cr3(struct kvm_vcpu *vcpu,
  1543. unsigned long root)
  1544. {
  1545. struct vcpu_svm *svm = to_svm(vcpu);
  1546. svm->vmcb->control.nested_cr3 = root;
  1547. mark_dirty(svm->vmcb, VMCB_NPT);
  1548. svm_flush_tlb(vcpu);
  1549. }
  1550. static void nested_svm_inject_npf_exit(struct kvm_vcpu *vcpu,
  1551. struct x86_exception *fault)
  1552. {
  1553. struct vcpu_svm *svm = to_svm(vcpu);
  1554. svm->vmcb->control.exit_code = SVM_EXIT_NPF;
  1555. svm->vmcb->control.exit_code_hi = 0;
  1556. svm->vmcb->control.exit_info_1 = fault->error_code;
  1557. svm->vmcb->control.exit_info_2 = fault->address;
  1558. nested_svm_vmexit(svm);
  1559. }
  1560. static int nested_svm_init_mmu_context(struct kvm_vcpu *vcpu)
  1561. {
  1562. int r;
  1563. r = kvm_init_shadow_mmu(vcpu, &vcpu->arch.mmu);
  1564. vcpu->arch.mmu.set_cr3 = nested_svm_set_tdp_cr3;
  1565. vcpu->arch.mmu.get_cr3 = nested_svm_get_tdp_cr3;
  1566. vcpu->arch.mmu.get_pdptr = nested_svm_get_tdp_pdptr;
  1567. vcpu->arch.mmu.inject_page_fault = nested_svm_inject_npf_exit;
  1568. vcpu->arch.mmu.shadow_root_level = get_npt_level();
  1569. vcpu->arch.walk_mmu = &vcpu->arch.nested_mmu;
  1570. return r;
  1571. }
  1572. static void nested_svm_uninit_mmu_context(struct kvm_vcpu *vcpu)
  1573. {
  1574. vcpu->arch.walk_mmu = &vcpu->arch.mmu;
  1575. }
  1576. static int nested_svm_check_permissions(struct vcpu_svm *svm)
  1577. {
  1578. if (!(svm->vcpu.arch.efer & EFER_SVME)
  1579. || !is_paging(&svm->vcpu)) {
  1580. kvm_queue_exception(&svm->vcpu, UD_VECTOR);
  1581. return 1;
  1582. }
  1583. if (svm->vmcb->save.cpl) {
  1584. kvm_inject_gp(&svm->vcpu, 0);
  1585. return 1;
  1586. }
  1587. return 0;
  1588. }
  1589. static int nested_svm_check_exception(struct vcpu_svm *svm, unsigned nr,
  1590. bool has_error_code, u32 error_code)
  1591. {
  1592. int vmexit;
  1593. if (!is_guest_mode(&svm->vcpu))
  1594. return 0;
  1595. svm->vmcb->control.exit_code = SVM_EXIT_EXCP_BASE + nr;
  1596. svm->vmcb->control.exit_code_hi = 0;
  1597. svm->vmcb->control.exit_info_1 = error_code;
  1598. svm->vmcb->control.exit_info_2 = svm->vcpu.arch.cr2;
  1599. vmexit = nested_svm_intercept(svm);
  1600. if (vmexit == NESTED_EXIT_DONE)
  1601. svm->nested.exit_required = true;
  1602. return vmexit;
  1603. }
  1604. /* This function returns true if it is save to enable the irq window */
  1605. static inline bool nested_svm_intr(struct vcpu_svm *svm)
  1606. {
  1607. if (!is_guest_mode(&svm->vcpu))
  1608. return true;
  1609. if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
  1610. return true;
  1611. if (!(svm->vcpu.arch.hflags & HF_HIF_MASK))
  1612. return false;
  1613. /*
  1614. * if vmexit was already requested (by intercepted exception
  1615. * for instance) do not overwrite it with "external interrupt"
  1616. * vmexit.
  1617. */
  1618. if (svm->nested.exit_required)
  1619. return false;
  1620. svm->vmcb->control.exit_code = SVM_EXIT_INTR;
  1621. svm->vmcb->control.exit_info_1 = 0;
  1622. svm->vmcb->control.exit_info_2 = 0;
  1623. if (svm->nested.intercept & 1ULL) {
  1624. /*
  1625. * The #vmexit can't be emulated here directly because this
  1626. * code path runs with irqs and preemption disabled. A
  1627. * #vmexit emulation might sleep. Only signal request for
  1628. * the #vmexit here.
  1629. */
  1630. svm->nested.exit_required = true;
  1631. trace_kvm_nested_intr_vmexit(svm->vmcb->save.rip);
  1632. return false;
  1633. }
  1634. return true;
  1635. }
  1636. /* This function returns true if it is save to enable the nmi window */
  1637. static inline bool nested_svm_nmi(struct vcpu_svm *svm)
  1638. {
  1639. if (!is_guest_mode(&svm->vcpu))
  1640. return true;
  1641. if (!(svm->nested.intercept & (1ULL << INTERCEPT_NMI)))
  1642. return true;
  1643. svm->vmcb->control.exit_code = SVM_EXIT_NMI;
  1644. svm->nested.exit_required = true;
  1645. return false;
  1646. }
  1647. static void *nested_svm_map(struct vcpu_svm *svm, u64 gpa, struct page **_page)
  1648. {
  1649. struct page *page;
  1650. might_sleep();
  1651. page = gfn_to_page(svm->vcpu.kvm, gpa >> PAGE_SHIFT);
  1652. if (is_error_page(page))
  1653. goto error;
  1654. *_page = page;
  1655. return kmap(page);
  1656. error:
  1657. kvm_inject_gp(&svm->vcpu, 0);
  1658. return NULL;
  1659. }
  1660. static void nested_svm_unmap(struct page *page)
  1661. {
  1662. kunmap(page);
  1663. kvm_release_page_dirty(page);
  1664. }
  1665. static int nested_svm_intercept_ioio(struct vcpu_svm *svm)
  1666. {
  1667. unsigned port;
  1668. u8 val, bit;
  1669. u64 gpa;
  1670. if (!(svm->nested.intercept & (1ULL << INTERCEPT_IOIO_PROT)))
  1671. return NESTED_EXIT_HOST;
  1672. port = svm->vmcb->control.exit_info_1 >> 16;
  1673. gpa = svm->nested.vmcb_iopm + (port / 8);
  1674. bit = port % 8;
  1675. val = 0;
  1676. if (kvm_read_guest(svm->vcpu.kvm, gpa, &val, 1))
  1677. val &= (1 << bit);
  1678. return val ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
  1679. }
  1680. static int nested_svm_exit_handled_msr(struct vcpu_svm *svm)
  1681. {
  1682. u32 offset, msr, value;
  1683. int write, mask;
  1684. if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
  1685. return NESTED_EXIT_HOST;
  1686. msr = svm->vcpu.arch.regs[VCPU_REGS_RCX];
  1687. offset = svm_msrpm_offset(msr);
  1688. write = svm->vmcb->control.exit_info_1 & 1;
  1689. mask = 1 << ((2 * (msr & 0xf)) + write);
  1690. if (offset == MSR_INVALID)
  1691. return NESTED_EXIT_DONE;
  1692. /* Offset is in 32 bit units but need in 8 bit units */
  1693. offset *= 4;
  1694. if (kvm_read_guest(svm->vcpu.kvm, svm->nested.vmcb_msrpm + offset, &value, 4))
  1695. return NESTED_EXIT_DONE;
  1696. return (value & mask) ? NESTED_EXIT_DONE : NESTED_EXIT_HOST;
  1697. }
  1698. static int nested_svm_exit_special(struct vcpu_svm *svm)
  1699. {
  1700. u32 exit_code = svm->vmcb->control.exit_code;
  1701. switch (exit_code) {
  1702. case SVM_EXIT_INTR:
  1703. case SVM_EXIT_NMI:
  1704. case SVM_EXIT_EXCP_BASE + MC_VECTOR:
  1705. return NESTED_EXIT_HOST;
  1706. case SVM_EXIT_NPF:
  1707. /* For now we are always handling NPFs when using them */
  1708. if (npt_enabled)
  1709. return NESTED_EXIT_HOST;
  1710. break;
  1711. case SVM_EXIT_EXCP_BASE + PF_VECTOR:
  1712. /* When we're shadowing, trap PFs, but not async PF */
  1713. if (!npt_enabled && svm->apf_reason == 0)
  1714. return NESTED_EXIT_HOST;
  1715. break;
  1716. case SVM_EXIT_EXCP_BASE + NM_VECTOR:
  1717. nm_interception(svm);
  1718. break;
  1719. default:
  1720. break;
  1721. }
  1722. return NESTED_EXIT_CONTINUE;
  1723. }
  1724. /*
  1725. * If this function returns true, this #vmexit was already handled
  1726. */
  1727. static int nested_svm_intercept(struct vcpu_svm *svm)
  1728. {
  1729. u32 exit_code = svm->vmcb->control.exit_code;
  1730. int vmexit = NESTED_EXIT_HOST;
  1731. switch (exit_code) {
  1732. case SVM_EXIT_MSR:
  1733. vmexit = nested_svm_exit_handled_msr(svm);
  1734. break;
  1735. case SVM_EXIT_IOIO:
  1736. vmexit = nested_svm_intercept_ioio(svm);
  1737. break;
  1738. case SVM_EXIT_READ_CR0 ... SVM_EXIT_WRITE_CR8: {
  1739. u32 bit = 1U << (exit_code - SVM_EXIT_READ_CR0);
  1740. if (svm->nested.intercept_cr & bit)
  1741. vmexit = NESTED_EXIT_DONE;
  1742. break;
  1743. }
  1744. case SVM_EXIT_READ_DR0 ... SVM_EXIT_WRITE_DR7: {
  1745. u32 bit = 1U << (exit_code - SVM_EXIT_READ_DR0);
  1746. if (svm->nested.intercept_dr & bit)
  1747. vmexit = NESTED_EXIT_DONE;
  1748. break;
  1749. }
  1750. case SVM_EXIT_EXCP_BASE ... SVM_EXIT_EXCP_BASE + 0x1f: {
  1751. u32 excp_bits = 1 << (exit_code - SVM_EXIT_EXCP_BASE);
  1752. if (svm->nested.intercept_exceptions & excp_bits)
  1753. vmexit = NESTED_EXIT_DONE;
  1754. /* async page fault always cause vmexit */
  1755. else if ((exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR) &&
  1756. svm->apf_reason != 0)
  1757. vmexit = NESTED_EXIT_DONE;
  1758. break;
  1759. }
  1760. case SVM_EXIT_ERR: {
  1761. vmexit = NESTED_EXIT_DONE;
  1762. break;
  1763. }
  1764. default: {
  1765. u64 exit_bits = 1ULL << (exit_code - SVM_EXIT_INTR);
  1766. if (svm->nested.intercept & exit_bits)
  1767. vmexit = NESTED_EXIT_DONE;
  1768. }
  1769. }
  1770. return vmexit;
  1771. }
  1772. static int nested_svm_exit_handled(struct vcpu_svm *svm)
  1773. {
  1774. int vmexit;
  1775. vmexit = nested_svm_intercept(svm);
  1776. if (vmexit == NESTED_EXIT_DONE)
  1777. nested_svm_vmexit(svm);
  1778. return vmexit;
  1779. }
  1780. static inline void copy_vmcb_control_area(struct vmcb *dst_vmcb, struct vmcb *from_vmcb)
  1781. {
  1782. struct vmcb_control_area *dst = &dst_vmcb->control;
  1783. struct vmcb_control_area *from = &from_vmcb->control;
  1784. dst->intercept_cr = from->intercept_cr;
  1785. dst->intercept_dr = from->intercept_dr;
  1786. dst->intercept_exceptions = from->intercept_exceptions;
  1787. dst->intercept = from->intercept;
  1788. dst->iopm_base_pa = from->iopm_base_pa;
  1789. dst->msrpm_base_pa = from->msrpm_base_pa;
  1790. dst->tsc_offset = from->tsc_offset;
  1791. dst->asid = from->asid;
  1792. dst->tlb_ctl = from->tlb_ctl;
  1793. dst->int_ctl = from->int_ctl;
  1794. dst->int_vector = from->int_vector;
  1795. dst->int_state = from->int_state;
  1796. dst->exit_code = from->exit_code;
  1797. dst->exit_code_hi = from->exit_code_hi;
  1798. dst->exit_info_1 = from->exit_info_1;
  1799. dst->exit_info_2 = from->exit_info_2;
  1800. dst->exit_int_info = from->exit_int_info;
  1801. dst->exit_int_info_err = from->exit_int_info_err;
  1802. dst->nested_ctl = from->nested_ctl;
  1803. dst->event_inj = from->event_inj;
  1804. dst->event_inj_err = from->event_inj_err;
  1805. dst->nested_cr3 = from->nested_cr3;
  1806. dst->lbr_ctl = from->lbr_ctl;
  1807. }
  1808. static int nested_svm_vmexit(struct vcpu_svm *svm)
  1809. {
  1810. struct vmcb *nested_vmcb;
  1811. struct vmcb *hsave = svm->nested.hsave;
  1812. struct vmcb *vmcb = svm->vmcb;
  1813. struct page *page;
  1814. trace_kvm_nested_vmexit_inject(vmcb->control.exit_code,
  1815. vmcb->control.exit_info_1,
  1816. vmcb->control.exit_info_2,
  1817. vmcb->control.exit_int_info,
  1818. vmcb->control.exit_int_info_err,
  1819. KVM_ISA_SVM);
  1820. nested_vmcb = nested_svm_map(svm, svm->nested.vmcb, &page);
  1821. if (!nested_vmcb)
  1822. return 1;
  1823. /* Exit Guest-Mode */
  1824. leave_guest_mode(&svm->vcpu);
  1825. svm->nested.vmcb = 0;
  1826. /* Give the current vmcb to the guest */
  1827. disable_gif(svm);
  1828. nested_vmcb->save.es = vmcb->save.es;
  1829. nested_vmcb->save.cs = vmcb->save.cs;
  1830. nested_vmcb->save.ss = vmcb->save.ss;
  1831. nested_vmcb->save.ds = vmcb->save.ds;
  1832. nested_vmcb->save.gdtr = vmcb->save.gdtr;
  1833. nested_vmcb->save.idtr = vmcb->save.idtr;
  1834. nested_vmcb->save.efer = svm->vcpu.arch.efer;
  1835. nested_vmcb->save.cr0 = kvm_read_cr0(&svm->vcpu);
  1836. nested_vmcb->save.cr3 = kvm_read_cr3(&svm->vcpu);
  1837. nested_vmcb->save.cr2 = vmcb->save.cr2;
  1838. nested_vmcb->save.cr4 = svm->vcpu.arch.cr4;
  1839. nested_vmcb->save.rflags = kvm_get_rflags(&svm->vcpu);
  1840. nested_vmcb->save.rip = vmcb->save.rip;
  1841. nested_vmcb->save.rsp = vmcb->save.rsp;
  1842. nested_vmcb->save.rax = vmcb->save.rax;
  1843. nested_vmcb->save.dr7 = vmcb->save.dr7;
  1844. nested_vmcb->save.dr6 = vmcb->save.dr6;
  1845. nested_vmcb->save.cpl = vmcb->save.cpl;
  1846. nested_vmcb->control.int_ctl = vmcb->control.int_ctl;
  1847. nested_vmcb->control.int_vector = vmcb->control.int_vector;
  1848. nested_vmcb->control.int_state = vmcb->control.int_state;
  1849. nested_vmcb->control.exit_code = vmcb->control.exit_code;
  1850. nested_vmcb->control.exit_code_hi = vmcb->control.exit_code_hi;
  1851. nested_vmcb->control.exit_info_1 = vmcb->control.exit_info_1;
  1852. nested_vmcb->control.exit_info_2 = vmcb->control.exit_info_2;
  1853. nested_vmcb->control.exit_int_info = vmcb->control.exit_int_info;
  1854. nested_vmcb->control.exit_int_info_err = vmcb->control.exit_int_info_err;
  1855. nested_vmcb->control.next_rip = vmcb->control.next_rip;
  1856. /*
  1857. * If we emulate a VMRUN/#VMEXIT in the same host #vmexit cycle we have
  1858. * to make sure that we do not lose injected events. So check event_inj
  1859. * here and copy it to exit_int_info if it is valid.
  1860. * Exit_int_info and event_inj can't be both valid because the case
  1861. * below only happens on a VMRUN instruction intercept which has
  1862. * no valid exit_int_info set.
  1863. */
  1864. if (vmcb->control.event_inj & SVM_EVTINJ_VALID) {
  1865. struct vmcb_control_area *nc = &nested_vmcb->control;
  1866. nc->exit_int_info = vmcb->control.event_inj;
  1867. nc->exit_int_info_err = vmcb->control.event_inj_err;
  1868. }
  1869. nested_vmcb->control.tlb_ctl = 0;
  1870. nested_vmcb->control.event_inj = 0;
  1871. nested_vmcb->control.event_inj_err = 0;
  1872. /* We always set V_INTR_MASKING and remember the old value in hflags */
  1873. if (!(svm->vcpu.arch.hflags & HF_VINTR_MASK))
  1874. nested_vmcb->control.int_ctl &= ~V_INTR_MASKING_MASK;
  1875. /* Restore the original control entries */
  1876. copy_vmcb_control_area(vmcb, hsave);
  1877. kvm_clear_exception_queue(&svm->vcpu);
  1878. kvm_clear_interrupt_queue(&svm->vcpu);
  1879. svm->nested.nested_cr3 = 0;
  1880. /* Restore selected save entries */
  1881. svm->vmcb->save.es = hsave->save.es;
  1882. svm->vmcb->save.cs = hsave->save.cs;
  1883. svm->vmcb->save.ss = hsave->save.ss;
  1884. svm->vmcb->save.ds = hsave->save.ds;
  1885. svm->vmcb->save.gdtr = hsave->save.gdtr;
  1886. svm->vmcb->save.idtr = hsave->save.idtr;
  1887. kvm_set_rflags(&svm->vcpu, hsave->save.rflags);
  1888. svm_set_efer(&svm->vcpu, hsave->save.efer);
  1889. svm_set_cr0(&svm->vcpu, hsave->save.cr0 | X86_CR0_PE);
  1890. svm_set_cr4(&svm->vcpu, hsave->save.cr4);
  1891. if (npt_enabled) {
  1892. svm->vmcb->save.cr3 = hsave->save.cr3;
  1893. svm->vcpu.arch.cr3 = hsave->save.cr3;
  1894. } else {
  1895. (void)kvm_set_cr3(&svm->vcpu, hsave->save.cr3);
  1896. }
  1897. kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, hsave->save.rax);
  1898. kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, hsave->save.rsp);
  1899. kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, hsave->save.rip);
  1900. svm->vmcb->save.dr7 = 0;
  1901. svm->vmcb->save.cpl = 0;
  1902. svm->vmcb->control.exit_int_info = 0;
  1903. mark_all_dirty(svm->vmcb);
  1904. nested_svm_unmap(page);
  1905. nested_svm_uninit_mmu_context(&svm->vcpu);
  1906. kvm_mmu_reset_context(&svm->vcpu);
  1907. kvm_mmu_load(&svm->vcpu);
  1908. return 0;
  1909. }
  1910. static bool nested_svm_vmrun_msrpm(struct vcpu_svm *svm)
  1911. {
  1912. /*
  1913. * This function merges the msr permission bitmaps of kvm and the
  1914. * nested vmcb. It is optimized in that it only merges the parts where
  1915. * the kvm msr permission bitmap may contain zero bits
  1916. */
  1917. int i;
  1918. if (!(svm->nested.intercept & (1ULL << INTERCEPT_MSR_PROT)))
  1919. return true;
  1920. for (i = 0; i < MSRPM_OFFSETS; i++) {
  1921. u32 value, p;
  1922. u64 offset;
  1923. if (msrpm_offsets[i] == 0xffffffff)
  1924. break;
  1925. p = msrpm_offsets[i];
  1926. offset = svm->nested.vmcb_msrpm + (p * 4);
  1927. if (kvm_read_guest(svm->vcpu.kvm, offset, &value, 4))
  1928. return false;
  1929. svm->nested.msrpm[p] = svm->msrpm[p] | value;
  1930. }
  1931. svm->vmcb->control.msrpm_base_pa = __pa(svm->nested.msrpm);
  1932. return true;
  1933. }
  1934. static bool nested_vmcb_checks(struct vmcb *vmcb)
  1935. {
  1936. if ((vmcb->control.intercept & (1ULL << INTERCEPT_VMRUN)) == 0)
  1937. return false;
  1938. if (vmcb->control.asid == 0)
  1939. return false;
  1940. if (vmcb->control.nested_ctl && !npt_enabled)
  1941. return false;
  1942. return true;
  1943. }
  1944. static bool nested_svm_vmrun(struct vcpu_svm *svm)
  1945. {
  1946. struct vmcb *nested_vmcb;
  1947. struct vmcb *hsave = svm->nested.hsave;
  1948. struct vmcb *vmcb = svm->vmcb;
  1949. struct page *page;
  1950. u64 vmcb_gpa;
  1951. vmcb_gpa = svm->vmcb->save.rax;
  1952. nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
  1953. if (!nested_vmcb)
  1954. return false;
  1955. if (!nested_vmcb_checks(nested_vmcb)) {
  1956. nested_vmcb->control.exit_code = SVM_EXIT_ERR;
  1957. nested_vmcb->control.exit_code_hi = 0;
  1958. nested_vmcb->control.exit_info_1 = 0;
  1959. nested_vmcb->control.exit_info_2 = 0;
  1960. nested_svm_unmap(page);
  1961. return false;
  1962. }
  1963. trace_kvm_nested_vmrun(svm->vmcb->save.rip, vmcb_gpa,
  1964. nested_vmcb->save.rip,
  1965. nested_vmcb->control.int_ctl,
  1966. nested_vmcb->control.event_inj,
  1967. nested_vmcb->control.nested_ctl);
  1968. trace_kvm_nested_intercepts(nested_vmcb->control.intercept_cr & 0xffff,
  1969. nested_vmcb->control.intercept_cr >> 16,
  1970. nested_vmcb->control.intercept_exceptions,
  1971. nested_vmcb->control.intercept);
  1972. /* Clear internal status */
  1973. kvm_clear_exception_queue(&svm->vcpu);
  1974. kvm_clear_interrupt_queue(&svm->vcpu);
  1975. /*
  1976. * Save the old vmcb, so we don't need to pick what we save, but can
  1977. * restore everything when a VMEXIT occurs
  1978. */
  1979. hsave->save.es = vmcb->save.es;
  1980. hsave->save.cs = vmcb->save.cs;
  1981. hsave->save.ss = vmcb->save.ss;
  1982. hsave->save.ds = vmcb->save.ds;
  1983. hsave->save.gdtr = vmcb->save.gdtr;
  1984. hsave->save.idtr = vmcb->save.idtr;
  1985. hsave->save.efer = svm->vcpu.arch.efer;
  1986. hsave->save.cr0 = kvm_read_cr0(&svm->vcpu);
  1987. hsave->save.cr4 = svm->vcpu.arch.cr4;
  1988. hsave->save.rflags = kvm_get_rflags(&svm->vcpu);
  1989. hsave->save.rip = kvm_rip_read(&svm->vcpu);
  1990. hsave->save.rsp = vmcb->save.rsp;
  1991. hsave->save.rax = vmcb->save.rax;
  1992. if (npt_enabled)
  1993. hsave->save.cr3 = vmcb->save.cr3;
  1994. else
  1995. hsave->save.cr3 = kvm_read_cr3(&svm->vcpu);
  1996. copy_vmcb_control_area(hsave, vmcb);
  1997. if (kvm_get_rflags(&svm->vcpu) & X86_EFLAGS_IF)
  1998. svm->vcpu.arch.hflags |= HF_HIF_MASK;
  1999. else
  2000. svm->vcpu.arch.hflags &= ~HF_HIF_MASK;
  2001. if (nested_vmcb->control.nested_ctl) {
  2002. kvm_mmu_unload(&svm->vcpu);
  2003. svm->nested.nested_cr3 = nested_vmcb->control.nested_cr3;
  2004. nested_svm_init_mmu_context(&svm->vcpu);
  2005. }
  2006. /* Load the nested guest state */
  2007. svm->vmcb->save.es = nested_vmcb->save.es;
  2008. svm->vmcb->save.cs = nested_vmcb->save.cs;
  2009. svm->vmcb->save.ss = nested_vmcb->save.ss;
  2010. svm->vmcb->save.ds = nested_vmcb->save.ds;
  2011. svm->vmcb->save.gdtr = nested_vmcb->save.gdtr;
  2012. svm->vmcb->save.idtr = nested_vmcb->save.idtr;
  2013. kvm_set_rflags(&svm->vcpu, nested_vmcb->save.rflags);
  2014. svm_set_efer(&svm->vcpu, nested_vmcb->save.efer);
  2015. svm_set_cr0(&svm->vcpu, nested_vmcb->save.cr0);
  2016. svm_set_cr4(&svm->vcpu, nested_vmcb->save.cr4);
  2017. if (npt_enabled) {
  2018. svm->vmcb->save.cr3 = nested_vmcb->save.cr3;
  2019. svm->vcpu.arch.cr3 = nested_vmcb->save.cr3;
  2020. } else
  2021. (void)kvm_set_cr3(&svm->vcpu, nested_vmcb->save.cr3);
  2022. /* Guest paging mode is active - reset mmu */
  2023. kvm_mmu_reset_context(&svm->vcpu);
  2024. svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = nested_vmcb->save.cr2;
  2025. kvm_register_write(&svm->vcpu, VCPU_REGS_RAX, nested_vmcb->save.rax);
  2026. kvm_register_write(&svm->vcpu, VCPU_REGS_RSP, nested_vmcb->save.rsp);
  2027. kvm_register_write(&svm->vcpu, VCPU_REGS_RIP, nested_vmcb->save.rip);
  2028. /* In case we don't even reach vcpu_run, the fields are not updated */
  2029. svm->vmcb->save.rax = nested_vmcb->save.rax;
  2030. svm->vmcb->save.rsp = nested_vmcb->save.rsp;
  2031. svm->vmcb->save.rip = nested_vmcb->save.rip;
  2032. svm->vmcb->save.dr7 = nested_vmcb->save.dr7;
  2033. svm->vmcb->save.dr6 = nested_vmcb->save.dr6;
  2034. svm->vmcb->save.cpl = nested_vmcb->save.cpl;
  2035. svm->nested.vmcb_msrpm = nested_vmcb->control.msrpm_base_pa & ~0x0fffULL;
  2036. svm->nested.vmcb_iopm = nested_vmcb->control.iopm_base_pa & ~0x0fffULL;
  2037. /* cache intercepts */
  2038. svm->nested.intercept_cr = nested_vmcb->control.intercept_cr;
  2039. svm->nested.intercept_dr = nested_vmcb->control.intercept_dr;
  2040. svm->nested.intercept_exceptions = nested_vmcb->control.intercept_exceptions;
  2041. svm->nested.intercept = nested_vmcb->control.intercept;
  2042. svm_flush_tlb(&svm->vcpu);
  2043. svm->vmcb->control.int_ctl = nested_vmcb->control.int_ctl | V_INTR_MASKING_MASK;
  2044. if (nested_vmcb->control.int_ctl & V_INTR_MASKING_MASK)
  2045. svm->vcpu.arch.hflags |= HF_VINTR_MASK;
  2046. else
  2047. svm->vcpu.arch.hflags &= ~HF_VINTR_MASK;
  2048. if (svm->vcpu.arch.hflags & HF_VINTR_MASK) {
  2049. /* We only want the cr8 intercept bits of the guest */
  2050. clr_cr_intercept(svm, INTERCEPT_CR8_READ);
  2051. clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
  2052. }
  2053. /* We don't want to see VMMCALLs from a nested guest */
  2054. clr_intercept(svm, INTERCEPT_VMMCALL);
  2055. svm->vmcb->control.lbr_ctl = nested_vmcb->control.lbr_ctl;
  2056. svm->vmcb->control.int_vector = nested_vmcb->control.int_vector;
  2057. svm->vmcb->control.int_state = nested_vmcb->control.int_state;
  2058. svm->vmcb->control.tsc_offset += nested_vmcb->control.tsc_offset;
  2059. svm->vmcb->control.event_inj = nested_vmcb->control.event_inj;
  2060. svm->vmcb->control.event_inj_err = nested_vmcb->control.event_inj_err;
  2061. nested_svm_unmap(page);
  2062. /* Enter Guest-Mode */
  2063. enter_guest_mode(&svm->vcpu);
  2064. /*
  2065. * Merge guest and host intercepts - must be called with vcpu in
  2066. * guest-mode to take affect here
  2067. */
  2068. recalc_intercepts(svm);
  2069. svm->nested.vmcb = vmcb_gpa;
  2070. enable_gif(svm);
  2071. mark_all_dirty(svm->vmcb);
  2072. return true;
  2073. }
  2074. static void nested_svm_vmloadsave(struct vmcb *from_vmcb, struct vmcb *to_vmcb)
  2075. {
  2076. to_vmcb->save.fs = from_vmcb->save.fs;
  2077. to_vmcb->save.gs = from_vmcb->save.gs;
  2078. to_vmcb->save.tr = from_vmcb->save.tr;
  2079. to_vmcb->save.ldtr = from_vmcb->save.ldtr;
  2080. to_vmcb->save.kernel_gs_base = from_vmcb->save.kernel_gs_base;
  2081. to_vmcb->save.star = from_vmcb->save.star;
  2082. to_vmcb->save.lstar = from_vmcb->save.lstar;
  2083. to_vmcb->save.cstar = from_vmcb->save.cstar;
  2084. to_vmcb->save.sfmask = from_vmcb->save.sfmask;
  2085. to_vmcb->save.sysenter_cs = from_vmcb->save.sysenter_cs;
  2086. to_vmcb->save.sysenter_esp = from_vmcb->save.sysenter_esp;
  2087. to_vmcb->save.sysenter_eip = from_vmcb->save.sysenter_eip;
  2088. }
  2089. static int vmload_interception(struct vcpu_svm *svm)
  2090. {
  2091. struct vmcb *nested_vmcb;
  2092. struct page *page;
  2093. if (nested_svm_check_permissions(svm))
  2094. return 1;
  2095. nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
  2096. if (!nested_vmcb)
  2097. return 1;
  2098. svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
  2099. skip_emulated_instruction(&svm->vcpu);
  2100. nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
  2101. nested_svm_unmap(page);
  2102. return 1;
  2103. }
  2104. static int vmsave_interception(struct vcpu_svm *svm)
  2105. {
  2106. struct vmcb *nested_vmcb;
  2107. struct page *page;
  2108. if (nested_svm_check_permissions(svm))
  2109. return 1;
  2110. nested_vmcb = nested_svm_map(svm, svm->vmcb->save.rax, &page);
  2111. if (!nested_vmcb)
  2112. return 1;
  2113. svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
  2114. skip_emulated_instruction(&svm->vcpu);
  2115. nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
  2116. nested_svm_unmap(page);
  2117. return 1;
  2118. }
  2119. static int vmrun_interception(struct vcpu_svm *svm)
  2120. {
  2121. if (nested_svm_check_permissions(svm))
  2122. return 1;
  2123. /* Save rip after vmrun instruction */
  2124. kvm_rip_write(&svm->vcpu, kvm_rip_read(&svm->vcpu) + 3);
  2125. if (!nested_svm_vmrun(svm))
  2126. return 1;
  2127. if (!nested_svm_vmrun_msrpm(svm))
  2128. goto failed;
  2129. return 1;
  2130. failed:
  2131. svm->vmcb->control.exit_code = SVM_EXIT_ERR;
  2132. svm->vmcb->control.exit_code_hi = 0;
  2133. svm->vmcb->control.exit_info_1 = 0;
  2134. svm->vmcb->control.exit_info_2 = 0;
  2135. nested_svm_vmexit(svm);
  2136. return 1;
  2137. }
  2138. static int stgi_interception(struct vcpu_svm *svm)
  2139. {
  2140. if (nested_svm_check_permissions(svm))
  2141. return 1;
  2142. svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
  2143. skip_emulated_instruction(&svm->vcpu);
  2144. kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
  2145. enable_gif(svm);
  2146. return 1;
  2147. }
  2148. static int clgi_interception(struct vcpu_svm *svm)
  2149. {
  2150. if (nested_svm_check_permissions(svm))
  2151. return 1;
  2152. svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
  2153. skip_emulated_instruction(&svm->vcpu);
  2154. disable_gif(svm);
  2155. /* After a CLGI no interrupts should come */
  2156. svm_clear_vintr(svm);
  2157. svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
  2158. mark_dirty(svm->vmcb, VMCB_INTR);
  2159. return 1;
  2160. }
  2161. static int invlpga_interception(struct vcpu_svm *svm)
  2162. {
  2163. struct kvm_vcpu *vcpu = &svm->vcpu;
  2164. trace_kvm_invlpga(svm->vmcb->save.rip, vcpu->arch.regs[VCPU_REGS_RCX],
  2165. vcpu->arch.regs[VCPU_REGS_RAX]);
  2166. /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
  2167. kvm_mmu_invlpg(vcpu, vcpu->arch.regs[VCPU_REGS_RAX]);
  2168. svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
  2169. skip_emulated_instruction(&svm->vcpu);
  2170. return 1;
  2171. }
  2172. static int skinit_interception(struct vcpu_svm *svm)
  2173. {
  2174. trace_kvm_skinit(svm->vmcb->save.rip, svm->vcpu.arch.regs[VCPU_REGS_RAX]);
  2175. kvm_queue_exception(&svm->vcpu, UD_VECTOR);
  2176. return 1;
  2177. }
  2178. static int xsetbv_interception(struct vcpu_svm *svm)
  2179. {
  2180. u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
  2181. u32 index = kvm_register_read(&svm->vcpu, VCPU_REGS_RCX);
  2182. if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
  2183. svm->next_rip = kvm_rip_read(&svm->vcpu) + 3;
  2184. skip_emulated_instruction(&svm->vcpu);
  2185. }
  2186. return 1;
  2187. }
  2188. static int invalid_op_interception(struct vcpu_svm *svm)
  2189. {
  2190. kvm_queue_exception(&svm->vcpu, UD_VECTOR);
  2191. return 1;
  2192. }
  2193. static int task_switch_interception(struct vcpu_svm *svm)
  2194. {
  2195. u16 tss_selector;
  2196. int reason;
  2197. int int_type = svm->vmcb->control.exit_int_info &
  2198. SVM_EXITINTINFO_TYPE_MASK;
  2199. int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
  2200. uint32_t type =
  2201. svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
  2202. uint32_t idt_v =
  2203. svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
  2204. bool has_error_code = false;
  2205. u32 error_code = 0;
  2206. tss_selector = (u16)svm->vmcb->control.exit_info_1;
  2207. if (svm->vmcb->control.exit_info_2 &
  2208. (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
  2209. reason = TASK_SWITCH_IRET;
  2210. else if (svm->vmcb->control.exit_info_2 &
  2211. (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
  2212. reason = TASK_SWITCH_JMP;
  2213. else if (idt_v)
  2214. reason = TASK_SWITCH_GATE;
  2215. else
  2216. reason = TASK_SWITCH_CALL;
  2217. if (reason == TASK_SWITCH_GATE) {
  2218. switch (type) {
  2219. case SVM_EXITINTINFO_TYPE_NMI:
  2220. svm->vcpu.arch.nmi_injected = false;
  2221. break;
  2222. case SVM_EXITINTINFO_TYPE_EXEPT:
  2223. if (svm->vmcb->control.exit_info_2 &
  2224. (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
  2225. has_error_code = true;
  2226. error_code =
  2227. (u32)svm->vmcb->control.exit_info_2;
  2228. }
  2229. kvm_clear_exception_queue(&svm->vcpu);
  2230. break;
  2231. case SVM_EXITINTINFO_TYPE_INTR:
  2232. kvm_clear_interrupt_queue(&svm->vcpu);
  2233. break;
  2234. default:
  2235. break;
  2236. }
  2237. }
  2238. if (reason != TASK_SWITCH_GATE ||
  2239. int_type == SVM_EXITINTINFO_TYPE_SOFT ||
  2240. (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
  2241. (int_vec == OF_VECTOR || int_vec == BP_VECTOR)))
  2242. skip_emulated_instruction(&svm->vcpu);
  2243. if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
  2244. int_vec = -1;
  2245. if (kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
  2246. has_error_code, error_code) == EMULATE_FAIL) {
  2247. svm->vcpu.run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
  2248. svm->vcpu.run->internal.suberror = KVM_INTERNAL_ERROR_EMULATION;
  2249. svm->vcpu.run->internal.ndata = 0;
  2250. return 0;
  2251. }
  2252. return 1;
  2253. }
  2254. static int cpuid_interception(struct vcpu_svm *svm)
  2255. {
  2256. svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
  2257. kvm_emulate_cpuid(&svm->vcpu);
  2258. return 1;
  2259. }
  2260. static int iret_interception(struct vcpu_svm *svm)
  2261. {
  2262. ++svm->vcpu.stat.nmi_window_exits;
  2263. clr_intercept(svm, INTERCEPT_IRET);
  2264. svm->vcpu.arch.hflags |= HF_IRET_MASK;
  2265. svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
  2266. return 1;
  2267. }
  2268. static int invlpg_interception(struct vcpu_svm *svm)
  2269. {
  2270. if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
  2271. return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
  2272. kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
  2273. skip_emulated_instruction(&svm->vcpu);
  2274. return 1;
  2275. }
  2276. static int emulate_on_interception(struct vcpu_svm *svm)
  2277. {
  2278. return emulate_instruction(&svm->vcpu, 0) == EMULATE_DONE;
  2279. }
  2280. static int rdpmc_interception(struct vcpu_svm *svm)
  2281. {
  2282. int err;
  2283. if (!static_cpu_has(X86_FEATURE_NRIPS))
  2284. return emulate_on_interception(svm);
  2285. err = kvm_rdpmc(&svm->vcpu);
  2286. kvm_complete_insn_gp(&svm->vcpu, err);
  2287. return 1;
  2288. }
  2289. bool check_selective_cr0_intercepted(struct vcpu_svm *svm, unsigned long val)
  2290. {
  2291. unsigned long cr0 = svm->vcpu.arch.cr0;
  2292. bool ret = false;
  2293. u64 intercept;
  2294. intercept = svm->nested.intercept;
  2295. if (!is_guest_mode(&svm->vcpu) ||
  2296. (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
  2297. return false;
  2298. cr0 &= ~SVM_CR0_SELECTIVE_MASK;
  2299. val &= ~SVM_CR0_SELECTIVE_MASK;
  2300. if (cr0 ^ val) {
  2301. svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
  2302. ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
  2303. }
  2304. return ret;
  2305. }
  2306. #define CR_VALID (1ULL << 63)
  2307. static int cr_interception(struct vcpu_svm *svm)
  2308. {
  2309. int reg, cr;
  2310. unsigned long val;
  2311. int err;
  2312. if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
  2313. return emulate_on_interception(svm);
  2314. if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
  2315. return emulate_on_interception(svm);
  2316. reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
  2317. cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
  2318. err = 0;
  2319. if (cr >= 16) { /* mov to cr */
  2320. cr -= 16;
  2321. val = kvm_register_read(&svm->vcpu, reg);
  2322. switch (cr) {
  2323. case 0:
  2324. if (!check_selective_cr0_intercepted(svm, val))
  2325. err = kvm_set_cr0(&svm->vcpu, val);
  2326. else
  2327. return 1;
  2328. break;
  2329. case 3:
  2330. err = kvm_set_cr3(&svm->vcpu, val);
  2331. break;
  2332. case 4:
  2333. err = kvm_set_cr4(&svm->vcpu, val);
  2334. break;
  2335. case 8:
  2336. err = kvm_set_cr8(&svm->vcpu, val);
  2337. break;
  2338. default:
  2339. WARN(1, "unhandled write to CR%d", cr);
  2340. kvm_queue_exception(&svm->vcpu, UD_VECTOR);
  2341. return 1;
  2342. }
  2343. } else { /* mov from cr */
  2344. switch (cr) {
  2345. case 0:
  2346. val = kvm_read_cr0(&svm->vcpu);
  2347. break;
  2348. case 2:
  2349. val = svm->vcpu.arch.cr2;
  2350. break;
  2351. case 3:
  2352. val = kvm_read_cr3(&svm->vcpu);
  2353. break;
  2354. case 4:
  2355. val = kvm_read_cr4(&svm->vcpu);
  2356. break;
  2357. case 8:
  2358. val = kvm_get_cr8(&svm->vcpu);
  2359. break;
  2360. default:
  2361. WARN(1, "unhandled read from CR%d", cr);
  2362. kvm_queue_exception(&svm->vcpu, UD_VECTOR);
  2363. return 1;
  2364. }
  2365. kvm_register_write(&svm->vcpu, reg, val);
  2366. }
  2367. kvm_complete_insn_gp(&svm->vcpu, err);
  2368. return 1;
  2369. }
  2370. static int dr_interception(struct vcpu_svm *svm)
  2371. {
  2372. int reg, dr;
  2373. unsigned long val;
  2374. int err;
  2375. if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
  2376. return emulate_on_interception(svm);
  2377. reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
  2378. dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
  2379. if (dr >= 16) { /* mov to DRn */
  2380. val = kvm_register_read(&svm->vcpu, reg);
  2381. kvm_set_dr(&svm->vcpu, dr - 16, val);
  2382. } else {
  2383. err = kvm_get_dr(&svm->vcpu, dr, &val);
  2384. if (!err)
  2385. kvm_register_write(&svm->vcpu, reg, val);
  2386. }
  2387. skip_emulated_instruction(&svm->vcpu);
  2388. return 1;
  2389. }
  2390. static int cr8_write_interception(struct vcpu_svm *svm)
  2391. {
  2392. struct kvm_run *kvm_run = svm->vcpu.run;
  2393. int r;
  2394. u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
  2395. /* instruction emulation calls kvm_set_cr8() */
  2396. r = cr_interception(svm);
  2397. if (irqchip_in_kernel(svm->vcpu.kvm)) {
  2398. clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
  2399. return r;
  2400. }
  2401. if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
  2402. return r;
  2403. kvm_run->exit_reason = KVM_EXIT_SET_TPR;
  2404. return 0;
  2405. }
  2406. u64 svm_read_l1_tsc(struct kvm_vcpu *vcpu, u64 host_tsc)
  2407. {
  2408. struct vmcb *vmcb = get_host_vmcb(to_svm(vcpu));
  2409. return vmcb->control.tsc_offset +
  2410. svm_scale_tsc(vcpu, host_tsc);
  2411. }
  2412. static int svm_get_msr(struct kvm_vcpu *vcpu, unsigned ecx, u64 *data)
  2413. {
  2414. struct vcpu_svm *svm = to_svm(vcpu);
  2415. switch (ecx) {
  2416. case MSR_IA32_TSC: {
  2417. *data = svm->vmcb->control.tsc_offset +
  2418. svm_scale_tsc(vcpu, native_read_tsc());
  2419. break;
  2420. }
  2421. case MSR_STAR:
  2422. *data = svm->vmcb->save.star;
  2423. break;
  2424. #ifdef CONFIG_X86_64
  2425. case MSR_LSTAR:
  2426. *data = svm->vmcb->save.lstar;
  2427. break;
  2428. case MSR_CSTAR:
  2429. *data = svm->vmcb->save.cstar;
  2430. break;
  2431. case MSR_KERNEL_GS_BASE:
  2432. *data = svm->vmcb->save.kernel_gs_base;
  2433. break;
  2434. case MSR_SYSCALL_MASK:
  2435. *data = svm->vmcb->save.sfmask;
  2436. break;
  2437. #endif
  2438. case MSR_IA32_SYSENTER_CS:
  2439. *data = svm->vmcb->save.sysenter_cs;
  2440. break;
  2441. case MSR_IA32_SYSENTER_EIP:
  2442. *data = svm->sysenter_eip;
  2443. break;
  2444. case MSR_IA32_SYSENTER_ESP:
  2445. *data = svm->sysenter_esp;
  2446. break;
  2447. /*
  2448. * Nobody will change the following 5 values in the VMCB so we can
  2449. * safely return them on rdmsr. They will always be 0 until LBRV is
  2450. * implemented.
  2451. */
  2452. case MSR_IA32_DEBUGCTLMSR:
  2453. *data = svm->vmcb->save.dbgctl;
  2454. break;
  2455. case MSR_IA32_LASTBRANCHFROMIP:
  2456. *data = svm->vmcb->save.br_from;
  2457. break;
  2458. case MSR_IA32_LASTBRANCHTOIP:
  2459. *data = svm->vmcb->save.br_to;
  2460. break;
  2461. case MSR_IA32_LASTINTFROMIP:
  2462. *data = svm->vmcb->save.last_excp_from;
  2463. break;
  2464. case MSR_IA32_LASTINTTOIP:
  2465. *data = svm->vmcb->save.last_excp_to;
  2466. break;
  2467. case MSR_VM_HSAVE_PA:
  2468. *data = svm->nested.hsave_msr;
  2469. break;
  2470. case MSR_VM_CR:
  2471. *data = svm->nested.vm_cr_msr;
  2472. break;
  2473. case MSR_IA32_UCODE_REV:
  2474. *data = 0x01000065;
  2475. break;
  2476. default:
  2477. return kvm_get_msr_common(vcpu, ecx, data);
  2478. }
  2479. return 0;
  2480. }
  2481. static int rdmsr_interception(struct vcpu_svm *svm)
  2482. {
  2483. u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
  2484. u64 data;
  2485. if (svm_get_msr(&svm->vcpu, ecx, &data)) {
  2486. trace_kvm_msr_read_ex(ecx);
  2487. kvm_inject_gp(&svm->vcpu, 0);
  2488. } else {
  2489. trace_kvm_msr_read(ecx, data);
  2490. svm->vcpu.arch.regs[VCPU_REGS_RAX] = data & 0xffffffff;
  2491. svm->vcpu.arch.regs[VCPU_REGS_RDX] = data >> 32;
  2492. svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
  2493. skip_emulated_instruction(&svm->vcpu);
  2494. }
  2495. return 1;
  2496. }
  2497. static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
  2498. {
  2499. struct vcpu_svm *svm = to_svm(vcpu);
  2500. int svm_dis, chg_mask;
  2501. if (data & ~SVM_VM_CR_VALID_MASK)
  2502. return 1;
  2503. chg_mask = SVM_VM_CR_VALID_MASK;
  2504. if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
  2505. chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
  2506. svm->nested.vm_cr_msr &= ~chg_mask;
  2507. svm->nested.vm_cr_msr |= (data & chg_mask);
  2508. svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
  2509. /* check for svm_disable while efer.svme is set */
  2510. if (svm_dis && (vcpu->arch.efer & EFER_SVME))
  2511. return 1;
  2512. return 0;
  2513. }
  2514. static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
  2515. {
  2516. struct vcpu_svm *svm = to_svm(vcpu);
  2517. u32 ecx = msr->index;
  2518. u64 data = msr->data;
  2519. switch (ecx) {
  2520. case MSR_IA32_TSC:
  2521. kvm_write_tsc(vcpu, msr);
  2522. break;
  2523. case MSR_STAR:
  2524. svm->vmcb->save.star = data;
  2525. break;
  2526. #ifdef CONFIG_X86_64
  2527. case MSR_LSTAR:
  2528. svm->vmcb->save.lstar = data;
  2529. break;
  2530. case MSR_CSTAR:
  2531. svm->vmcb->save.cstar = data;
  2532. break;
  2533. case MSR_KERNEL_GS_BASE:
  2534. svm->vmcb->save.kernel_gs_base = data;
  2535. break;
  2536. case MSR_SYSCALL_MASK:
  2537. svm->vmcb->save.sfmask = data;
  2538. break;
  2539. #endif
  2540. case MSR_IA32_SYSENTER_CS:
  2541. svm->vmcb->save.sysenter_cs = data;
  2542. break;
  2543. case MSR_IA32_SYSENTER_EIP:
  2544. svm->sysenter_eip = data;
  2545. svm->vmcb->save.sysenter_eip = data;
  2546. break;
  2547. case MSR_IA32_SYSENTER_ESP:
  2548. svm->sysenter_esp = data;
  2549. svm->vmcb->save.sysenter_esp = data;
  2550. break;
  2551. case MSR_IA32_DEBUGCTLMSR:
  2552. if (!boot_cpu_has(X86_FEATURE_LBRV)) {
  2553. vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
  2554. __func__, data);
  2555. break;
  2556. }
  2557. if (data & DEBUGCTL_RESERVED_BITS)
  2558. return 1;
  2559. svm->vmcb->save.dbgctl = data;
  2560. mark_dirty(svm->vmcb, VMCB_LBR);
  2561. if (data & (1ULL<<0))
  2562. svm_enable_lbrv(svm);
  2563. else
  2564. svm_disable_lbrv(svm);
  2565. break;
  2566. case MSR_VM_HSAVE_PA:
  2567. svm->nested.hsave_msr = data;
  2568. break;
  2569. case MSR_VM_CR:
  2570. return svm_set_vm_cr(vcpu, data);
  2571. case MSR_VM_IGNNE:
  2572. vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
  2573. break;
  2574. default:
  2575. return kvm_set_msr_common(vcpu, msr);
  2576. }
  2577. return 0;
  2578. }
  2579. static int wrmsr_interception(struct vcpu_svm *svm)
  2580. {
  2581. struct msr_data msr;
  2582. u32 ecx = svm->vcpu.arch.regs[VCPU_REGS_RCX];
  2583. u64 data = (svm->vcpu.arch.regs[VCPU_REGS_RAX] & -1u)
  2584. | ((u64)(svm->vcpu.arch.regs[VCPU_REGS_RDX] & -1u) << 32);
  2585. msr.data = data;
  2586. msr.index = ecx;
  2587. msr.host_initiated = false;
  2588. svm->next_rip = kvm_rip_read(&svm->vcpu) + 2;
  2589. if (svm_set_msr(&svm->vcpu, &msr)) {
  2590. trace_kvm_msr_write_ex(ecx, data);
  2591. kvm_inject_gp(&svm->vcpu, 0);
  2592. } else {
  2593. trace_kvm_msr_write(ecx, data);
  2594. skip_emulated_instruction(&svm->vcpu);
  2595. }
  2596. return 1;
  2597. }
  2598. static int msr_interception(struct vcpu_svm *svm)
  2599. {
  2600. if (svm->vmcb->control.exit_info_1)
  2601. return wrmsr_interception(svm);
  2602. else
  2603. return rdmsr_interception(svm);
  2604. }
  2605. static int interrupt_window_interception(struct vcpu_svm *svm)
  2606. {
  2607. struct kvm_run *kvm_run = svm->vcpu.run;
  2608. kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
  2609. svm_clear_vintr(svm);
  2610. svm->vmcb->control.int_ctl &= ~V_IRQ_MASK;
  2611. mark_dirty(svm->vmcb, VMCB_INTR);
  2612. ++svm->vcpu.stat.irq_window_exits;
  2613. /*
  2614. * If the user space waits to inject interrupts, exit as soon as
  2615. * possible
  2616. */
  2617. if (!irqchip_in_kernel(svm->vcpu.kvm) &&
  2618. kvm_run->request_interrupt_window &&
  2619. !kvm_cpu_has_interrupt(&svm->vcpu)) {
  2620. kvm_run->exit_reason = KVM_EXIT_IRQ_WINDOW_OPEN;
  2621. return 0;
  2622. }
  2623. return 1;
  2624. }
  2625. static int pause_interception(struct vcpu_svm *svm)
  2626. {
  2627. kvm_vcpu_on_spin(&(svm->vcpu));
  2628. return 1;
  2629. }
  2630. static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
  2631. [SVM_EXIT_READ_CR0] = cr_interception,
  2632. [SVM_EXIT_READ_CR3] = cr_interception,
  2633. [SVM_EXIT_READ_CR4] = cr_interception,
  2634. [SVM_EXIT_READ_CR8] = cr_interception,
  2635. [SVM_EXIT_CR0_SEL_WRITE] = emulate_on_interception,
  2636. [SVM_EXIT_WRITE_CR0] = cr_interception,
  2637. [SVM_EXIT_WRITE_CR3] = cr_interception,
  2638. [SVM_EXIT_WRITE_CR4] = cr_interception,
  2639. [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
  2640. [SVM_EXIT_READ_DR0] = dr_interception,
  2641. [SVM_EXIT_READ_DR1] = dr_interception,
  2642. [SVM_EXIT_READ_DR2] = dr_interception,
  2643. [SVM_EXIT_READ_DR3] = dr_interception,
  2644. [SVM_EXIT_READ_DR4] = dr_interception,
  2645. [SVM_EXIT_READ_DR5] = dr_interception,
  2646. [SVM_EXIT_READ_DR6] = dr_interception,
  2647. [SVM_EXIT_READ_DR7] = dr_interception,
  2648. [SVM_EXIT_WRITE_DR0] = dr_interception,
  2649. [SVM_EXIT_WRITE_DR1] = dr_interception,
  2650. [SVM_EXIT_WRITE_DR2] = dr_interception,
  2651. [SVM_EXIT_WRITE_DR3] = dr_interception,
  2652. [SVM_EXIT_WRITE_DR4] = dr_interception,
  2653. [SVM_EXIT_WRITE_DR5] = dr_interception,
  2654. [SVM_EXIT_WRITE_DR6] = dr_interception,
  2655. [SVM_EXIT_WRITE_DR7] = dr_interception,
  2656. [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
  2657. [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
  2658. [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
  2659. [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
  2660. [SVM_EXIT_EXCP_BASE + NM_VECTOR] = nm_interception,
  2661. [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
  2662. [SVM_EXIT_INTR] = intr_interception,
  2663. [SVM_EXIT_NMI] = nmi_interception,
  2664. [SVM_EXIT_SMI] = nop_on_interception,
  2665. [SVM_EXIT_INIT] = nop_on_interception,
  2666. [SVM_EXIT_VINTR] = interrupt_window_interception,
  2667. [SVM_EXIT_RDPMC] = rdpmc_interception,
  2668. [SVM_EXIT_CPUID] = cpuid_interception,
  2669. [SVM_EXIT_IRET] = iret_interception,
  2670. [SVM_EXIT_INVD] = emulate_on_interception,
  2671. [SVM_EXIT_PAUSE] = pause_interception,
  2672. [SVM_EXIT_HLT] = halt_interception,
  2673. [SVM_EXIT_INVLPG] = invlpg_interception,
  2674. [SVM_EXIT_INVLPGA] = invlpga_interception,
  2675. [SVM_EXIT_IOIO] = io_interception,
  2676. [SVM_EXIT_MSR] = msr_interception,
  2677. [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
  2678. [SVM_EXIT_SHUTDOWN] = shutdown_interception,
  2679. [SVM_EXIT_VMRUN] = vmrun_interception,
  2680. [SVM_EXIT_VMMCALL] = vmmcall_interception,
  2681. [SVM_EXIT_VMLOAD] = vmload_interception,
  2682. [SVM_EXIT_VMSAVE] = vmsave_interception,
  2683. [SVM_EXIT_STGI] = stgi_interception,
  2684. [SVM_EXIT_CLGI] = clgi_interception,
  2685. [SVM_EXIT_SKINIT] = skinit_interception,
  2686. [SVM_EXIT_WBINVD] = emulate_on_interception,
  2687. [SVM_EXIT_MONITOR] = invalid_op_interception,
  2688. [SVM_EXIT_MWAIT] = invalid_op_interception,
  2689. [SVM_EXIT_XSETBV] = xsetbv_interception,
  2690. [SVM_EXIT_NPF] = pf_interception,
  2691. };
  2692. static void dump_vmcb(struct kvm_vcpu *vcpu)
  2693. {
  2694. struct vcpu_svm *svm = to_svm(vcpu);
  2695. struct vmcb_control_area *control = &svm->vmcb->control;
  2696. struct vmcb_save_area *save = &svm->vmcb->save;
  2697. pr_err("VMCB Control Area:\n");
  2698. pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
  2699. pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
  2700. pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
  2701. pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
  2702. pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
  2703. pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
  2704. pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
  2705. pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
  2706. pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
  2707. pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
  2708. pr_err("%-20s%d\n", "asid:", control->asid);
  2709. pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
  2710. pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
  2711. pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
  2712. pr_err("%-20s%08x\n", "int_state:", control->int_state);
  2713. pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
  2714. pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
  2715. pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
  2716. pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
  2717. pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
  2718. pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
  2719. pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
  2720. pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
  2721. pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
  2722. pr_err("%-20s%lld\n", "lbr_ctl:", control->lbr_ctl);
  2723. pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
  2724. pr_err("VMCB State Save Area:\n");
  2725. pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
  2726. "es:",
  2727. save->es.selector, save->es.attrib,
  2728. save->es.limit, save->es.base);
  2729. pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
  2730. "cs:",
  2731. save->cs.selector, save->cs.attrib,
  2732. save->cs.limit, save->cs.base);
  2733. pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
  2734. "ss:",
  2735. save->ss.selector, save->ss.attrib,
  2736. save->ss.limit, save->ss.base);
  2737. pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
  2738. "ds:",
  2739. save->ds.selector, save->ds.attrib,
  2740. save->ds.limit, save->ds.base);
  2741. pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
  2742. "fs:",
  2743. save->fs.selector, save->fs.attrib,
  2744. save->fs.limit, save->fs.base);
  2745. pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
  2746. "gs:",
  2747. save->gs.selector, save->gs.attrib,
  2748. save->gs.limit, save->gs.base);
  2749. pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
  2750. "gdtr:",
  2751. save->gdtr.selector, save->gdtr.attrib,
  2752. save->gdtr.limit, save->gdtr.base);
  2753. pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
  2754. "ldtr:",
  2755. save->ldtr.selector, save->ldtr.attrib,
  2756. save->ldtr.limit, save->ldtr.base);
  2757. pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
  2758. "idtr:",
  2759. save->idtr.selector, save->idtr.attrib,
  2760. save->idtr.limit, save->idtr.base);
  2761. pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
  2762. "tr:",
  2763. save->tr.selector, save->tr.attrib,
  2764. save->tr.limit, save->tr.base);
  2765. pr_err("cpl: %d efer: %016llx\n",
  2766. save->cpl, save->efer);
  2767. pr_err("%-15s %016llx %-13s %016llx\n",
  2768. "cr0:", save->cr0, "cr2:", save->cr2);
  2769. pr_err("%-15s %016llx %-13s %016llx\n",
  2770. "cr3:", save->cr3, "cr4:", save->cr4);
  2771. pr_err("%-15s %016llx %-13s %016llx\n",
  2772. "dr6:", save->dr6, "dr7:", save->dr7);
  2773. pr_err("%-15s %016llx %-13s %016llx\n",
  2774. "rip:", save->rip, "rflags:", save->rflags);
  2775. pr_err("%-15s %016llx %-13s %016llx\n",
  2776. "rsp:", save->rsp, "rax:", save->rax);
  2777. pr_err("%-15s %016llx %-13s %016llx\n",
  2778. "star:", save->star, "lstar:", save->lstar);
  2779. pr_err("%-15s %016llx %-13s %016llx\n",
  2780. "cstar:", save->cstar, "sfmask:", save->sfmask);
  2781. pr_err("%-15s %016llx %-13s %016llx\n",
  2782. "kernel_gs_base:", save->kernel_gs_base,
  2783. "sysenter_cs:", save->sysenter_cs);
  2784. pr_err("%-15s %016llx %-13s %016llx\n",
  2785. "sysenter_esp:", save->sysenter_esp,
  2786. "sysenter_eip:", save->sysenter_eip);
  2787. pr_err("%-15s %016llx %-13s %016llx\n",
  2788. "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
  2789. pr_err("%-15s %016llx %-13s %016llx\n",
  2790. "br_from:", save->br_from, "br_to:", save->br_to);
  2791. pr_err("%-15s %016llx %-13s %016llx\n",
  2792. "excp_from:", save->last_excp_from,
  2793. "excp_to:", save->last_excp_to);
  2794. }
  2795. static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
  2796. {
  2797. struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
  2798. *info1 = control->exit_info_1;
  2799. *info2 = control->exit_info_2;
  2800. }
  2801. static int handle_exit(struct kvm_vcpu *vcpu)
  2802. {
  2803. struct vcpu_svm *svm = to_svm(vcpu);
  2804. struct kvm_run *kvm_run = vcpu->run;
  2805. u32 exit_code = svm->vmcb->control.exit_code;
  2806. if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
  2807. vcpu->arch.cr0 = svm->vmcb->save.cr0;
  2808. if (npt_enabled)
  2809. vcpu->arch.cr3 = svm->vmcb->save.cr3;
  2810. if (unlikely(svm->nested.exit_required)) {
  2811. nested_svm_vmexit(svm);
  2812. svm->nested.exit_required = false;
  2813. return 1;
  2814. }
  2815. if (is_guest_mode(vcpu)) {
  2816. int vmexit;
  2817. trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
  2818. svm->vmcb->control.exit_info_1,
  2819. svm->vmcb->control.exit_info_2,
  2820. svm->vmcb->control.exit_int_info,
  2821. svm->vmcb->control.exit_int_info_err,
  2822. KVM_ISA_SVM);
  2823. vmexit = nested_svm_exit_special(svm);
  2824. if (vmexit == NESTED_EXIT_CONTINUE)
  2825. vmexit = nested_svm_exit_handled(svm);
  2826. if (vmexit == NESTED_EXIT_DONE)
  2827. return 1;
  2828. }
  2829. svm_complete_interrupts(svm);
  2830. if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
  2831. kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
  2832. kvm_run->fail_entry.hardware_entry_failure_reason
  2833. = svm->vmcb->control.exit_code;
  2834. pr_err("KVM: FAILED VMRUN WITH VMCB:\n");
  2835. dump_vmcb(vcpu);
  2836. return 0;
  2837. }
  2838. if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
  2839. exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
  2840. exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
  2841. exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
  2842. printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
  2843. "exit_code 0x%x\n",
  2844. __func__, svm->vmcb->control.exit_int_info,
  2845. exit_code);
  2846. if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
  2847. || !svm_exit_handlers[exit_code]) {
  2848. kvm_run->exit_reason = KVM_EXIT_UNKNOWN;
  2849. kvm_run->hw.hardware_exit_reason = exit_code;
  2850. return 0;
  2851. }
  2852. return svm_exit_handlers[exit_code](svm);
  2853. }
  2854. static void reload_tss(struct kvm_vcpu *vcpu)
  2855. {
  2856. int cpu = raw_smp_processor_id();
  2857. struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
  2858. sd->tss_desc->type = 9; /* available 32/64-bit TSS */
  2859. load_TR_desc();
  2860. }
  2861. static void pre_svm_run(struct vcpu_svm *svm)
  2862. {
  2863. int cpu = raw_smp_processor_id();
  2864. struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
  2865. /* FIXME: handle wraparound of asid_generation */
  2866. if (svm->asid_generation != sd->asid_generation)
  2867. new_asid(svm, sd);
  2868. }
  2869. static void svm_inject_nmi(struct kvm_vcpu *vcpu)
  2870. {
  2871. struct vcpu_svm *svm = to_svm(vcpu);
  2872. svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
  2873. vcpu->arch.hflags |= HF_NMI_MASK;
  2874. set_intercept(svm, INTERCEPT_IRET);
  2875. ++vcpu->stat.nmi_injections;
  2876. }
  2877. static inline void svm_inject_irq(struct vcpu_svm *svm, int irq)
  2878. {
  2879. struct vmcb_control_area *control;
  2880. control = &svm->vmcb->control;
  2881. control->int_vector = irq;
  2882. control->int_ctl &= ~V_INTR_PRIO_MASK;
  2883. control->int_ctl |= V_IRQ_MASK |
  2884. ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
  2885. mark_dirty(svm->vmcb, VMCB_INTR);
  2886. }
  2887. static void svm_set_irq(struct kvm_vcpu *vcpu)
  2888. {
  2889. struct vcpu_svm *svm = to_svm(vcpu);
  2890. BUG_ON(!(gif_set(svm)));
  2891. trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
  2892. ++vcpu->stat.irq_injections;
  2893. svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
  2894. SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
  2895. }
  2896. static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
  2897. {
  2898. struct vcpu_svm *svm = to_svm(vcpu);
  2899. if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
  2900. return;
  2901. if (irr == -1)
  2902. return;
  2903. if (tpr >= irr)
  2904. set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
  2905. }
  2906. static void svm_set_virtual_x2apic_mode(struct kvm_vcpu *vcpu, bool set)
  2907. {
  2908. return;
  2909. }
  2910. static int svm_vm_has_apicv(struct kvm *kvm)
  2911. {
  2912. return 0;
  2913. }
  2914. static void svm_load_eoi_exitmap(struct kvm_vcpu *vcpu, u64 *eoi_exit_bitmap)
  2915. {
  2916. return;
  2917. }
  2918. static void svm_hwapic_isr_update(struct kvm *kvm, int isr)
  2919. {
  2920. return;
  2921. }
  2922. static void svm_sync_pir_to_irr(struct kvm_vcpu *vcpu)
  2923. {
  2924. return;
  2925. }
  2926. static int svm_nmi_allowed(struct kvm_vcpu *vcpu)
  2927. {
  2928. struct vcpu_svm *svm = to_svm(vcpu);
  2929. struct vmcb *vmcb = svm->vmcb;
  2930. int ret;
  2931. ret = !(vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) &&
  2932. !(svm->vcpu.arch.hflags & HF_NMI_MASK);
  2933. ret = ret && gif_set(svm) && nested_svm_nmi(svm);
  2934. return ret;
  2935. }
  2936. static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
  2937. {
  2938. struct vcpu_svm *svm = to_svm(vcpu);
  2939. return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
  2940. }
  2941. static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
  2942. {
  2943. struct vcpu_svm *svm = to_svm(vcpu);
  2944. if (masked) {
  2945. svm->vcpu.arch.hflags |= HF_NMI_MASK;
  2946. set_intercept(svm, INTERCEPT_IRET);
  2947. } else {
  2948. svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
  2949. clr_intercept(svm, INTERCEPT_IRET);
  2950. }
  2951. }
  2952. static int svm_interrupt_allowed(struct kvm_vcpu *vcpu)
  2953. {
  2954. struct vcpu_svm *svm = to_svm(vcpu);
  2955. struct vmcb *vmcb = svm->vmcb;
  2956. int ret;
  2957. if (!gif_set(svm) ||
  2958. (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK))
  2959. return 0;
  2960. ret = !!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF);
  2961. if (is_guest_mode(vcpu))
  2962. return ret && !(svm->vcpu.arch.hflags & HF_VINTR_MASK);
  2963. return ret;
  2964. }
  2965. static int enable_irq_window(struct kvm_vcpu *vcpu)
  2966. {
  2967. struct vcpu_svm *svm = to_svm(vcpu);
  2968. /*
  2969. * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
  2970. * 1, because that's a separate STGI/VMRUN intercept. The next time we
  2971. * get that intercept, this function will be called again though and
  2972. * we'll get the vintr intercept.
  2973. */
  2974. if (gif_set(svm) && nested_svm_intr(svm)) {
  2975. svm_set_vintr(svm);
  2976. svm_inject_irq(svm, 0x0);
  2977. }
  2978. return 0;
  2979. }
  2980. static void enable_nmi_window(struct kvm_vcpu *vcpu)
  2981. {
  2982. struct vcpu_svm *svm = to_svm(vcpu);
  2983. if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
  2984. == HF_NMI_MASK)
  2985. return; /* IRET will cause a vm exit */
  2986. /*
  2987. * Something prevents NMI from been injected. Single step over possible
  2988. * problem (IRET or exception injection or interrupt shadow)
  2989. */
  2990. svm->nmi_singlestep = true;
  2991. svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
  2992. update_db_bp_intercept(vcpu);
  2993. }
  2994. static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
  2995. {
  2996. return 0;
  2997. }
  2998. static void svm_flush_tlb(struct kvm_vcpu *vcpu)
  2999. {
  3000. struct vcpu_svm *svm = to_svm(vcpu);
  3001. if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
  3002. svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
  3003. else
  3004. svm->asid_generation--;
  3005. }
  3006. static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
  3007. {
  3008. }
  3009. static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
  3010. {
  3011. struct vcpu_svm *svm = to_svm(vcpu);
  3012. if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
  3013. return;
  3014. if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
  3015. int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
  3016. kvm_set_cr8(vcpu, cr8);
  3017. }
  3018. }
  3019. static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
  3020. {
  3021. struct vcpu_svm *svm = to_svm(vcpu);
  3022. u64 cr8;
  3023. if (is_guest_mode(vcpu) && (vcpu->arch.hflags & HF_VINTR_MASK))
  3024. return;
  3025. cr8 = kvm_get_cr8(vcpu);
  3026. svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
  3027. svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
  3028. }
  3029. static void svm_complete_interrupts(struct vcpu_svm *svm)
  3030. {
  3031. u8 vector;
  3032. int type;
  3033. u32 exitintinfo = svm->vmcb->control.exit_int_info;
  3034. unsigned int3_injected = svm->int3_injected;
  3035. svm->int3_injected = 0;
  3036. /*
  3037. * If we've made progress since setting HF_IRET_MASK, we've
  3038. * executed an IRET and can allow NMI injection.
  3039. */
  3040. if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
  3041. && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
  3042. svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
  3043. kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
  3044. }
  3045. svm->vcpu.arch.nmi_injected = false;
  3046. kvm_clear_exception_queue(&svm->vcpu);
  3047. kvm_clear_interrupt_queue(&svm->vcpu);
  3048. if (!(exitintinfo & SVM_EXITINTINFO_VALID))
  3049. return;
  3050. kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
  3051. vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
  3052. type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
  3053. switch (type) {
  3054. case SVM_EXITINTINFO_TYPE_NMI:
  3055. svm->vcpu.arch.nmi_injected = true;
  3056. break;
  3057. case SVM_EXITINTINFO_TYPE_EXEPT:
  3058. /*
  3059. * In case of software exceptions, do not reinject the vector,
  3060. * but re-execute the instruction instead. Rewind RIP first
  3061. * if we emulated INT3 before.
  3062. */
  3063. if (kvm_exception_is_soft(vector)) {
  3064. if (vector == BP_VECTOR && int3_injected &&
  3065. kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
  3066. kvm_rip_write(&svm->vcpu,
  3067. kvm_rip_read(&svm->vcpu) -
  3068. int3_injected);
  3069. break;
  3070. }
  3071. if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
  3072. u32 err = svm->vmcb->control.exit_int_info_err;
  3073. kvm_requeue_exception_e(&svm->vcpu, vector, err);
  3074. } else
  3075. kvm_requeue_exception(&svm->vcpu, vector);
  3076. break;
  3077. case SVM_EXITINTINFO_TYPE_INTR:
  3078. kvm_queue_interrupt(&svm->vcpu, vector, false);
  3079. break;
  3080. default:
  3081. break;
  3082. }
  3083. }
  3084. static void svm_cancel_injection(struct kvm_vcpu *vcpu)
  3085. {
  3086. struct vcpu_svm *svm = to_svm(vcpu);
  3087. struct vmcb_control_area *control = &svm->vmcb->control;
  3088. control->exit_int_info = control->event_inj;
  3089. control->exit_int_info_err = control->event_inj_err;
  3090. control->event_inj = 0;
  3091. svm_complete_interrupts(svm);
  3092. }
  3093. static void svm_vcpu_run(struct kvm_vcpu *vcpu)
  3094. {
  3095. struct vcpu_svm *svm = to_svm(vcpu);
  3096. svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
  3097. svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
  3098. svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
  3099. /*
  3100. * A vmexit emulation is required before the vcpu can be executed
  3101. * again.
  3102. */
  3103. if (unlikely(svm->nested.exit_required))
  3104. return;
  3105. pre_svm_run(svm);
  3106. sync_lapic_to_cr8(vcpu);
  3107. svm->vmcb->save.cr2 = vcpu->arch.cr2;
  3108. clgi();
  3109. local_irq_enable();
  3110. asm volatile (
  3111. "push %%" _ASM_BP "; \n\t"
  3112. "mov %c[rbx](%[svm]), %%" _ASM_BX " \n\t"
  3113. "mov %c[rcx](%[svm]), %%" _ASM_CX " \n\t"
  3114. "mov %c[rdx](%[svm]), %%" _ASM_DX " \n\t"
  3115. "mov %c[rsi](%[svm]), %%" _ASM_SI " \n\t"
  3116. "mov %c[rdi](%[svm]), %%" _ASM_DI " \n\t"
  3117. "mov %c[rbp](%[svm]), %%" _ASM_BP " \n\t"
  3118. #ifdef CONFIG_X86_64
  3119. "mov %c[r8](%[svm]), %%r8 \n\t"
  3120. "mov %c[r9](%[svm]), %%r9 \n\t"
  3121. "mov %c[r10](%[svm]), %%r10 \n\t"
  3122. "mov %c[r11](%[svm]), %%r11 \n\t"
  3123. "mov %c[r12](%[svm]), %%r12 \n\t"
  3124. "mov %c[r13](%[svm]), %%r13 \n\t"
  3125. "mov %c[r14](%[svm]), %%r14 \n\t"
  3126. "mov %c[r15](%[svm]), %%r15 \n\t"
  3127. #endif
  3128. /* Enter guest mode */
  3129. "push %%" _ASM_AX " \n\t"
  3130. "mov %c[vmcb](%[svm]), %%" _ASM_AX " \n\t"
  3131. __ex(SVM_VMLOAD) "\n\t"
  3132. __ex(SVM_VMRUN) "\n\t"
  3133. __ex(SVM_VMSAVE) "\n\t"
  3134. "pop %%" _ASM_AX " \n\t"
  3135. /* Save guest registers, load host registers */
  3136. "mov %%" _ASM_BX ", %c[rbx](%[svm]) \n\t"
  3137. "mov %%" _ASM_CX ", %c[rcx](%[svm]) \n\t"
  3138. "mov %%" _ASM_DX ", %c[rdx](%[svm]) \n\t"
  3139. "mov %%" _ASM_SI ", %c[rsi](%[svm]) \n\t"
  3140. "mov %%" _ASM_DI ", %c[rdi](%[svm]) \n\t"
  3141. "mov %%" _ASM_BP ", %c[rbp](%[svm]) \n\t"
  3142. #ifdef CONFIG_X86_64
  3143. "mov %%r8, %c[r8](%[svm]) \n\t"
  3144. "mov %%r9, %c[r9](%[svm]) \n\t"
  3145. "mov %%r10, %c[r10](%[svm]) \n\t"
  3146. "mov %%r11, %c[r11](%[svm]) \n\t"
  3147. "mov %%r12, %c[r12](%[svm]) \n\t"
  3148. "mov %%r13, %c[r13](%[svm]) \n\t"
  3149. "mov %%r14, %c[r14](%[svm]) \n\t"
  3150. "mov %%r15, %c[r15](%[svm]) \n\t"
  3151. #endif
  3152. "pop %%" _ASM_BP
  3153. :
  3154. : [svm]"a"(svm),
  3155. [vmcb]"i"(offsetof(struct vcpu_svm, vmcb_pa)),
  3156. [rbx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBX])),
  3157. [rcx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RCX])),
  3158. [rdx]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDX])),
  3159. [rsi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RSI])),
  3160. [rdi]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RDI])),
  3161. [rbp]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_RBP]))
  3162. #ifdef CONFIG_X86_64
  3163. , [r8]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R8])),
  3164. [r9]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R9])),
  3165. [r10]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R10])),
  3166. [r11]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R11])),
  3167. [r12]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R12])),
  3168. [r13]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R13])),
  3169. [r14]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R14])),
  3170. [r15]"i"(offsetof(struct vcpu_svm, vcpu.arch.regs[VCPU_REGS_R15]))
  3171. #endif
  3172. : "cc", "memory"
  3173. #ifdef CONFIG_X86_64
  3174. , "rbx", "rcx", "rdx", "rsi", "rdi"
  3175. , "r8", "r9", "r10", "r11" , "r12", "r13", "r14", "r15"
  3176. #else
  3177. , "ebx", "ecx", "edx", "esi", "edi"
  3178. #endif
  3179. );
  3180. #ifdef CONFIG_X86_64
  3181. wrmsrl(MSR_GS_BASE, svm->host.gs_base);
  3182. #else
  3183. loadsegment(fs, svm->host.fs);
  3184. #ifndef CONFIG_X86_32_LAZY_GS
  3185. loadsegment(gs, svm->host.gs);
  3186. #endif
  3187. #endif
  3188. reload_tss(vcpu);
  3189. local_irq_disable();
  3190. vcpu->arch.cr2 = svm->vmcb->save.cr2;
  3191. vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
  3192. vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
  3193. vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
  3194. trace_kvm_exit(svm->vmcb->control.exit_code, vcpu, KVM_ISA_SVM);
  3195. if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
  3196. kvm_before_handle_nmi(&svm->vcpu);
  3197. stgi();
  3198. /* Any pending NMI will happen here */
  3199. if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
  3200. kvm_after_handle_nmi(&svm->vcpu);
  3201. sync_cr8_to_lapic(vcpu);
  3202. svm->next_rip = 0;
  3203. svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
  3204. /* if exit due to PF check for async PF */
  3205. if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
  3206. svm->apf_reason = kvm_read_and_reset_pf_reason();
  3207. if (npt_enabled) {
  3208. vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
  3209. vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
  3210. }
  3211. /*
  3212. * We need to handle MC intercepts here before the vcpu has a chance to
  3213. * change the physical cpu
  3214. */
  3215. if (unlikely(svm->vmcb->control.exit_code ==
  3216. SVM_EXIT_EXCP_BASE + MC_VECTOR))
  3217. svm_handle_mce(svm);
  3218. mark_all_clean(svm->vmcb);
  3219. }
  3220. static void svm_set_cr3(struct kvm_vcpu *vcpu, unsigned long root)
  3221. {
  3222. struct vcpu_svm *svm = to_svm(vcpu);
  3223. svm->vmcb->save.cr3 = root;
  3224. mark_dirty(svm->vmcb, VMCB_CR);
  3225. svm_flush_tlb(vcpu);
  3226. }
  3227. static void set_tdp_cr3(struct kvm_vcpu *vcpu, unsigned long root)
  3228. {
  3229. struct vcpu_svm *svm = to_svm(vcpu);
  3230. svm->vmcb->control.nested_cr3 = root;
  3231. mark_dirty(svm->vmcb, VMCB_NPT);
  3232. /* Also sync guest cr3 here in case we live migrate */
  3233. svm->vmcb->save.cr3 = kvm_read_cr3(vcpu);
  3234. mark_dirty(svm->vmcb, VMCB_CR);
  3235. svm_flush_tlb(vcpu);
  3236. }
  3237. static int is_disabled(void)
  3238. {
  3239. u64 vm_cr;
  3240. rdmsrl(MSR_VM_CR, vm_cr);
  3241. if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
  3242. return 1;
  3243. return 0;
  3244. }
  3245. static void
  3246. svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
  3247. {
  3248. /*
  3249. * Patch in the VMMCALL instruction:
  3250. */
  3251. hypercall[0] = 0x0f;
  3252. hypercall[1] = 0x01;
  3253. hypercall[2] = 0xd9;
  3254. }
  3255. static void svm_check_processor_compat(void *rtn)
  3256. {
  3257. *(int *)rtn = 0;
  3258. }
  3259. static bool svm_cpu_has_accelerated_tpr(void)
  3260. {
  3261. return false;
  3262. }
  3263. static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
  3264. {
  3265. return 0;
  3266. }
  3267. static void svm_cpuid_update(struct kvm_vcpu *vcpu)
  3268. {
  3269. }
  3270. static void svm_set_supported_cpuid(u32 func, struct kvm_cpuid_entry2 *entry)
  3271. {
  3272. switch (func) {
  3273. case 0x80000001:
  3274. if (nested)
  3275. entry->ecx |= (1 << 2); /* Set SVM bit */
  3276. break;
  3277. case 0x8000000A:
  3278. entry->eax = 1; /* SVM revision 1 */
  3279. entry->ebx = 8; /* Lets support 8 ASIDs in case we add proper
  3280. ASID emulation to nested SVM */
  3281. entry->ecx = 0; /* Reserved */
  3282. entry->edx = 0; /* Per default do not support any
  3283. additional features */
  3284. /* Support next_rip if host supports it */
  3285. if (boot_cpu_has(X86_FEATURE_NRIPS))
  3286. entry->edx |= SVM_FEATURE_NRIP;
  3287. /* Support NPT for the guest if enabled */
  3288. if (npt_enabled)
  3289. entry->edx |= SVM_FEATURE_NPT;
  3290. break;
  3291. }
  3292. }
  3293. static int svm_get_lpage_level(void)
  3294. {
  3295. return PT_PDPE_LEVEL;
  3296. }
  3297. static bool svm_rdtscp_supported(void)
  3298. {
  3299. return false;
  3300. }
  3301. static bool svm_invpcid_supported(void)
  3302. {
  3303. return false;
  3304. }
  3305. static bool svm_has_wbinvd_exit(void)
  3306. {
  3307. return true;
  3308. }
  3309. static void svm_fpu_deactivate(struct kvm_vcpu *vcpu)
  3310. {
  3311. struct vcpu_svm *svm = to_svm(vcpu);
  3312. set_exception_intercept(svm, NM_VECTOR);
  3313. update_cr0_intercept(svm);
  3314. }
  3315. #define PRE_EX(exit) { .exit_code = (exit), \
  3316. .stage = X86_ICPT_PRE_EXCEPT, }
  3317. #define POST_EX(exit) { .exit_code = (exit), \
  3318. .stage = X86_ICPT_POST_EXCEPT, }
  3319. #define POST_MEM(exit) { .exit_code = (exit), \
  3320. .stage = X86_ICPT_POST_MEMACCESS, }
  3321. static const struct __x86_intercept {
  3322. u32 exit_code;
  3323. enum x86_intercept_stage stage;
  3324. } x86_intercept_map[] = {
  3325. [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0),
  3326. [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0),
  3327. [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0),
  3328. [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0),
  3329. [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0),
  3330. [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0),
  3331. [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0),
  3332. [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ),
  3333. [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ),
  3334. [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE),
  3335. [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE),
  3336. [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ),
  3337. [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ),
  3338. [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE),
  3339. [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE),
  3340. [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN),
  3341. [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL),
  3342. [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD),
  3343. [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE),
  3344. [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI),
  3345. [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI),
  3346. [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT),
  3347. [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA),
  3348. [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP),
  3349. [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR),
  3350. [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT),
  3351. [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG),
  3352. [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD),
  3353. [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD),
  3354. [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR),
  3355. [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC),
  3356. [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR),
  3357. [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC),
  3358. [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID),
  3359. [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM),
  3360. [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE),
  3361. [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF),
  3362. [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF),
  3363. [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT),
  3364. [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET),
  3365. [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP),
  3366. [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT),
  3367. [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO),
  3368. [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO),
  3369. [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO),
  3370. [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO),
  3371. };
  3372. #undef PRE_EX
  3373. #undef POST_EX
  3374. #undef POST_MEM
  3375. static int svm_check_intercept(struct kvm_vcpu *vcpu,
  3376. struct x86_instruction_info *info,
  3377. enum x86_intercept_stage stage)
  3378. {
  3379. struct vcpu_svm *svm = to_svm(vcpu);
  3380. int vmexit, ret = X86EMUL_CONTINUE;
  3381. struct __x86_intercept icpt_info;
  3382. struct vmcb *vmcb = svm->vmcb;
  3383. if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
  3384. goto out;
  3385. icpt_info = x86_intercept_map[info->intercept];
  3386. if (stage != icpt_info.stage)
  3387. goto out;
  3388. switch (icpt_info.exit_code) {
  3389. case SVM_EXIT_READ_CR0:
  3390. if (info->intercept == x86_intercept_cr_read)
  3391. icpt_info.exit_code += info->modrm_reg;
  3392. break;
  3393. case SVM_EXIT_WRITE_CR0: {
  3394. unsigned long cr0, val;
  3395. u64 intercept;
  3396. if (info->intercept == x86_intercept_cr_write)
  3397. icpt_info.exit_code += info->modrm_reg;
  3398. if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0)
  3399. break;
  3400. intercept = svm->nested.intercept;
  3401. if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
  3402. break;
  3403. cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
  3404. val = info->src_val & ~SVM_CR0_SELECTIVE_MASK;
  3405. if (info->intercept == x86_intercept_lmsw) {
  3406. cr0 &= 0xfUL;
  3407. val &= 0xfUL;
  3408. /* lmsw can't clear PE - catch this here */
  3409. if (cr0 & X86_CR0_PE)
  3410. val |= X86_CR0_PE;
  3411. }
  3412. if (cr0 ^ val)
  3413. icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
  3414. break;
  3415. }
  3416. case SVM_EXIT_READ_DR0:
  3417. case SVM_EXIT_WRITE_DR0:
  3418. icpt_info.exit_code += info->modrm_reg;
  3419. break;
  3420. case SVM_EXIT_MSR:
  3421. if (info->intercept == x86_intercept_wrmsr)
  3422. vmcb->control.exit_info_1 = 1;
  3423. else
  3424. vmcb->control.exit_info_1 = 0;
  3425. break;
  3426. case SVM_EXIT_PAUSE:
  3427. /*
  3428. * We get this for NOP only, but pause
  3429. * is rep not, check this here
  3430. */
  3431. if (info->rep_prefix != REPE_PREFIX)
  3432. goto out;
  3433. case SVM_EXIT_IOIO: {
  3434. u64 exit_info;
  3435. u32 bytes;
  3436. exit_info = (vcpu->arch.regs[VCPU_REGS_RDX] & 0xffff) << 16;
  3437. if (info->intercept == x86_intercept_in ||
  3438. info->intercept == x86_intercept_ins) {
  3439. exit_info |= SVM_IOIO_TYPE_MASK;
  3440. bytes = info->src_bytes;
  3441. } else {
  3442. bytes = info->dst_bytes;
  3443. }
  3444. if (info->intercept == x86_intercept_outs ||
  3445. info->intercept == x86_intercept_ins)
  3446. exit_info |= SVM_IOIO_STR_MASK;
  3447. if (info->rep_prefix)
  3448. exit_info |= SVM_IOIO_REP_MASK;
  3449. bytes = min(bytes, 4u);
  3450. exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
  3451. exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
  3452. vmcb->control.exit_info_1 = exit_info;
  3453. vmcb->control.exit_info_2 = info->next_rip;
  3454. break;
  3455. }
  3456. default:
  3457. break;
  3458. }
  3459. vmcb->control.next_rip = info->next_rip;
  3460. vmcb->control.exit_code = icpt_info.exit_code;
  3461. vmexit = nested_svm_exit_handled(svm);
  3462. ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
  3463. : X86EMUL_CONTINUE;
  3464. out:
  3465. return ret;
  3466. }
  3467. static void svm_handle_external_intr(struct kvm_vcpu *vcpu)
  3468. {
  3469. local_irq_enable();
  3470. }
  3471. static struct kvm_x86_ops svm_x86_ops = {
  3472. .cpu_has_kvm_support = has_svm,
  3473. .disabled_by_bios = is_disabled,
  3474. .hardware_setup = svm_hardware_setup,
  3475. .hardware_unsetup = svm_hardware_unsetup,
  3476. .check_processor_compatibility = svm_check_processor_compat,
  3477. .hardware_enable = svm_hardware_enable,
  3478. .hardware_disable = svm_hardware_disable,
  3479. .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
  3480. .vcpu_create = svm_create_vcpu,
  3481. .vcpu_free = svm_free_vcpu,
  3482. .vcpu_reset = svm_vcpu_reset,
  3483. .prepare_guest_switch = svm_prepare_guest_switch,
  3484. .vcpu_load = svm_vcpu_load,
  3485. .vcpu_put = svm_vcpu_put,
  3486. .update_db_bp_intercept = update_db_bp_intercept,
  3487. .get_msr = svm_get_msr,
  3488. .set_msr = svm_set_msr,
  3489. .get_segment_base = svm_get_segment_base,
  3490. .get_segment = svm_get_segment,
  3491. .set_segment = svm_set_segment,
  3492. .get_cpl = svm_get_cpl,
  3493. .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
  3494. .decache_cr0_guest_bits = svm_decache_cr0_guest_bits,
  3495. .decache_cr3 = svm_decache_cr3,
  3496. .decache_cr4_guest_bits = svm_decache_cr4_guest_bits,
  3497. .set_cr0 = svm_set_cr0,
  3498. .set_cr3 = svm_set_cr3,
  3499. .set_cr4 = svm_set_cr4,
  3500. .set_efer = svm_set_efer,
  3501. .get_idt = svm_get_idt,
  3502. .set_idt = svm_set_idt,
  3503. .get_gdt = svm_get_gdt,
  3504. .set_gdt = svm_set_gdt,
  3505. .set_dr7 = svm_set_dr7,
  3506. .cache_reg = svm_cache_reg,
  3507. .get_rflags = svm_get_rflags,
  3508. .set_rflags = svm_set_rflags,
  3509. .fpu_activate = svm_fpu_activate,
  3510. .fpu_deactivate = svm_fpu_deactivate,
  3511. .tlb_flush = svm_flush_tlb,
  3512. .run = svm_vcpu_run,
  3513. .handle_exit = handle_exit,
  3514. .skip_emulated_instruction = skip_emulated_instruction,
  3515. .set_interrupt_shadow = svm_set_interrupt_shadow,
  3516. .get_interrupt_shadow = svm_get_interrupt_shadow,
  3517. .patch_hypercall = svm_patch_hypercall,
  3518. .set_irq = svm_set_irq,
  3519. .set_nmi = svm_inject_nmi,
  3520. .queue_exception = svm_queue_exception,
  3521. .cancel_injection = svm_cancel_injection,
  3522. .interrupt_allowed = svm_interrupt_allowed,
  3523. .nmi_allowed = svm_nmi_allowed,
  3524. .get_nmi_mask = svm_get_nmi_mask,
  3525. .set_nmi_mask = svm_set_nmi_mask,
  3526. .enable_nmi_window = enable_nmi_window,
  3527. .enable_irq_window = enable_irq_window,
  3528. .update_cr8_intercept = update_cr8_intercept,
  3529. .set_virtual_x2apic_mode = svm_set_virtual_x2apic_mode,
  3530. .vm_has_apicv = svm_vm_has_apicv,
  3531. .load_eoi_exitmap = svm_load_eoi_exitmap,
  3532. .hwapic_isr_update = svm_hwapic_isr_update,
  3533. .sync_pir_to_irr = svm_sync_pir_to_irr,
  3534. .set_tss_addr = svm_set_tss_addr,
  3535. .get_tdp_level = get_npt_level,
  3536. .get_mt_mask = svm_get_mt_mask,
  3537. .get_exit_info = svm_get_exit_info,
  3538. .get_lpage_level = svm_get_lpage_level,
  3539. .cpuid_update = svm_cpuid_update,
  3540. .rdtscp_supported = svm_rdtscp_supported,
  3541. .invpcid_supported = svm_invpcid_supported,
  3542. .set_supported_cpuid = svm_set_supported_cpuid,
  3543. .has_wbinvd_exit = svm_has_wbinvd_exit,
  3544. .set_tsc_khz = svm_set_tsc_khz,
  3545. .read_tsc_offset = svm_read_tsc_offset,
  3546. .write_tsc_offset = svm_write_tsc_offset,
  3547. .adjust_tsc_offset = svm_adjust_tsc_offset,
  3548. .compute_tsc_offset = svm_compute_tsc_offset,
  3549. .read_l1_tsc = svm_read_l1_tsc,
  3550. .set_tdp_cr3 = set_tdp_cr3,
  3551. .check_intercept = svm_check_intercept,
  3552. .handle_external_intr = svm_handle_external_intr,
  3553. };
  3554. static int __init svm_init(void)
  3555. {
  3556. return kvm_init(&svm_x86_ops, sizeof(struct vcpu_svm),
  3557. __alignof__(struct vcpu_svm), THIS_MODULE);
  3558. }
  3559. static void __exit svm_exit(void)
  3560. {
  3561. kvm_exit();
  3562. }
  3563. module_init(svm_init)
  3564. module_exit(svm_exit)