walnut.dts 5.2 KB

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  1. /*
  2. * Device Tree Source for IBM Walnut
  3. *
  4. * Copyright 2007 IBM Corp.
  5. * Josh Boyer <jwboyer@linux.vnet.ibm.com>
  6. *
  7. * This file is licensed under the terms of the GNU General Public
  8. * License version 2. This program is licensed "as is" without
  9. * any warranty of any kind, whether express or implied.
  10. */
  11. / {
  12. #address-cells = <1>;
  13. #size-cells = <1>;
  14. model = "ibm,walnut";
  15. compatible = "ibm,walnut";
  16. dcr-parent = <&/cpus/cpu@0>;
  17. cpus {
  18. #address-cells = <1>;
  19. #size-cells = <0>;
  20. cpu@0 {
  21. device_type = "cpu";
  22. model = "PowerPC,405GP";
  23. reg = <0>;
  24. clock-frequency = <bebc200>; /* Filled in by zImage */
  25. timebase-frequency = <0>; /* Filled in by zImage */
  26. i-cache-line-size = <20>;
  27. d-cache-line-size = <20>;
  28. i-cache-size = <4000>;
  29. d-cache-size = <4000>;
  30. dcr-controller;
  31. dcr-access-method = "native";
  32. };
  33. };
  34. memory {
  35. device_type = "memory";
  36. reg = <0 0>; /* Filled in by zImage */
  37. };
  38. UIC0: interrupt-controller {
  39. compatible = "ibm,uic";
  40. interrupt-controller;
  41. cell-index = <0>;
  42. dcr-reg = <0c0 9>;
  43. #address-cells = <0>;
  44. #size-cells = <0>;
  45. #interrupt-cells = <2>;
  46. };
  47. plb {
  48. compatible = "ibm,plb3";
  49. #address-cells = <1>;
  50. #size-cells = <1>;
  51. ranges;
  52. clock-frequency = <0>; /* Filled in by zImage */
  53. SDRAM0: memory-controller {
  54. compatible = "ibm,sdram-405gp";
  55. dcr-reg = <010 2>;
  56. };
  57. MAL: mcmal {
  58. compatible = "ibm,mcmal-405gp", "ibm,mcmal";
  59. dcr-reg = <180 62>;
  60. num-tx-chans = <1>;
  61. num-rx-chans = <1>;
  62. interrupt-parent = <&UIC0>;
  63. interrupts = <
  64. b 4 /* TXEOB */
  65. c 4 /* RXEOB */
  66. a 4 /* SERR */
  67. d 4 /* TXDE */
  68. e 4 /* RXDE */>;
  69. };
  70. POB0: opb {
  71. compatible = "ibm,opb-405gp", "ibm,opb";
  72. #address-cells = <1>;
  73. #size-cells = <1>;
  74. ranges = <ef600000 ef600000 a00000>;
  75. dcr-reg = <0a0 5>;
  76. clock-frequency = <0>; /* Filled in by zImage */
  77. UART0: serial@ef600300 {
  78. device_type = "serial";
  79. compatible = "ns16550";
  80. reg = <ef600300 8>;
  81. virtual-reg = <ef600300>;
  82. clock-frequency = <0>; /* Filled in by zImage */
  83. current-speed = <2580>;
  84. interrupt-parent = <&UIC0>;
  85. interrupts = <0 4>;
  86. };
  87. UART1: serial@ef600400 {
  88. device_type = "serial";
  89. compatible = "ns16550";
  90. reg = <ef600400 8>;
  91. virtual-reg = <ef600400>;
  92. clock-frequency = <0>; /* Filled in by zImage */
  93. current-speed = <2580>;
  94. interrupt-parent = <&UIC0>;
  95. interrupts = <1 4>;
  96. };
  97. IIC: i2c@ef600500 {
  98. compatible = "ibm,iic-405gp", "ibm,iic";
  99. reg = <ef600500 11>;
  100. interrupt-parent = <&UIC0>;
  101. interrupts = <2 4>;
  102. };
  103. GPIO: gpio@ef600700 {
  104. compatible = "ibm,gpio-405gp";
  105. reg = <ef600700 20>;
  106. };
  107. EMAC: ethernet@ef600800 {
  108. linux,network-index = <0>;
  109. device_type = "network";
  110. compatible = "ibm,emac-405gp", "ibm,emac";
  111. interrupt-parent = <&UIC0>;
  112. interrupts = <
  113. f 4 /* Ethernet */
  114. 9 4 /* Ethernet Wake Up */>;
  115. local-mac-address = [000000000000]; /* Filled in by zImage */
  116. reg = <ef600800 70>;
  117. mal-device = <&MAL>;
  118. mal-tx-channel = <0>;
  119. mal-rx-channel = <0>;
  120. cell-index = <0>;
  121. max-frame-size = <5dc>;
  122. rx-fifo-size = <1000>;
  123. tx-fifo-size = <800>;
  124. phy-mode = "rmii";
  125. phy-map = <00000001>;
  126. };
  127. };
  128. EBC0: ebc {
  129. compatible = "ibm,ebc-405gp", "ibm,ebc";
  130. dcr-reg = <012 2>;
  131. #address-cells = <2>;
  132. #size-cells = <1>;
  133. /* The ranges property is supplied by the bootwrapper
  134. * and is based on the firmware's configuration of the
  135. * EBC bridge
  136. */
  137. clock-frequency = <0>; /* Filled in by zImage */
  138. sram@0,0 {
  139. reg = <0 0 80000>;
  140. };
  141. flash@0,80000 {
  142. compatible = "jedec-flash";
  143. bank-width = <1>;
  144. reg = <0 80000 80000>;
  145. #address-cells = <1>;
  146. #size-cells = <1>;
  147. partition@0 {
  148. label = "OpenBIOS";
  149. reg = <0 80000>;
  150. read-only;
  151. };
  152. };
  153. ds1743@1,0 {
  154. /* NVRAM and RTC */
  155. compatible = "ds1743";
  156. reg = <1 0 2000>;
  157. };
  158. keyboard@2,0 {
  159. compatible = "intel,82C42PC";
  160. reg = <2 0 2>;
  161. };
  162. ir@3,0 {
  163. compatible = "ti,TIR2000PAG";
  164. reg = <3 0 10>;
  165. };
  166. fpga@7,0 {
  167. compatible = "Walnut-FPGA";
  168. reg = <7 0 10>;
  169. virtual-reg = <f0300005>;
  170. };
  171. };
  172. PCI0: pci@ec000000 {
  173. device_type = "pci";
  174. #interrupt-cells = <1>;
  175. #size-cells = <2>;
  176. #address-cells = <3>;
  177. compatible = "ibm,plb405gp-pci", "ibm,plb-pci";
  178. primary;
  179. reg = <eec00000 8 /* Config space access */
  180. eed80000 4 /* IACK */
  181. eed80000 4 /* Special cycle */
  182. ef480000 40>; /* Internal registers */
  183. /* Outbound ranges, one memory and one IO,
  184. * later cannot be changed. Chip supports a second
  185. * IO range but we don't use it for now
  186. */
  187. ranges = <02000000 0 80000000 80000000 0 20000000
  188. 01000000 0 00000000 e8000000 0 00010000>;
  189. /* Inbound 2GB range starting at 0 */
  190. dma-ranges = <42000000 0 0 0 0 80000000>;
  191. /* Walnut has all 4 IRQ pins tied together per slot */
  192. interrupt-map-mask = <f800 0 0 0>;
  193. interrupt-map = <
  194. /* IDSEL 1 */
  195. 0800 0 0 0 &UIC0 1c 8
  196. /* IDSEL 2 */
  197. 1000 0 0 0 &UIC0 1d 8
  198. /* IDSEL 3 */
  199. 1800 0 0 0 &UIC0 1e 8
  200. /* IDSEL 4 */
  201. 2000 0 0 0 &UIC0 1f 8
  202. >;
  203. };
  204. };
  205. chosen {
  206. linux,stdout-path = "/plb/opb/serial@ef600300";
  207. };
  208. };