kilauea.dts 8.9 KB

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  1. /*
  2. * Device Tree Source for AMCC Kilauea (405EX)
  3. *
  4. * Copyright 2007 DENX Software Engineering, Stefan Roese <sr@denx.de>
  5. *
  6. * This file is licensed under the terms of the GNU General Public
  7. * License version 2. This program is licensed "as is" without
  8. * any warranty of any kind, whether express or implied.
  9. */
  10. / {
  11. #address-cells = <1>;
  12. #size-cells = <1>;
  13. model = "amcc,kilauea";
  14. compatible = "amcc,kilauea";
  15. dcr-parent = <&/cpus/cpu@0>;
  16. cpus {
  17. #address-cells = <1>;
  18. #size-cells = <0>;
  19. cpu@0 {
  20. device_type = "cpu";
  21. model = "PowerPC,405EX";
  22. reg = <0>;
  23. clock-frequency = <0>; /* Filled in by U-Boot */
  24. timebase-frequency = <0>; /* Filled in by U-Boot */
  25. i-cache-line-size = <20>;
  26. d-cache-line-size = <20>;
  27. i-cache-size = <4000>; /* 16 kB */
  28. d-cache-size = <4000>; /* 16 kB */
  29. dcr-controller;
  30. dcr-access-method = "native";
  31. };
  32. };
  33. memory {
  34. device_type = "memory";
  35. reg = <0 0>; /* Filled in by U-Boot */
  36. };
  37. UIC0: interrupt-controller {
  38. compatible = "ibm,uic-405ex", "ibm,uic";
  39. interrupt-controller;
  40. cell-index = <0>;
  41. dcr-reg = <0c0 009>;
  42. #address-cells = <0>;
  43. #size-cells = <0>;
  44. #interrupt-cells = <2>;
  45. };
  46. UIC1: interrupt-controller1 {
  47. compatible = "ibm,uic-405ex","ibm,uic";
  48. interrupt-controller;
  49. cell-index = <1>;
  50. dcr-reg = <0d0 009>;
  51. #address-cells = <0>;
  52. #size-cells = <0>;
  53. #interrupt-cells = <2>;
  54. interrupts = <1e 4 1f 4>; /* cascade */
  55. interrupt-parent = <&UIC0>;
  56. };
  57. UIC2: interrupt-controller2 {
  58. compatible = "ibm,uic-405ex","ibm,uic";
  59. interrupt-controller;
  60. cell-index = <2>;
  61. dcr-reg = <0e0 009>;
  62. #address-cells = <0>;
  63. #size-cells = <0>;
  64. #interrupt-cells = <2>;
  65. interrupts = <1c 4 1d 4>; /* cascade */
  66. interrupt-parent = <&UIC0>;
  67. };
  68. plb {
  69. compatible = "ibm,plb-405ex", "ibm,plb4";
  70. #address-cells = <1>;
  71. #size-cells = <1>;
  72. ranges;
  73. clock-frequency = <0>; /* Filled in by U-Boot */
  74. SDRAM0: memory-controller {
  75. compatible = "ibm,sdram-405ex";
  76. dcr-reg = <010 2>;
  77. };
  78. MAL0: mcmal {
  79. compatible = "ibm,mcmal-405ex", "ibm,mcmal2";
  80. dcr-reg = <180 62>;
  81. num-tx-chans = <2>;
  82. num-rx-chans = <2>;
  83. interrupt-parent = <&MAL0>;
  84. interrupts = <0 1 2 3 4>;
  85. #interrupt-cells = <1>;
  86. #address-cells = <0>;
  87. #size-cells = <0>;
  88. interrupt-map = </*TXEOB*/ 0 &UIC0 a 4
  89. /*RXEOB*/ 1 &UIC0 b 4
  90. /*SERR*/ 2 &UIC1 0 4
  91. /*TXDE*/ 3 &UIC1 1 4
  92. /*RXDE*/ 4 &UIC1 2 4>;
  93. interrupt-map-mask = <ffffffff>;
  94. };
  95. POB0: opb {
  96. compatible = "ibm,opb-405ex", "ibm,opb";
  97. #address-cells = <1>;
  98. #size-cells = <1>;
  99. ranges = <80000000 80000000 10000000
  100. ef600000 ef600000 a00000
  101. f0000000 f0000000 10000000>;
  102. dcr-reg = <0a0 5>;
  103. clock-frequency = <0>; /* Filled in by U-Boot */
  104. EBC0: ebc {
  105. compatible = "ibm,ebc-405ex", "ibm,ebc";
  106. dcr-reg = <012 2>;
  107. #address-cells = <2>;
  108. #size-cells = <1>;
  109. clock-frequency = <0>; /* Filled in by U-Boot */
  110. /* ranges property is supplied by U-Boot */
  111. interrupts = <5 1>;
  112. interrupt-parent = <&UIC1>;
  113. nor_flash@0,0 {
  114. compatible = "amd,s29gl512n", "cfi-flash";
  115. bank-width = <2>;
  116. reg = <0 000000 4000000>;
  117. #address-cells = <1>;
  118. #size-cells = <1>;
  119. partition@0 {
  120. label = "kernel";
  121. reg = <0 200000>;
  122. };
  123. partition@200000 {
  124. label = "root";
  125. reg = <200000 200000>;
  126. };
  127. partition@400000 {
  128. label = "user";
  129. reg = <400000 3b60000>;
  130. };
  131. partition@3f60000 {
  132. label = "env";
  133. reg = <3f60000 40000>;
  134. };
  135. partition@3fa0000 {
  136. label = "u-boot";
  137. reg = <3fa0000 60000>;
  138. };
  139. };
  140. };
  141. UART0: serial@ef600200 {
  142. device_type = "serial";
  143. compatible = "ns16550";
  144. reg = <ef600200 8>;
  145. virtual-reg = <ef600200>;
  146. clock-frequency = <0>; /* Filled in by U-Boot */
  147. current-speed = <0>;
  148. interrupt-parent = <&UIC0>;
  149. interrupts = <1a 4>;
  150. };
  151. UART1: serial@ef600300 {
  152. device_type = "serial";
  153. compatible = "ns16550";
  154. reg = <ef600300 8>;
  155. virtual-reg = <ef600300>;
  156. clock-frequency = <0>; /* Filled in by U-Boot */
  157. current-speed = <0>;
  158. interrupt-parent = <&UIC0>;
  159. interrupts = <1 4>;
  160. };
  161. IIC0: i2c@ef600400 {
  162. device_type = "i2c";
  163. compatible = "ibm,iic-405ex", "ibm,iic";
  164. reg = <ef600400 14>;
  165. interrupt-parent = <&UIC0>;
  166. interrupts = <2 4>;
  167. };
  168. IIC1: i2c@ef600500 {
  169. device_type = "i2c";
  170. compatible = "ibm,iic-405ex", "ibm,iic";
  171. reg = <ef600500 14>;
  172. interrupt-parent = <&UIC0>;
  173. interrupts = <7 4>;
  174. };
  175. RGMII0: emac-rgmii@ef600b00 {
  176. device_type = "rgmii-interface";
  177. compatible = "ibm,rgmii-405ex", "ibm,rgmii";
  178. reg = <ef600b00 104>;
  179. has-mdio;
  180. };
  181. EMAC0: ethernet@ef600900 {
  182. linux,network-index = <0>;
  183. device_type = "network";
  184. compatible = "ibm,emac-405ex", "ibm,emac4";
  185. interrupt-parent = <&EMAC0>;
  186. interrupts = <0 1>;
  187. #interrupt-cells = <1>;
  188. #address-cells = <0>;
  189. #size-cells = <0>;
  190. interrupt-map = </*Status*/ 0 &UIC0 18 4
  191. /*Wake*/ 1 &UIC1 1d 4>;
  192. reg = <ef600900 70>;
  193. local-mac-address = [000000000000]; /* Filled in by U-Boot */
  194. mal-device = <&MAL0>;
  195. mal-tx-channel = <0>;
  196. mal-rx-channel = <0>;
  197. cell-index = <0>;
  198. max-frame-size = <5dc>;
  199. rx-fifo-size = <1000>;
  200. tx-fifo-size = <800>;
  201. phy-mode = "rgmii";
  202. phy-map = <00000000>;
  203. rgmii-device = <&RGMII0>;
  204. rgmii-channel = <0>;
  205. has-inverted-stacr-oc;
  206. has-new-stacr-staopc;
  207. };
  208. EMAC1: ethernet@ef600a00 {
  209. linux,network-index = <1>;
  210. device_type = "network";
  211. compatible = "ibm,emac-405ex", "ibm,emac4";
  212. interrupt-parent = <&EMAC1>;
  213. interrupts = <0 1>;
  214. #interrupt-cells = <1>;
  215. #address-cells = <0>;
  216. #size-cells = <0>;
  217. interrupt-map = </*Status*/ 0 &UIC0 19 4
  218. /*Wake*/ 1 &UIC1 1f 4>;
  219. reg = <ef600a00 70>;
  220. local-mac-address = [000000000000]; /* Filled in by U-Boot */
  221. mal-device = <&MAL0>;
  222. mal-tx-channel = <1>;
  223. mal-rx-channel = <1>;
  224. cell-index = <1>;
  225. max-frame-size = <5dc>;
  226. rx-fifo-size = <1000>;
  227. tx-fifo-size = <800>;
  228. phy-mode = "rgmii";
  229. phy-map = <00000000>;
  230. rgmii-device = <&RGMII0>;
  231. rgmii-channel = <1>;
  232. has-inverted-stacr-oc;
  233. has-new-stacr-staopc;
  234. };
  235. };
  236. PCIE0: pciex@0a0000000 {
  237. device_type = "pci";
  238. #interrupt-cells = <1>;
  239. #size-cells = <2>;
  240. #address-cells = <3>;
  241. compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex";
  242. primary;
  243. port = <0>; /* port number */
  244. reg = <a0000000 20000000 /* Config space access */
  245. ef000000 00001000>; /* Registers */
  246. dcr-reg = <040 020>;
  247. sdr-base = <400>;
  248. /* Outbound ranges, one memory and one IO,
  249. * later cannot be changed
  250. */
  251. ranges = <02000000 0 80000000 90000000 0 08000000
  252. 01000000 0 00000000 e0000000 0 00010000>;
  253. /* Inbound 2GB range starting at 0 */
  254. dma-ranges = <42000000 0 0 0 0 80000000>;
  255. /* This drives busses 0x00 to 0x0f */
  256. bus-range = <00 0f>;
  257. /* Legacy interrupts (note the weird polarity, the bridge seems
  258. * to invert PCIe legacy interrupts).
  259. * We are de-swizzling here because the numbers are actually for
  260. * port of the root complex virtual P2P bridge. But I want
  261. * to avoid putting a node for it in the tree, so the numbers
  262. * below are basically de-swizzled numbers.
  263. * The real slot is on idsel 0, so the swizzling is 1:1
  264. */
  265. interrupt-map-mask = <0000 0 0 7>;
  266. interrupt-map = <
  267. 0000 0 0 1 &UIC2 0 4 /* swizzled int A */
  268. 0000 0 0 2 &UIC2 1 4 /* swizzled int B */
  269. 0000 0 0 3 &UIC2 2 4 /* swizzled int C */
  270. 0000 0 0 4 &UIC2 3 4 /* swizzled int D */>;
  271. };
  272. PCIE1: pciex@0c0000000 {
  273. device_type = "pci";
  274. #interrupt-cells = <1>;
  275. #size-cells = <2>;
  276. #address-cells = <3>;
  277. compatible = "ibm,plb-pciex-405ex", "ibm,plb-pciex";
  278. primary;
  279. port = <1>; /* port number */
  280. reg = <c0000000 20000000 /* Config space access */
  281. ef001000 00001000>; /* Registers */
  282. dcr-reg = <060 020>;
  283. sdr-base = <440>;
  284. /* Outbound ranges, one memory and one IO,
  285. * later cannot be changed
  286. */
  287. ranges = <02000000 0 80000000 98000000 0 08000000
  288. 01000000 0 00000000 e0010000 0 00010000>;
  289. /* Inbound 2GB range starting at 0 */
  290. dma-ranges = <42000000 0 0 0 0 80000000>;
  291. /* This drives busses 0x10 to 0x1f */
  292. bus-range = <10 1f>;
  293. /* Legacy interrupts (note the weird polarity, the bridge seems
  294. * to invert PCIe legacy interrupts).
  295. * We are de-swizzling here because the numbers are actually for
  296. * port of the root complex virtual P2P bridge. But I want
  297. * to avoid putting a node for it in the tree, so the numbers
  298. * below are basically de-swizzled numbers.
  299. * The real slot is on idsel 0, so the swizzling is 1:1
  300. */
  301. interrupt-map-mask = <0000 0 0 7>;
  302. interrupt-map = <
  303. 0000 0 0 1 &UIC2 b 4 /* swizzled int A */
  304. 0000 0 0 2 &UIC2 c 4 /* swizzled int B */
  305. 0000 0 0 3 &UIC2 d 4 /* swizzled int C */
  306. 0000 0 0 4 &UIC2 e 4 /* swizzled int D */>;
  307. };
  308. };
  309. };