katmai.dts 11 KB

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  1. /*
  2. * Device Tree Source for AMCC Katmai eval board
  3. *
  4. * Copyright (c) 2006, 2007 IBM Corp.
  5. * Benjamin Herrenschmidt <benh@kernel.crashing.org>
  6. *
  7. * Copyright (c) 2006, 2007 IBM Corp.
  8. * Josh Boyer <jwboyer@linux.vnet.ibm.com>
  9. *
  10. * This file is licensed under the terms of the GNU General Public
  11. * License version 2. This program is licensed "as is" without
  12. * any warranty of any kind, whether express or implied.
  13. */
  14. / {
  15. #address-cells = <2>;
  16. #size-cells = <1>;
  17. model = "amcc,katmai";
  18. compatible = "amcc,katmai";
  19. dcr-parent = <&/cpus/cpu@0>;
  20. cpus {
  21. #address-cells = <1>;
  22. #size-cells = <0>;
  23. cpu@0 {
  24. device_type = "cpu";
  25. model = "PowerPC,440SPe";
  26. reg = <0>;
  27. clock-frequency = <0>; /* Filled in by zImage */
  28. timebase-frequency = <0>; /* Filled in by zImage */
  29. i-cache-line-size = <20>;
  30. d-cache-line-size = <20>;
  31. i-cache-size = <20000>;
  32. d-cache-size = <20000>;
  33. dcr-controller;
  34. dcr-access-method = "native";
  35. };
  36. };
  37. memory {
  38. device_type = "memory";
  39. reg = <0 0 0>; /* Filled in by zImage */
  40. };
  41. UIC0: interrupt-controller0 {
  42. compatible = "ibm,uic-440spe","ibm,uic";
  43. interrupt-controller;
  44. cell-index = <0>;
  45. dcr-reg = <0c0 009>;
  46. #address-cells = <0>;
  47. #size-cells = <0>;
  48. #interrupt-cells = <2>;
  49. };
  50. UIC1: interrupt-controller1 {
  51. compatible = "ibm,uic-440spe","ibm,uic";
  52. interrupt-controller;
  53. cell-index = <1>;
  54. dcr-reg = <0d0 009>;
  55. #address-cells = <0>;
  56. #size-cells = <0>;
  57. #interrupt-cells = <2>;
  58. interrupts = <1e 4 1f 4>; /* cascade */
  59. interrupt-parent = <&UIC0>;
  60. };
  61. UIC2: interrupt-controller2 {
  62. compatible = "ibm,uic-440spe","ibm,uic";
  63. interrupt-controller;
  64. cell-index = <2>;
  65. dcr-reg = <0e0 009>;
  66. #address-cells = <0>;
  67. #size-cells = <0>;
  68. #interrupt-cells = <2>;
  69. interrupts = <a 4 b 4>; /* cascade */
  70. interrupt-parent = <&UIC0>;
  71. };
  72. UIC3: interrupt-controller3 {
  73. compatible = "ibm,uic-440spe","ibm,uic";
  74. interrupt-controller;
  75. cell-index = <3>;
  76. dcr-reg = <0f0 009>;
  77. #address-cells = <0>;
  78. #size-cells = <0>;
  79. #interrupt-cells = <2>;
  80. interrupts = <10 4 11 4>; /* cascade */
  81. interrupt-parent = <&UIC0>;
  82. };
  83. SDR0: sdr {
  84. compatible = "ibm,sdr-440spe";
  85. dcr-reg = <00e 002>;
  86. };
  87. CPR0: cpr {
  88. compatible = "ibm,cpr-440spe";
  89. dcr-reg = <00c 002>;
  90. };
  91. plb {
  92. compatible = "ibm,plb-440spe", "ibm,plb-440gp", "ibm,plb4";
  93. #address-cells = <2>;
  94. #size-cells = <1>;
  95. ranges;
  96. clock-frequency = <0>; /* Filled in by zImage */
  97. SDRAM0: sdram {
  98. compatible = "ibm,sdram-440spe", "ibm,sdram-405gp";
  99. dcr-reg = <010 2>;
  100. };
  101. MAL0: mcmal {
  102. compatible = "ibm,mcmal-440spe", "ibm,mcmal2";
  103. dcr-reg = <180 62>;
  104. num-tx-chans = <2>;
  105. num-rx-chans = <1>;
  106. interrupt-parent = <&MAL0>;
  107. interrupts = <0 1 2 3 4>;
  108. #interrupt-cells = <1>;
  109. #address-cells = <0>;
  110. #size-cells = <0>;
  111. interrupt-map = </*TXEOB*/ 0 &UIC1 6 4
  112. /*RXEOB*/ 1 &UIC1 7 4
  113. /*SERR*/ 2 &UIC1 1 4
  114. /*TXDE*/ 3 &UIC1 2 4
  115. /*RXDE*/ 4 &UIC1 3 4>;
  116. };
  117. POB0: opb {
  118. compatible = "ibm,opb-440spe", "ibm,opb-440gp", "ibm,opb";
  119. #address-cells = <1>;
  120. #size-cells = <1>;
  121. ranges = <00000000 4 e0000000 20000000>;
  122. clock-frequency = <0>; /* Filled in by zImage */
  123. EBC0: ebc {
  124. compatible = "ibm,ebc-440spe", "ibm,ebc-440gp", "ibm,ebc";
  125. dcr-reg = <012 2>;
  126. #address-cells = <2>;
  127. #size-cells = <1>;
  128. clock-frequency = <0>; /* Filled in by zImage */
  129. interrupts = <5 1>;
  130. interrupt-parent = <&UIC1>;
  131. };
  132. UART0: serial@10000200 {
  133. device_type = "serial";
  134. compatible = "ns16550";
  135. reg = <10000200 8>;
  136. virtual-reg = <a0000200>;
  137. clock-frequency = <0>; /* Filled in by zImage */
  138. current-speed = <1c200>;
  139. interrupt-parent = <&UIC0>;
  140. interrupts = <0 4>;
  141. };
  142. UART1: serial@10000300 {
  143. device_type = "serial";
  144. compatible = "ns16550";
  145. reg = <10000300 8>;
  146. virtual-reg = <a0000300>;
  147. clock-frequency = <0>;
  148. current-speed = <0>;
  149. interrupt-parent = <&UIC0>;
  150. interrupts = <1 4>;
  151. };
  152. UART2: serial@10000600 {
  153. device_type = "serial";
  154. compatible = "ns16550";
  155. reg = <10000600 8>;
  156. virtual-reg = <a0000600>;
  157. clock-frequency = <0>;
  158. current-speed = <0>;
  159. interrupt-parent = <&UIC1>;
  160. interrupts = <5 4>;
  161. };
  162. IIC0: i2c@10000400 {
  163. device_type = "i2c";
  164. compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic";
  165. reg = <10000400 14>;
  166. interrupt-parent = <&UIC0>;
  167. interrupts = <2 4>;
  168. };
  169. IIC1: i2c@10000500 {
  170. device_type = "i2c";
  171. compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic";
  172. reg = <10000500 14>;
  173. interrupt-parent = <&UIC0>;
  174. interrupts = <3 4>;
  175. };
  176. EMAC0: ethernet@10000800 {
  177. linux,network-index = <0>;
  178. device_type = "network";
  179. compatible = "ibm,emac-440spe", "ibm,emac4";
  180. interrupt-parent = <&UIC1>;
  181. interrupts = <1c 4 1d 4>;
  182. reg = <10000800 70>;
  183. local-mac-address = [000000000000];
  184. mal-device = <&MAL0>;
  185. mal-tx-channel = <0>;
  186. mal-rx-channel = <0>;
  187. cell-index = <0>;
  188. max-frame-size = <5dc>;
  189. rx-fifo-size = <1000>;
  190. tx-fifo-size = <800>;
  191. phy-mode = "gmii";
  192. phy-map = <00000000>;
  193. has-inverted-stacr-oc;
  194. has-new-stacr-staopc;
  195. };
  196. };
  197. PCIX0: pci@c0ec00000 {
  198. device_type = "pci";
  199. #interrupt-cells = <1>;
  200. #size-cells = <2>;
  201. #address-cells = <3>;
  202. compatible = "ibm,plb-pcix-440spe", "ibm,plb-pcix";
  203. primary;
  204. large-inbound-windows;
  205. enable-msi-hole;
  206. reg = <c 0ec00000 8 /* Config space access */
  207. 0 0 0 /* no IACK cycles */
  208. c 0ed00000 4 /* Special cycles */
  209. c 0ec80000 100 /* Internal registers */
  210. c 0ec80100 fc>; /* Internal messaging registers */
  211. /* Outbound ranges, one memory and one IO,
  212. * later cannot be changed
  213. */
  214. ranges = <02000000 0 80000000 0000000d 80000000 0 80000000
  215. 01000000 0 00000000 0000000c 08000000 0 00010000>;
  216. /* Inbound 2GB range starting at 0 */
  217. dma-ranges = <42000000 0 0 0 0 0 80000000>;
  218. /* This drives busses 0 to 0xf */
  219. bus-range = <0 f>;
  220. /*
  221. * On Katmai, the following PCI-X interrupts signals
  222. * have to be enabled via jumpers (only INTA is
  223. * enabled per default):
  224. *
  225. * INTB: J3: 1-2
  226. * INTC: J2: 1-2
  227. * INTD: J1: 1-2
  228. */
  229. interrupt-map-mask = <f800 0 0 7>;
  230. interrupt-map = <
  231. /* IDSEL 1 */
  232. 0800 0 0 1 &UIC1 14 8
  233. 0800 0 0 2 &UIC1 13 8
  234. 0800 0 0 3 &UIC1 12 8
  235. 0800 0 0 4 &UIC1 11 8
  236. >;
  237. };
  238. PCIE0: pciex@d00000000 {
  239. device_type = "pci";
  240. #interrupt-cells = <1>;
  241. #size-cells = <2>;
  242. #address-cells = <3>;
  243. compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex";
  244. primary;
  245. port = <0>; /* port number */
  246. reg = <d 00000000 20000000 /* Config space access */
  247. c 10000000 00001000>; /* Registers */
  248. dcr-reg = <100 020>;
  249. sdr-base = <300>;
  250. /* Outbound ranges, one memory and one IO,
  251. * later cannot be changed
  252. */
  253. ranges = <02000000 0 80000000 0000000e 00000000 0 80000000
  254. 01000000 0 00000000 0000000f 80000000 0 00010000>;
  255. /* Inbound 2GB range starting at 0 */
  256. dma-ranges = <42000000 0 0 0 0 0 80000000>;
  257. /* This drives busses 10 to 0x1f */
  258. bus-range = <10 1f>;
  259. /* Legacy interrupts (note the weird polarity, the bridge seems
  260. * to invert PCIe legacy interrupts).
  261. * We are de-swizzling here because the numbers are actually for
  262. * port of the root complex virtual P2P bridge. But I want
  263. * to avoid putting a node for it in the tree, so the numbers
  264. * below are basically de-swizzled numbers.
  265. * The real slot is on idsel 0, so the swizzling is 1:1
  266. */
  267. interrupt-map-mask = <0000 0 0 7>;
  268. interrupt-map = <
  269. 0000 0 0 1 &UIC3 0 4 /* swizzled int A */
  270. 0000 0 0 2 &UIC3 1 4 /* swizzled int B */
  271. 0000 0 0 3 &UIC3 2 4 /* swizzled int C */
  272. 0000 0 0 4 &UIC3 3 4 /* swizzled int D */>;
  273. };
  274. PCIE1: pciex@d20000000 {
  275. device_type = "pci";
  276. #interrupt-cells = <1>;
  277. #size-cells = <2>;
  278. #address-cells = <3>;
  279. compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex";
  280. primary;
  281. port = <1>; /* port number */
  282. reg = <d 20000000 20000000 /* Config space access */
  283. c 10001000 00001000>; /* Registers */
  284. dcr-reg = <120 020>;
  285. sdr-base = <340>;
  286. /* Outbound ranges, one memory and one IO,
  287. * later cannot be changed
  288. */
  289. ranges = <02000000 0 80000000 0000000e 80000000 0 80000000
  290. 01000000 0 00000000 0000000f 80010000 0 00010000>;
  291. /* Inbound 2GB range starting at 0 */
  292. dma-ranges = <42000000 0 0 0 0 0 80000000>;
  293. /* This drives busses 10 to 0x1f */
  294. bus-range = <20 2f>;
  295. /* Legacy interrupts (note the weird polarity, the bridge seems
  296. * to invert PCIe legacy interrupts).
  297. * We are de-swizzling here because the numbers are actually for
  298. * port of the root complex virtual P2P bridge. But I want
  299. * to avoid putting a node for it in the tree, so the numbers
  300. * below are basically de-swizzled numbers.
  301. * The real slot is on idsel 0, so the swizzling is 1:1
  302. */
  303. interrupt-map-mask = <0000 0 0 7>;
  304. interrupt-map = <
  305. 0000 0 0 1 &UIC3 4 4 /* swizzled int A */
  306. 0000 0 0 2 &UIC3 5 4 /* swizzled int B */
  307. 0000 0 0 3 &UIC3 6 4 /* swizzled int C */
  308. 0000 0 0 4 &UIC3 7 4 /* swizzled int D */>;
  309. };
  310. PCIE2: pciex@d40000000 {
  311. device_type = "pci";
  312. #interrupt-cells = <1>;
  313. #size-cells = <2>;
  314. #address-cells = <3>;
  315. compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex";
  316. primary;
  317. port = <2>; /* port number */
  318. reg = <d 40000000 20000000 /* Config space access */
  319. c 10002000 00001000>; /* Registers */
  320. dcr-reg = <140 020>;
  321. sdr-base = <370>;
  322. /* Outbound ranges, one memory and one IO,
  323. * later cannot be changed
  324. */
  325. ranges = <02000000 0 80000000 0000000f 00000000 0 80000000
  326. 01000000 0 00000000 0000000f 80020000 0 00010000>;
  327. /* Inbound 2GB range starting at 0 */
  328. dma-ranges = <42000000 0 0 0 0 0 80000000>;
  329. /* This drives busses 10 to 0x1f */
  330. bus-range = <30 3f>;
  331. /* Legacy interrupts (note the weird polarity, the bridge seems
  332. * to invert PCIe legacy interrupts).
  333. * We are de-swizzling here because the numbers are actually for
  334. * port of the root complex virtual P2P bridge. But I want
  335. * to avoid putting a node for it in the tree, so the numbers
  336. * below are basically de-swizzled numbers.
  337. * The real slot is on idsel 0, so the swizzling is 1:1
  338. */
  339. interrupt-map-mask = <0000 0 0 7>;
  340. interrupt-map = <
  341. 0000 0 0 1 &UIC3 8 4 /* swizzled int A */
  342. 0000 0 0 2 &UIC3 9 4 /* swizzled int B */
  343. 0000 0 0 3 &UIC3 a 4 /* swizzled int C */
  344. 0000 0 0 4 &UIC3 b 4 /* swizzled int D */>;
  345. };
  346. };
  347. chosen {
  348. linux,stdout-path = "/plb/opb/serial@10000200";
  349. };
  350. };