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iop3xx.h

iop3xx.h 7.2 KB
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  1. /*
    2. 

  2.  * include/asm-arm/hardware/iop3xx.h
    3. 

  3.  *
    4. 

  4.  * Intel IOP32X and IOP33X register definitions
    5. 

  5.  *
    6. 

  6.  * Author: Rory Bolt <rorybolt@pacbell.net>
    7. 

  7.  * Copyright (C) 2002 Rory Bolt
    8. 

  8.  * Copyright (C) 2004 Intel Corp.
    9. 

  9.  *
    10. 

  10.  * This program is free software; you can redistribute it and/or modify
    11. 

  11.  * it under the terms of the GNU General Public License version 2 as
    12. 

  12.  * published by the Free Software Foundation.
    13. 

  13.  */
    14. 

  14. 

  15. #ifndef __IOP3XX_H
    16. 

  16. #define __IOP3XX_H
    17. 

  17. 

  18. /*
    19. 

  19.  * IOP3XX GPIO handling
    20. 

  20.  */
    21. 

  21. #define GPIO_IN			0
    22. 

  22. #define GPIO_OUT		1
    23. 

  23. #define GPIO_LOW		0
    24. 

  24. #define GPIO_HIGH		1
    25. 

  25. #define IOP3XX_GPIO_LINE(x)	(x)
    26. 

  26. 

  27. #ifndef __ASSEMBLY__
    28. 

  28. extern void gpio_line_config(int line, int direction);
    29. 

  29. extern int  gpio_line_get(int line);
    30. 

  30. extern void gpio_line_set(int line, int value);
    31. 

  31. #endif
    32. 

  32. 

  33. 

  34. /*
    35. 

  35.  * IOP3XX processor registers
    36. 

  36.  */
    37. 

  37. #define IOP3XX_PERIPHERAL_PHYS_BASE	0xffffe000
    38. 

  38. #define IOP3XX_PERIPHERAL_VIRT_BASE	0xfeffe000
    39. 

  39. #define IOP3XX_PERIPHERAL_SIZE		0x00002000
    40. 

  40. #define IOP3XX_REG_ADDR(reg)		(IOP3XX_PERIPHERAL_VIRT_BASE + (reg))
    41. 

  41. 

  42. /* Address Translation Unit  */
    43. 

  43. #define IOP3XX_ATUVID		(volatile u16 *)IOP3XX_REG_ADDR(0x0100)
    44. 

  44. #define IOP3XX_ATUDID		(volatile u16 *)IOP3XX_REG_ADDR(0x0102)
    45. 

  45. #define IOP3XX_ATUCMD		(volatile u16 *)IOP3XX_REG_ADDR(0x0104)
    46. 

  46. #define IOP3XX_ATUSR		(volatile u16 *)IOP3XX_REG_ADDR(0x0106)
    47. 

  47. #define IOP3XX_ATURID		(volatile u8  *)IOP3XX_REG_ADDR(0x0108)
    48. 

  48. #define IOP3XX_ATUCCR		(volatile u32 *)IOP3XX_REG_ADDR(0x0109)
    49. 

  49. #define IOP3XX_ATUCLSR		(volatile u8  *)IOP3XX_REG_ADDR(0x010c)
    50. 

  50. #define IOP3XX_ATULT		(volatile u8  *)IOP3XX_REG_ADDR(0x010d)
    51. 

  51. #define IOP3XX_ATUHTR		(volatile u8  *)IOP3XX_REG_ADDR(0x010e)
    52. 

  52. #define IOP3XX_ATUBIST		(volatile u8  *)IOP3XX_REG_ADDR(0x010f)
    53. 

  53. #define IOP3XX_IABAR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0110)
    54. 

  54. #define IOP3XX_IAUBAR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0114)
    55. 

  55. #define IOP3XX_IABAR1		(volatile u32 *)IOP3XX_REG_ADDR(0x0118)
    56. 

  56. #define IOP3XX_IAUBAR1		(volatile u32 *)IOP3XX_REG_ADDR(0x011c)
    57. 

  57. #define IOP3XX_IABAR2		(volatile u32 *)IOP3XX_REG_ADDR(0x0120)
    58. 

  58. #define IOP3XX_IAUBAR2		(volatile u32 *)IOP3XX_REG_ADDR(0x0124)
    59. 

  59. #define IOP3XX_ASVIR		(volatile u16 *)IOP3XX_REG_ADDR(0x012c)
    60. 

  60. #define IOP3XX_ASIR		(volatile u16 *)IOP3XX_REG_ADDR(0x012e)
    61. 

  61. #define IOP3XX_ERBAR		(volatile u32 *)IOP3XX_REG_ADDR(0x0130)
    62. 

  62. #define IOP3XX_ATUILR		(volatile u8  *)IOP3XX_REG_ADDR(0x013c)
    63. 

  63. #define IOP3XX_ATUIPR		(volatile u8  *)IOP3XX_REG_ADDR(0x013d)
    64. 

  64. #define IOP3XX_ATUMGNT		(volatile u8  *)IOP3XX_REG_ADDR(0x013e)
    65. 

  65. #define IOP3XX_ATUMLAT		(volatile u8  *)IOP3XX_REG_ADDR(0x013f)
    66. 

  66. #define IOP3XX_IALR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0140)
    67. 

  67. #define IOP3XX_IATVR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0144)
    68. 

  68. #define IOP3XX_ERLR		(volatile u32 *)IOP3XX_REG_ADDR(0x0148)
    69. 

  69. #define IOP3XX_ERTVR		(volatile u32 *)IOP3XX_REG_ADDR(0x014c)
    70. 

  70. #define IOP3XX_IALR1		(volatile u32 *)IOP3XX_REG_ADDR(0x0150)
    71. 

  71. #define IOP3XX_IALR2		(volatile u32 *)IOP3XX_REG_ADDR(0x0154)
    72. 

  72. #define IOP3XX_IATVR2		(volatile u32 *)IOP3XX_REG_ADDR(0x0158)
    73. 

  73. #define IOP3XX_OIOWTVR		(volatile u32 *)IOP3XX_REG_ADDR(0x015c)
    74. 

  74. #define IOP3XX_OMWTVR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0160)
    75. 

  75. #define IOP3XX_OUMWTVR0		(volatile u32 *)IOP3XX_REG_ADDR(0x0164)
    76. 

  76. #define IOP3XX_OMWTVR1		(volatile u32 *)IOP3XX_REG_ADDR(0x0168)
    77. 

  77. #define IOP3XX_OUMWTVR1		(volatile u32 *)IOP3XX_REG_ADDR(0x016c)
    78. 

  78. #define IOP3XX_OUDWTVR		(volatile u32 *)IOP3XX_REG_ADDR(0x0178)
    79. 

  79. #define IOP3XX_ATUCR		(volatile u32 *)IOP3XX_REG_ADDR(0x0180)
    80. 

  80. #define IOP3XX_PCSR		(volatile u32 *)IOP3XX_REG_ADDR(0x0184)
    81. 

  81. #define IOP3XX_ATUISR		(volatile u32 *)IOP3XX_REG_ADDR(0x0188)
    82. 

  82. #define IOP3XX_ATUIMR		(volatile u32 *)IOP3XX_REG_ADDR(0x018c)
    83. 

  83. #define IOP3XX_IABAR3		(volatile u32 *)IOP3XX_REG_ADDR(0x0190)
    84. 

  84. #define IOP3XX_IAUBAR3		(volatile u32 *)IOP3XX_REG_ADDR(0x0194)
    85. 

  85. #define IOP3XX_IALR3		(volatile u32 *)IOP3XX_REG_ADDR(0x0198)
    86. 

  86. #define IOP3XX_IATVR3		(volatile u32 *)IOP3XX_REG_ADDR(0x019c)
    87. 

  87. #define IOP3XX_OCCAR		(volatile u32 *)IOP3XX_REG_ADDR(0x01a4)
    88. 

  88. #define IOP3XX_OCCDR		(volatile u32 *)IOP3XX_REG_ADDR(0x01ac)
    89. 

  89. #define IOP3XX_PDSCR		(volatile u32 *)IOP3XX_REG_ADDR(0x01bc)
    90. 

  90. #define IOP3XX_PMCAPID		(volatile u8  *)IOP3XX_REG_ADDR(0x01c0)
    91. 

  91. #define IOP3XX_PMNEXT		(volatile u8  *)IOP3XX_REG_ADDR(0x01c1)
    92. 

  92. #define IOP3XX_APMCR		(volatile u16 *)IOP3XX_REG_ADDR(0x01c2)
    93. 

  93. #define IOP3XX_APMCSR		(volatile u16 *)IOP3XX_REG_ADDR(0x01c4)
    94. 

  94. #define IOP3XX_PCIXCAPID	(volatile u8  *)IOP3XX_REG_ADDR(0x01e0)
    95. 

  95. #define IOP3XX_PCIXNEXT		(volatile u8  *)IOP3XX_REG_ADDR(0x01e1)
    96. 

  96. #define IOP3XX_PCIXCMD		(volatile u16 *)IOP3XX_REG_ADDR(0x01e2)
    97. 

  97. #define IOP3XX_PCIXSR		(volatile u32 *)IOP3XX_REG_ADDR(0x01e4)
    98. 

  98. #define IOP3XX_PCIIRSR		(volatile u32 *)IOP3XX_REG_ADDR(0x01ec)
    99. 

  99. 

  100. /* General Purpose I/O  */
    101. 

  101. #define IOP3XX_GPOE		(volatile u32 *)IOP3XX_GPIO_REG(0x0004)
    102. 

  102. #define IOP3XX_GPID		(volatile u32 *)IOP3XX_GPIO_REG(0x0008)
    103. 

  103. #define IOP3XX_GPOD		(volatile u32 *)IOP3XX_GPIO_REG(0x000c)
    104. 

  104. 

  105. /* Timers  */
    106. 

  106. #define IOP3XX_TU_TMR0		(volatile u32 *)IOP3XX_TIMER_REG(0x0000)
    107. 

  107. #define IOP3XX_TU_TMR1		(volatile u32 *)IOP3XX_TIMER_REG(0x0004)
    108. 

  108. #define IOP3XX_TU_TCR0		(volatile u32 *)IOP3XX_TIMER_REG(0x0008)
    109. 

  109. #define IOP3XX_TU_TCR1		(volatile u32 *)IOP3XX_TIMER_REG(0x000c)
    110. 

  110. #define IOP3XX_TU_TRR0		(volatile u32 *)IOP3XX_TIMER_REG(0x0010)
    111. 

  111. #define IOP3XX_TU_TRR1		(volatile u32 *)IOP3XX_TIMER_REG(0x0014)
    112. 

  112. #define IOP3XX_TU_TISR		(volatile u32 *)IOP3XX_TIMER_REG(0x0018)
    113. 

  113. #define IOP3XX_TU_WDTCR		(volatile u32 *)IOP3XX_TIMER_REG(0x001c)
    114. 

  114. #define IOP3XX_TMR_TC		0x01
    115. 

  115. #define IOP3XX_TMR_EN		0x02
    116. 

  116. #define IOP3XX_TMR_RELOAD	0x04
    117. 

  117. #define IOP3XX_TMR_PRIVILEGED	0x09
    118. 

  118. #define IOP3XX_TMR_RATIO_1_1	0x00
    119. 

  119. #define IOP3XX_TMR_RATIO_4_1	0x10
    120. 

  120. #define IOP3XX_TMR_RATIO_8_1	0x20
    121. 

  121. #define IOP3XX_TMR_RATIO_16_1	0x30
    122. 

  122. 

  123. /* I2C bus interface unit  */
    124. 

  124. #define IOP3XX_ICR0		(volatile u32 *)IOP3XX_REG_ADDR(0x1680)
    125. 

  125. #define IOP3XX_ISR0		(volatile u32 *)IOP3XX_REG_ADDR(0x1684)
    126. 

  126. #define IOP3XX_ISAR0		(volatile u32 *)IOP3XX_REG_ADDR(0x1688)
    127. 

  127. #define IOP3XX_IDBR0		(volatile u32 *)IOP3XX_REG_ADDR(0x168c)
    128. 

  128. #define IOP3XX_IBMR0		(volatile u32 *)IOP3XX_REG_ADDR(0x1694)
    129. 

  129. #define IOP3XX_ICR1		(volatile u32 *)IOP3XX_REG_ADDR(0x16a0)
    130. 

  130. #define IOP3XX_ISR1		(volatile u32 *)IOP3XX_REG_ADDR(0x16a4)
    131. 

  131. #define IOP3XX_ISAR1		(volatile u32 *)IOP3XX_REG_ADDR(0x16a8)
    132. 

  132. #define IOP3XX_IDBR1		(volatile u32 *)IOP3XX_REG_ADDR(0x16ac)
    133. 

  133. #define IOP3XX_IBMR1		(volatile u32 *)IOP3XX_REG_ADDR(0x16b4)
    134. 

  134. 

  135. 

  136. /*
    137. 

  137.  * IOP3XX I/O and Mem space regions for PCI autoconfiguration
    138. 

  138.  */
    139. 

  139. #define IOP3XX_PCI_MEM_WINDOW_SIZE	0x04000000
    140. 

  140. #define IOP3XX_PCI_LOWER_MEM_PA		0x80000000
    141. 

  141. #define IOP3XX_PCI_LOWER_MEM_BA		(*IOP3XX_OMWTVR0)
    142. 

  142. 

  143. #define IOP3XX_PCI_IO_WINDOW_SIZE	0x00010000
    144. 

  144. #define IOP3XX_PCI_LOWER_IO_PA		0x90000000
    145. 

  145. #define IOP3XX_PCI_LOWER_IO_VA		0xfe000000
    146. 

  146. #define IOP3XX_PCI_LOWER_IO_BA		(*IOP3XX_OIOWTVR)
    147. 

  147. 

  148. 

  149. #ifndef __ASSEMBLY__
    150. 

  150. void iop3xx_map_io(void);
    151. 

  151. void iop3xx_init_time(unsigned long);
    152. 

  152. unsigned long iop3xx_gettimeoffset(void);
    153. 

  153. 

  154. extern struct platform_device iop3xx_i2c0_device;
    155. 

  155. extern struct platform_device iop3xx_i2c1_device;
    156. 

  156. 

  157. extern inline void iop3xx_cp6_enable(void)
    158. 

  158. {
    159. 

  159. 	u32 temp;
    160. 

  160. 

  161. 	asm volatile (
    162. 

  162. 		"mrc	p15, 0, %0, c15, c1, 0\n\t"
    163. 

  163. 		"orr	%0, %0, #(1 << 6)\n\t"
    164. 

  164. 		"mcr	p15, 0, %0, c15, c1, 0\n\t"
    165. 

  165. 		"mrc	p15, 0, %0, c15, c1, 0\n\t"
    166. 

  166. 		"mov	%0, %0\n\t"
    167. 

  167. 		"sub	pc, pc, #4\n\t"
    168. 

  168. 		: "=r" (temp) );
    169. 

  169. }
    170. 

  170. 

  171. extern inline void iop3xx_cp6_disable(void)
    172. 

  172. {
    173. 

  173. 	u32 temp;
    174. 

  174. 

  175. 	asm volatile (
    176. 

  176. 		"mrc	p15, 0, %0, c15, c1, 0\n\t"
    177. 

  177. 		"bic	%0, %0, #(1 << 6)\n\t"
    178. 

  178. 		"mcr	p15, 0, %0, c15, c1, 0\n\t"
    179. 

  179. 		"mrc	p15, 0, %0, c15, c1, 0\n\t"
    180. 

  180. 		"mov	%0, %0\n\t"
    181. 

  181. 		"sub	pc, pc, #4\n\t"
    182. 

  182. 		: "=r" (temp) );
    183. 

  183. }
    184. 

  184. #endif
    185. 

  185. 

  186. 

  187. #endif
    188.