twl4030.c 56 KB

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  1. /*
  2. * ALSA SoC TWL4030 codec driver
  3. *
  4. * Author: Steve Sakoman, <steve@sakoman.com>
  5. *
  6. * This program is free software; you can redistribute it and/or
  7. * modify it under the terms of the GNU General Public License
  8. * version 2 as published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful, but
  11. * WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  13. * General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
  18. * 02110-1301 USA
  19. *
  20. */
  21. #include <linux/module.h>
  22. #include <linux/moduleparam.h>
  23. #include <linux/init.h>
  24. #include <linux/delay.h>
  25. #include <linux/pm.h>
  26. #include <linux/i2c.h>
  27. #include <linux/platform_device.h>
  28. #include <linux/i2c/twl4030.h>
  29. #include <sound/core.h>
  30. #include <sound/pcm.h>
  31. #include <sound/pcm_params.h>
  32. #include <sound/soc.h>
  33. #include <sound/soc-dapm.h>
  34. #include <sound/initval.h>
  35. #include <sound/tlv.h>
  36. #include "twl4030.h"
  37. /*
  38. * twl4030 register cache & default register settings
  39. */
  40. static const u8 twl4030_reg[TWL4030_CACHEREGNUM] = {
  41. 0x00, /* this register not used */
  42. 0x91, /* REG_CODEC_MODE (0x1) */
  43. 0xc3, /* REG_OPTION (0x2) */
  44. 0x00, /* REG_UNKNOWN (0x3) */
  45. 0x00, /* REG_MICBIAS_CTL (0x4) */
  46. 0x20, /* REG_ANAMICL (0x5) */
  47. 0x00, /* REG_ANAMICR (0x6) */
  48. 0x00, /* REG_AVADC_CTL (0x7) */
  49. 0x00, /* REG_ADCMICSEL (0x8) */
  50. 0x00, /* REG_DIGMIXING (0x9) */
  51. 0x0c, /* REG_ATXL1PGA (0xA) */
  52. 0x0c, /* REG_ATXR1PGA (0xB) */
  53. 0x00, /* REG_AVTXL2PGA (0xC) */
  54. 0x00, /* REG_AVTXR2PGA (0xD) */
  55. 0x01, /* REG_AUDIO_IF (0xE) */
  56. 0x00, /* REG_VOICE_IF (0xF) */
  57. 0x00, /* REG_ARXR1PGA (0x10) */
  58. 0x00, /* REG_ARXL1PGA (0x11) */
  59. 0x6c, /* REG_ARXR2PGA (0x12) */
  60. 0x6c, /* REG_ARXL2PGA (0x13) */
  61. 0x00, /* REG_VRXPGA (0x14) */
  62. 0x00, /* REG_VSTPGA (0x15) */
  63. 0x00, /* REG_VRX2ARXPGA (0x16) */
  64. 0x0c, /* REG_AVDAC_CTL (0x17) */
  65. 0x00, /* REG_ARX2VTXPGA (0x18) */
  66. 0x00, /* REG_ARXL1_APGA_CTL (0x19) */
  67. 0x00, /* REG_ARXR1_APGA_CTL (0x1A) */
  68. 0x4b, /* REG_ARXL2_APGA_CTL (0x1B) */
  69. 0x4b, /* REG_ARXR2_APGA_CTL (0x1C) */
  70. 0x00, /* REG_ATX2ARXPGA (0x1D) */
  71. 0x00, /* REG_BT_IF (0x1E) */
  72. 0x00, /* REG_BTPGA (0x1F) */
  73. 0x00, /* REG_BTSTPGA (0x20) */
  74. 0x00, /* REG_EAR_CTL (0x21) */
  75. 0x24, /* REG_HS_SEL (0x22) */
  76. 0x0a, /* REG_HS_GAIN_SET (0x23) */
  77. 0x00, /* REG_HS_POPN_SET (0x24) */
  78. 0x00, /* REG_PREDL_CTL (0x25) */
  79. 0x00, /* REG_PREDR_CTL (0x26) */
  80. 0x00, /* REG_PRECKL_CTL (0x27) */
  81. 0x00, /* REG_PRECKR_CTL (0x28) */
  82. 0x00, /* REG_HFL_CTL (0x29) */
  83. 0x00, /* REG_HFR_CTL (0x2A) */
  84. 0x00, /* REG_ALC_CTL (0x2B) */
  85. 0x00, /* REG_ALC_SET1 (0x2C) */
  86. 0x00, /* REG_ALC_SET2 (0x2D) */
  87. 0x00, /* REG_BOOST_CTL (0x2E) */
  88. 0x00, /* REG_SOFTVOL_CTL (0x2F) */
  89. 0x00, /* REG_DTMF_FREQSEL (0x30) */
  90. 0x00, /* REG_DTMF_TONEXT1H (0x31) */
  91. 0x00, /* REG_DTMF_TONEXT1L (0x32) */
  92. 0x00, /* REG_DTMF_TONEXT2H (0x33) */
  93. 0x00, /* REG_DTMF_TONEXT2L (0x34) */
  94. 0x00, /* REG_DTMF_TONOFF (0x35) */
  95. 0x00, /* REG_DTMF_WANONOFF (0x36) */
  96. 0x00, /* REG_I2S_RX_SCRAMBLE_H (0x37) */
  97. 0x00, /* REG_I2S_RX_SCRAMBLE_M (0x38) */
  98. 0x00, /* REG_I2S_RX_SCRAMBLE_L (0x39) */
  99. 0x16, /* REG_APLL_CTL (0x3A) */
  100. 0x00, /* REG_DTMF_CTL (0x3B) */
  101. 0x00, /* REG_DTMF_PGA_CTL2 (0x3C) */
  102. 0x00, /* REG_DTMF_PGA_CTL1 (0x3D) */
  103. 0x00, /* REG_MISC_SET_1 (0x3E) */
  104. 0x00, /* REG_PCMBTMUX (0x3F) */
  105. 0x00, /* not used (0x40) */
  106. 0x00, /* not used (0x41) */
  107. 0x00, /* not used (0x42) */
  108. 0x00, /* REG_RX_PATH_SEL (0x43) */
  109. 0x00, /* REG_VDL_APGA_CTL (0x44) */
  110. 0x00, /* REG_VIBRA_CTL (0x45) */
  111. 0x00, /* REG_VIBRA_SET (0x46) */
  112. 0x00, /* REG_VIBRA_PWM_SET (0x47) */
  113. 0x00, /* REG_ANAMIC_GAIN (0x48) */
  114. 0x00, /* REG_MISC_SET_2 (0x49) */
  115. };
  116. /* codec private data */
  117. struct twl4030_priv {
  118. unsigned int bypass_state;
  119. unsigned int codec_powered;
  120. unsigned int codec_muted;
  121. struct snd_pcm_substream *master_substream;
  122. struct snd_pcm_substream *slave_substream;
  123. unsigned int configured;
  124. unsigned int rate;
  125. unsigned int sample_bits;
  126. unsigned int channels;
  127. };
  128. /*
  129. * read twl4030 register cache
  130. */
  131. static inline unsigned int twl4030_read_reg_cache(struct snd_soc_codec *codec,
  132. unsigned int reg)
  133. {
  134. u8 *cache = codec->reg_cache;
  135. if (reg >= TWL4030_CACHEREGNUM)
  136. return -EIO;
  137. return cache[reg];
  138. }
  139. /*
  140. * write twl4030 register cache
  141. */
  142. static inline void twl4030_write_reg_cache(struct snd_soc_codec *codec,
  143. u8 reg, u8 value)
  144. {
  145. u8 *cache = codec->reg_cache;
  146. if (reg >= TWL4030_CACHEREGNUM)
  147. return;
  148. cache[reg] = value;
  149. }
  150. /*
  151. * write to the twl4030 register space
  152. */
  153. static int twl4030_write(struct snd_soc_codec *codec,
  154. unsigned int reg, unsigned int value)
  155. {
  156. twl4030_write_reg_cache(codec, reg, value);
  157. return twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE, value, reg);
  158. }
  159. static void twl4030_codec_enable(struct snd_soc_codec *codec, int enable)
  160. {
  161. struct twl4030_priv *twl4030 = codec->private_data;
  162. u8 mode;
  163. if (enable == twl4030->codec_powered)
  164. return;
  165. mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE);
  166. if (enable)
  167. mode |= TWL4030_CODECPDZ;
  168. else
  169. mode &= ~TWL4030_CODECPDZ;
  170. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  171. twl4030->codec_powered = enable;
  172. /* REVISIT: this delay is present in TI sample drivers */
  173. /* but there seems to be no TRM requirement for it */
  174. udelay(10);
  175. }
  176. static void twl4030_init_chip(struct snd_soc_codec *codec)
  177. {
  178. int i;
  179. /* clear CODECPDZ prior to setting register defaults */
  180. twl4030_codec_enable(codec, 0);
  181. /* set all audio section registers to reasonable defaults */
  182. for (i = TWL4030_REG_OPTION; i <= TWL4030_REG_MISC_SET_2; i++)
  183. twl4030_write(codec, i, twl4030_reg[i]);
  184. }
  185. static void twl4030_codec_mute(struct snd_soc_codec *codec, int mute)
  186. {
  187. struct twl4030_priv *twl4030 = codec->private_data;
  188. u8 reg_val;
  189. if (mute == twl4030->codec_muted)
  190. return;
  191. if (mute) {
  192. /* Bypass the reg_cache and mute the volumes
  193. * Headset mute is done in it's own event handler
  194. * Things to mute: Earpiece, PreDrivL/R, CarkitL/R
  195. */
  196. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_EAR_CTL);
  197. twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  198. reg_val & (~TWL4030_EAR_GAIN),
  199. TWL4030_REG_EAR_CTL);
  200. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PREDL_CTL);
  201. twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  202. reg_val & (~TWL4030_PREDL_GAIN),
  203. TWL4030_REG_PREDL_CTL);
  204. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PREDR_CTL);
  205. twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  206. reg_val & (~TWL4030_PREDR_GAIN),
  207. TWL4030_REG_PREDL_CTL);
  208. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PRECKL_CTL);
  209. twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  210. reg_val & (~TWL4030_PRECKL_GAIN),
  211. TWL4030_REG_PRECKL_CTL);
  212. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_PRECKR_CTL);
  213. twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  214. reg_val & (~TWL4030_PRECKL_GAIN),
  215. TWL4030_REG_PRECKR_CTL);
  216. /* Disable PLL */
  217. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL);
  218. reg_val &= ~TWL4030_APLL_EN;
  219. twl4030_write(codec, TWL4030_REG_APLL_CTL, reg_val);
  220. } else {
  221. /* Restore the volumes
  222. * Headset mute is done in it's own event handler
  223. * Things to restore: Earpiece, PreDrivL/R, CarkitL/R
  224. */
  225. twl4030_write(codec, TWL4030_REG_EAR_CTL,
  226. twl4030_read_reg_cache(codec, TWL4030_REG_EAR_CTL));
  227. twl4030_write(codec, TWL4030_REG_PREDL_CTL,
  228. twl4030_read_reg_cache(codec, TWL4030_REG_PREDL_CTL));
  229. twl4030_write(codec, TWL4030_REG_PREDR_CTL,
  230. twl4030_read_reg_cache(codec, TWL4030_REG_PREDR_CTL));
  231. twl4030_write(codec, TWL4030_REG_PRECKL_CTL,
  232. twl4030_read_reg_cache(codec, TWL4030_REG_PRECKL_CTL));
  233. twl4030_write(codec, TWL4030_REG_PRECKR_CTL,
  234. twl4030_read_reg_cache(codec, TWL4030_REG_PRECKR_CTL));
  235. /* Enable PLL */
  236. reg_val = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL);
  237. reg_val |= TWL4030_APLL_EN;
  238. twl4030_write(codec, TWL4030_REG_APLL_CTL, reg_val);
  239. }
  240. twl4030->codec_muted = mute;
  241. }
  242. static void twl4030_power_up(struct snd_soc_codec *codec)
  243. {
  244. struct twl4030_priv *twl4030 = codec->private_data;
  245. u8 anamicl, regmisc1, byte;
  246. int i = 0;
  247. if (twl4030->codec_powered)
  248. return;
  249. /* set CODECPDZ to turn on codec */
  250. twl4030_codec_enable(codec, 1);
  251. /* initiate offset cancellation */
  252. anamicl = twl4030_read_reg_cache(codec, TWL4030_REG_ANAMICL);
  253. twl4030_write(codec, TWL4030_REG_ANAMICL,
  254. anamicl | TWL4030_CNCL_OFFSET_START);
  255. /* wait for offset cancellation to complete */
  256. do {
  257. /* this takes a little while, so don't slam i2c */
  258. udelay(2000);
  259. twl4030_i2c_read_u8(TWL4030_MODULE_AUDIO_VOICE, &byte,
  260. TWL4030_REG_ANAMICL);
  261. } while ((i++ < 100) &&
  262. ((byte & TWL4030_CNCL_OFFSET_START) ==
  263. TWL4030_CNCL_OFFSET_START));
  264. /* Make sure that the reg_cache has the same value as the HW */
  265. twl4030_write_reg_cache(codec, TWL4030_REG_ANAMICL, byte);
  266. /* anti-pop when changing analog gain */
  267. regmisc1 = twl4030_read_reg_cache(codec, TWL4030_REG_MISC_SET_1);
  268. twl4030_write(codec, TWL4030_REG_MISC_SET_1,
  269. regmisc1 | TWL4030_SMOOTH_ANAVOL_EN);
  270. /* toggle CODECPDZ as per TRM */
  271. twl4030_codec_enable(codec, 0);
  272. twl4030_codec_enable(codec, 1);
  273. }
  274. /*
  275. * Unconditional power down
  276. */
  277. static void twl4030_power_down(struct snd_soc_codec *codec)
  278. {
  279. /* power down */
  280. twl4030_codec_enable(codec, 0);
  281. }
  282. /* Earpiece */
  283. static const struct snd_kcontrol_new twl4030_dapm_earpiece_controls[] = {
  284. SOC_DAPM_SINGLE("Voice", TWL4030_REG_EAR_CTL, 0, 1, 0),
  285. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_EAR_CTL, 1, 1, 0),
  286. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_EAR_CTL, 2, 1, 0),
  287. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_EAR_CTL, 3, 1, 0),
  288. };
  289. /* PreDrive Left */
  290. static const struct snd_kcontrol_new twl4030_dapm_predrivel_controls[] = {
  291. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDL_CTL, 0, 1, 0),
  292. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PREDL_CTL, 1, 1, 0),
  293. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDL_CTL, 2, 1, 0),
  294. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDL_CTL, 3, 1, 0),
  295. };
  296. /* PreDrive Right */
  297. static const struct snd_kcontrol_new twl4030_dapm_predriver_controls[] = {
  298. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PREDR_CTL, 0, 1, 0),
  299. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PREDR_CTL, 1, 1, 0),
  300. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PREDR_CTL, 2, 1, 0),
  301. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PREDR_CTL, 3, 1, 0),
  302. };
  303. /* Headset Left */
  304. static const struct snd_kcontrol_new twl4030_dapm_hsol_controls[] = {
  305. SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 0, 1, 0),
  306. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_HS_SEL, 1, 1, 0),
  307. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_HS_SEL, 2, 1, 0),
  308. };
  309. /* Headset Right */
  310. static const struct snd_kcontrol_new twl4030_dapm_hsor_controls[] = {
  311. SOC_DAPM_SINGLE("Voice", TWL4030_REG_HS_SEL, 3, 1, 0),
  312. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_HS_SEL, 4, 1, 0),
  313. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_HS_SEL, 5, 1, 0),
  314. };
  315. /* Carkit Left */
  316. static const struct snd_kcontrol_new twl4030_dapm_carkitl_controls[] = {
  317. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKL_CTL, 0, 1, 0),
  318. SOC_DAPM_SINGLE("AudioL1", TWL4030_REG_PRECKL_CTL, 1, 1, 0),
  319. SOC_DAPM_SINGLE("AudioL2", TWL4030_REG_PRECKL_CTL, 2, 1, 0),
  320. };
  321. /* Carkit Right */
  322. static const struct snd_kcontrol_new twl4030_dapm_carkitr_controls[] = {
  323. SOC_DAPM_SINGLE("Voice", TWL4030_REG_PRECKR_CTL, 0, 1, 0),
  324. SOC_DAPM_SINGLE("AudioR1", TWL4030_REG_PRECKR_CTL, 1, 1, 0),
  325. SOC_DAPM_SINGLE("AudioR2", TWL4030_REG_PRECKR_CTL, 2, 1, 0),
  326. };
  327. /* Handsfree Left */
  328. static const char *twl4030_handsfreel_texts[] =
  329. {"Voice", "AudioL1", "AudioL2", "AudioR2"};
  330. static const struct soc_enum twl4030_handsfreel_enum =
  331. SOC_ENUM_SINGLE(TWL4030_REG_HFL_CTL, 0,
  332. ARRAY_SIZE(twl4030_handsfreel_texts),
  333. twl4030_handsfreel_texts);
  334. static const struct snd_kcontrol_new twl4030_dapm_handsfreel_control =
  335. SOC_DAPM_ENUM("Route", twl4030_handsfreel_enum);
  336. /* Handsfree Right */
  337. static const char *twl4030_handsfreer_texts[] =
  338. {"Voice", "AudioR1", "AudioR2", "AudioL2"};
  339. static const struct soc_enum twl4030_handsfreer_enum =
  340. SOC_ENUM_SINGLE(TWL4030_REG_HFR_CTL, 0,
  341. ARRAY_SIZE(twl4030_handsfreer_texts),
  342. twl4030_handsfreer_texts);
  343. static const struct snd_kcontrol_new twl4030_dapm_handsfreer_control =
  344. SOC_DAPM_ENUM("Route", twl4030_handsfreer_enum);
  345. /* Left analog microphone selection */
  346. static const char *twl4030_analoglmic_texts[] =
  347. {"Off", "Main mic", "Headset mic", "AUXL", "Carkit mic"};
  348. static const unsigned int twl4030_analoglmic_values[] =
  349. {0x0, 0x1, 0x2, 0x4, 0x8};
  350. static const struct soc_enum twl4030_analoglmic_enum =
  351. SOC_VALUE_ENUM_SINGLE(TWL4030_REG_ANAMICL, 0, 0xf,
  352. ARRAY_SIZE(twl4030_analoglmic_texts),
  353. twl4030_analoglmic_texts,
  354. twl4030_analoglmic_values);
  355. static const struct snd_kcontrol_new twl4030_dapm_analoglmic_control =
  356. SOC_DAPM_VALUE_ENUM("Route", twl4030_analoglmic_enum);
  357. /* Right analog microphone selection */
  358. static const char *twl4030_analogrmic_texts[] =
  359. {"Off", "Sub mic", "AUXR"};
  360. static const unsigned int twl4030_analogrmic_values[] =
  361. {0x0, 0x1, 0x4};
  362. static const struct soc_enum twl4030_analogrmic_enum =
  363. SOC_VALUE_ENUM_SINGLE(TWL4030_REG_ANAMICR, 0, 0x5,
  364. ARRAY_SIZE(twl4030_analogrmic_texts),
  365. twl4030_analogrmic_texts,
  366. twl4030_analogrmic_values);
  367. static const struct snd_kcontrol_new twl4030_dapm_analogrmic_control =
  368. SOC_DAPM_VALUE_ENUM("Route", twl4030_analogrmic_enum);
  369. /* TX1 L/R Analog/Digital microphone selection */
  370. static const char *twl4030_micpathtx1_texts[] =
  371. {"Analog", "Digimic0"};
  372. static const struct soc_enum twl4030_micpathtx1_enum =
  373. SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 0,
  374. ARRAY_SIZE(twl4030_micpathtx1_texts),
  375. twl4030_micpathtx1_texts);
  376. static const struct snd_kcontrol_new twl4030_dapm_micpathtx1_control =
  377. SOC_DAPM_ENUM("Route", twl4030_micpathtx1_enum);
  378. /* TX2 L/R Analog/Digital microphone selection */
  379. static const char *twl4030_micpathtx2_texts[] =
  380. {"Analog", "Digimic1"};
  381. static const struct soc_enum twl4030_micpathtx2_enum =
  382. SOC_ENUM_SINGLE(TWL4030_REG_ADCMICSEL, 2,
  383. ARRAY_SIZE(twl4030_micpathtx2_texts),
  384. twl4030_micpathtx2_texts);
  385. static const struct snd_kcontrol_new twl4030_dapm_micpathtx2_control =
  386. SOC_DAPM_ENUM("Route", twl4030_micpathtx2_enum);
  387. /* Analog bypass for AudioR1 */
  388. static const struct snd_kcontrol_new twl4030_dapm_abypassr1_control =
  389. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR1_APGA_CTL, 2, 1, 0);
  390. /* Analog bypass for AudioL1 */
  391. static const struct snd_kcontrol_new twl4030_dapm_abypassl1_control =
  392. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL1_APGA_CTL, 2, 1, 0);
  393. /* Analog bypass for AudioR2 */
  394. static const struct snd_kcontrol_new twl4030_dapm_abypassr2_control =
  395. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXR2_APGA_CTL, 2, 1, 0);
  396. /* Analog bypass for AudioL2 */
  397. static const struct snd_kcontrol_new twl4030_dapm_abypassl2_control =
  398. SOC_DAPM_SINGLE("Switch", TWL4030_REG_ARXL2_APGA_CTL, 2, 1, 0);
  399. /* Digital bypass gain, 0 mutes the bypass */
  400. static const unsigned int twl4030_dapm_dbypass_tlv[] = {
  401. TLV_DB_RANGE_HEAD(2),
  402. 0, 3, TLV_DB_SCALE_ITEM(-2400, 0, 1),
  403. 4, 7, TLV_DB_SCALE_ITEM(-1800, 600, 0),
  404. };
  405. /* Digital bypass left (TX1L -> RX2L) */
  406. static const struct snd_kcontrol_new twl4030_dapm_dbypassl_control =
  407. SOC_DAPM_SINGLE_TLV("Volume",
  408. TWL4030_REG_ATX2ARXPGA, 3, 7, 0,
  409. twl4030_dapm_dbypass_tlv);
  410. /* Digital bypass right (TX1R -> RX2R) */
  411. static const struct snd_kcontrol_new twl4030_dapm_dbypassr_control =
  412. SOC_DAPM_SINGLE_TLV("Volume",
  413. TWL4030_REG_ATX2ARXPGA, 0, 7, 0,
  414. twl4030_dapm_dbypass_tlv);
  415. static int micpath_event(struct snd_soc_dapm_widget *w,
  416. struct snd_kcontrol *kcontrol, int event)
  417. {
  418. struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
  419. unsigned char adcmicsel, micbias_ctl;
  420. adcmicsel = twl4030_read_reg_cache(w->codec, TWL4030_REG_ADCMICSEL);
  421. micbias_ctl = twl4030_read_reg_cache(w->codec, TWL4030_REG_MICBIAS_CTL);
  422. /* Prepare the bits for the given TX path:
  423. * shift_l == 0: TX1 microphone path
  424. * shift_l == 2: TX2 microphone path */
  425. if (e->shift_l) {
  426. /* TX2 microphone path */
  427. if (adcmicsel & TWL4030_TX2IN_SEL)
  428. micbias_ctl |= TWL4030_MICBIAS2_CTL; /* digimic */
  429. else
  430. micbias_ctl &= ~TWL4030_MICBIAS2_CTL;
  431. } else {
  432. /* TX1 microphone path */
  433. if (adcmicsel & TWL4030_TX1IN_SEL)
  434. micbias_ctl |= TWL4030_MICBIAS1_CTL; /* digimic */
  435. else
  436. micbias_ctl &= ~TWL4030_MICBIAS1_CTL;
  437. }
  438. twl4030_write(w->codec, TWL4030_REG_MICBIAS_CTL, micbias_ctl);
  439. return 0;
  440. }
  441. static int handsfree_event(struct snd_soc_dapm_widget *w,
  442. struct snd_kcontrol *kcontrol, int event)
  443. {
  444. struct soc_enum *e = (struct soc_enum *)w->kcontrols->private_value;
  445. unsigned char hs_ctl;
  446. hs_ctl = twl4030_read_reg_cache(w->codec, e->reg);
  447. if (hs_ctl & TWL4030_HF_CTL_REF_EN) {
  448. hs_ctl |= TWL4030_HF_CTL_RAMP_EN;
  449. twl4030_write(w->codec, e->reg, hs_ctl);
  450. hs_ctl |= TWL4030_HF_CTL_LOOP_EN;
  451. twl4030_write(w->codec, e->reg, hs_ctl);
  452. hs_ctl |= TWL4030_HF_CTL_HB_EN;
  453. twl4030_write(w->codec, e->reg, hs_ctl);
  454. } else {
  455. hs_ctl &= ~(TWL4030_HF_CTL_RAMP_EN | TWL4030_HF_CTL_LOOP_EN
  456. | TWL4030_HF_CTL_HB_EN);
  457. twl4030_write(w->codec, e->reg, hs_ctl);
  458. }
  459. return 0;
  460. }
  461. static int headsetl_event(struct snd_soc_dapm_widget *w,
  462. struct snd_kcontrol *kcontrol, int event)
  463. {
  464. unsigned char hs_gain, hs_pop;
  465. /* Save the current volume */
  466. hs_gain = twl4030_read_reg_cache(w->codec, TWL4030_REG_HS_GAIN_SET);
  467. hs_pop = twl4030_read_reg_cache(w->codec, TWL4030_REG_HS_POPN_SET);
  468. switch (event) {
  469. case SND_SOC_DAPM_POST_PMU:
  470. /* Do the anti-pop/bias ramp enable according to the TRM */
  471. hs_pop |= TWL4030_VMID_EN;
  472. twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  473. /* Is this needed? Can we just use whatever gain here? */
  474. twl4030_write(w->codec, TWL4030_REG_HS_GAIN_SET,
  475. (hs_gain & (~0x0f)) | 0x0a);
  476. hs_pop |= TWL4030_RAMP_EN;
  477. twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  478. /* Restore the original volume */
  479. twl4030_write(w->codec, TWL4030_REG_HS_GAIN_SET, hs_gain);
  480. break;
  481. case SND_SOC_DAPM_POST_PMD:
  482. /* Do the anti-pop/bias ramp disable according to the TRM */
  483. hs_pop &= ~TWL4030_RAMP_EN;
  484. twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  485. /* Bypass the reg_cache to mute the headset */
  486. twl4030_i2c_write_u8(TWL4030_MODULE_AUDIO_VOICE,
  487. hs_gain & (~0x0f),
  488. TWL4030_REG_HS_GAIN_SET);
  489. hs_pop &= ~TWL4030_VMID_EN;
  490. twl4030_write(w->codec, TWL4030_REG_HS_POPN_SET, hs_pop);
  491. break;
  492. }
  493. return 0;
  494. }
  495. static int bypass_event(struct snd_soc_dapm_widget *w,
  496. struct snd_kcontrol *kcontrol, int event)
  497. {
  498. struct soc_mixer_control *m =
  499. (struct soc_mixer_control *)w->kcontrols->private_value;
  500. struct twl4030_priv *twl4030 = w->codec->private_data;
  501. unsigned char reg;
  502. reg = twl4030_read_reg_cache(w->codec, m->reg);
  503. if (m->reg <= TWL4030_REG_ARXR2_APGA_CTL) {
  504. /* Analog bypass */
  505. if (reg & (1 << m->shift))
  506. twl4030->bypass_state |=
  507. (1 << (m->reg - TWL4030_REG_ARXL1_APGA_CTL));
  508. else
  509. twl4030->bypass_state &=
  510. ~(1 << (m->reg - TWL4030_REG_ARXL1_APGA_CTL));
  511. } else {
  512. /* Digital bypass */
  513. if (reg & (0x7 << m->shift))
  514. twl4030->bypass_state |= (1 << (m->shift ? 5 : 4));
  515. else
  516. twl4030->bypass_state &= ~(1 << (m->shift ? 5 : 4));
  517. }
  518. if (w->codec->bias_level == SND_SOC_BIAS_STANDBY) {
  519. if (twl4030->bypass_state)
  520. twl4030_codec_mute(w->codec, 0);
  521. else
  522. twl4030_codec_mute(w->codec, 1);
  523. }
  524. return 0;
  525. }
  526. /*
  527. * Some of the gain controls in TWL (mostly those which are associated with
  528. * the outputs) are implemented in an interesting way:
  529. * 0x0 : Power down (mute)
  530. * 0x1 : 6dB
  531. * 0x2 : 0 dB
  532. * 0x3 : -6 dB
  533. * Inverting not going to help with these.
  534. * Custom volsw and volsw_2r get/put functions to handle these gain bits.
  535. */
  536. #define SOC_DOUBLE_TLV_TWL4030(xname, xreg, shift_left, shift_right, xmax,\
  537. xinvert, tlv_array) \
  538. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
  539. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  540. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  541. .tlv.p = (tlv_array), \
  542. .info = snd_soc_info_volsw, \
  543. .get = snd_soc_get_volsw_twl4030, \
  544. .put = snd_soc_put_volsw_twl4030, \
  545. .private_value = (unsigned long)&(struct soc_mixer_control) \
  546. {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
  547. .max = xmax, .invert = xinvert} }
  548. #define SOC_DOUBLE_R_TLV_TWL4030(xname, reg_left, reg_right, xshift, xmax,\
  549. xinvert, tlv_array) \
  550. { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
  551. .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  552. SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  553. .tlv.p = (tlv_array), \
  554. .info = snd_soc_info_volsw_2r, \
  555. .get = snd_soc_get_volsw_r2_twl4030,\
  556. .put = snd_soc_put_volsw_r2_twl4030, \
  557. .private_value = (unsigned long)&(struct soc_mixer_control) \
  558. {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
  559. .rshift = xshift, .max = xmax, .invert = xinvert} }
  560. #define SOC_SINGLE_TLV_TWL4030(xname, xreg, xshift, xmax, xinvert, tlv_array) \
  561. SOC_DOUBLE_TLV_TWL4030(xname, xreg, xshift, xshift, xmax, \
  562. xinvert, tlv_array)
  563. static int snd_soc_get_volsw_twl4030(struct snd_kcontrol *kcontrol,
  564. struct snd_ctl_elem_value *ucontrol)
  565. {
  566. struct soc_mixer_control *mc =
  567. (struct soc_mixer_control *)kcontrol->private_value;
  568. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  569. unsigned int reg = mc->reg;
  570. unsigned int shift = mc->shift;
  571. unsigned int rshift = mc->rshift;
  572. int max = mc->max;
  573. int mask = (1 << fls(max)) - 1;
  574. ucontrol->value.integer.value[0] =
  575. (snd_soc_read(codec, reg) >> shift) & mask;
  576. if (ucontrol->value.integer.value[0])
  577. ucontrol->value.integer.value[0] =
  578. max + 1 - ucontrol->value.integer.value[0];
  579. if (shift != rshift) {
  580. ucontrol->value.integer.value[1] =
  581. (snd_soc_read(codec, reg) >> rshift) & mask;
  582. if (ucontrol->value.integer.value[1])
  583. ucontrol->value.integer.value[1] =
  584. max + 1 - ucontrol->value.integer.value[1];
  585. }
  586. return 0;
  587. }
  588. static int snd_soc_put_volsw_twl4030(struct snd_kcontrol *kcontrol,
  589. struct snd_ctl_elem_value *ucontrol)
  590. {
  591. struct soc_mixer_control *mc =
  592. (struct soc_mixer_control *)kcontrol->private_value;
  593. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  594. unsigned int reg = mc->reg;
  595. unsigned int shift = mc->shift;
  596. unsigned int rshift = mc->rshift;
  597. int max = mc->max;
  598. int mask = (1 << fls(max)) - 1;
  599. unsigned short val, val2, val_mask;
  600. val = (ucontrol->value.integer.value[0] & mask);
  601. val_mask = mask << shift;
  602. if (val)
  603. val = max + 1 - val;
  604. val = val << shift;
  605. if (shift != rshift) {
  606. val2 = (ucontrol->value.integer.value[1] & mask);
  607. val_mask |= mask << rshift;
  608. if (val2)
  609. val2 = max + 1 - val2;
  610. val |= val2 << rshift;
  611. }
  612. return snd_soc_update_bits(codec, reg, val_mask, val);
  613. }
  614. static int snd_soc_get_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
  615. struct snd_ctl_elem_value *ucontrol)
  616. {
  617. struct soc_mixer_control *mc =
  618. (struct soc_mixer_control *)kcontrol->private_value;
  619. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  620. unsigned int reg = mc->reg;
  621. unsigned int reg2 = mc->rreg;
  622. unsigned int shift = mc->shift;
  623. int max = mc->max;
  624. int mask = (1<<fls(max))-1;
  625. ucontrol->value.integer.value[0] =
  626. (snd_soc_read(codec, reg) >> shift) & mask;
  627. ucontrol->value.integer.value[1] =
  628. (snd_soc_read(codec, reg2) >> shift) & mask;
  629. if (ucontrol->value.integer.value[0])
  630. ucontrol->value.integer.value[0] =
  631. max + 1 - ucontrol->value.integer.value[0];
  632. if (ucontrol->value.integer.value[1])
  633. ucontrol->value.integer.value[1] =
  634. max + 1 - ucontrol->value.integer.value[1];
  635. return 0;
  636. }
  637. static int snd_soc_put_volsw_r2_twl4030(struct snd_kcontrol *kcontrol,
  638. struct snd_ctl_elem_value *ucontrol)
  639. {
  640. struct soc_mixer_control *mc =
  641. (struct soc_mixer_control *)kcontrol->private_value;
  642. struct snd_soc_codec *codec = snd_kcontrol_chip(kcontrol);
  643. unsigned int reg = mc->reg;
  644. unsigned int reg2 = mc->rreg;
  645. unsigned int shift = mc->shift;
  646. int max = mc->max;
  647. int mask = (1 << fls(max)) - 1;
  648. int err;
  649. unsigned short val, val2, val_mask;
  650. val_mask = mask << shift;
  651. val = (ucontrol->value.integer.value[0] & mask);
  652. val2 = (ucontrol->value.integer.value[1] & mask);
  653. if (val)
  654. val = max + 1 - val;
  655. if (val2)
  656. val2 = max + 1 - val2;
  657. val = val << shift;
  658. val2 = val2 << shift;
  659. err = snd_soc_update_bits(codec, reg, val_mask, val);
  660. if (err < 0)
  661. return err;
  662. err = snd_soc_update_bits(codec, reg2, val_mask, val2);
  663. return err;
  664. }
  665. /*
  666. * FGAIN volume control:
  667. * from -62 to 0 dB in 1 dB steps (mute instead of -63 dB)
  668. */
  669. static DECLARE_TLV_DB_SCALE(digital_fine_tlv, -6300, 100, 1);
  670. /*
  671. * CGAIN volume control:
  672. * 0 dB to 12 dB in 6 dB steps
  673. * value 2 and 3 means 12 dB
  674. */
  675. static DECLARE_TLV_DB_SCALE(digital_coarse_tlv, 0, 600, 0);
  676. /*
  677. * Voice Downlink GAIN volume control:
  678. * from -37 to 12 dB in 1 dB steps (mute instead of -37 dB)
  679. */
  680. static DECLARE_TLV_DB_SCALE(digital_voice_downlink_tlv, -3700, 100, 1);
  681. /*
  682. * Analog playback gain
  683. * -24 dB to 12 dB in 2 dB steps
  684. */
  685. static DECLARE_TLV_DB_SCALE(analog_tlv, -2400, 200, 0);
  686. /*
  687. * Gain controls tied to outputs
  688. * -6 dB to 6 dB in 6 dB steps (mute instead of -12)
  689. */
  690. static DECLARE_TLV_DB_SCALE(output_tvl, -1200, 600, 1);
  691. /*
  692. * Gain control for earpiece amplifier
  693. * 0 dB to 12 dB in 6 dB steps (mute instead of -6)
  694. */
  695. static DECLARE_TLV_DB_SCALE(output_ear_tvl, -600, 600, 1);
  696. /*
  697. * Capture gain after the ADCs
  698. * from 0 dB to 31 dB in 1 dB steps
  699. */
  700. static DECLARE_TLV_DB_SCALE(digital_capture_tlv, 0, 100, 0);
  701. /*
  702. * Gain control for input amplifiers
  703. * 0 dB to 30 dB in 6 dB steps
  704. */
  705. static DECLARE_TLV_DB_SCALE(input_gain_tlv, 0, 600, 0);
  706. static const char *twl4030_rampdelay_texts[] = {
  707. "27/20/14 ms", "55/40/27 ms", "109/81/55 ms", "218/161/109 ms",
  708. "437/323/218 ms", "874/645/437 ms", "1748/1291/874 ms",
  709. "3495/2581/1748 ms"
  710. };
  711. static const struct soc_enum twl4030_rampdelay_enum =
  712. SOC_ENUM_SINGLE(TWL4030_REG_HS_POPN_SET, 2,
  713. ARRAY_SIZE(twl4030_rampdelay_texts),
  714. twl4030_rampdelay_texts);
  715. static const struct snd_kcontrol_new twl4030_snd_controls[] = {
  716. /* Common playback gain controls */
  717. SOC_DOUBLE_R_TLV("DAC1 Digital Fine Playback Volume",
  718. TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
  719. 0, 0x3f, 0, digital_fine_tlv),
  720. SOC_DOUBLE_R_TLV("DAC2 Digital Fine Playback Volume",
  721. TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
  722. 0, 0x3f, 0, digital_fine_tlv),
  723. SOC_DOUBLE_R_TLV("DAC1 Digital Coarse Playback Volume",
  724. TWL4030_REG_ARXL1PGA, TWL4030_REG_ARXR1PGA,
  725. 6, 0x2, 0, digital_coarse_tlv),
  726. SOC_DOUBLE_R_TLV("DAC2 Digital Coarse Playback Volume",
  727. TWL4030_REG_ARXL2PGA, TWL4030_REG_ARXR2PGA,
  728. 6, 0x2, 0, digital_coarse_tlv),
  729. SOC_DOUBLE_R_TLV("DAC1 Analog Playback Volume",
  730. TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
  731. 3, 0x12, 1, analog_tlv),
  732. SOC_DOUBLE_R_TLV("DAC2 Analog Playback Volume",
  733. TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
  734. 3, 0x12, 1, analog_tlv),
  735. SOC_DOUBLE_R("DAC1 Analog Playback Switch",
  736. TWL4030_REG_ARXL1_APGA_CTL, TWL4030_REG_ARXR1_APGA_CTL,
  737. 1, 1, 0),
  738. SOC_DOUBLE_R("DAC2 Analog Playback Switch",
  739. TWL4030_REG_ARXL2_APGA_CTL, TWL4030_REG_ARXR2_APGA_CTL,
  740. 1, 1, 0),
  741. /* Common voice downlink gain controls */
  742. SOC_SINGLE_TLV("DAC Voice Digital Downlink Volume",
  743. TWL4030_REG_VRXPGA, 0, 0x31, 0, digital_voice_downlink_tlv),
  744. SOC_SINGLE_TLV("DAC Voice Analog Downlink Volume",
  745. TWL4030_REG_VDL_APGA_CTL, 3, 0x12, 1, analog_tlv),
  746. SOC_SINGLE("DAC Voice Analog Downlink Switch",
  747. TWL4030_REG_VDL_APGA_CTL, 1, 1, 0),
  748. /* Separate output gain controls */
  749. SOC_DOUBLE_R_TLV_TWL4030("PreDriv Playback Volume",
  750. TWL4030_REG_PREDL_CTL, TWL4030_REG_PREDR_CTL,
  751. 4, 3, 0, output_tvl),
  752. SOC_DOUBLE_TLV_TWL4030("Headset Playback Volume",
  753. TWL4030_REG_HS_GAIN_SET, 0, 2, 3, 0, output_tvl),
  754. SOC_DOUBLE_R_TLV_TWL4030("Carkit Playback Volume",
  755. TWL4030_REG_PRECKL_CTL, TWL4030_REG_PRECKR_CTL,
  756. 4, 3, 0, output_tvl),
  757. SOC_SINGLE_TLV_TWL4030("Earpiece Playback Volume",
  758. TWL4030_REG_EAR_CTL, 4, 3, 0, output_ear_tvl),
  759. /* Common capture gain controls */
  760. SOC_DOUBLE_R_TLV("TX1 Digital Capture Volume",
  761. TWL4030_REG_ATXL1PGA, TWL4030_REG_ATXR1PGA,
  762. 0, 0x1f, 0, digital_capture_tlv),
  763. SOC_DOUBLE_R_TLV("TX2 Digital Capture Volume",
  764. TWL4030_REG_AVTXL2PGA, TWL4030_REG_AVTXR2PGA,
  765. 0, 0x1f, 0, digital_capture_tlv),
  766. SOC_DOUBLE_TLV("Analog Capture Volume", TWL4030_REG_ANAMIC_GAIN,
  767. 0, 3, 5, 0, input_gain_tlv),
  768. SOC_ENUM("HS ramp delay", twl4030_rampdelay_enum),
  769. };
  770. static const struct snd_soc_dapm_widget twl4030_dapm_widgets[] = {
  771. /* Left channel inputs */
  772. SND_SOC_DAPM_INPUT("MAINMIC"),
  773. SND_SOC_DAPM_INPUT("HSMIC"),
  774. SND_SOC_DAPM_INPUT("AUXL"),
  775. SND_SOC_DAPM_INPUT("CARKITMIC"),
  776. /* Right channel inputs */
  777. SND_SOC_DAPM_INPUT("SUBMIC"),
  778. SND_SOC_DAPM_INPUT("AUXR"),
  779. /* Digital microphones (Stereo) */
  780. SND_SOC_DAPM_INPUT("DIGIMIC0"),
  781. SND_SOC_DAPM_INPUT("DIGIMIC1"),
  782. /* Outputs */
  783. SND_SOC_DAPM_OUTPUT("OUTL"),
  784. SND_SOC_DAPM_OUTPUT("OUTR"),
  785. SND_SOC_DAPM_OUTPUT("EARPIECE"),
  786. SND_SOC_DAPM_OUTPUT("PREDRIVEL"),
  787. SND_SOC_DAPM_OUTPUT("PREDRIVER"),
  788. SND_SOC_DAPM_OUTPUT("HSOL"),
  789. SND_SOC_DAPM_OUTPUT("HSOR"),
  790. SND_SOC_DAPM_OUTPUT("CARKITL"),
  791. SND_SOC_DAPM_OUTPUT("CARKITR"),
  792. SND_SOC_DAPM_OUTPUT("HFL"),
  793. SND_SOC_DAPM_OUTPUT("HFR"),
  794. /* DACs */
  795. SND_SOC_DAPM_DAC("DAC Right1", "Right Front Playback",
  796. SND_SOC_NOPM, 0, 0),
  797. SND_SOC_DAPM_DAC("DAC Left1", "Left Front Playback",
  798. SND_SOC_NOPM, 0, 0),
  799. SND_SOC_DAPM_DAC("DAC Right2", "Right Rear Playback",
  800. SND_SOC_NOPM, 0, 0),
  801. SND_SOC_DAPM_DAC("DAC Left2", "Left Rear Playback",
  802. SND_SOC_NOPM, 0, 0),
  803. SND_SOC_DAPM_DAC("DAC Voice", "Voice Playback",
  804. TWL4030_REG_AVDAC_CTL, 4, 0),
  805. /* Analog PGAs */
  806. SND_SOC_DAPM_PGA("ARXR1_APGA", TWL4030_REG_ARXR1_APGA_CTL,
  807. 0, 0, NULL, 0),
  808. SND_SOC_DAPM_PGA("ARXL1_APGA", TWL4030_REG_ARXL1_APGA_CTL,
  809. 0, 0, NULL, 0),
  810. SND_SOC_DAPM_PGA("ARXR2_APGA", TWL4030_REG_ARXR2_APGA_CTL,
  811. 0, 0, NULL, 0),
  812. SND_SOC_DAPM_PGA("ARXL2_APGA", TWL4030_REG_ARXL2_APGA_CTL,
  813. 0, 0, NULL, 0),
  814. SND_SOC_DAPM_PGA("VDL_APGA", TWL4030_REG_VDL_APGA_CTL,
  815. 0, 0, NULL, 0),
  816. /* Analog bypasses */
  817. SND_SOC_DAPM_SWITCH_E("Right1 Analog Loopback", SND_SOC_NOPM, 0, 0,
  818. &twl4030_dapm_abypassr1_control, bypass_event,
  819. SND_SOC_DAPM_POST_REG),
  820. SND_SOC_DAPM_SWITCH_E("Left1 Analog Loopback", SND_SOC_NOPM, 0, 0,
  821. &twl4030_dapm_abypassl1_control,
  822. bypass_event, SND_SOC_DAPM_POST_REG),
  823. SND_SOC_DAPM_SWITCH_E("Right2 Analog Loopback", SND_SOC_NOPM, 0, 0,
  824. &twl4030_dapm_abypassr2_control,
  825. bypass_event, SND_SOC_DAPM_POST_REG),
  826. SND_SOC_DAPM_SWITCH_E("Left2 Analog Loopback", SND_SOC_NOPM, 0, 0,
  827. &twl4030_dapm_abypassl2_control,
  828. bypass_event, SND_SOC_DAPM_POST_REG),
  829. /* Digital bypasses */
  830. SND_SOC_DAPM_SWITCH_E("Left Digital Loopback", SND_SOC_NOPM, 0, 0,
  831. &twl4030_dapm_dbypassl_control, bypass_event,
  832. SND_SOC_DAPM_POST_REG),
  833. SND_SOC_DAPM_SWITCH_E("Right Digital Loopback", SND_SOC_NOPM, 0, 0,
  834. &twl4030_dapm_dbypassr_control, bypass_event,
  835. SND_SOC_DAPM_POST_REG),
  836. SND_SOC_DAPM_MIXER("Analog R1 Playback Mixer", TWL4030_REG_AVDAC_CTL,
  837. 0, 0, NULL, 0),
  838. SND_SOC_DAPM_MIXER("Analog L1 Playback Mixer", TWL4030_REG_AVDAC_CTL,
  839. 1, 0, NULL, 0),
  840. SND_SOC_DAPM_MIXER("Analog R2 Playback Mixer", TWL4030_REG_AVDAC_CTL,
  841. 2, 0, NULL, 0),
  842. SND_SOC_DAPM_MIXER("Analog L2 Playback Mixer", TWL4030_REG_AVDAC_CTL,
  843. 3, 0, NULL, 0),
  844. /* Output MIXER controls */
  845. /* Earpiece */
  846. SND_SOC_DAPM_MIXER("Earpiece Mixer", SND_SOC_NOPM, 0, 0,
  847. &twl4030_dapm_earpiece_controls[0],
  848. ARRAY_SIZE(twl4030_dapm_earpiece_controls)),
  849. /* PreDrivL/R */
  850. SND_SOC_DAPM_MIXER("PredriveL Mixer", SND_SOC_NOPM, 0, 0,
  851. &twl4030_dapm_predrivel_controls[0],
  852. ARRAY_SIZE(twl4030_dapm_predrivel_controls)),
  853. SND_SOC_DAPM_MIXER("PredriveR Mixer", SND_SOC_NOPM, 0, 0,
  854. &twl4030_dapm_predriver_controls[0],
  855. ARRAY_SIZE(twl4030_dapm_predriver_controls)),
  856. /* HeadsetL/R */
  857. SND_SOC_DAPM_MIXER_E("HeadsetL Mixer", SND_SOC_NOPM, 0, 0,
  858. &twl4030_dapm_hsol_controls[0],
  859. ARRAY_SIZE(twl4030_dapm_hsol_controls), headsetl_event,
  860. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  861. SND_SOC_DAPM_MIXER("HeadsetR Mixer", SND_SOC_NOPM, 0, 0,
  862. &twl4030_dapm_hsor_controls[0],
  863. ARRAY_SIZE(twl4030_dapm_hsor_controls)),
  864. /* CarkitL/R */
  865. SND_SOC_DAPM_MIXER("CarkitL Mixer", SND_SOC_NOPM, 0, 0,
  866. &twl4030_dapm_carkitl_controls[0],
  867. ARRAY_SIZE(twl4030_dapm_carkitl_controls)),
  868. SND_SOC_DAPM_MIXER("CarkitR Mixer", SND_SOC_NOPM, 0, 0,
  869. &twl4030_dapm_carkitr_controls[0],
  870. ARRAY_SIZE(twl4030_dapm_carkitr_controls)),
  871. /* Output MUX controls */
  872. /* HandsfreeL/R */
  873. SND_SOC_DAPM_MUX_E("HandsfreeL Mux", TWL4030_REG_HFL_CTL, 5, 0,
  874. &twl4030_dapm_handsfreel_control, handsfree_event,
  875. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  876. SND_SOC_DAPM_MUX_E("HandsfreeR Mux", TWL4030_REG_HFR_CTL, 5, 0,
  877. &twl4030_dapm_handsfreer_control, handsfree_event,
  878. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD),
  879. /* Introducing four virtual ADC, since TWL4030 have four channel for
  880. capture */
  881. SND_SOC_DAPM_ADC("ADC Virtual Left1", "Left Front Capture",
  882. SND_SOC_NOPM, 0, 0),
  883. SND_SOC_DAPM_ADC("ADC Virtual Right1", "Right Front Capture",
  884. SND_SOC_NOPM, 0, 0),
  885. SND_SOC_DAPM_ADC("ADC Virtual Left2", "Left Rear Capture",
  886. SND_SOC_NOPM, 0, 0),
  887. SND_SOC_DAPM_ADC("ADC Virtual Right2", "Right Rear Capture",
  888. SND_SOC_NOPM, 0, 0),
  889. /* Analog/Digital mic path selection.
  890. TX1 Left/Right: either analog Left/Right or Digimic0
  891. TX2 Left/Right: either analog Left/Right or Digimic1 */
  892. SND_SOC_DAPM_MUX_E("TX1 Capture Route", SND_SOC_NOPM, 0, 0,
  893. &twl4030_dapm_micpathtx1_control, micpath_event,
  894. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
  895. SND_SOC_DAPM_POST_REG),
  896. SND_SOC_DAPM_MUX_E("TX2 Capture Route", SND_SOC_NOPM, 0, 0,
  897. &twl4030_dapm_micpathtx2_control, micpath_event,
  898. SND_SOC_DAPM_POST_PMU|SND_SOC_DAPM_POST_PMD|
  899. SND_SOC_DAPM_POST_REG),
  900. /* Analog input muxes with switch for the capture amplifiers */
  901. SND_SOC_DAPM_VALUE_MUX("Analog Left Capture Route",
  902. TWL4030_REG_ANAMICL, 4, 0, &twl4030_dapm_analoglmic_control),
  903. SND_SOC_DAPM_VALUE_MUX("Analog Right Capture Route",
  904. TWL4030_REG_ANAMICR, 4, 0, &twl4030_dapm_analogrmic_control),
  905. SND_SOC_DAPM_PGA("ADC Physical Left",
  906. TWL4030_REG_AVADC_CTL, 3, 0, NULL, 0),
  907. SND_SOC_DAPM_PGA("ADC Physical Right",
  908. TWL4030_REG_AVADC_CTL, 1, 0, NULL, 0),
  909. SND_SOC_DAPM_PGA("Digimic0 Enable",
  910. TWL4030_REG_ADCMICSEL, 1, 0, NULL, 0),
  911. SND_SOC_DAPM_PGA("Digimic1 Enable",
  912. TWL4030_REG_ADCMICSEL, 3, 0, NULL, 0),
  913. SND_SOC_DAPM_MICBIAS("Mic Bias 1", TWL4030_REG_MICBIAS_CTL, 0, 0),
  914. SND_SOC_DAPM_MICBIAS("Mic Bias 2", TWL4030_REG_MICBIAS_CTL, 1, 0),
  915. SND_SOC_DAPM_MICBIAS("Headset Mic Bias", TWL4030_REG_MICBIAS_CTL, 2, 0),
  916. };
  917. static const struct snd_soc_dapm_route intercon[] = {
  918. {"Analog L1 Playback Mixer", NULL, "DAC Left1"},
  919. {"Analog R1 Playback Mixer", NULL, "DAC Right1"},
  920. {"Analog L2 Playback Mixer", NULL, "DAC Left2"},
  921. {"Analog R2 Playback Mixer", NULL, "DAC Right2"},
  922. {"ARXL1_APGA", NULL, "Analog L1 Playback Mixer"},
  923. {"ARXR1_APGA", NULL, "Analog R1 Playback Mixer"},
  924. {"ARXL2_APGA", NULL, "Analog L2 Playback Mixer"},
  925. {"ARXR2_APGA", NULL, "Analog R2 Playback Mixer"},
  926. {"VDL_APGA", NULL, "DAC Voice"},
  927. /* Internal playback routings */
  928. /* Earpiece */
  929. {"Earpiece Mixer", "Voice", "VDL_APGA"},
  930. {"Earpiece Mixer", "AudioL1", "ARXL1_APGA"},
  931. {"Earpiece Mixer", "AudioL2", "ARXL2_APGA"},
  932. {"Earpiece Mixer", "AudioR1", "ARXR1_APGA"},
  933. /* PreDrivL */
  934. {"PredriveL Mixer", "Voice", "VDL_APGA"},
  935. {"PredriveL Mixer", "AudioL1", "ARXL1_APGA"},
  936. {"PredriveL Mixer", "AudioL2", "ARXL2_APGA"},
  937. {"PredriveL Mixer", "AudioR2", "ARXR2_APGA"},
  938. /* PreDrivR */
  939. {"PredriveR Mixer", "Voice", "VDL_APGA"},
  940. {"PredriveR Mixer", "AudioR1", "ARXR1_APGA"},
  941. {"PredriveR Mixer", "AudioR2", "ARXR2_APGA"},
  942. {"PredriveR Mixer", "AudioL2", "ARXL2_APGA"},
  943. /* HeadsetL */
  944. {"HeadsetL Mixer", "Voice", "VDL_APGA"},
  945. {"HeadsetL Mixer", "AudioL1", "ARXL1_APGA"},
  946. {"HeadsetL Mixer", "AudioL2", "ARXL2_APGA"},
  947. /* HeadsetR */
  948. {"HeadsetR Mixer", "Voice", "VDL_APGA"},
  949. {"HeadsetR Mixer", "AudioR1", "ARXR1_APGA"},
  950. {"HeadsetR Mixer", "AudioR2", "ARXR2_APGA"},
  951. /* CarkitL */
  952. {"CarkitL Mixer", "Voice", "VDL_APGA"},
  953. {"CarkitL Mixer", "AudioL1", "ARXL1_APGA"},
  954. {"CarkitL Mixer", "AudioL2", "ARXL2_APGA"},
  955. /* CarkitR */
  956. {"CarkitR Mixer", "Voice", "VDL_APGA"},
  957. {"CarkitR Mixer", "AudioR1", "ARXR1_APGA"},
  958. {"CarkitR Mixer", "AudioR2", "ARXR2_APGA"},
  959. /* HandsfreeL */
  960. {"HandsfreeL Mux", "Voice", "VDL_APGA"},
  961. {"HandsfreeL Mux", "AudioL1", "ARXL1_APGA"},
  962. {"HandsfreeL Mux", "AudioL2", "ARXL2_APGA"},
  963. {"HandsfreeL Mux", "AudioR2", "ARXR2_APGA"},
  964. /* HandsfreeR */
  965. {"HandsfreeR Mux", "Voice", "VDL_APGA"},
  966. {"HandsfreeR Mux", "AudioR1", "ARXR1_APGA"},
  967. {"HandsfreeR Mux", "AudioR2", "ARXR2_APGA"},
  968. {"HandsfreeR Mux", "AudioL2", "ARXL2_APGA"},
  969. /* outputs */
  970. {"OUTL", NULL, "ARXL2_APGA"},
  971. {"OUTR", NULL, "ARXR2_APGA"},
  972. {"EARPIECE", NULL, "Earpiece Mixer"},
  973. {"PREDRIVEL", NULL, "PredriveL Mixer"},
  974. {"PREDRIVER", NULL, "PredriveR Mixer"},
  975. {"HSOL", NULL, "HeadsetL Mixer"},
  976. {"HSOR", NULL, "HeadsetR Mixer"},
  977. {"CARKITL", NULL, "CarkitL Mixer"},
  978. {"CARKITR", NULL, "CarkitR Mixer"},
  979. {"HFL", NULL, "HandsfreeL Mux"},
  980. {"HFR", NULL, "HandsfreeR Mux"},
  981. /* Capture path */
  982. {"Analog Left Capture Route", "Main mic", "MAINMIC"},
  983. {"Analog Left Capture Route", "Headset mic", "HSMIC"},
  984. {"Analog Left Capture Route", "AUXL", "AUXL"},
  985. {"Analog Left Capture Route", "Carkit mic", "CARKITMIC"},
  986. {"Analog Right Capture Route", "Sub mic", "SUBMIC"},
  987. {"Analog Right Capture Route", "AUXR", "AUXR"},
  988. {"ADC Physical Left", NULL, "Analog Left Capture Route"},
  989. {"ADC Physical Right", NULL, "Analog Right Capture Route"},
  990. {"Digimic0 Enable", NULL, "DIGIMIC0"},
  991. {"Digimic1 Enable", NULL, "DIGIMIC1"},
  992. /* TX1 Left capture path */
  993. {"TX1 Capture Route", "Analog", "ADC Physical Left"},
  994. {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
  995. /* TX1 Right capture path */
  996. {"TX1 Capture Route", "Analog", "ADC Physical Right"},
  997. {"TX1 Capture Route", "Digimic0", "Digimic0 Enable"},
  998. /* TX2 Left capture path */
  999. {"TX2 Capture Route", "Analog", "ADC Physical Left"},
  1000. {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
  1001. /* TX2 Right capture path */
  1002. {"TX2 Capture Route", "Analog", "ADC Physical Right"},
  1003. {"TX2 Capture Route", "Digimic1", "Digimic1 Enable"},
  1004. {"ADC Virtual Left1", NULL, "TX1 Capture Route"},
  1005. {"ADC Virtual Right1", NULL, "TX1 Capture Route"},
  1006. {"ADC Virtual Left2", NULL, "TX2 Capture Route"},
  1007. {"ADC Virtual Right2", NULL, "TX2 Capture Route"},
  1008. /* Analog bypass routes */
  1009. {"Right1 Analog Loopback", "Switch", "Analog Right Capture Route"},
  1010. {"Left1 Analog Loopback", "Switch", "Analog Left Capture Route"},
  1011. {"Right2 Analog Loopback", "Switch", "Analog Right Capture Route"},
  1012. {"Left2 Analog Loopback", "Switch", "Analog Left Capture Route"},
  1013. {"Analog R1 Playback Mixer", NULL, "Right1 Analog Loopback"},
  1014. {"Analog L1 Playback Mixer", NULL, "Left1 Analog Loopback"},
  1015. {"Analog R2 Playback Mixer", NULL, "Right2 Analog Loopback"},
  1016. {"Analog L2 Playback Mixer", NULL, "Left2 Analog Loopback"},
  1017. /* Digital bypass routes */
  1018. {"Right Digital Loopback", "Volume", "TX1 Capture Route"},
  1019. {"Left Digital Loopback", "Volume", "TX1 Capture Route"},
  1020. {"Analog R2 Playback Mixer", NULL, "Right Digital Loopback"},
  1021. {"Analog L2 Playback Mixer", NULL, "Left Digital Loopback"},
  1022. };
  1023. static int twl4030_add_widgets(struct snd_soc_codec *codec)
  1024. {
  1025. snd_soc_dapm_new_controls(codec, twl4030_dapm_widgets,
  1026. ARRAY_SIZE(twl4030_dapm_widgets));
  1027. snd_soc_dapm_add_routes(codec, intercon, ARRAY_SIZE(intercon));
  1028. snd_soc_dapm_new_widgets(codec);
  1029. return 0;
  1030. }
  1031. static int twl4030_set_bias_level(struct snd_soc_codec *codec,
  1032. enum snd_soc_bias_level level)
  1033. {
  1034. struct twl4030_priv *twl4030 = codec->private_data;
  1035. switch (level) {
  1036. case SND_SOC_BIAS_ON:
  1037. twl4030_codec_mute(codec, 0);
  1038. break;
  1039. case SND_SOC_BIAS_PREPARE:
  1040. twl4030_power_up(codec);
  1041. if (twl4030->bypass_state)
  1042. twl4030_codec_mute(codec, 0);
  1043. else
  1044. twl4030_codec_mute(codec, 1);
  1045. break;
  1046. case SND_SOC_BIAS_STANDBY:
  1047. twl4030_power_up(codec);
  1048. if (twl4030->bypass_state)
  1049. twl4030_codec_mute(codec, 0);
  1050. else
  1051. twl4030_codec_mute(codec, 1);
  1052. break;
  1053. case SND_SOC_BIAS_OFF:
  1054. twl4030_power_down(codec);
  1055. break;
  1056. }
  1057. codec->bias_level = level;
  1058. return 0;
  1059. }
  1060. static void twl4030_constraints(struct twl4030_priv *twl4030,
  1061. struct snd_pcm_substream *mst_substream)
  1062. {
  1063. struct snd_pcm_substream *slv_substream;
  1064. /* Pick the stream, which need to be constrained */
  1065. if (mst_substream == twl4030->master_substream)
  1066. slv_substream = twl4030->slave_substream;
  1067. else if (mst_substream == twl4030->slave_substream)
  1068. slv_substream = twl4030->master_substream;
  1069. else /* This should not happen.. */
  1070. return;
  1071. /* Set the constraints according to the already configured stream */
  1072. snd_pcm_hw_constraint_minmax(slv_substream->runtime,
  1073. SNDRV_PCM_HW_PARAM_RATE,
  1074. twl4030->rate,
  1075. twl4030->rate);
  1076. snd_pcm_hw_constraint_minmax(slv_substream->runtime,
  1077. SNDRV_PCM_HW_PARAM_SAMPLE_BITS,
  1078. twl4030->sample_bits,
  1079. twl4030->sample_bits);
  1080. snd_pcm_hw_constraint_minmax(slv_substream->runtime,
  1081. SNDRV_PCM_HW_PARAM_CHANNELS,
  1082. twl4030->channels,
  1083. twl4030->channels);
  1084. }
  1085. /* In case of 4 channel mode, the RX1 L/R for playback and the TX2 L/R for
  1086. * capture has to be enabled/disabled. */
  1087. static void twl4030_tdm_enable(struct snd_soc_codec *codec, int direction,
  1088. int enable)
  1089. {
  1090. u8 reg, mask;
  1091. reg = twl4030_read_reg_cache(codec, TWL4030_REG_OPTION);
  1092. if (direction == SNDRV_PCM_STREAM_PLAYBACK)
  1093. mask = TWL4030_ARXL1_VRX_EN | TWL4030_ARXR1_EN;
  1094. else
  1095. mask = TWL4030_ATXL2_VTXL_EN | TWL4030_ATXR2_VTXR_EN;
  1096. if (enable)
  1097. reg |= mask;
  1098. else
  1099. reg &= ~mask;
  1100. twl4030_write(codec, TWL4030_REG_OPTION, reg);
  1101. }
  1102. static int twl4030_startup(struct snd_pcm_substream *substream,
  1103. struct snd_soc_dai *dai)
  1104. {
  1105. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1106. struct snd_soc_device *socdev = rtd->socdev;
  1107. struct snd_soc_codec *codec = socdev->card->codec;
  1108. struct twl4030_priv *twl4030 = codec->private_data;
  1109. if (twl4030->master_substream) {
  1110. twl4030->slave_substream = substream;
  1111. /* The DAI has one configuration for playback and capture, so
  1112. * if the DAI has been already configured then constrain this
  1113. * substream to match it. */
  1114. if (twl4030->configured)
  1115. twl4030_constraints(twl4030, twl4030->master_substream);
  1116. } else {
  1117. if (!(twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) &
  1118. TWL4030_OPTION_1)) {
  1119. /* In option2 4 channel is not supported, set the
  1120. * constraint for the first stream for channels, the
  1121. * second stream will 'inherit' this cosntraint */
  1122. snd_pcm_hw_constraint_minmax(substream->runtime,
  1123. SNDRV_PCM_HW_PARAM_CHANNELS,
  1124. 2, 2);
  1125. }
  1126. twl4030->master_substream = substream;
  1127. }
  1128. return 0;
  1129. }
  1130. static void twl4030_shutdown(struct snd_pcm_substream *substream,
  1131. struct snd_soc_dai *dai)
  1132. {
  1133. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1134. struct snd_soc_device *socdev = rtd->socdev;
  1135. struct snd_soc_codec *codec = socdev->card->codec;
  1136. struct twl4030_priv *twl4030 = codec->private_data;
  1137. if (twl4030->master_substream == substream)
  1138. twl4030->master_substream = twl4030->slave_substream;
  1139. twl4030->slave_substream = NULL;
  1140. /* If all streams are closed, or the remaining stream has not yet
  1141. * been configured than set the DAI as not configured. */
  1142. if (!twl4030->master_substream)
  1143. twl4030->configured = 0;
  1144. else if (!twl4030->master_substream->runtime->channels)
  1145. twl4030->configured = 0;
  1146. /* If the closing substream had 4 channel, do the necessary cleanup */
  1147. if (substream->runtime->channels == 4)
  1148. twl4030_tdm_enable(codec, substream->stream, 0);
  1149. }
  1150. static int twl4030_hw_params(struct snd_pcm_substream *substream,
  1151. struct snd_pcm_hw_params *params,
  1152. struct snd_soc_dai *dai)
  1153. {
  1154. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1155. struct snd_soc_device *socdev = rtd->socdev;
  1156. struct snd_soc_codec *codec = socdev->card->codec;
  1157. struct twl4030_priv *twl4030 = codec->private_data;
  1158. u8 mode, old_mode, format, old_format;
  1159. /* If the substream has 4 channel, do the necessary setup */
  1160. if (params_channels(params) == 4) {
  1161. /* Safety check: are we in the correct operating mode? */
  1162. if ((twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE) &
  1163. TWL4030_OPTION_1))
  1164. twl4030_tdm_enable(codec, substream->stream, 1);
  1165. else
  1166. return -EINVAL;
  1167. }
  1168. if (twl4030->configured)
  1169. /* Ignoring hw_params for already configured DAI */
  1170. return 0;
  1171. /* bit rate */
  1172. old_mode = twl4030_read_reg_cache(codec,
  1173. TWL4030_REG_CODEC_MODE) & ~TWL4030_CODECPDZ;
  1174. mode = old_mode & ~TWL4030_APLL_RATE;
  1175. switch (params_rate(params)) {
  1176. case 8000:
  1177. mode |= TWL4030_APLL_RATE_8000;
  1178. break;
  1179. case 11025:
  1180. mode |= TWL4030_APLL_RATE_11025;
  1181. break;
  1182. case 12000:
  1183. mode |= TWL4030_APLL_RATE_12000;
  1184. break;
  1185. case 16000:
  1186. mode |= TWL4030_APLL_RATE_16000;
  1187. break;
  1188. case 22050:
  1189. mode |= TWL4030_APLL_RATE_22050;
  1190. break;
  1191. case 24000:
  1192. mode |= TWL4030_APLL_RATE_24000;
  1193. break;
  1194. case 32000:
  1195. mode |= TWL4030_APLL_RATE_32000;
  1196. break;
  1197. case 44100:
  1198. mode |= TWL4030_APLL_RATE_44100;
  1199. break;
  1200. case 48000:
  1201. mode |= TWL4030_APLL_RATE_48000;
  1202. break;
  1203. case 96000:
  1204. mode |= TWL4030_APLL_RATE_96000;
  1205. break;
  1206. default:
  1207. printk(KERN_ERR "TWL4030 hw params: unknown rate %d\n",
  1208. params_rate(params));
  1209. return -EINVAL;
  1210. }
  1211. if (mode != old_mode) {
  1212. /* change rate and set CODECPDZ */
  1213. twl4030_codec_enable(codec, 0);
  1214. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  1215. twl4030_codec_enable(codec, 1);
  1216. }
  1217. /* sample size */
  1218. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1219. format = old_format;
  1220. format &= ~TWL4030_DATA_WIDTH;
  1221. switch (params_format(params)) {
  1222. case SNDRV_PCM_FORMAT_S16_LE:
  1223. format |= TWL4030_DATA_WIDTH_16S_16W;
  1224. break;
  1225. case SNDRV_PCM_FORMAT_S24_LE:
  1226. format |= TWL4030_DATA_WIDTH_32S_24W;
  1227. break;
  1228. default:
  1229. printk(KERN_ERR "TWL4030 hw params: unknown format %d\n",
  1230. params_format(params));
  1231. return -EINVAL;
  1232. }
  1233. if (format != old_format) {
  1234. /* clear CODECPDZ before changing format (codec requirement) */
  1235. twl4030_codec_enable(codec, 0);
  1236. /* change format */
  1237. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  1238. /* set CODECPDZ afterwards */
  1239. twl4030_codec_enable(codec, 1);
  1240. }
  1241. /* Store the important parameters for the DAI configuration and set
  1242. * the DAI as configured */
  1243. twl4030->configured = 1;
  1244. twl4030->rate = params_rate(params);
  1245. twl4030->sample_bits = hw_param_interval(params,
  1246. SNDRV_PCM_HW_PARAM_SAMPLE_BITS)->min;
  1247. twl4030->channels = params_channels(params);
  1248. /* If both playback and capture streams are open, and one of them
  1249. * is setting the hw parameters right now (since we are here), set
  1250. * constraints to the other stream to match the current one. */
  1251. if (twl4030->slave_substream)
  1252. twl4030_constraints(twl4030, substream);
  1253. return 0;
  1254. }
  1255. static int twl4030_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  1256. int clk_id, unsigned int freq, int dir)
  1257. {
  1258. struct snd_soc_codec *codec = codec_dai->codec;
  1259. u8 infreq;
  1260. switch (freq) {
  1261. case 19200000:
  1262. infreq = TWL4030_APLL_INFREQ_19200KHZ;
  1263. break;
  1264. case 26000000:
  1265. infreq = TWL4030_APLL_INFREQ_26000KHZ;
  1266. break;
  1267. case 38400000:
  1268. infreq = TWL4030_APLL_INFREQ_38400KHZ;
  1269. break;
  1270. default:
  1271. printk(KERN_ERR "TWL4030 set sysclk: unknown rate %d\n",
  1272. freq);
  1273. return -EINVAL;
  1274. }
  1275. infreq |= TWL4030_APLL_EN;
  1276. twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
  1277. return 0;
  1278. }
  1279. static int twl4030_set_dai_fmt(struct snd_soc_dai *codec_dai,
  1280. unsigned int fmt)
  1281. {
  1282. struct snd_soc_codec *codec = codec_dai->codec;
  1283. u8 old_format, format;
  1284. /* get format */
  1285. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_AUDIO_IF);
  1286. format = old_format;
  1287. /* set master/slave audio interface */
  1288. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1289. case SND_SOC_DAIFMT_CBM_CFM:
  1290. format &= ~(TWL4030_AIF_SLAVE_EN);
  1291. format &= ~(TWL4030_CLK256FS_EN);
  1292. break;
  1293. case SND_SOC_DAIFMT_CBS_CFS:
  1294. format |= TWL4030_AIF_SLAVE_EN;
  1295. format |= TWL4030_CLK256FS_EN;
  1296. break;
  1297. default:
  1298. return -EINVAL;
  1299. }
  1300. /* interface format */
  1301. format &= ~TWL4030_AIF_FORMAT;
  1302. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  1303. case SND_SOC_DAIFMT_I2S:
  1304. format |= TWL4030_AIF_FORMAT_CODEC;
  1305. break;
  1306. case SND_SOC_DAIFMT_DSP_A:
  1307. format |= TWL4030_AIF_FORMAT_TDM;
  1308. break;
  1309. default:
  1310. return -EINVAL;
  1311. }
  1312. if (format != old_format) {
  1313. /* clear CODECPDZ before changing format (codec requirement) */
  1314. twl4030_codec_enable(codec, 0);
  1315. /* change format */
  1316. twl4030_write(codec, TWL4030_REG_AUDIO_IF, format);
  1317. /* set CODECPDZ afterwards */
  1318. twl4030_codec_enable(codec, 1);
  1319. }
  1320. return 0;
  1321. }
  1322. static int twl4030_voice_startup(struct snd_pcm_substream *substream,
  1323. struct snd_soc_dai *dai)
  1324. {
  1325. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1326. struct snd_soc_device *socdev = rtd->socdev;
  1327. struct snd_soc_codec *codec = socdev->card->codec;
  1328. u8 infreq;
  1329. u8 mode;
  1330. /* If the system master clock is not 26MHz, the voice PCM interface is
  1331. * not avilable.
  1332. */
  1333. infreq = twl4030_read_reg_cache(codec, TWL4030_REG_APLL_CTL)
  1334. & TWL4030_APLL_INFREQ;
  1335. if (infreq != TWL4030_APLL_INFREQ_26000KHZ) {
  1336. printk(KERN_ERR "TWL4030 voice startup: "
  1337. "MCLK is not 26MHz, call set_sysclk() on init\n");
  1338. return -EINVAL;
  1339. }
  1340. /* If the codec mode is not option2, the voice PCM interface is not
  1341. * avilable.
  1342. */
  1343. mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
  1344. & TWL4030_OPT_MODE;
  1345. if (mode != TWL4030_OPTION_2) {
  1346. printk(KERN_ERR "TWL4030 voice startup: "
  1347. "the codec mode is not option2\n");
  1348. return -EINVAL;
  1349. }
  1350. return 0;
  1351. }
  1352. static int twl4030_voice_hw_params(struct snd_pcm_substream *substream,
  1353. struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
  1354. {
  1355. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  1356. struct snd_soc_device *socdev = rtd->socdev;
  1357. struct snd_soc_codec *codec = socdev->card->codec;
  1358. u8 old_mode, mode;
  1359. /* bit rate */
  1360. old_mode = twl4030_read_reg_cache(codec, TWL4030_REG_CODEC_MODE)
  1361. & ~(TWL4030_CODECPDZ);
  1362. mode = old_mode;
  1363. switch (params_rate(params)) {
  1364. case 8000:
  1365. mode &= ~(TWL4030_SEL_16K);
  1366. break;
  1367. case 16000:
  1368. mode |= TWL4030_SEL_16K;
  1369. break;
  1370. default:
  1371. printk(KERN_ERR "TWL4030 voice hw params: unknown rate %d\n",
  1372. params_rate(params));
  1373. return -EINVAL;
  1374. }
  1375. if (mode != old_mode) {
  1376. /* change rate and set CODECPDZ */
  1377. twl4030_codec_enable(codec, 0);
  1378. twl4030_write(codec, TWL4030_REG_CODEC_MODE, mode);
  1379. twl4030_codec_enable(codec, 1);
  1380. }
  1381. return 0;
  1382. }
  1383. static int twl4030_voice_set_dai_sysclk(struct snd_soc_dai *codec_dai,
  1384. int clk_id, unsigned int freq, int dir)
  1385. {
  1386. struct snd_soc_codec *codec = codec_dai->codec;
  1387. u8 infreq;
  1388. switch (freq) {
  1389. case 26000000:
  1390. infreq = TWL4030_APLL_INFREQ_26000KHZ;
  1391. break;
  1392. default:
  1393. printk(KERN_ERR "TWL4030 voice set sysclk: unknown rate %d\n",
  1394. freq);
  1395. return -EINVAL;
  1396. }
  1397. infreq |= TWL4030_APLL_EN;
  1398. twl4030_write(codec, TWL4030_REG_APLL_CTL, infreq);
  1399. return 0;
  1400. }
  1401. static int twl4030_voice_set_dai_fmt(struct snd_soc_dai *codec_dai,
  1402. unsigned int fmt)
  1403. {
  1404. struct snd_soc_codec *codec = codec_dai->codec;
  1405. u8 old_format, format;
  1406. /* get format */
  1407. old_format = twl4030_read_reg_cache(codec, TWL4030_REG_VOICE_IF);
  1408. format = old_format;
  1409. /* set master/slave audio interface */
  1410. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1411. case SND_SOC_DAIFMT_CBS_CFM:
  1412. format &= ~(TWL4030_VIF_SLAVE_EN);
  1413. break;
  1414. case SND_SOC_DAIFMT_CBS_CFS:
  1415. format |= TWL4030_VIF_SLAVE_EN;
  1416. break;
  1417. default:
  1418. return -EINVAL;
  1419. }
  1420. /* clock inversion */
  1421. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  1422. case SND_SOC_DAIFMT_IB_NF:
  1423. format &= ~(TWL4030_VIF_FORMAT);
  1424. break;
  1425. case SND_SOC_DAIFMT_NB_IF:
  1426. format |= TWL4030_VIF_FORMAT;
  1427. break;
  1428. default:
  1429. return -EINVAL;
  1430. }
  1431. if (format != old_format) {
  1432. /* change format and set CODECPDZ */
  1433. twl4030_codec_enable(codec, 0);
  1434. twl4030_write(codec, TWL4030_REG_VOICE_IF, format);
  1435. twl4030_codec_enable(codec, 1);
  1436. }
  1437. return 0;
  1438. }
  1439. #define TWL4030_RATES (SNDRV_PCM_RATE_8000_48000)
  1440. #define TWL4030_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FORMAT_S24_LE)
  1441. static struct snd_soc_dai_ops twl4030_dai_ops = {
  1442. .startup = twl4030_startup,
  1443. .shutdown = twl4030_shutdown,
  1444. .hw_params = twl4030_hw_params,
  1445. .set_sysclk = twl4030_set_dai_sysclk,
  1446. .set_fmt = twl4030_set_dai_fmt,
  1447. };
  1448. static struct snd_soc_dai_ops twl4030_dai_voice_ops = {
  1449. .startup = twl4030_voice_startup,
  1450. .hw_params = twl4030_voice_hw_params,
  1451. .set_sysclk = twl4030_voice_set_dai_sysclk,
  1452. .set_fmt = twl4030_voice_set_dai_fmt,
  1453. };
  1454. struct snd_soc_dai twl4030_dai[] = {
  1455. {
  1456. .name = "twl4030",
  1457. .playback = {
  1458. .stream_name = "Playback",
  1459. .channels_min = 2,
  1460. .channels_max = 4,
  1461. .rates = TWL4030_RATES | SNDRV_PCM_RATE_96000,
  1462. .formats = TWL4030_FORMATS,},
  1463. .capture = {
  1464. .stream_name = "Capture",
  1465. .channels_min = 2,
  1466. .channels_max = 4,
  1467. .rates = TWL4030_RATES,
  1468. .formats = TWL4030_FORMATS,},
  1469. .ops = &twl4030_dai_ops,
  1470. },
  1471. {
  1472. .name = "twl4030 Voice",
  1473. .playback = {
  1474. .stream_name = "Playback",
  1475. .channels_min = 1,
  1476. .channels_max = 1,
  1477. .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
  1478. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  1479. .capture = {
  1480. .stream_name = "Capture",
  1481. .channels_min = 1,
  1482. .channels_max = 2,
  1483. .rates = SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000,
  1484. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  1485. .ops = &twl4030_dai_voice_ops,
  1486. },
  1487. };
  1488. EXPORT_SYMBOL_GPL(twl4030_dai);
  1489. static int twl4030_suspend(struct platform_device *pdev, pm_message_t state)
  1490. {
  1491. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1492. struct snd_soc_codec *codec = socdev->card->codec;
  1493. twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
  1494. return 0;
  1495. }
  1496. static int twl4030_resume(struct platform_device *pdev)
  1497. {
  1498. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1499. struct snd_soc_codec *codec = socdev->card->codec;
  1500. twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  1501. twl4030_set_bias_level(codec, codec->suspend_bias_level);
  1502. return 0;
  1503. }
  1504. /*
  1505. * initialize the driver
  1506. * register the mixer and dsp interfaces with the kernel
  1507. */
  1508. static int twl4030_init(struct snd_soc_device *socdev)
  1509. {
  1510. struct snd_soc_codec *codec = socdev->card->codec;
  1511. int ret = 0;
  1512. printk(KERN_INFO "TWL4030 Audio Codec init \n");
  1513. codec->name = "twl4030";
  1514. codec->owner = THIS_MODULE;
  1515. codec->read = twl4030_read_reg_cache;
  1516. codec->write = twl4030_write;
  1517. codec->set_bias_level = twl4030_set_bias_level;
  1518. codec->dai = twl4030_dai;
  1519. codec->num_dai = ARRAY_SIZE(twl4030_dai),
  1520. codec->reg_cache_size = sizeof(twl4030_reg);
  1521. codec->reg_cache = kmemdup(twl4030_reg, sizeof(twl4030_reg),
  1522. GFP_KERNEL);
  1523. if (codec->reg_cache == NULL)
  1524. return -ENOMEM;
  1525. /* register pcms */
  1526. ret = snd_soc_new_pcms(socdev, SNDRV_DEFAULT_IDX1, SNDRV_DEFAULT_STR1);
  1527. if (ret < 0) {
  1528. printk(KERN_ERR "twl4030: failed to create pcms\n");
  1529. goto pcm_err;
  1530. }
  1531. twl4030_init_chip(codec);
  1532. /* power on device */
  1533. twl4030_set_bias_level(codec, SND_SOC_BIAS_STANDBY);
  1534. snd_soc_add_controls(codec, twl4030_snd_controls,
  1535. ARRAY_SIZE(twl4030_snd_controls));
  1536. twl4030_add_widgets(codec);
  1537. ret = snd_soc_init_card(socdev);
  1538. if (ret < 0) {
  1539. printk(KERN_ERR "twl4030: failed to register card\n");
  1540. goto card_err;
  1541. }
  1542. return ret;
  1543. card_err:
  1544. snd_soc_free_pcms(socdev);
  1545. snd_soc_dapm_free(socdev);
  1546. pcm_err:
  1547. kfree(codec->reg_cache);
  1548. return ret;
  1549. }
  1550. static struct snd_soc_device *twl4030_socdev;
  1551. static int twl4030_probe(struct platform_device *pdev)
  1552. {
  1553. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1554. struct snd_soc_codec *codec;
  1555. struct twl4030_priv *twl4030;
  1556. codec = kzalloc(sizeof(struct snd_soc_codec), GFP_KERNEL);
  1557. if (codec == NULL)
  1558. return -ENOMEM;
  1559. twl4030 = kzalloc(sizeof(struct twl4030_priv), GFP_KERNEL);
  1560. if (twl4030 == NULL) {
  1561. kfree(codec);
  1562. return -ENOMEM;
  1563. }
  1564. codec->private_data = twl4030;
  1565. socdev->card->codec = codec;
  1566. mutex_init(&codec->mutex);
  1567. INIT_LIST_HEAD(&codec->dapm_widgets);
  1568. INIT_LIST_HEAD(&codec->dapm_paths);
  1569. twl4030_socdev = socdev;
  1570. twl4030_init(socdev);
  1571. return 0;
  1572. }
  1573. static int twl4030_remove(struct platform_device *pdev)
  1574. {
  1575. struct snd_soc_device *socdev = platform_get_drvdata(pdev);
  1576. struct snd_soc_codec *codec = socdev->card->codec;
  1577. printk(KERN_INFO "TWL4030 Audio Codec remove\n");
  1578. twl4030_set_bias_level(codec, SND_SOC_BIAS_OFF);
  1579. snd_soc_free_pcms(socdev);
  1580. snd_soc_dapm_free(socdev);
  1581. kfree(codec->private_data);
  1582. kfree(codec);
  1583. return 0;
  1584. }
  1585. struct snd_soc_codec_device soc_codec_dev_twl4030 = {
  1586. .probe = twl4030_probe,
  1587. .remove = twl4030_remove,
  1588. .suspend = twl4030_suspend,
  1589. .resume = twl4030_resume,
  1590. };
  1591. EXPORT_SYMBOL_GPL(soc_codec_dev_twl4030);
  1592. static int __init twl4030_modinit(void)
  1593. {
  1594. return snd_soc_register_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
  1595. }
  1596. module_init(twl4030_modinit);
  1597. static void __exit twl4030_exit(void)
  1598. {
  1599. snd_soc_unregister_dais(&twl4030_dai[0], ARRAY_SIZE(twl4030_dai));
  1600. }
  1601. module_exit(twl4030_exit);
  1602. MODULE_DESCRIPTION("ASoC TWL4030 codec driver");
  1603. MODULE_AUTHOR("Steve Sakoman");
  1604. MODULE_LICENSE("GPL");