pwm-imx.c 7.6 KB

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  1. /*
  2. * simple driver for PWM (Pulse Width Modulator) controller
  3. *
  4. * This program is free software; you can redistribute it and/or modify
  5. * it under the terms of the GNU General Public License version 2 as
  6. * published by the Free Software Foundation.
  7. *
  8. * Derived from pxa PWM driver by eric miao <eric.miao@marvell.com>
  9. */
  10. #include <linux/module.h>
  11. #include <linux/kernel.h>
  12. #include <linux/platform_device.h>
  13. #include <linux/slab.h>
  14. #include <linux/err.h>
  15. #include <linux/clk.h>
  16. #include <linux/io.h>
  17. #include <linux/pwm.h>
  18. #include <linux/of_device.h>
  19. /* i.MX1 and i.MX21 share the same PWM function block: */
  20. #define MX1_PWMC 0x00 /* PWM Control Register */
  21. #define MX1_PWMS 0x04 /* PWM Sample Register */
  22. #define MX1_PWMP 0x08 /* PWM Period Register */
  23. #define MX1_PWMC_EN (1 << 4)
  24. /* i.MX27, i.MX31, i.MX35 share the same PWM function block: */
  25. #define MX3_PWMCR 0x00 /* PWM Control Register */
  26. #define MX3_PWMSAR 0x0C /* PWM Sample Register */
  27. #define MX3_PWMPR 0x10 /* PWM Period Register */
  28. #define MX3_PWMCR_PRESCALER(x) (((x - 1) & 0xFFF) << 4)
  29. #define MX3_PWMCR_DOZEEN (1 << 24)
  30. #define MX3_PWMCR_WAITEN (1 << 23)
  31. #define MX3_PWMCR_DBGEN (1 << 22)
  32. #define MX3_PWMCR_CLKSRC_IPG_HIGH (2 << 16)
  33. #define MX3_PWMCR_CLKSRC_IPG (1 << 16)
  34. #define MX3_PWMCR_EN (1 << 0)
  35. struct imx_chip {
  36. struct clk *clk_per;
  37. struct clk *clk_ipg;
  38. void __iomem *mmio_base;
  39. struct pwm_chip chip;
  40. int (*config)(struct pwm_chip *chip,
  41. struct pwm_device *pwm, int duty_ns, int period_ns);
  42. void (*set_enable)(struct pwm_chip *chip, bool enable);
  43. };
  44. #define to_imx_chip(chip) container_of(chip, struct imx_chip, chip)
  45. static int imx_pwm_config_v1(struct pwm_chip *chip,
  46. struct pwm_device *pwm, int duty_ns, int period_ns)
  47. {
  48. struct imx_chip *imx = to_imx_chip(chip);
  49. /*
  50. * The PWM subsystem allows for exact frequencies. However,
  51. * I cannot connect a scope on my device to the PWM line and
  52. * thus cannot provide the program the PWM controller
  53. * exactly. Instead, I'm relying on the fact that the
  54. * Bootloader (u-boot or WinCE+haret) has programmed the PWM
  55. * function group already. So I'll just modify the PWM sample
  56. * register to follow the ratio of duty_ns vs. period_ns
  57. * accordingly.
  58. *
  59. * This is good enough for programming the brightness of
  60. * the LCD backlight.
  61. *
  62. * The real implementation would divide PERCLK[0] first by
  63. * both the prescaler (/1 .. /128) and then by CLKSEL
  64. * (/2 .. /16).
  65. */
  66. u32 max = readl(imx->mmio_base + MX1_PWMP);
  67. u32 p = max * duty_ns / period_ns;
  68. writel(max - p, imx->mmio_base + MX1_PWMS);
  69. return 0;
  70. }
  71. static void imx_pwm_set_enable_v1(struct pwm_chip *chip, bool enable)
  72. {
  73. struct imx_chip *imx = to_imx_chip(chip);
  74. u32 val;
  75. val = readl(imx->mmio_base + MX1_PWMC);
  76. if (enable)
  77. val |= MX1_PWMC_EN;
  78. else
  79. val &= ~MX1_PWMC_EN;
  80. writel(val, imx->mmio_base + MX1_PWMC);
  81. }
  82. static int imx_pwm_config_v2(struct pwm_chip *chip,
  83. struct pwm_device *pwm, int duty_ns, int period_ns)
  84. {
  85. struct imx_chip *imx = to_imx_chip(chip);
  86. unsigned long long c;
  87. unsigned long period_cycles, duty_cycles, prescale;
  88. u32 cr;
  89. c = clk_get_rate(imx->clk_per);
  90. c = c * period_ns;
  91. do_div(c, 1000000000);
  92. period_cycles = c;
  93. prescale = period_cycles / 0x10000 + 1;
  94. period_cycles /= prescale;
  95. c = (unsigned long long)period_cycles * duty_ns;
  96. do_div(c, period_ns);
  97. duty_cycles = c;
  98. /*
  99. * according to imx pwm RM, the real period value should be
  100. * PERIOD value in PWMPR plus 2.
  101. */
  102. if (period_cycles > 2)
  103. period_cycles -= 2;
  104. else
  105. period_cycles = 0;
  106. writel(duty_cycles, imx->mmio_base + MX3_PWMSAR);
  107. writel(period_cycles, imx->mmio_base + MX3_PWMPR);
  108. cr = MX3_PWMCR_PRESCALER(prescale) |
  109. MX3_PWMCR_DOZEEN | MX3_PWMCR_WAITEN |
  110. MX3_PWMCR_DBGEN | MX3_PWMCR_CLKSRC_IPG_HIGH;
  111. if (test_bit(PWMF_ENABLED, &pwm->flags))
  112. cr |= MX3_PWMCR_EN;
  113. writel(cr, imx->mmio_base + MX3_PWMCR);
  114. return 0;
  115. }
  116. static void imx_pwm_set_enable_v2(struct pwm_chip *chip, bool enable)
  117. {
  118. struct imx_chip *imx = to_imx_chip(chip);
  119. u32 val;
  120. val = readl(imx->mmio_base + MX3_PWMCR);
  121. if (enable)
  122. val |= MX3_PWMCR_EN;
  123. else
  124. val &= ~MX3_PWMCR_EN;
  125. writel(val, imx->mmio_base + MX3_PWMCR);
  126. }
  127. static int imx_pwm_config(struct pwm_chip *chip,
  128. struct pwm_device *pwm, int duty_ns, int period_ns)
  129. {
  130. struct imx_chip *imx = to_imx_chip(chip);
  131. int ret;
  132. ret = clk_prepare_enable(imx->clk_ipg);
  133. if (ret)
  134. return ret;
  135. ret = imx->config(chip, pwm, duty_ns, period_ns);
  136. clk_disable_unprepare(imx->clk_ipg);
  137. return ret;
  138. }
  139. static int imx_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm)
  140. {
  141. struct imx_chip *imx = to_imx_chip(chip);
  142. int ret;
  143. ret = clk_prepare_enable(imx->clk_per);
  144. if (ret)
  145. return ret;
  146. imx->set_enable(chip, true);
  147. return 0;
  148. }
  149. static void imx_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm)
  150. {
  151. struct imx_chip *imx = to_imx_chip(chip);
  152. imx->set_enable(chip, false);
  153. clk_disable_unprepare(imx->clk_per);
  154. }
  155. static struct pwm_ops imx_pwm_ops = {
  156. .enable = imx_pwm_enable,
  157. .disable = imx_pwm_disable,
  158. .config = imx_pwm_config,
  159. .owner = THIS_MODULE,
  160. };
  161. struct imx_pwm_data {
  162. int (*config)(struct pwm_chip *chip,
  163. struct pwm_device *pwm, int duty_ns, int period_ns);
  164. void (*set_enable)(struct pwm_chip *chip, bool enable);
  165. };
  166. static struct imx_pwm_data imx_pwm_data_v1 = {
  167. .config = imx_pwm_config_v1,
  168. .set_enable = imx_pwm_set_enable_v1,
  169. };
  170. static struct imx_pwm_data imx_pwm_data_v2 = {
  171. .config = imx_pwm_config_v2,
  172. .set_enable = imx_pwm_set_enable_v2,
  173. };
  174. static const struct of_device_id imx_pwm_dt_ids[] = {
  175. { .compatible = "fsl,imx1-pwm", .data = &imx_pwm_data_v1, },
  176. { .compatible = "fsl,imx27-pwm", .data = &imx_pwm_data_v2, },
  177. { /* sentinel */ }
  178. };
  179. MODULE_DEVICE_TABLE(of, imx_pwm_dt_ids);
  180. static int imx_pwm_probe(struct platform_device *pdev)
  181. {
  182. const struct of_device_id *of_id =
  183. of_match_device(imx_pwm_dt_ids, &pdev->dev);
  184. const struct imx_pwm_data *data;
  185. struct imx_chip *imx;
  186. struct resource *r;
  187. int ret = 0;
  188. if (!of_id)
  189. return -ENODEV;
  190. imx = devm_kzalloc(&pdev->dev, sizeof(*imx), GFP_KERNEL);
  191. if (imx == NULL) {
  192. dev_err(&pdev->dev, "failed to allocate memory\n");
  193. return -ENOMEM;
  194. }
  195. imx->clk_per = devm_clk_get(&pdev->dev, "per");
  196. if (IS_ERR(imx->clk_per)) {
  197. dev_err(&pdev->dev, "getting per clock failed with %ld\n",
  198. PTR_ERR(imx->clk_per));
  199. return PTR_ERR(imx->clk_per);
  200. }
  201. imx->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
  202. if (IS_ERR(imx->clk_ipg)) {
  203. dev_err(&pdev->dev, "getting ipg clock failed with %ld\n",
  204. PTR_ERR(imx->clk_ipg));
  205. return PTR_ERR(imx->clk_ipg);
  206. }
  207. imx->chip.ops = &imx_pwm_ops;
  208. imx->chip.dev = &pdev->dev;
  209. imx->chip.base = -1;
  210. imx->chip.npwm = 1;
  211. r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  212. if (r == NULL) {
  213. dev_err(&pdev->dev, "no memory resource defined\n");
  214. return -ENODEV;
  215. }
  216. imx->mmio_base = devm_ioremap_resource(&pdev->dev, r);
  217. if (IS_ERR(imx->mmio_base))
  218. return PTR_ERR(imx->mmio_base);
  219. data = of_id->data;
  220. imx->config = data->config;
  221. imx->set_enable = data->set_enable;
  222. ret = pwmchip_add(&imx->chip);
  223. if (ret < 0)
  224. return ret;
  225. platform_set_drvdata(pdev, imx);
  226. return 0;
  227. }
  228. static int imx_pwm_remove(struct platform_device *pdev)
  229. {
  230. struct imx_chip *imx;
  231. imx = platform_get_drvdata(pdev);
  232. if (imx == NULL)
  233. return -ENODEV;
  234. return pwmchip_remove(&imx->chip);
  235. }
  236. static struct platform_driver imx_pwm_driver = {
  237. .driver = {
  238. .name = "imx-pwm",
  239. .of_match_table = of_match_ptr(imx_pwm_dt_ids),
  240. },
  241. .probe = imx_pwm_probe,
  242. .remove = imx_pwm_remove,
  243. };
  244. module_platform_driver(imx_pwm_driver);
  245. MODULE_LICENSE("GPL v2");
  246. MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");