iwl-agn.c 117 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved.
  4. *
  5. * Portions of this file are derived from the ipw3945 project, as well
  6. * as portions of the ieee80211 subsystem header files.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of version 2 of the GNU General Public License as
  10. * published by the Free Software Foundation.
  11. *
  12. * This program is distributed in the hope that it will be useful, but WITHOUT
  13. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  15. * more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along with
  18. * this program; if not, write to the Free Software Foundation, Inc.,
  19. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  20. *
  21. * The full GNU General Public License is included in this distribution in the
  22. * file called LICENSE.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30. #include <linux/kernel.h>
  31. #include <linux/module.h>
  32. #include <linux/init.h>
  33. #include <linux/pci.h>
  34. #include <linux/pci-aspm.h>
  35. #include <linux/slab.h>
  36. #include <linux/dma-mapping.h>
  37. #include <linux/delay.h>
  38. #include <linux/sched.h>
  39. #include <linux/skbuff.h>
  40. #include <linux/netdevice.h>
  41. #include <linux/wireless.h>
  42. #include <linux/firmware.h>
  43. #include <linux/etherdevice.h>
  44. #include <linux/if_arp.h>
  45. #include <net/mac80211.h>
  46. #include <asm/div64.h>
  47. #define DRV_NAME "iwlagn"
  48. #include "iwl-eeprom.h"
  49. #include "iwl-dev.h"
  50. #include "iwl-core.h"
  51. #include "iwl-io.h"
  52. #include "iwl-helpers.h"
  53. #include "iwl-sta.h"
  54. #include "iwl-agn-calib.h"
  55. #include "iwl-agn.h"
  56. /******************************************************************************
  57. *
  58. * module boiler plate
  59. *
  60. ******************************************************************************/
  61. /*
  62. * module name, copyright, version, etc.
  63. */
  64. #define DRV_DESCRIPTION "Intel(R) Wireless WiFi Link AGN driver for Linux"
  65. #ifdef CONFIG_IWLWIFI_DEBUG
  66. #define VD "d"
  67. #else
  68. #define VD
  69. #endif
  70. #define DRV_VERSION IWLWIFI_VERSION VD
  71. MODULE_DESCRIPTION(DRV_DESCRIPTION);
  72. MODULE_VERSION(DRV_VERSION);
  73. MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR);
  74. MODULE_LICENSE("GPL");
  75. static int iwlagn_ant_coupling;
  76. static bool iwlagn_bt_ch_announce = 1;
  77. void iwl_update_chain_flags(struct iwl_priv *priv)
  78. {
  79. struct iwl_rxon_context *ctx;
  80. if (priv->cfg->ops->hcmd->set_rxon_chain) {
  81. for_each_context(priv, ctx) {
  82. priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
  83. if (ctx->active.rx_chain != ctx->staging.rx_chain)
  84. iwlagn_commit_rxon(priv, ctx);
  85. }
  86. }
  87. }
  88. /* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */
  89. static void iwl_set_beacon_tim(struct iwl_priv *priv,
  90. struct iwl_tx_beacon_cmd *tx_beacon_cmd,
  91. u8 *beacon, u32 frame_size)
  92. {
  93. u16 tim_idx;
  94. struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon;
  95. /*
  96. * The index is relative to frame start but we start looking at the
  97. * variable-length part of the beacon.
  98. */
  99. tim_idx = mgmt->u.beacon.variable - beacon;
  100. /* Parse variable-length elements of beacon to find WLAN_EID_TIM */
  101. while ((tim_idx < (frame_size - 2)) &&
  102. (beacon[tim_idx] != WLAN_EID_TIM))
  103. tim_idx += beacon[tim_idx+1] + 2;
  104. /* If TIM field was found, set variables */
  105. if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) {
  106. tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx);
  107. tx_beacon_cmd->tim_size = beacon[tim_idx+1];
  108. } else
  109. IWL_WARN(priv, "Unable to find TIM Element in beacon\n");
  110. }
  111. int iwlagn_send_beacon_cmd(struct iwl_priv *priv)
  112. {
  113. struct iwl_tx_beacon_cmd *tx_beacon_cmd;
  114. struct iwl_host_cmd cmd = {
  115. .id = REPLY_TX_BEACON,
  116. };
  117. u32 frame_size;
  118. u32 rate_flags;
  119. u32 rate;
  120. /*
  121. * We have to set up the TX command, the TX Beacon command, and the
  122. * beacon contents.
  123. */
  124. lockdep_assert_held(&priv->mutex);
  125. if (!priv->beacon_ctx) {
  126. IWL_ERR(priv, "trying to build beacon w/o beacon context!\n");
  127. return 0;
  128. }
  129. if (WARN_ON(!priv->beacon_skb))
  130. return -EINVAL;
  131. /* Allocate beacon command */
  132. if (!priv->beacon_cmd)
  133. priv->beacon_cmd = kzalloc(sizeof(*tx_beacon_cmd), GFP_KERNEL);
  134. tx_beacon_cmd = priv->beacon_cmd;
  135. if (!tx_beacon_cmd)
  136. return -ENOMEM;
  137. frame_size = priv->beacon_skb->len;
  138. /* Set up TX command fields */
  139. tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
  140. tx_beacon_cmd->tx.sta_id = priv->beacon_ctx->bcast_sta_id;
  141. tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  142. tx_beacon_cmd->tx.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK |
  143. TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK;
  144. /* Set up TX beacon command fields */
  145. iwl_set_beacon_tim(priv, tx_beacon_cmd, priv->beacon_skb->data,
  146. frame_size);
  147. /* Set up packet rate and flags */
  148. rate = iwl_rate_get_lowest_plcp(priv, priv->beacon_ctx);
  149. priv->mgmt_tx_ant = iwl_toggle_tx_ant(priv, priv->mgmt_tx_ant,
  150. priv->hw_params.valid_tx_ant);
  151. rate_flags = iwl_ant_idx_to_flags(priv->mgmt_tx_ant);
  152. if ((rate >= IWL_FIRST_CCK_RATE) && (rate <= IWL_LAST_CCK_RATE))
  153. rate_flags |= RATE_MCS_CCK_MSK;
  154. tx_beacon_cmd->tx.rate_n_flags = iwl_hw_set_rate_n_flags(rate,
  155. rate_flags);
  156. /* Submit command */
  157. cmd.len[0] = sizeof(*tx_beacon_cmd);
  158. cmd.data[0] = tx_beacon_cmd;
  159. cmd.dataflags[0] = IWL_HCMD_DFL_NOCOPY;
  160. cmd.len[1] = frame_size;
  161. cmd.data[1] = priv->beacon_skb->data;
  162. cmd.dataflags[1] = IWL_HCMD_DFL_NOCOPY;
  163. return iwl_send_cmd_sync(priv, &cmd);
  164. }
  165. static void iwl_bg_beacon_update(struct work_struct *work)
  166. {
  167. struct iwl_priv *priv =
  168. container_of(work, struct iwl_priv, beacon_update);
  169. struct sk_buff *beacon;
  170. mutex_lock(&priv->mutex);
  171. if (!priv->beacon_ctx) {
  172. IWL_ERR(priv, "updating beacon w/o beacon context!\n");
  173. goto out;
  174. }
  175. if (priv->beacon_ctx->vif->type != NL80211_IFTYPE_AP) {
  176. /*
  177. * The ucode will send beacon notifications even in
  178. * IBSS mode, but we don't want to process them. But
  179. * we need to defer the type check to here due to
  180. * requiring locking around the beacon_ctx access.
  181. */
  182. goto out;
  183. }
  184. /* Pull updated AP beacon from mac80211. will fail if not in AP mode */
  185. beacon = ieee80211_beacon_get(priv->hw, priv->beacon_ctx->vif);
  186. if (!beacon) {
  187. IWL_ERR(priv, "update beacon failed -- keeping old\n");
  188. goto out;
  189. }
  190. /* new beacon skb is allocated every time; dispose previous.*/
  191. dev_kfree_skb(priv->beacon_skb);
  192. priv->beacon_skb = beacon;
  193. iwlagn_send_beacon_cmd(priv);
  194. out:
  195. mutex_unlock(&priv->mutex);
  196. }
  197. static void iwl_bg_bt_runtime_config(struct work_struct *work)
  198. {
  199. struct iwl_priv *priv =
  200. container_of(work, struct iwl_priv, bt_runtime_config);
  201. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  202. return;
  203. /* dont send host command if rf-kill is on */
  204. if (!iwl_is_ready_rf(priv))
  205. return;
  206. priv->cfg->ops->hcmd->send_bt_config(priv);
  207. }
  208. static void iwl_bg_bt_full_concurrency(struct work_struct *work)
  209. {
  210. struct iwl_priv *priv =
  211. container_of(work, struct iwl_priv, bt_full_concurrency);
  212. struct iwl_rxon_context *ctx;
  213. mutex_lock(&priv->mutex);
  214. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  215. goto out;
  216. /* dont send host command if rf-kill is on */
  217. if (!iwl_is_ready_rf(priv))
  218. goto out;
  219. IWL_DEBUG_INFO(priv, "BT coex in %s mode\n",
  220. priv->bt_full_concurrent ?
  221. "full concurrency" : "3-wire");
  222. /*
  223. * LQ & RXON updated cmds must be sent before BT Config cmd
  224. * to avoid 3-wire collisions
  225. */
  226. for_each_context(priv, ctx) {
  227. if (priv->cfg->ops->hcmd->set_rxon_chain)
  228. priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
  229. iwlagn_commit_rxon(priv, ctx);
  230. }
  231. priv->cfg->ops->hcmd->send_bt_config(priv);
  232. out:
  233. mutex_unlock(&priv->mutex);
  234. }
  235. /**
  236. * iwl_bg_statistics_periodic - Timer callback to queue statistics
  237. *
  238. * This callback is provided in order to send a statistics request.
  239. *
  240. * This timer function is continually reset to execute within
  241. * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
  242. * was received. We need to ensure we receive the statistics in order
  243. * to update the temperature used for calibrating the TXPOWER.
  244. */
  245. static void iwl_bg_statistics_periodic(unsigned long data)
  246. {
  247. struct iwl_priv *priv = (struct iwl_priv *)data;
  248. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  249. return;
  250. /* dont send host command if rf-kill is on */
  251. if (!iwl_is_ready_rf(priv))
  252. return;
  253. iwl_send_statistics_request(priv, CMD_ASYNC, false);
  254. }
  255. static void iwl_print_cont_event_trace(struct iwl_priv *priv, u32 base,
  256. u32 start_idx, u32 num_events,
  257. u32 mode)
  258. {
  259. u32 i;
  260. u32 ptr; /* SRAM byte address of log data */
  261. u32 ev, time, data; /* event log data */
  262. unsigned long reg_flags;
  263. if (mode == 0)
  264. ptr = base + (4 * sizeof(u32)) + (start_idx * 2 * sizeof(u32));
  265. else
  266. ptr = base + (4 * sizeof(u32)) + (start_idx * 3 * sizeof(u32));
  267. /* Make sure device is powered up for SRAM reads */
  268. spin_lock_irqsave(&priv->reg_lock, reg_flags);
  269. if (iwl_grab_nic_access(priv)) {
  270. spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
  271. return;
  272. }
  273. /* Set starting address; reads will auto-increment */
  274. iwl_write32(priv, HBUS_TARG_MEM_RADDR, ptr);
  275. rmb();
  276. /*
  277. * "time" is actually "data" for mode 0 (no timestamp).
  278. * place event id # at far right for easier visual parsing.
  279. */
  280. for (i = 0; i < num_events; i++) {
  281. ev = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
  282. time = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
  283. if (mode == 0) {
  284. trace_iwlwifi_dev_ucode_cont_event(priv,
  285. 0, time, ev);
  286. } else {
  287. data = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
  288. trace_iwlwifi_dev_ucode_cont_event(priv,
  289. time, data, ev);
  290. }
  291. }
  292. /* Allow device to power down */
  293. iwl_release_nic_access(priv);
  294. spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
  295. }
  296. static void iwl_continuous_event_trace(struct iwl_priv *priv)
  297. {
  298. u32 capacity; /* event log capacity in # entries */
  299. u32 base; /* SRAM byte address of event log header */
  300. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  301. u32 num_wraps; /* # times uCode wrapped to top of log */
  302. u32 next_entry; /* index of next entry to be written by uCode */
  303. base = priv->device_pointers.error_event_table;
  304. if (priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  305. capacity = iwl_read_targ_mem(priv, base);
  306. num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
  307. mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
  308. next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
  309. } else
  310. return;
  311. if (num_wraps == priv->event_log.num_wraps) {
  312. iwl_print_cont_event_trace(priv,
  313. base, priv->event_log.next_entry,
  314. next_entry - priv->event_log.next_entry,
  315. mode);
  316. priv->event_log.non_wraps_count++;
  317. } else {
  318. if ((num_wraps - priv->event_log.num_wraps) > 1)
  319. priv->event_log.wraps_more_count++;
  320. else
  321. priv->event_log.wraps_once_count++;
  322. trace_iwlwifi_dev_ucode_wrap_event(priv,
  323. num_wraps - priv->event_log.num_wraps,
  324. next_entry, priv->event_log.next_entry);
  325. if (next_entry < priv->event_log.next_entry) {
  326. iwl_print_cont_event_trace(priv, base,
  327. priv->event_log.next_entry,
  328. capacity - priv->event_log.next_entry,
  329. mode);
  330. iwl_print_cont_event_trace(priv, base, 0,
  331. next_entry, mode);
  332. } else {
  333. iwl_print_cont_event_trace(priv, base,
  334. next_entry, capacity - next_entry,
  335. mode);
  336. iwl_print_cont_event_trace(priv, base, 0,
  337. next_entry, mode);
  338. }
  339. }
  340. priv->event_log.num_wraps = num_wraps;
  341. priv->event_log.next_entry = next_entry;
  342. }
  343. /**
  344. * iwl_bg_ucode_trace - Timer callback to log ucode event
  345. *
  346. * The timer is continually set to execute every
  347. * UCODE_TRACE_PERIOD milliseconds after the last timer expired
  348. * this function is to perform continuous uCode event logging operation
  349. * if enabled
  350. */
  351. static void iwl_bg_ucode_trace(unsigned long data)
  352. {
  353. struct iwl_priv *priv = (struct iwl_priv *)data;
  354. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  355. return;
  356. if (priv->event_log.ucode_trace) {
  357. iwl_continuous_event_trace(priv);
  358. /* Reschedule the timer to occur in UCODE_TRACE_PERIOD */
  359. mod_timer(&priv->ucode_trace,
  360. jiffies + msecs_to_jiffies(UCODE_TRACE_PERIOD));
  361. }
  362. }
  363. static void iwl_bg_tx_flush(struct work_struct *work)
  364. {
  365. struct iwl_priv *priv =
  366. container_of(work, struct iwl_priv, tx_flush);
  367. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  368. return;
  369. /* do nothing if rf-kill is on */
  370. if (!iwl_is_ready_rf(priv))
  371. return;
  372. IWL_DEBUG_INFO(priv, "device request: flush all tx frames\n");
  373. iwlagn_dev_txfifo_flush(priv, IWL_DROP_ALL);
  374. }
  375. /**
  376. * iwl_rx_handle - Main entry function for receiving responses from uCode
  377. *
  378. * Uses the priv->rx_handlers callback function array to invoke
  379. * the appropriate handlers, including command responses,
  380. * frame-received notifications, and other notifications.
  381. */
  382. static void iwl_rx_handle(struct iwl_priv *priv)
  383. {
  384. struct iwl_rx_mem_buffer *rxb;
  385. struct iwl_rx_packet *pkt;
  386. struct iwl_rx_queue *rxq = &priv->rxq;
  387. u32 r, i;
  388. int reclaim;
  389. unsigned long flags;
  390. u8 fill_rx = 0;
  391. u32 count = 8;
  392. int total_empty;
  393. /* uCode's read index (stored in shared DRAM) indicates the last Rx
  394. * buffer that the driver may process (last buffer filled by ucode). */
  395. r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF;
  396. i = rxq->read;
  397. /* Rx interrupt, but nothing sent from uCode */
  398. if (i == r)
  399. IWL_DEBUG_RX(priv, "r = %d, i = %d\n", r, i);
  400. /* calculate total frames need to be restock after handling RX */
  401. total_empty = r - rxq->write_actual;
  402. if (total_empty < 0)
  403. total_empty += RX_QUEUE_SIZE;
  404. if (total_empty > (RX_QUEUE_SIZE / 2))
  405. fill_rx = 1;
  406. while (i != r) {
  407. int len;
  408. rxb = rxq->queue[i];
  409. /* If an RXB doesn't have a Rx queue slot associated with it,
  410. * then a bug has been introduced in the queue refilling
  411. * routines -- catch it here */
  412. if (WARN_ON(rxb == NULL)) {
  413. i = (i + 1) & RX_QUEUE_MASK;
  414. continue;
  415. }
  416. rxq->queue[i] = NULL;
  417. pci_unmap_page(priv->pci_dev, rxb->page_dma,
  418. PAGE_SIZE << priv->hw_params.rx_page_order,
  419. PCI_DMA_FROMDEVICE);
  420. pkt = rxb_addr(rxb);
  421. len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
  422. len += sizeof(u32); /* account for status word */
  423. trace_iwlwifi_dev_rx(priv, pkt, len);
  424. /* Reclaim a command buffer only if this packet is a response
  425. * to a (driver-originated) command.
  426. * If the packet (e.g. Rx frame) originated from uCode,
  427. * there is no command buffer to reclaim.
  428. * Ucode should set SEQ_RX_FRAME bit if ucode-originated,
  429. * but apparently a few don't get set; catch them here. */
  430. reclaim = !(pkt->hdr.sequence & SEQ_RX_FRAME) &&
  431. (pkt->hdr.cmd != REPLY_RX_PHY_CMD) &&
  432. (pkt->hdr.cmd != REPLY_RX) &&
  433. (pkt->hdr.cmd != REPLY_RX_MPDU_CMD) &&
  434. (pkt->hdr.cmd != REPLY_COMPRESSED_BA) &&
  435. (pkt->hdr.cmd != STATISTICS_NOTIFICATION) &&
  436. (pkt->hdr.cmd != REPLY_TX);
  437. /*
  438. * Do the notification wait before RX handlers so
  439. * even if the RX handler consumes the RXB we have
  440. * access to it in the notification wait entry.
  441. */
  442. if (!list_empty(&priv->_agn.notif_waits)) {
  443. struct iwl_notification_wait *w;
  444. spin_lock(&priv->_agn.notif_wait_lock);
  445. list_for_each_entry(w, &priv->_agn.notif_waits, list) {
  446. if (w->cmd == pkt->hdr.cmd) {
  447. w->triggered = true;
  448. if (w->fn)
  449. w->fn(priv, pkt, w->fn_data);
  450. }
  451. }
  452. spin_unlock(&priv->_agn.notif_wait_lock);
  453. wake_up_all(&priv->_agn.notif_waitq);
  454. }
  455. if (priv->pre_rx_handler)
  456. priv->pre_rx_handler(priv, rxb);
  457. /* Based on type of command response or notification,
  458. * handle those that need handling via function in
  459. * rx_handlers table. See iwl_setup_rx_handlers() */
  460. if (priv->rx_handlers[pkt->hdr.cmd]) {
  461. IWL_DEBUG_RX(priv, "r = %d, i = %d, %s, 0x%02x\n", r,
  462. i, get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd);
  463. priv->isr_stats.rx_handlers[pkt->hdr.cmd]++;
  464. priv->rx_handlers[pkt->hdr.cmd] (priv, rxb);
  465. } else {
  466. /* No handling needed */
  467. IWL_DEBUG_RX(priv,
  468. "r %d i %d No handler needed for %s, 0x%02x\n",
  469. r, i, get_cmd_string(pkt->hdr.cmd),
  470. pkt->hdr.cmd);
  471. }
  472. /*
  473. * XXX: After here, we should always check rxb->page
  474. * against NULL before touching it or its virtual
  475. * memory (pkt). Because some rx_handler might have
  476. * already taken or freed the pages.
  477. */
  478. if (reclaim) {
  479. /* Invoke any callbacks, transfer the buffer to caller,
  480. * and fire off the (possibly) blocking iwl_send_cmd()
  481. * as we reclaim the driver command queue */
  482. if (rxb->page)
  483. iwl_tx_cmd_complete(priv, rxb);
  484. else
  485. IWL_WARN(priv, "Claim null rxb?\n");
  486. }
  487. /* Reuse the page if possible. For notification packets and
  488. * SKBs that fail to Rx correctly, add them back into the
  489. * rx_free list for reuse later. */
  490. spin_lock_irqsave(&rxq->lock, flags);
  491. if (rxb->page != NULL) {
  492. rxb->page_dma = pci_map_page(priv->pci_dev, rxb->page,
  493. 0, PAGE_SIZE << priv->hw_params.rx_page_order,
  494. PCI_DMA_FROMDEVICE);
  495. list_add_tail(&rxb->list, &rxq->rx_free);
  496. rxq->free_count++;
  497. } else
  498. list_add_tail(&rxb->list, &rxq->rx_used);
  499. spin_unlock_irqrestore(&rxq->lock, flags);
  500. i = (i + 1) & RX_QUEUE_MASK;
  501. /* If there are a lot of unused frames,
  502. * restock the Rx queue so ucode wont assert. */
  503. if (fill_rx) {
  504. count++;
  505. if (count >= 8) {
  506. rxq->read = i;
  507. iwlagn_rx_replenish_now(priv);
  508. count = 0;
  509. }
  510. }
  511. }
  512. /* Backtrack one entry */
  513. rxq->read = i;
  514. if (fill_rx)
  515. iwlagn_rx_replenish_now(priv);
  516. else
  517. iwlagn_rx_queue_restock(priv);
  518. }
  519. /* tasklet for iwlagn interrupt */
  520. static void iwl_irq_tasklet(struct iwl_priv *priv)
  521. {
  522. u32 inta = 0;
  523. u32 handled = 0;
  524. unsigned long flags;
  525. u32 i;
  526. #ifdef CONFIG_IWLWIFI_DEBUG
  527. u32 inta_mask;
  528. #endif
  529. spin_lock_irqsave(&priv->lock, flags);
  530. /* Ack/clear/reset pending uCode interrupts.
  531. * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS,
  532. */
  533. /* There is a hardware bug in the interrupt mask function that some
  534. * interrupts (i.e. CSR_INT_BIT_SCD) can still be generated even if
  535. * they are disabled in the CSR_INT_MASK register. Furthermore the
  536. * ICT interrupt handling mechanism has another bug that might cause
  537. * these unmasked interrupts fail to be detected. We workaround the
  538. * hardware bugs here by ACKing all the possible interrupts so that
  539. * interrupt coalescing can still be achieved.
  540. */
  541. iwl_write32(priv, CSR_INT, priv->_agn.inta | ~priv->inta_mask);
  542. inta = priv->_agn.inta;
  543. #ifdef CONFIG_IWLWIFI_DEBUG
  544. if (iwl_get_debug_level(priv) & IWL_DL_ISR) {
  545. /* just for debug */
  546. inta_mask = iwl_read32(priv, CSR_INT_MASK);
  547. IWL_DEBUG_ISR(priv, "inta 0x%08x, enabled 0x%08x\n ",
  548. inta, inta_mask);
  549. }
  550. #endif
  551. spin_unlock_irqrestore(&priv->lock, flags);
  552. /* saved interrupt in inta variable now we can reset priv->_agn.inta */
  553. priv->_agn.inta = 0;
  554. /* Now service all interrupt bits discovered above. */
  555. if (inta & CSR_INT_BIT_HW_ERR) {
  556. IWL_ERR(priv, "Hardware error detected. Restarting.\n");
  557. /* Tell the device to stop sending interrupts */
  558. iwl_disable_interrupts(priv);
  559. priv->isr_stats.hw++;
  560. iwl_irq_handle_error(priv);
  561. handled |= CSR_INT_BIT_HW_ERR;
  562. return;
  563. }
  564. #ifdef CONFIG_IWLWIFI_DEBUG
  565. if (iwl_get_debug_level(priv) & (IWL_DL_ISR)) {
  566. /* NIC fires this, but we don't use it, redundant with WAKEUP */
  567. if (inta & CSR_INT_BIT_SCD) {
  568. IWL_DEBUG_ISR(priv, "Scheduler finished to transmit "
  569. "the frame/frames.\n");
  570. priv->isr_stats.sch++;
  571. }
  572. /* Alive notification via Rx interrupt will do the real work */
  573. if (inta & CSR_INT_BIT_ALIVE) {
  574. IWL_DEBUG_ISR(priv, "Alive interrupt\n");
  575. priv->isr_stats.alive++;
  576. }
  577. }
  578. #endif
  579. /* Safely ignore these bits for debug checks below */
  580. inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE);
  581. /* HW RF KILL switch toggled */
  582. if (inta & CSR_INT_BIT_RF_KILL) {
  583. int hw_rf_kill = 0;
  584. if (!(iwl_read32(priv, CSR_GP_CNTRL) &
  585. CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW))
  586. hw_rf_kill = 1;
  587. IWL_WARN(priv, "RF_KILL bit toggled to %s.\n",
  588. hw_rf_kill ? "disable radio" : "enable radio");
  589. priv->isr_stats.rfkill++;
  590. /* driver only loads ucode once setting the interface up.
  591. * the driver allows loading the ucode even if the radio
  592. * is killed. Hence update the killswitch state here. The
  593. * rfkill handler will care about restarting if needed.
  594. */
  595. if (!test_bit(STATUS_ALIVE, &priv->status)) {
  596. if (hw_rf_kill)
  597. set_bit(STATUS_RF_KILL_HW, &priv->status);
  598. else
  599. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  600. wiphy_rfkill_set_hw_state(priv->hw->wiphy, hw_rf_kill);
  601. }
  602. handled |= CSR_INT_BIT_RF_KILL;
  603. }
  604. /* Chip got too hot and stopped itself */
  605. if (inta & CSR_INT_BIT_CT_KILL) {
  606. IWL_ERR(priv, "Microcode CT kill error detected.\n");
  607. priv->isr_stats.ctkill++;
  608. handled |= CSR_INT_BIT_CT_KILL;
  609. }
  610. /* Error detected by uCode */
  611. if (inta & CSR_INT_BIT_SW_ERR) {
  612. IWL_ERR(priv, "Microcode SW error detected. "
  613. " Restarting 0x%X.\n", inta);
  614. priv->isr_stats.sw++;
  615. iwl_irq_handle_error(priv);
  616. handled |= CSR_INT_BIT_SW_ERR;
  617. }
  618. /* uCode wakes up after power-down sleep */
  619. if (inta & CSR_INT_BIT_WAKEUP) {
  620. IWL_DEBUG_ISR(priv, "Wakeup interrupt\n");
  621. iwl_rx_queue_update_write_ptr(priv, &priv->rxq);
  622. for (i = 0; i < priv->hw_params.max_txq_num; i++)
  623. iwl_txq_update_write_ptr(priv, &priv->txq[i]);
  624. priv->isr_stats.wakeup++;
  625. handled |= CSR_INT_BIT_WAKEUP;
  626. }
  627. /* All uCode command responses, including Tx command responses,
  628. * Rx "responses" (frame-received notification), and other
  629. * notifications from uCode come through here*/
  630. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX |
  631. CSR_INT_BIT_RX_PERIODIC)) {
  632. IWL_DEBUG_ISR(priv, "Rx interrupt\n");
  633. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) {
  634. handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX);
  635. iwl_write32(priv, CSR_FH_INT_STATUS,
  636. CSR_FH_INT_RX_MASK);
  637. }
  638. if (inta & CSR_INT_BIT_RX_PERIODIC) {
  639. handled |= CSR_INT_BIT_RX_PERIODIC;
  640. iwl_write32(priv, CSR_INT, CSR_INT_BIT_RX_PERIODIC);
  641. }
  642. /* Sending RX interrupt require many steps to be done in the
  643. * the device:
  644. * 1- write interrupt to current index in ICT table.
  645. * 2- dma RX frame.
  646. * 3- update RX shared data to indicate last write index.
  647. * 4- send interrupt.
  648. * This could lead to RX race, driver could receive RX interrupt
  649. * but the shared data changes does not reflect this;
  650. * periodic interrupt will detect any dangling Rx activity.
  651. */
  652. /* Disable periodic interrupt; we use it as just a one-shot. */
  653. iwl_write8(priv, CSR_INT_PERIODIC_REG,
  654. CSR_INT_PERIODIC_DIS);
  655. iwl_rx_handle(priv);
  656. /*
  657. * Enable periodic interrupt in 8 msec only if we received
  658. * real RX interrupt (instead of just periodic int), to catch
  659. * any dangling Rx interrupt. If it was just the periodic
  660. * interrupt, there was no dangling Rx activity, and no need
  661. * to extend the periodic interrupt; one-shot is enough.
  662. */
  663. if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX))
  664. iwl_write8(priv, CSR_INT_PERIODIC_REG,
  665. CSR_INT_PERIODIC_ENA);
  666. priv->isr_stats.rx++;
  667. }
  668. /* This "Tx" DMA channel is used only for loading uCode */
  669. if (inta & CSR_INT_BIT_FH_TX) {
  670. iwl_write32(priv, CSR_FH_INT_STATUS, CSR_FH_INT_TX_MASK);
  671. IWL_DEBUG_ISR(priv, "uCode load interrupt\n");
  672. priv->isr_stats.tx++;
  673. handled |= CSR_INT_BIT_FH_TX;
  674. /* Wake up uCode load routine, now that load is complete */
  675. priv->ucode_write_complete = 1;
  676. wake_up_interruptible(&priv->wait_command_queue);
  677. }
  678. if (inta & ~handled) {
  679. IWL_ERR(priv, "Unhandled INTA bits 0x%08x\n", inta & ~handled);
  680. priv->isr_stats.unhandled++;
  681. }
  682. if (inta & ~(priv->inta_mask)) {
  683. IWL_WARN(priv, "Disabled INTA bits 0x%08x were pending\n",
  684. inta & ~priv->inta_mask);
  685. }
  686. /* Re-enable all interrupts */
  687. /* only Re-enable if disabled by irq */
  688. if (test_bit(STATUS_INT_ENABLED, &priv->status))
  689. iwl_enable_interrupts(priv);
  690. /* Re-enable RF_KILL if it occurred */
  691. else if (handled & CSR_INT_BIT_RF_KILL)
  692. iwl_enable_rfkill_int(priv);
  693. }
  694. /*****************************************************************************
  695. *
  696. * sysfs attributes
  697. *
  698. *****************************************************************************/
  699. #ifdef CONFIG_IWLWIFI_DEBUG
  700. /*
  701. * The following adds a new attribute to the sysfs representation
  702. * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/)
  703. * used for controlling the debug level.
  704. *
  705. * See the level definitions in iwl for details.
  706. *
  707. * The debug_level being managed using sysfs below is a per device debug
  708. * level that is used instead of the global debug level if it (the per
  709. * device debug level) is set.
  710. */
  711. static ssize_t show_debug_level(struct device *d,
  712. struct device_attribute *attr, char *buf)
  713. {
  714. struct iwl_priv *priv = dev_get_drvdata(d);
  715. return sprintf(buf, "0x%08X\n", iwl_get_debug_level(priv));
  716. }
  717. static ssize_t store_debug_level(struct device *d,
  718. struct device_attribute *attr,
  719. const char *buf, size_t count)
  720. {
  721. struct iwl_priv *priv = dev_get_drvdata(d);
  722. unsigned long val;
  723. int ret;
  724. ret = strict_strtoul(buf, 0, &val);
  725. if (ret)
  726. IWL_ERR(priv, "%s is not in hex or decimal form.\n", buf);
  727. else {
  728. priv->debug_level = val;
  729. if (iwl_alloc_traffic_mem(priv))
  730. IWL_ERR(priv,
  731. "Not enough memory to generate traffic log\n");
  732. }
  733. return strnlen(buf, count);
  734. }
  735. static DEVICE_ATTR(debug_level, S_IWUSR | S_IRUGO,
  736. show_debug_level, store_debug_level);
  737. #endif /* CONFIG_IWLWIFI_DEBUG */
  738. static ssize_t show_temperature(struct device *d,
  739. struct device_attribute *attr, char *buf)
  740. {
  741. struct iwl_priv *priv = dev_get_drvdata(d);
  742. if (!iwl_is_alive(priv))
  743. return -EAGAIN;
  744. return sprintf(buf, "%d\n", priv->temperature);
  745. }
  746. static DEVICE_ATTR(temperature, S_IRUGO, show_temperature, NULL);
  747. static ssize_t show_tx_power(struct device *d,
  748. struct device_attribute *attr, char *buf)
  749. {
  750. struct iwl_priv *priv = dev_get_drvdata(d);
  751. if (!iwl_is_ready_rf(priv))
  752. return sprintf(buf, "off\n");
  753. else
  754. return sprintf(buf, "%d\n", priv->tx_power_user_lmt);
  755. }
  756. static ssize_t store_tx_power(struct device *d,
  757. struct device_attribute *attr,
  758. const char *buf, size_t count)
  759. {
  760. struct iwl_priv *priv = dev_get_drvdata(d);
  761. unsigned long val;
  762. int ret;
  763. ret = strict_strtoul(buf, 10, &val);
  764. if (ret)
  765. IWL_INFO(priv, "%s is not in decimal form.\n", buf);
  766. else {
  767. ret = iwl_set_tx_power(priv, val, false);
  768. if (ret)
  769. IWL_ERR(priv, "failed setting tx power (0x%d).\n",
  770. ret);
  771. else
  772. ret = count;
  773. }
  774. return ret;
  775. }
  776. static DEVICE_ATTR(tx_power, S_IWUSR | S_IRUGO, show_tx_power, store_tx_power);
  777. static struct attribute *iwl_sysfs_entries[] = {
  778. &dev_attr_temperature.attr,
  779. &dev_attr_tx_power.attr,
  780. #ifdef CONFIG_IWLWIFI_DEBUG
  781. &dev_attr_debug_level.attr,
  782. #endif
  783. NULL
  784. };
  785. static struct attribute_group iwl_attribute_group = {
  786. .name = NULL, /* put in device directory */
  787. .attrs = iwl_sysfs_entries,
  788. };
  789. /******************************************************************************
  790. *
  791. * uCode download functions
  792. *
  793. ******************************************************************************/
  794. static void iwl_free_fw_desc(struct pci_dev *pci_dev, struct fw_desc *desc)
  795. {
  796. if (desc->v_addr)
  797. dma_free_coherent(&pci_dev->dev, desc->len,
  798. desc->v_addr, desc->p_addr);
  799. desc->v_addr = NULL;
  800. desc->len = 0;
  801. }
  802. static void iwl_free_fw_img(struct pci_dev *pci_dev, struct fw_img *img)
  803. {
  804. iwl_free_fw_desc(pci_dev, &img->code);
  805. iwl_free_fw_desc(pci_dev, &img->data);
  806. }
  807. static int iwl_alloc_fw_desc(struct pci_dev *pci_dev, struct fw_desc *desc,
  808. const void *data, size_t len)
  809. {
  810. if (!len) {
  811. desc->v_addr = NULL;
  812. return -EINVAL;
  813. }
  814. desc->v_addr = dma_alloc_coherent(&pci_dev->dev, len,
  815. &desc->p_addr, GFP_KERNEL);
  816. if (!desc->v_addr)
  817. return -ENOMEM;
  818. desc->len = len;
  819. memcpy(desc->v_addr, data, len);
  820. return 0;
  821. }
  822. static void iwl_dealloc_ucode_pci(struct iwl_priv *priv)
  823. {
  824. iwl_free_fw_img(priv->pci_dev, &priv->ucode_rt);
  825. iwl_free_fw_img(priv->pci_dev, &priv->ucode_init);
  826. }
  827. struct iwlagn_ucode_capabilities {
  828. u32 max_probe_length;
  829. u32 standard_phy_calibration_size;
  830. u32 flags;
  831. };
  832. static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context);
  833. static int iwl_mac_setup_register(struct iwl_priv *priv,
  834. struct iwlagn_ucode_capabilities *capa);
  835. #define UCODE_EXPERIMENTAL_INDEX 100
  836. #define UCODE_EXPERIMENTAL_TAG "exp"
  837. static int __must_check iwl_request_firmware(struct iwl_priv *priv, bool first)
  838. {
  839. const char *name_pre = priv->cfg->fw_name_pre;
  840. char tag[8];
  841. if (first) {
  842. #ifdef CONFIG_IWLWIFI_DEBUG_EXPERIMENTAL_UCODE
  843. priv->fw_index = UCODE_EXPERIMENTAL_INDEX;
  844. strcpy(tag, UCODE_EXPERIMENTAL_TAG);
  845. } else if (priv->fw_index == UCODE_EXPERIMENTAL_INDEX) {
  846. #endif
  847. priv->fw_index = priv->cfg->ucode_api_max;
  848. sprintf(tag, "%d", priv->fw_index);
  849. } else {
  850. priv->fw_index--;
  851. sprintf(tag, "%d", priv->fw_index);
  852. }
  853. if (priv->fw_index < priv->cfg->ucode_api_min) {
  854. IWL_ERR(priv, "no suitable firmware found!\n");
  855. return -ENOENT;
  856. }
  857. sprintf(priv->firmware_name, "%s%s%s", name_pre, tag, ".ucode");
  858. IWL_DEBUG_INFO(priv, "attempting to load firmware %s'%s'\n",
  859. (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
  860. ? "EXPERIMENTAL " : "",
  861. priv->firmware_name);
  862. return request_firmware_nowait(THIS_MODULE, 1, priv->firmware_name,
  863. &priv->pci_dev->dev, GFP_KERNEL, priv,
  864. iwl_ucode_callback);
  865. }
  866. struct iwlagn_firmware_pieces {
  867. const void *inst, *data, *init, *init_data;
  868. size_t inst_size, data_size, init_size, init_data_size;
  869. u32 build;
  870. u32 init_evtlog_ptr, init_evtlog_size, init_errlog_ptr;
  871. u32 inst_evtlog_ptr, inst_evtlog_size, inst_errlog_ptr;
  872. };
  873. static int iwlagn_load_legacy_firmware(struct iwl_priv *priv,
  874. const struct firmware *ucode_raw,
  875. struct iwlagn_firmware_pieces *pieces)
  876. {
  877. struct iwl_ucode_header *ucode = (void *)ucode_raw->data;
  878. u32 api_ver, hdr_size;
  879. const u8 *src;
  880. priv->ucode_ver = le32_to_cpu(ucode->ver);
  881. api_ver = IWL_UCODE_API(priv->ucode_ver);
  882. switch (api_ver) {
  883. default:
  884. hdr_size = 28;
  885. if (ucode_raw->size < hdr_size) {
  886. IWL_ERR(priv, "File size too small!\n");
  887. return -EINVAL;
  888. }
  889. pieces->build = le32_to_cpu(ucode->u.v2.build);
  890. pieces->inst_size = le32_to_cpu(ucode->u.v2.inst_size);
  891. pieces->data_size = le32_to_cpu(ucode->u.v2.data_size);
  892. pieces->init_size = le32_to_cpu(ucode->u.v2.init_size);
  893. pieces->init_data_size = le32_to_cpu(ucode->u.v2.init_data_size);
  894. src = ucode->u.v2.data;
  895. break;
  896. case 0:
  897. case 1:
  898. case 2:
  899. hdr_size = 24;
  900. if (ucode_raw->size < hdr_size) {
  901. IWL_ERR(priv, "File size too small!\n");
  902. return -EINVAL;
  903. }
  904. pieces->build = 0;
  905. pieces->inst_size = le32_to_cpu(ucode->u.v1.inst_size);
  906. pieces->data_size = le32_to_cpu(ucode->u.v1.data_size);
  907. pieces->init_size = le32_to_cpu(ucode->u.v1.init_size);
  908. pieces->init_data_size = le32_to_cpu(ucode->u.v1.init_data_size);
  909. src = ucode->u.v1.data;
  910. break;
  911. }
  912. /* Verify size of file vs. image size info in file's header */
  913. if (ucode_raw->size != hdr_size + pieces->inst_size +
  914. pieces->data_size + pieces->init_size +
  915. pieces->init_data_size) {
  916. IWL_ERR(priv,
  917. "uCode file size %d does not match expected size\n",
  918. (int)ucode_raw->size);
  919. return -EINVAL;
  920. }
  921. pieces->inst = src;
  922. src += pieces->inst_size;
  923. pieces->data = src;
  924. src += pieces->data_size;
  925. pieces->init = src;
  926. src += pieces->init_size;
  927. pieces->init_data = src;
  928. src += pieces->init_data_size;
  929. return 0;
  930. }
  931. static int iwlagn_wanted_ucode_alternative = 1;
  932. static int iwlagn_load_firmware(struct iwl_priv *priv,
  933. const struct firmware *ucode_raw,
  934. struct iwlagn_firmware_pieces *pieces,
  935. struct iwlagn_ucode_capabilities *capa)
  936. {
  937. struct iwl_tlv_ucode_header *ucode = (void *)ucode_raw->data;
  938. struct iwl_ucode_tlv *tlv;
  939. size_t len = ucode_raw->size;
  940. const u8 *data;
  941. int wanted_alternative = iwlagn_wanted_ucode_alternative, tmp;
  942. u64 alternatives;
  943. u32 tlv_len;
  944. enum iwl_ucode_tlv_type tlv_type;
  945. const u8 *tlv_data;
  946. if (len < sizeof(*ucode)) {
  947. IWL_ERR(priv, "uCode has invalid length: %zd\n", len);
  948. return -EINVAL;
  949. }
  950. if (ucode->magic != cpu_to_le32(IWL_TLV_UCODE_MAGIC)) {
  951. IWL_ERR(priv, "invalid uCode magic: 0X%x\n",
  952. le32_to_cpu(ucode->magic));
  953. return -EINVAL;
  954. }
  955. /*
  956. * Check which alternatives are present, and "downgrade"
  957. * when the chosen alternative is not present, warning
  958. * the user when that happens. Some files may not have
  959. * any alternatives, so don't warn in that case.
  960. */
  961. alternatives = le64_to_cpu(ucode->alternatives);
  962. tmp = wanted_alternative;
  963. if (wanted_alternative > 63)
  964. wanted_alternative = 63;
  965. while (wanted_alternative && !(alternatives & BIT(wanted_alternative)))
  966. wanted_alternative--;
  967. if (wanted_alternative && wanted_alternative != tmp)
  968. IWL_WARN(priv,
  969. "uCode alternative %d not available, choosing %d\n",
  970. tmp, wanted_alternative);
  971. priv->ucode_ver = le32_to_cpu(ucode->ver);
  972. pieces->build = le32_to_cpu(ucode->build);
  973. data = ucode->data;
  974. len -= sizeof(*ucode);
  975. while (len >= sizeof(*tlv)) {
  976. u16 tlv_alt;
  977. len -= sizeof(*tlv);
  978. tlv = (void *)data;
  979. tlv_len = le32_to_cpu(tlv->length);
  980. tlv_type = le16_to_cpu(tlv->type);
  981. tlv_alt = le16_to_cpu(tlv->alternative);
  982. tlv_data = tlv->data;
  983. if (len < tlv_len) {
  984. IWL_ERR(priv, "invalid TLV len: %zd/%u\n",
  985. len, tlv_len);
  986. return -EINVAL;
  987. }
  988. len -= ALIGN(tlv_len, 4);
  989. data += sizeof(*tlv) + ALIGN(tlv_len, 4);
  990. /*
  991. * Alternative 0 is always valid.
  992. *
  993. * Skip alternative TLVs that are not selected.
  994. */
  995. if (tlv_alt != 0 && tlv_alt != wanted_alternative)
  996. continue;
  997. switch (tlv_type) {
  998. case IWL_UCODE_TLV_INST:
  999. pieces->inst = tlv_data;
  1000. pieces->inst_size = tlv_len;
  1001. break;
  1002. case IWL_UCODE_TLV_DATA:
  1003. pieces->data = tlv_data;
  1004. pieces->data_size = tlv_len;
  1005. break;
  1006. case IWL_UCODE_TLV_INIT:
  1007. pieces->init = tlv_data;
  1008. pieces->init_size = tlv_len;
  1009. break;
  1010. case IWL_UCODE_TLV_INIT_DATA:
  1011. pieces->init_data = tlv_data;
  1012. pieces->init_data_size = tlv_len;
  1013. break;
  1014. case IWL_UCODE_TLV_BOOT:
  1015. IWL_ERR(priv, "Found unexpected BOOT ucode\n");
  1016. break;
  1017. case IWL_UCODE_TLV_PROBE_MAX_LEN:
  1018. if (tlv_len != sizeof(u32))
  1019. goto invalid_tlv_len;
  1020. capa->max_probe_length =
  1021. le32_to_cpup((__le32 *)tlv_data);
  1022. break;
  1023. case IWL_UCODE_TLV_PAN:
  1024. if (tlv_len)
  1025. goto invalid_tlv_len;
  1026. capa->flags |= IWL_UCODE_TLV_FLAGS_PAN;
  1027. break;
  1028. case IWL_UCODE_TLV_FLAGS:
  1029. /* must be at least one u32 */
  1030. if (tlv_len < sizeof(u32))
  1031. goto invalid_tlv_len;
  1032. /* and a proper number of u32s */
  1033. if (tlv_len % sizeof(u32))
  1034. goto invalid_tlv_len;
  1035. /*
  1036. * This driver only reads the first u32 as
  1037. * right now no more features are defined,
  1038. * if that changes then either the driver
  1039. * will not work with the new firmware, or
  1040. * it'll not take advantage of new features.
  1041. */
  1042. capa->flags = le32_to_cpup((__le32 *)tlv_data);
  1043. break;
  1044. case IWL_UCODE_TLV_INIT_EVTLOG_PTR:
  1045. if (tlv_len != sizeof(u32))
  1046. goto invalid_tlv_len;
  1047. pieces->init_evtlog_ptr =
  1048. le32_to_cpup((__le32 *)tlv_data);
  1049. break;
  1050. case IWL_UCODE_TLV_INIT_EVTLOG_SIZE:
  1051. if (tlv_len != sizeof(u32))
  1052. goto invalid_tlv_len;
  1053. pieces->init_evtlog_size =
  1054. le32_to_cpup((__le32 *)tlv_data);
  1055. break;
  1056. case IWL_UCODE_TLV_INIT_ERRLOG_PTR:
  1057. if (tlv_len != sizeof(u32))
  1058. goto invalid_tlv_len;
  1059. pieces->init_errlog_ptr =
  1060. le32_to_cpup((__le32 *)tlv_data);
  1061. break;
  1062. case IWL_UCODE_TLV_RUNT_EVTLOG_PTR:
  1063. if (tlv_len != sizeof(u32))
  1064. goto invalid_tlv_len;
  1065. pieces->inst_evtlog_ptr =
  1066. le32_to_cpup((__le32 *)tlv_data);
  1067. break;
  1068. case IWL_UCODE_TLV_RUNT_EVTLOG_SIZE:
  1069. if (tlv_len != sizeof(u32))
  1070. goto invalid_tlv_len;
  1071. pieces->inst_evtlog_size =
  1072. le32_to_cpup((__le32 *)tlv_data);
  1073. break;
  1074. case IWL_UCODE_TLV_RUNT_ERRLOG_PTR:
  1075. if (tlv_len != sizeof(u32))
  1076. goto invalid_tlv_len;
  1077. pieces->inst_errlog_ptr =
  1078. le32_to_cpup((__le32 *)tlv_data);
  1079. break;
  1080. case IWL_UCODE_TLV_ENHANCE_SENS_TBL:
  1081. if (tlv_len)
  1082. goto invalid_tlv_len;
  1083. priv->enhance_sensitivity_table = true;
  1084. break;
  1085. case IWL_UCODE_TLV_PHY_CALIBRATION_SIZE:
  1086. if (tlv_len != sizeof(u32))
  1087. goto invalid_tlv_len;
  1088. capa->standard_phy_calibration_size =
  1089. le32_to_cpup((__le32 *)tlv_data);
  1090. break;
  1091. default:
  1092. IWL_DEBUG_INFO(priv, "unknown TLV: %d\n", tlv_type);
  1093. break;
  1094. }
  1095. }
  1096. if (len) {
  1097. IWL_ERR(priv, "invalid TLV after parsing: %zd\n", len);
  1098. iwl_print_hex_dump(priv, IWL_DL_FW, (u8 *)data, len);
  1099. return -EINVAL;
  1100. }
  1101. return 0;
  1102. invalid_tlv_len:
  1103. IWL_ERR(priv, "TLV %d has invalid size: %u\n", tlv_type, tlv_len);
  1104. iwl_print_hex_dump(priv, IWL_DL_FW, tlv_data, tlv_len);
  1105. return -EINVAL;
  1106. }
  1107. /**
  1108. * iwl_ucode_callback - callback when firmware was loaded
  1109. *
  1110. * If loaded successfully, copies the firmware into buffers
  1111. * for the card to fetch (via DMA).
  1112. */
  1113. static void iwl_ucode_callback(const struct firmware *ucode_raw, void *context)
  1114. {
  1115. struct iwl_priv *priv = context;
  1116. struct iwl_ucode_header *ucode;
  1117. int err;
  1118. struct iwlagn_firmware_pieces pieces;
  1119. const unsigned int api_max = priv->cfg->ucode_api_max;
  1120. const unsigned int api_min = priv->cfg->ucode_api_min;
  1121. u32 api_ver;
  1122. char buildstr[25];
  1123. u32 build;
  1124. struct iwlagn_ucode_capabilities ucode_capa = {
  1125. .max_probe_length = 200,
  1126. .standard_phy_calibration_size =
  1127. IWL_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE,
  1128. };
  1129. memset(&pieces, 0, sizeof(pieces));
  1130. if (!ucode_raw) {
  1131. if (priv->fw_index <= priv->cfg->ucode_api_max)
  1132. IWL_ERR(priv,
  1133. "request for firmware file '%s' failed.\n",
  1134. priv->firmware_name);
  1135. goto try_again;
  1136. }
  1137. IWL_DEBUG_INFO(priv, "Loaded firmware file '%s' (%zd bytes).\n",
  1138. priv->firmware_name, ucode_raw->size);
  1139. /* Make sure that we got at least the API version number */
  1140. if (ucode_raw->size < 4) {
  1141. IWL_ERR(priv, "File size way too small!\n");
  1142. goto try_again;
  1143. }
  1144. /* Data from ucode file: header followed by uCode images */
  1145. ucode = (struct iwl_ucode_header *)ucode_raw->data;
  1146. if (ucode->ver)
  1147. err = iwlagn_load_legacy_firmware(priv, ucode_raw, &pieces);
  1148. else
  1149. err = iwlagn_load_firmware(priv, ucode_raw, &pieces,
  1150. &ucode_capa);
  1151. if (err)
  1152. goto try_again;
  1153. api_ver = IWL_UCODE_API(priv->ucode_ver);
  1154. build = pieces.build;
  1155. /*
  1156. * api_ver should match the api version forming part of the
  1157. * firmware filename ... but we don't check for that and only rely
  1158. * on the API version read from firmware header from here on forward
  1159. */
  1160. /* no api version check required for experimental uCode */
  1161. if (priv->fw_index != UCODE_EXPERIMENTAL_INDEX) {
  1162. if (api_ver < api_min || api_ver > api_max) {
  1163. IWL_ERR(priv,
  1164. "Driver unable to support your firmware API. "
  1165. "Driver supports v%u, firmware is v%u.\n",
  1166. api_max, api_ver);
  1167. goto try_again;
  1168. }
  1169. if (api_ver != api_max)
  1170. IWL_ERR(priv,
  1171. "Firmware has old API version. Expected v%u, "
  1172. "got v%u. New firmware can be obtained "
  1173. "from http://www.intellinuxwireless.org.\n",
  1174. api_max, api_ver);
  1175. }
  1176. if (build)
  1177. sprintf(buildstr, " build %u%s", build,
  1178. (priv->fw_index == UCODE_EXPERIMENTAL_INDEX)
  1179. ? " (EXP)" : "");
  1180. else
  1181. buildstr[0] = '\0';
  1182. IWL_INFO(priv, "loaded firmware version %u.%u.%u.%u%s\n",
  1183. IWL_UCODE_MAJOR(priv->ucode_ver),
  1184. IWL_UCODE_MINOR(priv->ucode_ver),
  1185. IWL_UCODE_API(priv->ucode_ver),
  1186. IWL_UCODE_SERIAL(priv->ucode_ver),
  1187. buildstr);
  1188. snprintf(priv->hw->wiphy->fw_version,
  1189. sizeof(priv->hw->wiphy->fw_version),
  1190. "%u.%u.%u.%u%s",
  1191. IWL_UCODE_MAJOR(priv->ucode_ver),
  1192. IWL_UCODE_MINOR(priv->ucode_ver),
  1193. IWL_UCODE_API(priv->ucode_ver),
  1194. IWL_UCODE_SERIAL(priv->ucode_ver),
  1195. buildstr);
  1196. /*
  1197. * For any of the failures below (before allocating pci memory)
  1198. * we will try to load a version with a smaller API -- maybe the
  1199. * user just got a corrupted version of the latest API.
  1200. */
  1201. IWL_DEBUG_INFO(priv, "f/w package hdr ucode version raw = 0x%x\n",
  1202. priv->ucode_ver);
  1203. IWL_DEBUG_INFO(priv, "f/w package hdr runtime inst size = %Zd\n",
  1204. pieces.inst_size);
  1205. IWL_DEBUG_INFO(priv, "f/w package hdr runtime data size = %Zd\n",
  1206. pieces.data_size);
  1207. IWL_DEBUG_INFO(priv, "f/w package hdr init inst size = %Zd\n",
  1208. pieces.init_size);
  1209. IWL_DEBUG_INFO(priv, "f/w package hdr init data size = %Zd\n",
  1210. pieces.init_data_size);
  1211. /* Verify that uCode images will fit in card's SRAM */
  1212. if (pieces.inst_size > priv->hw_params.max_inst_size) {
  1213. IWL_ERR(priv, "uCode instr len %Zd too large to fit in\n",
  1214. pieces.inst_size);
  1215. goto try_again;
  1216. }
  1217. if (pieces.data_size > priv->hw_params.max_data_size) {
  1218. IWL_ERR(priv, "uCode data len %Zd too large to fit in\n",
  1219. pieces.data_size);
  1220. goto try_again;
  1221. }
  1222. if (pieces.init_size > priv->hw_params.max_inst_size) {
  1223. IWL_ERR(priv, "uCode init instr len %Zd too large to fit in\n",
  1224. pieces.init_size);
  1225. goto try_again;
  1226. }
  1227. if (pieces.init_data_size > priv->hw_params.max_data_size) {
  1228. IWL_ERR(priv, "uCode init data len %Zd too large to fit in\n",
  1229. pieces.init_data_size);
  1230. goto try_again;
  1231. }
  1232. /* Allocate ucode buffers for card's bus-master loading ... */
  1233. /* Runtime instructions and 2 copies of data:
  1234. * 1) unmodified from disk
  1235. * 2) backup cache for save/restore during power-downs */
  1236. if (iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_rt.code,
  1237. pieces.inst, pieces.inst_size))
  1238. goto err_pci_alloc;
  1239. if (iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_rt.data,
  1240. pieces.data, pieces.data_size))
  1241. goto err_pci_alloc;
  1242. /* Initialization instructions and data */
  1243. if (pieces.init_size && pieces.init_data_size) {
  1244. if (iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init.code,
  1245. pieces.init, pieces.init_size))
  1246. goto err_pci_alloc;
  1247. if (iwl_alloc_fw_desc(priv->pci_dev, &priv->ucode_init.data,
  1248. pieces.init_data, pieces.init_data_size))
  1249. goto err_pci_alloc;
  1250. }
  1251. /* Now that we can no longer fail, copy information */
  1252. /*
  1253. * The (size - 16) / 12 formula is based on the information recorded
  1254. * for each event, which is of mode 1 (including timestamp) for all
  1255. * new microcodes that include this information.
  1256. */
  1257. priv->_agn.init_evtlog_ptr = pieces.init_evtlog_ptr;
  1258. if (pieces.init_evtlog_size)
  1259. priv->_agn.init_evtlog_size = (pieces.init_evtlog_size - 16)/12;
  1260. else
  1261. priv->_agn.init_evtlog_size =
  1262. priv->cfg->base_params->max_event_log_size;
  1263. priv->_agn.init_errlog_ptr = pieces.init_errlog_ptr;
  1264. priv->_agn.inst_evtlog_ptr = pieces.inst_evtlog_ptr;
  1265. if (pieces.inst_evtlog_size)
  1266. priv->_agn.inst_evtlog_size = (pieces.inst_evtlog_size - 16)/12;
  1267. else
  1268. priv->_agn.inst_evtlog_size =
  1269. priv->cfg->base_params->max_event_log_size;
  1270. priv->_agn.inst_errlog_ptr = pieces.inst_errlog_ptr;
  1271. priv->new_scan_threshold_behaviour =
  1272. !!(ucode_capa.flags & IWL_UCODE_TLV_FLAGS_NEWSCAN);
  1273. if ((priv->cfg->sku & EEPROM_SKU_CAP_IPAN_ENABLE) &&
  1274. (ucode_capa.flags & IWL_UCODE_TLV_FLAGS_PAN)) {
  1275. priv->valid_contexts |= BIT(IWL_RXON_CTX_PAN);
  1276. priv->sta_key_max_num = STA_KEY_MAX_NUM_PAN;
  1277. } else
  1278. priv->sta_key_max_num = STA_KEY_MAX_NUM;
  1279. if (priv->valid_contexts != BIT(IWL_RXON_CTX_BSS))
  1280. priv->cmd_queue = IWL_IPAN_CMD_QUEUE_NUM;
  1281. else
  1282. priv->cmd_queue = IWL_DEFAULT_CMD_QUEUE_NUM;
  1283. /*
  1284. * figure out the offset of chain noise reset and gain commands
  1285. * base on the size of standard phy calibration commands table size
  1286. */
  1287. if (ucode_capa.standard_phy_calibration_size >
  1288. IWL_MAX_PHY_CALIBRATE_TBL_SIZE)
  1289. ucode_capa.standard_phy_calibration_size =
  1290. IWL_MAX_STANDARD_PHY_CALIBRATE_TBL_SIZE;
  1291. priv->_agn.phy_calib_chain_noise_reset_cmd =
  1292. ucode_capa.standard_phy_calibration_size;
  1293. priv->_agn.phy_calib_chain_noise_gain_cmd =
  1294. ucode_capa.standard_phy_calibration_size + 1;
  1295. /**************************************************
  1296. * This is still part of probe() in a sense...
  1297. *
  1298. * 9. Setup and register with mac80211 and debugfs
  1299. **************************************************/
  1300. err = iwl_mac_setup_register(priv, &ucode_capa);
  1301. if (err)
  1302. goto out_unbind;
  1303. err = iwl_dbgfs_register(priv, DRV_NAME);
  1304. if (err)
  1305. IWL_ERR(priv, "failed to create debugfs files. Ignoring error: %d\n", err);
  1306. err = sysfs_create_group(&priv->pci_dev->dev.kobj,
  1307. &iwl_attribute_group);
  1308. if (err) {
  1309. IWL_ERR(priv, "failed to create sysfs device attributes\n");
  1310. goto out_unbind;
  1311. }
  1312. /* We have our copies now, allow OS release its copies */
  1313. release_firmware(ucode_raw);
  1314. complete(&priv->_agn.firmware_loading_complete);
  1315. return;
  1316. try_again:
  1317. /* try next, if any */
  1318. if (iwl_request_firmware(priv, false))
  1319. goto out_unbind;
  1320. release_firmware(ucode_raw);
  1321. return;
  1322. err_pci_alloc:
  1323. IWL_ERR(priv, "failed to allocate pci memory\n");
  1324. iwl_dealloc_ucode_pci(priv);
  1325. out_unbind:
  1326. complete(&priv->_agn.firmware_loading_complete);
  1327. device_release_driver(&priv->pci_dev->dev);
  1328. release_firmware(ucode_raw);
  1329. }
  1330. static const char *desc_lookup_text[] = {
  1331. "OK",
  1332. "FAIL",
  1333. "BAD_PARAM",
  1334. "BAD_CHECKSUM",
  1335. "NMI_INTERRUPT_WDG",
  1336. "SYSASSERT",
  1337. "FATAL_ERROR",
  1338. "BAD_COMMAND",
  1339. "HW_ERROR_TUNE_LOCK",
  1340. "HW_ERROR_TEMPERATURE",
  1341. "ILLEGAL_CHAN_FREQ",
  1342. "VCC_NOT_STABLE",
  1343. "FH_ERROR",
  1344. "NMI_INTERRUPT_HOST",
  1345. "NMI_INTERRUPT_ACTION_PT",
  1346. "NMI_INTERRUPT_UNKNOWN",
  1347. "UCODE_VERSION_MISMATCH",
  1348. "HW_ERROR_ABS_LOCK",
  1349. "HW_ERROR_CAL_LOCK_FAIL",
  1350. "NMI_INTERRUPT_INST_ACTION_PT",
  1351. "NMI_INTERRUPT_DATA_ACTION_PT",
  1352. "NMI_TRM_HW_ER",
  1353. "NMI_INTERRUPT_TRM",
  1354. "NMI_INTERRUPT_BREAK_POINT"
  1355. "DEBUG_0",
  1356. "DEBUG_1",
  1357. "DEBUG_2",
  1358. "DEBUG_3",
  1359. };
  1360. static struct { char *name; u8 num; } advanced_lookup[] = {
  1361. { "NMI_INTERRUPT_WDG", 0x34 },
  1362. { "SYSASSERT", 0x35 },
  1363. { "UCODE_VERSION_MISMATCH", 0x37 },
  1364. { "BAD_COMMAND", 0x38 },
  1365. { "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C },
  1366. { "FATAL_ERROR", 0x3D },
  1367. { "NMI_TRM_HW_ERR", 0x46 },
  1368. { "NMI_INTERRUPT_TRM", 0x4C },
  1369. { "NMI_INTERRUPT_BREAK_POINT", 0x54 },
  1370. { "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C },
  1371. { "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64 },
  1372. { "NMI_INTERRUPT_HOST", 0x66 },
  1373. { "NMI_INTERRUPT_ACTION_PT", 0x7C },
  1374. { "NMI_INTERRUPT_UNKNOWN", 0x84 },
  1375. { "NMI_INTERRUPT_INST_ACTION_PT", 0x86 },
  1376. { "ADVANCED_SYSASSERT", 0 },
  1377. };
  1378. static const char *desc_lookup(u32 num)
  1379. {
  1380. int i;
  1381. int max = ARRAY_SIZE(desc_lookup_text);
  1382. if (num < max)
  1383. return desc_lookup_text[num];
  1384. max = ARRAY_SIZE(advanced_lookup) - 1;
  1385. for (i = 0; i < max; i++) {
  1386. if (advanced_lookup[i].num == num)
  1387. break;
  1388. }
  1389. return advanced_lookup[i].name;
  1390. }
  1391. #define ERROR_START_OFFSET (1 * sizeof(u32))
  1392. #define ERROR_ELEM_SIZE (7 * sizeof(u32))
  1393. void iwl_dump_nic_error_log(struct iwl_priv *priv)
  1394. {
  1395. u32 base;
  1396. struct iwl_error_event_table table;
  1397. base = priv->device_pointers.error_event_table;
  1398. if (priv->ucode_type == IWL_UCODE_INIT) {
  1399. if (!base)
  1400. base = priv->_agn.init_errlog_ptr;
  1401. } else {
  1402. if (!base)
  1403. base = priv->_agn.inst_errlog_ptr;
  1404. }
  1405. if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  1406. IWL_ERR(priv,
  1407. "Not valid error log pointer 0x%08X for %s uCode\n",
  1408. base,
  1409. (priv->ucode_type == IWL_UCODE_INIT)
  1410. ? "Init" : "RT");
  1411. return;
  1412. }
  1413. iwl_read_targ_mem_words(priv, base, &table, sizeof(table));
  1414. if (ERROR_START_OFFSET <= table.valid * ERROR_ELEM_SIZE) {
  1415. IWL_ERR(priv, "Start IWL Error Log Dump:\n");
  1416. IWL_ERR(priv, "Status: 0x%08lX, count: %d\n",
  1417. priv->status, table.valid);
  1418. }
  1419. priv->isr_stats.err_code = table.error_id;
  1420. trace_iwlwifi_dev_ucode_error(priv, table.error_id, table.tsf_low,
  1421. table.data1, table.data2, table.line,
  1422. table.blink1, table.blink2, table.ilink1,
  1423. table.ilink2, table.bcon_time, table.gp1,
  1424. table.gp2, table.gp3, table.ucode_ver,
  1425. table.hw_ver, table.brd_ver);
  1426. IWL_ERR(priv, "0x%08X | %-28s\n", table.error_id,
  1427. desc_lookup(table.error_id));
  1428. IWL_ERR(priv, "0x%08X | uPc\n", table.pc);
  1429. IWL_ERR(priv, "0x%08X | branchlink1\n", table.blink1);
  1430. IWL_ERR(priv, "0x%08X | branchlink2\n", table.blink2);
  1431. IWL_ERR(priv, "0x%08X | interruptlink1\n", table.ilink1);
  1432. IWL_ERR(priv, "0x%08X | interruptlink2\n", table.ilink2);
  1433. IWL_ERR(priv, "0x%08X | data1\n", table.data1);
  1434. IWL_ERR(priv, "0x%08X | data2\n", table.data2);
  1435. IWL_ERR(priv, "0x%08X | line\n", table.line);
  1436. IWL_ERR(priv, "0x%08X | beacon time\n", table.bcon_time);
  1437. IWL_ERR(priv, "0x%08X | tsf low\n", table.tsf_low);
  1438. IWL_ERR(priv, "0x%08X | tsf hi\n", table.tsf_hi);
  1439. IWL_ERR(priv, "0x%08X | time gp1\n", table.gp1);
  1440. IWL_ERR(priv, "0x%08X | time gp2\n", table.gp2);
  1441. IWL_ERR(priv, "0x%08X | time gp3\n", table.gp3);
  1442. IWL_ERR(priv, "0x%08X | uCode version\n", table.ucode_ver);
  1443. IWL_ERR(priv, "0x%08X | hw version\n", table.hw_ver);
  1444. IWL_ERR(priv, "0x%08X | board version\n", table.brd_ver);
  1445. IWL_ERR(priv, "0x%08X | hcmd\n", table.hcmd);
  1446. }
  1447. #define EVENT_START_OFFSET (4 * sizeof(u32))
  1448. /**
  1449. * iwl_print_event_log - Dump error event log to syslog
  1450. *
  1451. */
  1452. static int iwl_print_event_log(struct iwl_priv *priv, u32 start_idx,
  1453. u32 num_events, u32 mode,
  1454. int pos, char **buf, size_t bufsz)
  1455. {
  1456. u32 i;
  1457. u32 base; /* SRAM byte address of event log header */
  1458. u32 event_size; /* 2 u32s, or 3 u32s if timestamp recorded */
  1459. u32 ptr; /* SRAM byte address of log data */
  1460. u32 ev, time, data; /* event log data */
  1461. unsigned long reg_flags;
  1462. if (num_events == 0)
  1463. return pos;
  1464. base = priv->device_pointers.log_event_table;
  1465. if (priv->ucode_type == IWL_UCODE_INIT) {
  1466. if (!base)
  1467. base = priv->_agn.init_evtlog_ptr;
  1468. } else {
  1469. if (!base)
  1470. base = priv->_agn.inst_evtlog_ptr;
  1471. }
  1472. if (mode == 0)
  1473. event_size = 2 * sizeof(u32);
  1474. else
  1475. event_size = 3 * sizeof(u32);
  1476. ptr = base + EVENT_START_OFFSET + (start_idx * event_size);
  1477. /* Make sure device is powered up for SRAM reads */
  1478. spin_lock_irqsave(&priv->reg_lock, reg_flags);
  1479. iwl_grab_nic_access(priv);
  1480. /* Set starting address; reads will auto-increment */
  1481. iwl_write32(priv, HBUS_TARG_MEM_RADDR, ptr);
  1482. rmb();
  1483. /* "time" is actually "data" for mode 0 (no timestamp).
  1484. * place event id # at far right for easier visual parsing. */
  1485. for (i = 0; i < num_events; i++) {
  1486. ev = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
  1487. time = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
  1488. if (mode == 0) {
  1489. /* data, ev */
  1490. if (bufsz) {
  1491. pos += scnprintf(*buf + pos, bufsz - pos,
  1492. "EVT_LOG:0x%08x:%04u\n",
  1493. time, ev);
  1494. } else {
  1495. trace_iwlwifi_dev_ucode_event(priv, 0,
  1496. time, ev);
  1497. IWL_ERR(priv, "EVT_LOG:0x%08x:%04u\n",
  1498. time, ev);
  1499. }
  1500. } else {
  1501. data = iwl_read32(priv, HBUS_TARG_MEM_RDAT);
  1502. if (bufsz) {
  1503. pos += scnprintf(*buf + pos, bufsz - pos,
  1504. "EVT_LOGT:%010u:0x%08x:%04u\n",
  1505. time, data, ev);
  1506. } else {
  1507. IWL_ERR(priv, "EVT_LOGT:%010u:0x%08x:%04u\n",
  1508. time, data, ev);
  1509. trace_iwlwifi_dev_ucode_event(priv, time,
  1510. data, ev);
  1511. }
  1512. }
  1513. }
  1514. /* Allow device to power down */
  1515. iwl_release_nic_access(priv);
  1516. spin_unlock_irqrestore(&priv->reg_lock, reg_flags);
  1517. return pos;
  1518. }
  1519. /**
  1520. * iwl_print_last_event_logs - Dump the newest # of event log to syslog
  1521. */
  1522. static int iwl_print_last_event_logs(struct iwl_priv *priv, u32 capacity,
  1523. u32 num_wraps, u32 next_entry,
  1524. u32 size, u32 mode,
  1525. int pos, char **buf, size_t bufsz)
  1526. {
  1527. /*
  1528. * display the newest DEFAULT_LOG_ENTRIES entries
  1529. * i.e the entries just before the next ont that uCode would fill.
  1530. */
  1531. if (num_wraps) {
  1532. if (next_entry < size) {
  1533. pos = iwl_print_event_log(priv,
  1534. capacity - (size - next_entry),
  1535. size - next_entry, mode,
  1536. pos, buf, bufsz);
  1537. pos = iwl_print_event_log(priv, 0,
  1538. next_entry, mode,
  1539. pos, buf, bufsz);
  1540. } else
  1541. pos = iwl_print_event_log(priv, next_entry - size,
  1542. size, mode, pos, buf, bufsz);
  1543. } else {
  1544. if (next_entry < size) {
  1545. pos = iwl_print_event_log(priv, 0, next_entry,
  1546. mode, pos, buf, bufsz);
  1547. } else {
  1548. pos = iwl_print_event_log(priv, next_entry - size,
  1549. size, mode, pos, buf, bufsz);
  1550. }
  1551. }
  1552. return pos;
  1553. }
  1554. #define DEFAULT_DUMP_EVENT_LOG_ENTRIES (20)
  1555. int iwl_dump_nic_event_log(struct iwl_priv *priv, bool full_log,
  1556. char **buf, bool display)
  1557. {
  1558. u32 base; /* SRAM byte address of event log header */
  1559. u32 capacity; /* event log capacity in # entries */
  1560. u32 mode; /* 0 - no timestamp, 1 - timestamp recorded */
  1561. u32 num_wraps; /* # times uCode wrapped to top of log */
  1562. u32 next_entry; /* index of next entry to be written by uCode */
  1563. u32 size; /* # entries that we'll print */
  1564. u32 logsize;
  1565. int pos = 0;
  1566. size_t bufsz = 0;
  1567. base = priv->device_pointers.log_event_table;
  1568. if (priv->ucode_type == IWL_UCODE_INIT) {
  1569. logsize = priv->_agn.init_evtlog_size;
  1570. if (!base)
  1571. base = priv->_agn.init_evtlog_ptr;
  1572. } else {
  1573. logsize = priv->_agn.inst_evtlog_size;
  1574. if (!base)
  1575. base = priv->_agn.inst_evtlog_ptr;
  1576. }
  1577. if (!priv->cfg->ops->lib->is_valid_rtc_data_addr(base)) {
  1578. IWL_ERR(priv,
  1579. "Invalid event log pointer 0x%08X for %s uCode\n",
  1580. base,
  1581. (priv->ucode_type == IWL_UCODE_INIT)
  1582. ? "Init" : "RT");
  1583. return -EINVAL;
  1584. }
  1585. /* event log header */
  1586. capacity = iwl_read_targ_mem(priv, base);
  1587. mode = iwl_read_targ_mem(priv, base + (1 * sizeof(u32)));
  1588. num_wraps = iwl_read_targ_mem(priv, base + (2 * sizeof(u32)));
  1589. next_entry = iwl_read_targ_mem(priv, base + (3 * sizeof(u32)));
  1590. if (capacity > logsize) {
  1591. IWL_ERR(priv, "Log capacity %d is bogus, limit to %d entries\n",
  1592. capacity, logsize);
  1593. capacity = logsize;
  1594. }
  1595. if (next_entry > logsize) {
  1596. IWL_ERR(priv, "Log write index %d is bogus, limit to %d\n",
  1597. next_entry, logsize);
  1598. next_entry = logsize;
  1599. }
  1600. size = num_wraps ? capacity : next_entry;
  1601. /* bail out if nothing in log */
  1602. if (size == 0) {
  1603. IWL_ERR(priv, "Start IWL Event Log Dump: nothing in log\n");
  1604. return pos;
  1605. }
  1606. /* enable/disable bt channel inhibition */
  1607. priv->bt_ch_announce = iwlagn_bt_ch_announce;
  1608. #ifdef CONFIG_IWLWIFI_DEBUG
  1609. if (!(iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) && !full_log)
  1610. size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
  1611. ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
  1612. #else
  1613. size = (size > DEFAULT_DUMP_EVENT_LOG_ENTRIES)
  1614. ? DEFAULT_DUMP_EVENT_LOG_ENTRIES : size;
  1615. #endif
  1616. IWL_ERR(priv, "Start IWL Event Log Dump: display last %u entries\n",
  1617. size);
  1618. #ifdef CONFIG_IWLWIFI_DEBUG
  1619. if (display) {
  1620. if (full_log)
  1621. bufsz = capacity * 48;
  1622. else
  1623. bufsz = size * 48;
  1624. *buf = kmalloc(bufsz, GFP_KERNEL);
  1625. if (!*buf)
  1626. return -ENOMEM;
  1627. }
  1628. if ((iwl_get_debug_level(priv) & IWL_DL_FW_ERRORS) || full_log) {
  1629. /*
  1630. * if uCode has wrapped back to top of log,
  1631. * start at the oldest entry,
  1632. * i.e the next one that uCode would fill.
  1633. */
  1634. if (num_wraps)
  1635. pos = iwl_print_event_log(priv, next_entry,
  1636. capacity - next_entry, mode,
  1637. pos, buf, bufsz);
  1638. /* (then/else) start at top of log */
  1639. pos = iwl_print_event_log(priv, 0,
  1640. next_entry, mode, pos, buf, bufsz);
  1641. } else
  1642. pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
  1643. next_entry, size, mode,
  1644. pos, buf, bufsz);
  1645. #else
  1646. pos = iwl_print_last_event_logs(priv, capacity, num_wraps,
  1647. next_entry, size, mode,
  1648. pos, buf, bufsz);
  1649. #endif
  1650. return pos;
  1651. }
  1652. static void iwl_rf_kill_ct_config(struct iwl_priv *priv)
  1653. {
  1654. struct iwl_ct_kill_config cmd;
  1655. struct iwl_ct_kill_throttling_config adv_cmd;
  1656. unsigned long flags;
  1657. int ret = 0;
  1658. spin_lock_irqsave(&priv->lock, flags);
  1659. iwl_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  1660. CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
  1661. spin_unlock_irqrestore(&priv->lock, flags);
  1662. priv->thermal_throttle.ct_kill_toggle = false;
  1663. if (priv->cfg->base_params->support_ct_kill_exit) {
  1664. adv_cmd.critical_temperature_enter =
  1665. cpu_to_le32(priv->hw_params.ct_kill_threshold);
  1666. adv_cmd.critical_temperature_exit =
  1667. cpu_to_le32(priv->hw_params.ct_kill_exit_threshold);
  1668. ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
  1669. sizeof(adv_cmd), &adv_cmd);
  1670. if (ret)
  1671. IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
  1672. else
  1673. IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
  1674. "succeeded, "
  1675. "critical temperature enter is %d,"
  1676. "exit is %d\n",
  1677. priv->hw_params.ct_kill_threshold,
  1678. priv->hw_params.ct_kill_exit_threshold);
  1679. } else {
  1680. cmd.critical_temperature_R =
  1681. cpu_to_le32(priv->hw_params.ct_kill_threshold);
  1682. ret = iwl_send_cmd_pdu(priv, REPLY_CT_KILL_CONFIG_CMD,
  1683. sizeof(cmd), &cmd);
  1684. if (ret)
  1685. IWL_ERR(priv, "REPLY_CT_KILL_CONFIG_CMD failed\n");
  1686. else
  1687. IWL_DEBUG_INFO(priv, "REPLY_CT_KILL_CONFIG_CMD "
  1688. "succeeded, "
  1689. "critical temperature is %d\n",
  1690. priv->hw_params.ct_kill_threshold);
  1691. }
  1692. }
  1693. static int iwlagn_send_calib_cfg_rt(struct iwl_priv *priv, u32 cfg)
  1694. {
  1695. struct iwl_calib_cfg_cmd calib_cfg_cmd;
  1696. struct iwl_host_cmd cmd = {
  1697. .id = CALIBRATION_CFG_CMD,
  1698. .len = { sizeof(struct iwl_calib_cfg_cmd), },
  1699. .data = { &calib_cfg_cmd, },
  1700. };
  1701. memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
  1702. calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
  1703. calib_cfg_cmd.ucd_calib_cfg.once.start = cpu_to_le32(cfg);
  1704. return iwl_send_cmd(priv, &cmd);
  1705. }
  1706. /**
  1707. * iwl_alive_start - called after REPLY_ALIVE notification received
  1708. * from protocol/runtime uCode (initialization uCode's
  1709. * Alive gets handled by iwl_init_alive_start()).
  1710. */
  1711. int iwl_alive_start(struct iwl_priv *priv)
  1712. {
  1713. int ret = 0;
  1714. struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  1715. iwl_reset_ict(priv);
  1716. IWL_DEBUG_INFO(priv, "Runtime Alive received.\n");
  1717. /* After the ALIVE response, we can send host commands to the uCode */
  1718. set_bit(STATUS_ALIVE, &priv->status);
  1719. /* Enable watchdog to monitor the driver tx queues */
  1720. iwl_setup_watchdog(priv);
  1721. if (iwl_is_rfkill(priv))
  1722. return -ERFKILL;
  1723. /* download priority table before any calibration request */
  1724. if (priv->cfg->bt_params &&
  1725. priv->cfg->bt_params->advanced_bt_coexist) {
  1726. /* Configure Bluetooth device coexistence support */
  1727. priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
  1728. priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
  1729. priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
  1730. priv->cfg->ops->hcmd->send_bt_config(priv);
  1731. priv->bt_valid = IWLAGN_BT_VALID_ENABLE_FLAGS;
  1732. iwlagn_send_prio_tbl(priv);
  1733. /* FIXME: w/a to force change uCode BT state machine */
  1734. ret = iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_OPEN,
  1735. BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
  1736. if (ret)
  1737. return ret;
  1738. ret = iwlagn_send_bt_env(priv, IWL_BT_COEX_ENV_CLOSE,
  1739. BT_COEX_PRIO_TBL_EVT_INIT_CALIB2);
  1740. if (ret)
  1741. return ret;
  1742. }
  1743. if (priv->hw_params.calib_rt_cfg)
  1744. iwlagn_send_calib_cfg_rt(priv, priv->hw_params.calib_rt_cfg);
  1745. ieee80211_wake_queues(priv->hw);
  1746. priv->active_rate = IWL_RATES_MASK;
  1747. /* Configure Tx antenna selection based on H/W config */
  1748. if (priv->cfg->ops->hcmd->set_tx_ant)
  1749. priv->cfg->ops->hcmd->set_tx_ant(priv, priv->cfg->valid_tx_ant);
  1750. if (iwl_is_associated_ctx(ctx)) {
  1751. struct iwl_rxon_cmd *active_rxon =
  1752. (struct iwl_rxon_cmd *)&ctx->active;
  1753. /* apply any changes in staging */
  1754. ctx->staging.filter_flags |= RXON_FILTER_ASSOC_MSK;
  1755. active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  1756. } else {
  1757. struct iwl_rxon_context *tmp;
  1758. /* Initialize our rx_config data */
  1759. for_each_context(priv, tmp)
  1760. iwl_connection_init_rx_config(priv, tmp);
  1761. if (priv->cfg->ops->hcmd->set_rxon_chain)
  1762. priv->cfg->ops->hcmd->set_rxon_chain(priv, ctx);
  1763. }
  1764. if (!priv->cfg->bt_params || (priv->cfg->bt_params &&
  1765. !priv->cfg->bt_params->advanced_bt_coexist)) {
  1766. /*
  1767. * default is 2-wire BT coexexistence support
  1768. */
  1769. priv->cfg->ops->hcmd->send_bt_config(priv);
  1770. }
  1771. iwl_reset_run_time_calib(priv);
  1772. set_bit(STATUS_READY, &priv->status);
  1773. /* Configure the adapter for unassociated operation */
  1774. ret = iwlagn_commit_rxon(priv, ctx);
  1775. if (ret)
  1776. return ret;
  1777. /* At this point, the NIC is initialized and operational */
  1778. iwl_rf_kill_ct_config(priv);
  1779. IWL_DEBUG_INFO(priv, "ALIVE processing complete.\n");
  1780. return iwl_power_update_mode(priv, true);
  1781. }
  1782. static void iwl_cancel_deferred_work(struct iwl_priv *priv);
  1783. static void __iwl_down(struct iwl_priv *priv)
  1784. {
  1785. int exit_pending;
  1786. IWL_DEBUG_INFO(priv, DRV_NAME " is going down\n");
  1787. iwl_scan_cancel_timeout(priv, 200);
  1788. exit_pending = test_and_set_bit(STATUS_EXIT_PENDING, &priv->status);
  1789. /* Stop TX queues watchdog. We need to have STATUS_EXIT_PENDING bit set
  1790. * to prevent rearm timer */
  1791. del_timer_sync(&priv->watchdog);
  1792. iwl_clear_ucode_stations(priv, NULL);
  1793. iwl_dealloc_bcast_stations(priv);
  1794. iwl_clear_driver_stations(priv);
  1795. /* reset BT coex data */
  1796. priv->bt_status = 0;
  1797. if (priv->cfg->bt_params)
  1798. priv->bt_traffic_load =
  1799. priv->cfg->bt_params->bt_init_traffic_load;
  1800. else
  1801. priv->bt_traffic_load = 0;
  1802. priv->bt_full_concurrent = false;
  1803. priv->bt_ci_compliance = 0;
  1804. /* Wipe out the EXIT_PENDING status bit if we are not actually
  1805. * exiting the module */
  1806. if (!exit_pending)
  1807. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  1808. if (priv->mac80211_registered)
  1809. ieee80211_stop_queues(priv->hw);
  1810. /* Clear out all status bits but a few that are stable across reset */
  1811. priv->status &= test_bit(STATUS_RF_KILL_HW, &priv->status) <<
  1812. STATUS_RF_KILL_HW |
  1813. test_bit(STATUS_GEO_CONFIGURED, &priv->status) <<
  1814. STATUS_GEO_CONFIGURED |
  1815. test_bit(STATUS_FW_ERROR, &priv->status) <<
  1816. STATUS_FW_ERROR |
  1817. test_bit(STATUS_EXIT_PENDING, &priv->status) <<
  1818. STATUS_EXIT_PENDING;
  1819. iwlagn_stop_device(priv);
  1820. dev_kfree_skb(priv->beacon_skb);
  1821. priv->beacon_skb = NULL;
  1822. }
  1823. static void iwl_down(struct iwl_priv *priv)
  1824. {
  1825. mutex_lock(&priv->mutex);
  1826. __iwl_down(priv);
  1827. mutex_unlock(&priv->mutex);
  1828. iwl_cancel_deferred_work(priv);
  1829. }
  1830. #define HW_READY_TIMEOUT (50)
  1831. /* Note: returns poll_bit return value, which is >= 0 if success */
  1832. static int iwl_set_hw_ready(struct iwl_priv *priv)
  1833. {
  1834. int ret;
  1835. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  1836. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
  1837. /* See if we got it */
  1838. ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
  1839. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
  1840. CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
  1841. HW_READY_TIMEOUT);
  1842. IWL_DEBUG_INFO(priv, "hardware%s ready\n", ret < 0 ? " not" : "");
  1843. return ret;
  1844. }
  1845. /* Note: returns standard 0/-ERROR code */
  1846. int iwl_prepare_card_hw(struct iwl_priv *priv)
  1847. {
  1848. int ret;
  1849. IWL_DEBUG_INFO(priv, "iwl_prepare_card_hw enter\n");
  1850. ret = iwl_set_hw_ready(priv);
  1851. if (ret >= 0)
  1852. return 0;
  1853. /* If HW is not ready, prepare the conditions to check again */
  1854. iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  1855. CSR_HW_IF_CONFIG_REG_PREPARE);
  1856. ret = iwl_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
  1857. ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE,
  1858. CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000);
  1859. if (ret < 0)
  1860. return ret;
  1861. /* HW should be ready by now, check again. */
  1862. ret = iwl_set_hw_ready(priv);
  1863. if (ret >= 0)
  1864. return 0;
  1865. return ret;
  1866. }
  1867. #define MAX_HW_RESTARTS 5
  1868. static int __iwl_up(struct iwl_priv *priv)
  1869. {
  1870. struct iwl_rxon_context *ctx;
  1871. int ret;
  1872. lockdep_assert_held(&priv->mutex);
  1873. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  1874. IWL_WARN(priv, "Exit pending; will not bring the NIC up\n");
  1875. return -EIO;
  1876. }
  1877. for_each_context(priv, ctx) {
  1878. ret = iwlagn_alloc_bcast_station(priv, ctx);
  1879. if (ret) {
  1880. iwl_dealloc_bcast_stations(priv);
  1881. return ret;
  1882. }
  1883. }
  1884. ret = iwlagn_run_init_ucode(priv);
  1885. if (ret) {
  1886. IWL_ERR(priv, "Failed to run INIT ucode: %d\n", ret);
  1887. goto error;
  1888. }
  1889. ret = iwlagn_load_ucode_wait_alive(priv,
  1890. &priv->ucode_rt,
  1891. IWL_UCODE_REGULAR);
  1892. if (ret) {
  1893. IWL_ERR(priv, "Failed to start RT ucode: %d\n", ret);
  1894. goto error;
  1895. }
  1896. ret = iwl_alive_start(priv);
  1897. if (ret)
  1898. goto error;
  1899. return 0;
  1900. error:
  1901. set_bit(STATUS_EXIT_PENDING, &priv->status);
  1902. __iwl_down(priv);
  1903. clear_bit(STATUS_EXIT_PENDING, &priv->status);
  1904. IWL_ERR(priv, "Unable to initialize device.\n");
  1905. return ret;
  1906. }
  1907. /*****************************************************************************
  1908. *
  1909. * Workqueue callbacks
  1910. *
  1911. *****************************************************************************/
  1912. static void iwl_bg_run_time_calib_work(struct work_struct *work)
  1913. {
  1914. struct iwl_priv *priv = container_of(work, struct iwl_priv,
  1915. run_time_calib_work);
  1916. mutex_lock(&priv->mutex);
  1917. if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
  1918. test_bit(STATUS_SCANNING, &priv->status)) {
  1919. mutex_unlock(&priv->mutex);
  1920. return;
  1921. }
  1922. if (priv->start_calib) {
  1923. iwl_chain_noise_calibration(priv);
  1924. iwl_sensitivity_calibration(priv);
  1925. }
  1926. mutex_unlock(&priv->mutex);
  1927. }
  1928. static void iwlagn_prepare_restart(struct iwl_priv *priv)
  1929. {
  1930. struct iwl_rxon_context *ctx;
  1931. bool bt_full_concurrent;
  1932. u8 bt_ci_compliance;
  1933. u8 bt_load;
  1934. u8 bt_status;
  1935. lockdep_assert_held(&priv->mutex);
  1936. for_each_context(priv, ctx)
  1937. ctx->vif = NULL;
  1938. priv->is_open = 0;
  1939. /*
  1940. * __iwl_down() will clear the BT status variables,
  1941. * which is correct, but when we restart we really
  1942. * want to keep them so restore them afterwards.
  1943. *
  1944. * The restart process will later pick them up and
  1945. * re-configure the hw when we reconfigure the BT
  1946. * command.
  1947. */
  1948. bt_full_concurrent = priv->bt_full_concurrent;
  1949. bt_ci_compliance = priv->bt_ci_compliance;
  1950. bt_load = priv->bt_traffic_load;
  1951. bt_status = priv->bt_status;
  1952. __iwl_down(priv);
  1953. priv->bt_full_concurrent = bt_full_concurrent;
  1954. priv->bt_ci_compliance = bt_ci_compliance;
  1955. priv->bt_traffic_load = bt_load;
  1956. priv->bt_status = bt_status;
  1957. }
  1958. static void iwl_bg_restart(struct work_struct *data)
  1959. {
  1960. struct iwl_priv *priv = container_of(data, struct iwl_priv, restart);
  1961. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1962. return;
  1963. if (test_and_clear_bit(STATUS_FW_ERROR, &priv->status)) {
  1964. mutex_lock(&priv->mutex);
  1965. iwlagn_prepare_restart(priv);
  1966. mutex_unlock(&priv->mutex);
  1967. iwl_cancel_deferred_work(priv);
  1968. ieee80211_restart_hw(priv->hw);
  1969. } else {
  1970. WARN_ON(1);
  1971. }
  1972. }
  1973. static void iwl_bg_rx_replenish(struct work_struct *data)
  1974. {
  1975. struct iwl_priv *priv =
  1976. container_of(data, struct iwl_priv, rx_replenish);
  1977. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  1978. return;
  1979. mutex_lock(&priv->mutex);
  1980. iwlagn_rx_replenish(priv);
  1981. mutex_unlock(&priv->mutex);
  1982. }
  1983. static int iwl_mac_offchannel_tx(struct ieee80211_hw *hw, struct sk_buff *skb,
  1984. struct ieee80211_channel *chan,
  1985. enum nl80211_channel_type channel_type,
  1986. unsigned int wait)
  1987. {
  1988. struct iwl_priv *priv = hw->priv;
  1989. int ret;
  1990. /* Not supported if we don't have PAN */
  1991. if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN))) {
  1992. ret = -EOPNOTSUPP;
  1993. goto free;
  1994. }
  1995. /* Not supported on pre-P2P firmware */
  1996. if (!(priv->contexts[IWL_RXON_CTX_PAN].interface_modes &
  1997. BIT(NL80211_IFTYPE_P2P_CLIENT))) {
  1998. ret = -EOPNOTSUPP;
  1999. goto free;
  2000. }
  2001. mutex_lock(&priv->mutex);
  2002. if (!priv->contexts[IWL_RXON_CTX_PAN].is_active) {
  2003. /*
  2004. * If the PAN context is free, use the normal
  2005. * way of doing remain-on-channel offload + TX.
  2006. */
  2007. ret = 1;
  2008. goto out;
  2009. }
  2010. /* TODO: queue up if scanning? */
  2011. if (test_bit(STATUS_SCANNING, &priv->status) ||
  2012. priv->_agn.offchan_tx_skb) {
  2013. ret = -EBUSY;
  2014. goto out;
  2015. }
  2016. /*
  2017. * max_scan_ie_len doesn't include the blank SSID or the header,
  2018. * so need to add that again here.
  2019. */
  2020. if (skb->len > hw->wiphy->max_scan_ie_len + 24 + 2) {
  2021. ret = -ENOBUFS;
  2022. goto out;
  2023. }
  2024. priv->_agn.offchan_tx_skb = skb;
  2025. priv->_agn.offchan_tx_timeout = wait;
  2026. priv->_agn.offchan_tx_chan = chan;
  2027. ret = iwl_scan_initiate(priv, priv->contexts[IWL_RXON_CTX_PAN].vif,
  2028. IWL_SCAN_OFFCH_TX, chan->band);
  2029. if (ret)
  2030. priv->_agn.offchan_tx_skb = NULL;
  2031. out:
  2032. mutex_unlock(&priv->mutex);
  2033. free:
  2034. if (ret < 0)
  2035. kfree_skb(skb);
  2036. return ret;
  2037. }
  2038. static int iwl_mac_offchannel_tx_cancel_wait(struct ieee80211_hw *hw)
  2039. {
  2040. struct iwl_priv *priv = hw->priv;
  2041. int ret;
  2042. mutex_lock(&priv->mutex);
  2043. if (!priv->_agn.offchan_tx_skb) {
  2044. ret = -EINVAL;
  2045. goto unlock;
  2046. }
  2047. priv->_agn.offchan_tx_skb = NULL;
  2048. ret = iwl_scan_cancel_timeout(priv, 200);
  2049. if (ret)
  2050. ret = -EIO;
  2051. unlock:
  2052. mutex_unlock(&priv->mutex);
  2053. return ret;
  2054. }
  2055. /*****************************************************************************
  2056. *
  2057. * mac80211 entry point functions
  2058. *
  2059. *****************************************************************************/
  2060. static const struct ieee80211_iface_limit iwlagn_sta_ap_limits[] = {
  2061. {
  2062. .max = 1,
  2063. .types = BIT(NL80211_IFTYPE_STATION),
  2064. },
  2065. {
  2066. .max = 1,
  2067. .types = BIT(NL80211_IFTYPE_AP),
  2068. },
  2069. };
  2070. static const struct ieee80211_iface_limit iwlagn_2sta_limits[] = {
  2071. {
  2072. .max = 2,
  2073. .types = BIT(NL80211_IFTYPE_STATION),
  2074. },
  2075. };
  2076. static const struct ieee80211_iface_limit iwlagn_p2p_sta_go_limits[] = {
  2077. {
  2078. .max = 1,
  2079. .types = BIT(NL80211_IFTYPE_STATION),
  2080. },
  2081. {
  2082. .max = 1,
  2083. .types = BIT(NL80211_IFTYPE_P2P_GO) |
  2084. BIT(NL80211_IFTYPE_AP),
  2085. },
  2086. };
  2087. static const struct ieee80211_iface_limit iwlagn_p2p_2sta_limits[] = {
  2088. {
  2089. .max = 2,
  2090. .types = BIT(NL80211_IFTYPE_STATION),
  2091. },
  2092. {
  2093. .max = 1,
  2094. .types = BIT(NL80211_IFTYPE_P2P_CLIENT),
  2095. },
  2096. };
  2097. static const struct ieee80211_iface_combination
  2098. iwlagn_iface_combinations_dualmode[] = {
  2099. { .num_different_channels = 1,
  2100. .max_interfaces = 2,
  2101. .beacon_int_infra_match = true,
  2102. .limits = iwlagn_sta_ap_limits,
  2103. .n_limits = ARRAY_SIZE(iwlagn_sta_ap_limits),
  2104. },
  2105. { .num_different_channels = 1,
  2106. .max_interfaces = 2,
  2107. .limits = iwlagn_2sta_limits,
  2108. .n_limits = ARRAY_SIZE(iwlagn_2sta_limits),
  2109. },
  2110. };
  2111. static const struct ieee80211_iface_combination
  2112. iwlagn_iface_combinations_p2p[] = {
  2113. { .num_different_channels = 1,
  2114. .max_interfaces = 2,
  2115. .beacon_int_infra_match = true,
  2116. .limits = iwlagn_p2p_sta_go_limits,
  2117. .n_limits = ARRAY_SIZE(iwlagn_p2p_sta_go_limits),
  2118. },
  2119. { .num_different_channels = 1,
  2120. .max_interfaces = 2,
  2121. .limits = iwlagn_p2p_2sta_limits,
  2122. .n_limits = ARRAY_SIZE(iwlagn_p2p_2sta_limits),
  2123. },
  2124. };
  2125. /*
  2126. * Not a mac80211 entry point function, but it fits in with all the
  2127. * other mac80211 functions grouped here.
  2128. */
  2129. static int iwl_mac_setup_register(struct iwl_priv *priv,
  2130. struct iwlagn_ucode_capabilities *capa)
  2131. {
  2132. int ret;
  2133. struct ieee80211_hw *hw = priv->hw;
  2134. struct iwl_rxon_context *ctx;
  2135. hw->rate_control_algorithm = "iwl-agn-rs";
  2136. /* Tell mac80211 our characteristics */
  2137. hw->flags = IEEE80211_HW_SIGNAL_DBM |
  2138. IEEE80211_HW_AMPDU_AGGREGATION |
  2139. IEEE80211_HW_NEED_DTIM_PERIOD |
  2140. IEEE80211_HW_SPECTRUM_MGMT |
  2141. IEEE80211_HW_REPORTS_TX_ACK_STATUS;
  2142. hw->max_tx_aggregation_subframes = LINK_QUAL_AGG_FRAME_LIMIT_DEF;
  2143. hw->flags |= IEEE80211_HW_SUPPORTS_PS |
  2144. IEEE80211_HW_SUPPORTS_DYNAMIC_PS;
  2145. if (priv->cfg->sku & EEPROM_SKU_CAP_11N_ENABLE)
  2146. hw->flags |= IEEE80211_HW_SUPPORTS_DYNAMIC_SMPS |
  2147. IEEE80211_HW_SUPPORTS_STATIC_SMPS;
  2148. if (capa->flags & IWL_UCODE_TLV_FLAGS_MFP)
  2149. hw->flags |= IEEE80211_HW_MFP_CAPABLE;
  2150. hw->sta_data_size = sizeof(struct iwl_station_priv);
  2151. hw->vif_data_size = sizeof(struct iwl_vif_priv);
  2152. for_each_context(priv, ctx) {
  2153. hw->wiphy->interface_modes |= ctx->interface_modes;
  2154. hw->wiphy->interface_modes |= ctx->exclusive_interface_modes;
  2155. }
  2156. BUILD_BUG_ON(NUM_IWL_RXON_CTX != 2);
  2157. if (hw->wiphy->interface_modes & BIT(NL80211_IFTYPE_P2P_CLIENT)) {
  2158. hw->wiphy->iface_combinations = iwlagn_iface_combinations_p2p;
  2159. hw->wiphy->n_iface_combinations =
  2160. ARRAY_SIZE(iwlagn_iface_combinations_p2p);
  2161. } else if (hw->wiphy->interface_modes & BIT(NL80211_IFTYPE_AP)) {
  2162. hw->wiphy->iface_combinations = iwlagn_iface_combinations_dualmode;
  2163. hw->wiphy->n_iface_combinations =
  2164. ARRAY_SIZE(iwlagn_iface_combinations_dualmode);
  2165. }
  2166. hw->wiphy->max_remain_on_channel_duration = 1000;
  2167. hw->wiphy->flags |= WIPHY_FLAG_CUSTOM_REGULATORY |
  2168. WIPHY_FLAG_DISABLE_BEACON_HINTS |
  2169. WIPHY_FLAG_IBSS_RSN;
  2170. /*
  2171. * For now, disable PS by default because it affects
  2172. * RX performance significantly.
  2173. */
  2174. hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
  2175. hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX;
  2176. /* we create the 802.11 header and a zero-length SSID element */
  2177. hw->wiphy->max_scan_ie_len = capa->max_probe_length - 24 - 2;
  2178. /* Default value; 4 EDCA QOS priorities */
  2179. hw->queues = 4;
  2180. hw->max_listen_interval = IWL_CONN_MAX_LISTEN_INTERVAL;
  2181. if (priv->bands[IEEE80211_BAND_2GHZ].n_channels)
  2182. priv->hw->wiphy->bands[IEEE80211_BAND_2GHZ] =
  2183. &priv->bands[IEEE80211_BAND_2GHZ];
  2184. if (priv->bands[IEEE80211_BAND_5GHZ].n_channels)
  2185. priv->hw->wiphy->bands[IEEE80211_BAND_5GHZ] =
  2186. &priv->bands[IEEE80211_BAND_5GHZ];
  2187. iwl_leds_init(priv);
  2188. ret = ieee80211_register_hw(priv->hw);
  2189. if (ret) {
  2190. IWL_ERR(priv, "Failed to register hw (error %d)\n", ret);
  2191. return ret;
  2192. }
  2193. priv->mac80211_registered = 1;
  2194. return 0;
  2195. }
  2196. static int iwlagn_mac_start(struct ieee80211_hw *hw)
  2197. {
  2198. struct iwl_priv *priv = hw->priv;
  2199. int ret;
  2200. IWL_DEBUG_MAC80211(priv, "enter\n");
  2201. /* we should be verifying the device is ready to be opened */
  2202. mutex_lock(&priv->mutex);
  2203. ret = __iwl_up(priv);
  2204. mutex_unlock(&priv->mutex);
  2205. if (ret)
  2206. return ret;
  2207. IWL_DEBUG_INFO(priv, "Start UP work done.\n");
  2208. /* Now we should be done, and the READY bit should be set. */
  2209. if (WARN_ON(!test_bit(STATUS_READY, &priv->status)))
  2210. ret = -EIO;
  2211. iwlagn_led_enable(priv);
  2212. priv->is_open = 1;
  2213. IWL_DEBUG_MAC80211(priv, "leave\n");
  2214. return 0;
  2215. }
  2216. static void iwlagn_mac_stop(struct ieee80211_hw *hw)
  2217. {
  2218. struct iwl_priv *priv = hw->priv;
  2219. IWL_DEBUG_MAC80211(priv, "enter\n");
  2220. if (!priv->is_open)
  2221. return;
  2222. priv->is_open = 0;
  2223. iwl_down(priv);
  2224. flush_workqueue(priv->workqueue);
  2225. /* User space software may expect getting rfkill changes
  2226. * even if interface is down */
  2227. iwl_write32(priv, CSR_INT, 0xFFFFFFFF);
  2228. iwl_enable_rfkill_int(priv);
  2229. IWL_DEBUG_MAC80211(priv, "leave\n");
  2230. }
  2231. static void iwlagn_mac_tx(struct ieee80211_hw *hw, struct sk_buff *skb)
  2232. {
  2233. struct iwl_priv *priv = hw->priv;
  2234. IWL_DEBUG_MACDUMP(priv, "enter\n");
  2235. IWL_DEBUG_TX(priv, "dev->xmit(%d bytes) at rate 0x%02x\n", skb->len,
  2236. ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate);
  2237. if (iwlagn_tx_skb(priv, skb))
  2238. dev_kfree_skb_any(skb);
  2239. IWL_DEBUG_MACDUMP(priv, "leave\n");
  2240. }
  2241. static void iwlagn_mac_update_tkip_key(struct ieee80211_hw *hw,
  2242. struct ieee80211_vif *vif,
  2243. struct ieee80211_key_conf *keyconf,
  2244. struct ieee80211_sta *sta,
  2245. u32 iv32, u16 *phase1key)
  2246. {
  2247. struct iwl_priv *priv = hw->priv;
  2248. struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
  2249. IWL_DEBUG_MAC80211(priv, "enter\n");
  2250. iwl_update_tkip_key(priv, vif_priv->ctx, keyconf, sta,
  2251. iv32, phase1key);
  2252. IWL_DEBUG_MAC80211(priv, "leave\n");
  2253. }
  2254. static int iwlagn_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
  2255. struct ieee80211_vif *vif,
  2256. struct ieee80211_sta *sta,
  2257. struct ieee80211_key_conf *key)
  2258. {
  2259. struct iwl_priv *priv = hw->priv;
  2260. struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
  2261. struct iwl_rxon_context *ctx = vif_priv->ctx;
  2262. int ret;
  2263. u8 sta_id;
  2264. bool is_default_wep_key = false;
  2265. IWL_DEBUG_MAC80211(priv, "enter\n");
  2266. if (iwlagn_mod_params.sw_crypto) {
  2267. IWL_DEBUG_MAC80211(priv, "leave - hwcrypto disabled\n");
  2268. return -EOPNOTSUPP;
  2269. }
  2270. /*
  2271. * To support IBSS RSN, don't program group keys in IBSS, the
  2272. * hardware will then not attempt to decrypt the frames.
  2273. */
  2274. if (vif->type == NL80211_IFTYPE_ADHOC &&
  2275. !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE))
  2276. return -EOPNOTSUPP;
  2277. sta_id = iwl_sta_id_or_broadcast(priv, vif_priv->ctx, sta);
  2278. if (sta_id == IWL_INVALID_STATION)
  2279. return -EINVAL;
  2280. mutex_lock(&priv->mutex);
  2281. iwl_scan_cancel_timeout(priv, 100);
  2282. /*
  2283. * If we are getting WEP group key and we didn't receive any key mapping
  2284. * so far, we are in legacy wep mode (group key only), otherwise we are
  2285. * in 1X mode.
  2286. * In legacy wep mode, we use another host command to the uCode.
  2287. */
  2288. if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 ||
  2289. key->cipher == WLAN_CIPHER_SUITE_WEP104) &&
  2290. !sta) {
  2291. if (cmd == SET_KEY)
  2292. is_default_wep_key = !ctx->key_mapping_keys;
  2293. else
  2294. is_default_wep_key =
  2295. (key->hw_key_idx == HW_KEY_DEFAULT);
  2296. }
  2297. switch (cmd) {
  2298. case SET_KEY:
  2299. if (is_default_wep_key)
  2300. ret = iwl_set_default_wep_key(priv, vif_priv->ctx, key);
  2301. else
  2302. ret = iwl_set_dynamic_key(priv, vif_priv->ctx,
  2303. key, sta_id);
  2304. IWL_DEBUG_MAC80211(priv, "enable hwcrypto key\n");
  2305. break;
  2306. case DISABLE_KEY:
  2307. if (is_default_wep_key)
  2308. ret = iwl_remove_default_wep_key(priv, ctx, key);
  2309. else
  2310. ret = iwl_remove_dynamic_key(priv, ctx, key, sta_id);
  2311. IWL_DEBUG_MAC80211(priv, "disable hwcrypto key\n");
  2312. break;
  2313. default:
  2314. ret = -EINVAL;
  2315. }
  2316. mutex_unlock(&priv->mutex);
  2317. IWL_DEBUG_MAC80211(priv, "leave\n");
  2318. return ret;
  2319. }
  2320. static int iwlagn_mac_ampdu_action(struct ieee80211_hw *hw,
  2321. struct ieee80211_vif *vif,
  2322. enum ieee80211_ampdu_mlme_action action,
  2323. struct ieee80211_sta *sta, u16 tid, u16 *ssn,
  2324. u8 buf_size)
  2325. {
  2326. struct iwl_priv *priv = hw->priv;
  2327. int ret = -EINVAL;
  2328. struct iwl_station_priv *sta_priv = (void *) sta->drv_priv;
  2329. IWL_DEBUG_HT(priv, "A-MPDU action on addr %pM tid %d\n",
  2330. sta->addr, tid);
  2331. if (!(priv->cfg->sku & EEPROM_SKU_CAP_11N_ENABLE))
  2332. return -EACCES;
  2333. mutex_lock(&priv->mutex);
  2334. switch (action) {
  2335. case IEEE80211_AMPDU_RX_START:
  2336. IWL_DEBUG_HT(priv, "start Rx\n");
  2337. ret = iwl_sta_rx_agg_start(priv, sta, tid, *ssn);
  2338. break;
  2339. case IEEE80211_AMPDU_RX_STOP:
  2340. IWL_DEBUG_HT(priv, "stop Rx\n");
  2341. ret = iwl_sta_rx_agg_stop(priv, sta, tid);
  2342. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2343. ret = 0;
  2344. break;
  2345. case IEEE80211_AMPDU_TX_START:
  2346. IWL_DEBUG_HT(priv, "start Tx\n");
  2347. ret = iwlagn_tx_agg_start(priv, vif, sta, tid, ssn);
  2348. if (ret == 0) {
  2349. priv->_agn.agg_tids_count++;
  2350. IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
  2351. priv->_agn.agg_tids_count);
  2352. }
  2353. break;
  2354. case IEEE80211_AMPDU_TX_STOP:
  2355. IWL_DEBUG_HT(priv, "stop Tx\n");
  2356. ret = iwlagn_tx_agg_stop(priv, vif, sta, tid);
  2357. if ((ret == 0) && (priv->_agn.agg_tids_count > 0)) {
  2358. priv->_agn.agg_tids_count--;
  2359. IWL_DEBUG_HT(priv, "priv->_agn.agg_tids_count = %u\n",
  2360. priv->_agn.agg_tids_count);
  2361. }
  2362. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  2363. ret = 0;
  2364. if (priv->cfg->ht_params &&
  2365. priv->cfg->ht_params->use_rts_for_aggregation) {
  2366. /*
  2367. * switch off RTS/CTS if it was previously enabled
  2368. */
  2369. sta_priv->lq_sta.lq.general_params.flags &=
  2370. ~LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
  2371. iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
  2372. &sta_priv->lq_sta.lq, CMD_ASYNC, false);
  2373. }
  2374. break;
  2375. case IEEE80211_AMPDU_TX_OPERATIONAL:
  2376. buf_size = min_t(int, buf_size, LINK_QUAL_AGG_FRAME_LIMIT_DEF);
  2377. iwlagn_txq_agg_queue_setup(priv, sta, tid, buf_size);
  2378. /*
  2379. * If the limit is 0, then it wasn't initialised yet,
  2380. * use the default. We can do that since we take the
  2381. * minimum below, and we don't want to go above our
  2382. * default due to hardware restrictions.
  2383. */
  2384. if (sta_priv->max_agg_bufsize == 0)
  2385. sta_priv->max_agg_bufsize =
  2386. LINK_QUAL_AGG_FRAME_LIMIT_DEF;
  2387. /*
  2388. * Even though in theory the peer could have different
  2389. * aggregation reorder buffer sizes for different sessions,
  2390. * our ucode doesn't allow for that and has a global limit
  2391. * for each station. Therefore, use the minimum of all the
  2392. * aggregation sessions and our default value.
  2393. */
  2394. sta_priv->max_agg_bufsize =
  2395. min(sta_priv->max_agg_bufsize, buf_size);
  2396. if (priv->cfg->ht_params &&
  2397. priv->cfg->ht_params->use_rts_for_aggregation) {
  2398. /*
  2399. * switch to RTS/CTS if it is the prefer protection
  2400. * method for HT traffic
  2401. */
  2402. sta_priv->lq_sta.lq.general_params.flags |=
  2403. LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK;
  2404. }
  2405. sta_priv->lq_sta.lq.agg_params.agg_frame_cnt_limit =
  2406. sta_priv->max_agg_bufsize;
  2407. iwl_send_lq_cmd(priv, iwl_rxon_ctx_from_vif(vif),
  2408. &sta_priv->lq_sta.lq, CMD_ASYNC, false);
  2409. IWL_INFO(priv, "Tx aggregation enabled on ra = %pM tid = %d\n",
  2410. sta->addr, tid);
  2411. ret = 0;
  2412. break;
  2413. }
  2414. mutex_unlock(&priv->mutex);
  2415. return ret;
  2416. }
  2417. static int iwlagn_mac_sta_add(struct ieee80211_hw *hw,
  2418. struct ieee80211_vif *vif,
  2419. struct ieee80211_sta *sta)
  2420. {
  2421. struct iwl_priv *priv = hw->priv;
  2422. struct iwl_station_priv *sta_priv = (void *)sta->drv_priv;
  2423. struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
  2424. bool is_ap = vif->type == NL80211_IFTYPE_STATION;
  2425. int ret;
  2426. u8 sta_id;
  2427. IWL_DEBUG_INFO(priv, "received request to add station %pM\n",
  2428. sta->addr);
  2429. mutex_lock(&priv->mutex);
  2430. IWL_DEBUG_INFO(priv, "proceeding to add station %pM\n",
  2431. sta->addr);
  2432. sta_priv->common.sta_id = IWL_INVALID_STATION;
  2433. atomic_set(&sta_priv->pending_frames, 0);
  2434. if (vif->type == NL80211_IFTYPE_AP)
  2435. sta_priv->client = true;
  2436. ret = iwl_add_station_common(priv, vif_priv->ctx, sta->addr,
  2437. is_ap, sta, &sta_id);
  2438. if (ret) {
  2439. IWL_ERR(priv, "Unable to add station %pM (%d)\n",
  2440. sta->addr, ret);
  2441. /* Should we return success if return code is EEXIST ? */
  2442. mutex_unlock(&priv->mutex);
  2443. return ret;
  2444. }
  2445. sta_priv->common.sta_id = sta_id;
  2446. /* Initialize rate scaling */
  2447. IWL_DEBUG_INFO(priv, "Initializing rate scaling for station %pM\n",
  2448. sta->addr);
  2449. iwl_rs_rate_init(priv, sta, sta_id);
  2450. mutex_unlock(&priv->mutex);
  2451. return 0;
  2452. }
  2453. static void iwlagn_mac_channel_switch(struct ieee80211_hw *hw,
  2454. struct ieee80211_channel_switch *ch_switch)
  2455. {
  2456. struct iwl_priv *priv = hw->priv;
  2457. const struct iwl_channel_info *ch_info;
  2458. struct ieee80211_conf *conf = &hw->conf;
  2459. struct ieee80211_channel *channel = ch_switch->channel;
  2460. struct iwl_ht_config *ht_conf = &priv->current_ht_config;
  2461. /*
  2462. * MULTI-FIXME
  2463. * When we add support for multiple interfaces, we need to
  2464. * revisit this. The channel switch command in the device
  2465. * only affects the BSS context, but what does that really
  2466. * mean? And what if we get a CSA on the second interface?
  2467. * This needs a lot of work.
  2468. */
  2469. struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_BSS];
  2470. u16 ch;
  2471. IWL_DEBUG_MAC80211(priv, "enter\n");
  2472. mutex_lock(&priv->mutex);
  2473. if (iwl_is_rfkill(priv))
  2474. goto out;
  2475. if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
  2476. test_bit(STATUS_SCANNING, &priv->status) ||
  2477. test_bit(STATUS_CHANNEL_SWITCH_PENDING, &priv->status))
  2478. goto out;
  2479. if (!iwl_is_associated_ctx(ctx))
  2480. goto out;
  2481. if (!priv->cfg->ops->lib->set_channel_switch)
  2482. goto out;
  2483. ch = channel->hw_value;
  2484. if (le16_to_cpu(ctx->active.channel) == ch)
  2485. goto out;
  2486. ch_info = iwl_get_channel_info(priv, channel->band, ch);
  2487. if (!is_channel_valid(ch_info)) {
  2488. IWL_DEBUG_MAC80211(priv, "invalid channel\n");
  2489. goto out;
  2490. }
  2491. spin_lock_irq(&priv->lock);
  2492. priv->current_ht_config.smps = conf->smps_mode;
  2493. /* Configure HT40 channels */
  2494. ctx->ht.enabled = conf_is_ht(conf);
  2495. if (ctx->ht.enabled) {
  2496. if (conf_is_ht40_minus(conf)) {
  2497. ctx->ht.extension_chan_offset =
  2498. IEEE80211_HT_PARAM_CHA_SEC_BELOW;
  2499. ctx->ht.is_40mhz = true;
  2500. } else if (conf_is_ht40_plus(conf)) {
  2501. ctx->ht.extension_chan_offset =
  2502. IEEE80211_HT_PARAM_CHA_SEC_ABOVE;
  2503. ctx->ht.is_40mhz = true;
  2504. } else {
  2505. ctx->ht.extension_chan_offset =
  2506. IEEE80211_HT_PARAM_CHA_SEC_NONE;
  2507. ctx->ht.is_40mhz = false;
  2508. }
  2509. } else
  2510. ctx->ht.is_40mhz = false;
  2511. if ((le16_to_cpu(ctx->staging.channel) != ch))
  2512. ctx->staging.flags = 0;
  2513. iwl_set_rxon_channel(priv, channel, ctx);
  2514. iwl_set_rxon_ht(priv, ht_conf);
  2515. iwl_set_flags_for_band(priv, ctx, channel->band, ctx->vif);
  2516. spin_unlock_irq(&priv->lock);
  2517. iwl_set_rate(priv);
  2518. /*
  2519. * at this point, staging_rxon has the
  2520. * configuration for channel switch
  2521. */
  2522. set_bit(STATUS_CHANNEL_SWITCH_PENDING, &priv->status);
  2523. priv->switch_channel = cpu_to_le16(ch);
  2524. if (priv->cfg->ops->lib->set_channel_switch(priv, ch_switch)) {
  2525. clear_bit(STATUS_CHANNEL_SWITCH_PENDING, &priv->status);
  2526. priv->switch_channel = 0;
  2527. ieee80211_chswitch_done(ctx->vif, false);
  2528. }
  2529. out:
  2530. mutex_unlock(&priv->mutex);
  2531. IWL_DEBUG_MAC80211(priv, "leave\n");
  2532. }
  2533. static void iwlagn_configure_filter(struct ieee80211_hw *hw,
  2534. unsigned int changed_flags,
  2535. unsigned int *total_flags,
  2536. u64 multicast)
  2537. {
  2538. struct iwl_priv *priv = hw->priv;
  2539. __le32 filter_or = 0, filter_nand = 0;
  2540. struct iwl_rxon_context *ctx;
  2541. #define CHK(test, flag) do { \
  2542. if (*total_flags & (test)) \
  2543. filter_or |= (flag); \
  2544. else \
  2545. filter_nand |= (flag); \
  2546. } while (0)
  2547. IWL_DEBUG_MAC80211(priv, "Enter: changed: 0x%x, total: 0x%x\n",
  2548. changed_flags, *total_flags);
  2549. CHK(FIF_OTHER_BSS | FIF_PROMISC_IN_BSS, RXON_FILTER_PROMISC_MSK);
  2550. /* Setting _just_ RXON_FILTER_CTL2HOST_MSK causes FH errors */
  2551. CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_PROMISC_MSK);
  2552. CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK);
  2553. #undef CHK
  2554. mutex_lock(&priv->mutex);
  2555. for_each_context(priv, ctx) {
  2556. ctx->staging.filter_flags &= ~filter_nand;
  2557. ctx->staging.filter_flags |= filter_or;
  2558. /*
  2559. * Not committing directly because hardware can perform a scan,
  2560. * but we'll eventually commit the filter flags change anyway.
  2561. */
  2562. }
  2563. mutex_unlock(&priv->mutex);
  2564. /*
  2565. * Receiving all multicast frames is always enabled by the
  2566. * default flags setup in iwl_connection_init_rx_config()
  2567. * since we currently do not support programming multicast
  2568. * filters into the device.
  2569. */
  2570. *total_flags &= FIF_OTHER_BSS | FIF_ALLMULTI | FIF_PROMISC_IN_BSS |
  2571. FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL;
  2572. }
  2573. static void iwlagn_mac_flush(struct ieee80211_hw *hw, bool drop)
  2574. {
  2575. struct iwl_priv *priv = hw->priv;
  2576. mutex_lock(&priv->mutex);
  2577. IWL_DEBUG_MAC80211(priv, "enter\n");
  2578. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  2579. IWL_DEBUG_TX(priv, "Aborting flush due to device shutdown\n");
  2580. goto done;
  2581. }
  2582. if (iwl_is_rfkill(priv)) {
  2583. IWL_DEBUG_TX(priv, "Aborting flush due to RF Kill\n");
  2584. goto done;
  2585. }
  2586. /*
  2587. * mac80211 will not push any more frames for transmit
  2588. * until the flush is completed
  2589. */
  2590. if (drop) {
  2591. IWL_DEBUG_MAC80211(priv, "send flush command\n");
  2592. if (iwlagn_txfifo_flush(priv, IWL_DROP_ALL)) {
  2593. IWL_ERR(priv, "flush request fail\n");
  2594. goto done;
  2595. }
  2596. }
  2597. IWL_DEBUG_MAC80211(priv, "wait transmit/flush all frames\n");
  2598. iwlagn_wait_tx_queue_empty(priv);
  2599. done:
  2600. mutex_unlock(&priv->mutex);
  2601. IWL_DEBUG_MAC80211(priv, "leave\n");
  2602. }
  2603. static void iwlagn_disable_roc(struct iwl_priv *priv)
  2604. {
  2605. struct iwl_rxon_context *ctx = &priv->contexts[IWL_RXON_CTX_PAN];
  2606. struct ieee80211_channel *chan = ACCESS_ONCE(priv->hw->conf.channel);
  2607. lockdep_assert_held(&priv->mutex);
  2608. if (!ctx->is_active)
  2609. return;
  2610. ctx->staging.dev_type = RXON_DEV_TYPE_2STA;
  2611. ctx->staging.filter_flags &= ~RXON_FILTER_ASSOC_MSK;
  2612. iwl_set_rxon_channel(priv, chan, ctx);
  2613. iwl_set_flags_for_band(priv, ctx, chan->band, NULL);
  2614. priv->_agn.hw_roc_channel = NULL;
  2615. iwlagn_commit_rxon(priv, ctx);
  2616. ctx->is_active = false;
  2617. }
  2618. static void iwlagn_bg_roc_done(struct work_struct *work)
  2619. {
  2620. struct iwl_priv *priv = container_of(work, struct iwl_priv,
  2621. _agn.hw_roc_work.work);
  2622. mutex_lock(&priv->mutex);
  2623. ieee80211_remain_on_channel_expired(priv->hw);
  2624. iwlagn_disable_roc(priv);
  2625. mutex_unlock(&priv->mutex);
  2626. }
  2627. static int iwl_mac_remain_on_channel(struct ieee80211_hw *hw,
  2628. struct ieee80211_channel *channel,
  2629. enum nl80211_channel_type channel_type,
  2630. int duration)
  2631. {
  2632. struct iwl_priv *priv = hw->priv;
  2633. int err = 0;
  2634. if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN)))
  2635. return -EOPNOTSUPP;
  2636. if (!(priv->contexts[IWL_RXON_CTX_PAN].interface_modes &
  2637. BIT(NL80211_IFTYPE_P2P_CLIENT)))
  2638. return -EOPNOTSUPP;
  2639. mutex_lock(&priv->mutex);
  2640. if (priv->contexts[IWL_RXON_CTX_PAN].is_active ||
  2641. test_bit(STATUS_SCAN_HW, &priv->status)) {
  2642. err = -EBUSY;
  2643. goto out;
  2644. }
  2645. priv->contexts[IWL_RXON_CTX_PAN].is_active = true;
  2646. priv->_agn.hw_roc_channel = channel;
  2647. priv->_agn.hw_roc_chantype = channel_type;
  2648. priv->_agn.hw_roc_duration = DIV_ROUND_UP(duration * 1000, 1024);
  2649. iwlagn_commit_rxon(priv, &priv->contexts[IWL_RXON_CTX_PAN]);
  2650. queue_delayed_work(priv->workqueue, &priv->_agn.hw_roc_work,
  2651. msecs_to_jiffies(duration + 20));
  2652. msleep(IWL_MIN_SLOT_TIME); /* TU is almost ms */
  2653. ieee80211_ready_on_channel(priv->hw);
  2654. out:
  2655. mutex_unlock(&priv->mutex);
  2656. return err;
  2657. }
  2658. static int iwl_mac_cancel_remain_on_channel(struct ieee80211_hw *hw)
  2659. {
  2660. struct iwl_priv *priv = hw->priv;
  2661. if (!(priv->valid_contexts & BIT(IWL_RXON_CTX_PAN)))
  2662. return -EOPNOTSUPP;
  2663. cancel_delayed_work_sync(&priv->_agn.hw_roc_work);
  2664. mutex_lock(&priv->mutex);
  2665. iwlagn_disable_roc(priv);
  2666. mutex_unlock(&priv->mutex);
  2667. return 0;
  2668. }
  2669. /*****************************************************************************
  2670. *
  2671. * driver setup and teardown
  2672. *
  2673. *****************************************************************************/
  2674. static void iwl_setup_deferred_work(struct iwl_priv *priv)
  2675. {
  2676. priv->workqueue = create_singlethread_workqueue(DRV_NAME);
  2677. init_waitqueue_head(&priv->wait_command_queue);
  2678. INIT_WORK(&priv->restart, iwl_bg_restart);
  2679. INIT_WORK(&priv->rx_replenish, iwl_bg_rx_replenish);
  2680. INIT_WORK(&priv->beacon_update, iwl_bg_beacon_update);
  2681. INIT_WORK(&priv->run_time_calib_work, iwl_bg_run_time_calib_work);
  2682. INIT_WORK(&priv->tx_flush, iwl_bg_tx_flush);
  2683. INIT_WORK(&priv->bt_full_concurrency, iwl_bg_bt_full_concurrency);
  2684. INIT_WORK(&priv->bt_runtime_config, iwl_bg_bt_runtime_config);
  2685. INIT_DELAYED_WORK(&priv->_agn.hw_roc_work, iwlagn_bg_roc_done);
  2686. iwl_setup_scan_deferred_work(priv);
  2687. if (priv->cfg->ops->lib->setup_deferred_work)
  2688. priv->cfg->ops->lib->setup_deferred_work(priv);
  2689. init_timer(&priv->statistics_periodic);
  2690. priv->statistics_periodic.data = (unsigned long)priv;
  2691. priv->statistics_periodic.function = iwl_bg_statistics_periodic;
  2692. init_timer(&priv->ucode_trace);
  2693. priv->ucode_trace.data = (unsigned long)priv;
  2694. priv->ucode_trace.function = iwl_bg_ucode_trace;
  2695. init_timer(&priv->watchdog);
  2696. priv->watchdog.data = (unsigned long)priv;
  2697. priv->watchdog.function = iwl_bg_watchdog;
  2698. tasklet_init(&priv->irq_tasklet, (void (*)(unsigned long))
  2699. iwl_irq_tasklet, (unsigned long)priv);
  2700. }
  2701. static void iwl_cancel_deferred_work(struct iwl_priv *priv)
  2702. {
  2703. if (priv->cfg->ops->lib->cancel_deferred_work)
  2704. priv->cfg->ops->lib->cancel_deferred_work(priv);
  2705. cancel_work_sync(&priv->run_time_calib_work);
  2706. cancel_work_sync(&priv->beacon_update);
  2707. iwl_cancel_scan_deferred_work(priv);
  2708. cancel_work_sync(&priv->bt_full_concurrency);
  2709. cancel_work_sync(&priv->bt_runtime_config);
  2710. del_timer_sync(&priv->statistics_periodic);
  2711. del_timer_sync(&priv->ucode_trace);
  2712. }
  2713. static void iwl_init_hw_rates(struct iwl_priv *priv,
  2714. struct ieee80211_rate *rates)
  2715. {
  2716. int i;
  2717. for (i = 0; i < IWL_RATE_COUNT_LEGACY; i++) {
  2718. rates[i].bitrate = iwl_rates[i].ieee * 5;
  2719. rates[i].hw_value = i; /* Rate scaling will work on indexes */
  2720. rates[i].hw_value_short = i;
  2721. rates[i].flags = 0;
  2722. if ((i >= IWL_FIRST_CCK_RATE) && (i <= IWL_LAST_CCK_RATE)) {
  2723. /*
  2724. * If CCK != 1M then set short preamble rate flag.
  2725. */
  2726. rates[i].flags |=
  2727. (iwl_rates[i].plcp == IWL_RATE_1M_PLCP) ?
  2728. 0 : IEEE80211_RATE_SHORT_PREAMBLE;
  2729. }
  2730. }
  2731. }
  2732. static int iwl_init_drv(struct iwl_priv *priv)
  2733. {
  2734. int ret;
  2735. spin_lock_init(&priv->sta_lock);
  2736. spin_lock_init(&priv->hcmd_lock);
  2737. mutex_init(&priv->mutex);
  2738. priv->ieee_channels = NULL;
  2739. priv->ieee_rates = NULL;
  2740. priv->band = IEEE80211_BAND_2GHZ;
  2741. priv->iw_mode = NL80211_IFTYPE_STATION;
  2742. priv->current_ht_config.smps = IEEE80211_SMPS_STATIC;
  2743. priv->missed_beacon_threshold = IWL_MISSED_BEACON_THRESHOLD_DEF;
  2744. priv->_agn.agg_tids_count = 0;
  2745. /* initialize force reset */
  2746. priv->force_reset[IWL_RF_RESET].reset_duration =
  2747. IWL_DELAY_NEXT_FORCE_RF_RESET;
  2748. priv->force_reset[IWL_FW_RESET].reset_duration =
  2749. IWL_DELAY_NEXT_FORCE_FW_RELOAD;
  2750. priv->rx_statistics_jiffies = jiffies;
  2751. /* Choose which receivers/antennas to use */
  2752. if (priv->cfg->ops->hcmd->set_rxon_chain)
  2753. priv->cfg->ops->hcmd->set_rxon_chain(priv,
  2754. &priv->contexts[IWL_RXON_CTX_BSS]);
  2755. iwl_init_scan_params(priv);
  2756. /* init bt coex */
  2757. if (priv->cfg->bt_params &&
  2758. priv->cfg->bt_params->advanced_bt_coexist) {
  2759. priv->kill_ack_mask = IWLAGN_BT_KILL_ACK_MASK_DEFAULT;
  2760. priv->kill_cts_mask = IWLAGN_BT_KILL_CTS_MASK_DEFAULT;
  2761. priv->bt_valid = IWLAGN_BT_ALL_VALID_MSK;
  2762. priv->bt_on_thresh = BT_ON_THRESHOLD_DEF;
  2763. priv->bt_duration = BT_DURATION_LIMIT_DEF;
  2764. priv->dynamic_frag_thresh = BT_FRAG_THRESHOLD_DEF;
  2765. }
  2766. ret = iwl_init_channel_map(priv);
  2767. if (ret) {
  2768. IWL_ERR(priv, "initializing regulatory failed: %d\n", ret);
  2769. goto err;
  2770. }
  2771. ret = iwlcore_init_geos(priv);
  2772. if (ret) {
  2773. IWL_ERR(priv, "initializing geos failed: %d\n", ret);
  2774. goto err_free_channel_map;
  2775. }
  2776. iwl_init_hw_rates(priv, priv->ieee_rates);
  2777. return 0;
  2778. err_free_channel_map:
  2779. iwl_free_channel_map(priv);
  2780. err:
  2781. return ret;
  2782. }
  2783. static void iwl_uninit_drv(struct iwl_priv *priv)
  2784. {
  2785. iwl_calib_free_results(priv);
  2786. iwlcore_free_geos(priv);
  2787. iwl_free_channel_map(priv);
  2788. kfree(priv->scan_cmd);
  2789. kfree(priv->beacon_cmd);
  2790. }
  2791. struct ieee80211_ops iwlagn_hw_ops = {
  2792. .tx = iwlagn_mac_tx,
  2793. .start = iwlagn_mac_start,
  2794. .stop = iwlagn_mac_stop,
  2795. .add_interface = iwl_mac_add_interface,
  2796. .remove_interface = iwl_mac_remove_interface,
  2797. .change_interface = iwl_mac_change_interface,
  2798. .config = iwlagn_mac_config,
  2799. .configure_filter = iwlagn_configure_filter,
  2800. .set_key = iwlagn_mac_set_key,
  2801. .update_tkip_key = iwlagn_mac_update_tkip_key,
  2802. .conf_tx = iwl_mac_conf_tx,
  2803. .bss_info_changed = iwlagn_bss_info_changed,
  2804. .ampdu_action = iwlagn_mac_ampdu_action,
  2805. .hw_scan = iwl_mac_hw_scan,
  2806. .sta_notify = iwlagn_mac_sta_notify,
  2807. .sta_add = iwlagn_mac_sta_add,
  2808. .sta_remove = iwl_mac_sta_remove,
  2809. .channel_switch = iwlagn_mac_channel_switch,
  2810. .flush = iwlagn_mac_flush,
  2811. .tx_last_beacon = iwl_mac_tx_last_beacon,
  2812. .remain_on_channel = iwl_mac_remain_on_channel,
  2813. .cancel_remain_on_channel = iwl_mac_cancel_remain_on_channel,
  2814. .offchannel_tx = iwl_mac_offchannel_tx,
  2815. .offchannel_tx_cancel_wait = iwl_mac_offchannel_tx_cancel_wait,
  2816. CFG80211_TESTMODE_CMD(iwl_testmode_cmd)
  2817. CFG80211_TESTMODE_DUMP(iwl_testmode_dump)
  2818. };
  2819. static u32 iwl_hw_detect(struct iwl_priv *priv)
  2820. {
  2821. u8 rev_id;
  2822. pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
  2823. IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", rev_id);
  2824. return iwl_read32(priv, CSR_HW_REV);
  2825. }
  2826. static int iwl_set_hw_params(struct iwl_priv *priv)
  2827. {
  2828. priv->hw_params.max_rxq_size = RX_QUEUE_SIZE;
  2829. priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG;
  2830. if (iwlagn_mod_params.amsdu_size_8K)
  2831. priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_8K);
  2832. else
  2833. priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_4K);
  2834. priv->hw_params.max_beacon_itrvl = IWL_MAX_UCODE_BEACON_INTERVAL;
  2835. if (iwlagn_mod_params.disable_11n)
  2836. priv->cfg->sku &= ~EEPROM_SKU_CAP_11N_ENABLE;
  2837. /* Device-specific setup */
  2838. return priv->cfg->ops->lib->set_hw_params(priv);
  2839. }
  2840. static const u8 iwlagn_bss_ac_to_fifo[] = {
  2841. IWL_TX_FIFO_VO,
  2842. IWL_TX_FIFO_VI,
  2843. IWL_TX_FIFO_BE,
  2844. IWL_TX_FIFO_BK,
  2845. };
  2846. static const u8 iwlagn_bss_ac_to_queue[] = {
  2847. 0, 1, 2, 3,
  2848. };
  2849. static const u8 iwlagn_pan_ac_to_fifo[] = {
  2850. IWL_TX_FIFO_VO_IPAN,
  2851. IWL_TX_FIFO_VI_IPAN,
  2852. IWL_TX_FIFO_BE_IPAN,
  2853. IWL_TX_FIFO_BK_IPAN,
  2854. };
  2855. static const u8 iwlagn_pan_ac_to_queue[] = {
  2856. 7, 6, 5, 4,
  2857. };
  2858. /* This function both allocates and initializes hw and priv. */
  2859. static struct ieee80211_hw *iwl_alloc_all(struct iwl_cfg *cfg)
  2860. {
  2861. struct iwl_priv *priv;
  2862. /* mac80211 allocates memory for this device instance, including
  2863. * space for this driver's private structure */
  2864. struct ieee80211_hw *hw;
  2865. hw = ieee80211_alloc_hw(sizeof(struct iwl_priv), &iwlagn_hw_ops);
  2866. if (hw == NULL) {
  2867. pr_err("%s: Can not allocate network device\n",
  2868. cfg->name);
  2869. goto out;
  2870. }
  2871. priv = hw->priv;
  2872. priv->hw = hw;
  2873. out:
  2874. return hw;
  2875. }
  2876. static void iwl_init_context(struct iwl_priv *priv)
  2877. {
  2878. int i;
  2879. /*
  2880. * The default context is always valid,
  2881. * more may be discovered when firmware
  2882. * is loaded.
  2883. */
  2884. priv->valid_contexts = BIT(IWL_RXON_CTX_BSS);
  2885. for (i = 0; i < NUM_IWL_RXON_CTX; i++)
  2886. priv->contexts[i].ctxid = i;
  2887. priv->contexts[IWL_RXON_CTX_BSS].always_active = true;
  2888. priv->contexts[IWL_RXON_CTX_BSS].is_active = true;
  2889. priv->contexts[IWL_RXON_CTX_BSS].rxon_cmd = REPLY_RXON;
  2890. priv->contexts[IWL_RXON_CTX_BSS].rxon_timing_cmd = REPLY_RXON_TIMING;
  2891. priv->contexts[IWL_RXON_CTX_BSS].rxon_assoc_cmd = REPLY_RXON_ASSOC;
  2892. priv->contexts[IWL_RXON_CTX_BSS].qos_cmd = REPLY_QOS_PARAM;
  2893. priv->contexts[IWL_RXON_CTX_BSS].ap_sta_id = IWL_AP_ID;
  2894. priv->contexts[IWL_RXON_CTX_BSS].wep_key_cmd = REPLY_WEPKEY;
  2895. priv->contexts[IWL_RXON_CTX_BSS].ac_to_fifo = iwlagn_bss_ac_to_fifo;
  2896. priv->contexts[IWL_RXON_CTX_BSS].ac_to_queue = iwlagn_bss_ac_to_queue;
  2897. priv->contexts[IWL_RXON_CTX_BSS].exclusive_interface_modes =
  2898. BIT(NL80211_IFTYPE_ADHOC);
  2899. priv->contexts[IWL_RXON_CTX_BSS].interface_modes =
  2900. BIT(NL80211_IFTYPE_STATION);
  2901. priv->contexts[IWL_RXON_CTX_BSS].ap_devtype = RXON_DEV_TYPE_AP;
  2902. priv->contexts[IWL_RXON_CTX_BSS].ibss_devtype = RXON_DEV_TYPE_IBSS;
  2903. priv->contexts[IWL_RXON_CTX_BSS].station_devtype = RXON_DEV_TYPE_ESS;
  2904. priv->contexts[IWL_RXON_CTX_BSS].unused_devtype = RXON_DEV_TYPE_ESS;
  2905. priv->contexts[IWL_RXON_CTX_PAN].rxon_cmd = REPLY_WIPAN_RXON;
  2906. priv->contexts[IWL_RXON_CTX_PAN].rxon_timing_cmd =
  2907. REPLY_WIPAN_RXON_TIMING;
  2908. priv->contexts[IWL_RXON_CTX_PAN].rxon_assoc_cmd =
  2909. REPLY_WIPAN_RXON_ASSOC;
  2910. priv->contexts[IWL_RXON_CTX_PAN].qos_cmd = REPLY_WIPAN_QOS_PARAM;
  2911. priv->contexts[IWL_RXON_CTX_PAN].ap_sta_id = IWL_AP_ID_PAN;
  2912. priv->contexts[IWL_RXON_CTX_PAN].wep_key_cmd = REPLY_WIPAN_WEPKEY;
  2913. priv->contexts[IWL_RXON_CTX_PAN].bcast_sta_id = IWLAGN_PAN_BCAST_ID;
  2914. priv->contexts[IWL_RXON_CTX_PAN].station_flags = STA_FLG_PAN_STATION;
  2915. priv->contexts[IWL_RXON_CTX_PAN].ac_to_fifo = iwlagn_pan_ac_to_fifo;
  2916. priv->contexts[IWL_RXON_CTX_PAN].ac_to_queue = iwlagn_pan_ac_to_queue;
  2917. priv->contexts[IWL_RXON_CTX_PAN].mcast_queue = IWL_IPAN_MCAST_QUEUE;
  2918. priv->contexts[IWL_RXON_CTX_PAN].interface_modes =
  2919. BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_AP);
  2920. #ifdef CONFIG_IWL_P2P
  2921. priv->contexts[IWL_RXON_CTX_PAN].interface_modes |=
  2922. BIT(NL80211_IFTYPE_P2P_CLIENT) | BIT(NL80211_IFTYPE_P2P_GO);
  2923. #endif
  2924. priv->contexts[IWL_RXON_CTX_PAN].ap_devtype = RXON_DEV_TYPE_CP;
  2925. priv->contexts[IWL_RXON_CTX_PAN].station_devtype = RXON_DEV_TYPE_2STA;
  2926. priv->contexts[IWL_RXON_CTX_PAN].unused_devtype = RXON_DEV_TYPE_P2P;
  2927. BUILD_BUG_ON(NUM_IWL_RXON_CTX != 2);
  2928. }
  2929. static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
  2930. {
  2931. int err = 0;
  2932. struct iwl_priv *priv;
  2933. struct ieee80211_hw *hw;
  2934. struct iwl_cfg *cfg = (struct iwl_cfg *)(ent->driver_data);
  2935. u16 pci_cmd, num_mac;
  2936. u32 hw_rev;
  2937. /************************
  2938. * 1. Allocating HW data
  2939. ************************/
  2940. hw = iwl_alloc_all(cfg);
  2941. if (!hw) {
  2942. err = -ENOMEM;
  2943. goto out; }
  2944. priv = hw->priv;
  2945. /* At this point both hw and priv are allocated. */
  2946. SET_IEEE80211_DEV(hw, &pdev->dev);
  2947. IWL_DEBUG_INFO(priv, "*** LOAD DRIVER ***\n");
  2948. priv->cfg = cfg;
  2949. priv->pci_dev = pdev;
  2950. priv->inta_mask = CSR_INI_SET_MASK;
  2951. /* is antenna coupling more than 35dB ? */
  2952. priv->bt_ant_couple_ok =
  2953. (iwlagn_ant_coupling > IWL_BT_ANTENNA_COUPLING_THRESHOLD) ?
  2954. true : false;
  2955. /* enable/disable bt channel inhibition */
  2956. priv->bt_ch_announce = iwlagn_bt_ch_announce;
  2957. IWL_DEBUG_INFO(priv, "BT channel inhibition is %s\n",
  2958. (priv->bt_ch_announce) ? "On" : "Off");
  2959. if (iwl_alloc_traffic_mem(priv))
  2960. IWL_ERR(priv, "Not enough memory to generate traffic log\n");
  2961. /**************************
  2962. * 2. Initializing PCI bus
  2963. **************************/
  2964. pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 |
  2965. PCIE_LINK_STATE_CLKPM);
  2966. if (pci_enable_device(pdev)) {
  2967. err = -ENODEV;
  2968. goto out_ieee80211_free_hw;
  2969. }
  2970. pci_set_master(pdev);
  2971. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(36));
  2972. if (!err)
  2973. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(36));
  2974. if (err) {
  2975. err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  2976. if (!err)
  2977. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
  2978. /* both attempts failed: */
  2979. if (err) {
  2980. IWL_WARN(priv, "No suitable DMA available.\n");
  2981. goto out_pci_disable_device;
  2982. }
  2983. }
  2984. err = pci_request_regions(pdev, DRV_NAME);
  2985. if (err)
  2986. goto out_pci_disable_device;
  2987. pci_set_drvdata(pdev, priv);
  2988. /***********************
  2989. * 3. Read REV register
  2990. ***********************/
  2991. priv->hw_base = pci_iomap(pdev, 0, 0);
  2992. if (!priv->hw_base) {
  2993. err = -ENODEV;
  2994. goto out_pci_release_regions;
  2995. }
  2996. IWL_DEBUG_INFO(priv, "pci_resource_len = 0x%08llx\n",
  2997. (unsigned long long) pci_resource_len(pdev, 0));
  2998. IWL_DEBUG_INFO(priv, "pci_resource_base = %p\n", priv->hw_base);
  2999. /* these spin locks will be used in apm_ops.init and EEPROM access
  3000. * we should init now
  3001. */
  3002. spin_lock_init(&priv->reg_lock);
  3003. spin_lock_init(&priv->lock);
  3004. /*
  3005. * stop and reset the on-board processor just in case it is in a
  3006. * strange state ... like being left stranded by a primary kernel
  3007. * and this is now the kdump kernel trying to start up
  3008. */
  3009. iwl_write32(priv, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET);
  3010. hw_rev = iwl_hw_detect(priv);
  3011. IWL_INFO(priv, "Detected %s, REV=0x%X\n",
  3012. priv->cfg->name, hw_rev);
  3013. /* We disable the RETRY_TIMEOUT register (0x41) to keep
  3014. * PCI Tx retries from interfering with C3 CPU state */
  3015. pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00);
  3016. if (iwl_prepare_card_hw(priv)) {
  3017. IWL_WARN(priv, "Failed, HW not ready\n");
  3018. goto out_iounmap;
  3019. }
  3020. /*****************
  3021. * 4. Read EEPROM
  3022. *****************/
  3023. /* Read the EEPROM */
  3024. err = iwl_eeprom_init(priv, hw_rev);
  3025. if (err) {
  3026. IWL_ERR(priv, "Unable to init EEPROM\n");
  3027. goto out_iounmap;
  3028. }
  3029. err = iwl_eeprom_check_version(priv);
  3030. if (err)
  3031. goto out_free_eeprom;
  3032. err = iwl_eeprom_check_sku(priv);
  3033. if (err)
  3034. goto out_free_eeprom;
  3035. /* extract MAC Address */
  3036. iwl_eeprom_get_mac(priv, priv->addresses[0].addr);
  3037. IWL_DEBUG_INFO(priv, "MAC address: %pM\n", priv->addresses[0].addr);
  3038. priv->hw->wiphy->addresses = priv->addresses;
  3039. priv->hw->wiphy->n_addresses = 1;
  3040. num_mac = iwl_eeprom_query16(priv, EEPROM_NUM_MAC_ADDRESS);
  3041. if (num_mac > 1) {
  3042. memcpy(priv->addresses[1].addr, priv->addresses[0].addr,
  3043. ETH_ALEN);
  3044. priv->addresses[1].addr[5]++;
  3045. priv->hw->wiphy->n_addresses++;
  3046. }
  3047. /* initialize all valid contexts */
  3048. iwl_init_context(priv);
  3049. /************************
  3050. * 5. Setup HW constants
  3051. ************************/
  3052. if (iwl_set_hw_params(priv)) {
  3053. IWL_ERR(priv, "failed to set hw parameters\n");
  3054. goto out_free_eeprom;
  3055. }
  3056. /*******************
  3057. * 6. Setup priv
  3058. *******************/
  3059. err = iwl_init_drv(priv);
  3060. if (err)
  3061. goto out_free_eeprom;
  3062. /* At this point both hw and priv are initialized. */
  3063. /********************
  3064. * 7. Setup services
  3065. ********************/
  3066. pci_enable_msi(priv->pci_dev);
  3067. iwl_alloc_isr_ict(priv);
  3068. err = request_irq(priv->pci_dev->irq, iwl_isr_ict,
  3069. IRQF_SHARED, DRV_NAME, priv);
  3070. if (err) {
  3071. IWL_ERR(priv, "Error allocating IRQ %d\n", priv->pci_dev->irq);
  3072. goto out_disable_msi;
  3073. }
  3074. iwl_setup_deferred_work(priv);
  3075. iwl_setup_rx_handlers(priv);
  3076. iwl_testmode_init(priv);
  3077. /*********************************************
  3078. * 8. Enable interrupts and read RFKILL state
  3079. *********************************************/
  3080. /* enable rfkill interrupt: hw bug w/a */
  3081. pci_read_config_word(priv->pci_dev, PCI_COMMAND, &pci_cmd);
  3082. if (pci_cmd & PCI_COMMAND_INTX_DISABLE) {
  3083. pci_cmd &= ~PCI_COMMAND_INTX_DISABLE;
  3084. pci_write_config_word(priv->pci_dev, PCI_COMMAND, pci_cmd);
  3085. }
  3086. iwl_enable_rfkill_int(priv);
  3087. /* If platform's RF_KILL switch is NOT set to KILL */
  3088. if (iwl_read32(priv, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)
  3089. clear_bit(STATUS_RF_KILL_HW, &priv->status);
  3090. else
  3091. set_bit(STATUS_RF_KILL_HW, &priv->status);
  3092. wiphy_rfkill_set_hw_state(priv->hw->wiphy,
  3093. test_bit(STATUS_RF_KILL_HW, &priv->status));
  3094. iwl_power_initialize(priv);
  3095. iwl_tt_initialize(priv);
  3096. init_completion(&priv->_agn.firmware_loading_complete);
  3097. err = iwl_request_firmware(priv, true);
  3098. if (err)
  3099. goto out_destroy_workqueue;
  3100. return 0;
  3101. out_destroy_workqueue:
  3102. destroy_workqueue(priv->workqueue);
  3103. priv->workqueue = NULL;
  3104. free_irq(priv->pci_dev->irq, priv);
  3105. out_disable_msi:
  3106. iwl_free_isr_ict(priv);
  3107. pci_disable_msi(priv->pci_dev);
  3108. iwl_uninit_drv(priv);
  3109. out_free_eeprom:
  3110. iwl_eeprom_free(priv);
  3111. out_iounmap:
  3112. pci_iounmap(pdev, priv->hw_base);
  3113. out_pci_release_regions:
  3114. pci_set_drvdata(pdev, NULL);
  3115. pci_release_regions(pdev);
  3116. out_pci_disable_device:
  3117. pci_disable_device(pdev);
  3118. out_ieee80211_free_hw:
  3119. iwl_free_traffic_mem(priv);
  3120. ieee80211_free_hw(priv->hw);
  3121. out:
  3122. return err;
  3123. }
  3124. static void __devexit iwl_pci_remove(struct pci_dev *pdev)
  3125. {
  3126. struct iwl_priv *priv = pci_get_drvdata(pdev);
  3127. unsigned long flags;
  3128. if (!priv)
  3129. return;
  3130. wait_for_completion(&priv->_agn.firmware_loading_complete);
  3131. IWL_DEBUG_INFO(priv, "*** UNLOAD DRIVER ***\n");
  3132. iwl_dbgfs_unregister(priv);
  3133. sysfs_remove_group(&pdev->dev.kobj, &iwl_attribute_group);
  3134. /* ieee80211_unregister_hw call wil cause iwl_mac_stop to
  3135. * to be called and iwl_down since we are removing the device
  3136. * we need to set STATUS_EXIT_PENDING bit.
  3137. */
  3138. set_bit(STATUS_EXIT_PENDING, &priv->status);
  3139. iwl_testmode_cleanup(priv);
  3140. iwl_leds_exit(priv);
  3141. if (priv->mac80211_registered) {
  3142. ieee80211_unregister_hw(priv->hw);
  3143. priv->mac80211_registered = 0;
  3144. }
  3145. /* Reset to low power before unloading driver. */
  3146. iwl_apm_stop(priv);
  3147. iwl_tt_exit(priv);
  3148. /* make sure we flush any pending irq or
  3149. * tasklet for the driver
  3150. */
  3151. spin_lock_irqsave(&priv->lock, flags);
  3152. iwl_disable_interrupts(priv);
  3153. spin_unlock_irqrestore(&priv->lock, flags);
  3154. iwl_synchronize_irq(priv);
  3155. iwl_dealloc_ucode_pci(priv);
  3156. if (priv->rxq.bd)
  3157. iwlagn_rx_queue_free(priv, &priv->rxq);
  3158. iwlagn_hw_txq_ctx_free(priv);
  3159. iwl_eeprom_free(priv);
  3160. /*netif_stop_queue(dev); */
  3161. flush_workqueue(priv->workqueue);
  3162. /* ieee80211_unregister_hw calls iwl_mac_stop, which flushes
  3163. * priv->workqueue... so we can't take down the workqueue
  3164. * until now... */
  3165. destroy_workqueue(priv->workqueue);
  3166. priv->workqueue = NULL;
  3167. iwl_free_traffic_mem(priv);
  3168. free_irq(priv->pci_dev->irq, priv);
  3169. pci_disable_msi(priv->pci_dev);
  3170. pci_iounmap(pdev, priv->hw_base);
  3171. pci_release_regions(pdev);
  3172. pci_disable_device(pdev);
  3173. pci_set_drvdata(pdev, NULL);
  3174. iwl_uninit_drv(priv);
  3175. iwl_free_isr_ict(priv);
  3176. dev_kfree_skb(priv->beacon_skb);
  3177. ieee80211_free_hw(priv->hw);
  3178. }
  3179. /*****************************************************************************
  3180. *
  3181. * driver and module entry point
  3182. *
  3183. *****************************************************************************/
  3184. /* Hardware specific file defines the PCI IDs table for that hardware module */
  3185. static DEFINE_PCI_DEVICE_TABLE(iwl_hw_card_ids) = {
  3186. {IWL_PCI_DEVICE(0x4232, 0x1201, iwl5100_agn_cfg)}, /* Mini Card */
  3187. {IWL_PCI_DEVICE(0x4232, 0x1301, iwl5100_agn_cfg)}, /* Half Mini Card */
  3188. {IWL_PCI_DEVICE(0x4232, 0x1204, iwl5100_agn_cfg)}, /* Mini Card */
  3189. {IWL_PCI_DEVICE(0x4232, 0x1304, iwl5100_agn_cfg)}, /* Half Mini Card */
  3190. {IWL_PCI_DEVICE(0x4232, 0x1205, iwl5100_bgn_cfg)}, /* Mini Card */
  3191. {IWL_PCI_DEVICE(0x4232, 0x1305, iwl5100_bgn_cfg)}, /* Half Mini Card */
  3192. {IWL_PCI_DEVICE(0x4232, 0x1206, iwl5100_abg_cfg)}, /* Mini Card */
  3193. {IWL_PCI_DEVICE(0x4232, 0x1306, iwl5100_abg_cfg)}, /* Half Mini Card */
  3194. {IWL_PCI_DEVICE(0x4232, 0x1221, iwl5100_agn_cfg)}, /* Mini Card */
  3195. {IWL_PCI_DEVICE(0x4232, 0x1321, iwl5100_agn_cfg)}, /* Half Mini Card */
  3196. {IWL_PCI_DEVICE(0x4232, 0x1224, iwl5100_agn_cfg)}, /* Mini Card */
  3197. {IWL_PCI_DEVICE(0x4232, 0x1324, iwl5100_agn_cfg)}, /* Half Mini Card */
  3198. {IWL_PCI_DEVICE(0x4232, 0x1225, iwl5100_bgn_cfg)}, /* Mini Card */
  3199. {IWL_PCI_DEVICE(0x4232, 0x1325, iwl5100_bgn_cfg)}, /* Half Mini Card */
  3200. {IWL_PCI_DEVICE(0x4232, 0x1226, iwl5100_abg_cfg)}, /* Mini Card */
  3201. {IWL_PCI_DEVICE(0x4232, 0x1326, iwl5100_abg_cfg)}, /* Half Mini Card */
  3202. {IWL_PCI_DEVICE(0x4237, 0x1211, iwl5100_agn_cfg)}, /* Mini Card */
  3203. {IWL_PCI_DEVICE(0x4237, 0x1311, iwl5100_agn_cfg)}, /* Half Mini Card */
  3204. {IWL_PCI_DEVICE(0x4237, 0x1214, iwl5100_agn_cfg)}, /* Mini Card */
  3205. {IWL_PCI_DEVICE(0x4237, 0x1314, iwl5100_agn_cfg)}, /* Half Mini Card */
  3206. {IWL_PCI_DEVICE(0x4237, 0x1215, iwl5100_bgn_cfg)}, /* Mini Card */
  3207. {IWL_PCI_DEVICE(0x4237, 0x1315, iwl5100_bgn_cfg)}, /* Half Mini Card */
  3208. {IWL_PCI_DEVICE(0x4237, 0x1216, iwl5100_abg_cfg)}, /* Mini Card */
  3209. {IWL_PCI_DEVICE(0x4237, 0x1316, iwl5100_abg_cfg)}, /* Half Mini Card */
  3210. /* 5300 Series WiFi */
  3211. {IWL_PCI_DEVICE(0x4235, 0x1021, iwl5300_agn_cfg)}, /* Mini Card */
  3212. {IWL_PCI_DEVICE(0x4235, 0x1121, iwl5300_agn_cfg)}, /* Half Mini Card */
  3213. {IWL_PCI_DEVICE(0x4235, 0x1024, iwl5300_agn_cfg)}, /* Mini Card */
  3214. {IWL_PCI_DEVICE(0x4235, 0x1124, iwl5300_agn_cfg)}, /* Half Mini Card */
  3215. {IWL_PCI_DEVICE(0x4235, 0x1001, iwl5300_agn_cfg)}, /* Mini Card */
  3216. {IWL_PCI_DEVICE(0x4235, 0x1101, iwl5300_agn_cfg)}, /* Half Mini Card */
  3217. {IWL_PCI_DEVICE(0x4235, 0x1004, iwl5300_agn_cfg)}, /* Mini Card */
  3218. {IWL_PCI_DEVICE(0x4235, 0x1104, iwl5300_agn_cfg)}, /* Half Mini Card */
  3219. {IWL_PCI_DEVICE(0x4236, 0x1011, iwl5300_agn_cfg)}, /* Mini Card */
  3220. {IWL_PCI_DEVICE(0x4236, 0x1111, iwl5300_agn_cfg)}, /* Half Mini Card */
  3221. {IWL_PCI_DEVICE(0x4236, 0x1014, iwl5300_agn_cfg)}, /* Mini Card */
  3222. {IWL_PCI_DEVICE(0x4236, 0x1114, iwl5300_agn_cfg)}, /* Half Mini Card */
  3223. /* 5350 Series WiFi/WiMax */
  3224. {IWL_PCI_DEVICE(0x423A, 0x1001, iwl5350_agn_cfg)}, /* Mini Card */
  3225. {IWL_PCI_DEVICE(0x423A, 0x1021, iwl5350_agn_cfg)}, /* Mini Card */
  3226. {IWL_PCI_DEVICE(0x423B, 0x1011, iwl5350_agn_cfg)}, /* Mini Card */
  3227. /* 5150 Series Wifi/WiMax */
  3228. {IWL_PCI_DEVICE(0x423C, 0x1201, iwl5150_agn_cfg)}, /* Mini Card */
  3229. {IWL_PCI_DEVICE(0x423C, 0x1301, iwl5150_agn_cfg)}, /* Half Mini Card */
  3230. {IWL_PCI_DEVICE(0x423C, 0x1206, iwl5150_abg_cfg)}, /* Mini Card */
  3231. {IWL_PCI_DEVICE(0x423C, 0x1306, iwl5150_abg_cfg)}, /* Half Mini Card */
  3232. {IWL_PCI_DEVICE(0x423C, 0x1221, iwl5150_agn_cfg)}, /* Mini Card */
  3233. {IWL_PCI_DEVICE(0x423C, 0x1321, iwl5150_agn_cfg)}, /* Half Mini Card */
  3234. {IWL_PCI_DEVICE(0x423D, 0x1211, iwl5150_agn_cfg)}, /* Mini Card */
  3235. {IWL_PCI_DEVICE(0x423D, 0x1311, iwl5150_agn_cfg)}, /* Half Mini Card */
  3236. {IWL_PCI_DEVICE(0x423D, 0x1216, iwl5150_abg_cfg)}, /* Mini Card */
  3237. {IWL_PCI_DEVICE(0x423D, 0x1316, iwl5150_abg_cfg)}, /* Half Mini Card */
  3238. /* 6x00 Series */
  3239. {IWL_PCI_DEVICE(0x422B, 0x1101, iwl6000_3agn_cfg)},
  3240. {IWL_PCI_DEVICE(0x422B, 0x1121, iwl6000_3agn_cfg)},
  3241. {IWL_PCI_DEVICE(0x422C, 0x1301, iwl6000i_2agn_cfg)},
  3242. {IWL_PCI_DEVICE(0x422C, 0x1306, iwl6000i_2abg_cfg)},
  3243. {IWL_PCI_DEVICE(0x422C, 0x1307, iwl6000i_2bg_cfg)},
  3244. {IWL_PCI_DEVICE(0x422C, 0x1321, iwl6000i_2agn_cfg)},
  3245. {IWL_PCI_DEVICE(0x422C, 0x1326, iwl6000i_2abg_cfg)},
  3246. {IWL_PCI_DEVICE(0x4238, 0x1111, iwl6000_3agn_cfg)},
  3247. {IWL_PCI_DEVICE(0x4239, 0x1311, iwl6000i_2agn_cfg)},
  3248. {IWL_PCI_DEVICE(0x4239, 0x1316, iwl6000i_2abg_cfg)},
  3249. /* 6x05 Series */
  3250. {IWL_PCI_DEVICE(0x0082, 0x1301, iwl6005_2agn_cfg)},
  3251. {IWL_PCI_DEVICE(0x0082, 0x1306, iwl6005_2abg_cfg)},
  3252. {IWL_PCI_DEVICE(0x0082, 0x1307, iwl6005_2bg_cfg)},
  3253. {IWL_PCI_DEVICE(0x0082, 0x1321, iwl6005_2agn_cfg)},
  3254. {IWL_PCI_DEVICE(0x0082, 0x1326, iwl6005_2abg_cfg)},
  3255. {IWL_PCI_DEVICE(0x0085, 0x1311, iwl6005_2agn_cfg)},
  3256. {IWL_PCI_DEVICE(0x0085, 0x1316, iwl6005_2abg_cfg)},
  3257. /* 6x30 Series */
  3258. {IWL_PCI_DEVICE(0x008A, 0x5305, iwl1030_bgn_cfg)},
  3259. {IWL_PCI_DEVICE(0x008A, 0x5307, iwl1030_bg_cfg)},
  3260. {IWL_PCI_DEVICE(0x008A, 0x5325, iwl1030_bgn_cfg)},
  3261. {IWL_PCI_DEVICE(0x008A, 0x5327, iwl1030_bg_cfg)},
  3262. {IWL_PCI_DEVICE(0x008B, 0x5315, iwl1030_bgn_cfg)},
  3263. {IWL_PCI_DEVICE(0x008B, 0x5317, iwl1030_bg_cfg)},
  3264. {IWL_PCI_DEVICE(0x0090, 0x5211, iwl6030_2agn_cfg)},
  3265. {IWL_PCI_DEVICE(0x0090, 0x5215, iwl6030_2bgn_cfg)},
  3266. {IWL_PCI_DEVICE(0x0090, 0x5216, iwl6030_2abg_cfg)},
  3267. {IWL_PCI_DEVICE(0x0091, 0x5201, iwl6030_2agn_cfg)},
  3268. {IWL_PCI_DEVICE(0x0091, 0x5205, iwl6030_2bgn_cfg)},
  3269. {IWL_PCI_DEVICE(0x0091, 0x5206, iwl6030_2abg_cfg)},
  3270. {IWL_PCI_DEVICE(0x0091, 0x5207, iwl6030_2bg_cfg)},
  3271. {IWL_PCI_DEVICE(0x0091, 0x5221, iwl6030_2agn_cfg)},
  3272. {IWL_PCI_DEVICE(0x0091, 0x5225, iwl6030_2bgn_cfg)},
  3273. {IWL_PCI_DEVICE(0x0091, 0x5226, iwl6030_2abg_cfg)},
  3274. /* 6x50 WiFi/WiMax Series */
  3275. {IWL_PCI_DEVICE(0x0087, 0x1301, iwl6050_2agn_cfg)},
  3276. {IWL_PCI_DEVICE(0x0087, 0x1306, iwl6050_2abg_cfg)},
  3277. {IWL_PCI_DEVICE(0x0087, 0x1321, iwl6050_2agn_cfg)},
  3278. {IWL_PCI_DEVICE(0x0087, 0x1326, iwl6050_2abg_cfg)},
  3279. {IWL_PCI_DEVICE(0x0089, 0x1311, iwl6050_2agn_cfg)},
  3280. {IWL_PCI_DEVICE(0x0089, 0x1316, iwl6050_2abg_cfg)},
  3281. /* 6150 WiFi/WiMax Series */
  3282. {IWL_PCI_DEVICE(0x0885, 0x1305, iwl6150_bgn_cfg)},
  3283. {IWL_PCI_DEVICE(0x0885, 0x1307, iwl6150_bg_cfg)},
  3284. {IWL_PCI_DEVICE(0x0885, 0x1325, iwl6150_bgn_cfg)},
  3285. {IWL_PCI_DEVICE(0x0885, 0x1327, iwl6150_bg_cfg)},
  3286. {IWL_PCI_DEVICE(0x0886, 0x1315, iwl6150_bgn_cfg)},
  3287. {IWL_PCI_DEVICE(0x0886, 0x1317, iwl6150_bg_cfg)},
  3288. /* 1000 Series WiFi */
  3289. {IWL_PCI_DEVICE(0x0083, 0x1205, iwl1000_bgn_cfg)},
  3290. {IWL_PCI_DEVICE(0x0083, 0x1305, iwl1000_bgn_cfg)},
  3291. {IWL_PCI_DEVICE(0x0083, 0x1225, iwl1000_bgn_cfg)},
  3292. {IWL_PCI_DEVICE(0x0083, 0x1325, iwl1000_bgn_cfg)},
  3293. {IWL_PCI_DEVICE(0x0084, 0x1215, iwl1000_bgn_cfg)},
  3294. {IWL_PCI_DEVICE(0x0084, 0x1315, iwl1000_bgn_cfg)},
  3295. {IWL_PCI_DEVICE(0x0083, 0x1206, iwl1000_bg_cfg)},
  3296. {IWL_PCI_DEVICE(0x0083, 0x1306, iwl1000_bg_cfg)},
  3297. {IWL_PCI_DEVICE(0x0083, 0x1226, iwl1000_bg_cfg)},
  3298. {IWL_PCI_DEVICE(0x0083, 0x1326, iwl1000_bg_cfg)},
  3299. {IWL_PCI_DEVICE(0x0084, 0x1216, iwl1000_bg_cfg)},
  3300. {IWL_PCI_DEVICE(0x0084, 0x1316, iwl1000_bg_cfg)},
  3301. /* 100 Series WiFi */
  3302. {IWL_PCI_DEVICE(0x08AE, 0x1005, iwl100_bgn_cfg)},
  3303. {IWL_PCI_DEVICE(0x08AE, 0x1007, iwl100_bg_cfg)},
  3304. {IWL_PCI_DEVICE(0x08AF, 0x1015, iwl100_bgn_cfg)},
  3305. {IWL_PCI_DEVICE(0x08AF, 0x1017, iwl100_bg_cfg)},
  3306. {IWL_PCI_DEVICE(0x08AE, 0x1025, iwl100_bgn_cfg)},
  3307. {IWL_PCI_DEVICE(0x08AE, 0x1027, iwl100_bg_cfg)},
  3308. /* 130 Series WiFi */
  3309. {IWL_PCI_DEVICE(0x0896, 0x5005, iwl130_bgn_cfg)},
  3310. {IWL_PCI_DEVICE(0x0896, 0x5007, iwl130_bg_cfg)},
  3311. {IWL_PCI_DEVICE(0x0897, 0x5015, iwl130_bgn_cfg)},
  3312. {IWL_PCI_DEVICE(0x0897, 0x5017, iwl130_bg_cfg)},
  3313. {IWL_PCI_DEVICE(0x0896, 0x5025, iwl130_bgn_cfg)},
  3314. {IWL_PCI_DEVICE(0x0896, 0x5027, iwl130_bg_cfg)},
  3315. /* 2x00 Series */
  3316. {IWL_PCI_DEVICE(0x0890, 0x4022, iwl2000_2bgn_cfg)},
  3317. {IWL_PCI_DEVICE(0x0891, 0x4222, iwl2000_2bgn_cfg)},
  3318. {IWL_PCI_DEVICE(0x0890, 0x4422, iwl2000_2bgn_cfg)},
  3319. {IWL_PCI_DEVICE(0x0890, 0x4026, iwl2000_2bg_cfg)},
  3320. {IWL_PCI_DEVICE(0x0891, 0x4226, iwl2000_2bg_cfg)},
  3321. {IWL_PCI_DEVICE(0x0890, 0x4426, iwl2000_2bg_cfg)},
  3322. /* 2x30 Series */
  3323. {IWL_PCI_DEVICE(0x0887, 0x4062, iwl2030_2bgn_cfg)},
  3324. {IWL_PCI_DEVICE(0x0888, 0x4262, iwl2030_2bgn_cfg)},
  3325. {IWL_PCI_DEVICE(0x0887, 0x4462, iwl2030_2bgn_cfg)},
  3326. {IWL_PCI_DEVICE(0x0887, 0x4066, iwl2030_2bg_cfg)},
  3327. {IWL_PCI_DEVICE(0x0888, 0x4266, iwl2030_2bg_cfg)},
  3328. {IWL_PCI_DEVICE(0x0887, 0x4466, iwl2030_2bg_cfg)},
  3329. /* 6x35 Series */
  3330. {IWL_PCI_DEVICE(0x088E, 0x4060, iwl6035_2agn_cfg)},
  3331. {IWL_PCI_DEVICE(0x088F, 0x4260, iwl6035_2agn_cfg)},
  3332. {IWL_PCI_DEVICE(0x088E, 0x4460, iwl6035_2agn_cfg)},
  3333. {IWL_PCI_DEVICE(0x088E, 0x4064, iwl6035_2abg_cfg)},
  3334. {IWL_PCI_DEVICE(0x088F, 0x4264, iwl6035_2abg_cfg)},
  3335. {IWL_PCI_DEVICE(0x088E, 0x4464, iwl6035_2abg_cfg)},
  3336. {IWL_PCI_DEVICE(0x088E, 0x4066, iwl6035_2bg_cfg)},
  3337. {IWL_PCI_DEVICE(0x088F, 0x4266, iwl6035_2bg_cfg)},
  3338. {IWL_PCI_DEVICE(0x088E, 0x4466, iwl6035_2bg_cfg)},
  3339. /* 105 Series */
  3340. {IWL_PCI_DEVICE(0x0894, 0x0022, iwl105_bgn_cfg)},
  3341. {IWL_PCI_DEVICE(0x0895, 0x0222, iwl105_bgn_cfg)},
  3342. {IWL_PCI_DEVICE(0x0894, 0x0422, iwl105_bgn_cfg)},
  3343. {IWL_PCI_DEVICE(0x0894, 0x0026, iwl105_bg_cfg)},
  3344. {IWL_PCI_DEVICE(0x0895, 0x0226, iwl105_bg_cfg)},
  3345. {IWL_PCI_DEVICE(0x0894, 0x0426, iwl105_bg_cfg)},
  3346. /* 135 Series */
  3347. {IWL_PCI_DEVICE(0x0892, 0x0062, iwl135_bgn_cfg)},
  3348. {IWL_PCI_DEVICE(0x0893, 0x0262, iwl135_bgn_cfg)},
  3349. {IWL_PCI_DEVICE(0x0892, 0x0462, iwl135_bgn_cfg)},
  3350. {IWL_PCI_DEVICE(0x0892, 0x0066, iwl135_bg_cfg)},
  3351. {IWL_PCI_DEVICE(0x0893, 0x0266, iwl135_bg_cfg)},
  3352. {IWL_PCI_DEVICE(0x0892, 0x0466, iwl135_bg_cfg)},
  3353. {0}
  3354. };
  3355. MODULE_DEVICE_TABLE(pci, iwl_hw_card_ids);
  3356. static struct pci_driver iwl_driver = {
  3357. .name = DRV_NAME,
  3358. .id_table = iwl_hw_card_ids,
  3359. .probe = iwl_pci_probe,
  3360. .remove = __devexit_p(iwl_pci_remove),
  3361. .driver.pm = IWL_PM_OPS,
  3362. };
  3363. static int __init iwl_init(void)
  3364. {
  3365. int ret;
  3366. pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n");
  3367. pr_info(DRV_COPYRIGHT "\n");
  3368. ret = iwlagn_rate_control_register();
  3369. if (ret) {
  3370. pr_err("Unable to register rate control algorithm: %d\n", ret);
  3371. return ret;
  3372. }
  3373. ret = pci_register_driver(&iwl_driver);
  3374. if (ret) {
  3375. pr_err("Unable to initialize PCI module\n");
  3376. goto error_register;
  3377. }
  3378. return ret;
  3379. error_register:
  3380. iwlagn_rate_control_unregister();
  3381. return ret;
  3382. }
  3383. static void __exit iwl_exit(void)
  3384. {
  3385. pci_unregister_driver(&iwl_driver);
  3386. iwlagn_rate_control_unregister();
  3387. }
  3388. module_exit(iwl_exit);
  3389. module_init(iwl_init);
  3390. #ifdef CONFIG_IWLWIFI_DEBUG
  3391. module_param_named(debug, iwl_debug_level, uint, S_IRUGO | S_IWUSR);
  3392. MODULE_PARM_DESC(debug, "debug output mask");
  3393. #endif
  3394. module_param_named(swcrypto, iwlagn_mod_params.sw_crypto, int, S_IRUGO);
  3395. MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])");
  3396. module_param_named(queues_num, iwlagn_mod_params.num_of_queues, int, S_IRUGO);
  3397. MODULE_PARM_DESC(queues_num, "number of hw queues.");
  3398. module_param_named(11n_disable, iwlagn_mod_params.disable_11n, int, S_IRUGO);
  3399. MODULE_PARM_DESC(11n_disable, "disable 11n functionality");
  3400. module_param_named(amsdu_size_8K, iwlagn_mod_params.amsdu_size_8K,
  3401. int, S_IRUGO);
  3402. MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size");
  3403. module_param_named(fw_restart, iwlagn_mod_params.restart_fw, int, S_IRUGO);
  3404. MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
  3405. module_param_named(ucode_alternative, iwlagn_wanted_ucode_alternative, int,
  3406. S_IRUGO);
  3407. MODULE_PARM_DESC(ucode_alternative,
  3408. "specify ucode alternative to use from ucode file");
  3409. module_param_named(antenna_coupling, iwlagn_ant_coupling, int, S_IRUGO);
  3410. MODULE_PARM_DESC(antenna_coupling,
  3411. "specify antenna coupling in dB (defualt: 0 dB)");
  3412. module_param_named(bt_ch_inhibition, iwlagn_bt_ch_announce, bool, S_IRUGO);
  3413. MODULE_PARM_DESC(bt_ch_inhibition,
  3414. "Disable BT channel inhibition (default: enable)");
  3415. module_param_named(plcp_check, iwlagn_mod_params.plcp_check, bool, S_IRUGO);
  3416. MODULE_PARM_DESC(plcp_check, "Check plcp health (default: 1 [enabled])");
  3417. module_param_named(ack_check, iwlagn_mod_params.ack_check, bool, S_IRUGO);
  3418. MODULE_PARM_DESC(ack_check, "Check ack health (default: 0 [disabled])");
  3419. /*
  3420. * set bt_coex_active to true, uCode will do kill/defer
  3421. * every time the priority line is asserted (BT is sending signals on the
  3422. * priority line in the PCIx).
  3423. * set bt_coex_active to false, uCode will ignore the BT activity and
  3424. * perform the normal operation
  3425. *
  3426. * User might experience transmit issue on some platform due to WiFi/BT
  3427. * co-exist problem. The possible behaviors are:
  3428. * Able to scan and finding all the available AP
  3429. * Not able to associate with any AP
  3430. * On those platforms, WiFi communication can be restored by set
  3431. * "bt_coex_active" module parameter to "false"
  3432. *
  3433. * default: bt_coex_active = true (BT_COEX_ENABLE)
  3434. */
  3435. module_param_named(bt_coex_active, iwlagn_mod_params.bt_coex_active,
  3436. bool, S_IRUGO);
  3437. MODULE_PARM_DESC(bt_coex_active, "enable wifi/bt co-exist (default: enable)");
  3438. module_param_named(led_mode, iwlagn_mod_params.led_mode, int, S_IRUGO);
  3439. MODULE_PARM_DESC(led_mode, "0=system default, "
  3440. "1=On(RF On)/Off(RF Off), 2=blinking (default: 0)");
  3441. /*
  3442. * For now, keep using power level 1 instead of automatically
  3443. * adjusting ...
  3444. */
  3445. module_param_named(no_sleep_autoadjust, iwlagn_mod_params.no_sleep_autoadjust,
  3446. bool, S_IRUGO);
  3447. MODULE_PARM_DESC(no_sleep_autoadjust,
  3448. "don't automatically adjust sleep level "
  3449. "according to maximum network latency (default: true)");