main.c 52 KB

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  1. /*
  2. * Copyright (c) 2008-2009 Atheros Communications Inc.
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/nl80211.h>
  17. #include "ath9k.h"
  18. #include "btcoex.h"
  19. static void ath_cache_conf_rate(struct ath_softc *sc,
  20. struct ieee80211_conf *conf)
  21. {
  22. switch (conf->channel->band) {
  23. case IEEE80211_BAND_2GHZ:
  24. if (conf_is_ht20(conf))
  25. sc->cur_rate_mode = ATH9K_MODE_11NG_HT20;
  26. else if (conf_is_ht40_minus(conf))
  27. sc->cur_rate_mode = ATH9K_MODE_11NG_HT40MINUS;
  28. else if (conf_is_ht40_plus(conf))
  29. sc->cur_rate_mode = ATH9K_MODE_11NG_HT40PLUS;
  30. else
  31. sc->cur_rate_mode = ATH9K_MODE_11G;
  32. break;
  33. case IEEE80211_BAND_5GHZ:
  34. if (conf_is_ht20(conf))
  35. sc->cur_rate_mode = ATH9K_MODE_11NA_HT20;
  36. else if (conf_is_ht40_minus(conf))
  37. sc->cur_rate_mode = ATH9K_MODE_11NA_HT40MINUS;
  38. else if (conf_is_ht40_plus(conf))
  39. sc->cur_rate_mode = ATH9K_MODE_11NA_HT40PLUS;
  40. else
  41. sc->cur_rate_mode = ATH9K_MODE_11A;
  42. break;
  43. default:
  44. BUG_ON(1);
  45. break;
  46. }
  47. }
  48. static void ath_update_txpow(struct ath_softc *sc)
  49. {
  50. struct ath_hw *ah = sc->sc_ah;
  51. if (sc->curtxpow != sc->config.txpowlimit) {
  52. ath9k_hw_set_txpowerlimit(ah, sc->config.txpowlimit);
  53. /* read back in case value is clamped */
  54. sc->curtxpow = ath9k_hw_regulatory(ah)->power_limit;
  55. }
  56. }
  57. static u8 parse_mpdudensity(u8 mpdudensity)
  58. {
  59. /*
  60. * 802.11n D2.0 defined values for "Minimum MPDU Start Spacing":
  61. * 0 for no restriction
  62. * 1 for 1/4 us
  63. * 2 for 1/2 us
  64. * 3 for 1 us
  65. * 4 for 2 us
  66. * 5 for 4 us
  67. * 6 for 8 us
  68. * 7 for 16 us
  69. */
  70. switch (mpdudensity) {
  71. case 0:
  72. return 0;
  73. case 1:
  74. case 2:
  75. case 3:
  76. /* Our lower layer calculations limit our precision to
  77. 1 microsecond */
  78. return 1;
  79. case 4:
  80. return 2;
  81. case 5:
  82. return 4;
  83. case 6:
  84. return 8;
  85. case 7:
  86. return 16;
  87. default:
  88. return 0;
  89. }
  90. }
  91. static struct ath9k_channel *ath_get_curchannel(struct ath_softc *sc,
  92. struct ieee80211_hw *hw)
  93. {
  94. struct ieee80211_channel *curchan = hw->conf.channel;
  95. struct ath9k_channel *channel;
  96. u8 chan_idx;
  97. chan_idx = curchan->hw_value;
  98. channel = &sc->sc_ah->channels[chan_idx];
  99. ath9k_update_ichannel(sc, hw, channel);
  100. return channel;
  101. }
  102. bool ath9k_setpower(struct ath_softc *sc, enum ath9k_power_mode mode)
  103. {
  104. unsigned long flags;
  105. bool ret;
  106. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  107. ret = ath9k_hw_setpower(sc->sc_ah, mode);
  108. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  109. return ret;
  110. }
  111. void ath9k_ps_wakeup(struct ath_softc *sc)
  112. {
  113. unsigned long flags;
  114. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  115. if (++sc->ps_usecount != 1)
  116. goto unlock;
  117. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
  118. unlock:
  119. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  120. }
  121. void ath9k_ps_restore(struct ath_softc *sc)
  122. {
  123. unsigned long flags;
  124. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  125. if (--sc->ps_usecount != 0)
  126. goto unlock;
  127. if (sc->ps_idle)
  128. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_FULL_SLEEP);
  129. else if (sc->ps_enabled &&
  130. !(sc->ps_flags & (PS_WAIT_FOR_BEACON |
  131. PS_WAIT_FOR_CAB |
  132. PS_WAIT_FOR_PSPOLL_DATA |
  133. PS_WAIT_FOR_TX_ACK)))
  134. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_NETWORK_SLEEP);
  135. unlock:
  136. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  137. }
  138. static void ath_start_ani(struct ath_common *common)
  139. {
  140. struct ath_hw *ah = common->ah;
  141. unsigned long timestamp = jiffies_to_msecs(jiffies);
  142. struct ath_softc *sc = (struct ath_softc *) common->priv;
  143. if (!(sc->sc_flags & SC_OP_ANI_RUN))
  144. return;
  145. if (sc->sc_flags & SC_OP_OFFCHANNEL)
  146. return;
  147. common->ani.longcal_timer = timestamp;
  148. common->ani.shortcal_timer = timestamp;
  149. common->ani.checkani_timer = timestamp;
  150. mod_timer(&common->ani.timer,
  151. jiffies +
  152. msecs_to_jiffies((u32)ah->config.ani_poll_interval));
  153. }
  154. /*
  155. * Set/change channels. If the channel is really being changed, it's done
  156. * by reseting the chip. To accomplish this we must first cleanup any pending
  157. * DMA, then restart stuff.
  158. */
  159. int ath_set_channel(struct ath_softc *sc, struct ieee80211_hw *hw,
  160. struct ath9k_channel *hchan)
  161. {
  162. struct ath_wiphy *aphy = hw->priv;
  163. struct ath_hw *ah = sc->sc_ah;
  164. struct ath_common *common = ath9k_hw_common(ah);
  165. struct ieee80211_conf *conf = &common->hw->conf;
  166. bool fastcc = true, stopped;
  167. struct ieee80211_channel *channel = hw->conf.channel;
  168. struct ath9k_hw_cal_data *caldata = NULL;
  169. int r;
  170. if (sc->sc_flags & SC_OP_INVALID)
  171. return -EIO;
  172. del_timer_sync(&common->ani.timer);
  173. cancel_work_sync(&sc->paprd_work);
  174. cancel_work_sync(&sc->hw_check_work);
  175. cancel_delayed_work_sync(&sc->tx_complete_work);
  176. ath9k_ps_wakeup(sc);
  177. /*
  178. * This is only performed if the channel settings have
  179. * actually changed.
  180. *
  181. * To switch channels clear any pending DMA operations;
  182. * wait long enough for the RX fifo to drain, reset the
  183. * hardware at the new frequency, and then re-enable
  184. * the relevant bits of the h/w.
  185. */
  186. ath9k_hw_set_interrupts(ah, 0);
  187. ath_drain_all_txq(sc, false);
  188. stopped = ath_stoprecv(sc);
  189. /* XXX: do not flush receive queue here. We don't want
  190. * to flush data frames already in queue because of
  191. * changing channel. */
  192. if (!stopped || !(sc->sc_flags & SC_OP_OFFCHANNEL))
  193. fastcc = false;
  194. if (!(sc->sc_flags & SC_OP_OFFCHANNEL))
  195. caldata = &aphy->caldata;
  196. ath_print(common, ATH_DBG_CONFIG,
  197. "(%u MHz) -> (%u MHz), conf_is_ht40: %d fastcc: %d\n",
  198. sc->sc_ah->curchan->channel,
  199. channel->center_freq, conf_is_ht40(conf),
  200. fastcc);
  201. spin_lock_bh(&sc->sc_resetlock);
  202. r = ath9k_hw_reset(ah, hchan, caldata, fastcc);
  203. if (r) {
  204. ath_print(common, ATH_DBG_FATAL,
  205. "Unable to reset channel (%u MHz), "
  206. "reset status %d\n",
  207. channel->center_freq, r);
  208. spin_unlock_bh(&sc->sc_resetlock);
  209. goto ps_restore;
  210. }
  211. spin_unlock_bh(&sc->sc_resetlock);
  212. if (ath_startrecv(sc) != 0) {
  213. ath_print(common, ATH_DBG_FATAL,
  214. "Unable to restart recv logic\n");
  215. r = -EIO;
  216. goto ps_restore;
  217. }
  218. ath_cache_conf_rate(sc, &hw->conf);
  219. ath_update_txpow(sc);
  220. ath9k_hw_set_interrupts(ah, ah->imask);
  221. if (!(sc->sc_flags & (SC_OP_OFFCHANNEL))) {
  222. ath_beacon_config(sc, NULL);
  223. ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
  224. ath_start_ani(common);
  225. }
  226. ps_restore:
  227. ath9k_ps_restore(sc);
  228. return r;
  229. }
  230. static void ath_paprd_activate(struct ath_softc *sc)
  231. {
  232. struct ath_hw *ah = sc->sc_ah;
  233. struct ath9k_hw_cal_data *caldata = ah->caldata;
  234. struct ath_common *common = ath9k_hw_common(ah);
  235. int chain;
  236. if (!caldata || !caldata->paprd_done)
  237. return;
  238. ath9k_ps_wakeup(sc);
  239. ar9003_paprd_enable(ah, false);
  240. for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
  241. if (!(common->tx_chainmask & BIT(chain)))
  242. continue;
  243. ar9003_paprd_populate_single_table(ah, caldata, chain);
  244. }
  245. ar9003_paprd_enable(ah, true);
  246. ath9k_ps_restore(sc);
  247. }
  248. void ath_paprd_calibrate(struct work_struct *work)
  249. {
  250. struct ath_softc *sc = container_of(work, struct ath_softc, paprd_work);
  251. struct ieee80211_hw *hw = sc->hw;
  252. struct ath_hw *ah = sc->sc_ah;
  253. struct ieee80211_hdr *hdr;
  254. struct sk_buff *skb = NULL;
  255. struct ieee80211_tx_info *tx_info;
  256. int band = hw->conf.channel->band;
  257. struct ieee80211_supported_band *sband = &sc->sbands[band];
  258. struct ath_tx_control txctl;
  259. struct ath9k_hw_cal_data *caldata = ah->caldata;
  260. struct ath_common *common = ath9k_hw_common(ah);
  261. int qnum, ftype;
  262. int chain_ok = 0;
  263. int chain;
  264. int len = 1800;
  265. int time_left;
  266. int i;
  267. if (!caldata)
  268. return;
  269. skb = alloc_skb(len, GFP_KERNEL);
  270. if (!skb)
  271. return;
  272. tx_info = IEEE80211_SKB_CB(skb);
  273. skb_put(skb, len);
  274. memset(skb->data, 0, len);
  275. hdr = (struct ieee80211_hdr *)skb->data;
  276. ftype = IEEE80211_FTYPE_DATA | IEEE80211_STYPE_NULLFUNC;
  277. hdr->frame_control = cpu_to_le16(ftype);
  278. hdr->duration_id = cpu_to_le16(10);
  279. memcpy(hdr->addr1, hw->wiphy->perm_addr, ETH_ALEN);
  280. memcpy(hdr->addr2, hw->wiphy->perm_addr, ETH_ALEN);
  281. memcpy(hdr->addr3, hw->wiphy->perm_addr, ETH_ALEN);
  282. memset(&txctl, 0, sizeof(txctl));
  283. qnum = sc->tx.hwq_map[WME_AC_BE];
  284. txctl.txq = &sc->tx.txq[qnum];
  285. ath9k_ps_wakeup(sc);
  286. ar9003_paprd_init_table(ah);
  287. for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
  288. if (!(common->tx_chainmask & BIT(chain)))
  289. continue;
  290. chain_ok = 0;
  291. memset(tx_info, 0, sizeof(*tx_info));
  292. tx_info->band = band;
  293. for (i = 0; i < 4; i++) {
  294. tx_info->control.rates[i].idx = sband->n_bitrates - 1;
  295. tx_info->control.rates[i].count = 6;
  296. }
  297. init_completion(&sc->paprd_complete);
  298. ar9003_paprd_setup_gain_table(ah, chain);
  299. txctl.paprd = BIT(chain);
  300. if (ath_tx_start(hw, skb, &txctl) != 0)
  301. break;
  302. time_left = wait_for_completion_timeout(&sc->paprd_complete,
  303. msecs_to_jiffies(ATH_PAPRD_TIMEOUT));
  304. if (!time_left) {
  305. ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE,
  306. "Timeout waiting for paprd training on "
  307. "TX chain %d\n",
  308. chain);
  309. goto fail_paprd;
  310. }
  311. if (!ar9003_paprd_is_done(ah))
  312. break;
  313. if (ar9003_paprd_create_curve(ah, caldata, chain) != 0)
  314. break;
  315. chain_ok = 1;
  316. }
  317. kfree_skb(skb);
  318. if (chain_ok) {
  319. caldata->paprd_done = true;
  320. ath_paprd_activate(sc);
  321. }
  322. fail_paprd:
  323. ath9k_ps_restore(sc);
  324. }
  325. /*
  326. * This routine performs the periodic noise floor calibration function
  327. * that is used to adjust and optimize the chip performance. This
  328. * takes environmental changes (location, temperature) into account.
  329. * When the task is complete, it reschedules itself depending on the
  330. * appropriate interval that was calculated.
  331. */
  332. void ath_ani_calibrate(unsigned long data)
  333. {
  334. struct ath_softc *sc = (struct ath_softc *)data;
  335. struct ath_hw *ah = sc->sc_ah;
  336. struct ath_common *common = ath9k_hw_common(ah);
  337. bool longcal = false;
  338. bool shortcal = false;
  339. bool aniflag = false;
  340. unsigned int timestamp = jiffies_to_msecs(jiffies);
  341. u32 cal_interval, short_cal_interval, long_cal_interval;
  342. if (ah->caldata && ah->caldata->nfcal_interference)
  343. long_cal_interval = ATH_LONG_CALINTERVAL_INT;
  344. else
  345. long_cal_interval = ATH_LONG_CALINTERVAL;
  346. short_cal_interval = (ah->opmode == NL80211_IFTYPE_AP) ?
  347. ATH_AP_SHORT_CALINTERVAL : ATH_STA_SHORT_CALINTERVAL;
  348. /* Only calibrate if awake */
  349. if (sc->sc_ah->power_mode != ATH9K_PM_AWAKE)
  350. goto set_timer;
  351. ath9k_ps_wakeup(sc);
  352. /* Long calibration runs independently of short calibration. */
  353. if ((timestamp - common->ani.longcal_timer) >= long_cal_interval) {
  354. longcal = true;
  355. ath_print(common, ATH_DBG_ANI, "longcal @%lu\n", jiffies);
  356. common->ani.longcal_timer = timestamp;
  357. }
  358. /* Short calibration applies only while caldone is false */
  359. if (!common->ani.caldone) {
  360. if ((timestamp - common->ani.shortcal_timer) >= short_cal_interval) {
  361. shortcal = true;
  362. ath_print(common, ATH_DBG_ANI,
  363. "shortcal @%lu\n", jiffies);
  364. common->ani.shortcal_timer = timestamp;
  365. common->ani.resetcal_timer = timestamp;
  366. }
  367. } else {
  368. if ((timestamp - common->ani.resetcal_timer) >=
  369. ATH_RESTART_CALINTERVAL) {
  370. common->ani.caldone = ath9k_hw_reset_calvalid(ah);
  371. if (common->ani.caldone)
  372. common->ani.resetcal_timer = timestamp;
  373. }
  374. }
  375. /* Verify whether we must check ANI */
  376. if ((timestamp - common->ani.checkani_timer) >=
  377. ah->config.ani_poll_interval) {
  378. aniflag = true;
  379. common->ani.checkani_timer = timestamp;
  380. }
  381. /* Skip all processing if there's nothing to do. */
  382. if (longcal || shortcal || aniflag) {
  383. /* Call ANI routine if necessary */
  384. if (aniflag)
  385. ath9k_hw_ani_monitor(ah, ah->curchan);
  386. /* Perform calibration if necessary */
  387. if (longcal || shortcal) {
  388. common->ani.caldone =
  389. ath9k_hw_calibrate(ah,
  390. ah->curchan,
  391. common->rx_chainmask,
  392. longcal);
  393. if (longcal)
  394. common->ani.noise_floor = ath9k_hw_getchan_noise(ah,
  395. ah->curchan);
  396. ath_print(common, ATH_DBG_ANI,
  397. " calibrate chan %u/%x nf: %d\n",
  398. ah->curchan->channel,
  399. ah->curchan->channelFlags,
  400. common->ani.noise_floor);
  401. }
  402. }
  403. ath9k_ps_restore(sc);
  404. set_timer:
  405. /*
  406. * Set timer interval based on previous results.
  407. * The interval must be the shortest necessary to satisfy ANI,
  408. * short calibration and long calibration.
  409. */
  410. cal_interval = ATH_LONG_CALINTERVAL;
  411. if (sc->sc_ah->config.enable_ani)
  412. cal_interval = min(cal_interval,
  413. (u32)ah->config.ani_poll_interval);
  414. if (!common->ani.caldone)
  415. cal_interval = min(cal_interval, (u32)short_cal_interval);
  416. mod_timer(&common->ani.timer, jiffies + msecs_to_jiffies(cal_interval));
  417. if ((sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_PAPRD) && ah->caldata) {
  418. if (!ah->caldata->paprd_done)
  419. ieee80211_queue_work(sc->hw, &sc->paprd_work);
  420. else
  421. ath_paprd_activate(sc);
  422. }
  423. }
  424. /*
  425. * Update tx/rx chainmask. For legacy association,
  426. * hard code chainmask to 1x1, for 11n association, use
  427. * the chainmask configuration, for bt coexistence, use
  428. * the chainmask configuration even in legacy mode.
  429. */
  430. void ath_update_chainmask(struct ath_softc *sc, int is_ht)
  431. {
  432. struct ath_hw *ah = sc->sc_ah;
  433. struct ath_common *common = ath9k_hw_common(ah);
  434. if ((sc->sc_flags & SC_OP_OFFCHANNEL) || is_ht ||
  435. (ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE)) {
  436. common->tx_chainmask = ah->caps.tx_chainmask;
  437. common->rx_chainmask = ah->caps.rx_chainmask;
  438. } else {
  439. common->tx_chainmask = 1;
  440. common->rx_chainmask = 1;
  441. }
  442. ath_print(common, ATH_DBG_CONFIG,
  443. "tx chmask: %d, rx chmask: %d\n",
  444. common->tx_chainmask,
  445. common->rx_chainmask);
  446. }
  447. static void ath_node_attach(struct ath_softc *sc, struct ieee80211_sta *sta)
  448. {
  449. struct ath_node *an;
  450. an = (struct ath_node *)sta->drv_priv;
  451. if (sc->sc_flags & SC_OP_TXAGGR) {
  452. ath_tx_node_init(sc, an);
  453. an->maxampdu = 1 << (IEEE80211_HT_MAX_AMPDU_FACTOR +
  454. sta->ht_cap.ampdu_factor);
  455. an->mpdudensity = parse_mpdudensity(sta->ht_cap.ampdu_density);
  456. an->last_rssi = ATH_RSSI_DUMMY_MARKER;
  457. }
  458. }
  459. static void ath_node_detach(struct ath_softc *sc, struct ieee80211_sta *sta)
  460. {
  461. struct ath_node *an = (struct ath_node *)sta->drv_priv;
  462. if (sc->sc_flags & SC_OP_TXAGGR)
  463. ath_tx_node_cleanup(sc, an);
  464. }
  465. void ath_hw_check(struct work_struct *work)
  466. {
  467. struct ath_softc *sc = container_of(work, struct ath_softc, hw_check_work);
  468. int i;
  469. ath9k_ps_wakeup(sc);
  470. for (i = 0; i < 3; i++) {
  471. if (ath9k_hw_check_alive(sc->sc_ah))
  472. goto out;
  473. msleep(1);
  474. }
  475. ath_reset(sc, false);
  476. out:
  477. ath9k_ps_restore(sc);
  478. }
  479. void ath9k_tasklet(unsigned long data)
  480. {
  481. struct ath_softc *sc = (struct ath_softc *)data;
  482. struct ath_hw *ah = sc->sc_ah;
  483. struct ath_common *common = ath9k_hw_common(ah);
  484. u32 status = sc->intrstatus;
  485. u32 rxmask;
  486. ath9k_ps_wakeup(sc);
  487. if (status & ATH9K_INT_FATAL) {
  488. ath_reset(sc, false);
  489. ath9k_ps_restore(sc);
  490. return;
  491. }
  492. if (!ath9k_hw_check_alive(ah))
  493. ieee80211_queue_work(sc->hw, &sc->hw_check_work);
  494. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  495. rxmask = (ATH9K_INT_RXHP | ATH9K_INT_RXLP | ATH9K_INT_RXEOL |
  496. ATH9K_INT_RXORN);
  497. else
  498. rxmask = (ATH9K_INT_RX | ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  499. if (status & rxmask) {
  500. spin_lock_bh(&sc->rx.rxflushlock);
  501. /* Check for high priority Rx first */
  502. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  503. (status & ATH9K_INT_RXHP))
  504. ath_rx_tasklet(sc, 0, true);
  505. ath_rx_tasklet(sc, 0, false);
  506. spin_unlock_bh(&sc->rx.rxflushlock);
  507. }
  508. if (status & ATH9K_INT_TX) {
  509. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  510. ath_tx_edma_tasklet(sc);
  511. else
  512. ath_tx_tasklet(sc);
  513. }
  514. if ((status & ATH9K_INT_TSFOOR) && sc->ps_enabled) {
  515. /*
  516. * TSF sync does not look correct; remain awake to sync with
  517. * the next Beacon.
  518. */
  519. ath_print(common, ATH_DBG_PS,
  520. "TSFOOR - Sync with next Beacon\n");
  521. sc->ps_flags |= PS_WAIT_FOR_BEACON | PS_BEACON_SYNC;
  522. }
  523. if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
  524. if (status & ATH9K_INT_GENTIMER)
  525. ath_gen_timer_isr(sc->sc_ah);
  526. /* re-enable hardware interrupt */
  527. ath9k_hw_set_interrupts(ah, ah->imask);
  528. ath9k_ps_restore(sc);
  529. }
  530. irqreturn_t ath_isr(int irq, void *dev)
  531. {
  532. #define SCHED_INTR ( \
  533. ATH9K_INT_FATAL | \
  534. ATH9K_INT_RXORN | \
  535. ATH9K_INT_RXEOL | \
  536. ATH9K_INT_RX | \
  537. ATH9K_INT_RXLP | \
  538. ATH9K_INT_RXHP | \
  539. ATH9K_INT_TX | \
  540. ATH9K_INT_BMISS | \
  541. ATH9K_INT_CST | \
  542. ATH9K_INT_TSFOOR | \
  543. ATH9K_INT_GENTIMER)
  544. struct ath_softc *sc = dev;
  545. struct ath_hw *ah = sc->sc_ah;
  546. enum ath9k_int status;
  547. bool sched = false;
  548. /*
  549. * The hardware is not ready/present, don't
  550. * touch anything. Note this can happen early
  551. * on if the IRQ is shared.
  552. */
  553. if (sc->sc_flags & SC_OP_INVALID)
  554. return IRQ_NONE;
  555. /* shared irq, not for us */
  556. if (!ath9k_hw_intrpend(ah))
  557. return IRQ_NONE;
  558. /*
  559. * Figure out the reason(s) for the interrupt. Note
  560. * that the hal returns a pseudo-ISR that may include
  561. * bits we haven't explicitly enabled so we mask the
  562. * value to insure we only process bits we requested.
  563. */
  564. ath9k_hw_getisr(ah, &status); /* NB: clears ISR too */
  565. status &= ah->imask; /* discard unasked-for bits */
  566. /*
  567. * If there are no status bits set, then this interrupt was not
  568. * for me (should have been caught above).
  569. */
  570. if (!status)
  571. return IRQ_NONE;
  572. /* Cache the status */
  573. sc->intrstatus = status;
  574. if (status & SCHED_INTR)
  575. sched = true;
  576. /*
  577. * If a FATAL or RXORN interrupt is received, we have to reset the
  578. * chip immediately.
  579. */
  580. if ((status & ATH9K_INT_FATAL) || ((status & ATH9K_INT_RXORN) &&
  581. !(ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)))
  582. goto chip_reset;
  583. if ((ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) &&
  584. (status & ATH9K_INT_BB_WATCHDOG)) {
  585. ar9003_hw_bb_watchdog_dbg_info(ah);
  586. goto chip_reset;
  587. }
  588. if (status & ATH9K_INT_SWBA)
  589. tasklet_schedule(&sc->bcon_tasklet);
  590. if (status & ATH9K_INT_TXURN)
  591. ath9k_hw_updatetxtriglevel(ah, true);
  592. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA) {
  593. if (status & ATH9K_INT_RXEOL) {
  594. ah->imask &= ~(ATH9K_INT_RXEOL | ATH9K_INT_RXORN);
  595. ath9k_hw_set_interrupts(ah, ah->imask);
  596. }
  597. }
  598. if (status & ATH9K_INT_MIB) {
  599. /*
  600. * Disable interrupts until we service the MIB
  601. * interrupt; otherwise it will continue to
  602. * fire.
  603. */
  604. ath9k_hw_set_interrupts(ah, 0);
  605. /*
  606. * Let the hal handle the event. We assume
  607. * it will clear whatever condition caused
  608. * the interrupt.
  609. */
  610. ath9k_hw_procmibevent(ah);
  611. ath9k_hw_set_interrupts(ah, ah->imask);
  612. }
  613. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  614. if (status & ATH9K_INT_TIM_TIMER) {
  615. /* Clear RxAbort bit so that we can
  616. * receive frames */
  617. ath9k_setpower(sc, ATH9K_PM_AWAKE);
  618. ath9k_hw_setrxabort(sc->sc_ah, 0);
  619. sc->ps_flags |= PS_WAIT_FOR_BEACON;
  620. }
  621. chip_reset:
  622. ath_debug_stat_interrupt(sc, status);
  623. if (sched) {
  624. /* turn off every interrupt except SWBA */
  625. ath9k_hw_set_interrupts(ah, (ah->imask & ATH9K_INT_SWBA));
  626. tasklet_schedule(&sc->intr_tq);
  627. }
  628. return IRQ_HANDLED;
  629. #undef SCHED_INTR
  630. }
  631. static u32 ath_get_extchanmode(struct ath_softc *sc,
  632. struct ieee80211_channel *chan,
  633. enum nl80211_channel_type channel_type)
  634. {
  635. u32 chanmode = 0;
  636. switch (chan->band) {
  637. case IEEE80211_BAND_2GHZ:
  638. switch(channel_type) {
  639. case NL80211_CHAN_NO_HT:
  640. case NL80211_CHAN_HT20:
  641. chanmode = CHANNEL_G_HT20;
  642. break;
  643. case NL80211_CHAN_HT40PLUS:
  644. chanmode = CHANNEL_G_HT40PLUS;
  645. break;
  646. case NL80211_CHAN_HT40MINUS:
  647. chanmode = CHANNEL_G_HT40MINUS;
  648. break;
  649. }
  650. break;
  651. case IEEE80211_BAND_5GHZ:
  652. switch(channel_type) {
  653. case NL80211_CHAN_NO_HT:
  654. case NL80211_CHAN_HT20:
  655. chanmode = CHANNEL_A_HT20;
  656. break;
  657. case NL80211_CHAN_HT40PLUS:
  658. chanmode = CHANNEL_A_HT40PLUS;
  659. break;
  660. case NL80211_CHAN_HT40MINUS:
  661. chanmode = CHANNEL_A_HT40MINUS;
  662. break;
  663. }
  664. break;
  665. default:
  666. break;
  667. }
  668. return chanmode;
  669. }
  670. static void ath9k_bss_assoc_info(struct ath_softc *sc,
  671. struct ieee80211_vif *vif,
  672. struct ieee80211_bss_conf *bss_conf)
  673. {
  674. struct ath_hw *ah = sc->sc_ah;
  675. struct ath_common *common = ath9k_hw_common(ah);
  676. if (bss_conf->assoc) {
  677. ath_print(common, ATH_DBG_CONFIG,
  678. "Bss Info ASSOC %d, bssid: %pM\n",
  679. bss_conf->aid, common->curbssid);
  680. /* New association, store aid */
  681. common->curaid = bss_conf->aid;
  682. ath9k_hw_write_associd(ah);
  683. /*
  684. * Request a re-configuration of Beacon related timers
  685. * on the receipt of the first Beacon frame (i.e.,
  686. * after time sync with the AP).
  687. */
  688. sc->ps_flags |= PS_BEACON_SYNC;
  689. /* Configure the beacon */
  690. ath_beacon_config(sc, vif);
  691. /* Reset rssi stats */
  692. sc->sc_ah->stats.avgbrssi = ATH_RSSI_DUMMY_MARKER;
  693. sc->sc_flags |= SC_OP_ANI_RUN;
  694. ath_start_ani(common);
  695. } else {
  696. ath_print(common, ATH_DBG_CONFIG, "Bss Info DISASSOC\n");
  697. common->curaid = 0;
  698. /* Stop ANI */
  699. sc->sc_flags &= ~SC_OP_ANI_RUN;
  700. del_timer_sync(&common->ani.timer);
  701. }
  702. }
  703. void ath_radio_enable(struct ath_softc *sc, struct ieee80211_hw *hw)
  704. {
  705. struct ath_hw *ah = sc->sc_ah;
  706. struct ath_common *common = ath9k_hw_common(ah);
  707. struct ieee80211_channel *channel = hw->conf.channel;
  708. int r;
  709. ath9k_ps_wakeup(sc);
  710. ath9k_hw_configpcipowersave(ah, 0, 0);
  711. if (!ah->curchan)
  712. ah->curchan = ath_get_curchannel(sc, sc->hw);
  713. spin_lock_bh(&sc->sc_resetlock);
  714. r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
  715. if (r) {
  716. ath_print(common, ATH_DBG_FATAL,
  717. "Unable to reset channel (%u MHz), "
  718. "reset status %d\n",
  719. channel->center_freq, r);
  720. }
  721. spin_unlock_bh(&sc->sc_resetlock);
  722. ath_update_txpow(sc);
  723. if (ath_startrecv(sc) != 0) {
  724. ath_print(common, ATH_DBG_FATAL,
  725. "Unable to restart recv logic\n");
  726. return;
  727. }
  728. if (sc->sc_flags & SC_OP_BEACONS)
  729. ath_beacon_config(sc, NULL); /* restart beacons */
  730. /* Re-Enable interrupts */
  731. ath9k_hw_set_interrupts(ah, ah->imask);
  732. /* Enable LED */
  733. ath9k_hw_cfg_output(ah, ah->led_pin,
  734. AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
  735. ath9k_hw_set_gpio(ah, ah->led_pin, 0);
  736. ieee80211_wake_queues(hw);
  737. ath9k_ps_restore(sc);
  738. }
  739. void ath_radio_disable(struct ath_softc *sc, struct ieee80211_hw *hw)
  740. {
  741. struct ath_hw *ah = sc->sc_ah;
  742. struct ieee80211_channel *channel = hw->conf.channel;
  743. int r;
  744. ath9k_ps_wakeup(sc);
  745. ieee80211_stop_queues(hw);
  746. /*
  747. * Keep the LED on when the radio is disabled
  748. * during idle unassociated state.
  749. */
  750. if (!sc->ps_idle) {
  751. ath9k_hw_set_gpio(ah, ah->led_pin, 1);
  752. ath9k_hw_cfg_gpio_input(ah, ah->led_pin);
  753. }
  754. /* Disable interrupts */
  755. ath9k_hw_set_interrupts(ah, 0);
  756. ath_drain_all_txq(sc, false); /* clear pending tx frames */
  757. ath_stoprecv(sc); /* turn off frame recv */
  758. ath_flushrecv(sc); /* flush recv queue */
  759. if (!ah->curchan)
  760. ah->curchan = ath_get_curchannel(sc, hw);
  761. spin_lock_bh(&sc->sc_resetlock);
  762. r = ath9k_hw_reset(ah, ah->curchan, ah->caldata, false);
  763. if (r) {
  764. ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
  765. "Unable to reset channel (%u MHz), "
  766. "reset status %d\n",
  767. channel->center_freq, r);
  768. }
  769. spin_unlock_bh(&sc->sc_resetlock);
  770. ath9k_hw_phy_disable(ah);
  771. ath9k_hw_configpcipowersave(ah, 1, 1);
  772. ath9k_ps_restore(sc);
  773. ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
  774. }
  775. int ath_reset(struct ath_softc *sc, bool retry_tx)
  776. {
  777. struct ath_hw *ah = sc->sc_ah;
  778. struct ath_common *common = ath9k_hw_common(ah);
  779. struct ieee80211_hw *hw = sc->hw;
  780. int r;
  781. /* Stop ANI */
  782. del_timer_sync(&common->ani.timer);
  783. ieee80211_stop_queues(hw);
  784. ath9k_hw_set_interrupts(ah, 0);
  785. ath_drain_all_txq(sc, retry_tx);
  786. ath_stoprecv(sc);
  787. ath_flushrecv(sc);
  788. spin_lock_bh(&sc->sc_resetlock);
  789. r = ath9k_hw_reset(ah, sc->sc_ah->curchan, ah->caldata, false);
  790. if (r)
  791. ath_print(common, ATH_DBG_FATAL,
  792. "Unable to reset hardware; reset status %d\n", r);
  793. spin_unlock_bh(&sc->sc_resetlock);
  794. if (ath_startrecv(sc) != 0)
  795. ath_print(common, ATH_DBG_FATAL,
  796. "Unable to start recv logic\n");
  797. /*
  798. * We may be doing a reset in response to a request
  799. * that changes the channel so update any state that
  800. * might change as a result.
  801. */
  802. ath_cache_conf_rate(sc, &hw->conf);
  803. ath_update_txpow(sc);
  804. if ((sc->sc_flags & SC_OP_BEACONS) || !(sc->sc_flags & (SC_OP_OFFCHANNEL)))
  805. ath_beacon_config(sc, NULL); /* restart beacons */
  806. ath9k_hw_set_interrupts(ah, ah->imask);
  807. if (retry_tx) {
  808. int i;
  809. for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++) {
  810. if (ATH_TXQ_SETUP(sc, i)) {
  811. spin_lock_bh(&sc->tx.txq[i].axq_lock);
  812. ath_txq_schedule(sc, &sc->tx.txq[i]);
  813. spin_unlock_bh(&sc->tx.txq[i].axq_lock);
  814. }
  815. }
  816. }
  817. ieee80211_wake_queues(hw);
  818. /* Start ANI */
  819. ath_start_ani(common);
  820. return r;
  821. }
  822. static int ath_get_hal_qnum(u16 queue, struct ath_softc *sc)
  823. {
  824. int qnum;
  825. switch (queue) {
  826. case 0:
  827. qnum = sc->tx.hwq_map[WME_AC_VO];
  828. break;
  829. case 1:
  830. qnum = sc->tx.hwq_map[WME_AC_VI];
  831. break;
  832. case 2:
  833. qnum = sc->tx.hwq_map[WME_AC_BE];
  834. break;
  835. case 3:
  836. qnum = sc->tx.hwq_map[WME_AC_BK];
  837. break;
  838. default:
  839. qnum = sc->tx.hwq_map[WME_AC_BE];
  840. break;
  841. }
  842. return qnum;
  843. }
  844. int ath_get_mac80211_qnum(u32 queue, struct ath_softc *sc)
  845. {
  846. int qnum;
  847. switch (queue) {
  848. case WME_AC_VO:
  849. qnum = 0;
  850. break;
  851. case WME_AC_VI:
  852. qnum = 1;
  853. break;
  854. case WME_AC_BE:
  855. qnum = 2;
  856. break;
  857. case WME_AC_BK:
  858. qnum = 3;
  859. break;
  860. default:
  861. qnum = -1;
  862. break;
  863. }
  864. return qnum;
  865. }
  866. /* XXX: Remove me once we don't depend on ath9k_channel for all
  867. * this redundant data */
  868. void ath9k_update_ichannel(struct ath_softc *sc, struct ieee80211_hw *hw,
  869. struct ath9k_channel *ichan)
  870. {
  871. struct ieee80211_channel *chan = hw->conf.channel;
  872. struct ieee80211_conf *conf = &hw->conf;
  873. ichan->channel = chan->center_freq;
  874. ichan->chan = chan;
  875. if (chan->band == IEEE80211_BAND_2GHZ) {
  876. ichan->chanmode = CHANNEL_G;
  877. ichan->channelFlags = CHANNEL_2GHZ | CHANNEL_OFDM | CHANNEL_G;
  878. } else {
  879. ichan->chanmode = CHANNEL_A;
  880. ichan->channelFlags = CHANNEL_5GHZ | CHANNEL_OFDM;
  881. }
  882. if (conf_is_ht(conf))
  883. ichan->chanmode = ath_get_extchanmode(sc, chan,
  884. conf->channel_type);
  885. }
  886. /**********************/
  887. /* mac80211 callbacks */
  888. /**********************/
  889. static int ath9k_start(struct ieee80211_hw *hw)
  890. {
  891. struct ath_wiphy *aphy = hw->priv;
  892. struct ath_softc *sc = aphy->sc;
  893. struct ath_hw *ah = sc->sc_ah;
  894. struct ath_common *common = ath9k_hw_common(ah);
  895. struct ieee80211_channel *curchan = hw->conf.channel;
  896. struct ath9k_channel *init_channel;
  897. int r;
  898. ath_print(common, ATH_DBG_CONFIG,
  899. "Starting driver with initial channel: %d MHz\n",
  900. curchan->center_freq);
  901. mutex_lock(&sc->mutex);
  902. if (ath9k_wiphy_started(sc)) {
  903. if (sc->chan_idx == curchan->hw_value) {
  904. /*
  905. * Already on the operational channel, the new wiphy
  906. * can be marked active.
  907. */
  908. aphy->state = ATH_WIPHY_ACTIVE;
  909. ieee80211_wake_queues(hw);
  910. } else {
  911. /*
  912. * Another wiphy is on another channel, start the new
  913. * wiphy in paused state.
  914. */
  915. aphy->state = ATH_WIPHY_PAUSED;
  916. ieee80211_stop_queues(hw);
  917. }
  918. mutex_unlock(&sc->mutex);
  919. return 0;
  920. }
  921. aphy->state = ATH_WIPHY_ACTIVE;
  922. /* setup initial channel */
  923. sc->chan_idx = curchan->hw_value;
  924. init_channel = ath_get_curchannel(sc, hw);
  925. /* Reset SERDES registers */
  926. ath9k_hw_configpcipowersave(ah, 0, 0);
  927. /*
  928. * The basic interface to setting the hardware in a good
  929. * state is ``reset''. On return the hardware is known to
  930. * be powered up and with interrupts disabled. This must
  931. * be followed by initialization of the appropriate bits
  932. * and then setup of the interrupt mask.
  933. */
  934. spin_lock_bh(&sc->sc_resetlock);
  935. r = ath9k_hw_reset(ah, init_channel, ah->caldata, false);
  936. if (r) {
  937. ath_print(common, ATH_DBG_FATAL,
  938. "Unable to reset hardware; reset status %d "
  939. "(freq %u MHz)\n", r,
  940. curchan->center_freq);
  941. spin_unlock_bh(&sc->sc_resetlock);
  942. goto mutex_unlock;
  943. }
  944. spin_unlock_bh(&sc->sc_resetlock);
  945. /*
  946. * This is needed only to setup initial state
  947. * but it's best done after a reset.
  948. */
  949. ath_update_txpow(sc);
  950. /*
  951. * Setup the hardware after reset:
  952. * The receive engine is set going.
  953. * Frame transmit is handled entirely
  954. * in the frame output path; there's nothing to do
  955. * here except setup the interrupt mask.
  956. */
  957. if (ath_startrecv(sc) != 0) {
  958. ath_print(common, ATH_DBG_FATAL,
  959. "Unable to start recv logic\n");
  960. r = -EIO;
  961. goto mutex_unlock;
  962. }
  963. /* Setup our intr mask. */
  964. ah->imask = ATH9K_INT_TX | ATH9K_INT_RXEOL |
  965. ATH9K_INT_RXORN | ATH9K_INT_FATAL |
  966. ATH9K_INT_GLOBAL;
  967. if (ah->caps.hw_caps & ATH9K_HW_CAP_EDMA)
  968. ah->imask |= ATH9K_INT_RXHP |
  969. ATH9K_INT_RXLP |
  970. ATH9K_INT_BB_WATCHDOG;
  971. else
  972. ah->imask |= ATH9K_INT_RX;
  973. ah->imask |= ATH9K_INT_GTT;
  974. if (ah->caps.hw_caps & ATH9K_HW_CAP_HT)
  975. ah->imask |= ATH9K_INT_CST;
  976. ath_cache_conf_rate(sc, &hw->conf);
  977. sc->sc_flags &= ~SC_OP_INVALID;
  978. /* Disable BMISS interrupt when we're not associated */
  979. ah->imask &= ~(ATH9K_INT_SWBA | ATH9K_INT_BMISS);
  980. ath9k_hw_set_interrupts(ah, ah->imask);
  981. ieee80211_wake_queues(hw);
  982. ieee80211_queue_delayed_work(sc->hw, &sc->tx_complete_work, 0);
  983. if ((ah->btcoex_hw.scheme != ATH_BTCOEX_CFG_NONE) &&
  984. !ah->btcoex_hw.enabled) {
  985. ath9k_hw_btcoex_set_weight(ah, AR_BT_COEX_WGHT,
  986. AR_STOMP_LOW_WLAN_WGHT);
  987. ath9k_hw_btcoex_enable(ah);
  988. if (common->bus_ops->bt_coex_prep)
  989. common->bus_ops->bt_coex_prep(common);
  990. if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
  991. ath9k_btcoex_timer_resume(sc);
  992. }
  993. mutex_unlock:
  994. mutex_unlock(&sc->mutex);
  995. return r;
  996. }
  997. static int ath9k_tx(struct ieee80211_hw *hw,
  998. struct sk_buff *skb)
  999. {
  1000. struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
  1001. struct ath_wiphy *aphy = hw->priv;
  1002. struct ath_softc *sc = aphy->sc;
  1003. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1004. struct ath_tx_control txctl;
  1005. int padpos, padsize;
  1006. struct ieee80211_hdr *hdr = (struct ieee80211_hdr *) skb->data;
  1007. int qnum;
  1008. if (aphy->state != ATH_WIPHY_ACTIVE && aphy->state != ATH_WIPHY_SCAN) {
  1009. ath_print(common, ATH_DBG_XMIT,
  1010. "ath9k: %s: TX in unexpected wiphy state "
  1011. "%d\n", wiphy_name(hw->wiphy), aphy->state);
  1012. goto exit;
  1013. }
  1014. if (sc->ps_enabled) {
  1015. /*
  1016. * mac80211 does not set PM field for normal data frames, so we
  1017. * need to update that based on the current PS mode.
  1018. */
  1019. if (ieee80211_is_data(hdr->frame_control) &&
  1020. !ieee80211_is_nullfunc(hdr->frame_control) &&
  1021. !ieee80211_has_pm(hdr->frame_control)) {
  1022. ath_print(common, ATH_DBG_PS, "Add PM=1 for a TX frame "
  1023. "while in PS mode\n");
  1024. hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
  1025. }
  1026. }
  1027. if (unlikely(sc->sc_ah->power_mode != ATH9K_PM_AWAKE)) {
  1028. /*
  1029. * We are using PS-Poll and mac80211 can request TX while in
  1030. * power save mode. Need to wake up hardware for the TX to be
  1031. * completed and if needed, also for RX of buffered frames.
  1032. */
  1033. ath9k_ps_wakeup(sc);
  1034. if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP))
  1035. ath9k_hw_setrxabort(sc->sc_ah, 0);
  1036. if (ieee80211_is_pspoll(hdr->frame_control)) {
  1037. ath_print(common, ATH_DBG_PS,
  1038. "Sending PS-Poll to pick a buffered frame\n");
  1039. sc->ps_flags |= PS_WAIT_FOR_PSPOLL_DATA;
  1040. } else {
  1041. ath_print(common, ATH_DBG_PS,
  1042. "Wake up to complete TX\n");
  1043. sc->ps_flags |= PS_WAIT_FOR_TX_ACK;
  1044. }
  1045. /*
  1046. * The actual restore operation will happen only after
  1047. * the sc_flags bit is cleared. We are just dropping
  1048. * the ps_usecount here.
  1049. */
  1050. ath9k_ps_restore(sc);
  1051. }
  1052. memset(&txctl, 0, sizeof(struct ath_tx_control));
  1053. /*
  1054. * As a temporary workaround, assign seq# here; this will likely need
  1055. * to be cleaned up to work better with Beacon transmission and virtual
  1056. * BSSes.
  1057. */
  1058. if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
  1059. if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
  1060. sc->tx.seq_no += 0x10;
  1061. hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
  1062. hdr->seq_ctrl |= cpu_to_le16(sc->tx.seq_no);
  1063. }
  1064. /* Add the padding after the header if this is not already done */
  1065. padpos = ath9k_cmn_padpos(hdr->frame_control);
  1066. padsize = padpos & 3;
  1067. if (padsize && skb->len>padpos) {
  1068. if (skb_headroom(skb) < padsize)
  1069. return -1;
  1070. skb_push(skb, padsize);
  1071. memmove(skb->data, skb->data + padsize, padpos);
  1072. }
  1073. qnum = ath_get_hal_qnum(skb_get_queue_mapping(skb), sc);
  1074. txctl.txq = &sc->tx.txq[qnum];
  1075. ath_print(common, ATH_DBG_XMIT, "transmitting packet, skb: %p\n", skb);
  1076. if (ath_tx_start(hw, skb, &txctl) != 0) {
  1077. ath_print(common, ATH_DBG_XMIT, "TX failed\n");
  1078. goto exit;
  1079. }
  1080. return 0;
  1081. exit:
  1082. dev_kfree_skb_any(skb);
  1083. return 0;
  1084. }
  1085. static void ath9k_stop(struct ieee80211_hw *hw)
  1086. {
  1087. struct ath_wiphy *aphy = hw->priv;
  1088. struct ath_softc *sc = aphy->sc;
  1089. struct ath_hw *ah = sc->sc_ah;
  1090. struct ath_common *common = ath9k_hw_common(ah);
  1091. int i;
  1092. mutex_lock(&sc->mutex);
  1093. aphy->state = ATH_WIPHY_INACTIVE;
  1094. if (led_blink)
  1095. cancel_delayed_work_sync(&sc->ath_led_blink_work);
  1096. cancel_delayed_work_sync(&sc->tx_complete_work);
  1097. cancel_work_sync(&sc->paprd_work);
  1098. cancel_work_sync(&sc->hw_check_work);
  1099. for (i = 0; i < sc->num_sec_wiphy; i++) {
  1100. if (sc->sec_wiphy[i])
  1101. break;
  1102. }
  1103. if (i == sc->num_sec_wiphy) {
  1104. cancel_delayed_work_sync(&sc->wiphy_work);
  1105. cancel_work_sync(&sc->chan_work);
  1106. }
  1107. if (sc->sc_flags & SC_OP_INVALID) {
  1108. ath_print(common, ATH_DBG_ANY, "Device not present\n");
  1109. mutex_unlock(&sc->mutex);
  1110. return;
  1111. }
  1112. if (ath9k_wiphy_started(sc)) {
  1113. mutex_unlock(&sc->mutex);
  1114. return; /* another wiphy still in use */
  1115. }
  1116. /* Ensure HW is awake when we try to shut it down. */
  1117. ath9k_ps_wakeup(sc);
  1118. if (ah->btcoex_hw.enabled) {
  1119. ath9k_hw_btcoex_disable(ah);
  1120. if (ah->btcoex_hw.scheme == ATH_BTCOEX_CFG_3WIRE)
  1121. ath9k_btcoex_timer_pause(sc);
  1122. }
  1123. /* make sure h/w will not generate any interrupt
  1124. * before setting the invalid flag. */
  1125. ath9k_hw_set_interrupts(ah, 0);
  1126. if (!(sc->sc_flags & SC_OP_INVALID)) {
  1127. ath_drain_all_txq(sc, false);
  1128. ath_stoprecv(sc);
  1129. ath9k_hw_phy_disable(ah);
  1130. } else
  1131. sc->rx.rxlink = NULL;
  1132. /* disable HAL and put h/w to sleep */
  1133. ath9k_hw_disable(ah);
  1134. ath9k_hw_configpcipowersave(ah, 1, 1);
  1135. ath9k_ps_restore(sc);
  1136. /* Finally, put the chip in FULL SLEEP mode */
  1137. ath9k_setpower(sc, ATH9K_PM_FULL_SLEEP);
  1138. sc->sc_flags |= SC_OP_INVALID;
  1139. mutex_unlock(&sc->mutex);
  1140. ath_print(common, ATH_DBG_CONFIG, "Driver halt\n");
  1141. }
  1142. static int ath9k_add_interface(struct ieee80211_hw *hw,
  1143. struct ieee80211_vif *vif)
  1144. {
  1145. struct ath_wiphy *aphy = hw->priv;
  1146. struct ath_softc *sc = aphy->sc;
  1147. struct ath_hw *ah = sc->sc_ah;
  1148. struct ath_common *common = ath9k_hw_common(ah);
  1149. struct ath_vif *avp = (void *)vif->drv_priv;
  1150. enum nl80211_iftype ic_opmode = NL80211_IFTYPE_UNSPECIFIED;
  1151. int ret = 0;
  1152. mutex_lock(&sc->mutex);
  1153. switch (vif->type) {
  1154. case NL80211_IFTYPE_STATION:
  1155. ic_opmode = NL80211_IFTYPE_STATION;
  1156. break;
  1157. case NL80211_IFTYPE_ADHOC:
  1158. case NL80211_IFTYPE_AP:
  1159. case NL80211_IFTYPE_MESH_POINT:
  1160. if (sc->nbcnvifs >= ATH_BCBUF) {
  1161. ret = -ENOBUFS;
  1162. goto out;
  1163. }
  1164. ic_opmode = vif->type;
  1165. break;
  1166. default:
  1167. ath_print(common, ATH_DBG_FATAL,
  1168. "Interface type %d not yet supported\n", vif->type);
  1169. ret = -EOPNOTSUPP;
  1170. goto out;
  1171. }
  1172. ath_print(common, ATH_DBG_CONFIG,
  1173. "Attach a VIF of type: %d\n", ic_opmode);
  1174. /* Set the VIF opmode */
  1175. avp->av_opmode = ic_opmode;
  1176. avp->av_bslot = -1;
  1177. sc->nvifs++;
  1178. ath9k_set_bssid_mask(hw, vif);
  1179. if (sc->nvifs > 1)
  1180. goto out; /* skip global settings for secondary vif */
  1181. if (ic_opmode == NL80211_IFTYPE_AP) {
  1182. ath9k_hw_set_tsfadjust(ah, 1);
  1183. sc->sc_flags |= SC_OP_TSF_RESET;
  1184. }
  1185. /* Set the device opmode */
  1186. ah->opmode = ic_opmode;
  1187. /*
  1188. * Enable MIB interrupts when there are hardware phy counters.
  1189. * Note we only do this (at the moment) for station mode.
  1190. */
  1191. if ((vif->type == NL80211_IFTYPE_STATION) ||
  1192. (vif->type == NL80211_IFTYPE_ADHOC) ||
  1193. (vif->type == NL80211_IFTYPE_MESH_POINT)) {
  1194. if (ah->config.enable_ani)
  1195. ah->imask |= ATH9K_INT_MIB;
  1196. ah->imask |= ATH9K_INT_TSFOOR;
  1197. }
  1198. ath9k_hw_set_interrupts(ah, ah->imask);
  1199. if (vif->type == NL80211_IFTYPE_AP ||
  1200. vif->type == NL80211_IFTYPE_ADHOC ||
  1201. vif->type == NL80211_IFTYPE_MONITOR) {
  1202. sc->sc_flags |= SC_OP_ANI_RUN;
  1203. ath_start_ani(common);
  1204. }
  1205. out:
  1206. mutex_unlock(&sc->mutex);
  1207. return ret;
  1208. }
  1209. static void ath9k_remove_interface(struct ieee80211_hw *hw,
  1210. struct ieee80211_vif *vif)
  1211. {
  1212. struct ath_wiphy *aphy = hw->priv;
  1213. struct ath_softc *sc = aphy->sc;
  1214. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1215. struct ath_vif *avp = (void *)vif->drv_priv;
  1216. int i;
  1217. ath_print(common, ATH_DBG_CONFIG, "Detach Interface\n");
  1218. mutex_lock(&sc->mutex);
  1219. /* Stop ANI */
  1220. sc->sc_flags &= ~SC_OP_ANI_RUN;
  1221. del_timer_sync(&common->ani.timer);
  1222. /* Reclaim beacon resources */
  1223. if ((sc->sc_ah->opmode == NL80211_IFTYPE_AP) ||
  1224. (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC) ||
  1225. (sc->sc_ah->opmode == NL80211_IFTYPE_MESH_POINT)) {
  1226. ath9k_ps_wakeup(sc);
  1227. ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
  1228. ath9k_ps_restore(sc);
  1229. }
  1230. ath_beacon_return(sc, avp);
  1231. sc->sc_flags &= ~SC_OP_BEACONS;
  1232. for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++) {
  1233. if (sc->beacon.bslot[i] == vif) {
  1234. printk(KERN_DEBUG "%s: vif had allocated beacon "
  1235. "slot\n", __func__);
  1236. sc->beacon.bslot[i] = NULL;
  1237. sc->beacon.bslot_aphy[i] = NULL;
  1238. }
  1239. }
  1240. sc->nvifs--;
  1241. mutex_unlock(&sc->mutex);
  1242. }
  1243. void ath9k_enable_ps(struct ath_softc *sc)
  1244. {
  1245. struct ath_hw *ah = sc->sc_ah;
  1246. sc->ps_enabled = true;
  1247. if (!(ah->caps.hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
  1248. if ((ah->imask & ATH9K_INT_TIM_TIMER) == 0) {
  1249. ah->imask |= ATH9K_INT_TIM_TIMER;
  1250. ath9k_hw_set_interrupts(ah, ah->imask);
  1251. }
  1252. ath9k_hw_setrxabort(ah, 1);
  1253. }
  1254. }
  1255. static int ath9k_config(struct ieee80211_hw *hw, u32 changed)
  1256. {
  1257. struct ath_wiphy *aphy = hw->priv;
  1258. struct ath_softc *sc = aphy->sc;
  1259. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1260. struct ieee80211_conf *conf = &hw->conf;
  1261. struct ath_hw *ah = sc->sc_ah;
  1262. bool disable_radio;
  1263. mutex_lock(&sc->mutex);
  1264. /*
  1265. * Leave this as the first check because we need to turn on the
  1266. * radio if it was disabled before prior to processing the rest
  1267. * of the changes. Likewise we must only disable the radio towards
  1268. * the end.
  1269. */
  1270. if (changed & IEEE80211_CONF_CHANGE_IDLE) {
  1271. bool enable_radio;
  1272. bool all_wiphys_idle;
  1273. bool idle = !!(conf->flags & IEEE80211_CONF_IDLE);
  1274. spin_lock_bh(&sc->wiphy_lock);
  1275. all_wiphys_idle = ath9k_all_wiphys_idle(sc);
  1276. ath9k_set_wiphy_idle(aphy, idle);
  1277. enable_radio = (!idle && all_wiphys_idle);
  1278. /*
  1279. * After we unlock here its possible another wiphy
  1280. * can be re-renabled so to account for that we will
  1281. * only disable the radio toward the end of this routine
  1282. * if by then all wiphys are still idle.
  1283. */
  1284. spin_unlock_bh(&sc->wiphy_lock);
  1285. if (enable_radio) {
  1286. sc->ps_idle = false;
  1287. ath_radio_enable(sc, hw);
  1288. ath_print(common, ATH_DBG_CONFIG,
  1289. "not-idle: enabling radio\n");
  1290. }
  1291. }
  1292. /*
  1293. * We just prepare to enable PS. We have to wait until our AP has
  1294. * ACK'd our null data frame to disable RX otherwise we'll ignore
  1295. * those ACKs and end up retransmitting the same null data frames.
  1296. * IEEE80211_CONF_CHANGE_PS is only passed by mac80211 for STA mode.
  1297. */
  1298. if (changed & IEEE80211_CONF_CHANGE_PS) {
  1299. unsigned long flags;
  1300. spin_lock_irqsave(&sc->sc_pm_lock, flags);
  1301. if (conf->flags & IEEE80211_CONF_PS) {
  1302. sc->ps_flags |= PS_ENABLED;
  1303. /*
  1304. * At this point we know hardware has received an ACK
  1305. * of a previously sent null data frame.
  1306. */
  1307. if ((sc->ps_flags & PS_NULLFUNC_COMPLETED)) {
  1308. sc->ps_flags &= ~PS_NULLFUNC_COMPLETED;
  1309. ath9k_enable_ps(sc);
  1310. }
  1311. } else {
  1312. sc->ps_enabled = false;
  1313. sc->ps_flags &= ~(PS_ENABLED |
  1314. PS_NULLFUNC_COMPLETED);
  1315. ath9k_hw_setpower(sc->sc_ah, ATH9K_PM_AWAKE);
  1316. if (!(ah->caps.hw_caps &
  1317. ATH9K_HW_CAP_AUTOSLEEP)) {
  1318. ath9k_hw_setrxabort(sc->sc_ah, 0);
  1319. sc->ps_flags &= ~(PS_WAIT_FOR_BEACON |
  1320. PS_WAIT_FOR_CAB |
  1321. PS_WAIT_FOR_PSPOLL_DATA |
  1322. PS_WAIT_FOR_TX_ACK);
  1323. if (ah->imask & ATH9K_INT_TIM_TIMER) {
  1324. ah->imask &= ~ATH9K_INT_TIM_TIMER;
  1325. ath9k_hw_set_interrupts(sc->sc_ah,
  1326. ah->imask);
  1327. }
  1328. }
  1329. }
  1330. spin_unlock_irqrestore(&sc->sc_pm_lock, flags);
  1331. }
  1332. if (changed & IEEE80211_CONF_CHANGE_MONITOR) {
  1333. if (conf->flags & IEEE80211_CONF_MONITOR) {
  1334. ath_print(common, ATH_DBG_CONFIG,
  1335. "HW opmode set to Monitor mode\n");
  1336. sc->sc_ah->opmode = NL80211_IFTYPE_MONITOR;
  1337. }
  1338. }
  1339. if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
  1340. struct ieee80211_channel *curchan = hw->conf.channel;
  1341. int pos = curchan->hw_value;
  1342. aphy->chan_idx = pos;
  1343. aphy->chan_is_ht = conf_is_ht(conf);
  1344. if (hw->conf.flags & IEEE80211_CONF_OFFCHANNEL)
  1345. sc->sc_flags |= SC_OP_OFFCHANNEL;
  1346. else
  1347. sc->sc_flags &= ~SC_OP_OFFCHANNEL;
  1348. if (aphy->state == ATH_WIPHY_SCAN ||
  1349. aphy->state == ATH_WIPHY_ACTIVE)
  1350. ath9k_wiphy_pause_all_forced(sc, aphy);
  1351. else {
  1352. /*
  1353. * Do not change operational channel based on a paused
  1354. * wiphy changes.
  1355. */
  1356. goto skip_chan_change;
  1357. }
  1358. ath_print(common, ATH_DBG_CONFIG, "Set channel: %d MHz\n",
  1359. curchan->center_freq);
  1360. /* XXX: remove me eventualy */
  1361. ath9k_update_ichannel(sc, hw, &sc->sc_ah->channels[pos]);
  1362. ath_update_chainmask(sc, conf_is_ht(conf));
  1363. if (ath_set_channel(sc, hw, &sc->sc_ah->channels[pos]) < 0) {
  1364. ath_print(common, ATH_DBG_FATAL,
  1365. "Unable to set channel\n");
  1366. mutex_unlock(&sc->mutex);
  1367. return -EINVAL;
  1368. }
  1369. }
  1370. skip_chan_change:
  1371. if (changed & IEEE80211_CONF_CHANGE_POWER) {
  1372. sc->config.txpowlimit = 2 * conf->power_level;
  1373. ath_update_txpow(sc);
  1374. }
  1375. spin_lock_bh(&sc->wiphy_lock);
  1376. disable_radio = ath9k_all_wiphys_idle(sc);
  1377. spin_unlock_bh(&sc->wiphy_lock);
  1378. if (disable_radio) {
  1379. ath_print(common, ATH_DBG_CONFIG, "idle: disabling radio\n");
  1380. sc->ps_idle = true;
  1381. ath_radio_disable(sc, hw);
  1382. }
  1383. mutex_unlock(&sc->mutex);
  1384. return 0;
  1385. }
  1386. #define SUPPORTED_FILTERS \
  1387. (FIF_PROMISC_IN_BSS | \
  1388. FIF_ALLMULTI | \
  1389. FIF_CONTROL | \
  1390. FIF_PSPOLL | \
  1391. FIF_OTHER_BSS | \
  1392. FIF_BCN_PRBRESP_PROMISC | \
  1393. FIF_FCSFAIL)
  1394. /* FIXME: sc->sc_full_reset ? */
  1395. static void ath9k_configure_filter(struct ieee80211_hw *hw,
  1396. unsigned int changed_flags,
  1397. unsigned int *total_flags,
  1398. u64 multicast)
  1399. {
  1400. struct ath_wiphy *aphy = hw->priv;
  1401. struct ath_softc *sc = aphy->sc;
  1402. u32 rfilt;
  1403. changed_flags &= SUPPORTED_FILTERS;
  1404. *total_flags &= SUPPORTED_FILTERS;
  1405. sc->rx.rxfilter = *total_flags;
  1406. ath9k_ps_wakeup(sc);
  1407. rfilt = ath_calcrxfilter(sc);
  1408. ath9k_hw_setrxfilter(sc->sc_ah, rfilt);
  1409. ath9k_ps_restore(sc);
  1410. ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_CONFIG,
  1411. "Set HW RX filter: 0x%x\n", rfilt);
  1412. }
  1413. static int ath9k_sta_add(struct ieee80211_hw *hw,
  1414. struct ieee80211_vif *vif,
  1415. struct ieee80211_sta *sta)
  1416. {
  1417. struct ath_wiphy *aphy = hw->priv;
  1418. struct ath_softc *sc = aphy->sc;
  1419. ath_node_attach(sc, sta);
  1420. return 0;
  1421. }
  1422. static int ath9k_sta_remove(struct ieee80211_hw *hw,
  1423. struct ieee80211_vif *vif,
  1424. struct ieee80211_sta *sta)
  1425. {
  1426. struct ath_wiphy *aphy = hw->priv;
  1427. struct ath_softc *sc = aphy->sc;
  1428. ath_node_detach(sc, sta);
  1429. return 0;
  1430. }
  1431. static int ath9k_conf_tx(struct ieee80211_hw *hw, u16 queue,
  1432. const struct ieee80211_tx_queue_params *params)
  1433. {
  1434. struct ath_wiphy *aphy = hw->priv;
  1435. struct ath_softc *sc = aphy->sc;
  1436. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1437. struct ath9k_tx_queue_info qi;
  1438. int ret = 0, qnum;
  1439. if (queue >= WME_NUM_AC)
  1440. return 0;
  1441. mutex_lock(&sc->mutex);
  1442. memset(&qi, 0, sizeof(struct ath9k_tx_queue_info));
  1443. qi.tqi_aifs = params->aifs;
  1444. qi.tqi_cwmin = params->cw_min;
  1445. qi.tqi_cwmax = params->cw_max;
  1446. qi.tqi_burstTime = params->txop;
  1447. qnum = ath_get_hal_qnum(queue, sc);
  1448. ath_print(common, ATH_DBG_CONFIG,
  1449. "Configure tx [queue/halq] [%d/%d], "
  1450. "aifs: %d, cw_min: %d, cw_max: %d, txop: %d\n",
  1451. queue, qnum, params->aifs, params->cw_min,
  1452. params->cw_max, params->txop);
  1453. ret = ath_txq_update(sc, qnum, &qi);
  1454. if (ret)
  1455. ath_print(common, ATH_DBG_FATAL, "TXQ Update failed\n");
  1456. if (sc->sc_ah->opmode == NL80211_IFTYPE_ADHOC)
  1457. if ((qnum == sc->tx.hwq_map[WME_AC_BE]) && !ret)
  1458. ath_beaconq_config(sc);
  1459. mutex_unlock(&sc->mutex);
  1460. return ret;
  1461. }
  1462. static int ath9k_set_key(struct ieee80211_hw *hw,
  1463. enum set_key_cmd cmd,
  1464. struct ieee80211_vif *vif,
  1465. struct ieee80211_sta *sta,
  1466. struct ieee80211_key_conf *key)
  1467. {
  1468. struct ath_wiphy *aphy = hw->priv;
  1469. struct ath_softc *sc = aphy->sc;
  1470. struct ath_common *common = ath9k_hw_common(sc->sc_ah);
  1471. int ret = 0;
  1472. if (modparam_nohwcrypt)
  1473. return -ENOSPC;
  1474. mutex_lock(&sc->mutex);
  1475. ath9k_ps_wakeup(sc);
  1476. ath_print(common, ATH_DBG_CONFIG, "Set HW Key\n");
  1477. switch (cmd) {
  1478. case SET_KEY:
  1479. ret = ath_key_config(common, vif, sta, key);
  1480. if (ret >= 0) {
  1481. key->hw_key_idx = ret;
  1482. /* push IV and Michael MIC generation to stack */
  1483. key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
  1484. if (key->cipher == WLAN_CIPHER_SUITE_TKIP)
  1485. key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
  1486. if (sc->sc_ah->sw_mgmt_crypto &&
  1487. key->cipher == WLAN_CIPHER_SUITE_CCMP)
  1488. key->flags |= IEEE80211_KEY_FLAG_SW_MGMT;
  1489. ret = 0;
  1490. }
  1491. break;
  1492. case DISABLE_KEY:
  1493. ath_key_delete(common, key);
  1494. break;
  1495. default:
  1496. ret = -EINVAL;
  1497. }
  1498. ath9k_ps_restore(sc);
  1499. mutex_unlock(&sc->mutex);
  1500. return ret;
  1501. }
  1502. static void ath9k_bss_info_changed(struct ieee80211_hw *hw,
  1503. struct ieee80211_vif *vif,
  1504. struct ieee80211_bss_conf *bss_conf,
  1505. u32 changed)
  1506. {
  1507. struct ath_wiphy *aphy = hw->priv;
  1508. struct ath_softc *sc = aphy->sc;
  1509. struct ath_hw *ah = sc->sc_ah;
  1510. struct ath_common *common = ath9k_hw_common(ah);
  1511. struct ath_vif *avp = (void *)vif->drv_priv;
  1512. int slottime;
  1513. int error;
  1514. mutex_lock(&sc->mutex);
  1515. if (changed & BSS_CHANGED_BSSID) {
  1516. /* Set BSSID */
  1517. memcpy(common->curbssid, bss_conf->bssid, ETH_ALEN);
  1518. memcpy(avp->bssid, bss_conf->bssid, ETH_ALEN);
  1519. common->curaid = 0;
  1520. ath9k_hw_write_associd(ah);
  1521. /* Set aggregation protection mode parameters */
  1522. sc->config.ath_aggr_prot = 0;
  1523. /* Only legacy IBSS for now */
  1524. if (vif->type == NL80211_IFTYPE_ADHOC)
  1525. ath_update_chainmask(sc, 0);
  1526. ath_print(common, ATH_DBG_CONFIG,
  1527. "BSSID: %pM aid: 0x%x\n",
  1528. common->curbssid, common->curaid);
  1529. /* need to reconfigure the beacon */
  1530. sc->sc_flags &= ~SC_OP_BEACONS ;
  1531. }
  1532. /* Enable transmission of beacons (AP, IBSS, MESH) */
  1533. if ((changed & BSS_CHANGED_BEACON) ||
  1534. ((changed & BSS_CHANGED_BEACON_ENABLED) && bss_conf->enable_beacon)) {
  1535. ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
  1536. error = ath_beacon_alloc(aphy, vif);
  1537. if (!error)
  1538. ath_beacon_config(sc, vif);
  1539. }
  1540. if (changed & BSS_CHANGED_ERP_SLOT) {
  1541. if (bss_conf->use_short_slot)
  1542. slottime = 9;
  1543. else
  1544. slottime = 20;
  1545. if (vif->type == NL80211_IFTYPE_AP) {
  1546. /*
  1547. * Defer update, so that connected stations can adjust
  1548. * their settings at the same time.
  1549. * See beacon.c for more details
  1550. */
  1551. sc->beacon.slottime = slottime;
  1552. sc->beacon.updateslot = UPDATE;
  1553. } else {
  1554. ah->slottime = slottime;
  1555. ath9k_hw_init_global_settings(ah);
  1556. }
  1557. }
  1558. /* Disable transmission of beacons */
  1559. if ((changed & BSS_CHANGED_BEACON_ENABLED) && !bss_conf->enable_beacon)
  1560. ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
  1561. if (changed & BSS_CHANGED_BEACON_INT) {
  1562. sc->beacon_interval = bss_conf->beacon_int;
  1563. /*
  1564. * In case of AP mode, the HW TSF has to be reset
  1565. * when the beacon interval changes.
  1566. */
  1567. if (vif->type == NL80211_IFTYPE_AP) {
  1568. sc->sc_flags |= SC_OP_TSF_RESET;
  1569. ath9k_hw_stoptxdma(sc->sc_ah, sc->beacon.beaconq);
  1570. error = ath_beacon_alloc(aphy, vif);
  1571. if (!error)
  1572. ath_beacon_config(sc, vif);
  1573. } else {
  1574. ath_beacon_config(sc, vif);
  1575. }
  1576. }
  1577. if (changed & BSS_CHANGED_ERP_PREAMBLE) {
  1578. ath_print(common, ATH_DBG_CONFIG, "BSS Changed PREAMBLE %d\n",
  1579. bss_conf->use_short_preamble);
  1580. if (bss_conf->use_short_preamble)
  1581. sc->sc_flags |= SC_OP_PREAMBLE_SHORT;
  1582. else
  1583. sc->sc_flags &= ~SC_OP_PREAMBLE_SHORT;
  1584. }
  1585. if (changed & BSS_CHANGED_ERP_CTS_PROT) {
  1586. ath_print(common, ATH_DBG_CONFIG, "BSS Changed CTS PROT %d\n",
  1587. bss_conf->use_cts_prot);
  1588. if (bss_conf->use_cts_prot &&
  1589. hw->conf.channel->band != IEEE80211_BAND_5GHZ)
  1590. sc->sc_flags |= SC_OP_PROTECT_ENABLE;
  1591. else
  1592. sc->sc_flags &= ~SC_OP_PROTECT_ENABLE;
  1593. }
  1594. if (changed & BSS_CHANGED_ASSOC) {
  1595. ath_print(common, ATH_DBG_CONFIG, "BSS Changed ASSOC %d\n",
  1596. bss_conf->assoc);
  1597. ath9k_bss_assoc_info(sc, vif, bss_conf);
  1598. }
  1599. mutex_unlock(&sc->mutex);
  1600. }
  1601. static u64 ath9k_get_tsf(struct ieee80211_hw *hw)
  1602. {
  1603. u64 tsf;
  1604. struct ath_wiphy *aphy = hw->priv;
  1605. struct ath_softc *sc = aphy->sc;
  1606. mutex_lock(&sc->mutex);
  1607. tsf = ath9k_hw_gettsf64(sc->sc_ah);
  1608. mutex_unlock(&sc->mutex);
  1609. return tsf;
  1610. }
  1611. static void ath9k_set_tsf(struct ieee80211_hw *hw, u64 tsf)
  1612. {
  1613. struct ath_wiphy *aphy = hw->priv;
  1614. struct ath_softc *sc = aphy->sc;
  1615. mutex_lock(&sc->mutex);
  1616. ath9k_hw_settsf64(sc->sc_ah, tsf);
  1617. mutex_unlock(&sc->mutex);
  1618. }
  1619. static void ath9k_reset_tsf(struct ieee80211_hw *hw)
  1620. {
  1621. struct ath_wiphy *aphy = hw->priv;
  1622. struct ath_softc *sc = aphy->sc;
  1623. mutex_lock(&sc->mutex);
  1624. ath9k_ps_wakeup(sc);
  1625. ath9k_hw_reset_tsf(sc->sc_ah);
  1626. ath9k_ps_restore(sc);
  1627. mutex_unlock(&sc->mutex);
  1628. }
  1629. static int ath9k_ampdu_action(struct ieee80211_hw *hw,
  1630. struct ieee80211_vif *vif,
  1631. enum ieee80211_ampdu_mlme_action action,
  1632. struct ieee80211_sta *sta,
  1633. u16 tid, u16 *ssn)
  1634. {
  1635. struct ath_wiphy *aphy = hw->priv;
  1636. struct ath_softc *sc = aphy->sc;
  1637. int ret = 0;
  1638. local_bh_disable();
  1639. switch (action) {
  1640. case IEEE80211_AMPDU_RX_START:
  1641. if (!(sc->sc_flags & SC_OP_RXAGGR))
  1642. ret = -ENOTSUPP;
  1643. break;
  1644. case IEEE80211_AMPDU_RX_STOP:
  1645. break;
  1646. case IEEE80211_AMPDU_TX_START:
  1647. ath9k_ps_wakeup(sc);
  1648. ret = ath_tx_aggr_start(sc, sta, tid, ssn);
  1649. if (!ret)
  1650. ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1651. ath9k_ps_restore(sc);
  1652. break;
  1653. case IEEE80211_AMPDU_TX_STOP:
  1654. ath9k_ps_wakeup(sc);
  1655. ath_tx_aggr_stop(sc, sta, tid);
  1656. ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
  1657. ath9k_ps_restore(sc);
  1658. break;
  1659. case IEEE80211_AMPDU_TX_OPERATIONAL:
  1660. ath9k_ps_wakeup(sc);
  1661. ath_tx_aggr_resume(sc, sta, tid);
  1662. ath9k_ps_restore(sc);
  1663. break;
  1664. default:
  1665. ath_print(ath9k_hw_common(sc->sc_ah), ATH_DBG_FATAL,
  1666. "Unknown AMPDU action\n");
  1667. }
  1668. local_bh_enable();
  1669. return ret;
  1670. }
  1671. static int ath9k_get_survey(struct ieee80211_hw *hw, int idx,
  1672. struct survey_info *survey)
  1673. {
  1674. struct ath_wiphy *aphy = hw->priv;
  1675. struct ath_softc *sc = aphy->sc;
  1676. struct ath_hw *ah = sc->sc_ah;
  1677. struct ath_common *common = ath9k_hw_common(ah);
  1678. struct ieee80211_conf *conf = &hw->conf;
  1679. if (idx != 0)
  1680. return -ENOENT;
  1681. survey->channel = conf->channel;
  1682. survey->filled = SURVEY_INFO_NOISE_DBM;
  1683. survey->noise = common->ani.noise_floor;
  1684. return 0;
  1685. }
  1686. static void ath9k_sw_scan_start(struct ieee80211_hw *hw)
  1687. {
  1688. struct ath_wiphy *aphy = hw->priv;
  1689. struct ath_softc *sc = aphy->sc;
  1690. mutex_lock(&sc->mutex);
  1691. if (ath9k_wiphy_scanning(sc)) {
  1692. /*
  1693. * There is a race here in mac80211 but fixing it requires
  1694. * we revisit how we handle the scan complete callback.
  1695. * After mac80211 fixes we will not have configured hardware
  1696. * to the home channel nor would we have configured the RX
  1697. * filter yet.
  1698. */
  1699. mutex_unlock(&sc->mutex);
  1700. return;
  1701. }
  1702. aphy->state = ATH_WIPHY_SCAN;
  1703. ath9k_wiphy_pause_all_forced(sc, aphy);
  1704. mutex_unlock(&sc->mutex);
  1705. }
  1706. /*
  1707. * XXX: this requires a revisit after the driver
  1708. * scan_complete gets moved to another place/removed in mac80211.
  1709. */
  1710. static void ath9k_sw_scan_complete(struct ieee80211_hw *hw)
  1711. {
  1712. struct ath_wiphy *aphy = hw->priv;
  1713. struct ath_softc *sc = aphy->sc;
  1714. mutex_lock(&sc->mutex);
  1715. aphy->state = ATH_WIPHY_ACTIVE;
  1716. mutex_unlock(&sc->mutex);
  1717. }
  1718. static void ath9k_set_coverage_class(struct ieee80211_hw *hw, u8 coverage_class)
  1719. {
  1720. struct ath_wiphy *aphy = hw->priv;
  1721. struct ath_softc *sc = aphy->sc;
  1722. struct ath_hw *ah = sc->sc_ah;
  1723. mutex_lock(&sc->mutex);
  1724. ah->coverage_class = coverage_class;
  1725. ath9k_hw_init_global_settings(ah);
  1726. mutex_unlock(&sc->mutex);
  1727. }
  1728. struct ieee80211_ops ath9k_ops = {
  1729. .tx = ath9k_tx,
  1730. .start = ath9k_start,
  1731. .stop = ath9k_stop,
  1732. .add_interface = ath9k_add_interface,
  1733. .remove_interface = ath9k_remove_interface,
  1734. .config = ath9k_config,
  1735. .configure_filter = ath9k_configure_filter,
  1736. .sta_add = ath9k_sta_add,
  1737. .sta_remove = ath9k_sta_remove,
  1738. .conf_tx = ath9k_conf_tx,
  1739. .bss_info_changed = ath9k_bss_info_changed,
  1740. .set_key = ath9k_set_key,
  1741. .get_tsf = ath9k_get_tsf,
  1742. .set_tsf = ath9k_set_tsf,
  1743. .reset_tsf = ath9k_reset_tsf,
  1744. .ampdu_action = ath9k_ampdu_action,
  1745. .get_survey = ath9k_get_survey,
  1746. .sw_scan_start = ath9k_sw_scan_start,
  1747. .sw_scan_complete = ath9k_sw_scan_complete,
  1748. .rfkill_poll = ath9k_rfkill_poll_state,
  1749. .set_coverage_class = ath9k_set_coverage_class,
  1750. };