x86.c 116 KB

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  1. /*
  2. * Kernel-based Virtual Machine driver for Linux
  3. *
  4. * derived from drivers/kvm/kvm_main.c
  5. *
  6. * Copyright (C) 2006 Qumranet, Inc.
  7. * Copyright (C) 2008 Qumranet, Inc.
  8. * Copyright IBM Corporation, 2008
  9. *
  10. * Authors:
  11. * Avi Kivity <avi@qumranet.com>
  12. * Yaniv Kamay <yaniv@qumranet.com>
  13. * Amit Shah <amit.shah@qumranet.com>
  14. * Ben-Ami Yassour <benami@il.ibm.com>
  15. *
  16. * This work is licensed under the terms of the GNU GPL, version 2. See
  17. * the COPYING file in the top-level directory.
  18. *
  19. */
  20. #include <linux/kvm_host.h>
  21. #include "irq.h"
  22. #include "mmu.h"
  23. #include "i8254.h"
  24. #include "tss.h"
  25. #include "kvm_cache_regs.h"
  26. #include "x86.h"
  27. #include <linux/clocksource.h>
  28. #include <linux/interrupt.h>
  29. #include <linux/kvm.h>
  30. #include <linux/fs.h>
  31. #include <linux/vmalloc.h>
  32. #include <linux/module.h>
  33. #include <linux/mman.h>
  34. #include <linux/highmem.h>
  35. #include <linux/iommu.h>
  36. #include <linux/intel-iommu.h>
  37. #include <linux/cpufreq.h>
  38. #include <asm/uaccess.h>
  39. #include <asm/msr.h>
  40. #include <asm/desc.h>
  41. #include <asm/mtrr.h>
  42. #include <asm/mce.h>
  43. #define MAX_IO_MSRS 256
  44. #define CR0_RESERVED_BITS \
  45. (~(unsigned long)(X86_CR0_PE | X86_CR0_MP | X86_CR0_EM | X86_CR0_TS \
  46. | X86_CR0_ET | X86_CR0_NE | X86_CR0_WP | X86_CR0_AM \
  47. | X86_CR0_NW | X86_CR0_CD | X86_CR0_PG))
  48. #define CR4_RESERVED_BITS \
  49. (~(unsigned long)(X86_CR4_VME | X86_CR4_PVI | X86_CR4_TSD | X86_CR4_DE\
  50. | X86_CR4_PSE | X86_CR4_PAE | X86_CR4_MCE \
  51. | X86_CR4_PGE | X86_CR4_PCE | X86_CR4_OSFXSR \
  52. | X86_CR4_OSXMMEXCPT | X86_CR4_VMXE))
  53. #define CR8_RESERVED_BITS (~(unsigned long)X86_CR8_TPR)
  54. #define KVM_MAX_MCE_BANKS 32
  55. #define KVM_MCE_CAP_SUPPORTED MCG_CTL_P
  56. /* EFER defaults:
  57. * - enable syscall per default because its emulated by KVM
  58. * - enable LME and LMA per default on 64 bit KVM
  59. */
  60. #ifdef CONFIG_X86_64
  61. static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffafeULL;
  62. #else
  63. static u64 __read_mostly efer_reserved_bits = 0xfffffffffffffffeULL;
  64. #endif
  65. #define VM_STAT(x) offsetof(struct kvm, stat.x), KVM_STAT_VM
  66. #define VCPU_STAT(x) offsetof(struct kvm_vcpu, stat.x), KVM_STAT_VCPU
  67. static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
  68. struct kvm_cpuid_entry2 __user *entries);
  69. struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
  70. u32 function, u32 index);
  71. struct kvm_x86_ops *kvm_x86_ops;
  72. EXPORT_SYMBOL_GPL(kvm_x86_ops);
  73. struct kvm_stats_debugfs_item debugfs_entries[] = {
  74. { "pf_fixed", VCPU_STAT(pf_fixed) },
  75. { "pf_guest", VCPU_STAT(pf_guest) },
  76. { "tlb_flush", VCPU_STAT(tlb_flush) },
  77. { "invlpg", VCPU_STAT(invlpg) },
  78. { "exits", VCPU_STAT(exits) },
  79. { "io_exits", VCPU_STAT(io_exits) },
  80. { "mmio_exits", VCPU_STAT(mmio_exits) },
  81. { "signal_exits", VCPU_STAT(signal_exits) },
  82. { "irq_window", VCPU_STAT(irq_window_exits) },
  83. { "nmi_window", VCPU_STAT(nmi_window_exits) },
  84. { "halt_exits", VCPU_STAT(halt_exits) },
  85. { "halt_wakeup", VCPU_STAT(halt_wakeup) },
  86. { "hypercalls", VCPU_STAT(hypercalls) },
  87. { "request_irq", VCPU_STAT(request_irq_exits) },
  88. { "irq_exits", VCPU_STAT(irq_exits) },
  89. { "host_state_reload", VCPU_STAT(host_state_reload) },
  90. { "efer_reload", VCPU_STAT(efer_reload) },
  91. { "fpu_reload", VCPU_STAT(fpu_reload) },
  92. { "insn_emulation", VCPU_STAT(insn_emulation) },
  93. { "insn_emulation_fail", VCPU_STAT(insn_emulation_fail) },
  94. { "irq_injections", VCPU_STAT(irq_injections) },
  95. { "nmi_injections", VCPU_STAT(nmi_injections) },
  96. { "mmu_shadow_zapped", VM_STAT(mmu_shadow_zapped) },
  97. { "mmu_pte_write", VM_STAT(mmu_pte_write) },
  98. { "mmu_pte_updated", VM_STAT(mmu_pte_updated) },
  99. { "mmu_pde_zapped", VM_STAT(mmu_pde_zapped) },
  100. { "mmu_flooded", VM_STAT(mmu_flooded) },
  101. { "mmu_recycled", VM_STAT(mmu_recycled) },
  102. { "mmu_cache_miss", VM_STAT(mmu_cache_miss) },
  103. { "mmu_unsync", VM_STAT(mmu_unsync) },
  104. { "remote_tlb_flush", VM_STAT(remote_tlb_flush) },
  105. { "largepages", VM_STAT(lpages) },
  106. { NULL }
  107. };
  108. unsigned long segment_base(u16 selector)
  109. {
  110. struct descriptor_table gdt;
  111. struct desc_struct *d;
  112. unsigned long table_base;
  113. unsigned long v;
  114. if (selector == 0)
  115. return 0;
  116. asm("sgdt %0" : "=m"(gdt));
  117. table_base = gdt.base;
  118. if (selector & 4) { /* from ldt */
  119. u16 ldt_selector;
  120. asm("sldt %0" : "=g"(ldt_selector));
  121. table_base = segment_base(ldt_selector);
  122. }
  123. d = (struct desc_struct *)(table_base + (selector & ~7));
  124. v = d->base0 | ((unsigned long)d->base1 << 16) |
  125. ((unsigned long)d->base2 << 24);
  126. #ifdef CONFIG_X86_64
  127. if (d->s == 0 && (d->type == 2 || d->type == 9 || d->type == 11))
  128. v |= ((unsigned long)((struct ldttss_desc64 *)d)->base3) << 32;
  129. #endif
  130. return v;
  131. }
  132. EXPORT_SYMBOL_GPL(segment_base);
  133. u64 kvm_get_apic_base(struct kvm_vcpu *vcpu)
  134. {
  135. if (irqchip_in_kernel(vcpu->kvm))
  136. return vcpu->arch.apic_base;
  137. else
  138. return vcpu->arch.apic_base;
  139. }
  140. EXPORT_SYMBOL_GPL(kvm_get_apic_base);
  141. void kvm_set_apic_base(struct kvm_vcpu *vcpu, u64 data)
  142. {
  143. /* TODO: reserve bits check */
  144. if (irqchip_in_kernel(vcpu->kvm))
  145. kvm_lapic_set_base(vcpu, data);
  146. else
  147. vcpu->arch.apic_base = data;
  148. }
  149. EXPORT_SYMBOL_GPL(kvm_set_apic_base);
  150. void kvm_queue_exception(struct kvm_vcpu *vcpu, unsigned nr)
  151. {
  152. WARN_ON(vcpu->arch.exception.pending);
  153. vcpu->arch.exception.pending = true;
  154. vcpu->arch.exception.has_error_code = false;
  155. vcpu->arch.exception.nr = nr;
  156. }
  157. EXPORT_SYMBOL_GPL(kvm_queue_exception);
  158. void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long addr,
  159. u32 error_code)
  160. {
  161. ++vcpu->stat.pf_guest;
  162. if (vcpu->arch.exception.pending) {
  163. if (vcpu->arch.exception.nr == PF_VECTOR) {
  164. printk(KERN_DEBUG "kvm: inject_page_fault:"
  165. " double fault 0x%lx\n", addr);
  166. vcpu->arch.exception.nr = DF_VECTOR;
  167. vcpu->arch.exception.error_code = 0;
  168. } else if (vcpu->arch.exception.nr == DF_VECTOR) {
  169. /* triple fault -> shutdown */
  170. set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
  171. }
  172. return;
  173. }
  174. vcpu->arch.cr2 = addr;
  175. kvm_queue_exception_e(vcpu, PF_VECTOR, error_code);
  176. }
  177. void kvm_inject_nmi(struct kvm_vcpu *vcpu)
  178. {
  179. vcpu->arch.nmi_pending = 1;
  180. }
  181. EXPORT_SYMBOL_GPL(kvm_inject_nmi);
  182. void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code)
  183. {
  184. WARN_ON(vcpu->arch.exception.pending);
  185. vcpu->arch.exception.pending = true;
  186. vcpu->arch.exception.has_error_code = true;
  187. vcpu->arch.exception.nr = nr;
  188. vcpu->arch.exception.error_code = error_code;
  189. }
  190. EXPORT_SYMBOL_GPL(kvm_queue_exception_e);
  191. static void __queue_exception(struct kvm_vcpu *vcpu)
  192. {
  193. kvm_x86_ops->queue_exception(vcpu, vcpu->arch.exception.nr,
  194. vcpu->arch.exception.has_error_code,
  195. vcpu->arch.exception.error_code);
  196. }
  197. /*
  198. * Load the pae pdptrs. Return true is they are all valid.
  199. */
  200. int load_pdptrs(struct kvm_vcpu *vcpu, unsigned long cr3)
  201. {
  202. gfn_t pdpt_gfn = cr3 >> PAGE_SHIFT;
  203. unsigned offset = ((cr3 & (PAGE_SIZE-1)) >> 5) << 2;
  204. int i;
  205. int ret;
  206. u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
  207. ret = kvm_read_guest_page(vcpu->kvm, pdpt_gfn, pdpte,
  208. offset * sizeof(u64), sizeof(pdpte));
  209. if (ret < 0) {
  210. ret = 0;
  211. goto out;
  212. }
  213. for (i = 0; i < ARRAY_SIZE(pdpte); ++i) {
  214. if (is_present_pte(pdpte[i]) &&
  215. (pdpte[i] & vcpu->arch.mmu.rsvd_bits_mask[0][2])) {
  216. ret = 0;
  217. goto out;
  218. }
  219. }
  220. ret = 1;
  221. memcpy(vcpu->arch.pdptrs, pdpte, sizeof(vcpu->arch.pdptrs));
  222. out:
  223. return ret;
  224. }
  225. EXPORT_SYMBOL_GPL(load_pdptrs);
  226. static bool pdptrs_changed(struct kvm_vcpu *vcpu)
  227. {
  228. u64 pdpte[ARRAY_SIZE(vcpu->arch.pdptrs)];
  229. bool changed = true;
  230. int r;
  231. if (is_long_mode(vcpu) || !is_pae(vcpu))
  232. return false;
  233. r = kvm_read_guest(vcpu->kvm, vcpu->arch.cr3 & ~31u, pdpte, sizeof(pdpte));
  234. if (r < 0)
  235. goto out;
  236. changed = memcmp(pdpte, vcpu->arch.pdptrs, sizeof(pdpte)) != 0;
  237. out:
  238. return changed;
  239. }
  240. void kvm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
  241. {
  242. if (cr0 & CR0_RESERVED_BITS) {
  243. printk(KERN_DEBUG "set_cr0: 0x%lx #GP, reserved bits 0x%lx\n",
  244. cr0, vcpu->arch.cr0);
  245. kvm_inject_gp(vcpu, 0);
  246. return;
  247. }
  248. if ((cr0 & X86_CR0_NW) && !(cr0 & X86_CR0_CD)) {
  249. printk(KERN_DEBUG "set_cr0: #GP, CD == 0 && NW == 1\n");
  250. kvm_inject_gp(vcpu, 0);
  251. return;
  252. }
  253. if ((cr0 & X86_CR0_PG) && !(cr0 & X86_CR0_PE)) {
  254. printk(KERN_DEBUG "set_cr0: #GP, set PG flag "
  255. "and a clear PE flag\n");
  256. kvm_inject_gp(vcpu, 0);
  257. return;
  258. }
  259. if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
  260. #ifdef CONFIG_X86_64
  261. if ((vcpu->arch.shadow_efer & EFER_LME)) {
  262. int cs_db, cs_l;
  263. if (!is_pae(vcpu)) {
  264. printk(KERN_DEBUG "set_cr0: #GP, start paging "
  265. "in long mode while PAE is disabled\n");
  266. kvm_inject_gp(vcpu, 0);
  267. return;
  268. }
  269. kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
  270. if (cs_l) {
  271. printk(KERN_DEBUG "set_cr0: #GP, start paging "
  272. "in long mode while CS.L == 1\n");
  273. kvm_inject_gp(vcpu, 0);
  274. return;
  275. }
  276. } else
  277. #endif
  278. if (is_pae(vcpu) && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
  279. printk(KERN_DEBUG "set_cr0: #GP, pdptrs "
  280. "reserved bits\n");
  281. kvm_inject_gp(vcpu, 0);
  282. return;
  283. }
  284. }
  285. kvm_x86_ops->set_cr0(vcpu, cr0);
  286. vcpu->arch.cr0 = cr0;
  287. kvm_mmu_reset_context(vcpu);
  288. return;
  289. }
  290. EXPORT_SYMBOL_GPL(kvm_set_cr0);
  291. void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
  292. {
  293. kvm_set_cr0(vcpu, (vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f));
  294. KVMTRACE_1D(LMSW, vcpu,
  295. (u32)((vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f)),
  296. handler);
  297. }
  298. EXPORT_SYMBOL_GPL(kvm_lmsw);
  299. void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
  300. {
  301. unsigned long old_cr4 = vcpu->arch.cr4;
  302. unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
  303. if (cr4 & CR4_RESERVED_BITS) {
  304. printk(KERN_DEBUG "set_cr4: #GP, reserved bits\n");
  305. kvm_inject_gp(vcpu, 0);
  306. return;
  307. }
  308. if (is_long_mode(vcpu)) {
  309. if (!(cr4 & X86_CR4_PAE)) {
  310. printk(KERN_DEBUG "set_cr4: #GP, clearing PAE while "
  311. "in long mode\n");
  312. kvm_inject_gp(vcpu, 0);
  313. return;
  314. }
  315. } else if (is_paging(vcpu) && (cr4 & X86_CR4_PAE)
  316. && ((cr4 ^ old_cr4) & pdptr_bits)
  317. && !load_pdptrs(vcpu, vcpu->arch.cr3)) {
  318. printk(KERN_DEBUG "set_cr4: #GP, pdptrs reserved bits\n");
  319. kvm_inject_gp(vcpu, 0);
  320. return;
  321. }
  322. if (cr4 & X86_CR4_VMXE) {
  323. printk(KERN_DEBUG "set_cr4: #GP, setting VMXE\n");
  324. kvm_inject_gp(vcpu, 0);
  325. return;
  326. }
  327. kvm_x86_ops->set_cr4(vcpu, cr4);
  328. vcpu->arch.cr4 = cr4;
  329. vcpu->arch.mmu.base_role.cr4_pge = (cr4 & X86_CR4_PGE) && !tdp_enabled;
  330. kvm_mmu_reset_context(vcpu);
  331. }
  332. EXPORT_SYMBOL_GPL(kvm_set_cr4);
  333. void kvm_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
  334. {
  335. if (cr3 == vcpu->arch.cr3 && !pdptrs_changed(vcpu)) {
  336. kvm_mmu_sync_roots(vcpu);
  337. kvm_mmu_flush_tlb(vcpu);
  338. return;
  339. }
  340. if (is_long_mode(vcpu)) {
  341. if (cr3 & CR3_L_MODE_RESERVED_BITS) {
  342. printk(KERN_DEBUG "set_cr3: #GP, reserved bits\n");
  343. kvm_inject_gp(vcpu, 0);
  344. return;
  345. }
  346. } else {
  347. if (is_pae(vcpu)) {
  348. if (cr3 & CR3_PAE_RESERVED_BITS) {
  349. printk(KERN_DEBUG
  350. "set_cr3: #GP, reserved bits\n");
  351. kvm_inject_gp(vcpu, 0);
  352. return;
  353. }
  354. if (is_paging(vcpu) && !load_pdptrs(vcpu, cr3)) {
  355. printk(KERN_DEBUG "set_cr3: #GP, pdptrs "
  356. "reserved bits\n");
  357. kvm_inject_gp(vcpu, 0);
  358. return;
  359. }
  360. }
  361. /*
  362. * We don't check reserved bits in nonpae mode, because
  363. * this isn't enforced, and VMware depends on this.
  364. */
  365. }
  366. /*
  367. * Does the new cr3 value map to physical memory? (Note, we
  368. * catch an invalid cr3 even in real-mode, because it would
  369. * cause trouble later on when we turn on paging anyway.)
  370. *
  371. * A real CPU would silently accept an invalid cr3 and would
  372. * attempt to use it - with largely undefined (and often hard
  373. * to debug) behavior on the guest side.
  374. */
  375. if (unlikely(!gfn_to_memslot(vcpu->kvm, cr3 >> PAGE_SHIFT)))
  376. kvm_inject_gp(vcpu, 0);
  377. else {
  378. vcpu->arch.cr3 = cr3;
  379. vcpu->arch.mmu.new_cr3(vcpu);
  380. }
  381. }
  382. EXPORT_SYMBOL_GPL(kvm_set_cr3);
  383. void kvm_set_cr8(struct kvm_vcpu *vcpu, unsigned long cr8)
  384. {
  385. if (cr8 & CR8_RESERVED_BITS) {
  386. printk(KERN_DEBUG "set_cr8: #GP, reserved bits 0x%lx\n", cr8);
  387. kvm_inject_gp(vcpu, 0);
  388. return;
  389. }
  390. if (irqchip_in_kernel(vcpu->kvm))
  391. kvm_lapic_set_tpr(vcpu, cr8);
  392. else
  393. vcpu->arch.cr8 = cr8;
  394. }
  395. EXPORT_SYMBOL_GPL(kvm_set_cr8);
  396. unsigned long kvm_get_cr8(struct kvm_vcpu *vcpu)
  397. {
  398. if (irqchip_in_kernel(vcpu->kvm))
  399. return kvm_lapic_get_cr8(vcpu);
  400. else
  401. return vcpu->arch.cr8;
  402. }
  403. EXPORT_SYMBOL_GPL(kvm_get_cr8);
  404. static inline u32 bit(int bitno)
  405. {
  406. return 1 << (bitno & 31);
  407. }
  408. /*
  409. * List of msr numbers which we expose to userspace through KVM_GET_MSRS
  410. * and KVM_SET_MSRS, and KVM_GET_MSR_INDEX_LIST.
  411. *
  412. * This list is modified at module load time to reflect the
  413. * capabilities of the host cpu.
  414. */
  415. static u32 msrs_to_save[] = {
  416. MSR_IA32_SYSENTER_CS, MSR_IA32_SYSENTER_ESP, MSR_IA32_SYSENTER_EIP,
  417. MSR_K6_STAR,
  418. #ifdef CONFIG_X86_64
  419. MSR_CSTAR, MSR_KERNEL_GS_BASE, MSR_SYSCALL_MASK, MSR_LSTAR,
  420. #endif
  421. MSR_IA32_TSC, MSR_KVM_SYSTEM_TIME, MSR_KVM_WALL_CLOCK,
  422. MSR_IA32_PERF_STATUS, MSR_IA32_CR_PAT, MSR_VM_HSAVE_PA
  423. };
  424. static unsigned num_msrs_to_save;
  425. static u32 emulated_msrs[] = {
  426. MSR_IA32_MISC_ENABLE,
  427. };
  428. static void set_efer(struct kvm_vcpu *vcpu, u64 efer)
  429. {
  430. if (efer & efer_reserved_bits) {
  431. printk(KERN_DEBUG "set_efer: 0x%llx #GP, reserved bits\n",
  432. efer);
  433. kvm_inject_gp(vcpu, 0);
  434. return;
  435. }
  436. if (is_paging(vcpu)
  437. && (vcpu->arch.shadow_efer & EFER_LME) != (efer & EFER_LME)) {
  438. printk(KERN_DEBUG "set_efer: #GP, change LME while paging\n");
  439. kvm_inject_gp(vcpu, 0);
  440. return;
  441. }
  442. if (efer & EFER_FFXSR) {
  443. struct kvm_cpuid_entry2 *feat;
  444. feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
  445. if (!feat || !(feat->edx & bit(X86_FEATURE_FXSR_OPT))) {
  446. printk(KERN_DEBUG "set_efer: #GP, enable FFXSR w/o CPUID capability\n");
  447. kvm_inject_gp(vcpu, 0);
  448. return;
  449. }
  450. }
  451. if (efer & EFER_SVME) {
  452. struct kvm_cpuid_entry2 *feat;
  453. feat = kvm_find_cpuid_entry(vcpu, 0x80000001, 0);
  454. if (!feat || !(feat->ecx & bit(X86_FEATURE_SVM))) {
  455. printk(KERN_DEBUG "set_efer: #GP, enable SVM w/o SVM\n");
  456. kvm_inject_gp(vcpu, 0);
  457. return;
  458. }
  459. }
  460. kvm_x86_ops->set_efer(vcpu, efer);
  461. efer &= ~EFER_LMA;
  462. efer |= vcpu->arch.shadow_efer & EFER_LMA;
  463. vcpu->arch.shadow_efer = efer;
  464. vcpu->arch.mmu.base_role.nxe = (efer & EFER_NX) && !tdp_enabled;
  465. kvm_mmu_reset_context(vcpu);
  466. }
  467. void kvm_enable_efer_bits(u64 mask)
  468. {
  469. efer_reserved_bits &= ~mask;
  470. }
  471. EXPORT_SYMBOL_GPL(kvm_enable_efer_bits);
  472. /*
  473. * Writes msr value into into the appropriate "register".
  474. * Returns 0 on success, non-0 otherwise.
  475. * Assumes vcpu_load() was already called.
  476. */
  477. int kvm_set_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 data)
  478. {
  479. return kvm_x86_ops->set_msr(vcpu, msr_index, data);
  480. }
  481. /*
  482. * Adapt set_msr() to msr_io()'s calling convention
  483. */
  484. static int do_set_msr(struct kvm_vcpu *vcpu, unsigned index, u64 *data)
  485. {
  486. return kvm_set_msr(vcpu, index, *data);
  487. }
  488. static void kvm_write_wall_clock(struct kvm *kvm, gpa_t wall_clock)
  489. {
  490. static int version;
  491. struct pvclock_wall_clock wc;
  492. struct timespec now, sys, boot;
  493. if (!wall_clock)
  494. return;
  495. version++;
  496. kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
  497. /*
  498. * The guest calculates current wall clock time by adding
  499. * system time (updated by kvm_write_guest_time below) to the
  500. * wall clock specified here. guest system time equals host
  501. * system time for us, thus we must fill in host boot time here.
  502. */
  503. now = current_kernel_time();
  504. ktime_get_ts(&sys);
  505. boot = ns_to_timespec(timespec_to_ns(&now) - timespec_to_ns(&sys));
  506. wc.sec = boot.tv_sec;
  507. wc.nsec = boot.tv_nsec;
  508. wc.version = version;
  509. kvm_write_guest(kvm, wall_clock, &wc, sizeof(wc));
  510. version++;
  511. kvm_write_guest(kvm, wall_clock, &version, sizeof(version));
  512. }
  513. static uint32_t div_frac(uint32_t dividend, uint32_t divisor)
  514. {
  515. uint32_t quotient, remainder;
  516. /* Don't try to replace with do_div(), this one calculates
  517. * "(dividend << 32) / divisor" */
  518. __asm__ ( "divl %4"
  519. : "=a" (quotient), "=d" (remainder)
  520. : "0" (0), "1" (dividend), "r" (divisor) );
  521. return quotient;
  522. }
  523. static void kvm_set_time_scale(uint32_t tsc_khz, struct pvclock_vcpu_time_info *hv_clock)
  524. {
  525. uint64_t nsecs = 1000000000LL;
  526. int32_t shift = 0;
  527. uint64_t tps64;
  528. uint32_t tps32;
  529. tps64 = tsc_khz * 1000LL;
  530. while (tps64 > nsecs*2) {
  531. tps64 >>= 1;
  532. shift--;
  533. }
  534. tps32 = (uint32_t)tps64;
  535. while (tps32 <= (uint32_t)nsecs) {
  536. tps32 <<= 1;
  537. shift++;
  538. }
  539. hv_clock->tsc_shift = shift;
  540. hv_clock->tsc_to_system_mul = div_frac(nsecs, tps32);
  541. pr_debug("%s: tsc_khz %u, tsc_shift %d, tsc_mul %u\n",
  542. __func__, tsc_khz, hv_clock->tsc_shift,
  543. hv_clock->tsc_to_system_mul);
  544. }
  545. static DEFINE_PER_CPU(unsigned long, cpu_tsc_khz);
  546. static void kvm_write_guest_time(struct kvm_vcpu *v)
  547. {
  548. struct timespec ts;
  549. unsigned long flags;
  550. struct kvm_vcpu_arch *vcpu = &v->arch;
  551. void *shared_kaddr;
  552. unsigned long this_tsc_khz;
  553. if ((!vcpu->time_page))
  554. return;
  555. this_tsc_khz = get_cpu_var(cpu_tsc_khz);
  556. if (unlikely(vcpu->hv_clock_tsc_khz != this_tsc_khz)) {
  557. kvm_set_time_scale(this_tsc_khz, &vcpu->hv_clock);
  558. vcpu->hv_clock_tsc_khz = this_tsc_khz;
  559. }
  560. put_cpu_var(cpu_tsc_khz);
  561. /* Keep irq disabled to prevent changes to the clock */
  562. local_irq_save(flags);
  563. kvm_get_msr(v, MSR_IA32_TSC, &vcpu->hv_clock.tsc_timestamp);
  564. ktime_get_ts(&ts);
  565. local_irq_restore(flags);
  566. /* With all the info we got, fill in the values */
  567. vcpu->hv_clock.system_time = ts.tv_nsec +
  568. (NSEC_PER_SEC * (u64)ts.tv_sec);
  569. /*
  570. * The interface expects us to write an even number signaling that the
  571. * update is finished. Since the guest won't see the intermediate
  572. * state, we just increase by 2 at the end.
  573. */
  574. vcpu->hv_clock.version += 2;
  575. shared_kaddr = kmap_atomic(vcpu->time_page, KM_USER0);
  576. memcpy(shared_kaddr + vcpu->time_offset, &vcpu->hv_clock,
  577. sizeof(vcpu->hv_clock));
  578. kunmap_atomic(shared_kaddr, KM_USER0);
  579. mark_page_dirty(v->kvm, vcpu->time >> PAGE_SHIFT);
  580. }
  581. static int kvm_request_guest_time_update(struct kvm_vcpu *v)
  582. {
  583. struct kvm_vcpu_arch *vcpu = &v->arch;
  584. if (!vcpu->time_page)
  585. return 0;
  586. set_bit(KVM_REQ_KVMCLOCK_UPDATE, &v->requests);
  587. return 1;
  588. }
  589. static bool msr_mtrr_valid(unsigned msr)
  590. {
  591. switch (msr) {
  592. case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
  593. case MSR_MTRRfix64K_00000:
  594. case MSR_MTRRfix16K_80000:
  595. case MSR_MTRRfix16K_A0000:
  596. case MSR_MTRRfix4K_C0000:
  597. case MSR_MTRRfix4K_C8000:
  598. case MSR_MTRRfix4K_D0000:
  599. case MSR_MTRRfix4K_D8000:
  600. case MSR_MTRRfix4K_E0000:
  601. case MSR_MTRRfix4K_E8000:
  602. case MSR_MTRRfix4K_F0000:
  603. case MSR_MTRRfix4K_F8000:
  604. case MSR_MTRRdefType:
  605. case MSR_IA32_CR_PAT:
  606. return true;
  607. case 0x2f8:
  608. return true;
  609. }
  610. return false;
  611. }
  612. static bool valid_pat_type(unsigned t)
  613. {
  614. return t < 8 && (1 << t) & 0xf3; /* 0, 1, 4, 5, 6, 7 */
  615. }
  616. static bool valid_mtrr_type(unsigned t)
  617. {
  618. return t < 8 && (1 << t) & 0x73; /* 0, 1, 4, 5, 6 */
  619. }
  620. static bool mtrr_valid(struct kvm_vcpu *vcpu, u32 msr, u64 data)
  621. {
  622. int i;
  623. if (!msr_mtrr_valid(msr))
  624. return false;
  625. if (msr == MSR_IA32_CR_PAT) {
  626. for (i = 0; i < 8; i++)
  627. if (!valid_pat_type((data >> (i * 8)) & 0xff))
  628. return false;
  629. return true;
  630. } else if (msr == MSR_MTRRdefType) {
  631. if (data & ~0xcff)
  632. return false;
  633. return valid_mtrr_type(data & 0xff);
  634. } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
  635. for (i = 0; i < 8 ; i++)
  636. if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
  637. return false;
  638. return true;
  639. }
  640. /* variable MTRRs */
  641. return valid_mtrr_type(data & 0xff);
  642. }
  643. static int set_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 data)
  644. {
  645. u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
  646. if (!mtrr_valid(vcpu, msr, data))
  647. return 1;
  648. if (msr == MSR_MTRRdefType) {
  649. vcpu->arch.mtrr_state.def_type = data;
  650. vcpu->arch.mtrr_state.enabled = (data & 0xc00) >> 10;
  651. } else if (msr == MSR_MTRRfix64K_00000)
  652. p[0] = data;
  653. else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
  654. p[1 + msr - MSR_MTRRfix16K_80000] = data;
  655. else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
  656. p[3 + msr - MSR_MTRRfix4K_C0000] = data;
  657. else if (msr == MSR_IA32_CR_PAT)
  658. vcpu->arch.pat = data;
  659. else { /* Variable MTRRs */
  660. int idx, is_mtrr_mask;
  661. u64 *pt;
  662. idx = (msr - 0x200) / 2;
  663. is_mtrr_mask = msr - 0x200 - 2 * idx;
  664. if (!is_mtrr_mask)
  665. pt =
  666. (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
  667. else
  668. pt =
  669. (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
  670. *pt = data;
  671. }
  672. kvm_mmu_reset_context(vcpu);
  673. return 0;
  674. }
  675. static int set_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 data)
  676. {
  677. u64 mcg_cap = vcpu->arch.mcg_cap;
  678. unsigned bank_num = mcg_cap & 0xff;
  679. switch (msr) {
  680. case MSR_IA32_MCG_STATUS:
  681. vcpu->arch.mcg_status = data;
  682. break;
  683. case MSR_IA32_MCG_CTL:
  684. if (!(mcg_cap & MCG_CTL_P))
  685. return 1;
  686. if (data != 0 && data != ~(u64)0)
  687. return -1;
  688. vcpu->arch.mcg_ctl = data;
  689. break;
  690. default:
  691. if (msr >= MSR_IA32_MC0_CTL &&
  692. msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
  693. u32 offset = msr - MSR_IA32_MC0_CTL;
  694. /* only 0 or all 1s can be written to IA32_MCi_CTL */
  695. if ((offset & 0x3) == 0 &&
  696. data != 0 && data != ~(u64)0)
  697. return -1;
  698. vcpu->arch.mce_banks[offset] = data;
  699. break;
  700. }
  701. return 1;
  702. }
  703. return 0;
  704. }
  705. int kvm_set_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 data)
  706. {
  707. switch (msr) {
  708. case MSR_EFER:
  709. set_efer(vcpu, data);
  710. break;
  711. case MSR_IA32_DEBUGCTLMSR:
  712. if (!data) {
  713. /* We support the non-activated case already */
  714. break;
  715. } else if (data & ~(DEBUGCTLMSR_LBR | DEBUGCTLMSR_BTF)) {
  716. /* Values other than LBR and BTF are vendor-specific,
  717. thus reserved and should throw a #GP */
  718. return 1;
  719. }
  720. pr_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTLMSR 0x%llx, nop\n",
  721. __func__, data);
  722. break;
  723. case MSR_IA32_UCODE_REV:
  724. case MSR_IA32_UCODE_WRITE:
  725. case MSR_VM_HSAVE_PA:
  726. break;
  727. case 0x200 ... 0x2ff:
  728. return set_msr_mtrr(vcpu, msr, data);
  729. case MSR_IA32_APICBASE:
  730. kvm_set_apic_base(vcpu, data);
  731. break;
  732. case MSR_IA32_MISC_ENABLE:
  733. vcpu->arch.ia32_misc_enable_msr = data;
  734. break;
  735. case MSR_KVM_WALL_CLOCK:
  736. vcpu->kvm->arch.wall_clock = data;
  737. kvm_write_wall_clock(vcpu->kvm, data);
  738. break;
  739. case MSR_KVM_SYSTEM_TIME: {
  740. if (vcpu->arch.time_page) {
  741. kvm_release_page_dirty(vcpu->arch.time_page);
  742. vcpu->arch.time_page = NULL;
  743. }
  744. vcpu->arch.time = data;
  745. /* we verify if the enable bit is set... */
  746. if (!(data & 1))
  747. break;
  748. /* ...but clean it before doing the actual write */
  749. vcpu->arch.time_offset = data & ~(PAGE_MASK | 1);
  750. vcpu->arch.time_page =
  751. gfn_to_page(vcpu->kvm, data >> PAGE_SHIFT);
  752. if (is_error_page(vcpu->arch.time_page)) {
  753. kvm_release_page_clean(vcpu->arch.time_page);
  754. vcpu->arch.time_page = NULL;
  755. }
  756. kvm_request_guest_time_update(vcpu);
  757. break;
  758. }
  759. case MSR_IA32_MCG_CTL:
  760. case MSR_IA32_MCG_STATUS:
  761. case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
  762. return set_msr_mce(vcpu, msr, data);
  763. default:
  764. pr_unimpl(vcpu, "unhandled wrmsr: 0x%x data %llx\n", msr, data);
  765. return 1;
  766. }
  767. return 0;
  768. }
  769. EXPORT_SYMBOL_GPL(kvm_set_msr_common);
  770. /*
  771. * Reads an msr value (of 'msr_index') into 'pdata'.
  772. * Returns 0 on success, non-0 otherwise.
  773. * Assumes vcpu_load() was already called.
  774. */
  775. int kvm_get_msr(struct kvm_vcpu *vcpu, u32 msr_index, u64 *pdata)
  776. {
  777. return kvm_x86_ops->get_msr(vcpu, msr_index, pdata);
  778. }
  779. static int get_msr_mtrr(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
  780. {
  781. u64 *p = (u64 *)&vcpu->arch.mtrr_state.fixed_ranges;
  782. if (!msr_mtrr_valid(msr))
  783. return 1;
  784. if (msr == MSR_MTRRdefType)
  785. *pdata = vcpu->arch.mtrr_state.def_type +
  786. (vcpu->arch.mtrr_state.enabled << 10);
  787. else if (msr == MSR_MTRRfix64K_00000)
  788. *pdata = p[0];
  789. else if (msr == MSR_MTRRfix16K_80000 || msr == MSR_MTRRfix16K_A0000)
  790. *pdata = p[1 + msr - MSR_MTRRfix16K_80000];
  791. else if (msr >= MSR_MTRRfix4K_C0000 && msr <= MSR_MTRRfix4K_F8000)
  792. *pdata = p[3 + msr - MSR_MTRRfix4K_C0000];
  793. else if (msr == MSR_IA32_CR_PAT)
  794. *pdata = vcpu->arch.pat;
  795. else { /* Variable MTRRs */
  796. int idx, is_mtrr_mask;
  797. u64 *pt;
  798. idx = (msr - 0x200) / 2;
  799. is_mtrr_mask = msr - 0x200 - 2 * idx;
  800. if (!is_mtrr_mask)
  801. pt =
  802. (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].base_lo;
  803. else
  804. pt =
  805. (u64 *)&vcpu->arch.mtrr_state.var_ranges[idx].mask_lo;
  806. *pdata = *pt;
  807. }
  808. return 0;
  809. }
  810. static int get_msr_mce(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
  811. {
  812. u64 data;
  813. u64 mcg_cap = vcpu->arch.mcg_cap;
  814. unsigned bank_num = mcg_cap & 0xff;
  815. switch (msr) {
  816. case MSR_IA32_P5_MC_ADDR:
  817. case MSR_IA32_P5_MC_TYPE:
  818. data = 0;
  819. break;
  820. case MSR_IA32_MCG_CAP:
  821. data = vcpu->arch.mcg_cap;
  822. break;
  823. case MSR_IA32_MCG_CTL:
  824. if (!(mcg_cap & MCG_CTL_P))
  825. return 1;
  826. data = vcpu->arch.mcg_ctl;
  827. break;
  828. case MSR_IA32_MCG_STATUS:
  829. data = vcpu->arch.mcg_status;
  830. break;
  831. default:
  832. if (msr >= MSR_IA32_MC0_CTL &&
  833. msr < MSR_IA32_MC0_CTL + 4 * bank_num) {
  834. u32 offset = msr - MSR_IA32_MC0_CTL;
  835. data = vcpu->arch.mce_banks[offset];
  836. break;
  837. }
  838. return 1;
  839. }
  840. *pdata = data;
  841. return 0;
  842. }
  843. int kvm_get_msr_common(struct kvm_vcpu *vcpu, u32 msr, u64 *pdata)
  844. {
  845. u64 data;
  846. switch (msr) {
  847. case MSR_IA32_PLATFORM_ID:
  848. case MSR_IA32_UCODE_REV:
  849. case MSR_IA32_EBL_CR_POWERON:
  850. case MSR_IA32_DEBUGCTLMSR:
  851. case MSR_IA32_LASTBRANCHFROMIP:
  852. case MSR_IA32_LASTBRANCHTOIP:
  853. case MSR_IA32_LASTINTFROMIP:
  854. case MSR_IA32_LASTINTTOIP:
  855. case MSR_K8_SYSCFG:
  856. case MSR_K7_HWCR:
  857. case MSR_VM_HSAVE_PA:
  858. case MSR_P6_EVNTSEL0:
  859. case MSR_P6_EVNTSEL1:
  860. case MSR_K7_EVNTSEL0:
  861. data = 0;
  862. break;
  863. case MSR_MTRRcap:
  864. data = 0x500 | KVM_NR_VAR_MTRR;
  865. break;
  866. case 0x200 ... 0x2ff:
  867. return get_msr_mtrr(vcpu, msr, pdata);
  868. case 0xcd: /* fsb frequency */
  869. data = 3;
  870. break;
  871. case MSR_IA32_APICBASE:
  872. data = kvm_get_apic_base(vcpu);
  873. break;
  874. case MSR_IA32_MISC_ENABLE:
  875. data = vcpu->arch.ia32_misc_enable_msr;
  876. break;
  877. case MSR_IA32_PERF_STATUS:
  878. /* TSC increment by tick */
  879. data = 1000ULL;
  880. /* CPU multiplier */
  881. data |= (((uint64_t)4ULL) << 40);
  882. break;
  883. case MSR_EFER:
  884. data = vcpu->arch.shadow_efer;
  885. break;
  886. case MSR_KVM_WALL_CLOCK:
  887. data = vcpu->kvm->arch.wall_clock;
  888. break;
  889. case MSR_KVM_SYSTEM_TIME:
  890. data = vcpu->arch.time;
  891. break;
  892. case MSR_IA32_P5_MC_ADDR:
  893. case MSR_IA32_P5_MC_TYPE:
  894. case MSR_IA32_MCG_CAP:
  895. case MSR_IA32_MCG_CTL:
  896. case MSR_IA32_MCG_STATUS:
  897. case MSR_IA32_MC0_CTL ... MSR_IA32_MC0_CTL + 4 * KVM_MAX_MCE_BANKS - 1:
  898. return get_msr_mce(vcpu, msr, pdata);
  899. default:
  900. pr_unimpl(vcpu, "unhandled rdmsr: 0x%x\n", msr);
  901. return 1;
  902. }
  903. *pdata = data;
  904. return 0;
  905. }
  906. EXPORT_SYMBOL_GPL(kvm_get_msr_common);
  907. /*
  908. * Read or write a bunch of msrs. All parameters are kernel addresses.
  909. *
  910. * @return number of msrs set successfully.
  911. */
  912. static int __msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs *msrs,
  913. struct kvm_msr_entry *entries,
  914. int (*do_msr)(struct kvm_vcpu *vcpu,
  915. unsigned index, u64 *data))
  916. {
  917. int i;
  918. vcpu_load(vcpu);
  919. down_read(&vcpu->kvm->slots_lock);
  920. for (i = 0; i < msrs->nmsrs; ++i)
  921. if (do_msr(vcpu, entries[i].index, &entries[i].data))
  922. break;
  923. up_read(&vcpu->kvm->slots_lock);
  924. vcpu_put(vcpu);
  925. return i;
  926. }
  927. /*
  928. * Read or write a bunch of msrs. Parameters are user addresses.
  929. *
  930. * @return number of msrs set successfully.
  931. */
  932. static int msr_io(struct kvm_vcpu *vcpu, struct kvm_msrs __user *user_msrs,
  933. int (*do_msr)(struct kvm_vcpu *vcpu,
  934. unsigned index, u64 *data),
  935. int writeback)
  936. {
  937. struct kvm_msrs msrs;
  938. struct kvm_msr_entry *entries;
  939. int r, n;
  940. unsigned size;
  941. r = -EFAULT;
  942. if (copy_from_user(&msrs, user_msrs, sizeof msrs))
  943. goto out;
  944. r = -E2BIG;
  945. if (msrs.nmsrs >= MAX_IO_MSRS)
  946. goto out;
  947. r = -ENOMEM;
  948. size = sizeof(struct kvm_msr_entry) * msrs.nmsrs;
  949. entries = vmalloc(size);
  950. if (!entries)
  951. goto out;
  952. r = -EFAULT;
  953. if (copy_from_user(entries, user_msrs->entries, size))
  954. goto out_free;
  955. r = n = __msr_io(vcpu, &msrs, entries, do_msr);
  956. if (r < 0)
  957. goto out_free;
  958. r = -EFAULT;
  959. if (writeback && copy_to_user(user_msrs->entries, entries, size))
  960. goto out_free;
  961. r = n;
  962. out_free:
  963. vfree(entries);
  964. out:
  965. return r;
  966. }
  967. int kvm_dev_ioctl_check_extension(long ext)
  968. {
  969. int r;
  970. switch (ext) {
  971. case KVM_CAP_IRQCHIP:
  972. case KVM_CAP_HLT:
  973. case KVM_CAP_MMU_SHADOW_CACHE_CONTROL:
  974. case KVM_CAP_SET_TSS_ADDR:
  975. case KVM_CAP_EXT_CPUID:
  976. case KVM_CAP_CLOCKSOURCE:
  977. case KVM_CAP_PIT:
  978. case KVM_CAP_NOP_IO_DELAY:
  979. case KVM_CAP_MP_STATE:
  980. case KVM_CAP_SYNC_MMU:
  981. case KVM_CAP_REINJECT_CONTROL:
  982. case KVM_CAP_IRQ_INJECT_STATUS:
  983. case KVM_CAP_ASSIGN_DEV_IRQ:
  984. case KVM_CAP_IRQFD:
  985. r = 1;
  986. break;
  987. case KVM_CAP_COALESCED_MMIO:
  988. r = KVM_COALESCED_MMIO_PAGE_OFFSET;
  989. break;
  990. case KVM_CAP_VAPIC:
  991. r = !kvm_x86_ops->cpu_has_accelerated_tpr();
  992. break;
  993. case KVM_CAP_NR_VCPUS:
  994. r = KVM_MAX_VCPUS;
  995. break;
  996. case KVM_CAP_NR_MEMSLOTS:
  997. r = KVM_MEMORY_SLOTS;
  998. break;
  999. case KVM_CAP_PV_MMU:
  1000. r = !tdp_enabled;
  1001. break;
  1002. case KVM_CAP_IOMMU:
  1003. r = iommu_found();
  1004. break;
  1005. case KVM_CAP_MCE:
  1006. r = KVM_MAX_MCE_BANKS;
  1007. break;
  1008. default:
  1009. r = 0;
  1010. break;
  1011. }
  1012. return r;
  1013. }
  1014. long kvm_arch_dev_ioctl(struct file *filp,
  1015. unsigned int ioctl, unsigned long arg)
  1016. {
  1017. void __user *argp = (void __user *)arg;
  1018. long r;
  1019. switch (ioctl) {
  1020. case KVM_GET_MSR_INDEX_LIST: {
  1021. struct kvm_msr_list __user *user_msr_list = argp;
  1022. struct kvm_msr_list msr_list;
  1023. unsigned n;
  1024. r = -EFAULT;
  1025. if (copy_from_user(&msr_list, user_msr_list, sizeof msr_list))
  1026. goto out;
  1027. n = msr_list.nmsrs;
  1028. msr_list.nmsrs = num_msrs_to_save + ARRAY_SIZE(emulated_msrs);
  1029. if (copy_to_user(user_msr_list, &msr_list, sizeof msr_list))
  1030. goto out;
  1031. r = -E2BIG;
  1032. if (n < msr_list.nmsrs)
  1033. goto out;
  1034. r = -EFAULT;
  1035. if (copy_to_user(user_msr_list->indices, &msrs_to_save,
  1036. num_msrs_to_save * sizeof(u32)))
  1037. goto out;
  1038. if (copy_to_user(user_msr_list->indices + num_msrs_to_save,
  1039. &emulated_msrs,
  1040. ARRAY_SIZE(emulated_msrs) * sizeof(u32)))
  1041. goto out;
  1042. r = 0;
  1043. break;
  1044. }
  1045. case KVM_GET_SUPPORTED_CPUID: {
  1046. struct kvm_cpuid2 __user *cpuid_arg = argp;
  1047. struct kvm_cpuid2 cpuid;
  1048. r = -EFAULT;
  1049. if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
  1050. goto out;
  1051. r = kvm_dev_ioctl_get_supported_cpuid(&cpuid,
  1052. cpuid_arg->entries);
  1053. if (r)
  1054. goto out;
  1055. r = -EFAULT;
  1056. if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
  1057. goto out;
  1058. r = 0;
  1059. break;
  1060. }
  1061. case KVM_X86_GET_MCE_CAP_SUPPORTED: {
  1062. u64 mce_cap;
  1063. mce_cap = KVM_MCE_CAP_SUPPORTED;
  1064. r = -EFAULT;
  1065. if (copy_to_user(argp, &mce_cap, sizeof mce_cap))
  1066. goto out;
  1067. r = 0;
  1068. break;
  1069. }
  1070. default:
  1071. r = -EINVAL;
  1072. }
  1073. out:
  1074. return r;
  1075. }
  1076. void kvm_arch_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
  1077. {
  1078. kvm_x86_ops->vcpu_load(vcpu, cpu);
  1079. kvm_request_guest_time_update(vcpu);
  1080. }
  1081. void kvm_arch_vcpu_put(struct kvm_vcpu *vcpu)
  1082. {
  1083. kvm_x86_ops->vcpu_put(vcpu);
  1084. kvm_put_guest_fpu(vcpu);
  1085. }
  1086. static int is_efer_nx(void)
  1087. {
  1088. unsigned long long efer = 0;
  1089. rdmsrl_safe(MSR_EFER, &efer);
  1090. return efer & EFER_NX;
  1091. }
  1092. static void cpuid_fix_nx_cap(struct kvm_vcpu *vcpu)
  1093. {
  1094. int i;
  1095. struct kvm_cpuid_entry2 *e, *entry;
  1096. entry = NULL;
  1097. for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
  1098. e = &vcpu->arch.cpuid_entries[i];
  1099. if (e->function == 0x80000001) {
  1100. entry = e;
  1101. break;
  1102. }
  1103. }
  1104. if (entry && (entry->edx & (1 << 20)) && !is_efer_nx()) {
  1105. entry->edx &= ~(1 << 20);
  1106. printk(KERN_INFO "kvm: guest NX capability removed\n");
  1107. }
  1108. }
  1109. /* when an old userspace process fills a new kernel module */
  1110. static int kvm_vcpu_ioctl_set_cpuid(struct kvm_vcpu *vcpu,
  1111. struct kvm_cpuid *cpuid,
  1112. struct kvm_cpuid_entry __user *entries)
  1113. {
  1114. int r, i;
  1115. struct kvm_cpuid_entry *cpuid_entries;
  1116. r = -E2BIG;
  1117. if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
  1118. goto out;
  1119. r = -ENOMEM;
  1120. cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry) * cpuid->nent);
  1121. if (!cpuid_entries)
  1122. goto out;
  1123. r = -EFAULT;
  1124. if (copy_from_user(cpuid_entries, entries,
  1125. cpuid->nent * sizeof(struct kvm_cpuid_entry)))
  1126. goto out_free;
  1127. for (i = 0; i < cpuid->nent; i++) {
  1128. vcpu->arch.cpuid_entries[i].function = cpuid_entries[i].function;
  1129. vcpu->arch.cpuid_entries[i].eax = cpuid_entries[i].eax;
  1130. vcpu->arch.cpuid_entries[i].ebx = cpuid_entries[i].ebx;
  1131. vcpu->arch.cpuid_entries[i].ecx = cpuid_entries[i].ecx;
  1132. vcpu->arch.cpuid_entries[i].edx = cpuid_entries[i].edx;
  1133. vcpu->arch.cpuid_entries[i].index = 0;
  1134. vcpu->arch.cpuid_entries[i].flags = 0;
  1135. vcpu->arch.cpuid_entries[i].padding[0] = 0;
  1136. vcpu->arch.cpuid_entries[i].padding[1] = 0;
  1137. vcpu->arch.cpuid_entries[i].padding[2] = 0;
  1138. }
  1139. vcpu->arch.cpuid_nent = cpuid->nent;
  1140. cpuid_fix_nx_cap(vcpu);
  1141. r = 0;
  1142. out_free:
  1143. vfree(cpuid_entries);
  1144. out:
  1145. return r;
  1146. }
  1147. static int kvm_vcpu_ioctl_set_cpuid2(struct kvm_vcpu *vcpu,
  1148. struct kvm_cpuid2 *cpuid,
  1149. struct kvm_cpuid_entry2 __user *entries)
  1150. {
  1151. int r;
  1152. r = -E2BIG;
  1153. if (cpuid->nent > KVM_MAX_CPUID_ENTRIES)
  1154. goto out;
  1155. r = -EFAULT;
  1156. if (copy_from_user(&vcpu->arch.cpuid_entries, entries,
  1157. cpuid->nent * sizeof(struct kvm_cpuid_entry2)))
  1158. goto out;
  1159. vcpu->arch.cpuid_nent = cpuid->nent;
  1160. return 0;
  1161. out:
  1162. return r;
  1163. }
  1164. static int kvm_vcpu_ioctl_get_cpuid2(struct kvm_vcpu *vcpu,
  1165. struct kvm_cpuid2 *cpuid,
  1166. struct kvm_cpuid_entry2 __user *entries)
  1167. {
  1168. int r;
  1169. r = -E2BIG;
  1170. if (cpuid->nent < vcpu->arch.cpuid_nent)
  1171. goto out;
  1172. r = -EFAULT;
  1173. if (copy_to_user(entries, &vcpu->arch.cpuid_entries,
  1174. vcpu->arch.cpuid_nent * sizeof(struct kvm_cpuid_entry2)))
  1175. goto out;
  1176. return 0;
  1177. out:
  1178. cpuid->nent = vcpu->arch.cpuid_nent;
  1179. return r;
  1180. }
  1181. static void do_cpuid_1_ent(struct kvm_cpuid_entry2 *entry, u32 function,
  1182. u32 index)
  1183. {
  1184. entry->function = function;
  1185. entry->index = index;
  1186. cpuid_count(entry->function, entry->index,
  1187. &entry->eax, &entry->ebx, &entry->ecx, &entry->edx);
  1188. entry->flags = 0;
  1189. }
  1190. #define F(x) bit(X86_FEATURE_##x)
  1191. static void do_cpuid_ent(struct kvm_cpuid_entry2 *entry, u32 function,
  1192. u32 index, int *nent, int maxnent)
  1193. {
  1194. unsigned f_nx = is_efer_nx() ? F(NX) : 0;
  1195. #ifdef CONFIG_X86_64
  1196. unsigned f_lm = F(LM);
  1197. #else
  1198. unsigned f_lm = 0;
  1199. #endif
  1200. /* cpuid 1.edx */
  1201. const u32 kvm_supported_word0_x86_features =
  1202. F(FPU) | F(VME) | F(DE) | F(PSE) |
  1203. F(TSC) | F(MSR) | F(PAE) | F(MCE) |
  1204. F(CX8) | F(APIC) | 0 /* Reserved */ | F(SEP) |
  1205. F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
  1206. F(PAT) | F(PSE36) | 0 /* PSN */ | F(CLFLSH) |
  1207. 0 /* Reserved, DS, ACPI */ | F(MMX) |
  1208. F(FXSR) | F(XMM) | F(XMM2) | F(SELFSNOOP) |
  1209. 0 /* HTT, TM, Reserved, PBE */;
  1210. /* cpuid 0x80000001.edx */
  1211. const u32 kvm_supported_word1_x86_features =
  1212. F(FPU) | F(VME) | F(DE) | F(PSE) |
  1213. F(TSC) | F(MSR) | F(PAE) | F(MCE) |
  1214. F(CX8) | F(APIC) | 0 /* Reserved */ | F(SYSCALL) |
  1215. F(MTRR) | F(PGE) | F(MCA) | F(CMOV) |
  1216. F(PAT) | F(PSE36) | 0 /* Reserved */ |
  1217. f_nx | 0 /* Reserved */ | F(MMXEXT) | F(MMX) |
  1218. F(FXSR) | F(FXSR_OPT) | 0 /* GBPAGES */ | 0 /* RDTSCP */ |
  1219. 0 /* Reserved */ | f_lm | F(3DNOWEXT) | F(3DNOW);
  1220. /* cpuid 1.ecx */
  1221. const u32 kvm_supported_word4_x86_features =
  1222. F(XMM3) | 0 /* Reserved, DTES64, MONITOR */ |
  1223. 0 /* DS-CPL, VMX, SMX, EST */ |
  1224. 0 /* TM2 */ | F(SSSE3) | 0 /* CNXT-ID */ | 0 /* Reserved */ |
  1225. 0 /* Reserved */ | F(CX16) | 0 /* xTPR Update, PDCM */ |
  1226. 0 /* Reserved, DCA */ | F(XMM4_1) |
  1227. F(XMM4_2) | 0 /* x2APIC */ | F(MOVBE) | F(POPCNT) |
  1228. 0 /* Reserved, XSAVE, OSXSAVE */;
  1229. /* cpuid 0x80000001.ecx */
  1230. const u32 kvm_supported_word6_x86_features =
  1231. F(LAHF_LM) | F(CMP_LEGACY) | F(SVM) | 0 /* ExtApicSpace */ |
  1232. F(CR8_LEGACY) | F(ABM) | F(SSE4A) | F(MISALIGNSSE) |
  1233. F(3DNOWPREFETCH) | 0 /* OSVW */ | 0 /* IBS */ | F(SSE5) |
  1234. 0 /* SKINIT */ | 0 /* WDT */;
  1235. /* all calls to cpuid_count() should be made on the same cpu */
  1236. get_cpu();
  1237. do_cpuid_1_ent(entry, function, index);
  1238. ++*nent;
  1239. switch (function) {
  1240. case 0:
  1241. entry->eax = min(entry->eax, (u32)0xb);
  1242. break;
  1243. case 1:
  1244. entry->edx &= kvm_supported_word0_x86_features;
  1245. entry->ecx &= kvm_supported_word4_x86_features;
  1246. break;
  1247. /* function 2 entries are STATEFUL. That is, repeated cpuid commands
  1248. * may return different values. This forces us to get_cpu() before
  1249. * issuing the first command, and also to emulate this annoying behavior
  1250. * in kvm_emulate_cpuid() using KVM_CPUID_FLAG_STATE_READ_NEXT */
  1251. case 2: {
  1252. int t, times = entry->eax & 0xff;
  1253. entry->flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
  1254. entry->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
  1255. for (t = 1; t < times && *nent < maxnent; ++t) {
  1256. do_cpuid_1_ent(&entry[t], function, 0);
  1257. entry[t].flags |= KVM_CPUID_FLAG_STATEFUL_FUNC;
  1258. ++*nent;
  1259. }
  1260. break;
  1261. }
  1262. /* function 4 and 0xb have additional index. */
  1263. case 4: {
  1264. int i, cache_type;
  1265. entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
  1266. /* read more entries until cache_type is zero */
  1267. for (i = 1; *nent < maxnent; ++i) {
  1268. cache_type = entry[i - 1].eax & 0x1f;
  1269. if (!cache_type)
  1270. break;
  1271. do_cpuid_1_ent(&entry[i], function, i);
  1272. entry[i].flags |=
  1273. KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
  1274. ++*nent;
  1275. }
  1276. break;
  1277. }
  1278. case 0xb: {
  1279. int i, level_type;
  1280. entry->flags |= KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
  1281. /* read more entries until level_type is zero */
  1282. for (i = 1; *nent < maxnent; ++i) {
  1283. level_type = entry[i - 1].ecx & 0xff00;
  1284. if (!level_type)
  1285. break;
  1286. do_cpuid_1_ent(&entry[i], function, i);
  1287. entry[i].flags |=
  1288. KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
  1289. ++*nent;
  1290. }
  1291. break;
  1292. }
  1293. case 0x80000000:
  1294. entry->eax = min(entry->eax, 0x8000001a);
  1295. break;
  1296. case 0x80000001:
  1297. entry->edx &= kvm_supported_word1_x86_features;
  1298. entry->ecx &= kvm_supported_word6_x86_features;
  1299. break;
  1300. }
  1301. put_cpu();
  1302. }
  1303. #undef F
  1304. static int kvm_dev_ioctl_get_supported_cpuid(struct kvm_cpuid2 *cpuid,
  1305. struct kvm_cpuid_entry2 __user *entries)
  1306. {
  1307. struct kvm_cpuid_entry2 *cpuid_entries;
  1308. int limit, nent = 0, r = -E2BIG;
  1309. u32 func;
  1310. if (cpuid->nent < 1)
  1311. goto out;
  1312. r = -ENOMEM;
  1313. cpuid_entries = vmalloc(sizeof(struct kvm_cpuid_entry2) * cpuid->nent);
  1314. if (!cpuid_entries)
  1315. goto out;
  1316. do_cpuid_ent(&cpuid_entries[0], 0, 0, &nent, cpuid->nent);
  1317. limit = cpuid_entries[0].eax;
  1318. for (func = 1; func <= limit && nent < cpuid->nent; ++func)
  1319. do_cpuid_ent(&cpuid_entries[nent], func, 0,
  1320. &nent, cpuid->nent);
  1321. r = -E2BIG;
  1322. if (nent >= cpuid->nent)
  1323. goto out_free;
  1324. do_cpuid_ent(&cpuid_entries[nent], 0x80000000, 0, &nent, cpuid->nent);
  1325. limit = cpuid_entries[nent - 1].eax;
  1326. for (func = 0x80000001; func <= limit && nent < cpuid->nent; ++func)
  1327. do_cpuid_ent(&cpuid_entries[nent], func, 0,
  1328. &nent, cpuid->nent);
  1329. r = -E2BIG;
  1330. if (nent >= cpuid->nent)
  1331. goto out_free;
  1332. r = -EFAULT;
  1333. if (copy_to_user(entries, cpuid_entries,
  1334. nent * sizeof(struct kvm_cpuid_entry2)))
  1335. goto out_free;
  1336. cpuid->nent = nent;
  1337. r = 0;
  1338. out_free:
  1339. vfree(cpuid_entries);
  1340. out:
  1341. return r;
  1342. }
  1343. static int kvm_vcpu_ioctl_get_lapic(struct kvm_vcpu *vcpu,
  1344. struct kvm_lapic_state *s)
  1345. {
  1346. vcpu_load(vcpu);
  1347. memcpy(s->regs, vcpu->arch.apic->regs, sizeof *s);
  1348. vcpu_put(vcpu);
  1349. return 0;
  1350. }
  1351. static int kvm_vcpu_ioctl_set_lapic(struct kvm_vcpu *vcpu,
  1352. struct kvm_lapic_state *s)
  1353. {
  1354. vcpu_load(vcpu);
  1355. memcpy(vcpu->arch.apic->regs, s->regs, sizeof *s);
  1356. kvm_apic_post_state_restore(vcpu);
  1357. vcpu_put(vcpu);
  1358. return 0;
  1359. }
  1360. static int kvm_vcpu_ioctl_interrupt(struct kvm_vcpu *vcpu,
  1361. struct kvm_interrupt *irq)
  1362. {
  1363. if (irq->irq < 0 || irq->irq >= 256)
  1364. return -EINVAL;
  1365. if (irqchip_in_kernel(vcpu->kvm))
  1366. return -ENXIO;
  1367. vcpu_load(vcpu);
  1368. kvm_queue_interrupt(vcpu, irq->irq, false);
  1369. vcpu_put(vcpu);
  1370. return 0;
  1371. }
  1372. static int kvm_vcpu_ioctl_nmi(struct kvm_vcpu *vcpu)
  1373. {
  1374. vcpu_load(vcpu);
  1375. kvm_inject_nmi(vcpu);
  1376. vcpu_put(vcpu);
  1377. return 0;
  1378. }
  1379. static int vcpu_ioctl_tpr_access_reporting(struct kvm_vcpu *vcpu,
  1380. struct kvm_tpr_access_ctl *tac)
  1381. {
  1382. if (tac->flags)
  1383. return -EINVAL;
  1384. vcpu->arch.tpr_access_reporting = !!tac->enabled;
  1385. return 0;
  1386. }
  1387. static int kvm_vcpu_ioctl_x86_setup_mce(struct kvm_vcpu *vcpu,
  1388. u64 mcg_cap)
  1389. {
  1390. int r;
  1391. unsigned bank_num = mcg_cap & 0xff, bank;
  1392. r = -EINVAL;
  1393. if (!bank_num)
  1394. goto out;
  1395. if (mcg_cap & ~(KVM_MCE_CAP_SUPPORTED | 0xff | 0xff0000))
  1396. goto out;
  1397. r = 0;
  1398. vcpu->arch.mcg_cap = mcg_cap;
  1399. /* Init IA32_MCG_CTL to all 1s */
  1400. if (mcg_cap & MCG_CTL_P)
  1401. vcpu->arch.mcg_ctl = ~(u64)0;
  1402. /* Init IA32_MCi_CTL to all 1s */
  1403. for (bank = 0; bank < bank_num; bank++)
  1404. vcpu->arch.mce_banks[bank*4] = ~(u64)0;
  1405. out:
  1406. return r;
  1407. }
  1408. static int kvm_vcpu_ioctl_x86_set_mce(struct kvm_vcpu *vcpu,
  1409. struct kvm_x86_mce *mce)
  1410. {
  1411. u64 mcg_cap = vcpu->arch.mcg_cap;
  1412. unsigned bank_num = mcg_cap & 0xff;
  1413. u64 *banks = vcpu->arch.mce_banks;
  1414. if (mce->bank >= bank_num || !(mce->status & MCI_STATUS_VAL))
  1415. return -EINVAL;
  1416. /*
  1417. * if IA32_MCG_CTL is not all 1s, the uncorrected error
  1418. * reporting is disabled
  1419. */
  1420. if ((mce->status & MCI_STATUS_UC) && (mcg_cap & MCG_CTL_P) &&
  1421. vcpu->arch.mcg_ctl != ~(u64)0)
  1422. return 0;
  1423. banks += 4 * mce->bank;
  1424. /*
  1425. * if IA32_MCi_CTL is not all 1s, the uncorrected error
  1426. * reporting is disabled for the bank
  1427. */
  1428. if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
  1429. return 0;
  1430. if (mce->status & MCI_STATUS_UC) {
  1431. if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
  1432. !(vcpu->arch.cr4 & X86_CR4_MCE)) {
  1433. printk(KERN_DEBUG "kvm: set_mce: "
  1434. "injects mce exception while "
  1435. "previous one is in progress!\n");
  1436. set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
  1437. return 0;
  1438. }
  1439. if (banks[1] & MCI_STATUS_VAL)
  1440. mce->status |= MCI_STATUS_OVER;
  1441. banks[2] = mce->addr;
  1442. banks[3] = mce->misc;
  1443. vcpu->arch.mcg_status = mce->mcg_status;
  1444. banks[1] = mce->status;
  1445. kvm_queue_exception(vcpu, MC_VECTOR);
  1446. } else if (!(banks[1] & MCI_STATUS_VAL)
  1447. || !(banks[1] & MCI_STATUS_UC)) {
  1448. if (banks[1] & MCI_STATUS_VAL)
  1449. mce->status |= MCI_STATUS_OVER;
  1450. banks[2] = mce->addr;
  1451. banks[3] = mce->misc;
  1452. banks[1] = mce->status;
  1453. } else
  1454. banks[1] |= MCI_STATUS_OVER;
  1455. return 0;
  1456. }
  1457. long kvm_arch_vcpu_ioctl(struct file *filp,
  1458. unsigned int ioctl, unsigned long arg)
  1459. {
  1460. struct kvm_vcpu *vcpu = filp->private_data;
  1461. void __user *argp = (void __user *)arg;
  1462. int r;
  1463. struct kvm_lapic_state *lapic = NULL;
  1464. switch (ioctl) {
  1465. case KVM_GET_LAPIC: {
  1466. lapic = kzalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
  1467. r = -ENOMEM;
  1468. if (!lapic)
  1469. goto out;
  1470. r = kvm_vcpu_ioctl_get_lapic(vcpu, lapic);
  1471. if (r)
  1472. goto out;
  1473. r = -EFAULT;
  1474. if (copy_to_user(argp, lapic, sizeof(struct kvm_lapic_state)))
  1475. goto out;
  1476. r = 0;
  1477. break;
  1478. }
  1479. case KVM_SET_LAPIC: {
  1480. lapic = kmalloc(sizeof(struct kvm_lapic_state), GFP_KERNEL);
  1481. r = -ENOMEM;
  1482. if (!lapic)
  1483. goto out;
  1484. r = -EFAULT;
  1485. if (copy_from_user(lapic, argp, sizeof(struct kvm_lapic_state)))
  1486. goto out;
  1487. r = kvm_vcpu_ioctl_set_lapic(vcpu, lapic);
  1488. if (r)
  1489. goto out;
  1490. r = 0;
  1491. break;
  1492. }
  1493. case KVM_INTERRUPT: {
  1494. struct kvm_interrupt irq;
  1495. r = -EFAULT;
  1496. if (copy_from_user(&irq, argp, sizeof irq))
  1497. goto out;
  1498. r = kvm_vcpu_ioctl_interrupt(vcpu, &irq);
  1499. if (r)
  1500. goto out;
  1501. r = 0;
  1502. break;
  1503. }
  1504. case KVM_NMI: {
  1505. r = kvm_vcpu_ioctl_nmi(vcpu);
  1506. if (r)
  1507. goto out;
  1508. r = 0;
  1509. break;
  1510. }
  1511. case KVM_SET_CPUID: {
  1512. struct kvm_cpuid __user *cpuid_arg = argp;
  1513. struct kvm_cpuid cpuid;
  1514. r = -EFAULT;
  1515. if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
  1516. goto out;
  1517. r = kvm_vcpu_ioctl_set_cpuid(vcpu, &cpuid, cpuid_arg->entries);
  1518. if (r)
  1519. goto out;
  1520. break;
  1521. }
  1522. case KVM_SET_CPUID2: {
  1523. struct kvm_cpuid2 __user *cpuid_arg = argp;
  1524. struct kvm_cpuid2 cpuid;
  1525. r = -EFAULT;
  1526. if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
  1527. goto out;
  1528. r = kvm_vcpu_ioctl_set_cpuid2(vcpu, &cpuid,
  1529. cpuid_arg->entries);
  1530. if (r)
  1531. goto out;
  1532. break;
  1533. }
  1534. case KVM_GET_CPUID2: {
  1535. struct kvm_cpuid2 __user *cpuid_arg = argp;
  1536. struct kvm_cpuid2 cpuid;
  1537. r = -EFAULT;
  1538. if (copy_from_user(&cpuid, cpuid_arg, sizeof cpuid))
  1539. goto out;
  1540. r = kvm_vcpu_ioctl_get_cpuid2(vcpu, &cpuid,
  1541. cpuid_arg->entries);
  1542. if (r)
  1543. goto out;
  1544. r = -EFAULT;
  1545. if (copy_to_user(cpuid_arg, &cpuid, sizeof cpuid))
  1546. goto out;
  1547. r = 0;
  1548. break;
  1549. }
  1550. case KVM_GET_MSRS:
  1551. r = msr_io(vcpu, argp, kvm_get_msr, 1);
  1552. break;
  1553. case KVM_SET_MSRS:
  1554. r = msr_io(vcpu, argp, do_set_msr, 0);
  1555. break;
  1556. case KVM_TPR_ACCESS_REPORTING: {
  1557. struct kvm_tpr_access_ctl tac;
  1558. r = -EFAULT;
  1559. if (copy_from_user(&tac, argp, sizeof tac))
  1560. goto out;
  1561. r = vcpu_ioctl_tpr_access_reporting(vcpu, &tac);
  1562. if (r)
  1563. goto out;
  1564. r = -EFAULT;
  1565. if (copy_to_user(argp, &tac, sizeof tac))
  1566. goto out;
  1567. r = 0;
  1568. break;
  1569. };
  1570. case KVM_SET_VAPIC_ADDR: {
  1571. struct kvm_vapic_addr va;
  1572. r = -EINVAL;
  1573. if (!irqchip_in_kernel(vcpu->kvm))
  1574. goto out;
  1575. r = -EFAULT;
  1576. if (copy_from_user(&va, argp, sizeof va))
  1577. goto out;
  1578. r = 0;
  1579. kvm_lapic_set_vapic_addr(vcpu, va.vapic_addr);
  1580. break;
  1581. }
  1582. case KVM_X86_SETUP_MCE: {
  1583. u64 mcg_cap;
  1584. r = -EFAULT;
  1585. if (copy_from_user(&mcg_cap, argp, sizeof mcg_cap))
  1586. goto out;
  1587. r = kvm_vcpu_ioctl_x86_setup_mce(vcpu, mcg_cap);
  1588. break;
  1589. }
  1590. case KVM_X86_SET_MCE: {
  1591. struct kvm_x86_mce mce;
  1592. r = -EFAULT;
  1593. if (copy_from_user(&mce, argp, sizeof mce))
  1594. goto out;
  1595. r = kvm_vcpu_ioctl_x86_set_mce(vcpu, &mce);
  1596. break;
  1597. }
  1598. default:
  1599. r = -EINVAL;
  1600. }
  1601. out:
  1602. kfree(lapic);
  1603. return r;
  1604. }
  1605. static int kvm_vm_ioctl_set_tss_addr(struct kvm *kvm, unsigned long addr)
  1606. {
  1607. int ret;
  1608. if (addr > (unsigned int)(-3 * PAGE_SIZE))
  1609. return -1;
  1610. ret = kvm_x86_ops->set_tss_addr(kvm, addr);
  1611. return ret;
  1612. }
  1613. static int kvm_vm_ioctl_set_nr_mmu_pages(struct kvm *kvm,
  1614. u32 kvm_nr_mmu_pages)
  1615. {
  1616. if (kvm_nr_mmu_pages < KVM_MIN_ALLOC_MMU_PAGES)
  1617. return -EINVAL;
  1618. down_write(&kvm->slots_lock);
  1619. spin_lock(&kvm->mmu_lock);
  1620. kvm_mmu_change_mmu_pages(kvm, kvm_nr_mmu_pages);
  1621. kvm->arch.n_requested_mmu_pages = kvm_nr_mmu_pages;
  1622. spin_unlock(&kvm->mmu_lock);
  1623. up_write(&kvm->slots_lock);
  1624. return 0;
  1625. }
  1626. static int kvm_vm_ioctl_get_nr_mmu_pages(struct kvm *kvm)
  1627. {
  1628. return kvm->arch.n_alloc_mmu_pages;
  1629. }
  1630. gfn_t unalias_gfn(struct kvm *kvm, gfn_t gfn)
  1631. {
  1632. int i;
  1633. struct kvm_mem_alias *alias;
  1634. for (i = 0; i < kvm->arch.naliases; ++i) {
  1635. alias = &kvm->arch.aliases[i];
  1636. if (gfn >= alias->base_gfn
  1637. && gfn < alias->base_gfn + alias->npages)
  1638. return alias->target_gfn + gfn - alias->base_gfn;
  1639. }
  1640. return gfn;
  1641. }
  1642. /*
  1643. * Set a new alias region. Aliases map a portion of physical memory into
  1644. * another portion. This is useful for memory windows, for example the PC
  1645. * VGA region.
  1646. */
  1647. static int kvm_vm_ioctl_set_memory_alias(struct kvm *kvm,
  1648. struct kvm_memory_alias *alias)
  1649. {
  1650. int r, n;
  1651. struct kvm_mem_alias *p;
  1652. r = -EINVAL;
  1653. /* General sanity checks */
  1654. if (alias->memory_size & (PAGE_SIZE - 1))
  1655. goto out;
  1656. if (alias->guest_phys_addr & (PAGE_SIZE - 1))
  1657. goto out;
  1658. if (alias->slot >= KVM_ALIAS_SLOTS)
  1659. goto out;
  1660. if (alias->guest_phys_addr + alias->memory_size
  1661. < alias->guest_phys_addr)
  1662. goto out;
  1663. if (alias->target_phys_addr + alias->memory_size
  1664. < alias->target_phys_addr)
  1665. goto out;
  1666. down_write(&kvm->slots_lock);
  1667. spin_lock(&kvm->mmu_lock);
  1668. p = &kvm->arch.aliases[alias->slot];
  1669. p->base_gfn = alias->guest_phys_addr >> PAGE_SHIFT;
  1670. p->npages = alias->memory_size >> PAGE_SHIFT;
  1671. p->target_gfn = alias->target_phys_addr >> PAGE_SHIFT;
  1672. for (n = KVM_ALIAS_SLOTS; n > 0; --n)
  1673. if (kvm->arch.aliases[n - 1].npages)
  1674. break;
  1675. kvm->arch.naliases = n;
  1676. spin_unlock(&kvm->mmu_lock);
  1677. kvm_mmu_zap_all(kvm);
  1678. up_write(&kvm->slots_lock);
  1679. return 0;
  1680. out:
  1681. return r;
  1682. }
  1683. static int kvm_vm_ioctl_get_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
  1684. {
  1685. int r;
  1686. r = 0;
  1687. switch (chip->chip_id) {
  1688. case KVM_IRQCHIP_PIC_MASTER:
  1689. memcpy(&chip->chip.pic,
  1690. &pic_irqchip(kvm)->pics[0],
  1691. sizeof(struct kvm_pic_state));
  1692. break;
  1693. case KVM_IRQCHIP_PIC_SLAVE:
  1694. memcpy(&chip->chip.pic,
  1695. &pic_irqchip(kvm)->pics[1],
  1696. sizeof(struct kvm_pic_state));
  1697. break;
  1698. case KVM_IRQCHIP_IOAPIC:
  1699. memcpy(&chip->chip.ioapic,
  1700. ioapic_irqchip(kvm),
  1701. sizeof(struct kvm_ioapic_state));
  1702. break;
  1703. default:
  1704. r = -EINVAL;
  1705. break;
  1706. }
  1707. return r;
  1708. }
  1709. static int kvm_vm_ioctl_set_irqchip(struct kvm *kvm, struct kvm_irqchip *chip)
  1710. {
  1711. int r;
  1712. r = 0;
  1713. switch (chip->chip_id) {
  1714. case KVM_IRQCHIP_PIC_MASTER:
  1715. memcpy(&pic_irqchip(kvm)->pics[0],
  1716. &chip->chip.pic,
  1717. sizeof(struct kvm_pic_state));
  1718. break;
  1719. case KVM_IRQCHIP_PIC_SLAVE:
  1720. memcpy(&pic_irqchip(kvm)->pics[1],
  1721. &chip->chip.pic,
  1722. sizeof(struct kvm_pic_state));
  1723. break;
  1724. case KVM_IRQCHIP_IOAPIC:
  1725. memcpy(ioapic_irqchip(kvm),
  1726. &chip->chip.ioapic,
  1727. sizeof(struct kvm_ioapic_state));
  1728. break;
  1729. default:
  1730. r = -EINVAL;
  1731. break;
  1732. }
  1733. kvm_pic_update_irq(pic_irqchip(kvm));
  1734. return r;
  1735. }
  1736. static int kvm_vm_ioctl_get_pit(struct kvm *kvm, struct kvm_pit_state *ps)
  1737. {
  1738. int r = 0;
  1739. memcpy(ps, &kvm->arch.vpit->pit_state, sizeof(struct kvm_pit_state));
  1740. return r;
  1741. }
  1742. static int kvm_vm_ioctl_set_pit(struct kvm *kvm, struct kvm_pit_state *ps)
  1743. {
  1744. int r = 0;
  1745. memcpy(&kvm->arch.vpit->pit_state, ps, sizeof(struct kvm_pit_state));
  1746. kvm_pit_load_count(kvm, 0, ps->channels[0].count);
  1747. return r;
  1748. }
  1749. static int kvm_vm_ioctl_reinject(struct kvm *kvm,
  1750. struct kvm_reinject_control *control)
  1751. {
  1752. if (!kvm->arch.vpit)
  1753. return -ENXIO;
  1754. kvm->arch.vpit->pit_state.pit_timer.reinject = control->pit_reinject;
  1755. return 0;
  1756. }
  1757. /*
  1758. * Get (and clear) the dirty memory log for a memory slot.
  1759. */
  1760. int kvm_vm_ioctl_get_dirty_log(struct kvm *kvm,
  1761. struct kvm_dirty_log *log)
  1762. {
  1763. int r;
  1764. int n;
  1765. struct kvm_memory_slot *memslot;
  1766. int is_dirty = 0;
  1767. down_write(&kvm->slots_lock);
  1768. r = kvm_get_dirty_log(kvm, log, &is_dirty);
  1769. if (r)
  1770. goto out;
  1771. /* If nothing is dirty, don't bother messing with page tables. */
  1772. if (is_dirty) {
  1773. spin_lock(&kvm->mmu_lock);
  1774. kvm_mmu_slot_remove_write_access(kvm, log->slot);
  1775. spin_unlock(&kvm->mmu_lock);
  1776. kvm_flush_remote_tlbs(kvm);
  1777. memslot = &kvm->memslots[log->slot];
  1778. n = ALIGN(memslot->npages, BITS_PER_LONG) / 8;
  1779. memset(memslot->dirty_bitmap, 0, n);
  1780. }
  1781. r = 0;
  1782. out:
  1783. up_write(&kvm->slots_lock);
  1784. return r;
  1785. }
  1786. long kvm_arch_vm_ioctl(struct file *filp,
  1787. unsigned int ioctl, unsigned long arg)
  1788. {
  1789. struct kvm *kvm = filp->private_data;
  1790. void __user *argp = (void __user *)arg;
  1791. int r = -EINVAL;
  1792. /*
  1793. * This union makes it completely explicit to gcc-3.x
  1794. * that these two variables' stack usage should be
  1795. * combined, not added together.
  1796. */
  1797. union {
  1798. struct kvm_pit_state ps;
  1799. struct kvm_memory_alias alias;
  1800. } u;
  1801. switch (ioctl) {
  1802. case KVM_SET_TSS_ADDR:
  1803. r = kvm_vm_ioctl_set_tss_addr(kvm, arg);
  1804. if (r < 0)
  1805. goto out;
  1806. break;
  1807. case KVM_SET_MEMORY_REGION: {
  1808. struct kvm_memory_region kvm_mem;
  1809. struct kvm_userspace_memory_region kvm_userspace_mem;
  1810. r = -EFAULT;
  1811. if (copy_from_user(&kvm_mem, argp, sizeof kvm_mem))
  1812. goto out;
  1813. kvm_userspace_mem.slot = kvm_mem.slot;
  1814. kvm_userspace_mem.flags = kvm_mem.flags;
  1815. kvm_userspace_mem.guest_phys_addr = kvm_mem.guest_phys_addr;
  1816. kvm_userspace_mem.memory_size = kvm_mem.memory_size;
  1817. r = kvm_vm_ioctl_set_memory_region(kvm, &kvm_userspace_mem, 0);
  1818. if (r)
  1819. goto out;
  1820. break;
  1821. }
  1822. case KVM_SET_NR_MMU_PAGES:
  1823. r = kvm_vm_ioctl_set_nr_mmu_pages(kvm, arg);
  1824. if (r)
  1825. goto out;
  1826. break;
  1827. case KVM_GET_NR_MMU_PAGES:
  1828. r = kvm_vm_ioctl_get_nr_mmu_pages(kvm);
  1829. break;
  1830. case KVM_SET_MEMORY_ALIAS:
  1831. r = -EFAULT;
  1832. if (copy_from_user(&u.alias, argp, sizeof(struct kvm_memory_alias)))
  1833. goto out;
  1834. r = kvm_vm_ioctl_set_memory_alias(kvm, &u.alias);
  1835. if (r)
  1836. goto out;
  1837. break;
  1838. case KVM_CREATE_IRQCHIP:
  1839. r = -ENOMEM;
  1840. kvm->arch.vpic = kvm_create_pic(kvm);
  1841. if (kvm->arch.vpic) {
  1842. r = kvm_ioapic_init(kvm);
  1843. if (r) {
  1844. kfree(kvm->arch.vpic);
  1845. kvm->arch.vpic = NULL;
  1846. goto out;
  1847. }
  1848. } else
  1849. goto out;
  1850. r = kvm_setup_default_irq_routing(kvm);
  1851. if (r) {
  1852. kfree(kvm->arch.vpic);
  1853. kfree(kvm->arch.vioapic);
  1854. goto out;
  1855. }
  1856. break;
  1857. case KVM_CREATE_PIT:
  1858. mutex_lock(&kvm->lock);
  1859. r = -EEXIST;
  1860. if (kvm->arch.vpit)
  1861. goto create_pit_unlock;
  1862. r = -ENOMEM;
  1863. kvm->arch.vpit = kvm_create_pit(kvm);
  1864. if (kvm->arch.vpit)
  1865. r = 0;
  1866. create_pit_unlock:
  1867. mutex_unlock(&kvm->lock);
  1868. break;
  1869. case KVM_IRQ_LINE_STATUS:
  1870. case KVM_IRQ_LINE: {
  1871. struct kvm_irq_level irq_event;
  1872. r = -EFAULT;
  1873. if (copy_from_user(&irq_event, argp, sizeof irq_event))
  1874. goto out;
  1875. if (irqchip_in_kernel(kvm)) {
  1876. __s32 status;
  1877. mutex_lock(&kvm->lock);
  1878. status = kvm_set_irq(kvm, KVM_USERSPACE_IRQ_SOURCE_ID,
  1879. irq_event.irq, irq_event.level);
  1880. mutex_unlock(&kvm->lock);
  1881. if (ioctl == KVM_IRQ_LINE_STATUS) {
  1882. irq_event.status = status;
  1883. if (copy_to_user(argp, &irq_event,
  1884. sizeof irq_event))
  1885. goto out;
  1886. }
  1887. r = 0;
  1888. }
  1889. break;
  1890. }
  1891. case KVM_GET_IRQCHIP: {
  1892. /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
  1893. struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
  1894. r = -ENOMEM;
  1895. if (!chip)
  1896. goto out;
  1897. r = -EFAULT;
  1898. if (copy_from_user(chip, argp, sizeof *chip))
  1899. goto get_irqchip_out;
  1900. r = -ENXIO;
  1901. if (!irqchip_in_kernel(kvm))
  1902. goto get_irqchip_out;
  1903. r = kvm_vm_ioctl_get_irqchip(kvm, chip);
  1904. if (r)
  1905. goto get_irqchip_out;
  1906. r = -EFAULT;
  1907. if (copy_to_user(argp, chip, sizeof *chip))
  1908. goto get_irqchip_out;
  1909. r = 0;
  1910. get_irqchip_out:
  1911. kfree(chip);
  1912. if (r)
  1913. goto out;
  1914. break;
  1915. }
  1916. case KVM_SET_IRQCHIP: {
  1917. /* 0: PIC master, 1: PIC slave, 2: IOAPIC */
  1918. struct kvm_irqchip *chip = kmalloc(sizeof(*chip), GFP_KERNEL);
  1919. r = -ENOMEM;
  1920. if (!chip)
  1921. goto out;
  1922. r = -EFAULT;
  1923. if (copy_from_user(chip, argp, sizeof *chip))
  1924. goto set_irqchip_out;
  1925. r = -ENXIO;
  1926. if (!irqchip_in_kernel(kvm))
  1927. goto set_irqchip_out;
  1928. r = kvm_vm_ioctl_set_irqchip(kvm, chip);
  1929. if (r)
  1930. goto set_irqchip_out;
  1931. r = 0;
  1932. set_irqchip_out:
  1933. kfree(chip);
  1934. if (r)
  1935. goto out;
  1936. break;
  1937. }
  1938. case KVM_GET_PIT: {
  1939. r = -EFAULT;
  1940. if (copy_from_user(&u.ps, argp, sizeof(struct kvm_pit_state)))
  1941. goto out;
  1942. r = -ENXIO;
  1943. if (!kvm->arch.vpit)
  1944. goto out;
  1945. r = kvm_vm_ioctl_get_pit(kvm, &u.ps);
  1946. if (r)
  1947. goto out;
  1948. r = -EFAULT;
  1949. if (copy_to_user(argp, &u.ps, sizeof(struct kvm_pit_state)))
  1950. goto out;
  1951. r = 0;
  1952. break;
  1953. }
  1954. case KVM_SET_PIT: {
  1955. r = -EFAULT;
  1956. if (copy_from_user(&u.ps, argp, sizeof u.ps))
  1957. goto out;
  1958. r = -ENXIO;
  1959. if (!kvm->arch.vpit)
  1960. goto out;
  1961. r = kvm_vm_ioctl_set_pit(kvm, &u.ps);
  1962. if (r)
  1963. goto out;
  1964. r = 0;
  1965. break;
  1966. }
  1967. case KVM_REINJECT_CONTROL: {
  1968. struct kvm_reinject_control control;
  1969. r = -EFAULT;
  1970. if (copy_from_user(&control, argp, sizeof(control)))
  1971. goto out;
  1972. r = kvm_vm_ioctl_reinject(kvm, &control);
  1973. if (r)
  1974. goto out;
  1975. r = 0;
  1976. break;
  1977. }
  1978. default:
  1979. ;
  1980. }
  1981. out:
  1982. return r;
  1983. }
  1984. static void kvm_init_msr_list(void)
  1985. {
  1986. u32 dummy[2];
  1987. unsigned i, j;
  1988. for (i = j = 0; i < ARRAY_SIZE(msrs_to_save); i++) {
  1989. if (rdmsr_safe(msrs_to_save[i], &dummy[0], &dummy[1]) < 0)
  1990. continue;
  1991. if (j < i)
  1992. msrs_to_save[j] = msrs_to_save[i];
  1993. j++;
  1994. }
  1995. num_msrs_to_save = j;
  1996. }
  1997. /*
  1998. * Only apic need an MMIO device hook, so shortcut now..
  1999. */
  2000. static struct kvm_io_device *vcpu_find_pervcpu_dev(struct kvm_vcpu *vcpu,
  2001. gpa_t addr, int len,
  2002. int is_write)
  2003. {
  2004. struct kvm_io_device *dev;
  2005. if (vcpu->arch.apic) {
  2006. dev = &vcpu->arch.apic->dev;
  2007. if (dev->in_range(dev, addr, len, is_write))
  2008. return dev;
  2009. }
  2010. return NULL;
  2011. }
  2012. static struct kvm_io_device *vcpu_find_mmio_dev(struct kvm_vcpu *vcpu,
  2013. gpa_t addr, int len,
  2014. int is_write)
  2015. {
  2016. struct kvm_io_device *dev;
  2017. dev = vcpu_find_pervcpu_dev(vcpu, addr, len, is_write);
  2018. if (dev == NULL)
  2019. dev = kvm_io_bus_find_dev(&vcpu->kvm->mmio_bus, addr, len,
  2020. is_write);
  2021. return dev;
  2022. }
  2023. static int kvm_read_guest_virt(gva_t addr, void *val, unsigned int bytes,
  2024. struct kvm_vcpu *vcpu)
  2025. {
  2026. void *data = val;
  2027. int r = X86EMUL_CONTINUE;
  2028. while (bytes) {
  2029. gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
  2030. unsigned offset = addr & (PAGE_SIZE-1);
  2031. unsigned toread = min(bytes, (unsigned)PAGE_SIZE - offset);
  2032. int ret;
  2033. if (gpa == UNMAPPED_GVA) {
  2034. r = X86EMUL_PROPAGATE_FAULT;
  2035. goto out;
  2036. }
  2037. ret = kvm_read_guest(vcpu->kvm, gpa, data, toread);
  2038. if (ret < 0) {
  2039. r = X86EMUL_UNHANDLEABLE;
  2040. goto out;
  2041. }
  2042. bytes -= toread;
  2043. data += toread;
  2044. addr += toread;
  2045. }
  2046. out:
  2047. return r;
  2048. }
  2049. static int kvm_write_guest_virt(gva_t addr, void *val, unsigned int bytes,
  2050. struct kvm_vcpu *vcpu)
  2051. {
  2052. void *data = val;
  2053. int r = X86EMUL_CONTINUE;
  2054. while (bytes) {
  2055. gpa_t gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
  2056. unsigned offset = addr & (PAGE_SIZE-1);
  2057. unsigned towrite = min(bytes, (unsigned)PAGE_SIZE - offset);
  2058. int ret;
  2059. if (gpa == UNMAPPED_GVA) {
  2060. r = X86EMUL_PROPAGATE_FAULT;
  2061. goto out;
  2062. }
  2063. ret = kvm_write_guest(vcpu->kvm, gpa, data, towrite);
  2064. if (ret < 0) {
  2065. r = X86EMUL_UNHANDLEABLE;
  2066. goto out;
  2067. }
  2068. bytes -= towrite;
  2069. data += towrite;
  2070. addr += towrite;
  2071. }
  2072. out:
  2073. return r;
  2074. }
  2075. static int emulator_read_emulated(unsigned long addr,
  2076. void *val,
  2077. unsigned int bytes,
  2078. struct kvm_vcpu *vcpu)
  2079. {
  2080. struct kvm_io_device *mmio_dev;
  2081. gpa_t gpa;
  2082. if (vcpu->mmio_read_completed) {
  2083. memcpy(val, vcpu->mmio_data, bytes);
  2084. vcpu->mmio_read_completed = 0;
  2085. return X86EMUL_CONTINUE;
  2086. }
  2087. gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
  2088. /* For APIC access vmexit */
  2089. if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
  2090. goto mmio;
  2091. if (kvm_read_guest_virt(addr, val, bytes, vcpu)
  2092. == X86EMUL_CONTINUE)
  2093. return X86EMUL_CONTINUE;
  2094. if (gpa == UNMAPPED_GVA)
  2095. return X86EMUL_PROPAGATE_FAULT;
  2096. mmio:
  2097. /*
  2098. * Is this MMIO handled locally?
  2099. */
  2100. mutex_lock(&vcpu->kvm->lock);
  2101. mmio_dev = vcpu_find_mmio_dev(vcpu, gpa, bytes, 0);
  2102. if (mmio_dev) {
  2103. kvm_iodevice_read(mmio_dev, gpa, bytes, val);
  2104. mutex_unlock(&vcpu->kvm->lock);
  2105. return X86EMUL_CONTINUE;
  2106. }
  2107. mutex_unlock(&vcpu->kvm->lock);
  2108. vcpu->mmio_needed = 1;
  2109. vcpu->mmio_phys_addr = gpa;
  2110. vcpu->mmio_size = bytes;
  2111. vcpu->mmio_is_write = 0;
  2112. return X86EMUL_UNHANDLEABLE;
  2113. }
  2114. int emulator_write_phys(struct kvm_vcpu *vcpu, gpa_t gpa,
  2115. const void *val, int bytes)
  2116. {
  2117. int ret;
  2118. ret = kvm_write_guest(vcpu->kvm, gpa, val, bytes);
  2119. if (ret < 0)
  2120. return 0;
  2121. kvm_mmu_pte_write(vcpu, gpa, val, bytes, 1);
  2122. return 1;
  2123. }
  2124. static int emulator_write_emulated_onepage(unsigned long addr,
  2125. const void *val,
  2126. unsigned int bytes,
  2127. struct kvm_vcpu *vcpu)
  2128. {
  2129. struct kvm_io_device *mmio_dev;
  2130. gpa_t gpa;
  2131. gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
  2132. if (gpa == UNMAPPED_GVA) {
  2133. kvm_inject_page_fault(vcpu, addr, 2);
  2134. return X86EMUL_PROPAGATE_FAULT;
  2135. }
  2136. /* For APIC access vmexit */
  2137. if ((gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
  2138. goto mmio;
  2139. if (emulator_write_phys(vcpu, gpa, val, bytes))
  2140. return X86EMUL_CONTINUE;
  2141. mmio:
  2142. /*
  2143. * Is this MMIO handled locally?
  2144. */
  2145. mutex_lock(&vcpu->kvm->lock);
  2146. mmio_dev = vcpu_find_mmio_dev(vcpu, gpa, bytes, 1);
  2147. if (mmio_dev) {
  2148. kvm_iodevice_write(mmio_dev, gpa, bytes, val);
  2149. mutex_unlock(&vcpu->kvm->lock);
  2150. return X86EMUL_CONTINUE;
  2151. }
  2152. mutex_unlock(&vcpu->kvm->lock);
  2153. vcpu->mmio_needed = 1;
  2154. vcpu->mmio_phys_addr = gpa;
  2155. vcpu->mmio_size = bytes;
  2156. vcpu->mmio_is_write = 1;
  2157. memcpy(vcpu->mmio_data, val, bytes);
  2158. return X86EMUL_CONTINUE;
  2159. }
  2160. int emulator_write_emulated(unsigned long addr,
  2161. const void *val,
  2162. unsigned int bytes,
  2163. struct kvm_vcpu *vcpu)
  2164. {
  2165. /* Crossing a page boundary? */
  2166. if (((addr + bytes - 1) ^ addr) & PAGE_MASK) {
  2167. int rc, now;
  2168. now = -addr & ~PAGE_MASK;
  2169. rc = emulator_write_emulated_onepage(addr, val, now, vcpu);
  2170. if (rc != X86EMUL_CONTINUE)
  2171. return rc;
  2172. addr += now;
  2173. val += now;
  2174. bytes -= now;
  2175. }
  2176. return emulator_write_emulated_onepage(addr, val, bytes, vcpu);
  2177. }
  2178. EXPORT_SYMBOL_GPL(emulator_write_emulated);
  2179. static int emulator_cmpxchg_emulated(unsigned long addr,
  2180. const void *old,
  2181. const void *new,
  2182. unsigned int bytes,
  2183. struct kvm_vcpu *vcpu)
  2184. {
  2185. static int reported;
  2186. if (!reported) {
  2187. reported = 1;
  2188. printk(KERN_WARNING "kvm: emulating exchange as write\n");
  2189. }
  2190. #ifndef CONFIG_X86_64
  2191. /* guests cmpxchg8b have to be emulated atomically */
  2192. if (bytes == 8) {
  2193. gpa_t gpa;
  2194. struct page *page;
  2195. char *kaddr;
  2196. u64 val;
  2197. gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, addr);
  2198. if (gpa == UNMAPPED_GVA ||
  2199. (gpa & PAGE_MASK) == APIC_DEFAULT_PHYS_BASE)
  2200. goto emul_write;
  2201. if (((gpa + bytes - 1) & PAGE_MASK) != (gpa & PAGE_MASK))
  2202. goto emul_write;
  2203. val = *(u64 *)new;
  2204. page = gfn_to_page(vcpu->kvm, gpa >> PAGE_SHIFT);
  2205. kaddr = kmap_atomic(page, KM_USER0);
  2206. set_64bit((u64 *)(kaddr + offset_in_page(gpa)), val);
  2207. kunmap_atomic(kaddr, KM_USER0);
  2208. kvm_release_page_dirty(page);
  2209. }
  2210. emul_write:
  2211. #endif
  2212. return emulator_write_emulated(addr, new, bytes, vcpu);
  2213. }
  2214. static unsigned long get_segment_base(struct kvm_vcpu *vcpu, int seg)
  2215. {
  2216. return kvm_x86_ops->get_segment_base(vcpu, seg);
  2217. }
  2218. int emulate_invlpg(struct kvm_vcpu *vcpu, gva_t address)
  2219. {
  2220. kvm_mmu_invlpg(vcpu, address);
  2221. return X86EMUL_CONTINUE;
  2222. }
  2223. int emulate_clts(struct kvm_vcpu *vcpu)
  2224. {
  2225. KVMTRACE_0D(CLTS, vcpu, handler);
  2226. kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 & ~X86_CR0_TS);
  2227. return X86EMUL_CONTINUE;
  2228. }
  2229. int emulator_get_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long *dest)
  2230. {
  2231. struct kvm_vcpu *vcpu = ctxt->vcpu;
  2232. switch (dr) {
  2233. case 0 ... 3:
  2234. *dest = kvm_x86_ops->get_dr(vcpu, dr);
  2235. return X86EMUL_CONTINUE;
  2236. default:
  2237. pr_unimpl(vcpu, "%s: unexpected dr %u\n", __func__, dr);
  2238. return X86EMUL_UNHANDLEABLE;
  2239. }
  2240. }
  2241. int emulator_set_dr(struct x86_emulate_ctxt *ctxt, int dr, unsigned long value)
  2242. {
  2243. unsigned long mask = (ctxt->mode == X86EMUL_MODE_PROT64) ? ~0ULL : ~0U;
  2244. int exception;
  2245. kvm_x86_ops->set_dr(ctxt->vcpu, dr, value & mask, &exception);
  2246. if (exception) {
  2247. /* FIXME: better handling */
  2248. return X86EMUL_UNHANDLEABLE;
  2249. }
  2250. return X86EMUL_CONTINUE;
  2251. }
  2252. void kvm_report_emulation_failure(struct kvm_vcpu *vcpu, const char *context)
  2253. {
  2254. u8 opcodes[4];
  2255. unsigned long rip = kvm_rip_read(vcpu);
  2256. unsigned long rip_linear;
  2257. if (!printk_ratelimit())
  2258. return;
  2259. rip_linear = rip + get_segment_base(vcpu, VCPU_SREG_CS);
  2260. kvm_read_guest_virt(rip_linear, (void *)opcodes, 4, vcpu);
  2261. printk(KERN_ERR "emulation failed (%s) rip %lx %02x %02x %02x %02x\n",
  2262. context, rip, opcodes[0], opcodes[1], opcodes[2], opcodes[3]);
  2263. }
  2264. EXPORT_SYMBOL_GPL(kvm_report_emulation_failure);
  2265. static struct x86_emulate_ops emulate_ops = {
  2266. .read_std = kvm_read_guest_virt,
  2267. .read_emulated = emulator_read_emulated,
  2268. .write_emulated = emulator_write_emulated,
  2269. .cmpxchg_emulated = emulator_cmpxchg_emulated,
  2270. };
  2271. static void cache_all_regs(struct kvm_vcpu *vcpu)
  2272. {
  2273. kvm_register_read(vcpu, VCPU_REGS_RAX);
  2274. kvm_register_read(vcpu, VCPU_REGS_RSP);
  2275. kvm_register_read(vcpu, VCPU_REGS_RIP);
  2276. vcpu->arch.regs_dirty = ~0;
  2277. }
  2278. int emulate_instruction(struct kvm_vcpu *vcpu,
  2279. struct kvm_run *run,
  2280. unsigned long cr2,
  2281. u16 error_code,
  2282. int emulation_type)
  2283. {
  2284. int r, shadow_mask;
  2285. struct decode_cache *c;
  2286. kvm_clear_exception_queue(vcpu);
  2287. vcpu->arch.mmio_fault_cr2 = cr2;
  2288. /*
  2289. * TODO: fix x86_emulate.c to use guest_read/write_register
  2290. * instead of direct ->regs accesses, can save hundred cycles
  2291. * on Intel for instructions that don't read/change RSP, for
  2292. * for example.
  2293. */
  2294. cache_all_regs(vcpu);
  2295. vcpu->mmio_is_write = 0;
  2296. vcpu->arch.pio.string = 0;
  2297. if (!(emulation_type & EMULTYPE_NO_DECODE)) {
  2298. int cs_db, cs_l;
  2299. kvm_x86_ops->get_cs_db_l_bits(vcpu, &cs_db, &cs_l);
  2300. vcpu->arch.emulate_ctxt.vcpu = vcpu;
  2301. vcpu->arch.emulate_ctxt.eflags = kvm_x86_ops->get_rflags(vcpu);
  2302. vcpu->arch.emulate_ctxt.mode =
  2303. (vcpu->arch.emulate_ctxt.eflags & X86_EFLAGS_VM)
  2304. ? X86EMUL_MODE_REAL : cs_l
  2305. ? X86EMUL_MODE_PROT64 : cs_db
  2306. ? X86EMUL_MODE_PROT32 : X86EMUL_MODE_PROT16;
  2307. r = x86_decode_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
  2308. /* Reject the instructions other than VMCALL/VMMCALL when
  2309. * try to emulate invalid opcode */
  2310. c = &vcpu->arch.emulate_ctxt.decode;
  2311. if ((emulation_type & EMULTYPE_TRAP_UD) &&
  2312. (!(c->twobyte && c->b == 0x01 &&
  2313. (c->modrm_reg == 0 || c->modrm_reg == 3) &&
  2314. c->modrm_mod == 3 && c->modrm_rm == 1)))
  2315. return EMULATE_FAIL;
  2316. ++vcpu->stat.insn_emulation;
  2317. if (r) {
  2318. ++vcpu->stat.insn_emulation_fail;
  2319. if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
  2320. return EMULATE_DONE;
  2321. return EMULATE_FAIL;
  2322. }
  2323. }
  2324. if (emulation_type & EMULTYPE_SKIP) {
  2325. kvm_rip_write(vcpu, vcpu->arch.emulate_ctxt.decode.eip);
  2326. return EMULATE_DONE;
  2327. }
  2328. r = x86_emulate_insn(&vcpu->arch.emulate_ctxt, &emulate_ops);
  2329. shadow_mask = vcpu->arch.emulate_ctxt.interruptibility;
  2330. if (r == 0)
  2331. kvm_x86_ops->set_interrupt_shadow(vcpu, shadow_mask);
  2332. if (vcpu->arch.pio.string)
  2333. return EMULATE_DO_MMIO;
  2334. if ((r || vcpu->mmio_is_write) && run) {
  2335. run->exit_reason = KVM_EXIT_MMIO;
  2336. run->mmio.phys_addr = vcpu->mmio_phys_addr;
  2337. memcpy(run->mmio.data, vcpu->mmio_data, 8);
  2338. run->mmio.len = vcpu->mmio_size;
  2339. run->mmio.is_write = vcpu->mmio_is_write;
  2340. }
  2341. if (r) {
  2342. if (kvm_mmu_unprotect_page_virt(vcpu, cr2))
  2343. return EMULATE_DONE;
  2344. if (!vcpu->mmio_needed) {
  2345. kvm_report_emulation_failure(vcpu, "mmio");
  2346. return EMULATE_FAIL;
  2347. }
  2348. return EMULATE_DO_MMIO;
  2349. }
  2350. kvm_x86_ops->set_rflags(vcpu, vcpu->arch.emulate_ctxt.eflags);
  2351. if (vcpu->mmio_is_write) {
  2352. vcpu->mmio_needed = 0;
  2353. return EMULATE_DO_MMIO;
  2354. }
  2355. return EMULATE_DONE;
  2356. }
  2357. EXPORT_SYMBOL_GPL(emulate_instruction);
  2358. static int pio_copy_data(struct kvm_vcpu *vcpu)
  2359. {
  2360. void *p = vcpu->arch.pio_data;
  2361. gva_t q = vcpu->arch.pio.guest_gva;
  2362. unsigned bytes;
  2363. int ret;
  2364. bytes = vcpu->arch.pio.size * vcpu->arch.pio.cur_count;
  2365. if (vcpu->arch.pio.in)
  2366. ret = kvm_write_guest_virt(q, p, bytes, vcpu);
  2367. else
  2368. ret = kvm_read_guest_virt(q, p, bytes, vcpu);
  2369. return ret;
  2370. }
  2371. int complete_pio(struct kvm_vcpu *vcpu)
  2372. {
  2373. struct kvm_pio_request *io = &vcpu->arch.pio;
  2374. long delta;
  2375. int r;
  2376. unsigned long val;
  2377. if (!io->string) {
  2378. if (io->in) {
  2379. val = kvm_register_read(vcpu, VCPU_REGS_RAX);
  2380. memcpy(&val, vcpu->arch.pio_data, io->size);
  2381. kvm_register_write(vcpu, VCPU_REGS_RAX, val);
  2382. }
  2383. } else {
  2384. if (io->in) {
  2385. r = pio_copy_data(vcpu);
  2386. if (r)
  2387. return r;
  2388. }
  2389. delta = 1;
  2390. if (io->rep) {
  2391. delta *= io->cur_count;
  2392. /*
  2393. * The size of the register should really depend on
  2394. * current address size.
  2395. */
  2396. val = kvm_register_read(vcpu, VCPU_REGS_RCX);
  2397. val -= delta;
  2398. kvm_register_write(vcpu, VCPU_REGS_RCX, val);
  2399. }
  2400. if (io->down)
  2401. delta = -delta;
  2402. delta *= io->size;
  2403. if (io->in) {
  2404. val = kvm_register_read(vcpu, VCPU_REGS_RDI);
  2405. val += delta;
  2406. kvm_register_write(vcpu, VCPU_REGS_RDI, val);
  2407. } else {
  2408. val = kvm_register_read(vcpu, VCPU_REGS_RSI);
  2409. val += delta;
  2410. kvm_register_write(vcpu, VCPU_REGS_RSI, val);
  2411. }
  2412. }
  2413. io->count -= io->cur_count;
  2414. io->cur_count = 0;
  2415. return 0;
  2416. }
  2417. static void kernel_pio(struct kvm_io_device *pio_dev,
  2418. struct kvm_vcpu *vcpu,
  2419. void *pd)
  2420. {
  2421. /* TODO: String I/O for in kernel device */
  2422. mutex_lock(&vcpu->kvm->lock);
  2423. if (vcpu->arch.pio.in)
  2424. kvm_iodevice_read(pio_dev, vcpu->arch.pio.port,
  2425. vcpu->arch.pio.size,
  2426. pd);
  2427. else
  2428. kvm_iodevice_write(pio_dev, vcpu->arch.pio.port,
  2429. vcpu->arch.pio.size,
  2430. pd);
  2431. mutex_unlock(&vcpu->kvm->lock);
  2432. }
  2433. static void pio_string_write(struct kvm_io_device *pio_dev,
  2434. struct kvm_vcpu *vcpu)
  2435. {
  2436. struct kvm_pio_request *io = &vcpu->arch.pio;
  2437. void *pd = vcpu->arch.pio_data;
  2438. int i;
  2439. mutex_lock(&vcpu->kvm->lock);
  2440. for (i = 0; i < io->cur_count; i++) {
  2441. kvm_iodevice_write(pio_dev, io->port,
  2442. io->size,
  2443. pd);
  2444. pd += io->size;
  2445. }
  2446. mutex_unlock(&vcpu->kvm->lock);
  2447. }
  2448. static struct kvm_io_device *vcpu_find_pio_dev(struct kvm_vcpu *vcpu,
  2449. gpa_t addr, int len,
  2450. int is_write)
  2451. {
  2452. return kvm_io_bus_find_dev(&vcpu->kvm->pio_bus, addr, len, is_write);
  2453. }
  2454. int kvm_emulate_pio(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
  2455. int size, unsigned port)
  2456. {
  2457. struct kvm_io_device *pio_dev;
  2458. unsigned long val;
  2459. vcpu->run->exit_reason = KVM_EXIT_IO;
  2460. vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
  2461. vcpu->run->io.size = vcpu->arch.pio.size = size;
  2462. vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
  2463. vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = 1;
  2464. vcpu->run->io.port = vcpu->arch.pio.port = port;
  2465. vcpu->arch.pio.in = in;
  2466. vcpu->arch.pio.string = 0;
  2467. vcpu->arch.pio.down = 0;
  2468. vcpu->arch.pio.rep = 0;
  2469. if (vcpu->run->io.direction == KVM_EXIT_IO_IN)
  2470. KVMTRACE_2D(IO_READ, vcpu, vcpu->run->io.port, (u32)size,
  2471. handler);
  2472. else
  2473. KVMTRACE_2D(IO_WRITE, vcpu, vcpu->run->io.port, (u32)size,
  2474. handler);
  2475. val = kvm_register_read(vcpu, VCPU_REGS_RAX);
  2476. memcpy(vcpu->arch.pio_data, &val, 4);
  2477. pio_dev = vcpu_find_pio_dev(vcpu, port, size, !in);
  2478. if (pio_dev) {
  2479. kernel_pio(pio_dev, vcpu, vcpu->arch.pio_data);
  2480. complete_pio(vcpu);
  2481. return 1;
  2482. }
  2483. return 0;
  2484. }
  2485. EXPORT_SYMBOL_GPL(kvm_emulate_pio);
  2486. int kvm_emulate_pio_string(struct kvm_vcpu *vcpu, struct kvm_run *run, int in,
  2487. int size, unsigned long count, int down,
  2488. gva_t address, int rep, unsigned port)
  2489. {
  2490. unsigned now, in_page;
  2491. int ret = 0;
  2492. struct kvm_io_device *pio_dev;
  2493. vcpu->run->exit_reason = KVM_EXIT_IO;
  2494. vcpu->run->io.direction = in ? KVM_EXIT_IO_IN : KVM_EXIT_IO_OUT;
  2495. vcpu->run->io.size = vcpu->arch.pio.size = size;
  2496. vcpu->run->io.data_offset = KVM_PIO_PAGE_OFFSET * PAGE_SIZE;
  2497. vcpu->run->io.count = vcpu->arch.pio.count = vcpu->arch.pio.cur_count = count;
  2498. vcpu->run->io.port = vcpu->arch.pio.port = port;
  2499. vcpu->arch.pio.in = in;
  2500. vcpu->arch.pio.string = 1;
  2501. vcpu->arch.pio.down = down;
  2502. vcpu->arch.pio.rep = rep;
  2503. if (vcpu->run->io.direction == KVM_EXIT_IO_IN)
  2504. KVMTRACE_2D(IO_READ, vcpu, vcpu->run->io.port, (u32)size,
  2505. handler);
  2506. else
  2507. KVMTRACE_2D(IO_WRITE, vcpu, vcpu->run->io.port, (u32)size,
  2508. handler);
  2509. if (!count) {
  2510. kvm_x86_ops->skip_emulated_instruction(vcpu);
  2511. return 1;
  2512. }
  2513. if (!down)
  2514. in_page = PAGE_SIZE - offset_in_page(address);
  2515. else
  2516. in_page = offset_in_page(address) + size;
  2517. now = min(count, (unsigned long)in_page / size);
  2518. if (!now)
  2519. now = 1;
  2520. if (down) {
  2521. /*
  2522. * String I/O in reverse. Yuck. Kill the guest, fix later.
  2523. */
  2524. pr_unimpl(vcpu, "guest string pio down\n");
  2525. kvm_inject_gp(vcpu, 0);
  2526. return 1;
  2527. }
  2528. vcpu->run->io.count = now;
  2529. vcpu->arch.pio.cur_count = now;
  2530. if (vcpu->arch.pio.cur_count == vcpu->arch.pio.count)
  2531. kvm_x86_ops->skip_emulated_instruction(vcpu);
  2532. vcpu->arch.pio.guest_gva = address;
  2533. pio_dev = vcpu_find_pio_dev(vcpu, port,
  2534. vcpu->arch.pio.cur_count,
  2535. !vcpu->arch.pio.in);
  2536. if (!vcpu->arch.pio.in) {
  2537. /* string PIO write */
  2538. ret = pio_copy_data(vcpu);
  2539. if (ret == X86EMUL_PROPAGATE_FAULT) {
  2540. kvm_inject_gp(vcpu, 0);
  2541. return 1;
  2542. }
  2543. if (ret == 0 && pio_dev) {
  2544. pio_string_write(pio_dev, vcpu);
  2545. complete_pio(vcpu);
  2546. if (vcpu->arch.pio.count == 0)
  2547. ret = 1;
  2548. }
  2549. } else if (pio_dev)
  2550. pr_unimpl(vcpu, "no string pio read support yet, "
  2551. "port %x size %d count %ld\n",
  2552. port, size, count);
  2553. return ret;
  2554. }
  2555. EXPORT_SYMBOL_GPL(kvm_emulate_pio_string);
  2556. static void bounce_off(void *info)
  2557. {
  2558. /* nothing */
  2559. }
  2560. static unsigned int ref_freq;
  2561. static unsigned long tsc_khz_ref;
  2562. static int kvmclock_cpufreq_notifier(struct notifier_block *nb, unsigned long val,
  2563. void *data)
  2564. {
  2565. struct cpufreq_freqs *freq = data;
  2566. struct kvm *kvm;
  2567. struct kvm_vcpu *vcpu;
  2568. int i, send_ipi = 0;
  2569. if (!ref_freq)
  2570. ref_freq = freq->old;
  2571. if (val == CPUFREQ_PRECHANGE && freq->old > freq->new)
  2572. return 0;
  2573. if (val == CPUFREQ_POSTCHANGE && freq->old < freq->new)
  2574. return 0;
  2575. per_cpu(cpu_tsc_khz, freq->cpu) = cpufreq_scale(tsc_khz_ref, ref_freq, freq->new);
  2576. spin_lock(&kvm_lock);
  2577. list_for_each_entry(kvm, &vm_list, vm_list) {
  2578. for (i = 0; i < KVM_MAX_VCPUS; ++i) {
  2579. vcpu = kvm->vcpus[i];
  2580. if (!vcpu)
  2581. continue;
  2582. if (vcpu->cpu != freq->cpu)
  2583. continue;
  2584. if (!kvm_request_guest_time_update(vcpu))
  2585. continue;
  2586. if (vcpu->cpu != smp_processor_id())
  2587. send_ipi++;
  2588. }
  2589. }
  2590. spin_unlock(&kvm_lock);
  2591. if (freq->old < freq->new && send_ipi) {
  2592. /*
  2593. * We upscale the frequency. Must make the guest
  2594. * doesn't see old kvmclock values while running with
  2595. * the new frequency, otherwise we risk the guest sees
  2596. * time go backwards.
  2597. *
  2598. * In case we update the frequency for another cpu
  2599. * (which might be in guest context) send an interrupt
  2600. * to kick the cpu out of guest context. Next time
  2601. * guest context is entered kvmclock will be updated,
  2602. * so the guest will not see stale values.
  2603. */
  2604. smp_call_function_single(freq->cpu, bounce_off, NULL, 1);
  2605. }
  2606. return 0;
  2607. }
  2608. static struct notifier_block kvmclock_cpufreq_notifier_block = {
  2609. .notifier_call = kvmclock_cpufreq_notifier
  2610. };
  2611. int kvm_arch_init(void *opaque)
  2612. {
  2613. int r, cpu;
  2614. struct kvm_x86_ops *ops = (struct kvm_x86_ops *)opaque;
  2615. if (kvm_x86_ops) {
  2616. printk(KERN_ERR "kvm: already loaded the other module\n");
  2617. r = -EEXIST;
  2618. goto out;
  2619. }
  2620. if (!ops->cpu_has_kvm_support()) {
  2621. printk(KERN_ERR "kvm: no hardware support\n");
  2622. r = -EOPNOTSUPP;
  2623. goto out;
  2624. }
  2625. if (ops->disabled_by_bios()) {
  2626. printk(KERN_ERR "kvm: disabled by bios\n");
  2627. r = -EOPNOTSUPP;
  2628. goto out;
  2629. }
  2630. r = kvm_mmu_module_init();
  2631. if (r)
  2632. goto out;
  2633. kvm_init_msr_list();
  2634. kvm_x86_ops = ops;
  2635. kvm_mmu_set_nonpresent_ptes(0ull, 0ull);
  2636. kvm_mmu_set_base_ptes(PT_PRESENT_MASK);
  2637. kvm_mmu_set_mask_ptes(PT_USER_MASK, PT_ACCESSED_MASK,
  2638. PT_DIRTY_MASK, PT64_NX_MASK, 0);
  2639. for_each_possible_cpu(cpu)
  2640. per_cpu(cpu_tsc_khz, cpu) = tsc_khz;
  2641. if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC)) {
  2642. tsc_khz_ref = tsc_khz;
  2643. cpufreq_register_notifier(&kvmclock_cpufreq_notifier_block,
  2644. CPUFREQ_TRANSITION_NOTIFIER);
  2645. }
  2646. return 0;
  2647. out:
  2648. return r;
  2649. }
  2650. void kvm_arch_exit(void)
  2651. {
  2652. if (!boot_cpu_has(X86_FEATURE_CONSTANT_TSC))
  2653. cpufreq_unregister_notifier(&kvmclock_cpufreq_notifier_block,
  2654. CPUFREQ_TRANSITION_NOTIFIER);
  2655. kvm_x86_ops = NULL;
  2656. kvm_mmu_module_exit();
  2657. }
  2658. int kvm_emulate_halt(struct kvm_vcpu *vcpu)
  2659. {
  2660. ++vcpu->stat.halt_exits;
  2661. KVMTRACE_0D(HLT, vcpu, handler);
  2662. if (irqchip_in_kernel(vcpu->kvm)) {
  2663. vcpu->arch.mp_state = KVM_MP_STATE_HALTED;
  2664. return 1;
  2665. } else {
  2666. vcpu->run->exit_reason = KVM_EXIT_HLT;
  2667. return 0;
  2668. }
  2669. }
  2670. EXPORT_SYMBOL_GPL(kvm_emulate_halt);
  2671. static inline gpa_t hc_gpa(struct kvm_vcpu *vcpu, unsigned long a0,
  2672. unsigned long a1)
  2673. {
  2674. if (is_long_mode(vcpu))
  2675. return a0;
  2676. else
  2677. return a0 | ((gpa_t)a1 << 32);
  2678. }
  2679. int kvm_emulate_hypercall(struct kvm_vcpu *vcpu)
  2680. {
  2681. unsigned long nr, a0, a1, a2, a3, ret;
  2682. int r = 1;
  2683. nr = kvm_register_read(vcpu, VCPU_REGS_RAX);
  2684. a0 = kvm_register_read(vcpu, VCPU_REGS_RBX);
  2685. a1 = kvm_register_read(vcpu, VCPU_REGS_RCX);
  2686. a2 = kvm_register_read(vcpu, VCPU_REGS_RDX);
  2687. a3 = kvm_register_read(vcpu, VCPU_REGS_RSI);
  2688. KVMTRACE_1D(VMMCALL, vcpu, (u32)nr, handler);
  2689. if (!is_long_mode(vcpu)) {
  2690. nr &= 0xFFFFFFFF;
  2691. a0 &= 0xFFFFFFFF;
  2692. a1 &= 0xFFFFFFFF;
  2693. a2 &= 0xFFFFFFFF;
  2694. a3 &= 0xFFFFFFFF;
  2695. }
  2696. switch (nr) {
  2697. case KVM_HC_VAPIC_POLL_IRQ:
  2698. ret = 0;
  2699. break;
  2700. case KVM_HC_MMU_OP:
  2701. r = kvm_pv_mmu_op(vcpu, a0, hc_gpa(vcpu, a1, a2), &ret);
  2702. break;
  2703. default:
  2704. ret = -KVM_ENOSYS;
  2705. break;
  2706. }
  2707. kvm_register_write(vcpu, VCPU_REGS_RAX, ret);
  2708. ++vcpu->stat.hypercalls;
  2709. return r;
  2710. }
  2711. EXPORT_SYMBOL_GPL(kvm_emulate_hypercall);
  2712. int kvm_fix_hypercall(struct kvm_vcpu *vcpu)
  2713. {
  2714. char instruction[3];
  2715. int ret = 0;
  2716. unsigned long rip = kvm_rip_read(vcpu);
  2717. /*
  2718. * Blow out the MMU to ensure that no other VCPU has an active mapping
  2719. * to ensure that the updated hypercall appears atomically across all
  2720. * VCPUs.
  2721. */
  2722. kvm_mmu_zap_all(vcpu->kvm);
  2723. kvm_x86_ops->patch_hypercall(vcpu, instruction);
  2724. if (emulator_write_emulated(rip, instruction, 3, vcpu)
  2725. != X86EMUL_CONTINUE)
  2726. ret = -EFAULT;
  2727. return ret;
  2728. }
  2729. static u64 mk_cr_64(u64 curr_cr, u32 new_val)
  2730. {
  2731. return (curr_cr & ~((1ULL << 32) - 1)) | new_val;
  2732. }
  2733. void realmode_lgdt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
  2734. {
  2735. struct descriptor_table dt = { limit, base };
  2736. kvm_x86_ops->set_gdt(vcpu, &dt);
  2737. }
  2738. void realmode_lidt(struct kvm_vcpu *vcpu, u16 limit, unsigned long base)
  2739. {
  2740. struct descriptor_table dt = { limit, base };
  2741. kvm_x86_ops->set_idt(vcpu, &dt);
  2742. }
  2743. void realmode_lmsw(struct kvm_vcpu *vcpu, unsigned long msw,
  2744. unsigned long *rflags)
  2745. {
  2746. kvm_lmsw(vcpu, msw);
  2747. *rflags = kvm_x86_ops->get_rflags(vcpu);
  2748. }
  2749. unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr)
  2750. {
  2751. unsigned long value;
  2752. kvm_x86_ops->decache_cr4_guest_bits(vcpu);
  2753. switch (cr) {
  2754. case 0:
  2755. value = vcpu->arch.cr0;
  2756. break;
  2757. case 2:
  2758. value = vcpu->arch.cr2;
  2759. break;
  2760. case 3:
  2761. value = vcpu->arch.cr3;
  2762. break;
  2763. case 4:
  2764. value = vcpu->arch.cr4;
  2765. break;
  2766. case 8:
  2767. value = kvm_get_cr8(vcpu);
  2768. break;
  2769. default:
  2770. vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
  2771. return 0;
  2772. }
  2773. KVMTRACE_3D(CR_READ, vcpu, (u32)cr, (u32)value,
  2774. (u32)((u64)value >> 32), handler);
  2775. return value;
  2776. }
  2777. void realmode_set_cr(struct kvm_vcpu *vcpu, int cr, unsigned long val,
  2778. unsigned long *rflags)
  2779. {
  2780. KVMTRACE_3D(CR_WRITE, vcpu, (u32)cr, (u32)val,
  2781. (u32)((u64)val >> 32), handler);
  2782. switch (cr) {
  2783. case 0:
  2784. kvm_set_cr0(vcpu, mk_cr_64(vcpu->arch.cr0, val));
  2785. *rflags = kvm_x86_ops->get_rflags(vcpu);
  2786. break;
  2787. case 2:
  2788. vcpu->arch.cr2 = val;
  2789. break;
  2790. case 3:
  2791. kvm_set_cr3(vcpu, val);
  2792. break;
  2793. case 4:
  2794. kvm_set_cr4(vcpu, mk_cr_64(vcpu->arch.cr4, val));
  2795. break;
  2796. case 8:
  2797. kvm_set_cr8(vcpu, val & 0xfUL);
  2798. break;
  2799. default:
  2800. vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
  2801. }
  2802. }
  2803. static int move_to_next_stateful_cpuid_entry(struct kvm_vcpu *vcpu, int i)
  2804. {
  2805. struct kvm_cpuid_entry2 *e = &vcpu->arch.cpuid_entries[i];
  2806. int j, nent = vcpu->arch.cpuid_nent;
  2807. e->flags &= ~KVM_CPUID_FLAG_STATE_READ_NEXT;
  2808. /* when no next entry is found, the current entry[i] is reselected */
  2809. for (j = i + 1; ; j = (j + 1) % nent) {
  2810. struct kvm_cpuid_entry2 *ej = &vcpu->arch.cpuid_entries[j];
  2811. if (ej->function == e->function) {
  2812. ej->flags |= KVM_CPUID_FLAG_STATE_READ_NEXT;
  2813. return j;
  2814. }
  2815. }
  2816. return 0; /* silence gcc, even though control never reaches here */
  2817. }
  2818. /* find an entry with matching function, matching index (if needed), and that
  2819. * should be read next (if it's stateful) */
  2820. static int is_matching_cpuid_entry(struct kvm_cpuid_entry2 *e,
  2821. u32 function, u32 index)
  2822. {
  2823. if (e->function != function)
  2824. return 0;
  2825. if ((e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) && e->index != index)
  2826. return 0;
  2827. if ((e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC) &&
  2828. !(e->flags & KVM_CPUID_FLAG_STATE_READ_NEXT))
  2829. return 0;
  2830. return 1;
  2831. }
  2832. struct kvm_cpuid_entry2 *kvm_find_cpuid_entry(struct kvm_vcpu *vcpu,
  2833. u32 function, u32 index)
  2834. {
  2835. int i;
  2836. struct kvm_cpuid_entry2 *best = NULL;
  2837. for (i = 0; i < vcpu->arch.cpuid_nent; ++i) {
  2838. struct kvm_cpuid_entry2 *e;
  2839. e = &vcpu->arch.cpuid_entries[i];
  2840. if (is_matching_cpuid_entry(e, function, index)) {
  2841. if (e->flags & KVM_CPUID_FLAG_STATEFUL_FUNC)
  2842. move_to_next_stateful_cpuid_entry(vcpu, i);
  2843. best = e;
  2844. break;
  2845. }
  2846. /*
  2847. * Both basic or both extended?
  2848. */
  2849. if (((e->function ^ function) & 0x80000000) == 0)
  2850. if (!best || e->function > best->function)
  2851. best = e;
  2852. }
  2853. return best;
  2854. }
  2855. int cpuid_maxphyaddr(struct kvm_vcpu *vcpu)
  2856. {
  2857. struct kvm_cpuid_entry2 *best;
  2858. best = kvm_find_cpuid_entry(vcpu, 0x80000008, 0);
  2859. if (best)
  2860. return best->eax & 0xff;
  2861. return 36;
  2862. }
  2863. void kvm_emulate_cpuid(struct kvm_vcpu *vcpu)
  2864. {
  2865. u32 function, index;
  2866. struct kvm_cpuid_entry2 *best;
  2867. function = kvm_register_read(vcpu, VCPU_REGS_RAX);
  2868. index = kvm_register_read(vcpu, VCPU_REGS_RCX);
  2869. kvm_register_write(vcpu, VCPU_REGS_RAX, 0);
  2870. kvm_register_write(vcpu, VCPU_REGS_RBX, 0);
  2871. kvm_register_write(vcpu, VCPU_REGS_RCX, 0);
  2872. kvm_register_write(vcpu, VCPU_REGS_RDX, 0);
  2873. best = kvm_find_cpuid_entry(vcpu, function, index);
  2874. if (best) {
  2875. kvm_register_write(vcpu, VCPU_REGS_RAX, best->eax);
  2876. kvm_register_write(vcpu, VCPU_REGS_RBX, best->ebx);
  2877. kvm_register_write(vcpu, VCPU_REGS_RCX, best->ecx);
  2878. kvm_register_write(vcpu, VCPU_REGS_RDX, best->edx);
  2879. }
  2880. kvm_x86_ops->skip_emulated_instruction(vcpu);
  2881. KVMTRACE_5D(CPUID, vcpu, function,
  2882. (u32)kvm_register_read(vcpu, VCPU_REGS_RAX),
  2883. (u32)kvm_register_read(vcpu, VCPU_REGS_RBX),
  2884. (u32)kvm_register_read(vcpu, VCPU_REGS_RCX),
  2885. (u32)kvm_register_read(vcpu, VCPU_REGS_RDX), handler);
  2886. }
  2887. EXPORT_SYMBOL_GPL(kvm_emulate_cpuid);
  2888. /*
  2889. * Check if userspace requested an interrupt window, and that the
  2890. * interrupt window is open.
  2891. *
  2892. * No need to exit to userspace if we already have an interrupt queued.
  2893. */
  2894. static int dm_request_for_irq_injection(struct kvm_vcpu *vcpu,
  2895. struct kvm_run *kvm_run)
  2896. {
  2897. return (!irqchip_in_kernel(vcpu->kvm) && !kvm_cpu_has_interrupt(vcpu) &&
  2898. kvm_run->request_interrupt_window &&
  2899. kvm_arch_interrupt_allowed(vcpu));
  2900. }
  2901. static void post_kvm_run_save(struct kvm_vcpu *vcpu,
  2902. struct kvm_run *kvm_run)
  2903. {
  2904. kvm_run->if_flag = (kvm_x86_ops->get_rflags(vcpu) & X86_EFLAGS_IF) != 0;
  2905. kvm_run->cr8 = kvm_get_cr8(vcpu);
  2906. kvm_run->apic_base = kvm_get_apic_base(vcpu);
  2907. if (irqchip_in_kernel(vcpu->kvm))
  2908. kvm_run->ready_for_interrupt_injection = 1;
  2909. else
  2910. kvm_run->ready_for_interrupt_injection =
  2911. kvm_arch_interrupt_allowed(vcpu) &&
  2912. !kvm_cpu_has_interrupt(vcpu) &&
  2913. !kvm_event_needs_reinjection(vcpu);
  2914. }
  2915. static void vapic_enter(struct kvm_vcpu *vcpu)
  2916. {
  2917. struct kvm_lapic *apic = vcpu->arch.apic;
  2918. struct page *page;
  2919. if (!apic || !apic->vapic_addr)
  2920. return;
  2921. page = gfn_to_page(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
  2922. vcpu->arch.apic->vapic_page = page;
  2923. }
  2924. static void vapic_exit(struct kvm_vcpu *vcpu)
  2925. {
  2926. struct kvm_lapic *apic = vcpu->arch.apic;
  2927. if (!apic || !apic->vapic_addr)
  2928. return;
  2929. down_read(&vcpu->kvm->slots_lock);
  2930. kvm_release_page_dirty(apic->vapic_page);
  2931. mark_page_dirty(vcpu->kvm, apic->vapic_addr >> PAGE_SHIFT);
  2932. up_read(&vcpu->kvm->slots_lock);
  2933. }
  2934. static void update_cr8_intercept(struct kvm_vcpu *vcpu)
  2935. {
  2936. int max_irr, tpr;
  2937. if (!kvm_x86_ops->update_cr8_intercept)
  2938. return;
  2939. if (!vcpu->arch.apic->vapic_addr)
  2940. max_irr = kvm_lapic_find_highest_irr(vcpu);
  2941. else
  2942. max_irr = -1;
  2943. if (max_irr != -1)
  2944. max_irr >>= 4;
  2945. tpr = kvm_lapic_get_cr8(vcpu);
  2946. kvm_x86_ops->update_cr8_intercept(vcpu, tpr, max_irr);
  2947. }
  2948. static void inject_pending_irq(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
  2949. {
  2950. /* try to reinject previous events if any */
  2951. if (vcpu->arch.nmi_injected) {
  2952. kvm_x86_ops->set_nmi(vcpu);
  2953. return;
  2954. }
  2955. if (vcpu->arch.interrupt.pending) {
  2956. kvm_x86_ops->set_irq(vcpu);
  2957. return;
  2958. }
  2959. /* try to inject new event if pending */
  2960. if (vcpu->arch.nmi_pending) {
  2961. if (kvm_x86_ops->nmi_allowed(vcpu)) {
  2962. vcpu->arch.nmi_pending = false;
  2963. vcpu->arch.nmi_injected = true;
  2964. kvm_x86_ops->set_nmi(vcpu);
  2965. }
  2966. } else if (kvm_cpu_has_interrupt(vcpu)) {
  2967. if (kvm_x86_ops->interrupt_allowed(vcpu)) {
  2968. kvm_queue_interrupt(vcpu, kvm_cpu_get_interrupt(vcpu),
  2969. false);
  2970. kvm_x86_ops->set_irq(vcpu);
  2971. }
  2972. }
  2973. }
  2974. static int vcpu_enter_guest(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
  2975. {
  2976. int r;
  2977. bool req_int_win = !irqchip_in_kernel(vcpu->kvm) &&
  2978. kvm_run->request_interrupt_window;
  2979. if (vcpu->requests)
  2980. if (test_and_clear_bit(KVM_REQ_MMU_RELOAD, &vcpu->requests))
  2981. kvm_mmu_unload(vcpu);
  2982. r = kvm_mmu_reload(vcpu);
  2983. if (unlikely(r))
  2984. goto out;
  2985. if (vcpu->requests) {
  2986. if (test_and_clear_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests))
  2987. __kvm_migrate_timers(vcpu);
  2988. if (test_and_clear_bit(KVM_REQ_KVMCLOCK_UPDATE, &vcpu->requests))
  2989. kvm_write_guest_time(vcpu);
  2990. if (test_and_clear_bit(KVM_REQ_MMU_SYNC, &vcpu->requests))
  2991. kvm_mmu_sync_roots(vcpu);
  2992. if (test_and_clear_bit(KVM_REQ_TLB_FLUSH, &vcpu->requests))
  2993. kvm_x86_ops->tlb_flush(vcpu);
  2994. if (test_and_clear_bit(KVM_REQ_REPORT_TPR_ACCESS,
  2995. &vcpu->requests)) {
  2996. kvm_run->exit_reason = KVM_EXIT_TPR_ACCESS;
  2997. r = 0;
  2998. goto out;
  2999. }
  3000. if (test_and_clear_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests)) {
  3001. kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
  3002. r = 0;
  3003. goto out;
  3004. }
  3005. }
  3006. preempt_disable();
  3007. kvm_x86_ops->prepare_guest_switch(vcpu);
  3008. kvm_load_guest_fpu(vcpu);
  3009. local_irq_disable();
  3010. clear_bit(KVM_REQ_KICK, &vcpu->requests);
  3011. smp_mb__after_clear_bit();
  3012. if (vcpu->requests || need_resched() || signal_pending(current)) {
  3013. local_irq_enable();
  3014. preempt_enable();
  3015. r = 1;
  3016. goto out;
  3017. }
  3018. if (vcpu->arch.exception.pending)
  3019. __queue_exception(vcpu);
  3020. else
  3021. inject_pending_irq(vcpu, kvm_run);
  3022. /* enable NMI/IRQ window open exits if needed */
  3023. if (vcpu->arch.nmi_pending)
  3024. kvm_x86_ops->enable_nmi_window(vcpu);
  3025. else if (kvm_cpu_has_interrupt(vcpu) || req_int_win)
  3026. kvm_x86_ops->enable_irq_window(vcpu);
  3027. if (kvm_lapic_enabled(vcpu)) {
  3028. update_cr8_intercept(vcpu);
  3029. kvm_lapic_sync_to_vapic(vcpu);
  3030. }
  3031. up_read(&vcpu->kvm->slots_lock);
  3032. kvm_guest_enter();
  3033. get_debugreg(vcpu->arch.host_dr6, 6);
  3034. get_debugreg(vcpu->arch.host_dr7, 7);
  3035. if (unlikely(vcpu->arch.switch_db_regs)) {
  3036. get_debugreg(vcpu->arch.host_db[0], 0);
  3037. get_debugreg(vcpu->arch.host_db[1], 1);
  3038. get_debugreg(vcpu->arch.host_db[2], 2);
  3039. get_debugreg(vcpu->arch.host_db[3], 3);
  3040. set_debugreg(0, 7);
  3041. set_debugreg(vcpu->arch.eff_db[0], 0);
  3042. set_debugreg(vcpu->arch.eff_db[1], 1);
  3043. set_debugreg(vcpu->arch.eff_db[2], 2);
  3044. set_debugreg(vcpu->arch.eff_db[3], 3);
  3045. }
  3046. KVMTRACE_0D(VMENTRY, vcpu, entryexit);
  3047. kvm_x86_ops->run(vcpu, kvm_run);
  3048. if (unlikely(vcpu->arch.switch_db_regs)) {
  3049. set_debugreg(0, 7);
  3050. set_debugreg(vcpu->arch.host_db[0], 0);
  3051. set_debugreg(vcpu->arch.host_db[1], 1);
  3052. set_debugreg(vcpu->arch.host_db[2], 2);
  3053. set_debugreg(vcpu->arch.host_db[3], 3);
  3054. }
  3055. set_debugreg(vcpu->arch.host_dr6, 6);
  3056. set_debugreg(vcpu->arch.host_dr7, 7);
  3057. set_bit(KVM_REQ_KICK, &vcpu->requests);
  3058. local_irq_enable();
  3059. ++vcpu->stat.exits;
  3060. /*
  3061. * We must have an instruction between local_irq_enable() and
  3062. * kvm_guest_exit(), so the timer interrupt isn't delayed by
  3063. * the interrupt shadow. The stat.exits increment will do nicely.
  3064. * But we need to prevent reordering, hence this barrier():
  3065. */
  3066. barrier();
  3067. kvm_guest_exit();
  3068. preempt_enable();
  3069. down_read(&vcpu->kvm->slots_lock);
  3070. /*
  3071. * Profile KVM exit RIPs:
  3072. */
  3073. if (unlikely(prof_on == KVM_PROFILING)) {
  3074. unsigned long rip = kvm_rip_read(vcpu);
  3075. profile_hit(KVM_PROFILING, (void *)rip);
  3076. }
  3077. kvm_lapic_sync_from_vapic(vcpu);
  3078. r = kvm_x86_ops->handle_exit(kvm_run, vcpu);
  3079. out:
  3080. return r;
  3081. }
  3082. static int __vcpu_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
  3083. {
  3084. int r;
  3085. if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED)) {
  3086. pr_debug("vcpu %d received sipi with vector # %x\n",
  3087. vcpu->vcpu_id, vcpu->arch.sipi_vector);
  3088. kvm_lapic_reset(vcpu);
  3089. r = kvm_arch_vcpu_reset(vcpu);
  3090. if (r)
  3091. return r;
  3092. vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
  3093. }
  3094. down_read(&vcpu->kvm->slots_lock);
  3095. vapic_enter(vcpu);
  3096. r = 1;
  3097. while (r > 0) {
  3098. if (vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE)
  3099. r = vcpu_enter_guest(vcpu, kvm_run);
  3100. else {
  3101. up_read(&vcpu->kvm->slots_lock);
  3102. kvm_vcpu_block(vcpu);
  3103. down_read(&vcpu->kvm->slots_lock);
  3104. if (test_and_clear_bit(KVM_REQ_UNHALT, &vcpu->requests))
  3105. {
  3106. switch(vcpu->arch.mp_state) {
  3107. case KVM_MP_STATE_HALTED:
  3108. vcpu->arch.mp_state =
  3109. KVM_MP_STATE_RUNNABLE;
  3110. case KVM_MP_STATE_RUNNABLE:
  3111. break;
  3112. case KVM_MP_STATE_SIPI_RECEIVED:
  3113. default:
  3114. r = -EINTR;
  3115. break;
  3116. }
  3117. }
  3118. }
  3119. if (r <= 0)
  3120. break;
  3121. clear_bit(KVM_REQ_PENDING_TIMER, &vcpu->requests);
  3122. if (kvm_cpu_has_pending_timer(vcpu))
  3123. kvm_inject_pending_timer_irqs(vcpu);
  3124. if (dm_request_for_irq_injection(vcpu, kvm_run)) {
  3125. r = -EINTR;
  3126. kvm_run->exit_reason = KVM_EXIT_INTR;
  3127. ++vcpu->stat.request_irq_exits;
  3128. }
  3129. if (signal_pending(current)) {
  3130. r = -EINTR;
  3131. kvm_run->exit_reason = KVM_EXIT_INTR;
  3132. ++vcpu->stat.signal_exits;
  3133. }
  3134. if (need_resched()) {
  3135. up_read(&vcpu->kvm->slots_lock);
  3136. kvm_resched(vcpu);
  3137. down_read(&vcpu->kvm->slots_lock);
  3138. }
  3139. }
  3140. up_read(&vcpu->kvm->slots_lock);
  3141. post_kvm_run_save(vcpu, kvm_run);
  3142. vapic_exit(vcpu);
  3143. return r;
  3144. }
  3145. int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu, struct kvm_run *kvm_run)
  3146. {
  3147. int r;
  3148. sigset_t sigsaved;
  3149. vcpu_load(vcpu);
  3150. if (vcpu->sigset_active)
  3151. sigprocmask(SIG_SETMASK, &vcpu->sigset, &sigsaved);
  3152. if (unlikely(vcpu->arch.mp_state == KVM_MP_STATE_UNINITIALIZED)) {
  3153. kvm_vcpu_block(vcpu);
  3154. clear_bit(KVM_REQ_UNHALT, &vcpu->requests);
  3155. r = -EAGAIN;
  3156. goto out;
  3157. }
  3158. /* re-sync apic's tpr */
  3159. if (!irqchip_in_kernel(vcpu->kvm))
  3160. kvm_set_cr8(vcpu, kvm_run->cr8);
  3161. if (vcpu->arch.pio.cur_count) {
  3162. r = complete_pio(vcpu);
  3163. if (r)
  3164. goto out;
  3165. }
  3166. #if CONFIG_HAS_IOMEM
  3167. if (vcpu->mmio_needed) {
  3168. memcpy(vcpu->mmio_data, kvm_run->mmio.data, 8);
  3169. vcpu->mmio_read_completed = 1;
  3170. vcpu->mmio_needed = 0;
  3171. down_read(&vcpu->kvm->slots_lock);
  3172. r = emulate_instruction(vcpu, kvm_run,
  3173. vcpu->arch.mmio_fault_cr2, 0,
  3174. EMULTYPE_NO_DECODE);
  3175. up_read(&vcpu->kvm->slots_lock);
  3176. if (r == EMULATE_DO_MMIO) {
  3177. /*
  3178. * Read-modify-write. Back to userspace.
  3179. */
  3180. r = 0;
  3181. goto out;
  3182. }
  3183. }
  3184. #endif
  3185. if (kvm_run->exit_reason == KVM_EXIT_HYPERCALL)
  3186. kvm_register_write(vcpu, VCPU_REGS_RAX,
  3187. kvm_run->hypercall.ret);
  3188. r = __vcpu_run(vcpu, kvm_run);
  3189. out:
  3190. if (vcpu->sigset_active)
  3191. sigprocmask(SIG_SETMASK, &sigsaved, NULL);
  3192. vcpu_put(vcpu);
  3193. return r;
  3194. }
  3195. int kvm_arch_vcpu_ioctl_get_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
  3196. {
  3197. vcpu_load(vcpu);
  3198. regs->rax = kvm_register_read(vcpu, VCPU_REGS_RAX);
  3199. regs->rbx = kvm_register_read(vcpu, VCPU_REGS_RBX);
  3200. regs->rcx = kvm_register_read(vcpu, VCPU_REGS_RCX);
  3201. regs->rdx = kvm_register_read(vcpu, VCPU_REGS_RDX);
  3202. regs->rsi = kvm_register_read(vcpu, VCPU_REGS_RSI);
  3203. regs->rdi = kvm_register_read(vcpu, VCPU_REGS_RDI);
  3204. regs->rsp = kvm_register_read(vcpu, VCPU_REGS_RSP);
  3205. regs->rbp = kvm_register_read(vcpu, VCPU_REGS_RBP);
  3206. #ifdef CONFIG_X86_64
  3207. regs->r8 = kvm_register_read(vcpu, VCPU_REGS_R8);
  3208. regs->r9 = kvm_register_read(vcpu, VCPU_REGS_R9);
  3209. regs->r10 = kvm_register_read(vcpu, VCPU_REGS_R10);
  3210. regs->r11 = kvm_register_read(vcpu, VCPU_REGS_R11);
  3211. regs->r12 = kvm_register_read(vcpu, VCPU_REGS_R12);
  3212. regs->r13 = kvm_register_read(vcpu, VCPU_REGS_R13);
  3213. regs->r14 = kvm_register_read(vcpu, VCPU_REGS_R14);
  3214. regs->r15 = kvm_register_read(vcpu, VCPU_REGS_R15);
  3215. #endif
  3216. regs->rip = kvm_rip_read(vcpu);
  3217. regs->rflags = kvm_x86_ops->get_rflags(vcpu);
  3218. /*
  3219. * Don't leak debug flags in case they were set for guest debugging
  3220. */
  3221. if (vcpu->guest_debug & KVM_GUESTDBG_SINGLESTEP)
  3222. regs->rflags &= ~(X86_EFLAGS_TF | X86_EFLAGS_RF);
  3223. vcpu_put(vcpu);
  3224. return 0;
  3225. }
  3226. int kvm_arch_vcpu_ioctl_set_regs(struct kvm_vcpu *vcpu, struct kvm_regs *regs)
  3227. {
  3228. vcpu_load(vcpu);
  3229. kvm_register_write(vcpu, VCPU_REGS_RAX, regs->rax);
  3230. kvm_register_write(vcpu, VCPU_REGS_RBX, regs->rbx);
  3231. kvm_register_write(vcpu, VCPU_REGS_RCX, regs->rcx);
  3232. kvm_register_write(vcpu, VCPU_REGS_RDX, regs->rdx);
  3233. kvm_register_write(vcpu, VCPU_REGS_RSI, regs->rsi);
  3234. kvm_register_write(vcpu, VCPU_REGS_RDI, regs->rdi);
  3235. kvm_register_write(vcpu, VCPU_REGS_RSP, regs->rsp);
  3236. kvm_register_write(vcpu, VCPU_REGS_RBP, regs->rbp);
  3237. #ifdef CONFIG_X86_64
  3238. kvm_register_write(vcpu, VCPU_REGS_R8, regs->r8);
  3239. kvm_register_write(vcpu, VCPU_REGS_R9, regs->r9);
  3240. kvm_register_write(vcpu, VCPU_REGS_R10, regs->r10);
  3241. kvm_register_write(vcpu, VCPU_REGS_R11, regs->r11);
  3242. kvm_register_write(vcpu, VCPU_REGS_R12, regs->r12);
  3243. kvm_register_write(vcpu, VCPU_REGS_R13, regs->r13);
  3244. kvm_register_write(vcpu, VCPU_REGS_R14, regs->r14);
  3245. kvm_register_write(vcpu, VCPU_REGS_R15, regs->r15);
  3246. #endif
  3247. kvm_rip_write(vcpu, regs->rip);
  3248. kvm_x86_ops->set_rflags(vcpu, regs->rflags);
  3249. vcpu->arch.exception.pending = false;
  3250. vcpu_put(vcpu);
  3251. return 0;
  3252. }
  3253. void kvm_get_segment(struct kvm_vcpu *vcpu,
  3254. struct kvm_segment *var, int seg)
  3255. {
  3256. kvm_x86_ops->get_segment(vcpu, var, seg);
  3257. }
  3258. void kvm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
  3259. {
  3260. struct kvm_segment cs;
  3261. kvm_get_segment(vcpu, &cs, VCPU_SREG_CS);
  3262. *db = cs.db;
  3263. *l = cs.l;
  3264. }
  3265. EXPORT_SYMBOL_GPL(kvm_get_cs_db_l_bits);
  3266. int kvm_arch_vcpu_ioctl_get_sregs(struct kvm_vcpu *vcpu,
  3267. struct kvm_sregs *sregs)
  3268. {
  3269. struct descriptor_table dt;
  3270. vcpu_load(vcpu);
  3271. kvm_get_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
  3272. kvm_get_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
  3273. kvm_get_segment(vcpu, &sregs->es, VCPU_SREG_ES);
  3274. kvm_get_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
  3275. kvm_get_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
  3276. kvm_get_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
  3277. kvm_get_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
  3278. kvm_get_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
  3279. kvm_x86_ops->get_idt(vcpu, &dt);
  3280. sregs->idt.limit = dt.limit;
  3281. sregs->idt.base = dt.base;
  3282. kvm_x86_ops->get_gdt(vcpu, &dt);
  3283. sregs->gdt.limit = dt.limit;
  3284. sregs->gdt.base = dt.base;
  3285. kvm_x86_ops->decache_cr4_guest_bits(vcpu);
  3286. sregs->cr0 = vcpu->arch.cr0;
  3287. sregs->cr2 = vcpu->arch.cr2;
  3288. sregs->cr3 = vcpu->arch.cr3;
  3289. sregs->cr4 = vcpu->arch.cr4;
  3290. sregs->cr8 = kvm_get_cr8(vcpu);
  3291. sregs->efer = vcpu->arch.shadow_efer;
  3292. sregs->apic_base = kvm_get_apic_base(vcpu);
  3293. memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
  3294. if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
  3295. set_bit(vcpu->arch.interrupt.nr,
  3296. (unsigned long *)sregs->interrupt_bitmap);
  3297. vcpu_put(vcpu);
  3298. return 0;
  3299. }
  3300. int kvm_arch_vcpu_ioctl_get_mpstate(struct kvm_vcpu *vcpu,
  3301. struct kvm_mp_state *mp_state)
  3302. {
  3303. vcpu_load(vcpu);
  3304. mp_state->mp_state = vcpu->arch.mp_state;
  3305. vcpu_put(vcpu);
  3306. return 0;
  3307. }
  3308. int kvm_arch_vcpu_ioctl_set_mpstate(struct kvm_vcpu *vcpu,
  3309. struct kvm_mp_state *mp_state)
  3310. {
  3311. vcpu_load(vcpu);
  3312. vcpu->arch.mp_state = mp_state->mp_state;
  3313. vcpu_put(vcpu);
  3314. return 0;
  3315. }
  3316. static void kvm_set_segment(struct kvm_vcpu *vcpu,
  3317. struct kvm_segment *var, int seg)
  3318. {
  3319. kvm_x86_ops->set_segment(vcpu, var, seg);
  3320. }
  3321. static void seg_desct_to_kvm_desct(struct desc_struct *seg_desc, u16 selector,
  3322. struct kvm_segment *kvm_desct)
  3323. {
  3324. kvm_desct->base = seg_desc->base0;
  3325. kvm_desct->base |= seg_desc->base1 << 16;
  3326. kvm_desct->base |= seg_desc->base2 << 24;
  3327. kvm_desct->limit = seg_desc->limit0;
  3328. kvm_desct->limit |= seg_desc->limit << 16;
  3329. if (seg_desc->g) {
  3330. kvm_desct->limit <<= 12;
  3331. kvm_desct->limit |= 0xfff;
  3332. }
  3333. kvm_desct->selector = selector;
  3334. kvm_desct->type = seg_desc->type;
  3335. kvm_desct->present = seg_desc->p;
  3336. kvm_desct->dpl = seg_desc->dpl;
  3337. kvm_desct->db = seg_desc->d;
  3338. kvm_desct->s = seg_desc->s;
  3339. kvm_desct->l = seg_desc->l;
  3340. kvm_desct->g = seg_desc->g;
  3341. kvm_desct->avl = seg_desc->avl;
  3342. if (!selector)
  3343. kvm_desct->unusable = 1;
  3344. else
  3345. kvm_desct->unusable = 0;
  3346. kvm_desct->padding = 0;
  3347. }
  3348. static void get_segment_descriptor_dtable(struct kvm_vcpu *vcpu,
  3349. u16 selector,
  3350. struct descriptor_table *dtable)
  3351. {
  3352. if (selector & 1 << 2) {
  3353. struct kvm_segment kvm_seg;
  3354. kvm_get_segment(vcpu, &kvm_seg, VCPU_SREG_LDTR);
  3355. if (kvm_seg.unusable)
  3356. dtable->limit = 0;
  3357. else
  3358. dtable->limit = kvm_seg.limit;
  3359. dtable->base = kvm_seg.base;
  3360. }
  3361. else
  3362. kvm_x86_ops->get_gdt(vcpu, dtable);
  3363. }
  3364. /* allowed just for 8 bytes segments */
  3365. static int load_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
  3366. struct desc_struct *seg_desc)
  3367. {
  3368. gpa_t gpa;
  3369. struct descriptor_table dtable;
  3370. u16 index = selector >> 3;
  3371. get_segment_descriptor_dtable(vcpu, selector, &dtable);
  3372. if (dtable.limit < index * 8 + 7) {
  3373. kvm_queue_exception_e(vcpu, GP_VECTOR, selector & 0xfffc);
  3374. return 1;
  3375. }
  3376. gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base);
  3377. gpa += index * 8;
  3378. return kvm_read_guest(vcpu->kvm, gpa, seg_desc, 8);
  3379. }
  3380. /* allowed just for 8 bytes segments */
  3381. static int save_guest_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
  3382. struct desc_struct *seg_desc)
  3383. {
  3384. gpa_t gpa;
  3385. struct descriptor_table dtable;
  3386. u16 index = selector >> 3;
  3387. get_segment_descriptor_dtable(vcpu, selector, &dtable);
  3388. if (dtable.limit < index * 8 + 7)
  3389. return 1;
  3390. gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, dtable.base);
  3391. gpa += index * 8;
  3392. return kvm_write_guest(vcpu->kvm, gpa, seg_desc, 8);
  3393. }
  3394. static u32 get_tss_base_addr(struct kvm_vcpu *vcpu,
  3395. struct desc_struct *seg_desc)
  3396. {
  3397. u32 base_addr;
  3398. base_addr = seg_desc->base0;
  3399. base_addr |= (seg_desc->base1 << 16);
  3400. base_addr |= (seg_desc->base2 << 24);
  3401. return vcpu->arch.mmu.gva_to_gpa(vcpu, base_addr);
  3402. }
  3403. static u16 get_segment_selector(struct kvm_vcpu *vcpu, int seg)
  3404. {
  3405. struct kvm_segment kvm_seg;
  3406. kvm_get_segment(vcpu, &kvm_seg, seg);
  3407. return kvm_seg.selector;
  3408. }
  3409. static int load_segment_descriptor_to_kvm_desct(struct kvm_vcpu *vcpu,
  3410. u16 selector,
  3411. struct kvm_segment *kvm_seg)
  3412. {
  3413. struct desc_struct seg_desc;
  3414. if (load_guest_segment_descriptor(vcpu, selector, &seg_desc))
  3415. return 1;
  3416. seg_desct_to_kvm_desct(&seg_desc, selector, kvm_seg);
  3417. return 0;
  3418. }
  3419. static int kvm_load_realmode_segment(struct kvm_vcpu *vcpu, u16 selector, int seg)
  3420. {
  3421. struct kvm_segment segvar = {
  3422. .base = selector << 4,
  3423. .limit = 0xffff,
  3424. .selector = selector,
  3425. .type = 3,
  3426. .present = 1,
  3427. .dpl = 3,
  3428. .db = 0,
  3429. .s = 1,
  3430. .l = 0,
  3431. .g = 0,
  3432. .avl = 0,
  3433. .unusable = 0,
  3434. };
  3435. kvm_x86_ops->set_segment(vcpu, &segvar, seg);
  3436. return 0;
  3437. }
  3438. int kvm_load_segment_descriptor(struct kvm_vcpu *vcpu, u16 selector,
  3439. int type_bits, int seg)
  3440. {
  3441. struct kvm_segment kvm_seg;
  3442. if (!(vcpu->arch.cr0 & X86_CR0_PE))
  3443. return kvm_load_realmode_segment(vcpu, selector, seg);
  3444. if (load_segment_descriptor_to_kvm_desct(vcpu, selector, &kvm_seg))
  3445. return 1;
  3446. kvm_seg.type |= type_bits;
  3447. if (seg != VCPU_SREG_SS && seg != VCPU_SREG_CS &&
  3448. seg != VCPU_SREG_LDTR)
  3449. if (!kvm_seg.s)
  3450. kvm_seg.unusable = 1;
  3451. kvm_set_segment(vcpu, &kvm_seg, seg);
  3452. return 0;
  3453. }
  3454. static void save_state_to_tss32(struct kvm_vcpu *vcpu,
  3455. struct tss_segment_32 *tss)
  3456. {
  3457. tss->cr3 = vcpu->arch.cr3;
  3458. tss->eip = kvm_rip_read(vcpu);
  3459. tss->eflags = kvm_x86_ops->get_rflags(vcpu);
  3460. tss->eax = kvm_register_read(vcpu, VCPU_REGS_RAX);
  3461. tss->ecx = kvm_register_read(vcpu, VCPU_REGS_RCX);
  3462. tss->edx = kvm_register_read(vcpu, VCPU_REGS_RDX);
  3463. tss->ebx = kvm_register_read(vcpu, VCPU_REGS_RBX);
  3464. tss->esp = kvm_register_read(vcpu, VCPU_REGS_RSP);
  3465. tss->ebp = kvm_register_read(vcpu, VCPU_REGS_RBP);
  3466. tss->esi = kvm_register_read(vcpu, VCPU_REGS_RSI);
  3467. tss->edi = kvm_register_read(vcpu, VCPU_REGS_RDI);
  3468. tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
  3469. tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
  3470. tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
  3471. tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
  3472. tss->fs = get_segment_selector(vcpu, VCPU_SREG_FS);
  3473. tss->gs = get_segment_selector(vcpu, VCPU_SREG_GS);
  3474. tss->ldt_selector = get_segment_selector(vcpu, VCPU_SREG_LDTR);
  3475. }
  3476. static int load_state_from_tss32(struct kvm_vcpu *vcpu,
  3477. struct tss_segment_32 *tss)
  3478. {
  3479. kvm_set_cr3(vcpu, tss->cr3);
  3480. kvm_rip_write(vcpu, tss->eip);
  3481. kvm_x86_ops->set_rflags(vcpu, tss->eflags | 2);
  3482. kvm_register_write(vcpu, VCPU_REGS_RAX, tss->eax);
  3483. kvm_register_write(vcpu, VCPU_REGS_RCX, tss->ecx);
  3484. kvm_register_write(vcpu, VCPU_REGS_RDX, tss->edx);
  3485. kvm_register_write(vcpu, VCPU_REGS_RBX, tss->ebx);
  3486. kvm_register_write(vcpu, VCPU_REGS_RSP, tss->esp);
  3487. kvm_register_write(vcpu, VCPU_REGS_RBP, tss->ebp);
  3488. kvm_register_write(vcpu, VCPU_REGS_RSI, tss->esi);
  3489. kvm_register_write(vcpu, VCPU_REGS_RDI, tss->edi);
  3490. if (kvm_load_segment_descriptor(vcpu, tss->ldt_selector, 0, VCPU_SREG_LDTR))
  3491. return 1;
  3492. if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
  3493. return 1;
  3494. if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
  3495. return 1;
  3496. if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
  3497. return 1;
  3498. if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
  3499. return 1;
  3500. if (kvm_load_segment_descriptor(vcpu, tss->fs, 1, VCPU_SREG_FS))
  3501. return 1;
  3502. if (kvm_load_segment_descriptor(vcpu, tss->gs, 1, VCPU_SREG_GS))
  3503. return 1;
  3504. return 0;
  3505. }
  3506. static void save_state_to_tss16(struct kvm_vcpu *vcpu,
  3507. struct tss_segment_16 *tss)
  3508. {
  3509. tss->ip = kvm_rip_read(vcpu);
  3510. tss->flag = kvm_x86_ops->get_rflags(vcpu);
  3511. tss->ax = kvm_register_read(vcpu, VCPU_REGS_RAX);
  3512. tss->cx = kvm_register_read(vcpu, VCPU_REGS_RCX);
  3513. tss->dx = kvm_register_read(vcpu, VCPU_REGS_RDX);
  3514. tss->bx = kvm_register_read(vcpu, VCPU_REGS_RBX);
  3515. tss->sp = kvm_register_read(vcpu, VCPU_REGS_RSP);
  3516. tss->bp = kvm_register_read(vcpu, VCPU_REGS_RBP);
  3517. tss->si = kvm_register_read(vcpu, VCPU_REGS_RSI);
  3518. tss->di = kvm_register_read(vcpu, VCPU_REGS_RDI);
  3519. tss->es = get_segment_selector(vcpu, VCPU_SREG_ES);
  3520. tss->cs = get_segment_selector(vcpu, VCPU_SREG_CS);
  3521. tss->ss = get_segment_selector(vcpu, VCPU_SREG_SS);
  3522. tss->ds = get_segment_selector(vcpu, VCPU_SREG_DS);
  3523. tss->ldt = get_segment_selector(vcpu, VCPU_SREG_LDTR);
  3524. tss->prev_task_link = get_segment_selector(vcpu, VCPU_SREG_TR);
  3525. }
  3526. static int load_state_from_tss16(struct kvm_vcpu *vcpu,
  3527. struct tss_segment_16 *tss)
  3528. {
  3529. kvm_rip_write(vcpu, tss->ip);
  3530. kvm_x86_ops->set_rflags(vcpu, tss->flag | 2);
  3531. kvm_register_write(vcpu, VCPU_REGS_RAX, tss->ax);
  3532. kvm_register_write(vcpu, VCPU_REGS_RCX, tss->cx);
  3533. kvm_register_write(vcpu, VCPU_REGS_RDX, tss->dx);
  3534. kvm_register_write(vcpu, VCPU_REGS_RBX, tss->bx);
  3535. kvm_register_write(vcpu, VCPU_REGS_RSP, tss->sp);
  3536. kvm_register_write(vcpu, VCPU_REGS_RBP, tss->bp);
  3537. kvm_register_write(vcpu, VCPU_REGS_RSI, tss->si);
  3538. kvm_register_write(vcpu, VCPU_REGS_RDI, tss->di);
  3539. if (kvm_load_segment_descriptor(vcpu, tss->ldt, 0, VCPU_SREG_LDTR))
  3540. return 1;
  3541. if (kvm_load_segment_descriptor(vcpu, tss->es, 1, VCPU_SREG_ES))
  3542. return 1;
  3543. if (kvm_load_segment_descriptor(vcpu, tss->cs, 9, VCPU_SREG_CS))
  3544. return 1;
  3545. if (kvm_load_segment_descriptor(vcpu, tss->ss, 1, VCPU_SREG_SS))
  3546. return 1;
  3547. if (kvm_load_segment_descriptor(vcpu, tss->ds, 1, VCPU_SREG_DS))
  3548. return 1;
  3549. return 0;
  3550. }
  3551. static int kvm_task_switch_16(struct kvm_vcpu *vcpu, u16 tss_selector,
  3552. u16 old_tss_sel, u32 old_tss_base,
  3553. struct desc_struct *nseg_desc)
  3554. {
  3555. struct tss_segment_16 tss_segment_16;
  3556. int ret = 0;
  3557. if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
  3558. sizeof tss_segment_16))
  3559. goto out;
  3560. save_state_to_tss16(vcpu, &tss_segment_16);
  3561. if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_16,
  3562. sizeof tss_segment_16))
  3563. goto out;
  3564. if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
  3565. &tss_segment_16, sizeof tss_segment_16))
  3566. goto out;
  3567. if (old_tss_sel != 0xffff) {
  3568. tss_segment_16.prev_task_link = old_tss_sel;
  3569. if (kvm_write_guest(vcpu->kvm,
  3570. get_tss_base_addr(vcpu, nseg_desc),
  3571. &tss_segment_16.prev_task_link,
  3572. sizeof tss_segment_16.prev_task_link))
  3573. goto out;
  3574. }
  3575. if (load_state_from_tss16(vcpu, &tss_segment_16))
  3576. goto out;
  3577. ret = 1;
  3578. out:
  3579. return ret;
  3580. }
  3581. static int kvm_task_switch_32(struct kvm_vcpu *vcpu, u16 tss_selector,
  3582. u16 old_tss_sel, u32 old_tss_base,
  3583. struct desc_struct *nseg_desc)
  3584. {
  3585. struct tss_segment_32 tss_segment_32;
  3586. int ret = 0;
  3587. if (kvm_read_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
  3588. sizeof tss_segment_32))
  3589. goto out;
  3590. save_state_to_tss32(vcpu, &tss_segment_32);
  3591. if (kvm_write_guest(vcpu->kvm, old_tss_base, &tss_segment_32,
  3592. sizeof tss_segment_32))
  3593. goto out;
  3594. if (kvm_read_guest(vcpu->kvm, get_tss_base_addr(vcpu, nseg_desc),
  3595. &tss_segment_32, sizeof tss_segment_32))
  3596. goto out;
  3597. if (old_tss_sel != 0xffff) {
  3598. tss_segment_32.prev_task_link = old_tss_sel;
  3599. if (kvm_write_guest(vcpu->kvm,
  3600. get_tss_base_addr(vcpu, nseg_desc),
  3601. &tss_segment_32.prev_task_link,
  3602. sizeof tss_segment_32.prev_task_link))
  3603. goto out;
  3604. }
  3605. if (load_state_from_tss32(vcpu, &tss_segment_32))
  3606. goto out;
  3607. ret = 1;
  3608. out:
  3609. return ret;
  3610. }
  3611. int kvm_task_switch(struct kvm_vcpu *vcpu, u16 tss_selector, int reason)
  3612. {
  3613. struct kvm_segment tr_seg;
  3614. struct desc_struct cseg_desc;
  3615. struct desc_struct nseg_desc;
  3616. int ret = 0;
  3617. u32 old_tss_base = get_segment_base(vcpu, VCPU_SREG_TR);
  3618. u16 old_tss_sel = get_segment_selector(vcpu, VCPU_SREG_TR);
  3619. old_tss_base = vcpu->arch.mmu.gva_to_gpa(vcpu, old_tss_base);
  3620. /* FIXME: Handle errors. Failure to read either TSS or their
  3621. * descriptors should generate a pagefault.
  3622. */
  3623. if (load_guest_segment_descriptor(vcpu, tss_selector, &nseg_desc))
  3624. goto out;
  3625. if (load_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc))
  3626. goto out;
  3627. if (reason != TASK_SWITCH_IRET) {
  3628. int cpl;
  3629. cpl = kvm_x86_ops->get_cpl(vcpu);
  3630. if ((tss_selector & 3) > nseg_desc.dpl || cpl > nseg_desc.dpl) {
  3631. kvm_queue_exception_e(vcpu, GP_VECTOR, 0);
  3632. return 1;
  3633. }
  3634. }
  3635. if (!nseg_desc.p || (nseg_desc.limit0 | nseg_desc.limit << 16) < 0x67) {
  3636. kvm_queue_exception_e(vcpu, TS_VECTOR, tss_selector & 0xfffc);
  3637. return 1;
  3638. }
  3639. if (reason == TASK_SWITCH_IRET || reason == TASK_SWITCH_JMP) {
  3640. cseg_desc.type &= ~(1 << 1); //clear the B flag
  3641. save_guest_segment_descriptor(vcpu, old_tss_sel, &cseg_desc);
  3642. }
  3643. if (reason == TASK_SWITCH_IRET) {
  3644. u32 eflags = kvm_x86_ops->get_rflags(vcpu);
  3645. kvm_x86_ops->set_rflags(vcpu, eflags & ~X86_EFLAGS_NT);
  3646. }
  3647. /* set back link to prev task only if NT bit is set in eflags
  3648. note that old_tss_sel is not used afetr this point */
  3649. if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
  3650. old_tss_sel = 0xffff;
  3651. /* set back link to prev task only if NT bit is set in eflags
  3652. note that old_tss_sel is not used afetr this point */
  3653. if (reason != TASK_SWITCH_CALL && reason != TASK_SWITCH_GATE)
  3654. old_tss_sel = 0xffff;
  3655. if (nseg_desc.type & 8)
  3656. ret = kvm_task_switch_32(vcpu, tss_selector, old_tss_sel,
  3657. old_tss_base, &nseg_desc);
  3658. else
  3659. ret = kvm_task_switch_16(vcpu, tss_selector, old_tss_sel,
  3660. old_tss_base, &nseg_desc);
  3661. if (reason == TASK_SWITCH_CALL || reason == TASK_SWITCH_GATE) {
  3662. u32 eflags = kvm_x86_ops->get_rflags(vcpu);
  3663. kvm_x86_ops->set_rflags(vcpu, eflags | X86_EFLAGS_NT);
  3664. }
  3665. if (reason != TASK_SWITCH_IRET) {
  3666. nseg_desc.type |= (1 << 1);
  3667. save_guest_segment_descriptor(vcpu, tss_selector,
  3668. &nseg_desc);
  3669. }
  3670. kvm_x86_ops->set_cr0(vcpu, vcpu->arch.cr0 | X86_CR0_TS);
  3671. seg_desct_to_kvm_desct(&nseg_desc, tss_selector, &tr_seg);
  3672. tr_seg.type = 11;
  3673. kvm_set_segment(vcpu, &tr_seg, VCPU_SREG_TR);
  3674. out:
  3675. return ret;
  3676. }
  3677. EXPORT_SYMBOL_GPL(kvm_task_switch);
  3678. int kvm_arch_vcpu_ioctl_set_sregs(struct kvm_vcpu *vcpu,
  3679. struct kvm_sregs *sregs)
  3680. {
  3681. int mmu_reset_needed = 0;
  3682. int pending_vec, max_bits;
  3683. struct descriptor_table dt;
  3684. vcpu_load(vcpu);
  3685. dt.limit = sregs->idt.limit;
  3686. dt.base = sregs->idt.base;
  3687. kvm_x86_ops->set_idt(vcpu, &dt);
  3688. dt.limit = sregs->gdt.limit;
  3689. dt.base = sregs->gdt.base;
  3690. kvm_x86_ops->set_gdt(vcpu, &dt);
  3691. vcpu->arch.cr2 = sregs->cr2;
  3692. mmu_reset_needed |= vcpu->arch.cr3 != sregs->cr3;
  3693. down_read(&vcpu->kvm->slots_lock);
  3694. if (gfn_to_memslot(vcpu->kvm, sregs->cr3 >> PAGE_SHIFT))
  3695. vcpu->arch.cr3 = sregs->cr3;
  3696. else
  3697. set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
  3698. up_read(&vcpu->kvm->slots_lock);
  3699. kvm_set_cr8(vcpu, sregs->cr8);
  3700. mmu_reset_needed |= vcpu->arch.shadow_efer != sregs->efer;
  3701. kvm_x86_ops->set_efer(vcpu, sregs->efer);
  3702. kvm_set_apic_base(vcpu, sregs->apic_base);
  3703. kvm_x86_ops->decache_cr4_guest_bits(vcpu);
  3704. mmu_reset_needed |= vcpu->arch.cr0 != sregs->cr0;
  3705. kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
  3706. vcpu->arch.cr0 = sregs->cr0;
  3707. mmu_reset_needed |= vcpu->arch.cr4 != sregs->cr4;
  3708. kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
  3709. if (!is_long_mode(vcpu) && is_pae(vcpu))
  3710. load_pdptrs(vcpu, vcpu->arch.cr3);
  3711. if (mmu_reset_needed)
  3712. kvm_mmu_reset_context(vcpu);
  3713. max_bits = (sizeof sregs->interrupt_bitmap) << 3;
  3714. pending_vec = find_first_bit(
  3715. (const unsigned long *)sregs->interrupt_bitmap, max_bits);
  3716. if (pending_vec < max_bits) {
  3717. kvm_queue_interrupt(vcpu, pending_vec, false);
  3718. pr_debug("Set back pending irq %d\n", pending_vec);
  3719. if (irqchip_in_kernel(vcpu->kvm))
  3720. kvm_pic_clear_isr_ack(vcpu->kvm);
  3721. }
  3722. kvm_set_segment(vcpu, &sregs->cs, VCPU_SREG_CS);
  3723. kvm_set_segment(vcpu, &sregs->ds, VCPU_SREG_DS);
  3724. kvm_set_segment(vcpu, &sregs->es, VCPU_SREG_ES);
  3725. kvm_set_segment(vcpu, &sregs->fs, VCPU_SREG_FS);
  3726. kvm_set_segment(vcpu, &sregs->gs, VCPU_SREG_GS);
  3727. kvm_set_segment(vcpu, &sregs->ss, VCPU_SREG_SS);
  3728. kvm_set_segment(vcpu, &sregs->tr, VCPU_SREG_TR);
  3729. kvm_set_segment(vcpu, &sregs->ldt, VCPU_SREG_LDTR);
  3730. /* Older userspace won't unhalt the vcpu on reset. */
  3731. if (vcpu->vcpu_id == 0 && kvm_rip_read(vcpu) == 0xfff0 &&
  3732. sregs->cs.selector == 0xf000 && sregs->cs.base == 0xffff0000 &&
  3733. !(vcpu->arch.cr0 & X86_CR0_PE))
  3734. vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
  3735. vcpu_put(vcpu);
  3736. return 0;
  3737. }
  3738. int kvm_arch_vcpu_ioctl_set_guest_debug(struct kvm_vcpu *vcpu,
  3739. struct kvm_guest_debug *dbg)
  3740. {
  3741. int i, r;
  3742. vcpu_load(vcpu);
  3743. if ((dbg->control & (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP)) ==
  3744. (KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP)) {
  3745. for (i = 0; i < KVM_NR_DB_REGS; ++i)
  3746. vcpu->arch.eff_db[i] = dbg->arch.debugreg[i];
  3747. vcpu->arch.switch_db_regs =
  3748. (dbg->arch.debugreg[7] & DR7_BP_EN_MASK);
  3749. } else {
  3750. for (i = 0; i < KVM_NR_DB_REGS; i++)
  3751. vcpu->arch.eff_db[i] = vcpu->arch.db[i];
  3752. vcpu->arch.switch_db_regs = (vcpu->arch.dr7 & DR7_BP_EN_MASK);
  3753. }
  3754. r = kvm_x86_ops->set_guest_debug(vcpu, dbg);
  3755. if (dbg->control & KVM_GUESTDBG_INJECT_DB)
  3756. kvm_queue_exception(vcpu, DB_VECTOR);
  3757. else if (dbg->control & KVM_GUESTDBG_INJECT_BP)
  3758. kvm_queue_exception(vcpu, BP_VECTOR);
  3759. vcpu_put(vcpu);
  3760. return r;
  3761. }
  3762. /*
  3763. * fxsave fpu state. Taken from x86_64/processor.h. To be killed when
  3764. * we have asm/x86/processor.h
  3765. */
  3766. struct fxsave {
  3767. u16 cwd;
  3768. u16 swd;
  3769. u16 twd;
  3770. u16 fop;
  3771. u64 rip;
  3772. u64 rdp;
  3773. u32 mxcsr;
  3774. u32 mxcsr_mask;
  3775. u32 st_space[32]; /* 8*16 bytes for each FP-reg = 128 bytes */
  3776. #ifdef CONFIG_X86_64
  3777. u32 xmm_space[64]; /* 16*16 bytes for each XMM-reg = 256 bytes */
  3778. #else
  3779. u32 xmm_space[32]; /* 8*16 bytes for each XMM-reg = 128 bytes */
  3780. #endif
  3781. };
  3782. /*
  3783. * Translate a guest virtual address to a guest physical address.
  3784. */
  3785. int kvm_arch_vcpu_ioctl_translate(struct kvm_vcpu *vcpu,
  3786. struct kvm_translation *tr)
  3787. {
  3788. unsigned long vaddr = tr->linear_address;
  3789. gpa_t gpa;
  3790. vcpu_load(vcpu);
  3791. down_read(&vcpu->kvm->slots_lock);
  3792. gpa = vcpu->arch.mmu.gva_to_gpa(vcpu, vaddr);
  3793. up_read(&vcpu->kvm->slots_lock);
  3794. tr->physical_address = gpa;
  3795. tr->valid = gpa != UNMAPPED_GVA;
  3796. tr->writeable = 1;
  3797. tr->usermode = 0;
  3798. vcpu_put(vcpu);
  3799. return 0;
  3800. }
  3801. int kvm_arch_vcpu_ioctl_get_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
  3802. {
  3803. struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
  3804. vcpu_load(vcpu);
  3805. memcpy(fpu->fpr, fxsave->st_space, 128);
  3806. fpu->fcw = fxsave->cwd;
  3807. fpu->fsw = fxsave->swd;
  3808. fpu->ftwx = fxsave->twd;
  3809. fpu->last_opcode = fxsave->fop;
  3810. fpu->last_ip = fxsave->rip;
  3811. fpu->last_dp = fxsave->rdp;
  3812. memcpy(fpu->xmm, fxsave->xmm_space, sizeof fxsave->xmm_space);
  3813. vcpu_put(vcpu);
  3814. return 0;
  3815. }
  3816. int kvm_arch_vcpu_ioctl_set_fpu(struct kvm_vcpu *vcpu, struct kvm_fpu *fpu)
  3817. {
  3818. struct fxsave *fxsave = (struct fxsave *)&vcpu->arch.guest_fx_image;
  3819. vcpu_load(vcpu);
  3820. memcpy(fxsave->st_space, fpu->fpr, 128);
  3821. fxsave->cwd = fpu->fcw;
  3822. fxsave->swd = fpu->fsw;
  3823. fxsave->twd = fpu->ftwx;
  3824. fxsave->fop = fpu->last_opcode;
  3825. fxsave->rip = fpu->last_ip;
  3826. fxsave->rdp = fpu->last_dp;
  3827. memcpy(fxsave->xmm_space, fpu->xmm, sizeof fxsave->xmm_space);
  3828. vcpu_put(vcpu);
  3829. return 0;
  3830. }
  3831. void fx_init(struct kvm_vcpu *vcpu)
  3832. {
  3833. unsigned after_mxcsr_mask;
  3834. /*
  3835. * Touch the fpu the first time in non atomic context as if
  3836. * this is the first fpu instruction the exception handler
  3837. * will fire before the instruction returns and it'll have to
  3838. * allocate ram with GFP_KERNEL.
  3839. */
  3840. if (!used_math())
  3841. kvm_fx_save(&vcpu->arch.host_fx_image);
  3842. /* Initialize guest FPU by resetting ours and saving into guest's */
  3843. preempt_disable();
  3844. kvm_fx_save(&vcpu->arch.host_fx_image);
  3845. kvm_fx_finit();
  3846. kvm_fx_save(&vcpu->arch.guest_fx_image);
  3847. kvm_fx_restore(&vcpu->arch.host_fx_image);
  3848. preempt_enable();
  3849. vcpu->arch.cr0 |= X86_CR0_ET;
  3850. after_mxcsr_mask = offsetof(struct i387_fxsave_struct, st_space);
  3851. vcpu->arch.guest_fx_image.mxcsr = 0x1f80;
  3852. memset((void *)&vcpu->arch.guest_fx_image + after_mxcsr_mask,
  3853. 0, sizeof(struct i387_fxsave_struct) - after_mxcsr_mask);
  3854. }
  3855. EXPORT_SYMBOL_GPL(fx_init);
  3856. void kvm_load_guest_fpu(struct kvm_vcpu *vcpu)
  3857. {
  3858. if (!vcpu->fpu_active || vcpu->guest_fpu_loaded)
  3859. return;
  3860. vcpu->guest_fpu_loaded = 1;
  3861. kvm_fx_save(&vcpu->arch.host_fx_image);
  3862. kvm_fx_restore(&vcpu->arch.guest_fx_image);
  3863. }
  3864. EXPORT_SYMBOL_GPL(kvm_load_guest_fpu);
  3865. void kvm_put_guest_fpu(struct kvm_vcpu *vcpu)
  3866. {
  3867. if (!vcpu->guest_fpu_loaded)
  3868. return;
  3869. vcpu->guest_fpu_loaded = 0;
  3870. kvm_fx_save(&vcpu->arch.guest_fx_image);
  3871. kvm_fx_restore(&vcpu->arch.host_fx_image);
  3872. ++vcpu->stat.fpu_reload;
  3873. }
  3874. EXPORT_SYMBOL_GPL(kvm_put_guest_fpu);
  3875. void kvm_arch_vcpu_free(struct kvm_vcpu *vcpu)
  3876. {
  3877. if (vcpu->arch.time_page) {
  3878. kvm_release_page_dirty(vcpu->arch.time_page);
  3879. vcpu->arch.time_page = NULL;
  3880. }
  3881. kvm_x86_ops->vcpu_free(vcpu);
  3882. }
  3883. struct kvm_vcpu *kvm_arch_vcpu_create(struct kvm *kvm,
  3884. unsigned int id)
  3885. {
  3886. return kvm_x86_ops->vcpu_create(kvm, id);
  3887. }
  3888. int kvm_arch_vcpu_setup(struct kvm_vcpu *vcpu)
  3889. {
  3890. int r;
  3891. /* We do fxsave: this must be aligned. */
  3892. BUG_ON((unsigned long)&vcpu->arch.host_fx_image & 0xF);
  3893. vcpu->arch.mtrr_state.have_fixed = 1;
  3894. vcpu_load(vcpu);
  3895. r = kvm_arch_vcpu_reset(vcpu);
  3896. if (r == 0)
  3897. r = kvm_mmu_setup(vcpu);
  3898. vcpu_put(vcpu);
  3899. if (r < 0)
  3900. goto free_vcpu;
  3901. return 0;
  3902. free_vcpu:
  3903. kvm_x86_ops->vcpu_free(vcpu);
  3904. return r;
  3905. }
  3906. void kvm_arch_vcpu_destroy(struct kvm_vcpu *vcpu)
  3907. {
  3908. vcpu_load(vcpu);
  3909. kvm_mmu_unload(vcpu);
  3910. vcpu_put(vcpu);
  3911. kvm_x86_ops->vcpu_free(vcpu);
  3912. }
  3913. int kvm_arch_vcpu_reset(struct kvm_vcpu *vcpu)
  3914. {
  3915. vcpu->arch.nmi_pending = false;
  3916. vcpu->arch.nmi_injected = false;
  3917. vcpu->arch.switch_db_regs = 0;
  3918. memset(vcpu->arch.db, 0, sizeof(vcpu->arch.db));
  3919. vcpu->arch.dr6 = DR6_FIXED_1;
  3920. vcpu->arch.dr7 = DR7_FIXED_1;
  3921. return kvm_x86_ops->vcpu_reset(vcpu);
  3922. }
  3923. void kvm_arch_hardware_enable(void *garbage)
  3924. {
  3925. kvm_x86_ops->hardware_enable(garbage);
  3926. }
  3927. void kvm_arch_hardware_disable(void *garbage)
  3928. {
  3929. kvm_x86_ops->hardware_disable(garbage);
  3930. }
  3931. int kvm_arch_hardware_setup(void)
  3932. {
  3933. return kvm_x86_ops->hardware_setup();
  3934. }
  3935. void kvm_arch_hardware_unsetup(void)
  3936. {
  3937. kvm_x86_ops->hardware_unsetup();
  3938. }
  3939. void kvm_arch_check_processor_compat(void *rtn)
  3940. {
  3941. kvm_x86_ops->check_processor_compatibility(rtn);
  3942. }
  3943. int kvm_arch_vcpu_init(struct kvm_vcpu *vcpu)
  3944. {
  3945. struct page *page;
  3946. struct kvm *kvm;
  3947. int r;
  3948. BUG_ON(vcpu->kvm == NULL);
  3949. kvm = vcpu->kvm;
  3950. vcpu->arch.mmu.root_hpa = INVALID_PAGE;
  3951. if (!irqchip_in_kernel(kvm) || vcpu->vcpu_id == 0)
  3952. vcpu->arch.mp_state = KVM_MP_STATE_RUNNABLE;
  3953. else
  3954. vcpu->arch.mp_state = KVM_MP_STATE_UNINITIALIZED;
  3955. page = alloc_page(GFP_KERNEL | __GFP_ZERO);
  3956. if (!page) {
  3957. r = -ENOMEM;
  3958. goto fail;
  3959. }
  3960. vcpu->arch.pio_data = page_address(page);
  3961. r = kvm_mmu_create(vcpu);
  3962. if (r < 0)
  3963. goto fail_free_pio_data;
  3964. if (irqchip_in_kernel(kvm)) {
  3965. r = kvm_create_lapic(vcpu);
  3966. if (r < 0)
  3967. goto fail_mmu_destroy;
  3968. }
  3969. vcpu->arch.mce_banks = kzalloc(KVM_MAX_MCE_BANKS * sizeof(u64) * 4,
  3970. GFP_KERNEL);
  3971. if (!vcpu->arch.mce_banks) {
  3972. r = -ENOMEM;
  3973. goto fail_mmu_destroy;
  3974. }
  3975. vcpu->arch.mcg_cap = KVM_MAX_MCE_BANKS;
  3976. return 0;
  3977. fail_mmu_destroy:
  3978. kvm_mmu_destroy(vcpu);
  3979. fail_free_pio_data:
  3980. free_page((unsigned long)vcpu->arch.pio_data);
  3981. fail:
  3982. return r;
  3983. }
  3984. void kvm_arch_vcpu_uninit(struct kvm_vcpu *vcpu)
  3985. {
  3986. kvm_free_lapic(vcpu);
  3987. down_read(&vcpu->kvm->slots_lock);
  3988. kvm_mmu_destroy(vcpu);
  3989. up_read(&vcpu->kvm->slots_lock);
  3990. free_page((unsigned long)vcpu->arch.pio_data);
  3991. }
  3992. struct kvm *kvm_arch_create_vm(void)
  3993. {
  3994. struct kvm *kvm = kzalloc(sizeof(struct kvm), GFP_KERNEL);
  3995. if (!kvm)
  3996. return ERR_PTR(-ENOMEM);
  3997. INIT_LIST_HEAD(&kvm->arch.active_mmu_pages);
  3998. INIT_LIST_HEAD(&kvm->arch.assigned_dev_head);
  3999. /* Reserve bit 0 of irq_sources_bitmap for userspace irq source */
  4000. set_bit(KVM_USERSPACE_IRQ_SOURCE_ID, &kvm->arch.irq_sources_bitmap);
  4001. rdtscll(kvm->arch.vm_init_tsc);
  4002. return kvm;
  4003. }
  4004. static void kvm_unload_vcpu_mmu(struct kvm_vcpu *vcpu)
  4005. {
  4006. vcpu_load(vcpu);
  4007. kvm_mmu_unload(vcpu);
  4008. vcpu_put(vcpu);
  4009. }
  4010. static void kvm_free_vcpus(struct kvm *kvm)
  4011. {
  4012. unsigned int i;
  4013. /*
  4014. * Unpin any mmu pages first.
  4015. */
  4016. for (i = 0; i < KVM_MAX_VCPUS; ++i)
  4017. if (kvm->vcpus[i])
  4018. kvm_unload_vcpu_mmu(kvm->vcpus[i]);
  4019. for (i = 0; i < KVM_MAX_VCPUS; ++i) {
  4020. if (kvm->vcpus[i]) {
  4021. kvm_arch_vcpu_free(kvm->vcpus[i]);
  4022. kvm->vcpus[i] = NULL;
  4023. }
  4024. }
  4025. }
  4026. void kvm_arch_sync_events(struct kvm *kvm)
  4027. {
  4028. kvm_free_all_assigned_devices(kvm);
  4029. }
  4030. void kvm_arch_destroy_vm(struct kvm *kvm)
  4031. {
  4032. kvm_iommu_unmap_guest(kvm);
  4033. kvm_free_pit(kvm);
  4034. kfree(kvm->arch.vpic);
  4035. kfree(kvm->arch.vioapic);
  4036. kvm_free_vcpus(kvm);
  4037. kvm_free_physmem(kvm);
  4038. if (kvm->arch.apic_access_page)
  4039. put_page(kvm->arch.apic_access_page);
  4040. if (kvm->arch.ept_identity_pagetable)
  4041. put_page(kvm->arch.ept_identity_pagetable);
  4042. kfree(kvm);
  4043. }
  4044. int kvm_arch_set_memory_region(struct kvm *kvm,
  4045. struct kvm_userspace_memory_region *mem,
  4046. struct kvm_memory_slot old,
  4047. int user_alloc)
  4048. {
  4049. int npages = mem->memory_size >> PAGE_SHIFT;
  4050. struct kvm_memory_slot *memslot = &kvm->memslots[mem->slot];
  4051. /*To keep backward compatibility with older userspace,
  4052. *x86 needs to hanlde !user_alloc case.
  4053. */
  4054. if (!user_alloc) {
  4055. if (npages && !old.rmap) {
  4056. unsigned long userspace_addr;
  4057. down_write(&current->mm->mmap_sem);
  4058. userspace_addr = do_mmap(NULL, 0,
  4059. npages * PAGE_SIZE,
  4060. PROT_READ | PROT_WRITE,
  4061. MAP_PRIVATE | MAP_ANONYMOUS,
  4062. 0);
  4063. up_write(&current->mm->mmap_sem);
  4064. if (IS_ERR((void *)userspace_addr))
  4065. return PTR_ERR((void *)userspace_addr);
  4066. /* set userspace_addr atomically for kvm_hva_to_rmapp */
  4067. spin_lock(&kvm->mmu_lock);
  4068. memslot->userspace_addr = userspace_addr;
  4069. spin_unlock(&kvm->mmu_lock);
  4070. } else {
  4071. if (!old.user_alloc && old.rmap) {
  4072. int ret;
  4073. down_write(&current->mm->mmap_sem);
  4074. ret = do_munmap(current->mm, old.userspace_addr,
  4075. old.npages * PAGE_SIZE);
  4076. up_write(&current->mm->mmap_sem);
  4077. if (ret < 0)
  4078. printk(KERN_WARNING
  4079. "kvm_vm_ioctl_set_memory_region: "
  4080. "failed to munmap memory\n");
  4081. }
  4082. }
  4083. }
  4084. spin_lock(&kvm->mmu_lock);
  4085. if (!kvm->arch.n_requested_mmu_pages) {
  4086. unsigned int nr_mmu_pages = kvm_mmu_calculate_mmu_pages(kvm);
  4087. kvm_mmu_change_mmu_pages(kvm, nr_mmu_pages);
  4088. }
  4089. kvm_mmu_slot_remove_write_access(kvm, mem->slot);
  4090. spin_unlock(&kvm->mmu_lock);
  4091. kvm_flush_remote_tlbs(kvm);
  4092. return 0;
  4093. }
  4094. void kvm_arch_flush_shadow(struct kvm *kvm)
  4095. {
  4096. kvm_mmu_zap_all(kvm);
  4097. kvm_reload_remote_mmus(kvm);
  4098. }
  4099. int kvm_arch_vcpu_runnable(struct kvm_vcpu *vcpu)
  4100. {
  4101. return vcpu->arch.mp_state == KVM_MP_STATE_RUNNABLE
  4102. || vcpu->arch.mp_state == KVM_MP_STATE_SIPI_RECEIVED
  4103. || vcpu->arch.nmi_pending;
  4104. }
  4105. void kvm_vcpu_kick(struct kvm_vcpu *vcpu)
  4106. {
  4107. int me;
  4108. int cpu = vcpu->cpu;
  4109. if (waitqueue_active(&vcpu->wq)) {
  4110. wake_up_interruptible(&vcpu->wq);
  4111. ++vcpu->stat.halt_wakeup;
  4112. }
  4113. me = get_cpu();
  4114. if (cpu != me && (unsigned)cpu < nr_cpu_ids && cpu_online(cpu))
  4115. if (!test_and_set_bit(KVM_REQ_KICK, &vcpu->requests))
  4116. smp_send_reschedule(cpu);
  4117. put_cpu();
  4118. }
  4119. int kvm_arch_interrupt_allowed(struct kvm_vcpu *vcpu)
  4120. {
  4121. return kvm_x86_ops->interrupt_allowed(vcpu);
  4122. }