registers.h 382 KB

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  1. /*
  2. * ARIZONA register definitions
  3. *
  4. * Copyright 2012 Wolfson Microelectronics plc
  5. *
  6. * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #ifndef _ARIZONA_REGISTERS_H
  13. #define _ARIZONA_REGISTERS_H
  14. /*
  15. * Register values.
  16. */
  17. #define ARIZONA_SOFTWARE_RESET 0x00
  18. #define ARIZONA_DEVICE_REVISION 0x01
  19. #define ARIZONA_CTRL_IF_SPI_CFG_1 0x08
  20. #define ARIZONA_CTRL_IF_I2C1_CFG_1 0x09
  21. #define ARIZONA_CTRL_IF_I2C2_CFG_1 0x0A
  22. #define ARIZONA_CTRL_IF_I2C1_CFG_2 0x0B
  23. #define ARIZONA_CTRL_IF_I2C2_CFG_2 0x0C
  24. #define ARIZONA_CTRL_IF_STATUS_1 0x0D
  25. #define ARIZONA_WRITE_SEQUENCER_CTRL_0 0x16
  26. #define ARIZONA_WRITE_SEQUENCER_CTRL_1 0x17
  27. #define ARIZONA_WRITE_SEQUENCER_CTRL_2 0x18
  28. #define ARIZONA_WRITE_SEQUENCER_PROM 0x1A
  29. #define ARIZONA_TONE_GENERATOR_1 0x20
  30. #define ARIZONA_TONE_GENERATOR_2 0x21
  31. #define ARIZONA_TONE_GENERATOR_3 0x22
  32. #define ARIZONA_TONE_GENERATOR_4 0x23
  33. #define ARIZONA_TONE_GENERATOR_5 0x24
  34. #define ARIZONA_PWM_DRIVE_1 0x30
  35. #define ARIZONA_PWM_DRIVE_2 0x31
  36. #define ARIZONA_PWM_DRIVE_3 0x32
  37. #define ARIZONA_WAKE_CONTROL 0x40
  38. #define ARIZONA_SEQUENCE_CONTROL 0x41
  39. #define ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_1 0x61
  40. #define ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_2 0x62
  41. #define ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_3 0x63
  42. #define ARIZONA_SAMPLE_RATE_SEQUENCE_SELECT_4 0x64
  43. #define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_1 0x68
  44. #define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_2 0x69
  45. #define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_3 0x6A
  46. #define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_4 0x6B
  47. #define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_5 0x6C
  48. #define ARIZONA_ALWAYS_ON_TRIGGERS_SEQUENCE_SELECT_6 0x6D
  49. #define ARIZONA_COMFORT_NOISE_GENERATOR 0x70
  50. #define ARIZONA_HAPTICS_CONTROL_1 0x90
  51. #define ARIZONA_HAPTICS_CONTROL_2 0x91
  52. #define ARIZONA_HAPTICS_PHASE_1_INTENSITY 0x92
  53. #define ARIZONA_HAPTICS_PHASE_1_DURATION 0x93
  54. #define ARIZONA_HAPTICS_PHASE_2_INTENSITY 0x94
  55. #define ARIZONA_HAPTICS_PHASE_2_DURATION 0x95
  56. #define ARIZONA_HAPTICS_PHASE_3_INTENSITY 0x96
  57. #define ARIZONA_HAPTICS_PHASE_3_DURATION 0x97
  58. #define ARIZONA_HAPTICS_STATUS 0x98
  59. #define ARIZONA_CLOCK_32K_1 0x100
  60. #define ARIZONA_SYSTEM_CLOCK_1 0x101
  61. #define ARIZONA_SAMPLE_RATE_1 0x102
  62. #define ARIZONA_SAMPLE_RATE_2 0x103
  63. #define ARIZONA_SAMPLE_RATE_3 0x104
  64. #define ARIZONA_SAMPLE_RATE_1_STATUS 0x10A
  65. #define ARIZONA_SAMPLE_RATE_2_STATUS 0x10B
  66. #define ARIZONA_SAMPLE_RATE_3_STATUS 0x10C
  67. #define ARIZONA_ASYNC_CLOCK_1 0x112
  68. #define ARIZONA_ASYNC_SAMPLE_RATE_1 0x113
  69. #define ARIZONA_ASYNC_SAMPLE_RATE_1_STATUS 0x11B
  70. #define ARIZONA_OUTPUT_SYSTEM_CLOCK 0x149
  71. #define ARIZONA_OUTPUT_ASYNC_CLOCK 0x14A
  72. #define ARIZONA_RATE_ESTIMATOR_1 0x152
  73. #define ARIZONA_RATE_ESTIMATOR_2 0x153
  74. #define ARIZONA_RATE_ESTIMATOR_3 0x154
  75. #define ARIZONA_RATE_ESTIMATOR_4 0x155
  76. #define ARIZONA_RATE_ESTIMATOR_5 0x156
  77. #define ARIZONA_DYNAMIC_FREQUENCY_SCALING_1 0x161
  78. #define ARIZONA_FLL1_CONTROL_1 0x171
  79. #define ARIZONA_FLL1_CONTROL_2 0x172
  80. #define ARIZONA_FLL1_CONTROL_3 0x173
  81. #define ARIZONA_FLL1_CONTROL_4 0x174
  82. #define ARIZONA_FLL1_CONTROL_5 0x175
  83. #define ARIZONA_FLL1_CONTROL_6 0x176
  84. #define ARIZONA_FLL1_LOOP_FILTER_TEST_1 0x177
  85. #define ARIZONA_FLL1_NCO_TEST_0 0x178
  86. #define ARIZONA_FLL1_CONTROL_7 0x179
  87. #define ARIZONA_FLL1_SYNCHRONISER_1 0x181
  88. #define ARIZONA_FLL1_SYNCHRONISER_2 0x182
  89. #define ARIZONA_FLL1_SYNCHRONISER_3 0x183
  90. #define ARIZONA_FLL1_SYNCHRONISER_4 0x184
  91. #define ARIZONA_FLL1_SYNCHRONISER_5 0x185
  92. #define ARIZONA_FLL1_SYNCHRONISER_6 0x186
  93. #define ARIZONA_FLL1_SYNCHRONISER_7 0x187
  94. #define ARIZONA_FLL1_SPREAD_SPECTRUM 0x189
  95. #define ARIZONA_FLL1_GPIO_CLOCK 0x18A
  96. #define ARIZONA_FLL2_CONTROL_1 0x191
  97. #define ARIZONA_FLL2_CONTROL_2 0x192
  98. #define ARIZONA_FLL2_CONTROL_3 0x193
  99. #define ARIZONA_FLL2_CONTROL_4 0x194
  100. #define ARIZONA_FLL2_CONTROL_5 0x195
  101. #define ARIZONA_FLL2_CONTROL_6 0x196
  102. #define ARIZONA_FLL2_LOOP_FILTER_TEST_1 0x197
  103. #define ARIZONA_FLL2_NCO_TEST_0 0x198
  104. #define ARIZONA_FLL2_CONTROL_7 0x199
  105. #define ARIZONA_FLL2_SYNCHRONISER_1 0x1A1
  106. #define ARIZONA_FLL2_SYNCHRONISER_2 0x1A2
  107. #define ARIZONA_FLL2_SYNCHRONISER_3 0x1A3
  108. #define ARIZONA_FLL2_SYNCHRONISER_4 0x1A4
  109. #define ARIZONA_FLL2_SYNCHRONISER_5 0x1A5
  110. #define ARIZONA_FLL2_SYNCHRONISER_6 0x1A6
  111. #define ARIZONA_FLL2_SYNCHRONISER_7 0x1A7
  112. #define ARIZONA_FLL2_SPREAD_SPECTRUM 0x1A9
  113. #define ARIZONA_FLL2_GPIO_CLOCK 0x1AA
  114. #define ARIZONA_MIC_CHARGE_PUMP_1 0x200
  115. #define ARIZONA_LDO1_CONTROL_1 0x210
  116. #define ARIZONA_LDO1_CONTROL_2 0x212
  117. #define ARIZONA_LDO2_CONTROL_1 0x213
  118. #define ARIZONA_MIC_BIAS_CTRL_1 0x218
  119. #define ARIZONA_MIC_BIAS_CTRL_2 0x219
  120. #define ARIZONA_MIC_BIAS_CTRL_3 0x21A
  121. #define ARIZONA_ACCESSORY_DETECT_MODE_1 0x293
  122. #define ARIZONA_HEADPHONE_DETECT_1 0x29B
  123. #define ARIZONA_HEADPHONE_DETECT_2 0x29C
  124. #define ARIZONA_HP_DACVAL 0x29F
  125. #define ARIZONA_MICD_CLAMP_CONTROL 0x2A2
  126. #define ARIZONA_MIC_DETECT_1 0x2A3
  127. #define ARIZONA_MIC_DETECT_2 0x2A4
  128. #define ARIZONA_MIC_DETECT_3 0x2A5
  129. #define ARIZONA_MIC_DETECT_LEVEL_1 0x2A6
  130. #define ARIZONA_MIC_DETECT_LEVEL_2 0x2A7
  131. #define ARIZONA_MIC_DETECT_LEVEL_3 0x2A8
  132. #define ARIZONA_MIC_DETECT_LEVEL_4 0x2A9
  133. #define ARIZONA_MIC_NOISE_MIX_CONTROL_1 0x2C3
  134. #define ARIZONA_ISOLATION_CONTROL 0x2CB
  135. #define ARIZONA_JACK_DETECT_ANALOGUE 0x2D3
  136. #define ARIZONA_INPUT_ENABLES 0x300
  137. #define ARIZONA_INPUT_ENABLES_STATUS 0x301
  138. #define ARIZONA_INPUT_RATE 0x308
  139. #define ARIZONA_INPUT_VOLUME_RAMP 0x309
  140. #define ARIZONA_IN1L_CONTROL 0x310
  141. #define ARIZONA_ADC_DIGITAL_VOLUME_1L 0x311
  142. #define ARIZONA_DMIC1L_CONTROL 0x312
  143. #define ARIZONA_IN1R_CONTROL 0x314
  144. #define ARIZONA_ADC_DIGITAL_VOLUME_1R 0x315
  145. #define ARIZONA_DMIC1R_CONTROL 0x316
  146. #define ARIZONA_IN2L_CONTROL 0x318
  147. #define ARIZONA_ADC_DIGITAL_VOLUME_2L 0x319
  148. #define ARIZONA_DMIC2L_CONTROL 0x31A
  149. #define ARIZONA_IN2R_CONTROL 0x31C
  150. #define ARIZONA_ADC_DIGITAL_VOLUME_2R 0x31D
  151. #define ARIZONA_DMIC2R_CONTROL 0x31E
  152. #define ARIZONA_IN3L_CONTROL 0x320
  153. #define ARIZONA_ADC_DIGITAL_VOLUME_3L 0x321
  154. #define ARIZONA_DMIC3L_CONTROL 0x322
  155. #define ARIZONA_IN3R_CONTROL 0x324
  156. #define ARIZONA_ADC_DIGITAL_VOLUME_3R 0x325
  157. #define ARIZONA_DMIC3R_CONTROL 0x326
  158. #define ARIZONA_IN4L_CONTROL 0x328
  159. #define ARIZONA_ADC_DIGITAL_VOLUME_4L 0x329
  160. #define ARIZONA_DMIC4L_CONTROL 0x32A
  161. #define ARIZONA_ADC_DIGITAL_VOLUME_4R 0x32D
  162. #define ARIZONA_DMIC4R_CONTROL 0x32E
  163. #define ARIZONA_OUTPUT_ENABLES_1 0x400
  164. #define ARIZONA_OUTPUT_STATUS_1 0x401
  165. #define ARIZONA_RAW_OUTPUT_STATUS_1 0x406
  166. #define ARIZONA_OUTPUT_RATE_1 0x408
  167. #define ARIZONA_OUTPUT_VOLUME_RAMP 0x409
  168. #define ARIZONA_OUTPUT_PATH_CONFIG_1L 0x410
  169. #define ARIZONA_DAC_DIGITAL_VOLUME_1L 0x411
  170. #define ARIZONA_DAC_VOLUME_LIMIT_1L 0x412
  171. #define ARIZONA_NOISE_GATE_SELECT_1L 0x413
  172. #define ARIZONA_OUTPUT_PATH_CONFIG_1R 0x414
  173. #define ARIZONA_DAC_DIGITAL_VOLUME_1R 0x415
  174. #define ARIZONA_DAC_VOLUME_LIMIT_1R 0x416
  175. #define ARIZONA_NOISE_GATE_SELECT_1R 0x417
  176. #define ARIZONA_OUTPUT_PATH_CONFIG_2L 0x418
  177. #define ARIZONA_DAC_DIGITAL_VOLUME_2L 0x419
  178. #define ARIZONA_DAC_VOLUME_LIMIT_2L 0x41A
  179. #define ARIZONA_NOISE_GATE_SELECT_2L 0x41B
  180. #define ARIZONA_OUTPUT_PATH_CONFIG_2R 0x41C
  181. #define ARIZONA_DAC_DIGITAL_VOLUME_2R 0x41D
  182. #define ARIZONA_DAC_VOLUME_LIMIT_2R 0x41E
  183. #define ARIZONA_NOISE_GATE_SELECT_2R 0x41F
  184. #define ARIZONA_OUTPUT_PATH_CONFIG_3L 0x420
  185. #define ARIZONA_DAC_DIGITAL_VOLUME_3L 0x421
  186. #define ARIZONA_DAC_VOLUME_LIMIT_3L 0x422
  187. #define ARIZONA_NOISE_GATE_SELECT_3L 0x423
  188. #define ARIZONA_OUTPUT_PATH_CONFIG_3R 0x424
  189. #define ARIZONA_DAC_DIGITAL_VOLUME_3R 0x425
  190. #define ARIZONA_DAC_VOLUME_LIMIT_3R 0x426
  191. #define ARIZONA_NOISE_GATE_SELECT_3R 0x427
  192. #define ARIZONA_OUTPUT_PATH_CONFIG_4L 0x428
  193. #define ARIZONA_DAC_DIGITAL_VOLUME_4L 0x429
  194. #define ARIZONA_OUT_VOLUME_4L 0x42A
  195. #define ARIZONA_NOISE_GATE_SELECT_4L 0x42B
  196. #define ARIZONA_OUTPUT_PATH_CONFIG_4R 0x42C
  197. #define ARIZONA_DAC_DIGITAL_VOLUME_4R 0x42D
  198. #define ARIZONA_OUT_VOLUME_4R 0x42E
  199. #define ARIZONA_NOISE_GATE_SELECT_4R 0x42F
  200. #define ARIZONA_OUTPUT_PATH_CONFIG_5L 0x430
  201. #define ARIZONA_DAC_DIGITAL_VOLUME_5L 0x431
  202. #define ARIZONA_DAC_VOLUME_LIMIT_5L 0x432
  203. #define ARIZONA_NOISE_GATE_SELECT_5L 0x433
  204. #define ARIZONA_OUTPUT_PATH_CONFIG_5R 0x434
  205. #define ARIZONA_DAC_DIGITAL_VOLUME_5R 0x435
  206. #define ARIZONA_DAC_VOLUME_LIMIT_5R 0x436
  207. #define ARIZONA_NOISE_GATE_SELECT_5R 0x437
  208. #define ARIZONA_OUTPUT_PATH_CONFIG_6L 0x438
  209. #define ARIZONA_DAC_DIGITAL_VOLUME_6L 0x439
  210. #define ARIZONA_DAC_VOLUME_LIMIT_6L 0x43A
  211. #define ARIZONA_NOISE_GATE_SELECT_6L 0x43B
  212. #define ARIZONA_OUTPUT_PATH_CONFIG_6R 0x43C
  213. #define ARIZONA_DAC_DIGITAL_VOLUME_6R 0x43D
  214. #define ARIZONA_DAC_VOLUME_LIMIT_6R 0x43E
  215. #define ARIZONA_NOISE_GATE_SELECT_6R 0x43F
  216. #define ARIZONA_DAC_AEC_CONTROL_1 0x450
  217. #define ARIZONA_NOISE_GATE_CONTROL 0x458
  218. #define ARIZONA_PDM_SPK1_CTRL_1 0x490
  219. #define ARIZONA_PDM_SPK1_CTRL_2 0x491
  220. #define ARIZONA_PDM_SPK2_CTRL_1 0x492
  221. #define ARIZONA_PDM_SPK2_CTRL_2 0x493
  222. #define ARIZONA_SPK_CTRL_2 0x4B5
  223. #define ARIZONA_SPK_CTRL_3 0x4B6
  224. #define ARIZONA_DAC_COMP_1 0x4DC
  225. #define ARIZONA_DAC_COMP_2 0x4DD
  226. #define ARIZONA_DAC_COMP_3 0x4DE
  227. #define ARIZONA_DAC_COMP_4 0x4DF
  228. #define ARIZONA_AIF1_BCLK_CTRL 0x500
  229. #define ARIZONA_AIF1_TX_PIN_CTRL 0x501
  230. #define ARIZONA_AIF1_RX_PIN_CTRL 0x502
  231. #define ARIZONA_AIF1_RATE_CTRL 0x503
  232. #define ARIZONA_AIF1_FORMAT 0x504
  233. #define ARIZONA_AIF1_TX_BCLK_RATE 0x505
  234. #define ARIZONA_AIF1_RX_BCLK_RATE 0x506
  235. #define ARIZONA_AIF1_FRAME_CTRL_1 0x507
  236. #define ARIZONA_AIF1_FRAME_CTRL_2 0x508
  237. #define ARIZONA_AIF1_FRAME_CTRL_3 0x509
  238. #define ARIZONA_AIF1_FRAME_CTRL_4 0x50A
  239. #define ARIZONA_AIF1_FRAME_CTRL_5 0x50B
  240. #define ARIZONA_AIF1_FRAME_CTRL_6 0x50C
  241. #define ARIZONA_AIF1_FRAME_CTRL_7 0x50D
  242. #define ARIZONA_AIF1_FRAME_CTRL_8 0x50E
  243. #define ARIZONA_AIF1_FRAME_CTRL_9 0x50F
  244. #define ARIZONA_AIF1_FRAME_CTRL_10 0x510
  245. #define ARIZONA_AIF1_FRAME_CTRL_11 0x511
  246. #define ARIZONA_AIF1_FRAME_CTRL_12 0x512
  247. #define ARIZONA_AIF1_FRAME_CTRL_13 0x513
  248. #define ARIZONA_AIF1_FRAME_CTRL_14 0x514
  249. #define ARIZONA_AIF1_FRAME_CTRL_15 0x515
  250. #define ARIZONA_AIF1_FRAME_CTRL_16 0x516
  251. #define ARIZONA_AIF1_FRAME_CTRL_17 0x517
  252. #define ARIZONA_AIF1_FRAME_CTRL_18 0x518
  253. #define ARIZONA_AIF1_TX_ENABLES 0x519
  254. #define ARIZONA_AIF1_RX_ENABLES 0x51A
  255. #define ARIZONA_AIF1_FORCE_WRITE 0x51B
  256. #define ARIZONA_AIF2_BCLK_CTRL 0x540
  257. #define ARIZONA_AIF2_TX_PIN_CTRL 0x541
  258. #define ARIZONA_AIF2_RX_PIN_CTRL 0x542
  259. #define ARIZONA_AIF2_RATE_CTRL 0x543
  260. #define ARIZONA_AIF2_FORMAT 0x544
  261. #define ARIZONA_AIF2_TX_BCLK_RATE 0x545
  262. #define ARIZONA_AIF2_RX_BCLK_RATE 0x546
  263. #define ARIZONA_AIF2_FRAME_CTRL_1 0x547
  264. #define ARIZONA_AIF2_FRAME_CTRL_2 0x548
  265. #define ARIZONA_AIF2_FRAME_CTRL_3 0x549
  266. #define ARIZONA_AIF2_FRAME_CTRL_4 0x54A
  267. #define ARIZONA_AIF2_FRAME_CTRL_11 0x551
  268. #define ARIZONA_AIF2_FRAME_CTRL_12 0x552
  269. #define ARIZONA_AIF2_TX_ENABLES 0x559
  270. #define ARIZONA_AIF2_RX_ENABLES 0x55A
  271. #define ARIZONA_AIF2_FORCE_WRITE 0x55B
  272. #define ARIZONA_AIF3_BCLK_CTRL 0x580
  273. #define ARIZONA_AIF3_TX_PIN_CTRL 0x581
  274. #define ARIZONA_AIF3_RX_PIN_CTRL 0x582
  275. #define ARIZONA_AIF3_RATE_CTRL 0x583
  276. #define ARIZONA_AIF3_FORMAT 0x584
  277. #define ARIZONA_AIF3_TX_BCLK_RATE 0x585
  278. #define ARIZONA_AIF3_RX_BCLK_RATE 0x586
  279. #define ARIZONA_AIF3_FRAME_CTRL_1 0x587
  280. #define ARIZONA_AIF3_FRAME_CTRL_2 0x588
  281. #define ARIZONA_AIF3_FRAME_CTRL_3 0x589
  282. #define ARIZONA_AIF3_FRAME_CTRL_4 0x58A
  283. #define ARIZONA_AIF3_FRAME_CTRL_11 0x591
  284. #define ARIZONA_AIF3_FRAME_CTRL_12 0x592
  285. #define ARIZONA_AIF3_TX_ENABLES 0x599
  286. #define ARIZONA_AIF3_RX_ENABLES 0x59A
  287. #define ARIZONA_AIF3_FORCE_WRITE 0x59B
  288. #define ARIZONA_SLIMBUS_FRAMER_REF_GEAR 0x5E3
  289. #define ARIZONA_SLIMBUS_RATES_1 0x5E5
  290. #define ARIZONA_SLIMBUS_RATES_2 0x5E6
  291. #define ARIZONA_SLIMBUS_RATES_3 0x5E7
  292. #define ARIZONA_SLIMBUS_RATES_4 0x5E8
  293. #define ARIZONA_SLIMBUS_RATES_5 0x5E9
  294. #define ARIZONA_SLIMBUS_RATES_6 0x5EA
  295. #define ARIZONA_SLIMBUS_RATES_7 0x5EB
  296. #define ARIZONA_SLIMBUS_RATES_8 0x5EC
  297. #define ARIZONA_SLIMBUS_RX_CHANNEL_ENABLE 0x5F5
  298. #define ARIZONA_SLIMBUS_TX_CHANNEL_ENABLE 0x5F6
  299. #define ARIZONA_SLIMBUS_RX_PORT_STATUS 0x5F7
  300. #define ARIZONA_SLIMBUS_TX_PORT_STATUS 0x5F8
  301. #define ARIZONA_PWM1MIX_INPUT_1_SOURCE 0x640
  302. #define ARIZONA_PWM1MIX_INPUT_1_VOLUME 0x641
  303. #define ARIZONA_PWM1MIX_INPUT_2_SOURCE 0x642
  304. #define ARIZONA_PWM1MIX_INPUT_2_VOLUME 0x643
  305. #define ARIZONA_PWM1MIX_INPUT_3_SOURCE 0x644
  306. #define ARIZONA_PWM1MIX_INPUT_3_VOLUME 0x645
  307. #define ARIZONA_PWM1MIX_INPUT_4_SOURCE 0x646
  308. #define ARIZONA_PWM1MIX_INPUT_4_VOLUME 0x647
  309. #define ARIZONA_PWM2MIX_INPUT_1_SOURCE 0x648
  310. #define ARIZONA_PWM2MIX_INPUT_1_VOLUME 0x649
  311. #define ARIZONA_PWM2MIX_INPUT_2_SOURCE 0x64A
  312. #define ARIZONA_PWM2MIX_INPUT_2_VOLUME 0x64B
  313. #define ARIZONA_PWM2MIX_INPUT_3_SOURCE 0x64C
  314. #define ARIZONA_PWM2MIX_INPUT_3_VOLUME 0x64D
  315. #define ARIZONA_PWM2MIX_INPUT_4_SOURCE 0x64E
  316. #define ARIZONA_PWM2MIX_INPUT_4_VOLUME 0x64F
  317. #define ARIZONA_MICMIX_INPUT_1_SOURCE 0x660
  318. #define ARIZONA_MICMIX_INPUT_1_VOLUME 0x661
  319. #define ARIZONA_MICMIX_INPUT_2_SOURCE 0x662
  320. #define ARIZONA_MICMIX_INPUT_2_VOLUME 0x663
  321. #define ARIZONA_MICMIX_INPUT_3_SOURCE 0x664
  322. #define ARIZONA_MICMIX_INPUT_3_VOLUME 0x665
  323. #define ARIZONA_MICMIX_INPUT_4_SOURCE 0x666
  324. #define ARIZONA_MICMIX_INPUT_4_VOLUME 0x667
  325. #define ARIZONA_NOISEMIX_INPUT_1_SOURCE 0x668
  326. #define ARIZONA_NOISEMIX_INPUT_1_VOLUME 0x669
  327. #define ARIZONA_NOISEMIX_INPUT_2_SOURCE 0x66A
  328. #define ARIZONA_NOISEMIX_INPUT_2_VOLUME 0x66B
  329. #define ARIZONA_NOISEMIX_INPUT_3_SOURCE 0x66C
  330. #define ARIZONA_NOISEMIX_INPUT_3_VOLUME 0x66D
  331. #define ARIZONA_NOISEMIX_INPUT_4_SOURCE 0x66E
  332. #define ARIZONA_NOISEMIX_INPUT_4_VOLUME 0x66F
  333. #define ARIZONA_OUT1LMIX_INPUT_1_SOURCE 0x680
  334. #define ARIZONA_OUT1LMIX_INPUT_1_VOLUME 0x681
  335. #define ARIZONA_OUT1LMIX_INPUT_2_SOURCE 0x682
  336. #define ARIZONA_OUT1LMIX_INPUT_2_VOLUME 0x683
  337. #define ARIZONA_OUT1LMIX_INPUT_3_SOURCE 0x684
  338. #define ARIZONA_OUT1LMIX_INPUT_3_VOLUME 0x685
  339. #define ARIZONA_OUT1LMIX_INPUT_4_SOURCE 0x686
  340. #define ARIZONA_OUT1LMIX_INPUT_4_VOLUME 0x687
  341. #define ARIZONA_OUT1RMIX_INPUT_1_SOURCE 0x688
  342. #define ARIZONA_OUT1RMIX_INPUT_1_VOLUME 0x689
  343. #define ARIZONA_OUT1RMIX_INPUT_2_SOURCE 0x68A
  344. #define ARIZONA_OUT1RMIX_INPUT_2_VOLUME 0x68B
  345. #define ARIZONA_OUT1RMIX_INPUT_3_SOURCE 0x68C
  346. #define ARIZONA_OUT1RMIX_INPUT_3_VOLUME 0x68D
  347. #define ARIZONA_OUT1RMIX_INPUT_4_SOURCE 0x68E
  348. #define ARIZONA_OUT1RMIX_INPUT_4_VOLUME 0x68F
  349. #define ARIZONA_OUT2LMIX_INPUT_1_SOURCE 0x690
  350. #define ARIZONA_OUT2LMIX_INPUT_1_VOLUME 0x691
  351. #define ARIZONA_OUT2LMIX_INPUT_2_SOURCE 0x692
  352. #define ARIZONA_OUT2LMIX_INPUT_2_VOLUME 0x693
  353. #define ARIZONA_OUT2LMIX_INPUT_3_SOURCE 0x694
  354. #define ARIZONA_OUT2LMIX_INPUT_3_VOLUME 0x695
  355. #define ARIZONA_OUT2LMIX_INPUT_4_SOURCE 0x696
  356. #define ARIZONA_OUT2LMIX_INPUT_4_VOLUME 0x697
  357. #define ARIZONA_OUT2RMIX_INPUT_1_SOURCE 0x698
  358. #define ARIZONA_OUT2RMIX_INPUT_1_VOLUME 0x699
  359. #define ARIZONA_OUT2RMIX_INPUT_2_SOURCE 0x69A
  360. #define ARIZONA_OUT2RMIX_INPUT_2_VOLUME 0x69B
  361. #define ARIZONA_OUT2RMIX_INPUT_3_SOURCE 0x69C
  362. #define ARIZONA_OUT2RMIX_INPUT_3_VOLUME 0x69D
  363. #define ARIZONA_OUT2RMIX_INPUT_4_SOURCE 0x69E
  364. #define ARIZONA_OUT2RMIX_INPUT_4_VOLUME 0x69F
  365. #define ARIZONA_OUT3LMIX_INPUT_1_SOURCE 0x6A0
  366. #define ARIZONA_OUT3LMIX_INPUT_1_VOLUME 0x6A1
  367. #define ARIZONA_OUT3LMIX_INPUT_2_SOURCE 0x6A2
  368. #define ARIZONA_OUT3LMIX_INPUT_2_VOLUME 0x6A3
  369. #define ARIZONA_OUT3LMIX_INPUT_3_SOURCE 0x6A4
  370. #define ARIZONA_OUT3LMIX_INPUT_3_VOLUME 0x6A5
  371. #define ARIZONA_OUT3LMIX_INPUT_4_SOURCE 0x6A6
  372. #define ARIZONA_OUT3LMIX_INPUT_4_VOLUME 0x6A7
  373. #define ARIZONA_OUT3RMIX_INPUT_1_SOURCE 0x6A8
  374. #define ARIZONA_OUT3RMIX_INPUT_1_VOLUME 0x6A9
  375. #define ARIZONA_OUT3RMIX_INPUT_2_SOURCE 0x6AA
  376. #define ARIZONA_OUT3RMIX_INPUT_2_VOLUME 0x6AB
  377. #define ARIZONA_OUT3RMIX_INPUT_3_SOURCE 0x6AC
  378. #define ARIZONA_OUT3RMIX_INPUT_3_VOLUME 0x6AD
  379. #define ARIZONA_OUT3RMIX_INPUT_4_SOURCE 0x6AE
  380. #define ARIZONA_OUT3RMIX_INPUT_4_VOLUME 0x6AF
  381. #define ARIZONA_OUT4LMIX_INPUT_1_SOURCE 0x6B0
  382. #define ARIZONA_OUT4LMIX_INPUT_1_VOLUME 0x6B1
  383. #define ARIZONA_OUT4LMIX_INPUT_2_SOURCE 0x6B2
  384. #define ARIZONA_OUT4LMIX_INPUT_2_VOLUME 0x6B3
  385. #define ARIZONA_OUT4LMIX_INPUT_3_SOURCE 0x6B4
  386. #define ARIZONA_OUT4LMIX_INPUT_3_VOLUME 0x6B5
  387. #define ARIZONA_OUT4LMIX_INPUT_4_SOURCE 0x6B6
  388. #define ARIZONA_OUT4LMIX_INPUT_4_VOLUME 0x6B7
  389. #define ARIZONA_OUT4RMIX_INPUT_1_SOURCE 0x6B8
  390. #define ARIZONA_OUT4RMIX_INPUT_1_VOLUME 0x6B9
  391. #define ARIZONA_OUT4RMIX_INPUT_2_SOURCE 0x6BA
  392. #define ARIZONA_OUT4RMIX_INPUT_2_VOLUME 0x6BB
  393. #define ARIZONA_OUT4RMIX_INPUT_3_SOURCE 0x6BC
  394. #define ARIZONA_OUT4RMIX_INPUT_3_VOLUME 0x6BD
  395. #define ARIZONA_OUT4RMIX_INPUT_4_SOURCE 0x6BE
  396. #define ARIZONA_OUT4RMIX_INPUT_4_VOLUME 0x6BF
  397. #define ARIZONA_OUT5LMIX_INPUT_1_SOURCE 0x6C0
  398. #define ARIZONA_OUT5LMIX_INPUT_1_VOLUME 0x6C1
  399. #define ARIZONA_OUT5LMIX_INPUT_2_SOURCE 0x6C2
  400. #define ARIZONA_OUT5LMIX_INPUT_2_VOLUME 0x6C3
  401. #define ARIZONA_OUT5LMIX_INPUT_3_SOURCE 0x6C4
  402. #define ARIZONA_OUT5LMIX_INPUT_3_VOLUME 0x6C5
  403. #define ARIZONA_OUT5LMIX_INPUT_4_SOURCE 0x6C6
  404. #define ARIZONA_OUT5LMIX_INPUT_4_VOLUME 0x6C7
  405. #define ARIZONA_OUT5RMIX_INPUT_1_SOURCE 0x6C8
  406. #define ARIZONA_OUT5RMIX_INPUT_1_VOLUME 0x6C9
  407. #define ARIZONA_OUT5RMIX_INPUT_2_SOURCE 0x6CA
  408. #define ARIZONA_OUT5RMIX_INPUT_2_VOLUME 0x6CB
  409. #define ARIZONA_OUT5RMIX_INPUT_3_SOURCE 0x6CC
  410. #define ARIZONA_OUT5RMIX_INPUT_3_VOLUME 0x6CD
  411. #define ARIZONA_OUT5RMIX_INPUT_4_SOURCE 0x6CE
  412. #define ARIZONA_OUT5RMIX_INPUT_4_VOLUME 0x6CF
  413. #define ARIZONA_OUT6LMIX_INPUT_1_SOURCE 0x6D0
  414. #define ARIZONA_OUT6LMIX_INPUT_1_VOLUME 0x6D1
  415. #define ARIZONA_OUT6LMIX_INPUT_2_SOURCE 0x6D2
  416. #define ARIZONA_OUT6LMIX_INPUT_2_VOLUME 0x6D3
  417. #define ARIZONA_OUT6LMIX_INPUT_3_SOURCE 0x6D4
  418. #define ARIZONA_OUT6LMIX_INPUT_3_VOLUME 0x6D5
  419. #define ARIZONA_OUT6LMIX_INPUT_4_SOURCE 0x6D6
  420. #define ARIZONA_OUT6LMIX_INPUT_4_VOLUME 0x6D7
  421. #define ARIZONA_OUT6RMIX_INPUT_1_SOURCE 0x6D8
  422. #define ARIZONA_OUT6RMIX_INPUT_1_VOLUME 0x6D9
  423. #define ARIZONA_OUT6RMIX_INPUT_2_SOURCE 0x6DA
  424. #define ARIZONA_OUT6RMIX_INPUT_2_VOLUME 0x6DB
  425. #define ARIZONA_OUT6RMIX_INPUT_3_SOURCE 0x6DC
  426. #define ARIZONA_OUT6RMIX_INPUT_3_VOLUME 0x6DD
  427. #define ARIZONA_OUT6RMIX_INPUT_4_SOURCE 0x6DE
  428. #define ARIZONA_OUT6RMIX_INPUT_4_VOLUME 0x6DF
  429. #define ARIZONA_AIF1TX1MIX_INPUT_1_SOURCE 0x700
  430. #define ARIZONA_AIF1TX1MIX_INPUT_1_VOLUME 0x701
  431. #define ARIZONA_AIF1TX1MIX_INPUT_2_SOURCE 0x702
  432. #define ARIZONA_AIF1TX1MIX_INPUT_2_VOLUME 0x703
  433. #define ARIZONA_AIF1TX1MIX_INPUT_3_SOURCE 0x704
  434. #define ARIZONA_AIF1TX1MIX_INPUT_3_VOLUME 0x705
  435. #define ARIZONA_AIF1TX1MIX_INPUT_4_SOURCE 0x706
  436. #define ARIZONA_AIF1TX1MIX_INPUT_4_VOLUME 0x707
  437. #define ARIZONA_AIF1TX2MIX_INPUT_1_SOURCE 0x708
  438. #define ARIZONA_AIF1TX2MIX_INPUT_1_VOLUME 0x709
  439. #define ARIZONA_AIF1TX2MIX_INPUT_2_SOURCE 0x70A
  440. #define ARIZONA_AIF1TX2MIX_INPUT_2_VOLUME 0x70B
  441. #define ARIZONA_AIF1TX2MIX_INPUT_3_SOURCE 0x70C
  442. #define ARIZONA_AIF1TX2MIX_INPUT_3_VOLUME 0x70D
  443. #define ARIZONA_AIF1TX2MIX_INPUT_4_SOURCE 0x70E
  444. #define ARIZONA_AIF1TX2MIX_INPUT_4_VOLUME 0x70F
  445. #define ARIZONA_AIF1TX3MIX_INPUT_1_SOURCE 0x710
  446. #define ARIZONA_AIF1TX3MIX_INPUT_1_VOLUME 0x711
  447. #define ARIZONA_AIF1TX3MIX_INPUT_2_SOURCE 0x712
  448. #define ARIZONA_AIF1TX3MIX_INPUT_2_VOLUME 0x713
  449. #define ARIZONA_AIF1TX3MIX_INPUT_3_SOURCE 0x714
  450. #define ARIZONA_AIF1TX3MIX_INPUT_3_VOLUME 0x715
  451. #define ARIZONA_AIF1TX3MIX_INPUT_4_SOURCE 0x716
  452. #define ARIZONA_AIF1TX3MIX_INPUT_4_VOLUME 0x717
  453. #define ARIZONA_AIF1TX4MIX_INPUT_1_SOURCE 0x718
  454. #define ARIZONA_AIF1TX4MIX_INPUT_1_VOLUME 0x719
  455. #define ARIZONA_AIF1TX4MIX_INPUT_2_SOURCE 0x71A
  456. #define ARIZONA_AIF1TX4MIX_INPUT_2_VOLUME 0x71B
  457. #define ARIZONA_AIF1TX4MIX_INPUT_3_SOURCE 0x71C
  458. #define ARIZONA_AIF1TX4MIX_INPUT_3_VOLUME 0x71D
  459. #define ARIZONA_AIF1TX4MIX_INPUT_4_SOURCE 0x71E
  460. #define ARIZONA_AIF1TX4MIX_INPUT_4_VOLUME 0x71F
  461. #define ARIZONA_AIF1TX5MIX_INPUT_1_SOURCE 0x720
  462. #define ARIZONA_AIF1TX5MIX_INPUT_1_VOLUME 0x721
  463. #define ARIZONA_AIF1TX5MIX_INPUT_2_SOURCE 0x722
  464. #define ARIZONA_AIF1TX5MIX_INPUT_2_VOLUME 0x723
  465. #define ARIZONA_AIF1TX5MIX_INPUT_3_SOURCE 0x724
  466. #define ARIZONA_AIF1TX5MIX_INPUT_3_VOLUME 0x725
  467. #define ARIZONA_AIF1TX5MIX_INPUT_4_SOURCE 0x726
  468. #define ARIZONA_AIF1TX5MIX_INPUT_4_VOLUME 0x727
  469. #define ARIZONA_AIF1TX6MIX_INPUT_1_SOURCE 0x728
  470. #define ARIZONA_AIF1TX6MIX_INPUT_1_VOLUME 0x729
  471. #define ARIZONA_AIF1TX6MIX_INPUT_2_SOURCE 0x72A
  472. #define ARIZONA_AIF1TX6MIX_INPUT_2_VOLUME 0x72B
  473. #define ARIZONA_AIF1TX6MIX_INPUT_3_SOURCE 0x72C
  474. #define ARIZONA_AIF1TX6MIX_INPUT_3_VOLUME 0x72D
  475. #define ARIZONA_AIF1TX6MIX_INPUT_4_SOURCE 0x72E
  476. #define ARIZONA_AIF1TX6MIX_INPUT_4_VOLUME 0x72F
  477. #define ARIZONA_AIF1TX7MIX_INPUT_1_SOURCE 0x730
  478. #define ARIZONA_AIF1TX7MIX_INPUT_1_VOLUME 0x731
  479. #define ARIZONA_AIF1TX7MIX_INPUT_2_SOURCE 0x732
  480. #define ARIZONA_AIF1TX7MIX_INPUT_2_VOLUME 0x733
  481. #define ARIZONA_AIF1TX7MIX_INPUT_3_SOURCE 0x734
  482. #define ARIZONA_AIF1TX7MIX_INPUT_3_VOLUME 0x735
  483. #define ARIZONA_AIF1TX7MIX_INPUT_4_SOURCE 0x736
  484. #define ARIZONA_AIF1TX7MIX_INPUT_4_VOLUME 0x737
  485. #define ARIZONA_AIF1TX8MIX_INPUT_1_SOURCE 0x738
  486. #define ARIZONA_AIF1TX8MIX_INPUT_1_VOLUME 0x739
  487. #define ARIZONA_AIF1TX8MIX_INPUT_2_SOURCE 0x73A
  488. #define ARIZONA_AIF1TX8MIX_INPUT_2_VOLUME 0x73B
  489. #define ARIZONA_AIF1TX8MIX_INPUT_3_SOURCE 0x73C
  490. #define ARIZONA_AIF1TX8MIX_INPUT_3_VOLUME 0x73D
  491. #define ARIZONA_AIF1TX8MIX_INPUT_4_SOURCE 0x73E
  492. #define ARIZONA_AIF1TX8MIX_INPUT_4_VOLUME 0x73F
  493. #define ARIZONA_AIF2TX1MIX_INPUT_1_SOURCE 0x740
  494. #define ARIZONA_AIF2TX1MIX_INPUT_1_VOLUME 0x741
  495. #define ARIZONA_AIF2TX1MIX_INPUT_2_SOURCE 0x742
  496. #define ARIZONA_AIF2TX1MIX_INPUT_2_VOLUME 0x743
  497. #define ARIZONA_AIF2TX1MIX_INPUT_3_SOURCE 0x744
  498. #define ARIZONA_AIF2TX1MIX_INPUT_3_VOLUME 0x745
  499. #define ARIZONA_AIF2TX1MIX_INPUT_4_SOURCE 0x746
  500. #define ARIZONA_AIF2TX1MIX_INPUT_4_VOLUME 0x747
  501. #define ARIZONA_AIF2TX2MIX_INPUT_1_SOURCE 0x748
  502. #define ARIZONA_AIF2TX2MIX_INPUT_1_VOLUME 0x749
  503. #define ARIZONA_AIF2TX2MIX_INPUT_2_SOURCE 0x74A
  504. #define ARIZONA_AIF2TX2MIX_INPUT_2_VOLUME 0x74B
  505. #define ARIZONA_AIF2TX2MIX_INPUT_3_SOURCE 0x74C
  506. #define ARIZONA_AIF2TX2MIX_INPUT_3_VOLUME 0x74D
  507. #define ARIZONA_AIF2TX2MIX_INPUT_4_SOURCE 0x74E
  508. #define ARIZONA_AIF2TX2MIX_INPUT_4_VOLUME 0x74F
  509. #define ARIZONA_AIF3TX1MIX_INPUT_1_SOURCE 0x780
  510. #define ARIZONA_AIF3TX1MIX_INPUT_1_VOLUME 0x781
  511. #define ARIZONA_AIF3TX1MIX_INPUT_2_SOURCE 0x782
  512. #define ARIZONA_AIF3TX1MIX_INPUT_2_VOLUME 0x783
  513. #define ARIZONA_AIF3TX1MIX_INPUT_3_SOURCE 0x784
  514. #define ARIZONA_AIF3TX1MIX_INPUT_3_VOLUME 0x785
  515. #define ARIZONA_AIF3TX1MIX_INPUT_4_SOURCE 0x786
  516. #define ARIZONA_AIF3TX1MIX_INPUT_4_VOLUME 0x787
  517. #define ARIZONA_AIF3TX2MIX_INPUT_1_SOURCE 0x788
  518. #define ARIZONA_AIF3TX2MIX_INPUT_1_VOLUME 0x789
  519. #define ARIZONA_AIF3TX2MIX_INPUT_2_SOURCE 0x78A
  520. #define ARIZONA_AIF3TX2MIX_INPUT_2_VOLUME 0x78B
  521. #define ARIZONA_AIF3TX2MIX_INPUT_3_SOURCE 0x78C
  522. #define ARIZONA_AIF3TX2MIX_INPUT_3_VOLUME 0x78D
  523. #define ARIZONA_AIF3TX2MIX_INPUT_4_SOURCE 0x78E
  524. #define ARIZONA_AIF3TX2MIX_INPUT_4_VOLUME 0x78F
  525. #define ARIZONA_SLIMTX1MIX_INPUT_1_SOURCE 0x7C0
  526. #define ARIZONA_SLIMTX1MIX_INPUT_1_VOLUME 0x7C1
  527. #define ARIZONA_SLIMTX1MIX_INPUT_2_SOURCE 0x7C2
  528. #define ARIZONA_SLIMTX1MIX_INPUT_2_VOLUME 0x7C3
  529. #define ARIZONA_SLIMTX1MIX_INPUT_3_SOURCE 0x7C4
  530. #define ARIZONA_SLIMTX1MIX_INPUT_3_VOLUME 0x7C5
  531. #define ARIZONA_SLIMTX1MIX_INPUT_4_SOURCE 0x7C6
  532. #define ARIZONA_SLIMTX1MIX_INPUT_4_VOLUME 0x7C7
  533. #define ARIZONA_SLIMTX2MIX_INPUT_1_SOURCE 0x7C8
  534. #define ARIZONA_SLIMTX2MIX_INPUT_1_VOLUME 0x7C9
  535. #define ARIZONA_SLIMTX2MIX_INPUT_2_SOURCE 0x7CA
  536. #define ARIZONA_SLIMTX2MIX_INPUT_2_VOLUME 0x7CB
  537. #define ARIZONA_SLIMTX2MIX_INPUT_3_SOURCE 0x7CC
  538. #define ARIZONA_SLIMTX2MIX_INPUT_3_VOLUME 0x7CD
  539. #define ARIZONA_SLIMTX2MIX_INPUT_4_SOURCE 0x7CE
  540. #define ARIZONA_SLIMTX2MIX_INPUT_4_VOLUME 0x7CF
  541. #define ARIZONA_SLIMTX3MIX_INPUT_1_SOURCE 0x7D0
  542. #define ARIZONA_SLIMTX3MIX_INPUT_1_VOLUME 0x7D1
  543. #define ARIZONA_SLIMTX3MIX_INPUT_2_SOURCE 0x7D2
  544. #define ARIZONA_SLIMTX3MIX_INPUT_2_VOLUME 0x7D3
  545. #define ARIZONA_SLIMTX3MIX_INPUT_3_SOURCE 0x7D4
  546. #define ARIZONA_SLIMTX3MIX_INPUT_3_VOLUME 0x7D5
  547. #define ARIZONA_SLIMTX3MIX_INPUT_4_SOURCE 0x7D6
  548. #define ARIZONA_SLIMTX3MIX_INPUT_4_VOLUME 0x7D7
  549. #define ARIZONA_SLIMTX4MIX_INPUT_1_SOURCE 0x7D8
  550. #define ARIZONA_SLIMTX4MIX_INPUT_1_VOLUME 0x7D9
  551. #define ARIZONA_SLIMTX4MIX_INPUT_2_SOURCE 0x7DA
  552. #define ARIZONA_SLIMTX4MIX_INPUT_2_VOLUME 0x7DB
  553. #define ARIZONA_SLIMTX4MIX_INPUT_3_SOURCE 0x7DC
  554. #define ARIZONA_SLIMTX4MIX_INPUT_3_VOLUME 0x7DD
  555. #define ARIZONA_SLIMTX4MIX_INPUT_4_SOURCE 0x7DE
  556. #define ARIZONA_SLIMTX4MIX_INPUT_4_VOLUME 0x7DF
  557. #define ARIZONA_SLIMTX5MIX_INPUT_1_SOURCE 0x7E0
  558. #define ARIZONA_SLIMTX5MIX_INPUT_1_VOLUME 0x7E1
  559. #define ARIZONA_SLIMTX5MIX_INPUT_2_SOURCE 0x7E2
  560. #define ARIZONA_SLIMTX5MIX_INPUT_2_VOLUME 0x7E3
  561. #define ARIZONA_SLIMTX5MIX_INPUT_3_SOURCE 0x7E4
  562. #define ARIZONA_SLIMTX5MIX_INPUT_3_VOLUME 0x7E5
  563. #define ARIZONA_SLIMTX5MIX_INPUT_4_SOURCE 0x7E6
  564. #define ARIZONA_SLIMTX5MIX_INPUT_4_VOLUME 0x7E7
  565. #define ARIZONA_SLIMTX6MIX_INPUT_1_SOURCE 0x7E8
  566. #define ARIZONA_SLIMTX6MIX_INPUT_1_VOLUME 0x7E9
  567. #define ARIZONA_SLIMTX6MIX_INPUT_2_SOURCE 0x7EA
  568. #define ARIZONA_SLIMTX6MIX_INPUT_2_VOLUME 0x7EB
  569. #define ARIZONA_SLIMTX6MIX_INPUT_3_SOURCE 0x7EC
  570. #define ARIZONA_SLIMTX6MIX_INPUT_3_VOLUME 0x7ED
  571. #define ARIZONA_SLIMTX6MIX_INPUT_4_SOURCE 0x7EE
  572. #define ARIZONA_SLIMTX6MIX_INPUT_4_VOLUME 0x7EF
  573. #define ARIZONA_SLIMTX7MIX_INPUT_1_SOURCE 0x7F0
  574. #define ARIZONA_SLIMTX7MIX_INPUT_1_VOLUME 0x7F1
  575. #define ARIZONA_SLIMTX7MIX_INPUT_2_SOURCE 0x7F2
  576. #define ARIZONA_SLIMTX7MIX_INPUT_2_VOLUME 0x7F3
  577. #define ARIZONA_SLIMTX7MIX_INPUT_3_SOURCE 0x7F4
  578. #define ARIZONA_SLIMTX7MIX_INPUT_3_VOLUME 0x7F5
  579. #define ARIZONA_SLIMTX7MIX_INPUT_4_SOURCE 0x7F6
  580. #define ARIZONA_SLIMTX7MIX_INPUT_4_VOLUME 0x7F7
  581. #define ARIZONA_SLIMTX8MIX_INPUT_1_SOURCE 0x7F8
  582. #define ARIZONA_SLIMTX8MIX_INPUT_1_VOLUME 0x7F9
  583. #define ARIZONA_SLIMTX8MIX_INPUT_2_SOURCE 0x7FA
  584. #define ARIZONA_SLIMTX8MIX_INPUT_2_VOLUME 0x7FB
  585. #define ARIZONA_SLIMTX8MIX_INPUT_3_SOURCE 0x7FC
  586. #define ARIZONA_SLIMTX8MIX_INPUT_3_VOLUME 0x7FD
  587. #define ARIZONA_SLIMTX8MIX_INPUT_4_SOURCE 0x7FE
  588. #define ARIZONA_SLIMTX8MIX_INPUT_4_VOLUME 0x7FF
  589. #define ARIZONA_EQ1MIX_INPUT_1_SOURCE 0x880
  590. #define ARIZONA_EQ1MIX_INPUT_1_VOLUME 0x881
  591. #define ARIZONA_EQ1MIX_INPUT_2_SOURCE 0x882
  592. #define ARIZONA_EQ1MIX_INPUT_2_VOLUME 0x883
  593. #define ARIZONA_EQ1MIX_INPUT_3_SOURCE 0x884
  594. #define ARIZONA_EQ1MIX_INPUT_3_VOLUME 0x885
  595. #define ARIZONA_EQ1MIX_INPUT_4_SOURCE 0x886
  596. #define ARIZONA_EQ1MIX_INPUT_4_VOLUME 0x887
  597. #define ARIZONA_EQ2MIX_INPUT_1_SOURCE 0x888
  598. #define ARIZONA_EQ2MIX_INPUT_1_VOLUME 0x889
  599. #define ARIZONA_EQ2MIX_INPUT_2_SOURCE 0x88A
  600. #define ARIZONA_EQ2MIX_INPUT_2_VOLUME 0x88B
  601. #define ARIZONA_EQ2MIX_INPUT_3_SOURCE 0x88C
  602. #define ARIZONA_EQ2MIX_INPUT_3_VOLUME 0x88D
  603. #define ARIZONA_EQ2MIX_INPUT_4_SOURCE 0x88E
  604. #define ARIZONA_EQ2MIX_INPUT_4_VOLUME 0x88F
  605. #define ARIZONA_EQ3MIX_INPUT_1_SOURCE 0x890
  606. #define ARIZONA_EQ3MIX_INPUT_1_VOLUME 0x891
  607. #define ARIZONA_EQ3MIX_INPUT_2_SOURCE 0x892
  608. #define ARIZONA_EQ3MIX_INPUT_2_VOLUME 0x893
  609. #define ARIZONA_EQ3MIX_INPUT_3_SOURCE 0x894
  610. #define ARIZONA_EQ3MIX_INPUT_3_VOLUME 0x895
  611. #define ARIZONA_EQ3MIX_INPUT_4_SOURCE 0x896
  612. #define ARIZONA_EQ3MIX_INPUT_4_VOLUME 0x897
  613. #define ARIZONA_EQ4MIX_INPUT_1_SOURCE 0x898
  614. #define ARIZONA_EQ4MIX_INPUT_1_VOLUME 0x899
  615. #define ARIZONA_EQ4MIX_INPUT_2_SOURCE 0x89A
  616. #define ARIZONA_EQ4MIX_INPUT_2_VOLUME 0x89B
  617. #define ARIZONA_EQ4MIX_INPUT_3_SOURCE 0x89C
  618. #define ARIZONA_EQ4MIX_INPUT_3_VOLUME 0x89D
  619. #define ARIZONA_EQ4MIX_INPUT_4_SOURCE 0x89E
  620. #define ARIZONA_EQ4MIX_INPUT_4_VOLUME 0x89F
  621. #define ARIZONA_DRC1LMIX_INPUT_1_SOURCE 0x8C0
  622. #define ARIZONA_DRC1LMIX_INPUT_1_VOLUME 0x8C1
  623. #define ARIZONA_DRC1LMIX_INPUT_2_SOURCE 0x8C2
  624. #define ARIZONA_DRC1LMIX_INPUT_2_VOLUME 0x8C3
  625. #define ARIZONA_DRC1LMIX_INPUT_3_SOURCE 0x8C4
  626. #define ARIZONA_DRC1LMIX_INPUT_3_VOLUME 0x8C5
  627. #define ARIZONA_DRC1LMIX_INPUT_4_SOURCE 0x8C6
  628. #define ARIZONA_DRC1LMIX_INPUT_4_VOLUME 0x8C7
  629. #define ARIZONA_DRC1RMIX_INPUT_1_SOURCE 0x8C8
  630. #define ARIZONA_DRC1RMIX_INPUT_1_VOLUME 0x8C9
  631. #define ARIZONA_DRC1RMIX_INPUT_2_SOURCE 0x8CA
  632. #define ARIZONA_DRC1RMIX_INPUT_2_VOLUME 0x8CB
  633. #define ARIZONA_DRC1RMIX_INPUT_3_SOURCE 0x8CC
  634. #define ARIZONA_DRC1RMIX_INPUT_3_VOLUME 0x8CD
  635. #define ARIZONA_DRC1RMIX_INPUT_4_SOURCE 0x8CE
  636. #define ARIZONA_DRC1RMIX_INPUT_4_VOLUME 0x8CF
  637. #define ARIZONA_DRC2LMIX_INPUT_1_SOURCE 0x8D0
  638. #define ARIZONA_DRC2LMIX_INPUT_1_VOLUME 0x8D1
  639. #define ARIZONA_DRC2LMIX_INPUT_2_SOURCE 0x8D2
  640. #define ARIZONA_DRC2LMIX_INPUT_2_VOLUME 0x8D3
  641. #define ARIZONA_DRC2LMIX_INPUT_3_SOURCE 0x8D4
  642. #define ARIZONA_DRC2LMIX_INPUT_3_VOLUME 0x8D5
  643. #define ARIZONA_DRC2LMIX_INPUT_4_SOURCE 0x8D6
  644. #define ARIZONA_DRC2LMIX_INPUT_4_VOLUME 0x8D7
  645. #define ARIZONA_DRC2RMIX_INPUT_1_SOURCE 0x8D8
  646. #define ARIZONA_DRC2RMIX_INPUT_1_VOLUME 0x8D9
  647. #define ARIZONA_DRC2RMIX_INPUT_2_SOURCE 0x8DA
  648. #define ARIZONA_DRC2RMIX_INPUT_2_VOLUME 0x8DB
  649. #define ARIZONA_DRC2RMIX_INPUT_3_SOURCE 0x8DC
  650. #define ARIZONA_DRC2RMIX_INPUT_3_VOLUME 0x8DD
  651. #define ARIZONA_DRC2RMIX_INPUT_4_SOURCE 0x8DE
  652. #define ARIZONA_DRC2RMIX_INPUT_4_VOLUME 0x8DF
  653. #define ARIZONA_HPLP1MIX_INPUT_1_SOURCE 0x900
  654. #define ARIZONA_HPLP1MIX_INPUT_1_VOLUME 0x901
  655. #define ARIZONA_HPLP1MIX_INPUT_2_SOURCE 0x902
  656. #define ARIZONA_HPLP1MIX_INPUT_2_VOLUME 0x903
  657. #define ARIZONA_HPLP1MIX_INPUT_3_SOURCE 0x904
  658. #define ARIZONA_HPLP1MIX_INPUT_3_VOLUME 0x905
  659. #define ARIZONA_HPLP1MIX_INPUT_4_SOURCE 0x906
  660. #define ARIZONA_HPLP1MIX_INPUT_4_VOLUME 0x907
  661. #define ARIZONA_HPLP2MIX_INPUT_1_SOURCE 0x908
  662. #define ARIZONA_HPLP2MIX_INPUT_1_VOLUME 0x909
  663. #define ARIZONA_HPLP2MIX_INPUT_2_SOURCE 0x90A
  664. #define ARIZONA_HPLP2MIX_INPUT_2_VOLUME 0x90B
  665. #define ARIZONA_HPLP2MIX_INPUT_3_SOURCE 0x90C
  666. #define ARIZONA_HPLP2MIX_INPUT_3_VOLUME 0x90D
  667. #define ARIZONA_HPLP2MIX_INPUT_4_SOURCE 0x90E
  668. #define ARIZONA_HPLP2MIX_INPUT_4_VOLUME 0x90F
  669. #define ARIZONA_HPLP3MIX_INPUT_1_SOURCE 0x910
  670. #define ARIZONA_HPLP3MIX_INPUT_1_VOLUME 0x911
  671. #define ARIZONA_HPLP3MIX_INPUT_2_SOURCE 0x912
  672. #define ARIZONA_HPLP3MIX_INPUT_2_VOLUME 0x913
  673. #define ARIZONA_HPLP3MIX_INPUT_3_SOURCE 0x914
  674. #define ARIZONA_HPLP3MIX_INPUT_3_VOLUME 0x915
  675. #define ARIZONA_HPLP3MIX_INPUT_4_SOURCE 0x916
  676. #define ARIZONA_HPLP3MIX_INPUT_4_VOLUME 0x917
  677. #define ARIZONA_HPLP4MIX_INPUT_1_SOURCE 0x918
  678. #define ARIZONA_HPLP4MIX_INPUT_1_VOLUME 0x919
  679. #define ARIZONA_HPLP4MIX_INPUT_2_SOURCE 0x91A
  680. #define ARIZONA_HPLP4MIX_INPUT_2_VOLUME 0x91B
  681. #define ARIZONA_HPLP4MIX_INPUT_3_SOURCE 0x91C
  682. #define ARIZONA_HPLP4MIX_INPUT_3_VOLUME 0x91D
  683. #define ARIZONA_HPLP4MIX_INPUT_4_SOURCE 0x91E
  684. #define ARIZONA_HPLP4MIX_INPUT_4_VOLUME 0x91F
  685. #define ARIZONA_DSP1LMIX_INPUT_1_SOURCE 0x940
  686. #define ARIZONA_DSP1LMIX_INPUT_1_VOLUME 0x941
  687. #define ARIZONA_DSP1LMIX_INPUT_2_SOURCE 0x942
  688. #define ARIZONA_DSP1LMIX_INPUT_2_VOLUME 0x943
  689. #define ARIZONA_DSP1LMIX_INPUT_3_SOURCE 0x944
  690. #define ARIZONA_DSP1LMIX_INPUT_3_VOLUME 0x945
  691. #define ARIZONA_DSP1LMIX_INPUT_4_SOURCE 0x946
  692. #define ARIZONA_DSP1LMIX_INPUT_4_VOLUME 0x947
  693. #define ARIZONA_DSP1RMIX_INPUT_1_SOURCE 0x948
  694. #define ARIZONA_DSP1RMIX_INPUT_1_VOLUME 0x949
  695. #define ARIZONA_DSP1RMIX_INPUT_2_SOURCE 0x94A
  696. #define ARIZONA_DSP1RMIX_INPUT_2_VOLUME 0x94B
  697. #define ARIZONA_DSP1RMIX_INPUT_3_SOURCE 0x94C
  698. #define ARIZONA_DSP1RMIX_INPUT_3_VOLUME 0x94D
  699. #define ARIZONA_DSP1RMIX_INPUT_4_SOURCE 0x94E
  700. #define ARIZONA_DSP1RMIX_INPUT_4_VOLUME 0x94F
  701. #define ARIZONA_DSP1AUX1MIX_INPUT_1_SOURCE 0x950
  702. #define ARIZONA_DSP1AUX2MIX_INPUT_1_SOURCE 0x958
  703. #define ARIZONA_DSP1AUX3MIX_INPUT_1_SOURCE 0x960
  704. #define ARIZONA_DSP1AUX4MIX_INPUT_1_SOURCE 0x968
  705. #define ARIZONA_DSP1AUX5MIX_INPUT_1_SOURCE 0x970
  706. #define ARIZONA_DSP1AUX6MIX_INPUT_1_SOURCE 0x978
  707. #define ARIZONA_DSP2LMIX_INPUT_1_SOURCE 0x980
  708. #define ARIZONA_DSP2LMIX_INPUT_1_VOLUME 0x981
  709. #define ARIZONA_DSP2LMIX_INPUT_2_SOURCE 0x982
  710. #define ARIZONA_DSP2LMIX_INPUT_2_VOLUME 0x983
  711. #define ARIZONA_DSP2LMIX_INPUT_3_SOURCE 0x984
  712. #define ARIZONA_DSP2LMIX_INPUT_3_VOLUME 0x985
  713. #define ARIZONA_DSP2LMIX_INPUT_4_SOURCE 0x986
  714. #define ARIZONA_DSP2LMIX_INPUT_4_VOLUME 0x987
  715. #define ARIZONA_DSP2RMIX_INPUT_1_SOURCE 0x988
  716. #define ARIZONA_DSP2RMIX_INPUT_1_VOLUME 0x989
  717. #define ARIZONA_DSP2RMIX_INPUT_2_SOURCE 0x98A
  718. #define ARIZONA_DSP2RMIX_INPUT_2_VOLUME 0x98B
  719. #define ARIZONA_DSP2RMIX_INPUT_3_SOURCE 0x98C
  720. #define ARIZONA_DSP2RMIX_INPUT_3_VOLUME 0x98D
  721. #define ARIZONA_DSP2RMIX_INPUT_4_SOURCE 0x98E
  722. #define ARIZONA_DSP2RMIX_INPUT_4_VOLUME 0x98F
  723. #define ARIZONA_DSP2AUX1MIX_INPUT_1_SOURCE 0x990
  724. #define ARIZONA_DSP2AUX2MIX_INPUT_1_SOURCE 0x998
  725. #define ARIZONA_DSP2AUX3MIX_INPUT_1_SOURCE 0x9A0
  726. #define ARIZONA_DSP2AUX4MIX_INPUT_1_SOURCE 0x9A8
  727. #define ARIZONA_DSP2AUX5MIX_INPUT_1_SOURCE 0x9B0
  728. #define ARIZONA_DSP2AUX6MIX_INPUT_1_SOURCE 0x9B8
  729. #define ARIZONA_DSP3LMIX_INPUT_1_SOURCE 0x9C0
  730. #define ARIZONA_DSP3LMIX_INPUT_1_VOLUME 0x9C1
  731. #define ARIZONA_DSP3LMIX_INPUT_2_SOURCE 0x9C2
  732. #define ARIZONA_DSP3LMIX_INPUT_2_VOLUME 0x9C3
  733. #define ARIZONA_DSP3LMIX_INPUT_3_SOURCE 0x9C4
  734. #define ARIZONA_DSP3LMIX_INPUT_3_VOLUME 0x9C5
  735. #define ARIZONA_DSP3LMIX_INPUT_4_SOURCE 0x9C6
  736. #define ARIZONA_DSP3LMIX_INPUT_4_VOLUME 0x9C7
  737. #define ARIZONA_DSP3RMIX_INPUT_1_SOURCE 0x9C8
  738. #define ARIZONA_DSP3RMIX_INPUT_1_VOLUME 0x9C9
  739. #define ARIZONA_DSP3RMIX_INPUT_2_SOURCE 0x9CA
  740. #define ARIZONA_DSP3RMIX_INPUT_2_VOLUME 0x9CB
  741. #define ARIZONA_DSP3RMIX_INPUT_3_SOURCE 0x9CC
  742. #define ARIZONA_DSP3RMIX_INPUT_3_VOLUME 0x9CD
  743. #define ARIZONA_DSP3RMIX_INPUT_4_SOURCE 0x9CE
  744. #define ARIZONA_DSP3RMIX_INPUT_4_VOLUME 0x9CF
  745. #define ARIZONA_DSP3AUX1MIX_INPUT_1_SOURCE 0x9D0
  746. #define ARIZONA_DSP3AUX2MIX_INPUT_1_SOURCE 0x9D8
  747. #define ARIZONA_DSP3AUX3MIX_INPUT_1_SOURCE 0x9E0
  748. #define ARIZONA_DSP3AUX4MIX_INPUT_1_SOURCE 0x9E8
  749. #define ARIZONA_DSP3AUX5MIX_INPUT_1_SOURCE 0x9F0
  750. #define ARIZONA_DSP3AUX6MIX_INPUT_1_SOURCE 0x9F8
  751. #define ARIZONA_DSP4LMIX_INPUT_1_SOURCE 0xA00
  752. #define ARIZONA_DSP4LMIX_INPUT_1_VOLUME 0xA01
  753. #define ARIZONA_DSP4LMIX_INPUT_2_SOURCE 0xA02
  754. #define ARIZONA_DSP4LMIX_INPUT_2_VOLUME 0xA03
  755. #define ARIZONA_DSP4LMIX_INPUT_3_SOURCE 0xA04
  756. #define ARIZONA_DSP4LMIX_INPUT_3_VOLUME 0xA05
  757. #define ARIZONA_DSP4LMIX_INPUT_4_SOURCE 0xA06
  758. #define ARIZONA_DSP4LMIX_INPUT_4_VOLUME 0xA07
  759. #define ARIZONA_DSP4RMIX_INPUT_1_SOURCE 0xA08
  760. #define ARIZONA_DSP4RMIX_INPUT_1_VOLUME 0xA09
  761. #define ARIZONA_DSP4RMIX_INPUT_2_SOURCE 0xA0A
  762. #define ARIZONA_DSP4RMIX_INPUT_2_VOLUME 0xA0B
  763. #define ARIZONA_DSP4RMIX_INPUT_3_SOURCE 0xA0C
  764. #define ARIZONA_DSP4RMIX_INPUT_3_VOLUME 0xA0D
  765. #define ARIZONA_DSP4RMIX_INPUT_4_SOURCE 0xA0E
  766. #define ARIZONA_DSP4RMIX_INPUT_4_VOLUME 0xA0F
  767. #define ARIZONA_DSP4AUX1MIX_INPUT_1_SOURCE 0xA10
  768. #define ARIZONA_DSP4AUX2MIX_INPUT_1_SOURCE 0xA18
  769. #define ARIZONA_DSP4AUX3MIX_INPUT_1_SOURCE 0xA20
  770. #define ARIZONA_DSP4AUX4MIX_INPUT_1_SOURCE 0xA28
  771. #define ARIZONA_DSP4AUX5MIX_INPUT_1_SOURCE 0xA30
  772. #define ARIZONA_DSP4AUX6MIX_INPUT_1_SOURCE 0xA38
  773. #define ARIZONA_ASRC1LMIX_INPUT_1_SOURCE 0xA80
  774. #define ARIZONA_ASRC1RMIX_INPUT_1_SOURCE 0xA88
  775. #define ARIZONA_ASRC2LMIX_INPUT_1_SOURCE 0xA90
  776. #define ARIZONA_ASRC2RMIX_INPUT_1_SOURCE 0xA98
  777. #define ARIZONA_ISRC1DEC1MIX_INPUT_1_SOURCE 0xB00
  778. #define ARIZONA_ISRC1DEC2MIX_INPUT_1_SOURCE 0xB08
  779. #define ARIZONA_ISRC1DEC3MIX_INPUT_1_SOURCE 0xB10
  780. #define ARIZONA_ISRC1DEC4MIX_INPUT_1_SOURCE 0xB18
  781. #define ARIZONA_ISRC1INT1MIX_INPUT_1_SOURCE 0xB20
  782. #define ARIZONA_ISRC1INT2MIX_INPUT_1_SOURCE 0xB28
  783. #define ARIZONA_ISRC1INT3MIX_INPUT_1_SOURCE 0xB30
  784. #define ARIZONA_ISRC1INT4MIX_INPUT_1_SOURCE 0xB38
  785. #define ARIZONA_ISRC2DEC1MIX_INPUT_1_SOURCE 0xB40
  786. #define ARIZONA_ISRC2DEC2MIX_INPUT_1_SOURCE 0xB48
  787. #define ARIZONA_ISRC2INT1MIX_INPUT_1_SOURCE 0xB60
  788. #define ARIZONA_ISRC2INT2MIX_INPUT_1_SOURCE 0xB68
  789. #define ARIZONA_ISRC1INT3MIX_INPUT_1_SOURCE 0xB30
  790. #define ARIZONA_ISRC1INT4MIX_INPUT_1_SOURCE 0xB38
  791. #define ARIZONA_ISRC2DEC1MIX_INPUT_1_SOURCE 0xB40
  792. #define ARIZONA_ISRC2DEC2MIX_INPUT_1_SOURCE 0xB48
  793. #define ARIZONA_ISRC2DEC3MIX_INPUT_1_SOURCE 0xB50
  794. #define ARIZONA_ISRC2DEC4MIX_INPUT_1_SOURCE 0xB58
  795. #define ARIZONA_ISRC2INT1MIX_INPUT_1_SOURCE 0xB60
  796. #define ARIZONA_ISRC2INT2MIX_INPUT_1_SOURCE 0xB68
  797. #define ARIZONA_ISRC2INT3MIX_INPUT_1_SOURCE 0xB70
  798. #define ARIZONA_ISRC2INT4MIX_INPUT_1_SOURCE 0xB78
  799. #define ARIZONA_ISRC3DEC1MIX_INPUT_1_SOURCE 0xB80
  800. #define ARIZONA_ISRC3DEC2MIX_INPUT_1_SOURCE 0xB88
  801. #define ARIZONA_ISRC3DEC3MIX_INPUT_1_SOURCE 0xB90
  802. #define ARIZONA_ISRC3DEC4MIX_INPUT_1_SOURCE 0xB98
  803. #define ARIZONA_ISRC3INT1MIX_INPUT_1_SOURCE 0xBA0
  804. #define ARIZONA_ISRC3INT2MIX_INPUT_1_SOURCE 0xBA8
  805. #define ARIZONA_ISRC3INT3MIX_INPUT_1_SOURCE 0xBB0
  806. #define ARIZONA_ISRC3INT4MIX_INPUT_1_SOURCE 0xBB8
  807. #define ARIZONA_GPIO1_CTRL 0xC00
  808. #define ARIZONA_GPIO2_CTRL 0xC01
  809. #define ARIZONA_GPIO3_CTRL 0xC02
  810. #define ARIZONA_GPIO4_CTRL 0xC03
  811. #define ARIZONA_GPIO5_CTRL 0xC04
  812. #define ARIZONA_IRQ_CTRL_1 0xC0F
  813. #define ARIZONA_GPIO_DEBOUNCE_CONFIG 0xC10
  814. #define ARIZONA_MISC_PAD_CTRL_1 0xC20
  815. #define ARIZONA_MISC_PAD_CTRL_2 0xC21
  816. #define ARIZONA_MISC_PAD_CTRL_3 0xC22
  817. #define ARIZONA_MISC_PAD_CTRL_4 0xC23
  818. #define ARIZONA_MISC_PAD_CTRL_5 0xC24
  819. #define ARIZONA_MISC_PAD_CTRL_6 0xC25
  820. #define ARIZONA_MISC_PAD_CTRL_7 0xC30
  821. #define ARIZONA_MISC_PAD_CTRL_8 0xC31
  822. #define ARIZONA_MISC_PAD_CTRL_9 0xC32
  823. #define ARIZONA_MISC_PAD_CTRL_10 0xC33
  824. #define ARIZONA_MISC_PAD_CTRL_11 0xC34
  825. #define ARIZONA_MISC_PAD_CTRL_12 0xC35
  826. #define ARIZONA_MISC_PAD_CTRL_13 0xC36
  827. #define ARIZONA_MISC_PAD_CTRL_14 0xC37
  828. #define ARIZONA_MISC_PAD_CTRL_15 0xC38
  829. #define ARIZONA_MISC_PAD_CTRL_16 0xC39
  830. #define ARIZONA_MISC_PAD_CTRL_17 0xC3A
  831. #define ARIZONA_MISC_PAD_CTRL_18 0xC3B
  832. #define ARIZONA_INTERRUPT_STATUS_1 0xD00
  833. #define ARIZONA_INTERRUPT_STATUS_2 0xD01
  834. #define ARIZONA_INTERRUPT_STATUS_3 0xD02
  835. #define ARIZONA_INTERRUPT_STATUS_4 0xD03
  836. #define ARIZONA_INTERRUPT_STATUS_5 0xD04
  837. #define ARIZONA_INTERRUPT_STATUS_1_MASK 0xD08
  838. #define ARIZONA_INTERRUPT_STATUS_2_MASK 0xD09
  839. #define ARIZONA_INTERRUPT_STATUS_3_MASK 0xD0A
  840. #define ARIZONA_INTERRUPT_STATUS_4_MASK 0xD0B
  841. #define ARIZONA_INTERRUPT_STATUS_5_MASK 0xD0C
  842. #define ARIZONA_INTERRUPT_CONTROL 0xD0F
  843. #define ARIZONA_IRQ2_STATUS_1 0xD10
  844. #define ARIZONA_IRQ2_STATUS_2 0xD11
  845. #define ARIZONA_IRQ2_STATUS_3 0xD12
  846. #define ARIZONA_IRQ2_STATUS_4 0xD13
  847. #define ARIZONA_IRQ2_STATUS_5 0xD14
  848. #define ARIZONA_IRQ2_STATUS_1_MASK 0xD18
  849. #define ARIZONA_IRQ2_STATUS_2_MASK 0xD19
  850. #define ARIZONA_IRQ2_STATUS_3_MASK 0xD1A
  851. #define ARIZONA_IRQ2_STATUS_4_MASK 0xD1B
  852. #define ARIZONA_IRQ2_STATUS_5_MASK 0xD1C
  853. #define ARIZONA_IRQ2_CONTROL 0xD1F
  854. #define ARIZONA_INTERRUPT_RAW_STATUS_2 0xD20
  855. #define ARIZONA_INTERRUPT_RAW_STATUS_3 0xD21
  856. #define ARIZONA_INTERRUPT_RAW_STATUS_4 0xD22
  857. #define ARIZONA_INTERRUPT_RAW_STATUS_5 0xD23
  858. #define ARIZONA_INTERRUPT_RAW_STATUS_6 0xD24
  859. #define ARIZONA_INTERRUPT_RAW_STATUS_7 0xD25
  860. #define ARIZONA_INTERRUPT_RAW_STATUS_8 0xD26
  861. #define ARIZONA_IRQ_PIN_STATUS 0xD40
  862. #define ARIZONA_ADSP2_IRQ0 0xD41
  863. #define ARIZONA_AOD_WKUP_AND_TRIG 0xD50
  864. #define ARIZONA_AOD_IRQ1 0xD51
  865. #define ARIZONA_AOD_IRQ2 0xD52
  866. #define ARIZONA_AOD_IRQ_MASK_IRQ1 0xD53
  867. #define ARIZONA_AOD_IRQ_MASK_IRQ2 0xD54
  868. #define ARIZONA_AOD_IRQ_RAW_STATUS 0xD55
  869. #define ARIZONA_JACK_DETECT_DEBOUNCE 0xD56
  870. #define ARIZONA_FX_CTRL1 0xE00
  871. #define ARIZONA_FX_CTRL2 0xE01
  872. #define ARIZONA_EQ1_1 0xE10
  873. #define ARIZONA_EQ1_2 0xE11
  874. #define ARIZONA_EQ1_3 0xE12
  875. #define ARIZONA_EQ1_4 0xE13
  876. #define ARIZONA_EQ1_5 0xE14
  877. #define ARIZONA_EQ1_6 0xE15
  878. #define ARIZONA_EQ1_7 0xE16
  879. #define ARIZONA_EQ1_8 0xE17
  880. #define ARIZONA_EQ1_9 0xE18
  881. #define ARIZONA_EQ1_10 0xE19
  882. #define ARIZONA_EQ1_11 0xE1A
  883. #define ARIZONA_EQ1_12 0xE1B
  884. #define ARIZONA_EQ1_13 0xE1C
  885. #define ARIZONA_EQ1_14 0xE1D
  886. #define ARIZONA_EQ1_15 0xE1E
  887. #define ARIZONA_EQ1_16 0xE1F
  888. #define ARIZONA_EQ1_17 0xE20
  889. #define ARIZONA_EQ1_18 0xE21
  890. #define ARIZONA_EQ1_19 0xE22
  891. #define ARIZONA_EQ1_20 0xE23
  892. #define ARIZONA_EQ1_21 0xE24
  893. #define ARIZONA_EQ2_1 0xE26
  894. #define ARIZONA_EQ2_2 0xE27
  895. #define ARIZONA_EQ2_3 0xE28
  896. #define ARIZONA_EQ2_4 0xE29
  897. #define ARIZONA_EQ2_5 0xE2A
  898. #define ARIZONA_EQ2_6 0xE2B
  899. #define ARIZONA_EQ2_7 0xE2C
  900. #define ARIZONA_EQ2_8 0xE2D
  901. #define ARIZONA_EQ2_9 0xE2E
  902. #define ARIZONA_EQ2_10 0xE2F
  903. #define ARIZONA_EQ2_11 0xE30
  904. #define ARIZONA_EQ2_12 0xE31
  905. #define ARIZONA_EQ2_13 0xE32
  906. #define ARIZONA_EQ2_14 0xE33
  907. #define ARIZONA_EQ2_15 0xE34
  908. #define ARIZONA_EQ2_16 0xE35
  909. #define ARIZONA_EQ2_17 0xE36
  910. #define ARIZONA_EQ2_18 0xE37
  911. #define ARIZONA_EQ2_19 0xE38
  912. #define ARIZONA_EQ2_20 0xE39
  913. #define ARIZONA_EQ2_21 0xE3A
  914. #define ARIZONA_EQ3_1 0xE3C
  915. #define ARIZONA_EQ3_2 0xE3D
  916. #define ARIZONA_EQ3_3 0xE3E
  917. #define ARIZONA_EQ3_4 0xE3F
  918. #define ARIZONA_EQ3_5 0xE40
  919. #define ARIZONA_EQ3_6 0xE41
  920. #define ARIZONA_EQ3_7 0xE42
  921. #define ARIZONA_EQ3_8 0xE43
  922. #define ARIZONA_EQ3_9 0xE44
  923. #define ARIZONA_EQ3_10 0xE45
  924. #define ARIZONA_EQ3_11 0xE46
  925. #define ARIZONA_EQ3_12 0xE47
  926. #define ARIZONA_EQ3_13 0xE48
  927. #define ARIZONA_EQ3_14 0xE49
  928. #define ARIZONA_EQ3_15 0xE4A
  929. #define ARIZONA_EQ3_16 0xE4B
  930. #define ARIZONA_EQ3_17 0xE4C
  931. #define ARIZONA_EQ3_18 0xE4D
  932. #define ARIZONA_EQ3_19 0xE4E
  933. #define ARIZONA_EQ3_20 0xE4F
  934. #define ARIZONA_EQ3_21 0xE50
  935. #define ARIZONA_EQ4_1 0xE52
  936. #define ARIZONA_EQ4_2 0xE53
  937. #define ARIZONA_EQ4_3 0xE54
  938. #define ARIZONA_EQ4_4 0xE55
  939. #define ARIZONA_EQ4_5 0xE56
  940. #define ARIZONA_EQ4_6 0xE57
  941. #define ARIZONA_EQ4_7 0xE58
  942. #define ARIZONA_EQ4_8 0xE59
  943. #define ARIZONA_EQ4_9 0xE5A
  944. #define ARIZONA_EQ4_10 0xE5B
  945. #define ARIZONA_EQ4_11 0xE5C
  946. #define ARIZONA_EQ4_12 0xE5D
  947. #define ARIZONA_EQ4_13 0xE5E
  948. #define ARIZONA_EQ4_14 0xE5F
  949. #define ARIZONA_EQ4_15 0xE60
  950. #define ARIZONA_EQ4_16 0xE61
  951. #define ARIZONA_EQ4_17 0xE62
  952. #define ARIZONA_EQ4_18 0xE63
  953. #define ARIZONA_EQ4_19 0xE64
  954. #define ARIZONA_EQ4_20 0xE65
  955. #define ARIZONA_EQ4_21 0xE66
  956. #define ARIZONA_DRC1_CTRL1 0xE80
  957. #define ARIZONA_DRC1_CTRL2 0xE81
  958. #define ARIZONA_DRC1_CTRL3 0xE82
  959. #define ARIZONA_DRC1_CTRL4 0xE83
  960. #define ARIZONA_DRC1_CTRL5 0xE84
  961. #define ARIZONA_DRC2_CTRL1 0xE89
  962. #define ARIZONA_DRC2_CTRL2 0xE8A
  963. #define ARIZONA_DRC2_CTRL3 0xE8B
  964. #define ARIZONA_DRC2_CTRL4 0xE8C
  965. #define ARIZONA_DRC2_CTRL5 0xE8D
  966. #define ARIZONA_HPLPF1_1 0xEC0
  967. #define ARIZONA_HPLPF1_2 0xEC1
  968. #define ARIZONA_HPLPF2_1 0xEC4
  969. #define ARIZONA_HPLPF2_2 0xEC5
  970. #define ARIZONA_HPLPF3_1 0xEC8
  971. #define ARIZONA_HPLPF3_2 0xEC9
  972. #define ARIZONA_HPLPF4_1 0xECC
  973. #define ARIZONA_HPLPF4_2 0xECD
  974. #define ARIZONA_ASRC_ENABLE 0xEE0
  975. #define ARIZONA_ASRC_STATUS 0xEE1
  976. #define ARIZONA_ASRC_RATE1 0xEE2
  977. #define ARIZONA_ASRC_RATE2 0xEE3
  978. #define ARIZONA_ISRC_1_CTRL_1 0xEF0
  979. #define ARIZONA_ISRC_1_CTRL_2 0xEF1
  980. #define ARIZONA_ISRC_1_CTRL_3 0xEF2
  981. #define ARIZONA_ISRC_2_CTRL_1 0xEF3
  982. #define ARIZONA_ISRC_2_CTRL_2 0xEF4
  983. #define ARIZONA_ISRC_2_CTRL_3 0xEF5
  984. #define ARIZONA_ISRC_3_CTRL_1 0xEF6
  985. #define ARIZONA_ISRC_3_CTRL_2 0xEF7
  986. #define ARIZONA_ISRC_3_CTRL_3 0xEF8
  987. #define ARIZONA_CLOCK_CONTROL 0xF00
  988. #define ARIZONA_ANC_SRC 0xF01
  989. #define ARIZONA_DSP_STATUS 0xF02
  990. #define ARIZONA_DSP1_CONTROL_1 0x1100
  991. #define ARIZONA_DSP1_CLOCKING_1 0x1101
  992. #define ARIZONA_DSP1_STATUS_1 0x1104
  993. #define ARIZONA_DSP1_STATUS_2 0x1105
  994. #define ARIZONA_DSP1_STATUS_3 0x1106
  995. #define ARIZONA_DSP1_SCRATCH_0 0x1140
  996. #define ARIZONA_DSP1_SCRATCH_1 0x1141
  997. #define ARIZONA_DSP1_SCRATCH_2 0x1142
  998. #define ARIZONA_DSP1_SCRATCH_3 0x1143
  999. #define ARIZONA_DSP2_CONTROL_1 0x1200
  1000. #define ARIZONA_DSP2_CLOCKING_1 0x1201
  1001. #define ARIZONA_DSP2_STATUS_1 0x1204
  1002. #define ARIZONA_DSP2_STATUS_2 0x1205
  1003. #define ARIZONA_DSP2_STATUS_3 0x1206
  1004. #define ARIZONA_DSP2_SCRATCH_0 0x1240
  1005. #define ARIZONA_DSP2_SCRATCH_1 0x1241
  1006. #define ARIZONA_DSP2_SCRATCH_2 0x1242
  1007. #define ARIZONA_DSP2_SCRATCH_3 0x1243
  1008. #define ARIZONA_DSP3_CONTROL_1 0x1300
  1009. #define ARIZONA_DSP3_CLOCKING_1 0x1301
  1010. #define ARIZONA_DSP3_STATUS_1 0x1304
  1011. #define ARIZONA_DSP3_STATUS_2 0x1305
  1012. #define ARIZONA_DSP3_STATUS_3 0x1306
  1013. #define ARIZONA_DSP3_SCRATCH_0 0x1340
  1014. #define ARIZONA_DSP3_SCRATCH_1 0x1341
  1015. #define ARIZONA_DSP3_SCRATCH_2 0x1342
  1016. #define ARIZONA_DSP3_SCRATCH_3 0x1343
  1017. #define ARIZONA_DSP4_CONTROL_1 0x1400
  1018. #define ARIZONA_DSP4_CLOCKING_1 0x1401
  1019. #define ARIZONA_DSP4_STATUS_1 0x1404
  1020. #define ARIZONA_DSP4_STATUS_2 0x1405
  1021. #define ARIZONA_DSP4_STATUS_3 0x1406
  1022. #define ARIZONA_DSP4_SCRATCH_0 0x1440
  1023. #define ARIZONA_DSP4_SCRATCH_1 0x1441
  1024. #define ARIZONA_DSP4_SCRATCH_2 0x1442
  1025. #define ARIZONA_DSP4_SCRATCH_3 0x1443
  1026. /*
  1027. * Field Definitions.
  1028. */
  1029. /*
  1030. * R0 (0x00) - software reset
  1031. */
  1032. #define ARIZONA_SW_RST_DEV_ID1_MASK 0xFFFF /* SW_RST_DEV_ID1 - [15:0] */
  1033. #define ARIZONA_SW_RST_DEV_ID1_SHIFT 0 /* SW_RST_DEV_ID1 - [15:0] */
  1034. #define ARIZONA_SW_RST_DEV_ID1_WIDTH 16 /* SW_RST_DEV_ID1 - [15:0] */
  1035. /*
  1036. * R1 (0x01) - Device Revision
  1037. */
  1038. #define ARIZONA_DEVICE_REVISION_MASK 0x00FF /* DEVICE_REVISION - [7:0] */
  1039. #define ARIZONA_DEVICE_REVISION_SHIFT 0 /* DEVICE_REVISION - [7:0] */
  1040. #define ARIZONA_DEVICE_REVISION_WIDTH 8 /* DEVICE_REVISION - [7:0] */
  1041. /*
  1042. * R8 (0x08) - Ctrl IF SPI CFG 1
  1043. */
  1044. #define ARIZONA_SPI_CFG 0x0010 /* SPI_CFG */
  1045. #define ARIZONA_SPI_CFG_MASK 0x0010 /* SPI_CFG */
  1046. #define ARIZONA_SPI_CFG_SHIFT 4 /* SPI_CFG */
  1047. #define ARIZONA_SPI_CFG_WIDTH 1 /* SPI_CFG */
  1048. #define ARIZONA_SPI_4WIRE 0x0008 /* SPI_4WIRE */
  1049. #define ARIZONA_SPI_4WIRE_MASK 0x0008 /* SPI_4WIRE */
  1050. #define ARIZONA_SPI_4WIRE_SHIFT 3 /* SPI_4WIRE */
  1051. #define ARIZONA_SPI_4WIRE_WIDTH 1 /* SPI_4WIRE */
  1052. #define ARIZONA_SPI_AUTO_INC_MASK 0x0003 /* SPI_AUTO_INC - [1:0] */
  1053. #define ARIZONA_SPI_AUTO_INC_SHIFT 0 /* SPI_AUTO_INC - [1:0] */
  1054. #define ARIZONA_SPI_AUTO_INC_WIDTH 2 /* SPI_AUTO_INC - [1:0] */
  1055. /*
  1056. * R9 (0x09) - Ctrl IF I2C1 CFG 1
  1057. */
  1058. #define ARIZONA_I2C1_AUTO_INC_MASK 0x0003 /* I2C1_AUTO_INC - [1:0] */
  1059. #define ARIZONA_I2C1_AUTO_INC_SHIFT 0 /* I2C1_AUTO_INC - [1:0] */
  1060. #define ARIZONA_I2C1_AUTO_INC_WIDTH 2 /* I2C1_AUTO_INC - [1:0] */
  1061. /*
  1062. * R13 (0x0D) - Ctrl IF Status 1
  1063. */
  1064. #define ARIZONA_I2C1_BUSY 0x0020 /* I2C1_BUSY */
  1065. #define ARIZONA_I2C1_BUSY_MASK 0x0020 /* I2C1_BUSY */
  1066. #define ARIZONA_I2C1_BUSY_SHIFT 5 /* I2C1_BUSY */
  1067. #define ARIZONA_I2C1_BUSY_WIDTH 1 /* I2C1_BUSY */
  1068. #define ARIZONA_SPI_BUSY 0x0010 /* SPI_BUSY */
  1069. #define ARIZONA_SPI_BUSY_MASK 0x0010 /* SPI_BUSY */
  1070. #define ARIZONA_SPI_BUSY_SHIFT 4 /* SPI_BUSY */
  1071. #define ARIZONA_SPI_BUSY_WIDTH 1 /* SPI_BUSY */
  1072. /*
  1073. * R22 (0x16) - Write Sequencer Ctrl 0
  1074. */
  1075. #define ARIZONA_WSEQ_ABORT 0x0800 /* WSEQ_ABORT */
  1076. #define ARIZONA_WSEQ_ABORT_MASK 0x0800 /* WSEQ_ABORT */
  1077. #define ARIZONA_WSEQ_ABORT_SHIFT 11 /* WSEQ_ABORT */
  1078. #define ARIZONA_WSEQ_ABORT_WIDTH 1 /* WSEQ_ABORT */
  1079. #define ARIZONA_WSEQ_START 0x0400 /* WSEQ_START */
  1080. #define ARIZONA_WSEQ_START_MASK 0x0400 /* WSEQ_START */
  1081. #define ARIZONA_WSEQ_START_SHIFT 10 /* WSEQ_START */
  1082. #define ARIZONA_WSEQ_START_WIDTH 1 /* WSEQ_START */
  1083. #define ARIZONA_WSEQ_ENA 0x0200 /* WSEQ_ENA */
  1084. #define ARIZONA_WSEQ_ENA_MASK 0x0200 /* WSEQ_ENA */
  1085. #define ARIZONA_WSEQ_ENA_SHIFT 9 /* WSEQ_ENA */
  1086. #define ARIZONA_WSEQ_ENA_WIDTH 1 /* WSEQ_ENA */
  1087. #define ARIZONA_WSEQ_START_INDEX_MASK 0x01FF /* WSEQ_START_INDEX - [8:0] */
  1088. #define ARIZONA_WSEQ_START_INDEX_SHIFT 0 /* WSEQ_START_INDEX - [8:0] */
  1089. #define ARIZONA_WSEQ_START_INDEX_WIDTH 9 /* WSEQ_START_INDEX - [8:0] */
  1090. /*
  1091. * R23 (0x17) - Write Sequencer Ctrl 1
  1092. */
  1093. #define ARIZONA_WSEQ_BUSY 0x0200 /* WSEQ_BUSY */
  1094. #define ARIZONA_WSEQ_BUSY_MASK 0x0200 /* WSEQ_BUSY */
  1095. #define ARIZONA_WSEQ_BUSY_SHIFT 9 /* WSEQ_BUSY */
  1096. #define ARIZONA_WSEQ_BUSY_WIDTH 1 /* WSEQ_BUSY */
  1097. #define ARIZONA_WSEQ_CURRENT_INDEX_MASK 0x01FF /* WSEQ_CURRENT_INDEX - [8:0] */
  1098. #define ARIZONA_WSEQ_CURRENT_INDEX_SHIFT 0 /* WSEQ_CURRENT_INDEX - [8:0] */
  1099. #define ARIZONA_WSEQ_CURRENT_INDEX_WIDTH 9 /* WSEQ_CURRENT_INDEX - [8:0] */
  1100. /*
  1101. * R24 (0x18) - Write Sequencer Ctrl 2
  1102. */
  1103. #define ARIZONA_LOAD_DEFAULTS 0x0002 /* LOAD_DEFAULTS */
  1104. #define ARIZONA_LOAD_DEFAULTS_MASK 0x0002 /* LOAD_DEFAULTS */
  1105. #define ARIZONA_LOAD_DEFAULTS_SHIFT 1 /* LOAD_DEFAULTS */
  1106. #define ARIZONA_LOAD_DEFAULTS_WIDTH 1 /* LOAD_DEFAULTS */
  1107. #define ARIZONA_WSEQ_LOAD_MEM 0x0001 /* WSEQ_LOAD_MEM */
  1108. #define ARIZONA_WSEQ_LOAD_MEM_MASK 0x0001 /* WSEQ_LOAD_MEM */
  1109. #define ARIZONA_WSEQ_LOAD_MEM_SHIFT 0 /* WSEQ_LOAD_MEM */
  1110. #define ARIZONA_WSEQ_LOAD_MEM_WIDTH 1 /* WSEQ_LOAD_MEM */
  1111. /*
  1112. * R26 (0x1A) - Write Sequencer PROM
  1113. */
  1114. #define ARIZONA_WSEQ_OTP_WRITE 0x0001 /* WSEQ_OTP_WRITE */
  1115. #define ARIZONA_WSEQ_OTP_WRITE_MASK 0x0001 /* WSEQ_OTP_WRITE */
  1116. #define ARIZONA_WSEQ_OTP_WRITE_SHIFT 0 /* WSEQ_OTP_WRITE */
  1117. #define ARIZONA_WSEQ_OTP_WRITE_WIDTH 1 /* WSEQ_OTP_WRITE */
  1118. /*
  1119. * R32 (0x20) - Tone Generator 1
  1120. */
  1121. #define ARIZONA_TONE_RATE_MASK 0x7800 /* TONE_RATE - [14:11] */
  1122. #define ARIZONA_TONE_RATE_SHIFT 11 /* TONE_RATE - [14:11] */
  1123. #define ARIZONA_TONE_RATE_WIDTH 4 /* TONE_RATE - [14:11] */
  1124. #define ARIZONA_TONE_OFFSET_MASK 0x0300 /* TONE_OFFSET - [9:8] */
  1125. #define ARIZONA_TONE_OFFSET_SHIFT 8 /* TONE_OFFSET - [9:8] */
  1126. #define ARIZONA_TONE_OFFSET_WIDTH 2 /* TONE_OFFSET - [9:8] */
  1127. #define ARIZONA_TONE2_OVD 0x0020 /* TONE2_OVD */
  1128. #define ARIZONA_TONE2_OVD_MASK 0x0020 /* TONE2_OVD */
  1129. #define ARIZONA_TONE2_OVD_SHIFT 5 /* TONE2_OVD */
  1130. #define ARIZONA_TONE2_OVD_WIDTH 1 /* TONE2_OVD */
  1131. #define ARIZONA_TONE1_OVD 0x0010 /* TONE1_OVD */
  1132. #define ARIZONA_TONE1_OVD_MASK 0x0010 /* TONE1_OVD */
  1133. #define ARIZONA_TONE1_OVD_SHIFT 4 /* TONE1_OVD */
  1134. #define ARIZONA_TONE1_OVD_WIDTH 1 /* TONE1_OVD */
  1135. #define ARIZONA_TONE2_ENA 0x0002 /* TONE2_ENA */
  1136. #define ARIZONA_TONE2_ENA_MASK 0x0002 /* TONE2_ENA */
  1137. #define ARIZONA_TONE2_ENA_SHIFT 1 /* TONE2_ENA */
  1138. #define ARIZONA_TONE2_ENA_WIDTH 1 /* TONE2_ENA */
  1139. #define ARIZONA_TONE1_ENA 0x0001 /* TONE1_ENA */
  1140. #define ARIZONA_TONE1_ENA_MASK 0x0001 /* TONE1_ENA */
  1141. #define ARIZONA_TONE1_ENA_SHIFT 0 /* TONE1_ENA */
  1142. #define ARIZONA_TONE1_ENA_WIDTH 1 /* TONE1_ENA */
  1143. /*
  1144. * R33 (0x21) - Tone Generator 2
  1145. */
  1146. #define ARIZONA_TONE1_LVL_0_MASK 0xFFFF /* TONE1_LVL - [15:0] */
  1147. #define ARIZONA_TONE1_LVL_0_SHIFT 0 /* TONE1_LVL - [15:0] */
  1148. #define ARIZONA_TONE1_LVL_0_WIDTH 16 /* TONE1_LVL - [15:0] */
  1149. /*
  1150. * R34 (0x22) - Tone Generator 3
  1151. */
  1152. #define ARIZONA_TONE1_LVL_MASK 0x00FF /* TONE1_LVL - [7:0] */
  1153. #define ARIZONA_TONE1_LVL_SHIFT 0 /* TONE1_LVL - [7:0] */
  1154. #define ARIZONA_TONE1_LVL_WIDTH 8 /* TONE1_LVL - [7:0] */
  1155. /*
  1156. * R35 (0x23) - Tone Generator 4
  1157. */
  1158. #define ARIZONA_TONE2_LVL_0_MASK 0xFFFF /* TONE2_LVL - [15:0] */
  1159. #define ARIZONA_TONE2_LVL_0_SHIFT 0 /* TONE2_LVL - [15:0] */
  1160. #define ARIZONA_TONE2_LVL_0_WIDTH 16 /* TONE2_LVL - [15:0] */
  1161. /*
  1162. * R36 (0x24) - Tone Generator 5
  1163. */
  1164. #define ARIZONA_TONE2_LVL_MASK 0x00FF /* TONE2_LVL - [7:0] */
  1165. #define ARIZONA_TONE2_LVL_SHIFT 0 /* TONE2_LVL - [7:0] */
  1166. #define ARIZONA_TONE2_LVL_WIDTH 8 /* TONE2_LVL - [7:0] */
  1167. /*
  1168. * R48 (0x30) - PWM Drive 1
  1169. */
  1170. #define ARIZONA_PWM_RATE_MASK 0x7800 /* PWM_RATE - [14:11] */
  1171. #define ARIZONA_PWM_RATE_SHIFT 11 /* PWM_RATE - [14:11] */
  1172. #define ARIZONA_PWM_RATE_WIDTH 4 /* PWM_RATE - [14:11] */
  1173. #define ARIZONA_PWM_CLK_SEL_MASK 0x0700 /* PWM_CLK_SEL - [10:8] */
  1174. #define ARIZONA_PWM_CLK_SEL_SHIFT 8 /* PWM_CLK_SEL - [10:8] */
  1175. #define ARIZONA_PWM_CLK_SEL_WIDTH 3 /* PWM_CLK_SEL - [10:8] */
  1176. #define ARIZONA_PWM2_OVD 0x0020 /* PWM2_OVD */
  1177. #define ARIZONA_PWM2_OVD_MASK 0x0020 /* PWM2_OVD */
  1178. #define ARIZONA_PWM2_OVD_SHIFT 5 /* PWM2_OVD */
  1179. #define ARIZONA_PWM2_OVD_WIDTH 1 /* PWM2_OVD */
  1180. #define ARIZONA_PWM1_OVD 0x0010 /* PWM1_OVD */
  1181. #define ARIZONA_PWM1_OVD_MASK 0x0010 /* PWM1_OVD */
  1182. #define ARIZONA_PWM1_OVD_SHIFT 4 /* PWM1_OVD */
  1183. #define ARIZONA_PWM1_OVD_WIDTH 1 /* PWM1_OVD */
  1184. #define ARIZONA_PWM2_ENA 0x0002 /* PWM2_ENA */
  1185. #define ARIZONA_PWM2_ENA_MASK 0x0002 /* PWM2_ENA */
  1186. #define ARIZONA_PWM2_ENA_SHIFT 1 /* PWM2_ENA */
  1187. #define ARIZONA_PWM2_ENA_WIDTH 1 /* PWM2_ENA */
  1188. #define ARIZONA_PWM1_ENA 0x0001 /* PWM1_ENA */
  1189. #define ARIZONA_PWM1_ENA_MASK 0x0001 /* PWM1_ENA */
  1190. #define ARIZONA_PWM1_ENA_SHIFT 0 /* PWM1_ENA */
  1191. #define ARIZONA_PWM1_ENA_WIDTH 1 /* PWM1_ENA */
  1192. /*
  1193. * R49 (0x31) - PWM Drive 2
  1194. */
  1195. #define ARIZONA_PWM1_LVL_MASK 0x03FF /* PWM1_LVL - [9:0] */
  1196. #define ARIZONA_PWM1_LVL_SHIFT 0 /* PWM1_LVL - [9:0] */
  1197. #define ARIZONA_PWM1_LVL_WIDTH 10 /* PWM1_LVL - [9:0] */
  1198. /*
  1199. * R50 (0x32) - PWM Drive 3
  1200. */
  1201. #define ARIZONA_PWM2_LVL_MASK 0x03FF /* PWM2_LVL - [9:0] */
  1202. #define ARIZONA_PWM2_LVL_SHIFT 0 /* PWM2_LVL - [9:0] */
  1203. #define ARIZONA_PWM2_LVL_WIDTH 10 /* PWM2_LVL - [9:0] */
  1204. /*
  1205. * R64 (0x40) - Wake control
  1206. */
  1207. #define ARIZONA_WKUP_MICD_CLAMP_FALL 0x0080 /* WKUP_MICD_CLAMP_FALL */
  1208. #define ARIZONA_WKUP_MICD_CLAMP_FALL_MASK 0x0080 /* WKUP_MICD_CLAMP_FALL */
  1209. #define ARIZONA_WKUP_MICD_CLAMP_FALL_SHIFT 7 /* WKUP_MICD_CLAMP_FALL */
  1210. #define ARIZONA_WKUP_MICD_CLAMP_FALL_WIDTH 1 /* WKUP_MICD_CLAMP_FALL */
  1211. #define ARIZONA_WKUP_MICD_CLAMP_RISE 0x0040 /* WKUP_MICD_CLAMP_RISE */
  1212. #define ARIZONA_WKUP_MICD_CLAMP_RISE_MASK 0x0040 /* WKUP_MICD_CLAMP_RISE */
  1213. #define ARIZONA_WKUP_MICD_CLAMP_RISE_SHIFT 6 /* WKUP_MICD_CLAMP_RISE */
  1214. #define ARIZONA_WKUP_MICD_CLAMP_RISE_WIDTH 1 /* WKUP_MICD_CLAMP_RISE */
  1215. #define ARIZONA_WKUP_GP5_FALL 0x0020 /* WKUP_GP5_FALL */
  1216. #define ARIZONA_WKUP_GP5_FALL_MASK 0x0020 /* WKUP_GP5_FALL */
  1217. #define ARIZONA_WKUP_GP5_FALL_SHIFT 5 /* WKUP_GP5_FALL */
  1218. #define ARIZONA_WKUP_GP5_FALL_WIDTH 1 /* WKUP_GP5_FALL */
  1219. #define ARIZONA_WKUP_GP5_RISE 0x0010 /* WKUP_GP5_RISE */
  1220. #define ARIZONA_WKUP_GP5_RISE_MASK 0x0010 /* WKUP_GP5_RISE */
  1221. #define ARIZONA_WKUP_GP5_RISE_SHIFT 4 /* WKUP_GP5_RISE */
  1222. #define ARIZONA_WKUP_GP5_RISE_WIDTH 1 /* WKUP_GP5_RISE */
  1223. #define ARIZONA_WKUP_JD1_FALL 0x0008 /* WKUP_JD1_FALL */
  1224. #define ARIZONA_WKUP_JD1_FALL_MASK 0x0008 /* WKUP_JD1_FALL */
  1225. #define ARIZONA_WKUP_JD1_FALL_SHIFT 3 /* WKUP_JD1_FALL */
  1226. #define ARIZONA_WKUP_JD1_FALL_WIDTH 1 /* WKUP_JD1_FALL */
  1227. #define ARIZONA_WKUP_JD1_RISE 0x0004 /* WKUP_JD1_RISE */
  1228. #define ARIZONA_WKUP_JD1_RISE_MASK 0x0004 /* WKUP_JD1_RISE */
  1229. #define ARIZONA_WKUP_JD1_RISE_SHIFT 2 /* WKUP_JD1_RISE */
  1230. #define ARIZONA_WKUP_JD1_RISE_WIDTH 1 /* WKUP_JD1_RISE */
  1231. #define ARIZONA_WKUP_JD2_FALL 0x0002 /* WKUP_JD2_FALL */
  1232. #define ARIZONA_WKUP_JD2_FALL_MASK 0x0002 /* WKUP_JD2_FALL */
  1233. #define ARIZONA_WKUP_JD2_FALL_SHIFT 1 /* WKUP_JD2_FALL */
  1234. #define ARIZONA_WKUP_JD2_FALL_WIDTH 1 /* WKUP_JD2_FALL */
  1235. #define ARIZONA_WKUP_JD2_RISE 0x0001 /* WKUP_JD2_RISE */
  1236. #define ARIZONA_WKUP_JD2_RISE_MASK 0x0001 /* WKUP_JD2_RISE */
  1237. #define ARIZONA_WKUP_JD2_RISE_SHIFT 0 /* WKUP_JD2_RISE */
  1238. #define ARIZONA_WKUP_JD2_RISE_WIDTH 1 /* WKUP_JD2_RISE */
  1239. /*
  1240. * R65 (0x41) - Sequence control
  1241. */
  1242. #define ARIZONA_WSEQ_ENA_GP5_FALL 0x0020 /* WSEQ_ENA_GP5_FALL */
  1243. #define ARIZONA_WSEQ_ENA_GP5_FALL_MASK 0x0020 /* WSEQ_ENA_GP5_FALL */
  1244. #define ARIZONA_WSEQ_ENA_GP5_FALL_SHIFT 5 /* WSEQ_ENA_GP5_FALL */
  1245. #define ARIZONA_WSEQ_ENA_GP5_FALL_WIDTH 1 /* WSEQ_ENA_GP5_FALL */
  1246. #define ARIZONA_WSEQ_ENA_GP5_RISE 0x0010 /* WSEQ_ENA_GP5_RISE */
  1247. #define ARIZONA_WSEQ_ENA_GP5_RISE_MASK 0x0010 /* WSEQ_ENA_GP5_RISE */
  1248. #define ARIZONA_WSEQ_ENA_GP5_RISE_SHIFT 4 /* WSEQ_ENA_GP5_RISE */
  1249. #define ARIZONA_WSEQ_ENA_GP5_RISE_WIDTH 1 /* WSEQ_ENA_GP5_RISE */
  1250. #define ARIZONA_WSEQ_ENA_JD1_FALL 0x0008 /* WSEQ_ENA_JD1_FALL */
  1251. #define ARIZONA_WSEQ_ENA_JD1_FALL_MASK 0x0008 /* WSEQ_ENA_JD1_FALL */
  1252. #define ARIZONA_WSEQ_ENA_JD1_FALL_SHIFT 3 /* WSEQ_ENA_JD1_FALL */
  1253. #define ARIZONA_WSEQ_ENA_JD1_FALL_WIDTH 1 /* WSEQ_ENA_JD1_FALL */
  1254. #define ARIZONA_WSEQ_ENA_JD1_RISE 0x0004 /* WSEQ_ENA_JD1_RISE */
  1255. #define ARIZONA_WSEQ_ENA_JD1_RISE_MASK 0x0004 /* WSEQ_ENA_JD1_RISE */
  1256. #define ARIZONA_WSEQ_ENA_JD1_RISE_SHIFT 2 /* WSEQ_ENA_JD1_RISE */
  1257. #define ARIZONA_WSEQ_ENA_JD1_RISE_WIDTH 1 /* WSEQ_ENA_JD1_RISE */
  1258. #define ARIZONA_WSEQ_ENA_JD2_FALL 0x0002 /* WSEQ_ENA_JD2_FALL */
  1259. #define ARIZONA_WSEQ_ENA_JD2_FALL_MASK 0x0002 /* WSEQ_ENA_JD2_FALL */
  1260. #define ARIZONA_WSEQ_ENA_JD2_FALL_SHIFT 1 /* WSEQ_ENA_JD2_FALL */
  1261. #define ARIZONA_WSEQ_ENA_JD2_FALL_WIDTH 1 /* WSEQ_ENA_JD2_FALL */
  1262. #define ARIZONA_WSEQ_ENA_JD2_RISE 0x0001 /* WSEQ_ENA_JD2_RISE */
  1263. #define ARIZONA_WSEQ_ENA_JD2_RISE_MASK 0x0001 /* WSEQ_ENA_JD2_RISE */
  1264. #define ARIZONA_WSEQ_ENA_JD2_RISE_SHIFT 0 /* WSEQ_ENA_JD2_RISE */
  1265. #define ARIZONA_WSEQ_ENA_JD2_RISE_WIDTH 1 /* WSEQ_ENA_JD2_RISE */
  1266. /*
  1267. * R97 (0x61) - Sample Rate Sequence Select 1
  1268. */
  1269. #define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_A_SEQ_ADDR_MASK 0x01FF /* WSEQ_SAMPLE_RATE_DETECT_A_SEQ_ADDR - [8:0] */
  1270. #define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_A_SEQ_ADDR_SHIFT 0 /* WSEQ_SAMPLE_RATE_DETECT_A_SEQ_ADDR - [8:0] */
  1271. #define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_A_SEQ_ADDR_WIDTH 9 /* WSEQ_SAMPLE_RATE_DETECT_A_SEQ_ADDR - [8:0] */
  1272. /*
  1273. * R98 (0x62) - Sample Rate Sequence Select 2
  1274. */
  1275. #define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_B_SEQ_ADDR_MASK 0x01FF /* WSEQ_SAMPLE_RATE_DETECT_B_SEQ_ADDR - [8:0] */
  1276. #define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_B_SEQ_ADDR_SHIFT 0 /* WSEQ_SAMPLE_RATE_DETECT_B_SEQ_ADDR - [8:0] */
  1277. #define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_B_SEQ_ADDR_WIDTH 9 /* WSEQ_SAMPLE_RATE_DETECT_B_SEQ_ADDR - [8:0] */
  1278. /*
  1279. * R99 (0x63) - Sample Rate Sequence Select 3
  1280. */
  1281. #define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_C_SEQ_ADDR_MASK 0x01FF /* WSEQ_SAMPLE_RATE_DETECT_C_SEQ_ADDR - [8:0] */
  1282. #define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_C_SEQ_ADDR_SHIFT 0 /* WSEQ_SAMPLE_RATE_DETECT_C_SEQ_ADDR - [8:0] */
  1283. #define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_C_SEQ_ADDR_WIDTH 9 /* WSEQ_SAMPLE_RATE_DETECT_C_SEQ_ADDR - [8:0] */
  1284. /*
  1285. * R100 (0x64) - Sample Rate Sequence Select 4
  1286. */
  1287. #define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_D_SEQ_ADDR_MASK 0x01FF /* WSEQ_SAMPLE_RATE_DETECT_D_SEQ_ADDR - [8:0] */
  1288. #define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_D_SEQ_ADDR_SHIFT 0 /* WSEQ_SAMPLE_RATE_DETECT_D_SEQ_ADDR - [8:0] */
  1289. #define ARIZONA_WSEQ_SAMPLE_RATE_DETECT_D_SEQ_ADDR_WIDTH 9 /* WSEQ_SAMPLE_RATE_DETECT_D_SEQ_ADDR - [8:0] */
  1290. /*
  1291. * R104 (0x68) - Always On Triggers Sequence Select 1
  1292. */
  1293. #define ARIZONA_WSEQ_GP5_RISE_SEQ_ADDR_MASK 0x01FF /* WSEQ_GP5_RISE_SEQ_ADDR - [8:0] */
  1294. #define ARIZONA_WSEQ_GP5_RISE_SEQ_ADDR_SHIFT 0 /* WSEQ_GP5_RISE_SEQ_ADDR - [8:0] */
  1295. #define ARIZONA_WSEQ_GP5_RISE_SEQ_ADDR_WIDTH 9 /* WSEQ_GP5_RISE_SEQ_ADDR - [8:0] */
  1296. /*
  1297. * R105 (0x69) - Always On Triggers Sequence Select 2
  1298. */
  1299. #define ARIZONA_WSEQ_GP5_FALL_SEQ_ADDR_MASK 0x01FF /* WSEQ_GP5_FALL_SEQ_ADDR - [8:0] */
  1300. #define ARIZONA_WSEQ_GP5_FALL_SEQ_ADDR_SHIFT 0 /* WSEQ_GP5_FALL_SEQ_ADDR - [8:0] */
  1301. #define ARIZONA_WSEQ_GP5_FALL_SEQ_ADDR_WIDTH 9 /* WSEQ_GP5_FALL_SEQ_ADDR - [8:0] */
  1302. /*
  1303. * R106 (0x6A) - Always On Triggers Sequence Select 3
  1304. */
  1305. #define ARIZONA_WSEQ_JD1_RISE_SEQ_ADDR_MASK 0x01FF /* WSEQ_JD1_RISE_SEQ_ADDR - [8:0] */
  1306. #define ARIZONA_WSEQ_JD1_RISE_SEQ_ADDR_SHIFT 0 /* WSEQ_JD1_RISE_SEQ_ADDR - [8:0] */
  1307. #define ARIZONA_WSEQ_JD1_RISE_SEQ_ADDR_WIDTH 9 /* WSEQ_JD1_RISE_SEQ_ADDR - [8:0] */
  1308. /*
  1309. * R107 (0x6B) - Always On Triggers Sequence Select 4
  1310. */
  1311. #define ARIZONA_WSEQ_JD1_FALL_SEQ_ADDR_MASK 0x01FF /* WSEQ_JD1_FALL_SEQ_ADDR - [8:0] */
  1312. #define ARIZONA_WSEQ_JD1_FALL_SEQ_ADDR_SHIFT 0 /* WSEQ_JD1_FALL_SEQ_ADDR - [8:0] */
  1313. #define ARIZONA_WSEQ_JD1_FALL_SEQ_ADDR_WIDTH 9 /* WSEQ_JD1_FALL_SEQ_ADDR - [8:0] */
  1314. /*
  1315. * R108 (0x6C) - Always On Triggers Sequence Select 5
  1316. */
  1317. #define ARIZONA_WSEQ_JD2_RISE_SEQ_ADDR_MASK 0x01FF /* WSEQ_JD2_RISE_SEQ_ADDR - [8:0] */
  1318. #define ARIZONA_WSEQ_JD2_RISE_SEQ_ADDR_SHIFT 0 /* WSEQ_JD2_RISE_SEQ_ADDR - [8:0] */
  1319. #define ARIZONA_WSEQ_JD2_RISE_SEQ_ADDR_WIDTH 9 /* WSEQ_JD2_RISE_SEQ_ADDR - [8:0] */
  1320. /*
  1321. * R109 (0x6D) - Always On Triggers Sequence Select 6
  1322. */
  1323. #define ARIZONA_WSEQ_JD2_FALL_SEQ_ADDR_MASK 0x01FF /* WSEQ_JD2_FALL_SEQ_ADDR - [8:0] */
  1324. #define ARIZONA_WSEQ_JD2_FALL_SEQ_ADDR_SHIFT 0 /* WSEQ_JD2_FALL_SEQ_ADDR - [8:0] */
  1325. #define ARIZONA_WSEQ_JD2_FALL_SEQ_ADDR_WIDTH 9 /* WSEQ_JD2_FALL_SEQ_ADDR - [8:0] */
  1326. /*
  1327. * R112 (0x70) - Comfort Noise Generator
  1328. */
  1329. #define ARIZONA_NOISE_GEN_RATE_MASK 0x7800 /* NOISE_GEN_RATE - [14:11] */
  1330. #define ARIZONA_NOISE_GEN_RATE_SHIFT 11 /* NOISE_GEN_RATE - [14:11] */
  1331. #define ARIZONA_NOISE_GEN_RATE_WIDTH 4 /* NOISE_GEN_RATE - [14:11] */
  1332. #define ARIZONA_NOISE_GEN_ENA 0x0020 /* NOISE_GEN_ENA */
  1333. #define ARIZONA_NOISE_GEN_ENA_MASK 0x0020 /* NOISE_GEN_ENA */
  1334. #define ARIZONA_NOISE_GEN_ENA_SHIFT 5 /* NOISE_GEN_ENA */
  1335. #define ARIZONA_NOISE_GEN_ENA_WIDTH 1 /* NOISE_GEN_ENA */
  1336. #define ARIZONA_NOISE_GEN_GAIN_MASK 0x001F /* NOISE_GEN_GAIN - [4:0] */
  1337. #define ARIZONA_NOISE_GEN_GAIN_SHIFT 0 /* NOISE_GEN_GAIN - [4:0] */
  1338. #define ARIZONA_NOISE_GEN_GAIN_WIDTH 5 /* NOISE_GEN_GAIN - [4:0] */
  1339. /*
  1340. * R144 (0x90) - Haptics Control 1
  1341. */
  1342. #define ARIZONA_HAP_RATE_MASK 0x7800 /* HAP_RATE - [14:11] */
  1343. #define ARIZONA_HAP_RATE_SHIFT 11 /* HAP_RATE - [14:11] */
  1344. #define ARIZONA_HAP_RATE_WIDTH 4 /* HAP_RATE - [14:11] */
  1345. #define ARIZONA_ONESHOT_TRIG 0x0010 /* ONESHOT_TRIG */
  1346. #define ARIZONA_ONESHOT_TRIG_MASK 0x0010 /* ONESHOT_TRIG */
  1347. #define ARIZONA_ONESHOT_TRIG_SHIFT 4 /* ONESHOT_TRIG */
  1348. #define ARIZONA_ONESHOT_TRIG_WIDTH 1 /* ONESHOT_TRIG */
  1349. #define ARIZONA_HAP_CTRL_MASK 0x000C /* HAP_CTRL - [3:2] */
  1350. #define ARIZONA_HAP_CTRL_SHIFT 2 /* HAP_CTRL - [3:2] */
  1351. #define ARIZONA_HAP_CTRL_WIDTH 2 /* HAP_CTRL - [3:2] */
  1352. #define ARIZONA_HAP_ACT 0x0002 /* HAP_ACT */
  1353. #define ARIZONA_HAP_ACT_MASK 0x0002 /* HAP_ACT */
  1354. #define ARIZONA_HAP_ACT_SHIFT 1 /* HAP_ACT */
  1355. #define ARIZONA_HAP_ACT_WIDTH 1 /* HAP_ACT */
  1356. /*
  1357. * R145 (0x91) - Haptics Control 2
  1358. */
  1359. #define ARIZONA_LRA_FREQ_MASK 0x7FFF /* LRA_FREQ - [14:0] */
  1360. #define ARIZONA_LRA_FREQ_SHIFT 0 /* LRA_FREQ - [14:0] */
  1361. #define ARIZONA_LRA_FREQ_WIDTH 15 /* LRA_FREQ - [14:0] */
  1362. /*
  1363. * R146 (0x92) - Haptics phase 1 intensity
  1364. */
  1365. #define ARIZONA_PHASE1_INTENSITY_MASK 0x00FF /* PHASE1_INTENSITY - [7:0] */
  1366. #define ARIZONA_PHASE1_INTENSITY_SHIFT 0 /* PHASE1_INTENSITY - [7:0] */
  1367. #define ARIZONA_PHASE1_INTENSITY_WIDTH 8 /* PHASE1_INTENSITY - [7:0] */
  1368. /*
  1369. * R147 (0x93) - Haptics phase 1 duration
  1370. */
  1371. #define ARIZONA_PHASE1_DURATION_MASK 0x01FF /* PHASE1_DURATION - [8:0] */
  1372. #define ARIZONA_PHASE1_DURATION_SHIFT 0 /* PHASE1_DURATION - [8:0] */
  1373. #define ARIZONA_PHASE1_DURATION_WIDTH 9 /* PHASE1_DURATION - [8:0] */
  1374. /*
  1375. * R148 (0x94) - Haptics phase 2 intensity
  1376. */
  1377. #define ARIZONA_PHASE2_INTENSITY_MASK 0x00FF /* PHASE2_INTENSITY - [7:0] */
  1378. #define ARIZONA_PHASE2_INTENSITY_SHIFT 0 /* PHASE2_INTENSITY - [7:0] */
  1379. #define ARIZONA_PHASE2_INTENSITY_WIDTH 8 /* PHASE2_INTENSITY - [7:0] */
  1380. /*
  1381. * R149 (0x95) - Haptics phase 2 duration
  1382. */
  1383. #define ARIZONA_PHASE2_DURATION_MASK 0x07FF /* PHASE2_DURATION - [10:0] */
  1384. #define ARIZONA_PHASE2_DURATION_SHIFT 0 /* PHASE2_DURATION - [10:0] */
  1385. #define ARIZONA_PHASE2_DURATION_WIDTH 11 /* PHASE2_DURATION - [10:0] */
  1386. /*
  1387. * R150 (0x96) - Haptics phase 3 intensity
  1388. */
  1389. #define ARIZONA_PHASE3_INTENSITY_MASK 0x00FF /* PHASE3_INTENSITY - [7:0] */
  1390. #define ARIZONA_PHASE3_INTENSITY_SHIFT 0 /* PHASE3_INTENSITY - [7:0] */
  1391. #define ARIZONA_PHASE3_INTENSITY_WIDTH 8 /* PHASE3_INTENSITY - [7:0] */
  1392. /*
  1393. * R151 (0x97) - Haptics phase 3 duration
  1394. */
  1395. #define ARIZONA_PHASE3_DURATION_MASK 0x01FF /* PHASE3_DURATION - [8:0] */
  1396. #define ARIZONA_PHASE3_DURATION_SHIFT 0 /* PHASE3_DURATION - [8:0] */
  1397. #define ARIZONA_PHASE3_DURATION_WIDTH 9 /* PHASE3_DURATION - [8:0] */
  1398. /*
  1399. * R152 (0x98) - Haptics Status
  1400. */
  1401. #define ARIZONA_ONESHOT_STS 0x0001 /* ONESHOT_STS */
  1402. #define ARIZONA_ONESHOT_STS_MASK 0x0001 /* ONESHOT_STS */
  1403. #define ARIZONA_ONESHOT_STS_SHIFT 0 /* ONESHOT_STS */
  1404. #define ARIZONA_ONESHOT_STS_WIDTH 1 /* ONESHOT_STS */
  1405. /*
  1406. * R256 (0x100) - Clock 32k 1
  1407. */
  1408. #define ARIZONA_CLK_32K_ENA 0x0040 /* CLK_32K_ENA */
  1409. #define ARIZONA_CLK_32K_ENA_MASK 0x0040 /* CLK_32K_ENA */
  1410. #define ARIZONA_CLK_32K_ENA_SHIFT 6 /* CLK_32K_ENA */
  1411. #define ARIZONA_CLK_32K_ENA_WIDTH 1 /* CLK_32K_ENA */
  1412. #define ARIZONA_CLK_32K_SRC_MASK 0x0003 /* CLK_32K_SRC - [1:0] */
  1413. #define ARIZONA_CLK_32K_SRC_SHIFT 0 /* CLK_32K_SRC - [1:0] */
  1414. #define ARIZONA_CLK_32K_SRC_WIDTH 2 /* CLK_32K_SRC - [1:0] */
  1415. /*
  1416. * R257 (0x101) - System Clock 1
  1417. */
  1418. #define ARIZONA_SYSCLK_FRAC 0x8000 /* SYSCLK_FRAC */
  1419. #define ARIZONA_SYSCLK_FRAC_MASK 0x8000 /* SYSCLK_FRAC */
  1420. #define ARIZONA_SYSCLK_FRAC_SHIFT 15 /* SYSCLK_FRAC */
  1421. #define ARIZONA_SYSCLK_FRAC_WIDTH 1 /* SYSCLK_FRAC */
  1422. #define ARIZONA_SYSCLK_FREQ_MASK 0x0700 /* SYSCLK_FREQ - [10:8] */
  1423. #define ARIZONA_SYSCLK_FREQ_SHIFT 8 /* SYSCLK_FREQ - [10:8] */
  1424. #define ARIZONA_SYSCLK_FREQ_WIDTH 3 /* SYSCLK_FREQ - [10:8] */
  1425. #define ARIZONA_SYSCLK_ENA 0x0040 /* SYSCLK_ENA */
  1426. #define ARIZONA_SYSCLK_ENA_MASK 0x0040 /* SYSCLK_ENA */
  1427. #define ARIZONA_SYSCLK_ENA_SHIFT 6 /* SYSCLK_ENA */
  1428. #define ARIZONA_SYSCLK_ENA_WIDTH 1 /* SYSCLK_ENA */
  1429. #define ARIZONA_SYSCLK_SRC_MASK 0x000F /* SYSCLK_SRC - [3:0] */
  1430. #define ARIZONA_SYSCLK_SRC_SHIFT 0 /* SYSCLK_SRC - [3:0] */
  1431. #define ARIZONA_SYSCLK_SRC_WIDTH 4 /* SYSCLK_SRC - [3:0] */
  1432. /*
  1433. * R258 (0x102) - Sample rate 1
  1434. */
  1435. #define ARIZONA_SAMPLE_RATE_1_MASK 0x001F /* SAMPLE_RATE_1 - [4:0] */
  1436. #define ARIZONA_SAMPLE_RATE_1_SHIFT 0 /* SAMPLE_RATE_1 - [4:0] */
  1437. #define ARIZONA_SAMPLE_RATE_1_WIDTH 5 /* SAMPLE_RATE_1 - [4:0] */
  1438. /*
  1439. * R259 (0x103) - Sample rate 2
  1440. */
  1441. #define ARIZONA_SAMPLE_RATE_2_MASK 0x001F /* SAMPLE_RATE_2 - [4:0] */
  1442. #define ARIZONA_SAMPLE_RATE_2_SHIFT 0 /* SAMPLE_RATE_2 - [4:0] */
  1443. #define ARIZONA_SAMPLE_RATE_2_WIDTH 5 /* SAMPLE_RATE_2 - [4:0] */
  1444. /*
  1445. * R260 (0x104) - Sample rate 3
  1446. */
  1447. #define ARIZONA_SAMPLE_RATE_3_MASK 0x001F /* SAMPLE_RATE_3 - [4:0] */
  1448. #define ARIZONA_SAMPLE_RATE_3_SHIFT 0 /* SAMPLE_RATE_3 - [4:0] */
  1449. #define ARIZONA_SAMPLE_RATE_3_WIDTH 5 /* SAMPLE_RATE_3 - [4:0] */
  1450. /*
  1451. * R266 (0x10A) - Sample rate 1 status
  1452. */
  1453. #define ARIZONA_SAMPLE_RATE_1_STS_MASK 0x001F /* SAMPLE_RATE_1_STS - [4:0] */
  1454. #define ARIZONA_SAMPLE_RATE_1_STS_SHIFT 0 /* SAMPLE_RATE_1_STS - [4:0] */
  1455. #define ARIZONA_SAMPLE_RATE_1_STS_WIDTH 5 /* SAMPLE_RATE_1_STS - [4:0] */
  1456. /*
  1457. * R267 (0x10B) - Sample rate 2 status
  1458. */
  1459. #define ARIZONA_SAMPLE_RATE_2_STS_MASK 0x001F /* SAMPLE_RATE_2_STS - [4:0] */
  1460. #define ARIZONA_SAMPLE_RATE_2_STS_SHIFT 0 /* SAMPLE_RATE_2_STS - [4:0] */
  1461. #define ARIZONA_SAMPLE_RATE_2_STS_WIDTH 5 /* SAMPLE_RATE_2_STS - [4:0] */
  1462. /*
  1463. * R268 (0x10C) - Sample rate 3 status
  1464. */
  1465. #define ARIZONA_SAMPLE_RATE_3_STS_MASK 0x001F /* SAMPLE_RATE_3_STS - [4:0] */
  1466. #define ARIZONA_SAMPLE_RATE_3_STS_SHIFT 0 /* SAMPLE_RATE_3_STS - [4:0] */
  1467. #define ARIZONA_SAMPLE_RATE_3_STS_WIDTH 5 /* SAMPLE_RATE_3_STS - [4:0] */
  1468. /*
  1469. * R274 (0x112) - Async clock 1
  1470. */
  1471. #define ARIZONA_ASYNC_CLK_FREQ_MASK 0x0700 /* ASYNC_CLK_FREQ - [10:8] */
  1472. #define ARIZONA_ASYNC_CLK_FREQ_SHIFT 8 /* ASYNC_CLK_FREQ - [10:8] */
  1473. #define ARIZONA_ASYNC_CLK_FREQ_WIDTH 3 /* ASYNC_CLK_FREQ - [10:8] */
  1474. #define ARIZONA_ASYNC_CLK_ENA 0x0040 /* ASYNC_CLK_ENA */
  1475. #define ARIZONA_ASYNC_CLK_ENA_MASK 0x0040 /* ASYNC_CLK_ENA */
  1476. #define ARIZONA_ASYNC_CLK_ENA_SHIFT 6 /* ASYNC_CLK_ENA */
  1477. #define ARIZONA_ASYNC_CLK_ENA_WIDTH 1 /* ASYNC_CLK_ENA */
  1478. #define ARIZONA_ASYNC_CLK_SRC_MASK 0x000F /* ASYNC_CLK_SRC - [3:0] */
  1479. #define ARIZONA_ASYNC_CLK_SRC_SHIFT 0 /* ASYNC_CLK_SRC - [3:0] */
  1480. #define ARIZONA_ASYNC_CLK_SRC_WIDTH 4 /* ASYNC_CLK_SRC - [3:0] */
  1481. /*
  1482. * R275 (0x113) - Async sample rate 1
  1483. */
  1484. #define ARIZONA_ASYNC_SAMPLE_RATE_MASK 0x001F /* ASYNC_SAMPLE_RATE - [4:0] */
  1485. #define ARIZONA_ASYNC_SAMPLE_RATE_SHIFT 0 /* ASYNC_SAMPLE_RATE - [4:0] */
  1486. #define ARIZONA_ASYNC_SAMPLE_RATE_WIDTH 5 /* ASYNC_SAMPLE_RATE - [4:0] */
  1487. /*
  1488. * R283 (0x11B) - Async sample rate 1 status
  1489. */
  1490. #define ARIZONA_ASYNC_SAMPLE_RATE_STS_MASK 0x001F /* ASYNC_SAMPLE_RATE_STS - [4:0] */
  1491. #define ARIZONA_ASYNC_SAMPLE_RATE_STS_SHIFT 0 /* ASYNC_SAMPLE_RATE_STS - [4:0] */
  1492. #define ARIZONA_ASYNC_SAMPLE_RATE_STS_WIDTH 5 /* ASYNC_SAMPLE_RATE_STS - [4:0] */
  1493. /*
  1494. * R329 (0x149) - Output system clock
  1495. */
  1496. #define ARIZONA_OPCLK_ENA 0x8000 /* OPCLK_ENA */
  1497. #define ARIZONA_OPCLK_ENA_MASK 0x8000 /* OPCLK_ENA */
  1498. #define ARIZONA_OPCLK_ENA_SHIFT 15 /* OPCLK_ENA */
  1499. #define ARIZONA_OPCLK_ENA_WIDTH 1 /* OPCLK_ENA */
  1500. #define ARIZONA_OPCLK_DIV_MASK 0x00F8 /* OPCLK_DIV - [7:3] */
  1501. #define ARIZONA_OPCLK_DIV_SHIFT 3 /* OPCLK_DIV - [7:3] */
  1502. #define ARIZONA_OPCLK_DIV_WIDTH 5 /* OPCLK_DIV - [7:3] */
  1503. #define ARIZONA_OPCLK_SEL_MASK 0x0007 /* OPCLK_SEL - [2:0] */
  1504. #define ARIZONA_OPCLK_SEL_SHIFT 0 /* OPCLK_SEL - [2:0] */
  1505. #define ARIZONA_OPCLK_SEL_WIDTH 3 /* OPCLK_SEL - [2:0] */
  1506. /*
  1507. * R330 (0x14A) - Output async clock
  1508. */
  1509. #define ARIZONA_OPCLK_ASYNC_ENA 0x8000 /* OPCLK_ASYNC_ENA */
  1510. #define ARIZONA_OPCLK_ASYNC_ENA_MASK 0x8000 /* OPCLK_ASYNC_ENA */
  1511. #define ARIZONA_OPCLK_ASYNC_ENA_SHIFT 15 /* OPCLK_ASYNC_ENA */
  1512. #define ARIZONA_OPCLK_ASYNC_ENA_WIDTH 1 /* OPCLK_ASYNC_ENA */
  1513. #define ARIZONA_OPCLK_ASYNC_DIV_MASK 0x00F8 /* OPCLK_ASYNC_DIV - [7:3] */
  1514. #define ARIZONA_OPCLK_ASYNC_DIV_SHIFT 3 /* OPCLK_ASYNC_DIV - [7:3] */
  1515. #define ARIZONA_OPCLK_ASYNC_DIV_WIDTH 5 /* OPCLK_ASYNC_DIV - [7:3] */
  1516. #define ARIZONA_OPCLK_ASYNC_SEL_MASK 0x0007 /* OPCLK_ASYNC_SEL - [2:0] */
  1517. #define ARIZONA_OPCLK_ASYNC_SEL_SHIFT 0 /* OPCLK_ASYNC_SEL - [2:0] */
  1518. #define ARIZONA_OPCLK_ASYNC_SEL_WIDTH 3 /* OPCLK_ASYNC_SEL - [2:0] */
  1519. /*
  1520. * R338 (0x152) - Rate Estimator 1
  1521. */
  1522. #define ARIZONA_TRIG_ON_STARTUP 0x0010 /* TRIG_ON_STARTUP */
  1523. #define ARIZONA_TRIG_ON_STARTUP_MASK 0x0010 /* TRIG_ON_STARTUP */
  1524. #define ARIZONA_TRIG_ON_STARTUP_SHIFT 4 /* TRIG_ON_STARTUP */
  1525. #define ARIZONA_TRIG_ON_STARTUP_WIDTH 1 /* TRIG_ON_STARTUP */
  1526. #define ARIZONA_LRCLK_SRC_MASK 0x000E /* LRCLK_SRC - [3:1] */
  1527. #define ARIZONA_LRCLK_SRC_SHIFT 1 /* LRCLK_SRC - [3:1] */
  1528. #define ARIZONA_LRCLK_SRC_WIDTH 3 /* LRCLK_SRC - [3:1] */
  1529. #define ARIZONA_RATE_EST_ENA 0x0001 /* RATE_EST_ENA */
  1530. #define ARIZONA_RATE_EST_ENA_MASK 0x0001 /* RATE_EST_ENA */
  1531. #define ARIZONA_RATE_EST_ENA_SHIFT 0 /* RATE_EST_ENA */
  1532. #define ARIZONA_RATE_EST_ENA_WIDTH 1 /* RATE_EST_ENA */
  1533. /*
  1534. * R339 (0x153) - Rate Estimator 2
  1535. */
  1536. #define ARIZONA_SAMPLE_RATE_DETECT_A_MASK 0x001F /* SAMPLE_RATE_DETECT_A - [4:0] */
  1537. #define ARIZONA_SAMPLE_RATE_DETECT_A_SHIFT 0 /* SAMPLE_RATE_DETECT_A - [4:0] */
  1538. #define ARIZONA_SAMPLE_RATE_DETECT_A_WIDTH 5 /* SAMPLE_RATE_DETECT_A - [4:0] */
  1539. /*
  1540. * R340 (0x154) - Rate Estimator 3
  1541. */
  1542. #define ARIZONA_SAMPLE_RATE_DETECT_B_MASK 0x001F /* SAMPLE_RATE_DETECT_B - [4:0] */
  1543. #define ARIZONA_SAMPLE_RATE_DETECT_B_SHIFT 0 /* SAMPLE_RATE_DETECT_B - [4:0] */
  1544. #define ARIZONA_SAMPLE_RATE_DETECT_B_WIDTH 5 /* SAMPLE_RATE_DETECT_B - [4:0] */
  1545. /*
  1546. * R341 (0x155) - Rate Estimator 4
  1547. */
  1548. #define ARIZONA_SAMPLE_RATE_DETECT_C_MASK 0x001F /* SAMPLE_RATE_DETECT_C - [4:0] */
  1549. #define ARIZONA_SAMPLE_RATE_DETECT_C_SHIFT 0 /* SAMPLE_RATE_DETECT_C - [4:0] */
  1550. #define ARIZONA_SAMPLE_RATE_DETECT_C_WIDTH 5 /* SAMPLE_RATE_DETECT_C - [4:0] */
  1551. /*
  1552. * R342 (0x156) - Rate Estimator 5
  1553. */
  1554. #define ARIZONA_SAMPLE_RATE_DETECT_D_MASK 0x001F /* SAMPLE_RATE_DETECT_D - [4:0] */
  1555. #define ARIZONA_SAMPLE_RATE_DETECT_D_SHIFT 0 /* SAMPLE_RATE_DETECT_D - [4:0] */
  1556. #define ARIZONA_SAMPLE_RATE_DETECT_D_WIDTH 5 /* SAMPLE_RATE_DETECT_D - [4:0] */
  1557. /*
  1558. * R353 (0x161) - Dynamic Frequency Scaling 1
  1559. */
  1560. #define ARIZONA_SUBSYS_MAX_FREQ 0x0001 /* SUBSYS_MAX_FREQ */
  1561. #define ARIZONA_SUBSYS_MAX_FREQ_SHIFT 0 /* SUBSYS_MAX_FREQ */
  1562. #define ARIZONA_SUBSYS_MAX_FREQ_WIDTH 1 /* SUBSYS_MAX_FREQ */
  1563. /*
  1564. * R369 (0x171) - FLL1 Control 1
  1565. */
  1566. #define ARIZONA_FLL1_FREERUN 0x0002 /* FLL1_FREERUN */
  1567. #define ARIZONA_FLL1_FREERUN_MASK 0x0002 /* FLL1_FREERUN */
  1568. #define ARIZONA_FLL1_FREERUN_SHIFT 1 /* FLL1_FREERUN */
  1569. #define ARIZONA_FLL1_FREERUN_WIDTH 1 /* FLL1_FREERUN */
  1570. #define ARIZONA_FLL1_ENA 0x0001 /* FLL1_ENA */
  1571. #define ARIZONA_FLL1_ENA_MASK 0x0001 /* FLL1_ENA */
  1572. #define ARIZONA_FLL1_ENA_SHIFT 0 /* FLL1_ENA */
  1573. #define ARIZONA_FLL1_ENA_WIDTH 1 /* FLL1_ENA */
  1574. /*
  1575. * R370 (0x172) - FLL1 Control 2
  1576. */
  1577. #define ARIZONA_FLL1_CTRL_UPD 0x8000 /* FLL1_CTRL_UPD */
  1578. #define ARIZONA_FLL1_CTRL_UPD_MASK 0x8000 /* FLL1_CTRL_UPD */
  1579. #define ARIZONA_FLL1_CTRL_UPD_SHIFT 15 /* FLL1_CTRL_UPD */
  1580. #define ARIZONA_FLL1_CTRL_UPD_WIDTH 1 /* FLL1_CTRL_UPD */
  1581. #define ARIZONA_FLL1_N_MASK 0x03FF /* FLL1_N - [9:0] */
  1582. #define ARIZONA_FLL1_N_SHIFT 0 /* FLL1_N - [9:0] */
  1583. #define ARIZONA_FLL1_N_WIDTH 10 /* FLL1_N - [9:0] */
  1584. /*
  1585. * R371 (0x173) - FLL1 Control 3
  1586. */
  1587. #define ARIZONA_FLL1_THETA_MASK 0xFFFF /* FLL1_THETA - [15:0] */
  1588. #define ARIZONA_FLL1_THETA_SHIFT 0 /* FLL1_THETA - [15:0] */
  1589. #define ARIZONA_FLL1_THETA_WIDTH 16 /* FLL1_THETA - [15:0] */
  1590. /*
  1591. * R372 (0x174) - FLL1 Control 4
  1592. */
  1593. #define ARIZONA_FLL1_LAMBDA_MASK 0xFFFF /* FLL1_LAMBDA - [15:0] */
  1594. #define ARIZONA_FLL1_LAMBDA_SHIFT 0 /* FLL1_LAMBDA - [15:0] */
  1595. #define ARIZONA_FLL1_LAMBDA_WIDTH 16 /* FLL1_LAMBDA - [15:0] */
  1596. /*
  1597. * R373 (0x175) - FLL1 Control 5
  1598. */
  1599. #define ARIZONA_FLL1_FRATIO_MASK 0x0700 /* FLL1_FRATIO - [10:8] */
  1600. #define ARIZONA_FLL1_FRATIO_SHIFT 8 /* FLL1_FRATIO - [10:8] */
  1601. #define ARIZONA_FLL1_FRATIO_WIDTH 3 /* FLL1_FRATIO - [10:8] */
  1602. #define ARIZONA_FLL1_OUTDIV_MASK 0x000E /* FLL1_OUTDIV - [3:1] */
  1603. #define ARIZONA_FLL1_OUTDIV_SHIFT 1 /* FLL1_OUTDIV - [3:1] */
  1604. #define ARIZONA_FLL1_OUTDIV_WIDTH 3 /* FLL1_OUTDIV - [3:1] */
  1605. /*
  1606. * R374 (0x176) - FLL1 Control 6
  1607. */
  1608. #define ARIZONA_FLL1_CLK_REF_DIV_MASK 0x00C0 /* FLL1_CLK_REF_DIV - [7:6] */
  1609. #define ARIZONA_FLL1_CLK_REF_DIV_SHIFT 6 /* FLL1_CLK_REF_DIV - [7:6] */
  1610. #define ARIZONA_FLL1_CLK_REF_DIV_WIDTH 2 /* FLL1_CLK_REF_DIV - [7:6] */
  1611. #define ARIZONA_FLL1_CLK_REF_SRC_MASK 0x000F /* FLL1_CLK_REF_SRC - [3:0] */
  1612. #define ARIZONA_FLL1_CLK_REF_SRC_SHIFT 0 /* FLL1_CLK_REF_SRC - [3:0] */
  1613. #define ARIZONA_FLL1_CLK_REF_SRC_WIDTH 4 /* FLL1_CLK_REF_SRC - [3:0] */
  1614. /*
  1615. * R375 (0x177) - FLL1 Loop Filter Test 1
  1616. */
  1617. #define ARIZONA_FLL1_FRC_INTEG_UPD 0x8000 /* FLL1_FRC_INTEG_UPD */
  1618. #define ARIZONA_FLL1_FRC_INTEG_UPD_MASK 0x8000 /* FLL1_FRC_INTEG_UPD */
  1619. #define ARIZONA_FLL1_FRC_INTEG_UPD_SHIFT 15 /* FLL1_FRC_INTEG_UPD */
  1620. #define ARIZONA_FLL1_FRC_INTEG_UPD_WIDTH 1 /* FLL1_FRC_INTEG_UPD */
  1621. #define ARIZONA_FLL1_FRC_INTEG_VAL_MASK 0x0FFF /* FLL1_FRC_INTEG_VAL - [11:0] */
  1622. #define ARIZONA_FLL1_FRC_INTEG_VAL_SHIFT 0 /* FLL1_FRC_INTEG_VAL - [11:0] */
  1623. #define ARIZONA_FLL1_FRC_INTEG_VAL_WIDTH 12 /* FLL1_FRC_INTEG_VAL - [11:0] */
  1624. /*
  1625. * R377 (0x179) - FLL1 Control 7
  1626. */
  1627. #define ARIZONA_FLL1_GAIN_MASK 0x003c /* FLL1_GAIN */
  1628. #define ARIZONA_FLL1_GAIN_SHIFT 2 /* FLL1_GAIN */
  1629. #define ARIZONA_FLL1_GAIN_WIDTH 4 /* FLL1_GAIN */
  1630. /*
  1631. * R385 (0x181) - FLL1 Synchroniser 1
  1632. */
  1633. #define ARIZONA_FLL1_SYNC_ENA 0x0001 /* FLL1_SYNC_ENA */
  1634. #define ARIZONA_FLL1_SYNC_ENA_MASK 0x0001 /* FLL1_SYNC_ENA */
  1635. #define ARIZONA_FLL1_SYNC_ENA_SHIFT 0 /* FLL1_SYNC_ENA */
  1636. #define ARIZONA_FLL1_SYNC_ENA_WIDTH 1 /* FLL1_SYNC_ENA */
  1637. /*
  1638. * R386 (0x182) - FLL1 Synchroniser 2
  1639. */
  1640. #define ARIZONA_FLL1_SYNC_N_MASK 0x03FF /* FLL1_SYNC_N - [9:0] */
  1641. #define ARIZONA_FLL1_SYNC_N_SHIFT 0 /* FLL1_SYNC_N - [9:0] */
  1642. #define ARIZONA_FLL1_SYNC_N_WIDTH 10 /* FLL1_SYNC_N - [9:0] */
  1643. /*
  1644. * R387 (0x183) - FLL1 Synchroniser 3
  1645. */
  1646. #define ARIZONA_FLL1_SYNC_THETA_MASK 0xFFFF /* FLL1_SYNC_THETA - [15:0] */
  1647. #define ARIZONA_FLL1_SYNC_THETA_SHIFT 0 /* FLL1_SYNC_THETA - [15:0] */
  1648. #define ARIZONA_FLL1_SYNC_THETA_WIDTH 16 /* FLL1_SYNC_THETA - [15:0] */
  1649. /*
  1650. * R388 (0x184) - FLL1 Synchroniser 4
  1651. */
  1652. #define ARIZONA_FLL1_SYNC_LAMBDA_MASK 0xFFFF /* FLL1_SYNC_LAMBDA - [15:0] */
  1653. #define ARIZONA_FLL1_SYNC_LAMBDA_SHIFT 0 /* FLL1_SYNC_LAMBDA - [15:0] */
  1654. #define ARIZONA_FLL1_SYNC_LAMBDA_WIDTH 16 /* FLL1_SYNC_LAMBDA - [15:0] */
  1655. /*
  1656. * R389 (0x185) - FLL1 Synchroniser 5
  1657. */
  1658. #define ARIZONA_FLL1_SYNC_FRATIO_MASK 0x0700 /* FLL1_SYNC_FRATIO - [10:8] */
  1659. #define ARIZONA_FLL1_SYNC_FRATIO_SHIFT 8 /* FLL1_SYNC_FRATIO - [10:8] */
  1660. #define ARIZONA_FLL1_SYNC_FRATIO_WIDTH 3 /* FLL1_SYNC_FRATIO - [10:8] */
  1661. /*
  1662. * R390 (0x186) - FLL1 Synchroniser 6
  1663. */
  1664. #define ARIZONA_FLL1_CLK_SYNC_DIV_MASK 0x00C0 /* FLL1_CLK_SYNC_DIV - [7:6] */
  1665. #define ARIZONA_FLL1_CLK_SYNC_DIV_SHIFT 6 /* FLL1_CLK_SYNC_DIV - [7:6] */
  1666. #define ARIZONA_FLL1_CLK_SYNC_DIV_WIDTH 2 /* FLL1_CLK_SYNC_DIV - [7:6] */
  1667. #define ARIZONA_FLL1_CLK_SYNC_SRC_MASK 0x000F /* FLL1_CLK_SYNC_SRC - [3:0] */
  1668. #define ARIZONA_FLL1_CLK_SYNC_SRC_SHIFT 0 /* FLL1_CLK_SYNC_SRC - [3:0] */
  1669. #define ARIZONA_FLL1_CLK_SYNC_SRC_WIDTH 4 /* FLL1_CLK_SYNC_SRC - [3:0] */
  1670. /*
  1671. * R391 (0x187) - FLL1 Synchroniser 7
  1672. */
  1673. #define ARIZONA_FLL1_SYNC_GAIN_MASK 0x003c /* FLL1_SYNC_GAIN */
  1674. #define ARIZONA_FLL1_SYNC_GAIN_SHIFT 2 /* FLL1_SYNC_GAIN */
  1675. #define ARIZONA_FLL1_SYNC_GAIN_WIDTH 4 /* FLL1_SYNC_GAIN */
  1676. #define ARIZONA_FLL1_SYNC_BW 0x0001 /* FLL1_SYNC_BW */
  1677. #define ARIZONA_FLL1_SYNC_BW_MASK 0x0001 /* FLL1_SYNC_BW */
  1678. #define ARIZONA_FLL1_SYNC_BW_SHIFT 0 /* FLL1_SYNC_BW */
  1679. #define ARIZONA_FLL1_SYNC_BW_WIDTH 1 /* FLL1_SYNC_BW */
  1680. /*
  1681. * R393 (0x189) - FLL1 Spread Spectrum
  1682. */
  1683. #define ARIZONA_FLL1_SS_AMPL_MASK 0x0030 /* FLL1_SS_AMPL - [5:4] */
  1684. #define ARIZONA_FLL1_SS_AMPL_SHIFT 4 /* FLL1_SS_AMPL - [5:4] */
  1685. #define ARIZONA_FLL1_SS_AMPL_WIDTH 2 /* FLL1_SS_AMPL - [5:4] */
  1686. #define ARIZONA_FLL1_SS_FREQ_MASK 0x000C /* FLL1_SS_FREQ - [3:2] */
  1687. #define ARIZONA_FLL1_SS_FREQ_SHIFT 2 /* FLL1_SS_FREQ - [3:2] */
  1688. #define ARIZONA_FLL1_SS_FREQ_WIDTH 2 /* FLL1_SS_FREQ - [3:2] */
  1689. #define ARIZONA_FLL1_SS_SEL_MASK 0x0003 /* FLL1_SS_SEL - [1:0] */
  1690. #define ARIZONA_FLL1_SS_SEL_SHIFT 0 /* FLL1_SS_SEL - [1:0] */
  1691. #define ARIZONA_FLL1_SS_SEL_WIDTH 2 /* FLL1_SS_SEL - [1:0] */
  1692. /*
  1693. * R394 (0x18A) - FLL1 GPIO Clock
  1694. */
  1695. #define ARIZONA_FLL1_GPDIV_MASK 0x00FE /* FLL1_GPDIV - [7:1] */
  1696. #define ARIZONA_FLL1_GPDIV_SHIFT 1 /* FLL1_GPDIV - [7:1] */
  1697. #define ARIZONA_FLL1_GPDIV_WIDTH 7 /* FLL1_GPDIV - [7:1] */
  1698. #define ARIZONA_FLL1_GPDIV_ENA 0x0001 /* FLL1_GPDIV_ENA */
  1699. #define ARIZONA_FLL1_GPDIV_ENA_MASK 0x0001 /* FLL1_GPDIV_ENA */
  1700. #define ARIZONA_FLL1_GPDIV_ENA_SHIFT 0 /* FLL1_GPDIV_ENA */
  1701. #define ARIZONA_FLL1_GPDIV_ENA_WIDTH 1 /* FLL1_GPDIV_ENA */
  1702. /*
  1703. * R401 (0x191) - FLL2 Control 1
  1704. */
  1705. #define ARIZONA_FLL2_FREERUN 0x0002 /* FLL2_FREERUN */
  1706. #define ARIZONA_FLL2_FREERUN_MASK 0x0002 /* FLL2_FREERUN */
  1707. #define ARIZONA_FLL2_FREERUN_SHIFT 1 /* FLL2_FREERUN */
  1708. #define ARIZONA_FLL2_FREERUN_WIDTH 1 /* FLL2_FREERUN */
  1709. #define ARIZONA_FLL2_ENA 0x0001 /* FLL2_ENA */
  1710. #define ARIZONA_FLL2_ENA_MASK 0x0001 /* FLL2_ENA */
  1711. #define ARIZONA_FLL2_ENA_SHIFT 0 /* FLL2_ENA */
  1712. #define ARIZONA_FLL2_ENA_WIDTH 1 /* FLL2_ENA */
  1713. /*
  1714. * R402 (0x192) - FLL2 Control 2
  1715. */
  1716. #define ARIZONA_FLL2_CTRL_UPD 0x8000 /* FLL2_CTRL_UPD */
  1717. #define ARIZONA_FLL2_CTRL_UPD_MASK 0x8000 /* FLL2_CTRL_UPD */
  1718. #define ARIZONA_FLL2_CTRL_UPD_SHIFT 15 /* FLL2_CTRL_UPD */
  1719. #define ARIZONA_FLL2_CTRL_UPD_WIDTH 1 /* FLL2_CTRL_UPD */
  1720. #define ARIZONA_FLL2_N_MASK 0x03FF /* FLL2_N - [9:0] */
  1721. #define ARIZONA_FLL2_N_SHIFT 0 /* FLL2_N - [9:0] */
  1722. #define ARIZONA_FLL2_N_WIDTH 10 /* FLL2_N - [9:0] */
  1723. /*
  1724. * R403 (0x193) - FLL2 Control 3
  1725. */
  1726. #define ARIZONA_FLL2_THETA_MASK 0xFFFF /* FLL2_THETA - [15:0] */
  1727. #define ARIZONA_FLL2_THETA_SHIFT 0 /* FLL2_THETA - [15:0] */
  1728. #define ARIZONA_FLL2_THETA_WIDTH 16 /* FLL2_THETA - [15:0] */
  1729. /*
  1730. * R404 (0x194) - FLL2 Control 4
  1731. */
  1732. #define ARIZONA_FLL2_LAMBDA_MASK 0xFFFF /* FLL2_LAMBDA - [15:0] */
  1733. #define ARIZONA_FLL2_LAMBDA_SHIFT 0 /* FLL2_LAMBDA - [15:0] */
  1734. #define ARIZONA_FLL2_LAMBDA_WIDTH 16 /* FLL2_LAMBDA - [15:0] */
  1735. /*
  1736. * R405 (0x195) - FLL2 Control 5
  1737. */
  1738. #define ARIZONA_FLL2_FRATIO_MASK 0x0700 /* FLL2_FRATIO - [10:8] */
  1739. #define ARIZONA_FLL2_FRATIO_SHIFT 8 /* FLL2_FRATIO - [10:8] */
  1740. #define ARIZONA_FLL2_FRATIO_WIDTH 3 /* FLL2_FRATIO - [10:8] */
  1741. #define ARIZONA_FLL2_OUTDIV_MASK 0x000E /* FLL2_OUTDIV - [3:1] */
  1742. #define ARIZONA_FLL2_OUTDIV_SHIFT 1 /* FLL2_OUTDIV - [3:1] */
  1743. #define ARIZONA_FLL2_OUTDIV_WIDTH 3 /* FLL2_OUTDIV - [3:1] */
  1744. /*
  1745. * R406 (0x196) - FLL2 Control 6
  1746. */
  1747. #define ARIZONA_FLL2_CLK_REF_DIV_MASK 0x00C0 /* FLL2_CLK_REF_DIV - [7:6] */
  1748. #define ARIZONA_FLL2_CLK_REF_DIV_SHIFT 6 /* FLL2_CLK_REF_DIV - [7:6] */
  1749. #define ARIZONA_FLL2_CLK_REF_DIV_WIDTH 2 /* FLL2_CLK_REF_DIV - [7:6] */
  1750. #define ARIZONA_FLL2_CLK_REF_SRC_MASK 0x000F /* FLL2_CLK_REF_SRC - [3:0] */
  1751. #define ARIZONA_FLL2_CLK_REF_SRC_SHIFT 0 /* FLL2_CLK_REF_SRC - [3:0] */
  1752. #define ARIZONA_FLL2_CLK_REF_SRC_WIDTH 4 /* FLL2_CLK_REF_SRC - [3:0] */
  1753. /*
  1754. * R407 (0x197) - FLL2 Loop Filter Test 1
  1755. */
  1756. #define ARIZONA_FLL2_FRC_INTEG_UPD 0x8000 /* FLL2_FRC_INTEG_UPD */
  1757. #define ARIZONA_FLL2_FRC_INTEG_UPD_MASK 0x8000 /* FLL2_FRC_INTEG_UPD */
  1758. #define ARIZONA_FLL2_FRC_INTEG_UPD_SHIFT 15 /* FLL2_FRC_INTEG_UPD */
  1759. #define ARIZONA_FLL2_FRC_INTEG_UPD_WIDTH 1 /* FLL2_FRC_INTEG_UPD */
  1760. #define ARIZONA_FLL2_FRC_INTEG_VAL_MASK 0x0FFF /* FLL2_FRC_INTEG_VAL - [11:0] */
  1761. #define ARIZONA_FLL2_FRC_INTEG_VAL_SHIFT 0 /* FLL2_FRC_INTEG_VAL - [11:0] */
  1762. #define ARIZONA_FLL2_FRC_INTEG_VAL_WIDTH 12 /* FLL2_FRC_INTEG_VAL - [11:0] */
  1763. /*
  1764. * R409 (0x199) - FLL2 Control 7
  1765. */
  1766. #define ARIZONA_FLL2_GAIN_MASK 0x003c /* FLL2_GAIN */
  1767. #define ARIZONA_FLL2_GAIN_SHIFT 2 /* FLL2_GAIN */
  1768. #define ARIZONA_FLL2_GAIN_WIDTH 4 /* FLL2_GAIN */
  1769. /*
  1770. * R417 (0x1A1) - FLL2 Synchroniser 1
  1771. */
  1772. #define ARIZONA_FLL2_SYNC_ENA 0x0001 /* FLL2_SYNC_ENA */
  1773. #define ARIZONA_FLL2_SYNC_ENA_MASK 0x0001 /* FLL2_SYNC_ENA */
  1774. #define ARIZONA_FLL2_SYNC_ENA_SHIFT 0 /* FLL2_SYNC_ENA */
  1775. #define ARIZONA_FLL2_SYNC_ENA_WIDTH 1 /* FLL2_SYNC_ENA */
  1776. /*
  1777. * R418 (0x1A2) - FLL2 Synchroniser 2
  1778. */
  1779. #define ARIZONA_FLL2_SYNC_N_MASK 0x03FF /* FLL2_SYNC_N - [9:0] */
  1780. #define ARIZONA_FLL2_SYNC_N_SHIFT 0 /* FLL2_SYNC_N - [9:0] */
  1781. #define ARIZONA_FLL2_SYNC_N_WIDTH 10 /* FLL2_SYNC_N - [9:0] */
  1782. /*
  1783. * R419 (0x1A3) - FLL2 Synchroniser 3
  1784. */
  1785. #define ARIZONA_FLL2_SYNC_THETA_MASK 0xFFFF /* FLL2_SYNC_THETA - [15:0] */
  1786. #define ARIZONA_FLL2_SYNC_THETA_SHIFT 0 /* FLL2_SYNC_THETA - [15:0] */
  1787. #define ARIZONA_FLL2_SYNC_THETA_WIDTH 16 /* FLL2_SYNC_THETA - [15:0] */
  1788. /*
  1789. * R420 (0x1A4) - FLL2 Synchroniser 4
  1790. */
  1791. #define ARIZONA_FLL2_SYNC_LAMBDA_MASK 0xFFFF /* FLL2_SYNC_LAMBDA - [15:0] */
  1792. #define ARIZONA_FLL2_SYNC_LAMBDA_SHIFT 0 /* FLL2_SYNC_LAMBDA - [15:0] */
  1793. #define ARIZONA_FLL2_SYNC_LAMBDA_WIDTH 16 /* FLL2_SYNC_LAMBDA - [15:0] */
  1794. /*
  1795. * R421 (0x1A5) - FLL2 Synchroniser 5
  1796. */
  1797. #define ARIZONA_FLL2_SYNC_FRATIO_MASK 0x0700 /* FLL2_SYNC_FRATIO - [10:8] */
  1798. #define ARIZONA_FLL2_SYNC_FRATIO_SHIFT 8 /* FLL2_SYNC_FRATIO - [10:8] */
  1799. #define ARIZONA_FLL2_SYNC_FRATIO_WIDTH 3 /* FLL2_SYNC_FRATIO - [10:8] */
  1800. /*
  1801. * R422 (0x1A6) - FLL2 Synchroniser 6
  1802. */
  1803. #define ARIZONA_FLL2_CLK_SYNC_DIV_MASK 0x00C0 /* FLL2_CLK_SYNC_DIV - [7:6] */
  1804. #define ARIZONA_FLL2_CLK_SYNC_DIV_SHIFT 6 /* FLL2_CLK_SYNC_DIV - [7:6] */
  1805. #define ARIZONA_FLL2_CLK_SYNC_DIV_WIDTH 2 /* FLL2_CLK_SYNC_DIV - [7:6] */
  1806. #define ARIZONA_FLL2_CLK_SYNC_SRC_MASK 0x000F /* FLL2_CLK_SYNC_SRC - [3:0] */
  1807. #define ARIZONA_FLL2_CLK_SYNC_SRC_SHIFT 0 /* FLL2_CLK_SYNC_SRC - [3:0] */
  1808. #define ARIZONA_FLL2_CLK_SYNC_SRC_WIDTH 4 /* FLL2_CLK_SYNC_SRC - [3:0] */
  1809. /*
  1810. * R423 (0x1A7) - FLL2 Synchroniser 7
  1811. */
  1812. #define ARIZONA_FLL2_SYNC_GAIN_MASK 0x003c /* FLL2_SYNC_GAIN */
  1813. #define ARIZONA_FLL2_SYNC_GAIN_SHIFT 2 /* FLL2_SYNC_GAIN */
  1814. #define ARIZONA_FLL2_SYNC_GAIN_WIDTH 4 /* FLL2_SYNC_GAIN */
  1815. #define ARIZONA_FLL2_SYNC_BW_MASK 0x0001 /* FLL2_SYNC_BW */
  1816. #define ARIZONA_FLL2_SYNC_BW_MASK 0x0001 /* FLL2_SYNC_BW */
  1817. #define ARIZONA_FLL2_SYNC_BW_SHIFT 0 /* FLL2_SYNC_BW */
  1818. #define ARIZONA_FLL2_SYNC_BW_WIDTH 1 /* FLL2_SYNC_BW */
  1819. /*
  1820. * R425 (0x1A9) - FLL2 Spread Spectrum
  1821. */
  1822. #define ARIZONA_FLL2_SS_AMPL_MASK 0x0030 /* FLL2_SS_AMPL - [5:4] */
  1823. #define ARIZONA_FLL2_SS_AMPL_SHIFT 4 /* FLL2_SS_AMPL - [5:4] */
  1824. #define ARIZONA_FLL2_SS_AMPL_WIDTH 2 /* FLL2_SS_AMPL - [5:4] */
  1825. #define ARIZONA_FLL2_SS_FREQ_MASK 0x000C /* FLL2_SS_FREQ - [3:2] */
  1826. #define ARIZONA_FLL2_SS_FREQ_SHIFT 2 /* FLL2_SS_FREQ - [3:2] */
  1827. #define ARIZONA_FLL2_SS_FREQ_WIDTH 2 /* FLL2_SS_FREQ - [3:2] */
  1828. #define ARIZONA_FLL2_SS_SEL_MASK 0x0003 /* FLL2_SS_SEL - [1:0] */
  1829. #define ARIZONA_FLL2_SS_SEL_SHIFT 0 /* FLL2_SS_SEL - [1:0] */
  1830. #define ARIZONA_FLL2_SS_SEL_WIDTH 2 /* FLL2_SS_SEL - [1:0] */
  1831. /*
  1832. * R426 (0x1AA) - FLL2 GPIO Clock
  1833. */
  1834. #define ARIZONA_FLL2_GPDIV_MASK 0x00FE /* FLL2_GPDIV - [7:1] */
  1835. #define ARIZONA_FLL2_GPDIV_SHIFT 1 /* FLL2_GPDIV - [7:1] */
  1836. #define ARIZONA_FLL2_GPDIV_WIDTH 7 /* FLL2_GPDIV - [7:1] */
  1837. #define ARIZONA_FLL2_GPDIV_ENA 0x0001 /* FLL2_GPDIV_ENA */
  1838. #define ARIZONA_FLL2_GPDIV_ENA_MASK 0x0001 /* FLL2_GPDIV_ENA */
  1839. #define ARIZONA_FLL2_GPDIV_ENA_SHIFT 0 /* FLL2_GPDIV_ENA */
  1840. #define ARIZONA_FLL2_GPDIV_ENA_WIDTH 1 /* FLL2_GPDIV_ENA */
  1841. /*
  1842. * R512 (0x200) - Mic Charge Pump 1
  1843. */
  1844. #define ARIZONA_CPMIC_DISCH 0x0004 /* CPMIC_DISCH */
  1845. #define ARIZONA_CPMIC_DISCH_MASK 0x0004 /* CPMIC_DISCH */
  1846. #define ARIZONA_CPMIC_DISCH_SHIFT 2 /* CPMIC_DISCH */
  1847. #define ARIZONA_CPMIC_DISCH_WIDTH 1 /* CPMIC_DISCH */
  1848. #define ARIZONA_CPMIC_BYPASS 0x0002 /* CPMIC_BYPASS */
  1849. #define ARIZONA_CPMIC_BYPASS_MASK 0x0002 /* CPMIC_BYPASS */
  1850. #define ARIZONA_CPMIC_BYPASS_SHIFT 1 /* CPMIC_BYPASS */
  1851. #define ARIZONA_CPMIC_BYPASS_WIDTH 1 /* CPMIC_BYPASS */
  1852. #define ARIZONA_CPMIC_ENA 0x0001 /* CPMIC_ENA */
  1853. #define ARIZONA_CPMIC_ENA_MASK 0x0001 /* CPMIC_ENA */
  1854. #define ARIZONA_CPMIC_ENA_SHIFT 0 /* CPMIC_ENA */
  1855. #define ARIZONA_CPMIC_ENA_WIDTH 1 /* CPMIC_ENA */
  1856. /*
  1857. * R528 (0x210) - LDO1 Control 1
  1858. */
  1859. #define ARIZONA_LDO1_VSEL_MASK 0x07E0 /* LDO1_VSEL - [10:5] */
  1860. #define ARIZONA_LDO1_VSEL_SHIFT 5 /* LDO1_VSEL - [10:5] */
  1861. #define ARIZONA_LDO1_VSEL_WIDTH 6 /* LDO1_VSEL - [10:5] */
  1862. #define ARIZONA_LDO1_FAST 0x0010 /* LDO1_FAST */
  1863. #define ARIZONA_LDO1_FAST_MASK 0x0010 /* LDO1_FAST */
  1864. #define ARIZONA_LDO1_FAST_SHIFT 4 /* LDO1_FAST */
  1865. #define ARIZONA_LDO1_FAST_WIDTH 1 /* LDO1_FAST */
  1866. #define ARIZONA_LDO1_DISCH 0x0004 /* LDO1_DISCH */
  1867. #define ARIZONA_LDO1_DISCH_MASK 0x0004 /* LDO1_DISCH */
  1868. #define ARIZONA_LDO1_DISCH_SHIFT 2 /* LDO1_DISCH */
  1869. #define ARIZONA_LDO1_DISCH_WIDTH 1 /* LDO1_DISCH */
  1870. #define ARIZONA_LDO1_BYPASS 0x0002 /* LDO1_BYPASS */
  1871. #define ARIZONA_LDO1_BYPASS_MASK 0x0002 /* LDO1_BYPASS */
  1872. #define ARIZONA_LDO1_BYPASS_SHIFT 1 /* LDO1_BYPASS */
  1873. #define ARIZONA_LDO1_BYPASS_WIDTH 1 /* LDO1_BYPASS */
  1874. #define ARIZONA_LDO1_ENA 0x0001 /* LDO1_ENA */
  1875. #define ARIZONA_LDO1_ENA_MASK 0x0001 /* LDO1_ENA */
  1876. #define ARIZONA_LDO1_ENA_SHIFT 0 /* LDO1_ENA */
  1877. #define ARIZONA_LDO1_ENA_WIDTH 1 /* LDO1_ENA */
  1878. /*
  1879. * R530 (0x212) - LDO1 Control 2
  1880. */
  1881. #define ARIZONA_LDO1_HI_PWR 0x0001 /* LDO1_HI_PWR */
  1882. #define ARIZONA_LDO1_HI_PWR_SHIFT 0 /* LDO1_HI_PWR */
  1883. #define ARIZONA_LDO1_HI_PWR_WIDTH 1 /* LDO1_HI_PWR */
  1884. /*
  1885. * R531 (0x213) - LDO2 Control 1
  1886. */
  1887. #define ARIZONA_LDO2_VSEL_MASK 0x07E0 /* LDO2_VSEL - [10:5] */
  1888. #define ARIZONA_LDO2_VSEL_SHIFT 5 /* LDO2_VSEL - [10:5] */
  1889. #define ARIZONA_LDO2_VSEL_WIDTH 6 /* LDO2_VSEL - [10:5] */
  1890. #define ARIZONA_LDO2_FAST 0x0010 /* LDO2_FAST */
  1891. #define ARIZONA_LDO2_FAST_MASK 0x0010 /* LDO2_FAST */
  1892. #define ARIZONA_LDO2_FAST_SHIFT 4 /* LDO2_FAST */
  1893. #define ARIZONA_LDO2_FAST_WIDTH 1 /* LDO2_FAST */
  1894. #define ARIZONA_LDO2_DISCH 0x0004 /* LDO2_DISCH */
  1895. #define ARIZONA_LDO2_DISCH_MASK 0x0004 /* LDO2_DISCH */
  1896. #define ARIZONA_LDO2_DISCH_SHIFT 2 /* LDO2_DISCH */
  1897. #define ARIZONA_LDO2_DISCH_WIDTH 1 /* LDO2_DISCH */
  1898. #define ARIZONA_LDO2_BYPASS 0x0002 /* LDO2_BYPASS */
  1899. #define ARIZONA_LDO2_BYPASS_MASK 0x0002 /* LDO2_BYPASS */
  1900. #define ARIZONA_LDO2_BYPASS_SHIFT 1 /* LDO2_BYPASS */
  1901. #define ARIZONA_LDO2_BYPASS_WIDTH 1 /* LDO2_BYPASS */
  1902. #define ARIZONA_LDO2_ENA 0x0001 /* LDO2_ENA */
  1903. #define ARIZONA_LDO2_ENA_MASK 0x0001 /* LDO2_ENA */
  1904. #define ARIZONA_LDO2_ENA_SHIFT 0 /* LDO2_ENA */
  1905. #define ARIZONA_LDO2_ENA_WIDTH 1 /* LDO2_ENA */
  1906. /*
  1907. * R536 (0x218) - Mic Bias Ctrl 1
  1908. */
  1909. #define ARIZONA_MICB1_EXT_CAP 0x8000 /* MICB1_EXT_CAP */
  1910. #define ARIZONA_MICB1_EXT_CAP_MASK 0x8000 /* MICB1_EXT_CAP */
  1911. #define ARIZONA_MICB1_EXT_CAP_SHIFT 15 /* MICB1_EXT_CAP */
  1912. #define ARIZONA_MICB1_EXT_CAP_WIDTH 1 /* MICB1_EXT_CAP */
  1913. #define ARIZONA_MICB1_LVL_MASK 0x01E0 /* MICB1_LVL - [8:5] */
  1914. #define ARIZONA_MICB1_LVL_SHIFT 5 /* MICB1_LVL - [8:5] */
  1915. #define ARIZONA_MICB1_LVL_WIDTH 4 /* MICB1_LVL - [8:5] */
  1916. #define ARIZONA_MICB1_FAST 0x0010 /* MICB1_FAST */
  1917. #define ARIZONA_MICB1_FAST_MASK 0x0010 /* MICB1_FAST */
  1918. #define ARIZONA_MICB1_FAST_SHIFT 4 /* MICB1_FAST */
  1919. #define ARIZONA_MICB1_FAST_WIDTH 1 /* MICB1_FAST */
  1920. #define ARIZONA_MICB1_RATE 0x0008 /* MICB1_RATE */
  1921. #define ARIZONA_MICB1_RATE_MASK 0x0008 /* MICB1_RATE */
  1922. #define ARIZONA_MICB1_RATE_SHIFT 3 /* MICB1_RATE */
  1923. #define ARIZONA_MICB1_RATE_WIDTH 1 /* MICB1_RATE */
  1924. #define ARIZONA_MICB1_DISCH 0x0004 /* MICB1_DISCH */
  1925. #define ARIZONA_MICB1_DISCH_MASK 0x0004 /* MICB1_DISCH */
  1926. #define ARIZONA_MICB1_DISCH_SHIFT 2 /* MICB1_DISCH */
  1927. #define ARIZONA_MICB1_DISCH_WIDTH 1 /* MICB1_DISCH */
  1928. #define ARIZONA_MICB1_BYPASS 0x0002 /* MICB1_BYPASS */
  1929. #define ARIZONA_MICB1_BYPASS_MASK 0x0002 /* MICB1_BYPASS */
  1930. #define ARIZONA_MICB1_BYPASS_SHIFT 1 /* MICB1_BYPASS */
  1931. #define ARIZONA_MICB1_BYPASS_WIDTH 1 /* MICB1_BYPASS */
  1932. #define ARIZONA_MICB1_ENA 0x0001 /* MICB1_ENA */
  1933. #define ARIZONA_MICB1_ENA_MASK 0x0001 /* MICB1_ENA */
  1934. #define ARIZONA_MICB1_ENA_SHIFT 0 /* MICB1_ENA */
  1935. #define ARIZONA_MICB1_ENA_WIDTH 1 /* MICB1_ENA */
  1936. /*
  1937. * R537 (0x219) - Mic Bias Ctrl 2
  1938. */
  1939. #define ARIZONA_MICB2_EXT_CAP 0x8000 /* MICB2_EXT_CAP */
  1940. #define ARIZONA_MICB2_EXT_CAP_MASK 0x8000 /* MICB2_EXT_CAP */
  1941. #define ARIZONA_MICB2_EXT_CAP_SHIFT 15 /* MICB2_EXT_CAP */
  1942. #define ARIZONA_MICB2_EXT_CAP_WIDTH 1 /* MICB2_EXT_CAP */
  1943. #define ARIZONA_MICB2_LVL_MASK 0x01E0 /* MICB2_LVL - [8:5] */
  1944. #define ARIZONA_MICB2_LVL_SHIFT 5 /* MICB2_LVL - [8:5] */
  1945. #define ARIZONA_MICB2_LVL_WIDTH 4 /* MICB2_LVL - [8:5] */
  1946. #define ARIZONA_MICB2_FAST 0x0010 /* MICB2_FAST */
  1947. #define ARIZONA_MICB2_FAST_MASK 0x0010 /* MICB2_FAST */
  1948. #define ARIZONA_MICB2_FAST_SHIFT 4 /* MICB2_FAST */
  1949. #define ARIZONA_MICB2_FAST_WIDTH 1 /* MICB2_FAST */
  1950. #define ARIZONA_MICB2_RATE 0x0008 /* MICB2_RATE */
  1951. #define ARIZONA_MICB2_RATE_MASK 0x0008 /* MICB2_RATE */
  1952. #define ARIZONA_MICB2_RATE_SHIFT 3 /* MICB2_RATE */
  1953. #define ARIZONA_MICB2_RATE_WIDTH 1 /* MICB2_RATE */
  1954. #define ARIZONA_MICB2_DISCH 0x0004 /* MICB2_DISCH */
  1955. #define ARIZONA_MICB2_DISCH_MASK 0x0004 /* MICB2_DISCH */
  1956. #define ARIZONA_MICB2_DISCH_SHIFT 2 /* MICB2_DISCH */
  1957. #define ARIZONA_MICB2_DISCH_WIDTH 1 /* MICB2_DISCH */
  1958. #define ARIZONA_MICB2_BYPASS 0x0002 /* MICB2_BYPASS */
  1959. #define ARIZONA_MICB2_BYPASS_MASK 0x0002 /* MICB2_BYPASS */
  1960. #define ARIZONA_MICB2_BYPASS_SHIFT 1 /* MICB2_BYPASS */
  1961. #define ARIZONA_MICB2_BYPASS_WIDTH 1 /* MICB2_BYPASS */
  1962. #define ARIZONA_MICB2_ENA 0x0001 /* MICB2_ENA */
  1963. #define ARIZONA_MICB2_ENA_MASK 0x0001 /* MICB2_ENA */
  1964. #define ARIZONA_MICB2_ENA_SHIFT 0 /* MICB2_ENA */
  1965. #define ARIZONA_MICB2_ENA_WIDTH 1 /* MICB2_ENA */
  1966. /*
  1967. * R538 (0x21A) - Mic Bias Ctrl 3
  1968. */
  1969. #define ARIZONA_MICB3_EXT_CAP 0x8000 /* MICB3_EXT_CAP */
  1970. #define ARIZONA_MICB3_EXT_CAP_MASK 0x8000 /* MICB3_EXT_CAP */
  1971. #define ARIZONA_MICB3_EXT_CAP_SHIFT 15 /* MICB3_EXT_CAP */
  1972. #define ARIZONA_MICB3_EXT_CAP_WIDTH 1 /* MICB3_EXT_CAP */
  1973. #define ARIZONA_MICB3_LVL_MASK 0x01E0 /* MICB3_LVL - [8:5] */
  1974. #define ARIZONA_MICB3_LVL_SHIFT 5 /* MICB3_LVL - [8:5] */
  1975. #define ARIZONA_MICB3_LVL_WIDTH 4 /* MICB3_LVL - [8:5] */
  1976. #define ARIZONA_MICB3_FAST 0x0010 /* MICB3_FAST */
  1977. #define ARIZONA_MICB3_FAST_MASK 0x0010 /* MICB3_FAST */
  1978. #define ARIZONA_MICB3_FAST_SHIFT 4 /* MICB3_FAST */
  1979. #define ARIZONA_MICB3_FAST_WIDTH 1 /* MICB3_FAST */
  1980. #define ARIZONA_MICB3_RATE 0x0008 /* MICB3_RATE */
  1981. #define ARIZONA_MICB3_RATE_MASK 0x0008 /* MICB3_RATE */
  1982. #define ARIZONA_MICB3_RATE_SHIFT 3 /* MICB3_RATE */
  1983. #define ARIZONA_MICB3_RATE_WIDTH 1 /* MICB3_RATE */
  1984. #define ARIZONA_MICB3_DISCH 0x0004 /* MICB3_DISCH */
  1985. #define ARIZONA_MICB3_DISCH_MASK 0x0004 /* MICB3_DISCH */
  1986. #define ARIZONA_MICB3_DISCH_SHIFT 2 /* MICB3_DISCH */
  1987. #define ARIZONA_MICB3_DISCH_WIDTH 1 /* MICB3_DISCH */
  1988. #define ARIZONA_MICB3_BYPASS 0x0002 /* MICB3_BYPASS */
  1989. #define ARIZONA_MICB3_BYPASS_MASK 0x0002 /* MICB3_BYPASS */
  1990. #define ARIZONA_MICB3_BYPASS_SHIFT 1 /* MICB3_BYPASS */
  1991. #define ARIZONA_MICB3_BYPASS_WIDTH 1 /* MICB3_BYPASS */
  1992. #define ARIZONA_MICB3_ENA 0x0001 /* MICB3_ENA */
  1993. #define ARIZONA_MICB3_ENA_MASK 0x0001 /* MICB3_ENA */
  1994. #define ARIZONA_MICB3_ENA_SHIFT 0 /* MICB3_ENA */
  1995. #define ARIZONA_MICB3_ENA_WIDTH 1 /* MICB3_ENA */
  1996. /*
  1997. * R659 (0x293) - Accessory Detect Mode 1
  1998. */
  1999. #define ARIZONA_ACCDET_SRC 0x2000 /* ACCDET_SRC */
  2000. #define ARIZONA_ACCDET_SRC_MASK 0x2000 /* ACCDET_SRC */
  2001. #define ARIZONA_ACCDET_SRC_SHIFT 13 /* ACCDET_SRC */
  2002. #define ARIZONA_ACCDET_SRC_WIDTH 1 /* ACCDET_SRC */
  2003. #define ARIZONA_ACCDET_MODE_MASK 0x0003 /* ACCDET_MODE - [1:0] */
  2004. #define ARIZONA_ACCDET_MODE_SHIFT 0 /* ACCDET_MODE - [1:0] */
  2005. #define ARIZONA_ACCDET_MODE_WIDTH 2 /* ACCDET_MODE - [1:0] */
  2006. /*
  2007. * R667 (0x29B) - Headphone Detect 1
  2008. */
  2009. #define ARIZONA_HP_IMPEDANCE_RANGE_MASK 0x0600 /* HP_IMPEDANCE_RANGE - [10:9] */
  2010. #define ARIZONA_HP_IMPEDANCE_RANGE_SHIFT 9 /* HP_IMPEDANCE_RANGE - [10:9] */
  2011. #define ARIZONA_HP_IMPEDANCE_RANGE_WIDTH 2 /* HP_IMPEDANCE_RANGE - [10:9] */
  2012. #define ARIZONA_HP_STEP_SIZE 0x0100 /* HP_STEP_SIZE */
  2013. #define ARIZONA_HP_STEP_SIZE_MASK 0x0100 /* HP_STEP_SIZE */
  2014. #define ARIZONA_HP_STEP_SIZE_SHIFT 8 /* HP_STEP_SIZE */
  2015. #define ARIZONA_HP_STEP_SIZE_WIDTH 1 /* HP_STEP_SIZE */
  2016. #define ARIZONA_HP_HOLDTIME_MASK 0x00E0 /* HP_HOLDTIME - [7:5] */
  2017. #define ARIZONA_HP_HOLDTIME_SHIFT 5 /* HP_HOLDTIME - [7:5] */
  2018. #define ARIZONA_HP_HOLDTIME_WIDTH 3 /* HP_HOLDTIME - [7:5] */
  2019. #define ARIZONA_HP_CLK_DIV_MASK 0x0018 /* HP_CLK_DIV - [4:3] */
  2020. #define ARIZONA_HP_CLK_DIV_SHIFT 3 /* HP_CLK_DIV - [4:3] */
  2021. #define ARIZONA_HP_CLK_DIV_WIDTH 2 /* HP_CLK_DIV - [4:3] */
  2022. #define ARIZONA_HP_IDAC_STEER 0x0004 /* HP_IDAC_STEER */
  2023. #define ARIZONA_HP_IDAC_STEER_MASK 0x0004 /* HP_IDAC_STEER */
  2024. #define ARIZONA_HP_IDAC_STEER_SHIFT 2 /* HP_IDAC_STEER */
  2025. #define ARIZONA_HP_IDAC_STEER_WIDTH 1 /* HP_IDAC_STEER */
  2026. #define ARIZONA_HP_RATE 0x0002 /* HP_RATE */
  2027. #define ARIZONA_HP_RATE_MASK 0x0002 /* HP_RATE */
  2028. #define ARIZONA_HP_RATE_SHIFT 1 /* HP_RATE */
  2029. #define ARIZONA_HP_RATE_WIDTH 1 /* HP_RATE */
  2030. #define ARIZONA_HP_POLL 0x0001 /* HP_POLL */
  2031. #define ARIZONA_HP_POLL_MASK 0x0001 /* HP_POLL */
  2032. #define ARIZONA_HP_POLL_SHIFT 0 /* HP_POLL */
  2033. #define ARIZONA_HP_POLL_WIDTH 1 /* HP_POLL */
  2034. /*
  2035. * R668 (0x29C) - Headphone Detect 2
  2036. */
  2037. #define ARIZONA_HP_DONE 0x0080 /* HP_DONE */
  2038. #define ARIZONA_HP_DONE_MASK 0x0080 /* HP_DONE */
  2039. #define ARIZONA_HP_DONE_SHIFT 7 /* HP_DONE */
  2040. #define ARIZONA_HP_DONE_WIDTH 1 /* HP_DONE */
  2041. #define ARIZONA_HP_LVL_MASK 0x007F /* HP_LVL - [6:0] */
  2042. #define ARIZONA_HP_LVL_SHIFT 0 /* HP_LVL - [6:0] */
  2043. #define ARIZONA_HP_LVL_WIDTH 7 /* HP_LVL - [6:0] */
  2044. #define ARIZONA_HP_DONE_B 0x8000 /* HP_DONE */
  2045. #define ARIZONA_HP_DONE_B_MASK 0x8000 /* HP_DONE */
  2046. #define ARIZONA_HP_DONE_B_SHIFT 15 /* HP_DONE */
  2047. #define ARIZONA_HP_DONE_B_WIDTH 1 /* HP_DONE */
  2048. #define ARIZONA_HP_LVL_B_MASK 0x7FFF /* HP_LVL - [14:0] */
  2049. #define ARIZONA_HP_LVL_B_SHIFT 0 /* HP_LVL - [14:0] */
  2050. #define ARIZONA_HP_LVL_B_WIDTH 15 /* HP_LVL - [14:0] */
  2051. /*
  2052. * R674 (0x2A2) - MICD clamp control
  2053. */
  2054. #define ARIZONA_MICD_CLAMP_MODE_MASK 0x000F /* MICD_CLAMP_MODE - [3:0] */
  2055. #define ARIZONA_MICD_CLAMP_MODE_SHIFT 0 /* MICD_CLAMP_MODE - [3:0] */
  2056. #define ARIZONA_MICD_CLAMP_MODE_WIDTH 4 /* MICD_CLAMP_MODE - [3:0] */
  2057. /*
  2058. * R675 (0x2A3) - Mic Detect 1
  2059. */
  2060. #define ARIZONA_MICD_BIAS_STARTTIME_MASK 0xF000 /* MICD_BIAS_STARTTIME - [15:12] */
  2061. #define ARIZONA_MICD_BIAS_STARTTIME_SHIFT 12 /* MICD_BIAS_STARTTIME - [15:12] */
  2062. #define ARIZONA_MICD_BIAS_STARTTIME_WIDTH 4 /* MICD_BIAS_STARTTIME - [15:12] */
  2063. #define ARIZONA_MICD_RATE_MASK 0x0F00 /* MICD_RATE - [11:8] */
  2064. #define ARIZONA_MICD_RATE_SHIFT 8 /* MICD_RATE - [11:8] */
  2065. #define ARIZONA_MICD_RATE_WIDTH 4 /* MICD_RATE - [11:8] */
  2066. #define ARIZONA_MICD_BIAS_SRC_MASK 0x0030 /* MICD_BIAS_SRC - [5:4] */
  2067. #define ARIZONA_MICD_BIAS_SRC_SHIFT 4 /* MICD_BIAS_SRC - [5:4] */
  2068. #define ARIZONA_MICD_BIAS_SRC_WIDTH 2 /* MICD_BIAS_SRC - [5:4] */
  2069. #define ARIZONA_MICD_DBTIME 0x0002 /* MICD_DBTIME */
  2070. #define ARIZONA_MICD_DBTIME_MASK 0x0002 /* MICD_DBTIME */
  2071. #define ARIZONA_MICD_DBTIME_SHIFT 1 /* MICD_DBTIME */
  2072. #define ARIZONA_MICD_DBTIME_WIDTH 1 /* MICD_DBTIME */
  2073. #define ARIZONA_MICD_ENA 0x0001 /* MICD_ENA */
  2074. #define ARIZONA_MICD_ENA_MASK 0x0001 /* MICD_ENA */
  2075. #define ARIZONA_MICD_ENA_SHIFT 0 /* MICD_ENA */
  2076. #define ARIZONA_MICD_ENA_WIDTH 1 /* MICD_ENA */
  2077. /*
  2078. * R676 (0x2A4) - Mic Detect 2
  2079. */
  2080. #define ARIZONA_MICD_LVL_SEL_MASK 0x00FF /* MICD_LVL_SEL - [7:0] */
  2081. #define ARIZONA_MICD_LVL_SEL_SHIFT 0 /* MICD_LVL_SEL - [7:0] */
  2082. #define ARIZONA_MICD_LVL_SEL_WIDTH 8 /* MICD_LVL_SEL - [7:0] */
  2083. /*
  2084. * R677 (0x2A5) - Mic Detect 3
  2085. */
  2086. #define ARIZONA_MICD_LVL_MASK 0x07FC /* MICD_LVL - [10:2] */
  2087. #define ARIZONA_MICD_LVL_SHIFT 2 /* MICD_LVL - [10:2] */
  2088. #define ARIZONA_MICD_LVL_WIDTH 9 /* MICD_LVL - [10:2] */
  2089. #define ARIZONA_MICD_VALID 0x0002 /* MICD_VALID */
  2090. #define ARIZONA_MICD_VALID_MASK 0x0002 /* MICD_VALID */
  2091. #define ARIZONA_MICD_VALID_SHIFT 1 /* MICD_VALID */
  2092. #define ARIZONA_MICD_VALID_WIDTH 1 /* MICD_VALID */
  2093. #define ARIZONA_MICD_STS 0x0001 /* MICD_STS */
  2094. #define ARIZONA_MICD_STS_MASK 0x0001 /* MICD_STS */
  2095. #define ARIZONA_MICD_STS_SHIFT 0 /* MICD_STS */
  2096. #define ARIZONA_MICD_STS_WIDTH 1 /* MICD_STS */
  2097. /*
  2098. * R707 (0x2C3) - Mic noise mix control 1
  2099. */
  2100. #define ARIZONA_MICMUTE_RATE_MASK 0x7800 /* MICMUTE_RATE - [14:11] */
  2101. #define ARIZONA_MICMUTE_RATE_SHIFT 11 /* MICMUTE_RATE - [14:11] */
  2102. #define ARIZONA_MICMUTE_RATE_WIDTH 4 /* MICMUTE_RATE - [14:11] */
  2103. #define ARIZONA_MICMUTE_MIX_ENA 0x0040 /* MICMUTE_MIX_ENA */
  2104. #define ARIZONA_MICMUTE_MIX_ENA_MASK 0x0040 /* MICMUTE_MIX_ENA */
  2105. #define ARIZONA_MICMUTE_MIX_ENA_SHIFT 6 /* MICMUTE_MIX_ENA */
  2106. #define ARIZONA_MICMUTE_MIX_ENA_WIDTH 1 /* MICMUTE_MIX_ENA */
  2107. /*
  2108. * R715 (0x2CB) - Isolation control
  2109. */
  2110. #define ARIZONA_ISOLATE_DCVDD1 0x0001 /* ISOLATE_DCVDD1 */
  2111. #define ARIZONA_ISOLATE_DCVDD1_MASK 0x0001 /* ISOLATE_DCVDD1 */
  2112. #define ARIZONA_ISOLATE_DCVDD1_SHIFT 0 /* ISOLATE_DCVDD1 */
  2113. #define ARIZONA_ISOLATE_DCVDD1_WIDTH 1 /* ISOLATE_DCVDD1 */
  2114. /*
  2115. * R723 (0x2D3) - Jack detect analogue
  2116. */
  2117. #define ARIZONA_JD2_ENA 0x0002 /* JD2_ENA */
  2118. #define ARIZONA_JD2_ENA_MASK 0x0002 /* JD2_ENA */
  2119. #define ARIZONA_JD2_ENA_SHIFT 1 /* JD2_ENA */
  2120. #define ARIZONA_JD2_ENA_WIDTH 1 /* JD2_ENA */
  2121. #define ARIZONA_JD1_ENA 0x0001 /* JD1_ENA */
  2122. #define ARIZONA_JD1_ENA_MASK 0x0001 /* JD1_ENA */
  2123. #define ARIZONA_JD1_ENA_SHIFT 0 /* JD1_ENA */
  2124. #define ARIZONA_JD1_ENA_WIDTH 1 /* JD1_ENA */
  2125. /*
  2126. * R768 (0x300) - Input Enables
  2127. */
  2128. #define ARIZONA_IN4L_ENA 0x0080 /* IN4L_ENA */
  2129. #define ARIZONA_IN4L_ENA_MASK 0x0080 /* IN4L_ENA */
  2130. #define ARIZONA_IN4L_ENA_SHIFT 7 /* IN4L_ENA */
  2131. #define ARIZONA_IN4L_ENA_WIDTH 1 /* IN4L_ENA */
  2132. #define ARIZONA_IN4R_ENA 0x0040 /* IN4R_ENA */
  2133. #define ARIZONA_IN4R_ENA_MASK 0x0040 /* IN4R_ENA */
  2134. #define ARIZONA_IN4R_ENA_SHIFT 6 /* IN4R_ENA */
  2135. #define ARIZONA_IN4R_ENA_WIDTH 1 /* IN4R_ENA */
  2136. #define ARIZONA_IN3L_ENA 0x0020 /* IN3L_ENA */
  2137. #define ARIZONA_IN3L_ENA_MASK 0x0020 /* IN3L_ENA */
  2138. #define ARIZONA_IN3L_ENA_SHIFT 5 /* IN3L_ENA */
  2139. #define ARIZONA_IN3L_ENA_WIDTH 1 /* IN3L_ENA */
  2140. #define ARIZONA_IN3R_ENA 0x0010 /* IN3R_ENA */
  2141. #define ARIZONA_IN3R_ENA_MASK 0x0010 /* IN3R_ENA */
  2142. #define ARIZONA_IN3R_ENA_SHIFT 4 /* IN3R_ENA */
  2143. #define ARIZONA_IN3R_ENA_WIDTH 1 /* IN3R_ENA */
  2144. #define ARIZONA_IN2L_ENA 0x0008 /* IN2L_ENA */
  2145. #define ARIZONA_IN2L_ENA_MASK 0x0008 /* IN2L_ENA */
  2146. #define ARIZONA_IN2L_ENA_SHIFT 3 /* IN2L_ENA */
  2147. #define ARIZONA_IN2L_ENA_WIDTH 1 /* IN2L_ENA */
  2148. #define ARIZONA_IN2R_ENA 0x0004 /* IN2R_ENA */
  2149. #define ARIZONA_IN2R_ENA_MASK 0x0004 /* IN2R_ENA */
  2150. #define ARIZONA_IN2R_ENA_SHIFT 2 /* IN2R_ENA */
  2151. #define ARIZONA_IN2R_ENA_WIDTH 1 /* IN2R_ENA */
  2152. #define ARIZONA_IN1L_ENA 0x0002 /* IN1L_ENA */
  2153. #define ARIZONA_IN1L_ENA_MASK 0x0002 /* IN1L_ENA */
  2154. #define ARIZONA_IN1L_ENA_SHIFT 1 /* IN1L_ENA */
  2155. #define ARIZONA_IN1L_ENA_WIDTH 1 /* IN1L_ENA */
  2156. #define ARIZONA_IN1R_ENA 0x0001 /* IN1R_ENA */
  2157. #define ARIZONA_IN1R_ENA_MASK 0x0001 /* IN1R_ENA */
  2158. #define ARIZONA_IN1R_ENA_SHIFT 0 /* IN1R_ENA */
  2159. #define ARIZONA_IN1R_ENA_WIDTH 1 /* IN1R_ENA */
  2160. /*
  2161. * R776 (0x308) - Input Rate
  2162. */
  2163. #define ARIZONA_IN_RATE_MASK 0x7800 /* IN_RATE - [14:11] */
  2164. #define ARIZONA_IN_RATE_SHIFT 11 /* IN_RATE - [14:11] */
  2165. #define ARIZONA_IN_RATE_WIDTH 4 /* IN_RATE - [14:11] */
  2166. /*
  2167. * R777 (0x309) - Input Volume Ramp
  2168. */
  2169. #define ARIZONA_IN_VD_RAMP_MASK 0x0070 /* IN_VD_RAMP - [6:4] */
  2170. #define ARIZONA_IN_VD_RAMP_SHIFT 4 /* IN_VD_RAMP - [6:4] */
  2171. #define ARIZONA_IN_VD_RAMP_WIDTH 3 /* IN_VD_RAMP - [6:4] */
  2172. #define ARIZONA_IN_VI_RAMP_MASK 0x0007 /* IN_VI_RAMP - [2:0] */
  2173. #define ARIZONA_IN_VI_RAMP_SHIFT 0 /* IN_VI_RAMP - [2:0] */
  2174. #define ARIZONA_IN_VI_RAMP_WIDTH 3 /* IN_VI_RAMP - [2:0] */
  2175. /*
  2176. * R784 (0x310) - IN1L Control
  2177. */
  2178. #define ARIZONA_IN1_OSR_MASK 0x6000 /* IN1_OSR - [14:13] */
  2179. #define ARIZONA_IN1_OSR_SHIFT 13 /* IN1_OSR - [14:13] */
  2180. #define ARIZONA_IN1_OSR_WIDTH 2 /* IN1_OSR - [14:13] */
  2181. #define ARIZONA_IN1_DMIC_SUP_MASK 0x1800 /* IN1_DMIC_SUP - [12:11] */
  2182. #define ARIZONA_IN1_DMIC_SUP_SHIFT 11 /* IN1_DMIC_SUP - [12:11] */
  2183. #define ARIZONA_IN1_DMIC_SUP_WIDTH 2 /* IN1_DMIC_SUP - [12:11] */
  2184. #define ARIZONA_IN1_MODE_MASK 0x0600 /* IN1_MODE - [10:9] */
  2185. #define ARIZONA_IN1_MODE_SHIFT 9 /* IN1_MODE - [10:9] */
  2186. #define ARIZONA_IN1_MODE_WIDTH 2 /* IN1_MODE - [10:9] */
  2187. #define ARIZONA_IN1L_PGA_VOL_MASK 0x00FE /* IN1L_PGA_VOL - [7:1] */
  2188. #define ARIZONA_IN1L_PGA_VOL_SHIFT 1 /* IN1L_PGA_VOL - [7:1] */
  2189. #define ARIZONA_IN1L_PGA_VOL_WIDTH 7 /* IN1L_PGA_VOL - [7:1] */
  2190. /*
  2191. * R785 (0x311) - ADC Digital Volume 1L
  2192. */
  2193. #define ARIZONA_IN_VU 0x0200 /* IN_VU */
  2194. #define ARIZONA_IN_VU_MASK 0x0200 /* IN_VU */
  2195. #define ARIZONA_IN_VU_SHIFT 9 /* IN_VU */
  2196. #define ARIZONA_IN_VU_WIDTH 1 /* IN_VU */
  2197. #define ARIZONA_IN1L_MUTE 0x0100 /* IN1L_MUTE */
  2198. #define ARIZONA_IN1L_MUTE_MASK 0x0100 /* IN1L_MUTE */
  2199. #define ARIZONA_IN1L_MUTE_SHIFT 8 /* IN1L_MUTE */
  2200. #define ARIZONA_IN1L_MUTE_WIDTH 1 /* IN1L_MUTE */
  2201. #define ARIZONA_IN1L_DIG_VOL_MASK 0x00FF /* IN1L_DIG_VOL - [7:0] */
  2202. #define ARIZONA_IN1L_DIG_VOL_SHIFT 0 /* IN1L_DIG_VOL - [7:0] */
  2203. #define ARIZONA_IN1L_DIG_VOL_WIDTH 8 /* IN1L_DIG_VOL - [7:0] */
  2204. /*
  2205. * R786 (0x312) - DMIC1L Control
  2206. */
  2207. #define ARIZONA_IN1_DMICL_DLY_MASK 0x003F /* IN1_DMICL_DLY - [5:0] */
  2208. #define ARIZONA_IN1_DMICL_DLY_SHIFT 0 /* IN1_DMICL_DLY - [5:0] */
  2209. #define ARIZONA_IN1_DMICL_DLY_WIDTH 6 /* IN1_DMICL_DLY - [5:0] */
  2210. /*
  2211. * R788 (0x314) - IN1R Control
  2212. */
  2213. #define ARIZONA_IN1R_PGA_VOL_MASK 0x00FE /* IN1R_PGA_VOL - [7:1] */
  2214. #define ARIZONA_IN1R_PGA_VOL_SHIFT 1 /* IN1R_PGA_VOL - [7:1] */
  2215. #define ARIZONA_IN1R_PGA_VOL_WIDTH 7 /* IN1R_PGA_VOL - [7:1] */
  2216. /*
  2217. * R789 (0x315) - ADC Digital Volume 1R
  2218. */
  2219. #define ARIZONA_IN_VU 0x0200 /* IN_VU */
  2220. #define ARIZONA_IN_VU_MASK 0x0200 /* IN_VU */
  2221. #define ARIZONA_IN_VU_SHIFT 9 /* IN_VU */
  2222. #define ARIZONA_IN_VU_WIDTH 1 /* IN_VU */
  2223. #define ARIZONA_IN1R_MUTE 0x0100 /* IN1R_MUTE */
  2224. #define ARIZONA_IN1R_MUTE_MASK 0x0100 /* IN1R_MUTE */
  2225. #define ARIZONA_IN1R_MUTE_SHIFT 8 /* IN1R_MUTE */
  2226. #define ARIZONA_IN1R_MUTE_WIDTH 1 /* IN1R_MUTE */
  2227. #define ARIZONA_IN1R_DIG_VOL_MASK 0x00FF /* IN1R_DIG_VOL - [7:0] */
  2228. #define ARIZONA_IN1R_DIG_VOL_SHIFT 0 /* IN1R_DIG_VOL - [7:0] */
  2229. #define ARIZONA_IN1R_DIG_VOL_WIDTH 8 /* IN1R_DIG_VOL - [7:0] */
  2230. /*
  2231. * R790 (0x316) - DMIC1R Control
  2232. */
  2233. #define ARIZONA_IN1_DMICR_DLY_MASK 0x003F /* IN1_DMICR_DLY - [5:0] */
  2234. #define ARIZONA_IN1_DMICR_DLY_SHIFT 0 /* IN1_DMICR_DLY - [5:0] */
  2235. #define ARIZONA_IN1_DMICR_DLY_WIDTH 6 /* IN1_DMICR_DLY - [5:0] */
  2236. /*
  2237. * R792 (0x318) - IN2L Control
  2238. */
  2239. #define ARIZONA_IN2_OSR_MASK 0x6000 /* IN2_OSR - [14:13] */
  2240. #define ARIZONA_IN2_OSR_SHIFT 13 /* IN2_OSR - [14:13] */
  2241. #define ARIZONA_IN2_OSR_WIDTH 2 /* IN2_OSR - [14:13] */
  2242. #define ARIZONA_IN2_DMIC_SUP_MASK 0x1800 /* IN2_DMIC_SUP - [12:11] */
  2243. #define ARIZONA_IN2_DMIC_SUP_SHIFT 11 /* IN2_DMIC_SUP - [12:11] */
  2244. #define ARIZONA_IN2_DMIC_SUP_WIDTH 2 /* IN2_DMIC_SUP - [12:11] */
  2245. #define ARIZONA_IN2_MODE_MASK 0x0600 /* IN2_MODE - [10:9] */
  2246. #define ARIZONA_IN2_MODE_SHIFT 9 /* IN2_MODE - [10:9] */
  2247. #define ARIZONA_IN2_MODE_WIDTH 2 /* IN2_MODE - [10:9] */
  2248. #define ARIZONA_IN2L_PGA_VOL_MASK 0x00FE /* IN2L_PGA_VOL - [7:1] */
  2249. #define ARIZONA_IN2L_PGA_VOL_SHIFT 1 /* IN2L_PGA_VOL - [7:1] */
  2250. #define ARIZONA_IN2L_PGA_VOL_WIDTH 7 /* IN2L_PGA_VOL - [7:1] */
  2251. /*
  2252. * R793 (0x319) - ADC Digital Volume 2L
  2253. */
  2254. #define ARIZONA_IN_VU 0x0200 /* IN_VU */
  2255. #define ARIZONA_IN_VU_MASK 0x0200 /* IN_VU */
  2256. #define ARIZONA_IN_VU_SHIFT 9 /* IN_VU */
  2257. #define ARIZONA_IN_VU_WIDTH 1 /* IN_VU */
  2258. #define ARIZONA_IN2L_MUTE 0x0100 /* IN2L_MUTE */
  2259. #define ARIZONA_IN2L_MUTE_MASK 0x0100 /* IN2L_MUTE */
  2260. #define ARIZONA_IN2L_MUTE_SHIFT 8 /* IN2L_MUTE */
  2261. #define ARIZONA_IN2L_MUTE_WIDTH 1 /* IN2L_MUTE */
  2262. #define ARIZONA_IN2L_DIG_VOL_MASK 0x00FF /* IN2L_DIG_VOL - [7:0] */
  2263. #define ARIZONA_IN2L_DIG_VOL_SHIFT 0 /* IN2L_DIG_VOL - [7:0] */
  2264. #define ARIZONA_IN2L_DIG_VOL_WIDTH 8 /* IN2L_DIG_VOL - [7:0] */
  2265. /*
  2266. * R794 (0x31A) - DMIC2L Control
  2267. */
  2268. #define ARIZONA_IN2_DMICL_DLY_MASK 0x003F /* IN2_DMICL_DLY - [5:0] */
  2269. #define ARIZONA_IN2_DMICL_DLY_SHIFT 0 /* IN2_DMICL_DLY - [5:0] */
  2270. #define ARIZONA_IN2_DMICL_DLY_WIDTH 6 /* IN2_DMICL_DLY - [5:0] */
  2271. /*
  2272. * R796 (0x31C) - IN2R Control
  2273. */
  2274. #define ARIZONA_IN2R_PGA_VOL_MASK 0x00FE /* IN2R_PGA_VOL - [7:1] */
  2275. #define ARIZONA_IN2R_PGA_VOL_SHIFT 1 /* IN2R_PGA_VOL - [7:1] */
  2276. #define ARIZONA_IN2R_PGA_VOL_WIDTH 7 /* IN2R_PGA_VOL - [7:1] */
  2277. /*
  2278. * R797 (0x31D) - ADC Digital Volume 2R
  2279. */
  2280. #define ARIZONA_IN_VU 0x0200 /* IN_VU */
  2281. #define ARIZONA_IN_VU_MASK 0x0200 /* IN_VU */
  2282. #define ARIZONA_IN_VU_SHIFT 9 /* IN_VU */
  2283. #define ARIZONA_IN_VU_WIDTH 1 /* IN_VU */
  2284. #define ARIZONA_IN2R_MUTE 0x0100 /* IN2R_MUTE */
  2285. #define ARIZONA_IN2R_MUTE_MASK 0x0100 /* IN2R_MUTE */
  2286. #define ARIZONA_IN2R_MUTE_SHIFT 8 /* IN2R_MUTE */
  2287. #define ARIZONA_IN2R_MUTE_WIDTH 1 /* IN2R_MUTE */
  2288. #define ARIZONA_IN2R_DIG_VOL_MASK 0x00FF /* IN2R_DIG_VOL - [7:0] */
  2289. #define ARIZONA_IN2R_DIG_VOL_SHIFT 0 /* IN2R_DIG_VOL - [7:0] */
  2290. #define ARIZONA_IN2R_DIG_VOL_WIDTH 8 /* IN2R_DIG_VOL - [7:0] */
  2291. /*
  2292. * R798 (0x31E) - DMIC2R Control
  2293. */
  2294. #define ARIZONA_IN2_DMICR_DLY_MASK 0x003F /* IN2_DMICR_DLY - [5:0] */
  2295. #define ARIZONA_IN2_DMICR_DLY_SHIFT 0 /* IN2_DMICR_DLY - [5:0] */
  2296. #define ARIZONA_IN2_DMICR_DLY_WIDTH 6 /* IN2_DMICR_DLY - [5:0] */
  2297. /*
  2298. * R800 (0x320) - IN3L Control
  2299. */
  2300. #define ARIZONA_IN3_OSR_MASK 0x6000 /* IN3_OSR - [14:13] */
  2301. #define ARIZONA_IN3_OSR_SHIFT 13 /* IN3_OSR - [14:13] */
  2302. #define ARIZONA_IN3_OSR_WIDTH 2 /* IN3_OSR - [14:13] */
  2303. #define ARIZONA_IN3_DMIC_SUP_MASK 0x1800 /* IN3_DMIC_SUP - [12:11] */
  2304. #define ARIZONA_IN3_DMIC_SUP_SHIFT 11 /* IN3_DMIC_SUP - [12:11] */
  2305. #define ARIZONA_IN3_DMIC_SUP_WIDTH 2 /* IN3_DMIC_SUP - [12:11] */
  2306. #define ARIZONA_IN3_MODE_MASK 0x0600 /* IN3_MODE - [10:9] */
  2307. #define ARIZONA_IN3_MODE_SHIFT 9 /* IN3_MODE - [10:9] */
  2308. #define ARIZONA_IN3_MODE_WIDTH 2 /* IN3_MODE - [10:9] */
  2309. #define ARIZONA_IN3L_PGA_VOL_MASK 0x00FE /* IN3L_PGA_VOL - [7:1] */
  2310. #define ARIZONA_IN3L_PGA_VOL_SHIFT 1 /* IN3L_PGA_VOL - [7:1] */
  2311. #define ARIZONA_IN3L_PGA_VOL_WIDTH 7 /* IN3L_PGA_VOL - [7:1] */
  2312. /*
  2313. * R801 (0x321) - ADC Digital Volume 3L
  2314. */
  2315. #define ARIZONA_IN_VU 0x0200 /* IN_VU */
  2316. #define ARIZONA_IN_VU_MASK 0x0200 /* IN_VU */
  2317. #define ARIZONA_IN_VU_SHIFT 9 /* IN_VU */
  2318. #define ARIZONA_IN_VU_WIDTH 1 /* IN_VU */
  2319. #define ARIZONA_IN3L_MUTE 0x0100 /* IN3L_MUTE */
  2320. #define ARIZONA_IN3L_MUTE_MASK 0x0100 /* IN3L_MUTE */
  2321. #define ARIZONA_IN3L_MUTE_SHIFT 8 /* IN3L_MUTE */
  2322. #define ARIZONA_IN3L_MUTE_WIDTH 1 /* IN3L_MUTE */
  2323. #define ARIZONA_IN3L_DIG_VOL_MASK 0x00FF /* IN3L_DIG_VOL - [7:0] */
  2324. #define ARIZONA_IN3L_DIG_VOL_SHIFT 0 /* IN3L_DIG_VOL - [7:0] */
  2325. #define ARIZONA_IN3L_DIG_VOL_WIDTH 8 /* IN3L_DIG_VOL - [7:0] */
  2326. /*
  2327. * R802 (0x322) - DMIC3L Control
  2328. */
  2329. #define ARIZONA_IN3_DMICL_DLY_MASK 0x003F /* IN3_DMICL_DLY - [5:0] */
  2330. #define ARIZONA_IN3_DMICL_DLY_SHIFT 0 /* IN3_DMICL_DLY - [5:0] */
  2331. #define ARIZONA_IN3_DMICL_DLY_WIDTH 6 /* IN3_DMICL_DLY - [5:0] */
  2332. /*
  2333. * R804 (0x324) - IN3R Control
  2334. */
  2335. #define ARIZONA_IN3R_PGA_VOL_MASK 0x00FE /* IN3R_PGA_VOL - [7:1] */
  2336. #define ARIZONA_IN3R_PGA_VOL_SHIFT 1 /* IN3R_PGA_VOL - [7:1] */
  2337. #define ARIZONA_IN3R_PGA_VOL_WIDTH 7 /* IN3R_PGA_VOL - [7:1] */
  2338. /*
  2339. * R805 (0x325) - ADC Digital Volume 3R
  2340. */
  2341. #define ARIZONA_IN_VU 0x0200 /* IN_VU */
  2342. #define ARIZONA_IN_VU_MASK 0x0200 /* IN_VU */
  2343. #define ARIZONA_IN_VU_SHIFT 9 /* IN_VU */
  2344. #define ARIZONA_IN_VU_WIDTH 1 /* IN_VU */
  2345. #define ARIZONA_IN3R_MUTE 0x0100 /* IN3R_MUTE */
  2346. #define ARIZONA_IN3R_MUTE_MASK 0x0100 /* IN3R_MUTE */
  2347. #define ARIZONA_IN3R_MUTE_SHIFT 8 /* IN3R_MUTE */
  2348. #define ARIZONA_IN3R_MUTE_WIDTH 1 /* IN3R_MUTE */
  2349. #define ARIZONA_IN3R_DIG_VOL_MASK 0x00FF /* IN3R_DIG_VOL - [7:0] */
  2350. #define ARIZONA_IN3R_DIG_VOL_SHIFT 0 /* IN3R_DIG_VOL - [7:0] */
  2351. #define ARIZONA_IN3R_DIG_VOL_WIDTH 8 /* IN3R_DIG_VOL - [7:0] */
  2352. /*
  2353. * R806 (0x326) - DMIC3R Control
  2354. */
  2355. #define ARIZONA_IN3_DMICR_DLY_MASK 0x003F /* IN3_DMICR_DLY - [5:0] */
  2356. #define ARIZONA_IN3_DMICR_DLY_SHIFT 0 /* IN3_DMICR_DLY - [5:0] */
  2357. #define ARIZONA_IN3_DMICR_DLY_WIDTH 6 /* IN3_DMICR_DLY - [5:0] */
  2358. /*
  2359. * R808 (0x328) - IN4 Control
  2360. */
  2361. #define ARIZONA_IN4_OSR_MASK 0x6000 /* IN4_OSR - [14:13] */
  2362. #define ARIZONA_IN4_OSR_SHIFT 13 /* IN4_OSR - [14:13] */
  2363. #define ARIZONA_IN4_OSR_WIDTH 2 /* IN4_OSR - [14:13] */
  2364. #define ARIZONA_IN4_DMIC_SUP_MASK 0x1800 /* IN4_DMIC_SUP - [12:11] */
  2365. #define ARIZONA_IN4_DMIC_SUP_SHIFT 11 /* IN4_DMIC_SUP - [12:11] */
  2366. #define ARIZONA_IN4_DMIC_SUP_WIDTH 2 /* IN4_DMIC_SUP - [12:11] */
  2367. /*
  2368. * R809 (0x329) - ADC Digital Volume 4L
  2369. */
  2370. #define ARIZONA_IN_VU 0x0200 /* IN_VU */
  2371. #define ARIZONA_IN_VU_MASK 0x0200 /* IN_VU */
  2372. #define ARIZONA_IN_VU_SHIFT 9 /* IN_VU */
  2373. #define ARIZONA_IN_VU_WIDTH 1 /* IN_VU */
  2374. #define ARIZONA_IN4L_MUTE 0x0100 /* IN4L_MUTE */
  2375. #define ARIZONA_IN4L_MUTE_MASK 0x0100 /* IN4L_MUTE */
  2376. #define ARIZONA_IN4L_MUTE_SHIFT 8 /* IN4L_MUTE */
  2377. #define ARIZONA_IN4L_MUTE_WIDTH 1 /* IN4L_MUTE */
  2378. #define ARIZONA_IN4L_DIG_VOL_MASK 0x00FF /* IN4L_DIG_VOL - [7:0] */
  2379. #define ARIZONA_IN4L_DIG_VOL_SHIFT 0 /* IN4L_DIG_VOL - [7:0] */
  2380. #define ARIZONA_IN4L_DIG_VOL_WIDTH 8 /* IN4L_DIG_VOL - [7:0] */
  2381. /*
  2382. * R810 (0x32A) - DMIC4L Control
  2383. */
  2384. #define ARIZONA_IN4L_DMIC_DLY_MASK 0x003F /* IN4L_DMIC_DLY - [5:0] */
  2385. #define ARIZONA_IN4L_DMIC_DLY_SHIFT 0 /* IN4L_DMIC_DLY - [5:0] */
  2386. #define ARIZONA_IN4L_DMIC_DLY_WIDTH 6 /* IN4L_DMIC_DLY - [5:0] */
  2387. /*
  2388. * R813 (0x32D) - ADC Digital Volume 4R
  2389. */
  2390. #define ARIZONA_IN_VU 0x0200 /* IN_VU */
  2391. #define ARIZONA_IN_VU_MASK 0x0200 /* IN_VU */
  2392. #define ARIZONA_IN_VU_SHIFT 9 /* IN_VU */
  2393. #define ARIZONA_IN_VU_WIDTH 1 /* IN_VU */
  2394. #define ARIZONA_IN4R_MUTE 0x0100 /* IN4R_MUTE */
  2395. #define ARIZONA_IN4R_MUTE_MASK 0x0100 /* IN4R_MUTE */
  2396. #define ARIZONA_IN4R_MUTE_SHIFT 8 /* IN4R_MUTE */
  2397. #define ARIZONA_IN4R_MUTE_WIDTH 1 /* IN4R_MUTE */
  2398. #define ARIZONA_IN4R_DIG_VOL_MASK 0x00FF /* IN4R_DIG_VOL - [7:0] */
  2399. #define ARIZONA_IN4R_DIG_VOL_SHIFT 0 /* IN4R_DIG_VOL - [7:0] */
  2400. #define ARIZONA_IN4R_DIG_VOL_WIDTH 8 /* IN4R_DIG_VOL - [7:0] */
  2401. /*
  2402. * R814 (0x32E) - DMIC4R Control
  2403. */
  2404. #define ARIZONA_IN4R_DMIC_DLY_MASK 0x003F /* IN4R_DMIC_DLY - [5:0] */
  2405. #define ARIZONA_IN4R_DMIC_DLY_SHIFT 0 /* IN4R_DMIC_DLY - [5:0] */
  2406. #define ARIZONA_IN4R_DMIC_DLY_WIDTH 6 /* IN4R_DMIC_DLY - [5:0] */
  2407. /*
  2408. * R1024 (0x400) - Output Enables 1
  2409. */
  2410. #define ARIZONA_OUT6L_ENA 0x0800 /* OUT6L_ENA */
  2411. #define ARIZONA_OUT6L_ENA_MASK 0x0800 /* OUT6L_ENA */
  2412. #define ARIZONA_OUT6L_ENA_SHIFT 11 /* OUT6L_ENA */
  2413. #define ARIZONA_OUT6L_ENA_WIDTH 1 /* OUT6L_ENA */
  2414. #define ARIZONA_OUT6R_ENA 0x0400 /* OUT6R_ENA */
  2415. #define ARIZONA_OUT6R_ENA_MASK 0x0400 /* OUT6R_ENA */
  2416. #define ARIZONA_OUT6R_ENA_SHIFT 10 /* OUT6R_ENA */
  2417. #define ARIZONA_OUT6R_ENA_WIDTH 1 /* OUT6R_ENA */
  2418. #define ARIZONA_OUT5L_ENA 0x0200 /* OUT5L_ENA */
  2419. #define ARIZONA_OUT5L_ENA_MASK 0x0200 /* OUT5L_ENA */
  2420. #define ARIZONA_OUT5L_ENA_SHIFT 9 /* OUT5L_ENA */
  2421. #define ARIZONA_OUT5L_ENA_WIDTH 1 /* OUT5L_ENA */
  2422. #define ARIZONA_OUT5R_ENA 0x0100 /* OUT5R_ENA */
  2423. #define ARIZONA_OUT5R_ENA_MASK 0x0100 /* OUT5R_ENA */
  2424. #define ARIZONA_OUT5R_ENA_SHIFT 8 /* OUT5R_ENA */
  2425. #define ARIZONA_OUT5R_ENA_WIDTH 1 /* OUT5R_ENA */
  2426. #define ARIZONA_OUT4L_ENA 0x0080 /* OUT4L_ENA */
  2427. #define ARIZONA_OUT4L_ENA_MASK 0x0080 /* OUT4L_ENA */
  2428. #define ARIZONA_OUT4L_ENA_SHIFT 7 /* OUT4L_ENA */
  2429. #define ARIZONA_OUT4L_ENA_WIDTH 1 /* OUT4L_ENA */
  2430. #define ARIZONA_OUT4R_ENA 0x0040 /* OUT4R_ENA */
  2431. #define ARIZONA_OUT4R_ENA_MASK 0x0040 /* OUT4R_ENA */
  2432. #define ARIZONA_OUT4R_ENA_SHIFT 6 /* OUT4R_ENA */
  2433. #define ARIZONA_OUT4R_ENA_WIDTH 1 /* OUT4R_ENA */
  2434. #define ARIZONA_OUT3L_ENA 0x0020 /* OUT3L_ENA */
  2435. #define ARIZONA_OUT3L_ENA_MASK 0x0020 /* OUT3L_ENA */
  2436. #define ARIZONA_OUT3L_ENA_SHIFT 5 /* OUT3L_ENA */
  2437. #define ARIZONA_OUT3L_ENA_WIDTH 1 /* OUT3L_ENA */
  2438. #define ARIZONA_OUT3R_ENA 0x0010 /* OUT3R_ENA */
  2439. #define ARIZONA_OUT3R_ENA_MASK 0x0010 /* OUT3R_ENA */
  2440. #define ARIZONA_OUT3R_ENA_SHIFT 4 /* OUT3R_ENA */
  2441. #define ARIZONA_OUT3R_ENA_WIDTH 1 /* OUT3R_ENA */
  2442. #define ARIZONA_OUT2L_ENA 0x0008 /* OUT2L_ENA */
  2443. #define ARIZONA_OUT2L_ENA_MASK 0x0008 /* OUT2L_ENA */
  2444. #define ARIZONA_OUT2L_ENA_SHIFT 3 /* OUT2L_ENA */
  2445. #define ARIZONA_OUT2L_ENA_WIDTH 1 /* OUT2L_ENA */
  2446. #define ARIZONA_OUT2R_ENA 0x0004 /* OUT2R_ENA */
  2447. #define ARIZONA_OUT2R_ENA_MASK 0x0004 /* OUT2R_ENA */
  2448. #define ARIZONA_OUT2R_ENA_SHIFT 2 /* OUT2R_ENA */
  2449. #define ARIZONA_OUT2R_ENA_WIDTH 1 /* OUT2R_ENA */
  2450. #define ARIZONA_OUT1L_ENA 0x0002 /* OUT1L_ENA */
  2451. #define ARIZONA_OUT1L_ENA_MASK 0x0002 /* OUT1L_ENA */
  2452. #define ARIZONA_OUT1L_ENA_SHIFT 1 /* OUT1L_ENA */
  2453. #define ARIZONA_OUT1L_ENA_WIDTH 1 /* OUT1L_ENA */
  2454. #define ARIZONA_OUT1R_ENA 0x0001 /* OUT1R_ENA */
  2455. #define ARIZONA_OUT1R_ENA_MASK 0x0001 /* OUT1R_ENA */
  2456. #define ARIZONA_OUT1R_ENA_SHIFT 0 /* OUT1R_ENA */
  2457. #define ARIZONA_OUT1R_ENA_WIDTH 1 /* OUT1R_ENA */
  2458. /*
  2459. * R1025 (0x401) - Output Status 1
  2460. */
  2461. #define ARIZONA_OUT6L_ENA_STS 0x0800 /* OUT6L_ENA_STS */
  2462. #define ARIZONA_OUT6L_ENA_STS_MASK 0x0800 /* OUT6L_ENA_STS */
  2463. #define ARIZONA_OUT6L_ENA_STS_SHIFT 11 /* OUT6L_ENA_STS */
  2464. #define ARIZONA_OUT6L_ENA_STS_WIDTH 1 /* OUT6L_ENA_STS */
  2465. #define ARIZONA_OUT6R_ENA_STS 0x0400 /* OUT6R_ENA_STS */
  2466. #define ARIZONA_OUT6R_ENA_STS_MASK 0x0400 /* OUT6R_ENA_STS */
  2467. #define ARIZONA_OUT6R_ENA_STS_SHIFT 10 /* OUT6R_ENA_STS */
  2468. #define ARIZONA_OUT6R_ENA_STS_WIDTH 1 /* OUT6R_ENA_STS */
  2469. #define ARIZONA_OUT5L_ENA_STS 0x0200 /* OUT5L_ENA_STS */
  2470. #define ARIZONA_OUT5L_ENA_STS_MASK 0x0200 /* OUT5L_ENA_STS */
  2471. #define ARIZONA_OUT5L_ENA_STS_SHIFT 9 /* OUT5L_ENA_STS */
  2472. #define ARIZONA_OUT5L_ENA_STS_WIDTH 1 /* OUT5L_ENA_STS */
  2473. #define ARIZONA_OUT5R_ENA_STS 0x0100 /* OUT5R_ENA_STS */
  2474. #define ARIZONA_OUT5R_ENA_STS_MASK 0x0100 /* OUT5R_ENA_STS */
  2475. #define ARIZONA_OUT5R_ENA_STS_SHIFT 8 /* OUT5R_ENA_STS */
  2476. #define ARIZONA_OUT5R_ENA_STS_WIDTH 1 /* OUT5R_ENA_STS */
  2477. #define ARIZONA_OUT4L_ENA_STS 0x0080 /* OUT4L_ENA_STS */
  2478. #define ARIZONA_OUT4L_ENA_STS_MASK 0x0080 /* OUT4L_ENA_STS */
  2479. #define ARIZONA_OUT4L_ENA_STS_SHIFT 7 /* OUT4L_ENA_STS */
  2480. #define ARIZONA_OUT4L_ENA_STS_WIDTH 1 /* OUT4L_ENA_STS */
  2481. #define ARIZONA_OUT4R_ENA_STS 0x0040 /* OUT4R_ENA_STS */
  2482. #define ARIZONA_OUT4R_ENA_STS_MASK 0x0040 /* OUT4R_ENA_STS */
  2483. #define ARIZONA_OUT4R_ENA_STS_SHIFT 6 /* OUT4R_ENA_STS */
  2484. #define ARIZONA_OUT4R_ENA_STS_WIDTH 1 /* OUT4R_ENA_STS */
  2485. /*
  2486. * R1032 (0x408) - Output Rate 1
  2487. */
  2488. #define ARIZONA_OUT_RATE_MASK 0x7800 /* OUT_RATE - [14:11] */
  2489. #define ARIZONA_OUT_RATE_SHIFT 11 /* OUT_RATE - [14:11] */
  2490. #define ARIZONA_OUT_RATE_WIDTH 4 /* OUT_RATE - [14:11] */
  2491. /*
  2492. * R1033 (0x409) - Output Volume Ramp
  2493. */
  2494. #define ARIZONA_OUT_VD_RAMP_MASK 0x0070 /* OUT_VD_RAMP - [6:4] */
  2495. #define ARIZONA_OUT_VD_RAMP_SHIFT 4 /* OUT_VD_RAMP - [6:4] */
  2496. #define ARIZONA_OUT_VD_RAMP_WIDTH 3 /* OUT_VD_RAMP - [6:4] */
  2497. #define ARIZONA_OUT_VI_RAMP_MASK 0x0007 /* OUT_VI_RAMP - [2:0] */
  2498. #define ARIZONA_OUT_VI_RAMP_SHIFT 0 /* OUT_VI_RAMP - [2:0] */
  2499. #define ARIZONA_OUT_VI_RAMP_WIDTH 3 /* OUT_VI_RAMP - [2:0] */
  2500. /*
  2501. * R1040 (0x410) - Output Path Config 1L
  2502. */
  2503. #define ARIZONA_OUT1_LP_MODE 0x8000 /* OUT1_LP_MODE */
  2504. #define ARIZONA_OUT1_LP_MODE_MASK 0x8000 /* OUT1_LP_MODE */
  2505. #define ARIZONA_OUT1_LP_MODE_SHIFT 15 /* OUT1_LP_MODE */
  2506. #define ARIZONA_OUT1_LP_MODE_WIDTH 1 /* OUT1_LP_MODE */
  2507. #define ARIZONA_OUT1_OSR 0x2000 /* OUT1_OSR */
  2508. #define ARIZONA_OUT1_OSR_MASK 0x2000 /* OUT1_OSR */
  2509. #define ARIZONA_OUT1_OSR_SHIFT 13 /* OUT1_OSR */
  2510. #define ARIZONA_OUT1_OSR_WIDTH 1 /* OUT1_OSR */
  2511. #define ARIZONA_OUT1_MONO 0x1000 /* OUT1_MONO */
  2512. #define ARIZONA_OUT1_MONO_MASK 0x1000 /* OUT1_MONO */
  2513. #define ARIZONA_OUT1_MONO_SHIFT 12 /* OUT1_MONO */
  2514. #define ARIZONA_OUT1_MONO_WIDTH 1 /* OUT1_MONO */
  2515. #define ARIZONA_OUT1L_ANC_SRC_MASK 0x0C00 /* OUT1L_ANC_SRC - [11:10] */
  2516. #define ARIZONA_OUT1L_ANC_SRC_SHIFT 10 /* OUT1L_ANC_SRC - [11:10] */
  2517. #define ARIZONA_OUT1L_ANC_SRC_WIDTH 2 /* OUT1L_ANC_SRC - [11:10] */
  2518. #define ARIZONA_OUT1L_PGA_VOL_MASK 0x00FE /* OUT1L_PGA_VOL - [7:1] */
  2519. #define ARIZONA_OUT1L_PGA_VOL_SHIFT 1 /* OUT1L_PGA_VOL - [7:1] */
  2520. #define ARIZONA_OUT1L_PGA_VOL_WIDTH 7 /* OUT1L_PGA_VOL - [7:1] */
  2521. /*
  2522. * R1041 (0x411) - DAC Digital Volume 1L
  2523. */
  2524. #define ARIZONA_OUT_VU 0x0200 /* OUT_VU */
  2525. #define ARIZONA_OUT_VU_MASK 0x0200 /* OUT_VU */
  2526. #define ARIZONA_OUT_VU_SHIFT 9 /* OUT_VU */
  2527. #define ARIZONA_OUT_VU_WIDTH 1 /* OUT_VU */
  2528. #define ARIZONA_OUT1L_MUTE 0x0100 /* OUT1L_MUTE */
  2529. #define ARIZONA_OUT1L_MUTE_MASK 0x0100 /* OUT1L_MUTE */
  2530. #define ARIZONA_OUT1L_MUTE_SHIFT 8 /* OUT1L_MUTE */
  2531. #define ARIZONA_OUT1L_MUTE_WIDTH 1 /* OUT1L_MUTE */
  2532. #define ARIZONA_OUT1L_VOL_MASK 0x00FF /* OUT1L_VOL - [7:0] */
  2533. #define ARIZONA_OUT1L_VOL_SHIFT 0 /* OUT1L_VOL - [7:0] */
  2534. #define ARIZONA_OUT1L_VOL_WIDTH 8 /* OUT1L_VOL - [7:0] */
  2535. /*
  2536. * R1042 (0x412) - DAC Volume Limit 1L
  2537. */
  2538. #define ARIZONA_OUT1L_VOL_LIM_MASK 0x00FF /* OUT1L_VOL_LIM - [7:0] */
  2539. #define ARIZONA_OUT1L_VOL_LIM_SHIFT 0 /* OUT1L_VOL_LIM - [7:0] */
  2540. #define ARIZONA_OUT1L_VOL_LIM_WIDTH 8 /* OUT1L_VOL_LIM - [7:0] */
  2541. /*
  2542. * R1043 (0x413) - Noise Gate Select 1L
  2543. */
  2544. #define ARIZONA_OUT1L_NGATE_SRC_MASK 0x0FFF /* OUT1L_NGATE_SRC - [11:0] */
  2545. #define ARIZONA_OUT1L_NGATE_SRC_SHIFT 0 /* OUT1L_NGATE_SRC - [11:0] */
  2546. #define ARIZONA_OUT1L_NGATE_SRC_WIDTH 12 /* OUT1L_NGATE_SRC - [11:0] */
  2547. /*
  2548. * R1044 (0x414) - Output Path Config 1R
  2549. */
  2550. #define ARIZONA_OUT1R_ANC_SRC_MASK 0x0C00 /* OUT1R_ANC_SRC - [11:10] */
  2551. #define ARIZONA_OUT1R_ANC_SRC_SHIFT 10 /* OUT1R_ANC_SRC - [11:10] */
  2552. #define ARIZONA_OUT1R_ANC_SRC_WIDTH 2 /* OUT1R_ANC_SRC - [11:10] */
  2553. #define ARIZONA_OUT1R_PGA_VOL_MASK 0x00FE /* OUT1R_PGA_VOL - [7:1] */
  2554. #define ARIZONA_OUT1R_PGA_VOL_SHIFT 1 /* OUT1R_PGA_VOL - [7:1] */
  2555. #define ARIZONA_OUT1R_PGA_VOL_WIDTH 7 /* OUT1R_PGA_VOL - [7:1] */
  2556. /*
  2557. * R1045 (0x415) - DAC Digital Volume 1R
  2558. */
  2559. #define ARIZONA_OUT_VU 0x0200 /* OUT_VU */
  2560. #define ARIZONA_OUT_VU_MASK 0x0200 /* OUT_VU */
  2561. #define ARIZONA_OUT_VU_SHIFT 9 /* OUT_VU */
  2562. #define ARIZONA_OUT_VU_WIDTH 1 /* OUT_VU */
  2563. #define ARIZONA_OUT1R_MUTE 0x0100 /* OUT1R_MUTE */
  2564. #define ARIZONA_OUT1R_MUTE_MASK 0x0100 /* OUT1R_MUTE */
  2565. #define ARIZONA_OUT1R_MUTE_SHIFT 8 /* OUT1R_MUTE */
  2566. #define ARIZONA_OUT1R_MUTE_WIDTH 1 /* OUT1R_MUTE */
  2567. #define ARIZONA_OUT1R_VOL_MASK 0x00FF /* OUT1R_VOL - [7:0] */
  2568. #define ARIZONA_OUT1R_VOL_SHIFT 0 /* OUT1R_VOL - [7:0] */
  2569. #define ARIZONA_OUT1R_VOL_WIDTH 8 /* OUT1R_VOL - [7:0] */
  2570. /*
  2571. * R1046 (0x416) - DAC Volume Limit 1R
  2572. */
  2573. #define ARIZONA_OUT1R_VOL_LIM_MASK 0x00FF /* OUT1R_VOL_LIM - [7:0] */
  2574. #define ARIZONA_OUT1R_VOL_LIM_SHIFT 0 /* OUT1R_VOL_LIM - [7:0] */
  2575. #define ARIZONA_OUT1R_VOL_LIM_WIDTH 8 /* OUT1R_VOL_LIM - [7:0] */
  2576. /*
  2577. * R1047 (0x417) - Noise Gate Select 1R
  2578. */
  2579. #define ARIZONA_OUT1R_NGATE_SRC_MASK 0x0FFF /* OUT1R_NGATE_SRC - [11:0] */
  2580. #define ARIZONA_OUT1R_NGATE_SRC_SHIFT 0 /* OUT1R_NGATE_SRC - [11:0] */
  2581. #define ARIZONA_OUT1R_NGATE_SRC_WIDTH 12 /* OUT1R_NGATE_SRC - [11:0] */
  2582. /*
  2583. * R1048 (0x418) - Output Path Config 2L
  2584. */
  2585. #define ARIZONA_OUT2_LP_MODE 0x8000 /* OUT2_LP_MODE */
  2586. #define ARIZONA_OUT2_LP_MODE_MASK 0x8000 /* OUT2_LP_MODE */
  2587. #define ARIZONA_OUT2_LP_MODE_SHIFT 15 /* OUT2_LP_MODE */
  2588. #define ARIZONA_OUT2_LP_MODE_WIDTH 1 /* OUT2_LP_MODE */
  2589. #define ARIZONA_OUT2_OSR 0x2000 /* OUT2_OSR */
  2590. #define ARIZONA_OUT2_OSR_MASK 0x2000 /* OUT2_OSR */
  2591. #define ARIZONA_OUT2_OSR_SHIFT 13 /* OUT2_OSR */
  2592. #define ARIZONA_OUT2_OSR_WIDTH 1 /* OUT2_OSR */
  2593. #define ARIZONA_OUT2_MONO 0x1000 /* OUT2_MONO */
  2594. #define ARIZONA_OUT2_MONO_MASK 0x1000 /* OUT2_MONO */
  2595. #define ARIZONA_OUT2_MONO_SHIFT 12 /* OUT2_MONO */
  2596. #define ARIZONA_OUT2_MONO_WIDTH 1 /* OUT2_MONO */
  2597. #define ARIZONA_OUT2L_ANC_SRC_MASK 0x0C00 /* OUT2L_ANC_SRC - [11:10] */
  2598. #define ARIZONA_OUT2L_ANC_SRC_SHIFT 10 /* OUT2L_ANC_SRC - [11:10] */
  2599. #define ARIZONA_OUT2L_ANC_SRC_WIDTH 2 /* OUT2L_ANC_SRC - [11:10] */
  2600. #define ARIZONA_OUT2L_PGA_VOL_MASK 0x00FE /* OUT2L_PGA_VOL - [7:1] */
  2601. #define ARIZONA_OUT2L_PGA_VOL_SHIFT 1 /* OUT2L_PGA_VOL - [7:1] */
  2602. #define ARIZONA_OUT2L_PGA_VOL_WIDTH 7 /* OUT2L_PGA_VOL - [7:1] */
  2603. /*
  2604. * R1049 (0x419) - DAC Digital Volume 2L
  2605. */
  2606. #define ARIZONA_OUT_VU 0x0200 /* OUT_VU */
  2607. #define ARIZONA_OUT_VU_MASK 0x0200 /* OUT_VU */
  2608. #define ARIZONA_OUT_VU_SHIFT 9 /* OUT_VU */
  2609. #define ARIZONA_OUT_VU_WIDTH 1 /* OUT_VU */
  2610. #define ARIZONA_OUT2L_MUTE 0x0100 /* OUT2L_MUTE */
  2611. #define ARIZONA_OUT2L_MUTE_MASK 0x0100 /* OUT2L_MUTE */
  2612. #define ARIZONA_OUT2L_MUTE_SHIFT 8 /* OUT2L_MUTE */
  2613. #define ARIZONA_OUT2L_MUTE_WIDTH 1 /* OUT2L_MUTE */
  2614. #define ARIZONA_OUT2L_VOL_MASK 0x00FF /* OUT2L_VOL - [7:0] */
  2615. #define ARIZONA_OUT2L_VOL_SHIFT 0 /* OUT2L_VOL - [7:0] */
  2616. #define ARIZONA_OUT2L_VOL_WIDTH 8 /* OUT2L_VOL - [7:0] */
  2617. /*
  2618. * R1050 (0x41A) - DAC Volume Limit 2L
  2619. */
  2620. #define ARIZONA_OUT2L_VOL_LIM_MASK 0x00FF /* OUT2L_VOL_LIM - [7:0] */
  2621. #define ARIZONA_OUT2L_VOL_LIM_SHIFT 0 /* OUT2L_VOL_LIM - [7:0] */
  2622. #define ARIZONA_OUT2L_VOL_LIM_WIDTH 8 /* OUT2L_VOL_LIM - [7:0] */
  2623. /*
  2624. * R1051 (0x41B) - Noise Gate Select 2L
  2625. */
  2626. #define ARIZONA_OUT2L_NGATE_SRC_MASK 0x0FFF /* OUT2L_NGATE_SRC - [11:0] */
  2627. #define ARIZONA_OUT2L_NGATE_SRC_SHIFT 0 /* OUT2L_NGATE_SRC - [11:0] */
  2628. #define ARIZONA_OUT2L_NGATE_SRC_WIDTH 12 /* OUT2L_NGATE_SRC - [11:0] */
  2629. /*
  2630. * R1052 (0x41C) - Output Path Config 2R
  2631. */
  2632. #define ARIZONA_OUT2R_ANC_SRC_MASK 0x0C00 /* OUT2R_ANC_SRC - [11:10] */
  2633. #define ARIZONA_OUT2R_ANC_SRC_SHIFT 10 /* OUT2R_ANC_SRC - [11:10] */
  2634. #define ARIZONA_OUT2R_ANC_SRC_WIDTH 2 /* OUT2R_ANC_SRC - [11:10] */
  2635. #define ARIZONA_OUT2R_PGA_VOL_MASK 0x00FE /* OUT2R_PGA_VOL - [7:1] */
  2636. #define ARIZONA_OUT2R_PGA_VOL_SHIFT 1 /* OUT2R_PGA_VOL - [7:1] */
  2637. #define ARIZONA_OUT2R_PGA_VOL_WIDTH 7 /* OUT2R_PGA_VOL - [7:1] */
  2638. /*
  2639. * R1053 (0x41D) - DAC Digital Volume 2R
  2640. */
  2641. #define ARIZONA_OUT_VU 0x0200 /* OUT_VU */
  2642. #define ARIZONA_OUT_VU_MASK 0x0200 /* OUT_VU */
  2643. #define ARIZONA_OUT_VU_SHIFT 9 /* OUT_VU */
  2644. #define ARIZONA_OUT_VU_WIDTH 1 /* OUT_VU */
  2645. #define ARIZONA_OUT2R_MUTE 0x0100 /* OUT2R_MUTE */
  2646. #define ARIZONA_OUT2R_MUTE_MASK 0x0100 /* OUT2R_MUTE */
  2647. #define ARIZONA_OUT2R_MUTE_SHIFT 8 /* OUT2R_MUTE */
  2648. #define ARIZONA_OUT2R_MUTE_WIDTH 1 /* OUT2R_MUTE */
  2649. #define ARIZONA_OUT2R_VOL_MASK 0x00FF /* OUT2R_VOL - [7:0] */
  2650. #define ARIZONA_OUT2R_VOL_SHIFT 0 /* OUT2R_VOL - [7:0] */
  2651. #define ARIZONA_OUT2R_VOL_WIDTH 8 /* OUT2R_VOL - [7:0] */
  2652. /*
  2653. * R1054 (0x41E) - DAC Volume Limit 2R
  2654. */
  2655. #define ARIZONA_OUT2R_VOL_LIM_MASK 0x00FF /* OUT2R_VOL_LIM - [7:0] */
  2656. #define ARIZONA_OUT2R_VOL_LIM_SHIFT 0 /* OUT2R_VOL_LIM - [7:0] */
  2657. #define ARIZONA_OUT2R_VOL_LIM_WIDTH 8 /* OUT2R_VOL_LIM - [7:0] */
  2658. /*
  2659. * R1055 (0x41F) - Noise Gate Select 2R
  2660. */
  2661. #define ARIZONA_OUT2R_NGATE_SRC_MASK 0x0FFF /* OUT2R_NGATE_SRC - [11:0] */
  2662. #define ARIZONA_OUT2R_NGATE_SRC_SHIFT 0 /* OUT2R_NGATE_SRC - [11:0] */
  2663. #define ARIZONA_OUT2R_NGATE_SRC_WIDTH 12 /* OUT2R_NGATE_SRC - [11:0] */
  2664. /*
  2665. * R1056 (0x420) - Output Path Config 3L
  2666. */
  2667. #define ARIZONA_OUT3_LP_MODE 0x8000 /* OUT3_LP_MODE */
  2668. #define ARIZONA_OUT3_LP_MODE_MASK 0x8000 /* OUT3_LP_MODE */
  2669. #define ARIZONA_OUT3_LP_MODE_SHIFT 15 /* OUT3_LP_MODE */
  2670. #define ARIZONA_OUT3_LP_MODE_WIDTH 1 /* OUT3_LP_MODE */
  2671. #define ARIZONA_OUT3_OSR 0x2000 /* OUT3_OSR */
  2672. #define ARIZONA_OUT3_OSR_MASK 0x2000 /* OUT3_OSR */
  2673. #define ARIZONA_OUT3_OSR_SHIFT 13 /* OUT3_OSR */
  2674. #define ARIZONA_OUT3_OSR_WIDTH 1 /* OUT3_OSR */
  2675. #define ARIZONA_OUT3_MONO 0x1000 /* OUT3_MONO */
  2676. #define ARIZONA_OUT3_MONO_MASK 0x1000 /* OUT3_MONO */
  2677. #define ARIZONA_OUT3_MONO_SHIFT 12 /* OUT3_MONO */
  2678. #define ARIZONA_OUT3_MONO_WIDTH 1 /* OUT3_MONO */
  2679. #define ARIZONA_OUT3L_ANC_SRC_MASK 0x0C00 /* OUT3L_ANC_SRC - [11:10] */
  2680. #define ARIZONA_OUT3L_ANC_SRC_SHIFT 10 /* OUT3L_ANC_SRC - [11:10] */
  2681. #define ARIZONA_OUT3L_ANC_SRC_WIDTH 2 /* OUT3L_ANC_SRC - [11:10] */
  2682. #define ARIZONA_OUT3L_PGA_VOL_MASK 0x00FE /* OUT3L_PGA_VOL - [7:1] */
  2683. #define ARIZONA_OUT3L_PGA_VOL_SHIFT 1 /* OUT3L_PGA_VOL - [7:1] */
  2684. #define ARIZONA_OUT3L_PGA_VOL_WIDTH 7 /* OUT3L_PGA_VOL - [7:1] */
  2685. /*
  2686. * R1057 (0x421) - DAC Digital Volume 3L
  2687. */
  2688. #define ARIZONA_OUT_VU 0x0200 /* OUT_VU */
  2689. #define ARIZONA_OUT_VU_MASK 0x0200 /* OUT_VU */
  2690. #define ARIZONA_OUT_VU_SHIFT 9 /* OUT_VU */
  2691. #define ARIZONA_OUT_VU_WIDTH 1 /* OUT_VU */
  2692. #define ARIZONA_OUT3L_MUTE 0x0100 /* OUT3L_MUTE */
  2693. #define ARIZONA_OUT3L_MUTE_MASK 0x0100 /* OUT3L_MUTE */
  2694. #define ARIZONA_OUT3L_MUTE_SHIFT 8 /* OUT3L_MUTE */
  2695. #define ARIZONA_OUT3L_MUTE_WIDTH 1 /* OUT3L_MUTE */
  2696. #define ARIZONA_OUT3L_VOL_MASK 0x00FF /* OUT3L_VOL - [7:0] */
  2697. #define ARIZONA_OUT3L_VOL_SHIFT 0 /* OUT3L_VOL - [7:0] */
  2698. #define ARIZONA_OUT3L_VOL_WIDTH 8 /* OUT3L_VOL - [7:0] */
  2699. /*
  2700. * R1058 (0x422) - DAC Volume Limit 3L
  2701. */
  2702. #define ARIZONA_OUT3L_VOL_LIM_MASK 0x00FF /* OUT3L_VOL_LIM - [7:0] */
  2703. #define ARIZONA_OUT3L_VOL_LIM_SHIFT 0 /* OUT3L_VOL_LIM - [7:0] */
  2704. #define ARIZONA_OUT3L_VOL_LIM_WIDTH 8 /* OUT3L_VOL_LIM - [7:0] */
  2705. /*
  2706. * R1059 (0x423) - Noise Gate Select 3L
  2707. */
  2708. #define ARIZONA_OUT3_NGATE_SRC_MASK 0x0FFF /* OUT3_NGATE_SRC - [11:0] */
  2709. #define ARIZONA_OUT3_NGATE_SRC_SHIFT 0 /* OUT3_NGATE_SRC - [11:0] */
  2710. #define ARIZONA_OUT3_NGATE_SRC_WIDTH 12 /* OUT3_NGATE_SRC - [11:0] */
  2711. /*
  2712. * R1060 (0x424) - Output Path Config 3R
  2713. */
  2714. #define ARIZONA_OUT3R_PGA_VOL_MASK 0x00FE /* OUT3R_PGA_VOL - [7:1] */
  2715. #define ARIZONA_OUT3R_PGA_VOL_SHIFT 1 /* OUT3R_PGA_VOL - [7:1] */
  2716. #define ARIZONA_OUT3R_PGA_VOL_WIDTH 7 /* OUT3R_PGA_VOL - [7:1] */
  2717. /*
  2718. * R1061 (0x425) - DAC Digital Volume 3R
  2719. */
  2720. #define ARIZONA_OUT_VU 0x0200 /* OUT_VU */
  2721. #define ARIZONA_OUT_VU_MASK 0x0200 /* OUT_VU */
  2722. #define ARIZONA_OUT_VU_SHIFT 9 /* OUT_VU */
  2723. #define ARIZONA_OUT_VU_WIDTH 1 /* OUT_VU */
  2724. #define ARIZONA_OUT3R_MUTE 0x0100 /* OUT3R_MUTE */
  2725. #define ARIZONA_OUT3R_MUTE_MASK 0x0100 /* OUT3R_MUTE */
  2726. #define ARIZONA_OUT3R_MUTE_SHIFT 8 /* OUT3R_MUTE */
  2727. #define ARIZONA_OUT3R_MUTE_WIDTH 1 /* OUT3R_MUTE */
  2728. #define ARIZONA_OUT3R_VOL_MASK 0x00FF /* OUT3R_VOL - [7:0] */
  2729. #define ARIZONA_OUT3R_VOL_SHIFT 0 /* OUT3R_VOL - [7:0] */
  2730. #define ARIZONA_OUT3R_VOL_WIDTH 8 /* OUT3R_VOL - [7:0] */
  2731. /*
  2732. * R1062 (0x426) - DAC Volume Limit 3R
  2733. */
  2734. #define ARIZONA_OUT3R_ANC_SRC_MASK 0x0C00 /* OUT3R_ANC_SRC - [11:10] */
  2735. #define ARIZONA_OUT3R_ANC_SRC_SHIFT 10 /* OUT3R_ANC_SRC - [11:10] */
  2736. #define ARIZONA_OUT3R_ANC_SRC_WIDTH 2 /* OUT3R_ANC_SRC - [11:10] */
  2737. #define ARIZONA_OUT3R_VOL_LIM_MASK 0x00FF /* OUT3R_VOL_LIM - [7:0] */
  2738. #define ARIZONA_OUT3R_VOL_LIM_SHIFT 0 /* OUT3R_VOL_LIM - [7:0] */
  2739. #define ARIZONA_OUT3R_VOL_LIM_WIDTH 8 /* OUT3R_VOL_LIM - [7:0] */
  2740. /*
  2741. * R1064 (0x428) - Output Path Config 4L
  2742. */
  2743. #define ARIZONA_OUT4_OSR 0x2000 /* OUT4_OSR */
  2744. #define ARIZONA_OUT4_OSR_MASK 0x2000 /* OUT4_OSR */
  2745. #define ARIZONA_OUT4_OSR_SHIFT 13 /* OUT4_OSR */
  2746. #define ARIZONA_OUT4_OSR_WIDTH 1 /* OUT4_OSR */
  2747. #define ARIZONA_OUT4L_ANC_SRC_MASK 0x0C00 /* OUT4L_ANC_SRC - [11:10] */
  2748. #define ARIZONA_OUT4L_ANC_SRC_SHIFT 10 /* OUT4L_ANC_SRC - [11:10] */
  2749. #define ARIZONA_OUT4L_ANC_SRC_WIDTH 2 /* OUT4L_ANC_SRC - [11:10] */
  2750. /*
  2751. * R1065 (0x429) - DAC Digital Volume 4L
  2752. */
  2753. #define ARIZONA_OUT_VU 0x0200 /* OUT_VU */
  2754. #define ARIZONA_OUT_VU_MASK 0x0200 /* OUT_VU */
  2755. #define ARIZONA_OUT_VU_SHIFT 9 /* OUT_VU */
  2756. #define ARIZONA_OUT_VU_WIDTH 1 /* OUT_VU */
  2757. #define ARIZONA_OUT4L_MUTE 0x0100 /* OUT4L_MUTE */
  2758. #define ARIZONA_OUT4L_MUTE_MASK 0x0100 /* OUT4L_MUTE */
  2759. #define ARIZONA_OUT4L_MUTE_SHIFT 8 /* OUT4L_MUTE */
  2760. #define ARIZONA_OUT4L_MUTE_WIDTH 1 /* OUT4L_MUTE */
  2761. #define ARIZONA_OUT4L_VOL_MASK 0x00FF /* OUT4L_VOL - [7:0] */
  2762. #define ARIZONA_OUT4L_VOL_SHIFT 0 /* OUT4L_VOL - [7:0] */
  2763. #define ARIZONA_OUT4L_VOL_WIDTH 8 /* OUT4L_VOL - [7:0] */
  2764. /*
  2765. * R1066 (0x42A) - Out Volume 4L
  2766. */
  2767. #define ARIZONA_OUT4L_VOL_LIM_MASK 0x00FF /* OUT4L_VOL_LIM - [7:0] */
  2768. #define ARIZONA_OUT4L_VOL_LIM_SHIFT 0 /* OUT4L_VOL_LIM - [7:0] */
  2769. #define ARIZONA_OUT4L_VOL_LIM_WIDTH 8 /* OUT4L_VOL_LIM - [7:0] */
  2770. /*
  2771. * R1067 (0x42B) - Noise Gate Select 4L
  2772. */
  2773. #define ARIZONA_OUT4L_NGATE_SRC_MASK 0x0FFF /* OUT4L_NGATE_SRC - [11:0] */
  2774. #define ARIZONA_OUT4L_NGATE_SRC_SHIFT 0 /* OUT4L_NGATE_SRC - [11:0] */
  2775. #define ARIZONA_OUT4L_NGATE_SRC_WIDTH 12 /* OUT4L_NGATE_SRC - [11:0] */
  2776. /*
  2777. * R1068 (0x42C) - Output Path Config 4R
  2778. */
  2779. #define ARIZONA_OUT4R_ANC_SRC_MASK 0x0C00 /* OUT4R_ANC_SRC - [11:10] */
  2780. #define ARIZONA_OUT4R_ANC_SRC_SHIFT 10 /* OUT4R_ANC_SRC - [11:10] */
  2781. #define ARIZONA_OUT4R_ANC_SRC_WIDTH 2 /* OUT4R_ANC_SRC - [11:10] */
  2782. /*
  2783. * R1069 (0x42D) - DAC Digital Volume 4R
  2784. */
  2785. #define ARIZONA_OUT_VU 0x0200 /* OUT_VU */
  2786. #define ARIZONA_OUT_VU_MASK 0x0200 /* OUT_VU */
  2787. #define ARIZONA_OUT_VU_SHIFT 9 /* OUT_VU */
  2788. #define ARIZONA_OUT_VU_WIDTH 1 /* OUT_VU */
  2789. #define ARIZONA_OUT4R_MUTE 0x0100 /* OUT4R_MUTE */
  2790. #define ARIZONA_OUT4R_MUTE_MASK 0x0100 /* OUT4R_MUTE */
  2791. #define ARIZONA_OUT4R_MUTE_SHIFT 8 /* OUT4R_MUTE */
  2792. #define ARIZONA_OUT4R_MUTE_WIDTH 1 /* OUT4R_MUTE */
  2793. #define ARIZONA_OUT4R_VOL_MASK 0x00FF /* OUT4R_VOL - [7:0] */
  2794. #define ARIZONA_OUT4R_VOL_SHIFT 0 /* OUT4R_VOL - [7:0] */
  2795. #define ARIZONA_OUT4R_VOL_WIDTH 8 /* OUT4R_VOL - [7:0] */
  2796. /*
  2797. * R1070 (0x42E) - Out Volume 4R
  2798. */
  2799. #define ARIZONA_OUT4R_VOL_LIM_MASK 0x00FF /* OUT4R_VOL_LIM - [7:0] */
  2800. #define ARIZONA_OUT4R_VOL_LIM_SHIFT 0 /* OUT4R_VOL_LIM - [7:0] */
  2801. #define ARIZONA_OUT4R_VOL_LIM_WIDTH 8 /* OUT4R_VOL_LIM - [7:0] */
  2802. /*
  2803. * R1071 (0x42F) - Noise Gate Select 4R
  2804. */
  2805. #define ARIZONA_OUT4R_NGATE_SRC_MASK 0x0FFF /* OUT4R_NGATE_SRC - [11:0] */
  2806. #define ARIZONA_OUT4R_NGATE_SRC_SHIFT 0 /* OUT4R_NGATE_SRC - [11:0] */
  2807. #define ARIZONA_OUT4R_NGATE_SRC_WIDTH 12 /* OUT4R_NGATE_SRC - [11:0] */
  2808. /*
  2809. * R1072 (0x430) - Output Path Config 5L
  2810. */
  2811. #define ARIZONA_OUT5_OSR 0x2000 /* OUT5_OSR */
  2812. #define ARIZONA_OUT5_OSR_MASK 0x2000 /* OUT5_OSR */
  2813. #define ARIZONA_OUT5_OSR_SHIFT 13 /* OUT5_OSR */
  2814. #define ARIZONA_OUT5_OSR_WIDTH 1 /* OUT5_OSR */
  2815. #define ARIZONA_OUT5L_ANC_SRC_MASK 0x0C00 /* OUT5L_ANC_SRC - [11:10] */
  2816. #define ARIZONA_OUT5L_ANC_SRC_SHIFT 10 /* OUT5L_ANC_SRC - [11:10] */
  2817. #define ARIZONA_OUT5L_ANC_SRC_WIDTH 2 /* OUT5L_ANC_SRC - [11:10] */
  2818. /*
  2819. * R1073 (0x431) - DAC Digital Volume 5L
  2820. */
  2821. #define ARIZONA_OUT_VU 0x0200 /* OUT_VU */
  2822. #define ARIZONA_OUT_VU_MASK 0x0200 /* OUT_VU */
  2823. #define ARIZONA_OUT_VU_SHIFT 9 /* OUT_VU */
  2824. #define ARIZONA_OUT_VU_WIDTH 1 /* OUT_VU */
  2825. #define ARIZONA_OUT5L_MUTE 0x0100 /* OUT5L_MUTE */
  2826. #define ARIZONA_OUT5L_MUTE_MASK 0x0100 /* OUT5L_MUTE */
  2827. #define ARIZONA_OUT5L_MUTE_SHIFT 8 /* OUT5L_MUTE */
  2828. #define ARIZONA_OUT5L_MUTE_WIDTH 1 /* OUT5L_MUTE */
  2829. #define ARIZONA_OUT5L_VOL_MASK 0x00FF /* OUT5L_VOL - [7:0] */
  2830. #define ARIZONA_OUT5L_VOL_SHIFT 0 /* OUT5L_VOL - [7:0] */
  2831. #define ARIZONA_OUT5L_VOL_WIDTH 8 /* OUT5L_VOL - [7:0] */
  2832. /*
  2833. * R1074 (0x432) - DAC Volume Limit 5L
  2834. */
  2835. #define ARIZONA_OUT5L_VOL_LIM_MASK 0x00FF /* OUT5L_VOL_LIM - [7:0] */
  2836. #define ARIZONA_OUT5L_VOL_LIM_SHIFT 0 /* OUT5L_VOL_LIM - [7:0] */
  2837. #define ARIZONA_OUT5L_VOL_LIM_WIDTH 8 /* OUT5L_VOL_LIM - [7:0] */
  2838. /*
  2839. * R1075 (0x433) - Noise Gate Select 5L
  2840. */
  2841. #define ARIZONA_OUT5L_NGATE_SRC_MASK 0x0FFF /* OUT5L_NGATE_SRC - [11:0] */
  2842. #define ARIZONA_OUT5L_NGATE_SRC_SHIFT 0 /* OUT5L_NGATE_SRC - [11:0] */
  2843. #define ARIZONA_OUT5L_NGATE_SRC_WIDTH 12 /* OUT5L_NGATE_SRC - [11:0] */
  2844. /*
  2845. * R1076 (0x434) - Output Path Config 5R
  2846. */
  2847. #define ARIZONA_OUT5R_ANC_SRC_MASK 0x0C00 /* OUT5R_ANC_SRC - [11:10] */
  2848. #define ARIZONA_OUT5R_ANC_SRC_SHIFT 10 /* OUT5R_ANC_SRC - [11:10] */
  2849. #define ARIZONA_OUT5R_ANC_SRC_WIDTH 2 /* OUT5R_ANC_SRC - [11:10] */
  2850. /*
  2851. * R1077 (0x435) - DAC Digital Volume 5R
  2852. */
  2853. #define ARIZONA_OUT_VU 0x0200 /* OUT_VU */
  2854. #define ARIZONA_OUT_VU_MASK 0x0200 /* OUT_VU */
  2855. #define ARIZONA_OUT_VU_SHIFT 9 /* OUT_VU */
  2856. #define ARIZONA_OUT_VU_WIDTH 1 /* OUT_VU */
  2857. #define ARIZONA_OUT5R_MUTE 0x0100 /* OUT5R_MUTE */
  2858. #define ARIZONA_OUT5R_MUTE_MASK 0x0100 /* OUT5R_MUTE */
  2859. #define ARIZONA_OUT5R_MUTE_SHIFT 8 /* OUT5R_MUTE */
  2860. #define ARIZONA_OUT5R_MUTE_WIDTH 1 /* OUT5R_MUTE */
  2861. #define ARIZONA_OUT5R_VOL_MASK 0x00FF /* OUT5R_VOL - [7:0] */
  2862. #define ARIZONA_OUT5R_VOL_SHIFT 0 /* OUT5R_VOL - [7:0] */
  2863. #define ARIZONA_OUT5R_VOL_WIDTH 8 /* OUT5R_VOL - [7:0] */
  2864. /*
  2865. * R1078 (0x436) - DAC Volume Limit 5R
  2866. */
  2867. #define ARIZONA_OUT5R_VOL_LIM_MASK 0x00FF /* OUT5R_VOL_LIM - [7:0] */
  2868. #define ARIZONA_OUT5R_VOL_LIM_SHIFT 0 /* OUT5R_VOL_LIM - [7:0] */
  2869. #define ARIZONA_OUT5R_VOL_LIM_WIDTH 8 /* OUT5R_VOL_LIM - [7:0] */
  2870. /*
  2871. * R1079 (0x437) - Noise Gate Select 5R
  2872. */
  2873. #define ARIZONA_OUT5R_NGATE_SRC_MASK 0x0FFF /* OUT5R_NGATE_SRC - [11:0] */
  2874. #define ARIZONA_OUT5R_NGATE_SRC_SHIFT 0 /* OUT5R_NGATE_SRC - [11:0] */
  2875. #define ARIZONA_OUT5R_NGATE_SRC_WIDTH 12 /* OUT5R_NGATE_SRC - [11:0] */
  2876. /*
  2877. * R1080 (0x438) - Output Path Config 6L
  2878. */
  2879. #define ARIZONA_OUT6_OSR 0x2000 /* OUT6_OSR */
  2880. #define ARIZONA_OUT6_OSR_MASK 0x2000 /* OUT6_OSR */
  2881. #define ARIZONA_OUT6_OSR_SHIFT 13 /* OUT6_OSR */
  2882. #define ARIZONA_OUT6_OSR_WIDTH 1 /* OUT6_OSR */
  2883. #define ARIZONA_OUT6L_ANC_SRC_MASK 0x0C00 /* OUT6L_ANC_SRC - [11:10] */
  2884. #define ARIZONA_OUT6L_ANC_SRC_SHIFT 10 /* OUT6L_ANC_SRC - [11:10] */
  2885. #define ARIZONA_OUT6L_ANC_SRC_WIDTH 2 /* OUT6L_ANC_SRC - [11:10] */
  2886. /*
  2887. * R1081 (0x439) - DAC Digital Volume 6L
  2888. */
  2889. #define ARIZONA_OUT_VU 0x0200 /* OUT_VU */
  2890. #define ARIZONA_OUT_VU_MASK 0x0200 /* OUT_VU */
  2891. #define ARIZONA_OUT_VU_SHIFT 9 /* OUT_VU */
  2892. #define ARIZONA_OUT_VU_WIDTH 1 /* OUT_VU */
  2893. #define ARIZONA_OUT6L_MUTE 0x0100 /* OUT6L_MUTE */
  2894. #define ARIZONA_OUT6L_MUTE_MASK 0x0100 /* OUT6L_MUTE */
  2895. #define ARIZONA_OUT6L_MUTE_SHIFT 8 /* OUT6L_MUTE */
  2896. #define ARIZONA_OUT6L_MUTE_WIDTH 1 /* OUT6L_MUTE */
  2897. #define ARIZONA_OUT6L_VOL_MASK 0x00FF /* OUT6L_VOL - [7:0] */
  2898. #define ARIZONA_OUT6L_VOL_SHIFT 0 /* OUT6L_VOL - [7:0] */
  2899. #define ARIZONA_OUT6L_VOL_WIDTH 8 /* OUT6L_VOL - [7:0] */
  2900. /*
  2901. * R1082 (0x43A) - DAC Volume Limit 6L
  2902. */
  2903. #define ARIZONA_OUT6L_VOL_LIM_MASK 0x00FF /* OUT6L_VOL_LIM - [7:0] */
  2904. #define ARIZONA_OUT6L_VOL_LIM_SHIFT 0 /* OUT6L_VOL_LIM - [7:0] */
  2905. #define ARIZONA_OUT6L_VOL_LIM_WIDTH 8 /* OUT6L_VOL_LIM - [7:0] */
  2906. /*
  2907. * R1083 (0x43B) - Noise Gate Select 6L
  2908. */
  2909. #define ARIZONA_OUT6L_NGATE_SRC_MASK 0x0FFF /* OUT6L_NGATE_SRC - [11:0] */
  2910. #define ARIZONA_OUT6L_NGATE_SRC_SHIFT 0 /* OUT6L_NGATE_SRC - [11:0] */
  2911. #define ARIZONA_OUT6L_NGATE_SRC_WIDTH 12 /* OUT6L_NGATE_SRC - [11:0] */
  2912. /*
  2913. * R1084 (0x43C) - Output Path Config 6R
  2914. */
  2915. #define ARIZONA_OUT6R_ANC_SRC_MASK 0x0C00 /* OUT6R_ANC_SRC - [11:10] */
  2916. #define ARIZONA_OUT6R_ANC_SRC_SHIFT 10 /* OUT6R_ANC_SRC - [11:10] */
  2917. #define ARIZONA_OUT6R_ANC_SRC_WIDTH 2 /* OUT6R_ANC_SRC - [11:10] */
  2918. /*
  2919. * R1085 (0x43D) - DAC Digital Volume 6R
  2920. */
  2921. #define ARIZONA_OUT_VU 0x0200 /* OUT_VU */
  2922. #define ARIZONA_OUT_VU_MASK 0x0200 /* OUT_VU */
  2923. #define ARIZONA_OUT_VU_SHIFT 9 /* OUT_VU */
  2924. #define ARIZONA_OUT_VU_WIDTH 1 /* OUT_VU */
  2925. #define ARIZONA_OUT6R_MUTE 0x0100 /* OUT6R_MUTE */
  2926. #define ARIZONA_OUT6R_MUTE_MASK 0x0100 /* OUT6R_MUTE */
  2927. #define ARIZONA_OUT6R_MUTE_SHIFT 8 /* OUT6R_MUTE */
  2928. #define ARIZONA_OUT6R_MUTE_WIDTH 1 /* OUT6R_MUTE */
  2929. #define ARIZONA_OUT6R_VOL_MASK 0x00FF /* OUT6R_VOL - [7:0] */
  2930. #define ARIZONA_OUT6R_VOL_SHIFT 0 /* OUT6R_VOL - [7:0] */
  2931. #define ARIZONA_OUT6R_VOL_WIDTH 8 /* OUT6R_VOL - [7:0] */
  2932. /*
  2933. * R1086 (0x43E) - DAC Volume Limit 6R
  2934. */
  2935. #define ARIZONA_OUT6R_VOL_LIM_MASK 0x00FF /* OUT6R_VOL_LIM - [7:0] */
  2936. #define ARIZONA_OUT6R_VOL_LIM_SHIFT 0 /* OUT6R_VOL_LIM - [7:0] */
  2937. #define ARIZONA_OUT6R_VOL_LIM_WIDTH 8 /* OUT6R_VOL_LIM - [7:0] */
  2938. /*
  2939. * R1087 (0x43F) - Noise Gate Select 6R
  2940. */
  2941. #define ARIZONA_OUT6R_NGATE_SRC_MASK 0x0FFF /* OUT6R_NGATE_SRC - [11:0] */
  2942. #define ARIZONA_OUT6R_NGATE_SRC_SHIFT 0 /* OUT6R_NGATE_SRC - [11:0] */
  2943. #define ARIZONA_OUT6R_NGATE_SRC_WIDTH 12 /* OUT6R_NGATE_SRC - [11:0] */
  2944. /*
  2945. * R1104 (0x450) - DAC AEC Control 1
  2946. */
  2947. #define ARIZONA_AEC_LOOPBACK_SRC_MASK 0x003C /* AEC_LOOPBACK_SRC - [5:2] */
  2948. #define ARIZONA_AEC_LOOPBACK_SRC_SHIFT 2 /* AEC_LOOPBACK_SRC - [5:2] */
  2949. #define ARIZONA_AEC_LOOPBACK_SRC_WIDTH 4 /* AEC_LOOPBACK_SRC - [5:2] */
  2950. #define ARIZONA_AEC_ENA_STS 0x0002 /* AEC_ENA_STS */
  2951. #define ARIZONA_AEC_ENA_STS_MASK 0x0002 /* AEC_ENA_STS */
  2952. #define ARIZONA_AEC_ENA_STS_SHIFT 1 /* AEC_ENA_STS */
  2953. #define ARIZONA_AEC_ENA_STS_WIDTH 1 /* AEC_ENA_STS */
  2954. #define ARIZONA_AEC_LOOPBACK_ENA 0x0001 /* AEC_LOOPBACK_ENA */
  2955. #define ARIZONA_AEC_LOOPBACK_ENA_MASK 0x0001 /* AEC_LOOPBACK_ENA */
  2956. #define ARIZONA_AEC_LOOPBACK_ENA_SHIFT 0 /* AEC_LOOPBACK_ENA */
  2957. #define ARIZONA_AEC_LOOPBACK_ENA_WIDTH 1 /* AEC_LOOPBACK_ENA */
  2958. /*
  2959. * R1112 (0x458) - Noise Gate Control
  2960. */
  2961. #define ARIZONA_NGATE_HOLD_MASK 0x0030 /* NGATE_HOLD - [5:4] */
  2962. #define ARIZONA_NGATE_HOLD_SHIFT 4 /* NGATE_HOLD - [5:4] */
  2963. #define ARIZONA_NGATE_HOLD_WIDTH 2 /* NGATE_HOLD - [5:4] */
  2964. #define ARIZONA_NGATE_THR_MASK 0x000E /* NGATE_THR - [3:1] */
  2965. #define ARIZONA_NGATE_THR_SHIFT 1 /* NGATE_THR - [3:1] */
  2966. #define ARIZONA_NGATE_THR_WIDTH 3 /* NGATE_THR - [3:1] */
  2967. #define ARIZONA_NGATE_ENA 0x0001 /* NGATE_ENA */
  2968. #define ARIZONA_NGATE_ENA_MASK 0x0001 /* NGATE_ENA */
  2969. #define ARIZONA_NGATE_ENA_SHIFT 0 /* NGATE_ENA */
  2970. #define ARIZONA_NGATE_ENA_WIDTH 1 /* NGATE_ENA */
  2971. /*
  2972. * R1168 (0x490) - PDM SPK1 CTRL 1
  2973. */
  2974. #define ARIZONA_SPK1R_MUTE 0x2000 /* SPK1R_MUTE */
  2975. #define ARIZONA_SPK1R_MUTE_MASK 0x2000 /* SPK1R_MUTE */
  2976. #define ARIZONA_SPK1R_MUTE_SHIFT 13 /* SPK1R_MUTE */
  2977. #define ARIZONA_SPK1R_MUTE_WIDTH 1 /* SPK1R_MUTE */
  2978. #define ARIZONA_SPK1L_MUTE 0x1000 /* SPK1L_MUTE */
  2979. #define ARIZONA_SPK1L_MUTE_MASK 0x1000 /* SPK1L_MUTE */
  2980. #define ARIZONA_SPK1L_MUTE_SHIFT 12 /* SPK1L_MUTE */
  2981. #define ARIZONA_SPK1L_MUTE_WIDTH 1 /* SPK1L_MUTE */
  2982. #define ARIZONA_SPK1_MUTE_ENDIAN 0x0100 /* SPK1_MUTE_ENDIAN */
  2983. #define ARIZONA_SPK1_MUTE_ENDIAN_MASK 0x0100 /* SPK1_MUTE_ENDIAN */
  2984. #define ARIZONA_SPK1_MUTE_ENDIAN_SHIFT 8 /* SPK1_MUTE_ENDIAN */
  2985. #define ARIZONA_SPK1_MUTE_ENDIAN_WIDTH 1 /* SPK1_MUTE_ENDIAN */
  2986. #define ARIZONA_SPK1_MUTE_SEQ1_MASK 0x00FF /* SPK1_MUTE_SEQ1 - [7:0] */
  2987. #define ARIZONA_SPK1_MUTE_SEQ1_SHIFT 0 /* SPK1_MUTE_SEQ1 - [7:0] */
  2988. #define ARIZONA_SPK1_MUTE_SEQ1_WIDTH 8 /* SPK1_MUTE_SEQ1 - [7:0] */
  2989. /*
  2990. * R1169 (0x491) - PDM SPK1 CTRL 2
  2991. */
  2992. #define ARIZONA_SPK1_FMT 0x0001 /* SPK1_FMT */
  2993. #define ARIZONA_SPK1_FMT_MASK 0x0001 /* SPK1_FMT */
  2994. #define ARIZONA_SPK1_FMT_SHIFT 0 /* SPK1_FMT */
  2995. #define ARIZONA_SPK1_FMT_WIDTH 1 /* SPK1_FMT */
  2996. /*
  2997. * R1170 (0x492) - PDM SPK2 CTRL 1
  2998. */
  2999. #define ARIZONA_SPK2R_MUTE 0x2000 /* SPK2R_MUTE */
  3000. #define ARIZONA_SPK2R_MUTE_MASK 0x2000 /* SPK2R_MUTE */
  3001. #define ARIZONA_SPK2R_MUTE_SHIFT 13 /* SPK2R_MUTE */
  3002. #define ARIZONA_SPK2R_MUTE_WIDTH 1 /* SPK2R_MUTE */
  3003. #define ARIZONA_SPK2L_MUTE 0x1000 /* SPK2L_MUTE */
  3004. #define ARIZONA_SPK2L_MUTE_MASK 0x1000 /* SPK2L_MUTE */
  3005. #define ARIZONA_SPK2L_MUTE_SHIFT 12 /* SPK2L_MUTE */
  3006. #define ARIZONA_SPK2L_MUTE_WIDTH 1 /* SPK2L_MUTE */
  3007. #define ARIZONA_SPK2_MUTE_ENDIAN 0x0100 /* SPK2_MUTE_ENDIAN */
  3008. #define ARIZONA_SPK2_MUTE_ENDIAN_MASK 0x0100 /* SPK2_MUTE_ENDIAN */
  3009. #define ARIZONA_SPK2_MUTE_ENDIAN_SHIFT 8 /* SPK2_MUTE_ENDIAN */
  3010. #define ARIZONA_SPK2_MUTE_ENDIAN_WIDTH 1 /* SPK2_MUTE_ENDIAN */
  3011. #define ARIZONA_SPK2_MUTE_SEQ_MASK 0x00FF /* SPK2_MUTE_SEQ - [7:0] */
  3012. #define ARIZONA_SPK2_MUTE_SEQ_SHIFT 0 /* SPK2_MUTE_SEQ - [7:0] */
  3013. #define ARIZONA_SPK2_MUTE_SEQ_WIDTH 8 /* SPK2_MUTE_SEQ - [7:0] */
  3014. /*
  3015. * R1171 (0x493) - PDM SPK2 CTRL 2
  3016. */
  3017. #define ARIZONA_SPK2_FMT 0x0001 /* SPK2_FMT */
  3018. #define ARIZONA_SPK2_FMT_MASK 0x0001 /* SPK2_FMT */
  3019. #define ARIZONA_SPK2_FMT_SHIFT 0 /* SPK2_FMT */
  3020. #define ARIZONA_SPK2_FMT_WIDTH 1 /* SPK2_FMT */
  3021. /*
  3022. * R1244 (0x4DC) - DAC comp 1
  3023. */
  3024. #define ARIZONA_OUT_COMP_COEFF_MASK 0xFFFF /* OUT_COMP_COEFF - [15:0] */
  3025. #define ARIZONA_OUT_COMP_COEFF_SHIFT 0 /* OUT_COMP_COEFF - [15:0] */
  3026. #define ARIZONA_OUT_COMP_COEFF_WIDTH 16 /* OUT_COMP_COEFF - [15:0] */
  3027. /*
  3028. * R1245 (0x4DD) - DAC comp 2
  3029. */
  3030. #define ARIZONA_OUT_COMP_COEFF_1 0x0002 /* OUT_COMP_COEFF */
  3031. #define ARIZONA_OUT_COMP_COEFF_1_MASK 0x0002 /* OUT_COMP_COEFF */
  3032. #define ARIZONA_OUT_COMP_COEFF_1_SHIFT 1 /* OUT_COMP_COEFF */
  3033. #define ARIZONA_OUT_COMP_COEFF_1_WIDTH 1 /* OUT_COMP_COEFF */
  3034. #define ARIZONA_OUT_COMP_COEFF_SEL 0x0001 /* OUT_COMP_COEFF_SEL */
  3035. #define ARIZONA_OUT_COMP_COEFF_SEL_MASK 0x0001 /* OUT_COMP_COEFF_SEL */
  3036. #define ARIZONA_OUT_COMP_COEFF_SEL_SHIFT 0 /* OUT_COMP_COEFF_SEL */
  3037. #define ARIZONA_OUT_COMP_COEFF_SEL_WIDTH 1 /* OUT_COMP_COEFF_SEL */
  3038. /*
  3039. * R1246 (0x4DE) - DAC comp 3
  3040. */
  3041. #define ARIZONA_AEC_COMP_COEFF_MASK 0xFFFF /* AEC_COMP_COEFF - [15:0] */
  3042. #define ARIZONA_AEC_COMP_COEFF_SHIFT 0 /* AEC_COMP_COEFF - [15:0] */
  3043. #define ARIZONA_AEC_COMP_COEFF_WIDTH 16 /* AEC_COMP_COEFF - [15:0] */
  3044. /*
  3045. * R1247 (0x4DF) - DAC comp 4
  3046. */
  3047. #define ARIZONA_AEC_COMP_COEFF_1 0x0002 /* AEC_COMP_COEFF */
  3048. #define ARIZONA_AEC_COMP_COEFF_1_MASK 0x0002 /* AEC_COMP_COEFF */
  3049. #define ARIZONA_AEC_COMP_COEFF_1_SHIFT 1 /* AEC_COMP_COEFF */
  3050. #define ARIZONA_AEC_COMP_COEFF_1_WIDTH 1 /* AEC_COMP_COEFF */
  3051. #define ARIZONA_AEC_COMP_COEFF_SEL 0x0001 /* AEC_COMP_COEFF_SEL */
  3052. #define ARIZONA_AEC_COMP_COEFF_SEL_MASK 0x0001 /* AEC_COMP_COEFF_SEL */
  3053. #define ARIZONA_AEC_COMP_COEFF_SEL_SHIFT 0 /* AEC_COMP_COEFF_SEL */
  3054. #define ARIZONA_AEC_COMP_COEFF_SEL_WIDTH 1 /* AEC_COMP_COEFF_SEL */
  3055. /*
  3056. * R1280 (0x500) - AIF1 BCLK Ctrl
  3057. */
  3058. #define ARIZONA_AIF1_BCLK_INV 0x0080 /* AIF1_BCLK_INV */
  3059. #define ARIZONA_AIF1_BCLK_INV_MASK 0x0080 /* AIF1_BCLK_INV */
  3060. #define ARIZONA_AIF1_BCLK_INV_SHIFT 7 /* AIF1_BCLK_INV */
  3061. #define ARIZONA_AIF1_BCLK_INV_WIDTH 1 /* AIF1_BCLK_INV */
  3062. #define ARIZONA_AIF1_BCLK_FRC 0x0040 /* AIF1_BCLK_FRC */
  3063. #define ARIZONA_AIF1_BCLK_FRC_MASK 0x0040 /* AIF1_BCLK_FRC */
  3064. #define ARIZONA_AIF1_BCLK_FRC_SHIFT 6 /* AIF1_BCLK_FRC */
  3065. #define ARIZONA_AIF1_BCLK_FRC_WIDTH 1 /* AIF1_BCLK_FRC */
  3066. #define ARIZONA_AIF1_BCLK_MSTR 0x0020 /* AIF1_BCLK_MSTR */
  3067. #define ARIZONA_AIF1_BCLK_MSTR_MASK 0x0020 /* AIF1_BCLK_MSTR */
  3068. #define ARIZONA_AIF1_BCLK_MSTR_SHIFT 5 /* AIF1_BCLK_MSTR */
  3069. #define ARIZONA_AIF1_BCLK_MSTR_WIDTH 1 /* AIF1_BCLK_MSTR */
  3070. #define ARIZONA_AIF1_BCLK_FREQ_MASK 0x001F /* AIF1_BCLK_FREQ - [4:0] */
  3071. #define ARIZONA_AIF1_BCLK_FREQ_SHIFT 0 /* AIF1_BCLK_FREQ - [4:0] */
  3072. #define ARIZONA_AIF1_BCLK_FREQ_WIDTH 5 /* AIF1_BCLK_FREQ - [4:0] */
  3073. /*
  3074. * R1281 (0x501) - AIF1 Tx Pin Ctrl
  3075. */
  3076. #define ARIZONA_AIF1TX_DAT_TRI 0x0020 /* AIF1TX_DAT_TRI */
  3077. #define ARIZONA_AIF1TX_DAT_TRI_MASK 0x0020 /* AIF1TX_DAT_TRI */
  3078. #define ARIZONA_AIF1TX_DAT_TRI_SHIFT 5 /* AIF1TX_DAT_TRI */
  3079. #define ARIZONA_AIF1TX_DAT_TRI_WIDTH 1 /* AIF1TX_DAT_TRI */
  3080. #define ARIZONA_AIF1TX_LRCLK_SRC 0x0008 /* AIF1TX_LRCLK_SRC */
  3081. #define ARIZONA_AIF1TX_LRCLK_SRC_MASK 0x0008 /* AIF1TX_LRCLK_SRC */
  3082. #define ARIZONA_AIF1TX_LRCLK_SRC_SHIFT 3 /* AIF1TX_LRCLK_SRC */
  3083. #define ARIZONA_AIF1TX_LRCLK_SRC_WIDTH 1 /* AIF1TX_LRCLK_SRC */
  3084. #define ARIZONA_AIF1TX_LRCLK_INV 0x0004 /* AIF1TX_LRCLK_INV */
  3085. #define ARIZONA_AIF1TX_LRCLK_INV_MASK 0x0004 /* AIF1TX_LRCLK_INV */
  3086. #define ARIZONA_AIF1TX_LRCLK_INV_SHIFT 2 /* AIF1TX_LRCLK_INV */
  3087. #define ARIZONA_AIF1TX_LRCLK_INV_WIDTH 1 /* AIF1TX_LRCLK_INV */
  3088. #define ARIZONA_AIF1TX_LRCLK_FRC 0x0002 /* AIF1TX_LRCLK_FRC */
  3089. #define ARIZONA_AIF1TX_LRCLK_FRC_MASK 0x0002 /* AIF1TX_LRCLK_FRC */
  3090. #define ARIZONA_AIF1TX_LRCLK_FRC_SHIFT 1 /* AIF1TX_LRCLK_FRC */
  3091. #define ARIZONA_AIF1TX_LRCLK_FRC_WIDTH 1 /* AIF1TX_LRCLK_FRC */
  3092. #define ARIZONA_AIF1TX_LRCLK_MSTR 0x0001 /* AIF1TX_LRCLK_MSTR */
  3093. #define ARIZONA_AIF1TX_LRCLK_MSTR_MASK 0x0001 /* AIF1TX_LRCLK_MSTR */
  3094. #define ARIZONA_AIF1TX_LRCLK_MSTR_SHIFT 0 /* AIF1TX_LRCLK_MSTR */
  3095. #define ARIZONA_AIF1TX_LRCLK_MSTR_WIDTH 1 /* AIF1TX_LRCLK_MSTR */
  3096. /*
  3097. * R1282 (0x502) - AIF1 Rx Pin Ctrl
  3098. */
  3099. #define ARIZONA_AIF1RX_LRCLK_INV 0x0004 /* AIF1RX_LRCLK_INV */
  3100. #define ARIZONA_AIF1RX_LRCLK_INV_MASK 0x0004 /* AIF1RX_LRCLK_INV */
  3101. #define ARIZONA_AIF1RX_LRCLK_INV_SHIFT 2 /* AIF1RX_LRCLK_INV */
  3102. #define ARIZONA_AIF1RX_LRCLK_INV_WIDTH 1 /* AIF1RX_LRCLK_INV */
  3103. #define ARIZONA_AIF1RX_LRCLK_FRC 0x0002 /* AIF1RX_LRCLK_FRC */
  3104. #define ARIZONA_AIF1RX_LRCLK_FRC_MASK 0x0002 /* AIF1RX_LRCLK_FRC */
  3105. #define ARIZONA_AIF1RX_LRCLK_FRC_SHIFT 1 /* AIF1RX_LRCLK_FRC */
  3106. #define ARIZONA_AIF1RX_LRCLK_FRC_WIDTH 1 /* AIF1RX_LRCLK_FRC */
  3107. #define ARIZONA_AIF1RX_LRCLK_MSTR 0x0001 /* AIF1RX_LRCLK_MSTR */
  3108. #define ARIZONA_AIF1RX_LRCLK_MSTR_MASK 0x0001 /* AIF1RX_LRCLK_MSTR */
  3109. #define ARIZONA_AIF1RX_LRCLK_MSTR_SHIFT 0 /* AIF1RX_LRCLK_MSTR */
  3110. #define ARIZONA_AIF1RX_LRCLK_MSTR_WIDTH 1 /* AIF1RX_LRCLK_MSTR */
  3111. /*
  3112. * R1283 (0x503) - AIF1 Rate Ctrl
  3113. */
  3114. #define ARIZONA_AIF1_RATE_MASK 0x7800 /* AIF1_RATE - [14:11] */
  3115. #define ARIZONA_AIF1_RATE_SHIFT 11 /* AIF1_RATE - [14:11] */
  3116. #define ARIZONA_AIF1_RATE_WIDTH 4 /* AIF1_RATE - [14:11] */
  3117. #define ARIZONA_AIF1_TRI 0x0040 /* AIF1_TRI */
  3118. #define ARIZONA_AIF1_TRI_MASK 0x0040 /* AIF1_TRI */
  3119. #define ARIZONA_AIF1_TRI_SHIFT 6 /* AIF1_TRI */
  3120. #define ARIZONA_AIF1_TRI_WIDTH 1 /* AIF1_TRI */
  3121. /*
  3122. * R1284 (0x504) - AIF1 Format
  3123. */
  3124. #define ARIZONA_AIF1_FMT_MASK 0x0007 /* AIF1_FMT - [2:0] */
  3125. #define ARIZONA_AIF1_FMT_SHIFT 0 /* AIF1_FMT - [2:0] */
  3126. #define ARIZONA_AIF1_FMT_WIDTH 3 /* AIF1_FMT - [2:0] */
  3127. /*
  3128. * R1285 (0x505) - AIF1 Tx BCLK Rate
  3129. */
  3130. #define ARIZONA_AIF1TX_BCPF_MASK 0x1FFF /* AIF1TX_BCPF - [12:0] */
  3131. #define ARIZONA_AIF1TX_BCPF_SHIFT 0 /* AIF1TX_BCPF - [12:0] */
  3132. #define ARIZONA_AIF1TX_BCPF_WIDTH 13 /* AIF1TX_BCPF - [12:0] */
  3133. /*
  3134. * R1286 (0x506) - AIF1 Rx BCLK Rate
  3135. */
  3136. #define ARIZONA_AIF1RX_BCPF_MASK 0x1FFF /* AIF1RX_BCPF - [12:0] */
  3137. #define ARIZONA_AIF1RX_BCPF_SHIFT 0 /* AIF1RX_BCPF - [12:0] */
  3138. #define ARIZONA_AIF1RX_BCPF_WIDTH 13 /* AIF1RX_BCPF - [12:0] */
  3139. /*
  3140. * R1287 (0x507) - AIF1 Frame Ctrl 1
  3141. */
  3142. #define ARIZONA_AIF1TX_WL_MASK 0x3F00 /* AIF1TX_WL - [13:8] */
  3143. #define ARIZONA_AIF1TX_WL_SHIFT 8 /* AIF1TX_WL - [13:8] */
  3144. #define ARIZONA_AIF1TX_WL_WIDTH 6 /* AIF1TX_WL - [13:8] */
  3145. #define ARIZONA_AIF1TX_SLOT_LEN_MASK 0x00FF /* AIF1TX_SLOT_LEN - [7:0] */
  3146. #define ARIZONA_AIF1TX_SLOT_LEN_SHIFT 0 /* AIF1TX_SLOT_LEN - [7:0] */
  3147. #define ARIZONA_AIF1TX_SLOT_LEN_WIDTH 8 /* AIF1TX_SLOT_LEN - [7:0] */
  3148. /*
  3149. * R1288 (0x508) - AIF1 Frame Ctrl 2
  3150. */
  3151. #define ARIZONA_AIF1RX_WL_MASK 0x3F00 /* AIF1RX_WL - [13:8] */
  3152. #define ARIZONA_AIF1RX_WL_SHIFT 8 /* AIF1RX_WL - [13:8] */
  3153. #define ARIZONA_AIF1RX_WL_WIDTH 6 /* AIF1RX_WL - [13:8] */
  3154. #define ARIZONA_AIF1RX_SLOT_LEN_MASK 0x00FF /* AIF1RX_SLOT_LEN - [7:0] */
  3155. #define ARIZONA_AIF1RX_SLOT_LEN_SHIFT 0 /* AIF1RX_SLOT_LEN - [7:0] */
  3156. #define ARIZONA_AIF1RX_SLOT_LEN_WIDTH 8 /* AIF1RX_SLOT_LEN - [7:0] */
  3157. /*
  3158. * R1289 (0x509) - AIF1 Frame Ctrl 3
  3159. */
  3160. #define ARIZONA_AIF1TX1_SLOT_MASK 0x003F /* AIF1TX1_SLOT - [5:0] */
  3161. #define ARIZONA_AIF1TX1_SLOT_SHIFT 0 /* AIF1TX1_SLOT - [5:0] */
  3162. #define ARIZONA_AIF1TX1_SLOT_WIDTH 6 /* AIF1TX1_SLOT - [5:0] */
  3163. /*
  3164. * R1290 (0x50A) - AIF1 Frame Ctrl 4
  3165. */
  3166. #define ARIZONA_AIF1TX2_SLOT_MASK 0x003F /* AIF1TX2_SLOT - [5:0] */
  3167. #define ARIZONA_AIF1TX2_SLOT_SHIFT 0 /* AIF1TX2_SLOT - [5:0] */
  3168. #define ARIZONA_AIF1TX2_SLOT_WIDTH 6 /* AIF1TX2_SLOT - [5:0] */
  3169. /*
  3170. * R1291 (0x50B) - AIF1 Frame Ctrl 5
  3171. */
  3172. #define ARIZONA_AIF1TX3_SLOT_MASK 0x003F /* AIF1TX3_SLOT - [5:0] */
  3173. #define ARIZONA_AIF1TX3_SLOT_SHIFT 0 /* AIF1TX3_SLOT - [5:0] */
  3174. #define ARIZONA_AIF1TX3_SLOT_WIDTH 6 /* AIF1TX3_SLOT - [5:0] */
  3175. /*
  3176. * R1292 (0x50C) - AIF1 Frame Ctrl 6
  3177. */
  3178. #define ARIZONA_AIF1TX4_SLOT_MASK 0x003F /* AIF1TX4_SLOT - [5:0] */
  3179. #define ARIZONA_AIF1TX4_SLOT_SHIFT 0 /* AIF1TX4_SLOT - [5:0] */
  3180. #define ARIZONA_AIF1TX4_SLOT_WIDTH 6 /* AIF1TX4_SLOT - [5:0] */
  3181. /*
  3182. * R1293 (0x50D) - AIF1 Frame Ctrl 7
  3183. */
  3184. #define ARIZONA_AIF1TX5_SLOT_MASK 0x003F /* AIF1TX5_SLOT - [5:0] */
  3185. #define ARIZONA_AIF1TX5_SLOT_SHIFT 0 /* AIF1TX5_SLOT - [5:0] */
  3186. #define ARIZONA_AIF1TX5_SLOT_WIDTH 6 /* AIF1TX5_SLOT - [5:0] */
  3187. /*
  3188. * R1294 (0x50E) - AIF1 Frame Ctrl 8
  3189. */
  3190. #define ARIZONA_AIF1TX6_SLOT_MASK 0x003F /* AIF1TX6_SLOT - [5:0] */
  3191. #define ARIZONA_AIF1TX6_SLOT_SHIFT 0 /* AIF1TX6_SLOT - [5:0] */
  3192. #define ARIZONA_AIF1TX6_SLOT_WIDTH 6 /* AIF1TX6_SLOT - [5:0] */
  3193. /*
  3194. * R1295 (0x50F) - AIF1 Frame Ctrl 9
  3195. */
  3196. #define ARIZONA_AIF1TX7_SLOT_MASK 0x003F /* AIF1TX7_SLOT - [5:0] */
  3197. #define ARIZONA_AIF1TX7_SLOT_SHIFT 0 /* AIF1TX7_SLOT - [5:0] */
  3198. #define ARIZONA_AIF1TX7_SLOT_WIDTH 6 /* AIF1TX7_SLOT - [5:0] */
  3199. /*
  3200. * R1296 (0x510) - AIF1 Frame Ctrl 10
  3201. */
  3202. #define ARIZONA_AIF1TX8_SLOT_MASK 0x003F /* AIF1TX8_SLOT - [5:0] */
  3203. #define ARIZONA_AIF1TX8_SLOT_SHIFT 0 /* AIF1TX8_SLOT - [5:0] */
  3204. #define ARIZONA_AIF1TX8_SLOT_WIDTH 6 /* AIF1TX8_SLOT - [5:0] */
  3205. /*
  3206. * R1297 (0x511) - AIF1 Frame Ctrl 11
  3207. */
  3208. #define ARIZONA_AIF1RX1_SLOT_MASK 0x003F /* AIF1RX1_SLOT - [5:0] */
  3209. #define ARIZONA_AIF1RX1_SLOT_SHIFT 0 /* AIF1RX1_SLOT - [5:0] */
  3210. #define ARIZONA_AIF1RX1_SLOT_WIDTH 6 /* AIF1RX1_SLOT - [5:0] */
  3211. /*
  3212. * R1298 (0x512) - AIF1 Frame Ctrl 12
  3213. */
  3214. #define ARIZONA_AIF1RX2_SLOT_MASK 0x003F /* AIF1RX2_SLOT - [5:0] */
  3215. #define ARIZONA_AIF1RX2_SLOT_SHIFT 0 /* AIF1RX2_SLOT - [5:0] */
  3216. #define ARIZONA_AIF1RX2_SLOT_WIDTH 6 /* AIF1RX2_SLOT - [5:0] */
  3217. /*
  3218. * R1299 (0x513) - AIF1 Frame Ctrl 13
  3219. */
  3220. #define ARIZONA_AIF1RX3_SLOT_MASK 0x003F /* AIF1RX3_SLOT - [5:0] */
  3221. #define ARIZONA_AIF1RX3_SLOT_SHIFT 0 /* AIF1RX3_SLOT - [5:0] */
  3222. #define ARIZONA_AIF1RX3_SLOT_WIDTH 6 /* AIF1RX3_SLOT - [5:0] */
  3223. /*
  3224. * R1300 (0x514) - AIF1 Frame Ctrl 14
  3225. */
  3226. #define ARIZONA_AIF1RX4_SLOT_MASK 0x003F /* AIF1RX4_SLOT - [5:0] */
  3227. #define ARIZONA_AIF1RX4_SLOT_SHIFT 0 /* AIF1RX4_SLOT - [5:0] */
  3228. #define ARIZONA_AIF1RX4_SLOT_WIDTH 6 /* AIF1RX4_SLOT - [5:0] */
  3229. /*
  3230. * R1301 (0x515) - AIF1 Frame Ctrl 15
  3231. */
  3232. #define ARIZONA_AIF1RX5_SLOT_MASK 0x003F /* AIF1RX5_SLOT - [5:0] */
  3233. #define ARIZONA_AIF1RX5_SLOT_SHIFT 0 /* AIF1RX5_SLOT - [5:0] */
  3234. #define ARIZONA_AIF1RX5_SLOT_WIDTH 6 /* AIF1RX5_SLOT - [5:0] */
  3235. /*
  3236. * R1302 (0x516) - AIF1 Frame Ctrl 16
  3237. */
  3238. #define ARIZONA_AIF1RX6_SLOT_MASK 0x003F /* AIF1RX6_SLOT - [5:0] */
  3239. #define ARIZONA_AIF1RX6_SLOT_SHIFT 0 /* AIF1RX6_SLOT - [5:0] */
  3240. #define ARIZONA_AIF1RX6_SLOT_WIDTH 6 /* AIF1RX6_SLOT - [5:0] */
  3241. /*
  3242. * R1303 (0x517) - AIF1 Frame Ctrl 17
  3243. */
  3244. #define ARIZONA_AIF1RX7_SLOT_MASK 0x003F /* AIF1RX7_SLOT - [5:0] */
  3245. #define ARIZONA_AIF1RX7_SLOT_SHIFT 0 /* AIF1RX7_SLOT - [5:0] */
  3246. #define ARIZONA_AIF1RX7_SLOT_WIDTH 6 /* AIF1RX7_SLOT - [5:0] */
  3247. /*
  3248. * R1304 (0x518) - AIF1 Frame Ctrl 18
  3249. */
  3250. #define ARIZONA_AIF1RX8_SLOT_MASK 0x003F /* AIF1RX8_SLOT - [5:0] */
  3251. #define ARIZONA_AIF1RX8_SLOT_SHIFT 0 /* AIF1RX8_SLOT - [5:0] */
  3252. #define ARIZONA_AIF1RX8_SLOT_WIDTH 6 /* AIF1RX8_SLOT - [5:0] */
  3253. /*
  3254. * R1305 (0x519) - AIF1 Tx Enables
  3255. */
  3256. #define ARIZONA_AIF1TX8_ENA 0x0080 /* AIF1TX8_ENA */
  3257. #define ARIZONA_AIF1TX8_ENA_MASK 0x0080 /* AIF1TX8_ENA */
  3258. #define ARIZONA_AIF1TX8_ENA_SHIFT 7 /* AIF1TX8_ENA */
  3259. #define ARIZONA_AIF1TX8_ENA_WIDTH 1 /* AIF1TX8_ENA */
  3260. #define ARIZONA_AIF1TX7_ENA 0x0040 /* AIF1TX7_ENA */
  3261. #define ARIZONA_AIF1TX7_ENA_MASK 0x0040 /* AIF1TX7_ENA */
  3262. #define ARIZONA_AIF1TX7_ENA_SHIFT 6 /* AIF1TX7_ENA */
  3263. #define ARIZONA_AIF1TX7_ENA_WIDTH 1 /* AIF1TX7_ENA */
  3264. #define ARIZONA_AIF1TX6_ENA 0x0020 /* AIF1TX6_ENA */
  3265. #define ARIZONA_AIF1TX6_ENA_MASK 0x0020 /* AIF1TX6_ENA */
  3266. #define ARIZONA_AIF1TX6_ENA_SHIFT 5 /* AIF1TX6_ENA */
  3267. #define ARIZONA_AIF1TX6_ENA_WIDTH 1 /* AIF1TX6_ENA */
  3268. #define ARIZONA_AIF1TX5_ENA 0x0010 /* AIF1TX5_ENA */
  3269. #define ARIZONA_AIF1TX5_ENA_MASK 0x0010 /* AIF1TX5_ENA */
  3270. #define ARIZONA_AIF1TX5_ENA_SHIFT 4 /* AIF1TX5_ENA */
  3271. #define ARIZONA_AIF1TX5_ENA_WIDTH 1 /* AIF1TX5_ENA */
  3272. #define ARIZONA_AIF1TX4_ENA 0x0008 /* AIF1TX4_ENA */
  3273. #define ARIZONA_AIF1TX4_ENA_MASK 0x0008 /* AIF1TX4_ENA */
  3274. #define ARIZONA_AIF1TX4_ENA_SHIFT 3 /* AIF1TX4_ENA */
  3275. #define ARIZONA_AIF1TX4_ENA_WIDTH 1 /* AIF1TX4_ENA */
  3276. #define ARIZONA_AIF1TX3_ENA 0x0004 /* AIF1TX3_ENA */
  3277. #define ARIZONA_AIF1TX3_ENA_MASK 0x0004 /* AIF1TX3_ENA */
  3278. #define ARIZONA_AIF1TX3_ENA_SHIFT 2 /* AIF1TX3_ENA */
  3279. #define ARIZONA_AIF1TX3_ENA_WIDTH 1 /* AIF1TX3_ENA */
  3280. #define ARIZONA_AIF1TX2_ENA 0x0002 /* AIF1TX2_ENA */
  3281. #define ARIZONA_AIF1TX2_ENA_MASK 0x0002 /* AIF1TX2_ENA */
  3282. #define ARIZONA_AIF1TX2_ENA_SHIFT 1 /* AIF1TX2_ENA */
  3283. #define ARIZONA_AIF1TX2_ENA_WIDTH 1 /* AIF1TX2_ENA */
  3284. #define ARIZONA_AIF1TX1_ENA 0x0001 /* AIF1TX1_ENA */
  3285. #define ARIZONA_AIF1TX1_ENA_MASK 0x0001 /* AIF1TX1_ENA */
  3286. #define ARIZONA_AIF1TX1_ENA_SHIFT 0 /* AIF1TX1_ENA */
  3287. #define ARIZONA_AIF1TX1_ENA_WIDTH 1 /* AIF1TX1_ENA */
  3288. /*
  3289. * R1306 (0x51A) - AIF1 Rx Enables
  3290. */
  3291. #define ARIZONA_AIF1RX8_ENA 0x0080 /* AIF1RX8_ENA */
  3292. #define ARIZONA_AIF1RX8_ENA_MASK 0x0080 /* AIF1RX8_ENA */
  3293. #define ARIZONA_AIF1RX8_ENA_SHIFT 7 /* AIF1RX8_ENA */
  3294. #define ARIZONA_AIF1RX8_ENA_WIDTH 1 /* AIF1RX8_ENA */
  3295. #define ARIZONA_AIF1RX7_ENA 0x0040 /* AIF1RX7_ENA */
  3296. #define ARIZONA_AIF1RX7_ENA_MASK 0x0040 /* AIF1RX7_ENA */
  3297. #define ARIZONA_AIF1RX7_ENA_SHIFT 6 /* AIF1RX7_ENA */
  3298. #define ARIZONA_AIF1RX7_ENA_WIDTH 1 /* AIF1RX7_ENA */
  3299. #define ARIZONA_AIF1RX6_ENA 0x0020 /* AIF1RX6_ENA */
  3300. #define ARIZONA_AIF1RX6_ENA_MASK 0x0020 /* AIF1RX6_ENA */
  3301. #define ARIZONA_AIF1RX6_ENA_SHIFT 5 /* AIF1RX6_ENA */
  3302. #define ARIZONA_AIF1RX6_ENA_WIDTH 1 /* AIF1RX6_ENA */
  3303. #define ARIZONA_AIF1RX5_ENA 0x0010 /* AIF1RX5_ENA */
  3304. #define ARIZONA_AIF1RX5_ENA_MASK 0x0010 /* AIF1RX5_ENA */
  3305. #define ARIZONA_AIF1RX5_ENA_SHIFT 4 /* AIF1RX5_ENA */
  3306. #define ARIZONA_AIF1RX5_ENA_WIDTH 1 /* AIF1RX5_ENA */
  3307. #define ARIZONA_AIF1RX4_ENA 0x0008 /* AIF1RX4_ENA */
  3308. #define ARIZONA_AIF1RX4_ENA_MASK 0x0008 /* AIF1RX4_ENA */
  3309. #define ARIZONA_AIF1RX4_ENA_SHIFT 3 /* AIF1RX4_ENA */
  3310. #define ARIZONA_AIF1RX4_ENA_WIDTH 1 /* AIF1RX4_ENA */
  3311. #define ARIZONA_AIF1RX3_ENA 0x0004 /* AIF1RX3_ENA */
  3312. #define ARIZONA_AIF1RX3_ENA_MASK 0x0004 /* AIF1RX3_ENA */
  3313. #define ARIZONA_AIF1RX3_ENA_SHIFT 2 /* AIF1RX3_ENA */
  3314. #define ARIZONA_AIF1RX3_ENA_WIDTH 1 /* AIF1RX3_ENA */
  3315. #define ARIZONA_AIF1RX2_ENA 0x0002 /* AIF1RX2_ENA */
  3316. #define ARIZONA_AIF1RX2_ENA_MASK 0x0002 /* AIF1RX2_ENA */
  3317. #define ARIZONA_AIF1RX2_ENA_SHIFT 1 /* AIF1RX2_ENA */
  3318. #define ARIZONA_AIF1RX2_ENA_WIDTH 1 /* AIF1RX2_ENA */
  3319. #define ARIZONA_AIF1RX1_ENA 0x0001 /* AIF1RX1_ENA */
  3320. #define ARIZONA_AIF1RX1_ENA_MASK 0x0001 /* AIF1RX1_ENA */
  3321. #define ARIZONA_AIF1RX1_ENA_SHIFT 0 /* AIF1RX1_ENA */
  3322. #define ARIZONA_AIF1RX1_ENA_WIDTH 1 /* AIF1RX1_ENA */
  3323. /*
  3324. * R1307 (0x51B) - AIF1 Force Write
  3325. */
  3326. #define ARIZONA_AIF1_FRC_WR 0x0001 /* AIF1_FRC_WR */
  3327. #define ARIZONA_AIF1_FRC_WR_MASK 0x0001 /* AIF1_FRC_WR */
  3328. #define ARIZONA_AIF1_FRC_WR_SHIFT 0 /* AIF1_FRC_WR */
  3329. #define ARIZONA_AIF1_FRC_WR_WIDTH 1 /* AIF1_FRC_WR */
  3330. /*
  3331. * R1344 (0x540) - AIF2 BCLK Ctrl
  3332. */
  3333. #define ARIZONA_AIF2_BCLK_INV 0x0080 /* AIF2_BCLK_INV */
  3334. #define ARIZONA_AIF2_BCLK_INV_MASK 0x0080 /* AIF2_BCLK_INV */
  3335. #define ARIZONA_AIF2_BCLK_INV_SHIFT 7 /* AIF2_BCLK_INV */
  3336. #define ARIZONA_AIF2_BCLK_INV_WIDTH 1 /* AIF2_BCLK_INV */
  3337. #define ARIZONA_AIF2_BCLK_FRC 0x0040 /* AIF2_BCLK_FRC */
  3338. #define ARIZONA_AIF2_BCLK_FRC_MASK 0x0040 /* AIF2_BCLK_FRC */
  3339. #define ARIZONA_AIF2_BCLK_FRC_SHIFT 6 /* AIF2_BCLK_FRC */
  3340. #define ARIZONA_AIF2_BCLK_FRC_WIDTH 1 /* AIF2_BCLK_FRC */
  3341. #define ARIZONA_AIF2_BCLK_MSTR 0x0020 /* AIF2_BCLK_MSTR */
  3342. #define ARIZONA_AIF2_BCLK_MSTR_MASK 0x0020 /* AIF2_BCLK_MSTR */
  3343. #define ARIZONA_AIF2_BCLK_MSTR_SHIFT 5 /* AIF2_BCLK_MSTR */
  3344. #define ARIZONA_AIF2_BCLK_MSTR_WIDTH 1 /* AIF2_BCLK_MSTR */
  3345. #define ARIZONA_AIF2_BCLK_FREQ_MASK 0x001F /* AIF2_BCLK_FREQ - [4:0] */
  3346. #define ARIZONA_AIF2_BCLK_FREQ_SHIFT 0 /* AIF2_BCLK_FREQ - [4:0] */
  3347. #define ARIZONA_AIF2_BCLK_FREQ_WIDTH 5 /* AIF2_BCLK_FREQ - [4:0] */
  3348. /*
  3349. * R1345 (0x541) - AIF2 Tx Pin Ctrl
  3350. */
  3351. #define ARIZONA_AIF2TX_DAT_TRI 0x0020 /* AIF2TX_DAT_TRI */
  3352. #define ARIZONA_AIF2TX_DAT_TRI_MASK 0x0020 /* AIF2TX_DAT_TRI */
  3353. #define ARIZONA_AIF2TX_DAT_TRI_SHIFT 5 /* AIF2TX_DAT_TRI */
  3354. #define ARIZONA_AIF2TX_DAT_TRI_WIDTH 1 /* AIF2TX_DAT_TRI */
  3355. #define ARIZONA_AIF2TX_LRCLK_SRC 0x0008 /* AIF2TX_LRCLK_SRC */
  3356. #define ARIZONA_AIF2TX_LRCLK_SRC_MASK 0x0008 /* AIF2TX_LRCLK_SRC */
  3357. #define ARIZONA_AIF2TX_LRCLK_SRC_SHIFT 3 /* AIF2TX_LRCLK_SRC */
  3358. #define ARIZONA_AIF2TX_LRCLK_SRC_WIDTH 1 /* AIF2TX_LRCLK_SRC */
  3359. #define ARIZONA_AIF2TX_LRCLK_INV 0x0004 /* AIF2TX_LRCLK_INV */
  3360. #define ARIZONA_AIF2TX_LRCLK_INV_MASK 0x0004 /* AIF2TX_LRCLK_INV */
  3361. #define ARIZONA_AIF2TX_LRCLK_INV_SHIFT 2 /* AIF2TX_LRCLK_INV */
  3362. #define ARIZONA_AIF2TX_LRCLK_INV_WIDTH 1 /* AIF2TX_LRCLK_INV */
  3363. #define ARIZONA_AIF2TX_LRCLK_FRC 0x0002 /* AIF2TX_LRCLK_FRC */
  3364. #define ARIZONA_AIF2TX_LRCLK_FRC_MASK 0x0002 /* AIF2TX_LRCLK_FRC */
  3365. #define ARIZONA_AIF2TX_LRCLK_FRC_SHIFT 1 /* AIF2TX_LRCLK_FRC */
  3366. #define ARIZONA_AIF2TX_LRCLK_FRC_WIDTH 1 /* AIF2TX_LRCLK_FRC */
  3367. #define ARIZONA_AIF2TX_LRCLK_MSTR 0x0001 /* AIF2TX_LRCLK_MSTR */
  3368. #define ARIZONA_AIF2TX_LRCLK_MSTR_MASK 0x0001 /* AIF2TX_LRCLK_MSTR */
  3369. #define ARIZONA_AIF2TX_LRCLK_MSTR_SHIFT 0 /* AIF2TX_LRCLK_MSTR */
  3370. #define ARIZONA_AIF2TX_LRCLK_MSTR_WIDTH 1 /* AIF2TX_LRCLK_MSTR */
  3371. /*
  3372. * R1346 (0x542) - AIF2 Rx Pin Ctrl
  3373. */
  3374. #define ARIZONA_AIF2RX_LRCLK_INV 0x0004 /* AIF2RX_LRCLK_INV */
  3375. #define ARIZONA_AIF2RX_LRCLK_INV_MASK 0x0004 /* AIF2RX_LRCLK_INV */
  3376. #define ARIZONA_AIF2RX_LRCLK_INV_SHIFT 2 /* AIF2RX_LRCLK_INV */
  3377. #define ARIZONA_AIF2RX_LRCLK_INV_WIDTH 1 /* AIF2RX_LRCLK_INV */
  3378. #define ARIZONA_AIF2RX_LRCLK_FRC 0x0002 /* AIF2RX_LRCLK_FRC */
  3379. #define ARIZONA_AIF2RX_LRCLK_FRC_MASK 0x0002 /* AIF2RX_LRCLK_FRC */
  3380. #define ARIZONA_AIF2RX_LRCLK_FRC_SHIFT 1 /* AIF2RX_LRCLK_FRC */
  3381. #define ARIZONA_AIF2RX_LRCLK_FRC_WIDTH 1 /* AIF2RX_LRCLK_FRC */
  3382. #define ARIZONA_AIF2RX_LRCLK_MSTR 0x0001 /* AIF2RX_LRCLK_MSTR */
  3383. #define ARIZONA_AIF2RX_LRCLK_MSTR_MASK 0x0001 /* AIF2RX_LRCLK_MSTR */
  3384. #define ARIZONA_AIF2RX_LRCLK_MSTR_SHIFT 0 /* AIF2RX_LRCLK_MSTR */
  3385. #define ARIZONA_AIF2RX_LRCLK_MSTR_WIDTH 1 /* AIF2RX_LRCLK_MSTR */
  3386. /*
  3387. * R1347 (0x543) - AIF2 Rate Ctrl
  3388. */
  3389. #define ARIZONA_AIF2_RATE_MASK 0x7800 /* AIF2_RATE - [14:11] */
  3390. #define ARIZONA_AIF2_RATE_SHIFT 11 /* AIF2_RATE - [14:11] */
  3391. #define ARIZONA_AIF2_RATE_WIDTH 4 /* AIF2_RATE - [14:11] */
  3392. #define ARIZONA_AIF2_TRI 0x0040 /* AIF2_TRI */
  3393. #define ARIZONA_AIF2_TRI_MASK 0x0040 /* AIF2_TRI */
  3394. #define ARIZONA_AIF2_TRI_SHIFT 6 /* AIF2_TRI */
  3395. #define ARIZONA_AIF2_TRI_WIDTH 1 /* AIF2_TRI */
  3396. /*
  3397. * R1348 (0x544) - AIF2 Format
  3398. */
  3399. #define ARIZONA_AIF2_FMT_MASK 0x0007 /* AIF2_FMT - [2:0] */
  3400. #define ARIZONA_AIF2_FMT_SHIFT 0 /* AIF2_FMT - [2:0] */
  3401. #define ARIZONA_AIF2_FMT_WIDTH 3 /* AIF2_FMT - [2:0] */
  3402. /*
  3403. * R1349 (0x545) - AIF2 Tx BCLK Rate
  3404. */
  3405. #define ARIZONA_AIF2TX_BCPF_MASK 0x1FFF /* AIF2TX_BCPF - [12:0] */
  3406. #define ARIZONA_AIF2TX_BCPF_SHIFT 0 /* AIF2TX_BCPF - [12:0] */
  3407. #define ARIZONA_AIF2TX_BCPF_WIDTH 13 /* AIF2TX_BCPF - [12:0] */
  3408. /*
  3409. * R1350 (0x546) - AIF2 Rx BCLK Rate
  3410. */
  3411. #define ARIZONA_AIF2RX_BCPF_MASK 0x1FFF /* AIF2RX_BCPF - [12:0] */
  3412. #define ARIZONA_AIF2RX_BCPF_SHIFT 0 /* AIF2RX_BCPF - [12:0] */
  3413. #define ARIZONA_AIF2RX_BCPF_WIDTH 13 /* AIF2RX_BCPF - [12:0] */
  3414. /*
  3415. * R1351 (0x547) - AIF2 Frame Ctrl 1
  3416. */
  3417. #define ARIZONA_AIF2TX_WL_MASK 0x3F00 /* AIF2TX_WL - [13:8] */
  3418. #define ARIZONA_AIF2TX_WL_SHIFT 8 /* AIF2TX_WL - [13:8] */
  3419. #define ARIZONA_AIF2TX_WL_WIDTH 6 /* AIF2TX_WL - [13:8] */
  3420. #define ARIZONA_AIF2TX_SLOT_LEN_MASK 0x00FF /* AIF2TX_SLOT_LEN - [7:0] */
  3421. #define ARIZONA_AIF2TX_SLOT_LEN_SHIFT 0 /* AIF2TX_SLOT_LEN - [7:0] */
  3422. #define ARIZONA_AIF2TX_SLOT_LEN_WIDTH 8 /* AIF2TX_SLOT_LEN - [7:0] */
  3423. /*
  3424. * R1352 (0x548) - AIF2 Frame Ctrl 2
  3425. */
  3426. #define ARIZONA_AIF2RX_WL_MASK 0x3F00 /* AIF2RX_WL - [13:8] */
  3427. #define ARIZONA_AIF2RX_WL_SHIFT 8 /* AIF2RX_WL - [13:8] */
  3428. #define ARIZONA_AIF2RX_WL_WIDTH 6 /* AIF2RX_WL - [13:8] */
  3429. #define ARIZONA_AIF2RX_SLOT_LEN_MASK 0x00FF /* AIF2RX_SLOT_LEN - [7:0] */
  3430. #define ARIZONA_AIF2RX_SLOT_LEN_SHIFT 0 /* AIF2RX_SLOT_LEN - [7:0] */
  3431. #define ARIZONA_AIF2RX_SLOT_LEN_WIDTH 8 /* AIF2RX_SLOT_LEN - [7:0] */
  3432. /*
  3433. * R1353 (0x549) - AIF2 Frame Ctrl 3
  3434. */
  3435. #define ARIZONA_AIF2TX1_SLOT_MASK 0x003F /* AIF2TX1_SLOT - [5:0] */
  3436. #define ARIZONA_AIF2TX1_SLOT_SHIFT 0 /* AIF2TX1_SLOT - [5:0] */
  3437. #define ARIZONA_AIF2TX1_SLOT_WIDTH 6 /* AIF2TX1_SLOT - [5:0] */
  3438. /*
  3439. * R1354 (0x54A) - AIF2 Frame Ctrl 4
  3440. */
  3441. #define ARIZONA_AIF2TX2_SLOT_MASK 0x003F /* AIF2TX2_SLOT - [5:0] */
  3442. #define ARIZONA_AIF2TX2_SLOT_SHIFT 0 /* AIF2TX2_SLOT - [5:0] */
  3443. #define ARIZONA_AIF2TX2_SLOT_WIDTH 6 /* AIF2TX2_SLOT - [5:0] */
  3444. /*
  3445. * R1361 (0x551) - AIF2 Frame Ctrl 11
  3446. */
  3447. #define ARIZONA_AIF2RX1_SLOT_MASK 0x003F /* AIF2RX1_SLOT - [5:0] */
  3448. #define ARIZONA_AIF2RX1_SLOT_SHIFT 0 /* AIF2RX1_SLOT - [5:0] */
  3449. #define ARIZONA_AIF2RX1_SLOT_WIDTH 6 /* AIF2RX1_SLOT - [5:0] */
  3450. /*
  3451. * R1362 (0x552) - AIF2 Frame Ctrl 12
  3452. */
  3453. #define ARIZONA_AIF2RX2_SLOT_MASK 0x003F /* AIF2RX2_SLOT - [5:0] */
  3454. #define ARIZONA_AIF2RX2_SLOT_SHIFT 0 /* AIF2RX2_SLOT - [5:0] */
  3455. #define ARIZONA_AIF2RX2_SLOT_WIDTH 6 /* AIF2RX2_SLOT - [5:0] */
  3456. /*
  3457. * R1369 (0x559) - AIF2 Tx Enables
  3458. */
  3459. #define ARIZONA_AIF2TX2_ENA 0x0002 /* AIF2TX2_ENA */
  3460. #define ARIZONA_AIF2TX2_ENA_MASK 0x0002 /* AIF2TX2_ENA */
  3461. #define ARIZONA_AIF2TX2_ENA_SHIFT 1 /* AIF2TX2_ENA */
  3462. #define ARIZONA_AIF2TX2_ENA_WIDTH 1 /* AIF2TX2_ENA */
  3463. #define ARIZONA_AIF2TX1_ENA 0x0001 /* AIF2TX1_ENA */
  3464. #define ARIZONA_AIF2TX1_ENA_MASK 0x0001 /* AIF2TX1_ENA */
  3465. #define ARIZONA_AIF2TX1_ENA_SHIFT 0 /* AIF2TX1_ENA */
  3466. #define ARIZONA_AIF2TX1_ENA_WIDTH 1 /* AIF2TX1_ENA */
  3467. /*
  3468. * R1370 (0x55A) - AIF2 Rx Enables
  3469. */
  3470. #define ARIZONA_AIF2RX2_ENA 0x0002 /* AIF2RX2_ENA */
  3471. #define ARIZONA_AIF2RX2_ENA_MASK 0x0002 /* AIF2RX2_ENA */
  3472. #define ARIZONA_AIF2RX2_ENA_SHIFT 1 /* AIF2RX2_ENA */
  3473. #define ARIZONA_AIF2RX2_ENA_WIDTH 1 /* AIF2RX2_ENA */
  3474. #define ARIZONA_AIF2RX1_ENA 0x0001 /* AIF2RX1_ENA */
  3475. #define ARIZONA_AIF2RX1_ENA_MASK 0x0001 /* AIF2RX1_ENA */
  3476. #define ARIZONA_AIF2RX1_ENA_SHIFT 0 /* AIF2RX1_ENA */
  3477. #define ARIZONA_AIF2RX1_ENA_WIDTH 1 /* AIF2RX1_ENA */
  3478. /*
  3479. * R1371 (0x55B) - AIF2 Force Write
  3480. */
  3481. #define ARIZONA_AIF2_FRC_WR 0x0001 /* AIF2_FRC_WR */
  3482. #define ARIZONA_AIF2_FRC_WR_MASK 0x0001 /* AIF2_FRC_WR */
  3483. #define ARIZONA_AIF2_FRC_WR_SHIFT 0 /* AIF2_FRC_WR */
  3484. #define ARIZONA_AIF2_FRC_WR_WIDTH 1 /* AIF2_FRC_WR */
  3485. /*
  3486. * R1408 (0x580) - AIF3 BCLK Ctrl
  3487. */
  3488. #define ARIZONA_AIF3_BCLK_INV 0x0080 /* AIF3_BCLK_INV */
  3489. #define ARIZONA_AIF3_BCLK_INV_MASK 0x0080 /* AIF3_BCLK_INV */
  3490. #define ARIZONA_AIF3_BCLK_INV_SHIFT 7 /* AIF3_BCLK_INV */
  3491. #define ARIZONA_AIF3_BCLK_INV_WIDTH 1 /* AIF3_BCLK_INV */
  3492. #define ARIZONA_AIF3_BCLK_FRC 0x0040 /* AIF3_BCLK_FRC */
  3493. #define ARIZONA_AIF3_BCLK_FRC_MASK 0x0040 /* AIF3_BCLK_FRC */
  3494. #define ARIZONA_AIF3_BCLK_FRC_SHIFT 6 /* AIF3_BCLK_FRC */
  3495. #define ARIZONA_AIF3_BCLK_FRC_WIDTH 1 /* AIF3_BCLK_FRC */
  3496. #define ARIZONA_AIF3_BCLK_MSTR 0x0020 /* AIF3_BCLK_MSTR */
  3497. #define ARIZONA_AIF3_BCLK_MSTR_MASK 0x0020 /* AIF3_BCLK_MSTR */
  3498. #define ARIZONA_AIF3_BCLK_MSTR_SHIFT 5 /* AIF3_BCLK_MSTR */
  3499. #define ARIZONA_AIF3_BCLK_MSTR_WIDTH 1 /* AIF3_BCLK_MSTR */
  3500. #define ARIZONA_AIF3_BCLK_FREQ_MASK 0x001F /* AIF3_BCLK_FREQ - [4:0] */
  3501. #define ARIZONA_AIF3_BCLK_FREQ_SHIFT 0 /* AIF3_BCLK_FREQ - [4:0] */
  3502. #define ARIZONA_AIF3_BCLK_FREQ_WIDTH 5 /* AIF3_BCLK_FREQ - [4:0] */
  3503. /*
  3504. * R1409 (0x581) - AIF3 Tx Pin Ctrl
  3505. */
  3506. #define ARIZONA_AIF3TX_DAT_TRI 0x0020 /* AIF3TX_DAT_TRI */
  3507. #define ARIZONA_AIF3TX_DAT_TRI_MASK 0x0020 /* AIF3TX_DAT_TRI */
  3508. #define ARIZONA_AIF3TX_DAT_TRI_SHIFT 5 /* AIF3TX_DAT_TRI */
  3509. #define ARIZONA_AIF3TX_DAT_TRI_WIDTH 1 /* AIF3TX_DAT_TRI */
  3510. #define ARIZONA_AIF3TX_LRCLK_SRC 0x0008 /* AIF3TX_LRCLK_SRC */
  3511. #define ARIZONA_AIF3TX_LRCLK_SRC_MASK 0x0008 /* AIF3TX_LRCLK_SRC */
  3512. #define ARIZONA_AIF3TX_LRCLK_SRC_SHIFT 3 /* AIF3TX_LRCLK_SRC */
  3513. #define ARIZONA_AIF3TX_LRCLK_SRC_WIDTH 1 /* AIF3TX_LRCLK_SRC */
  3514. #define ARIZONA_AIF3TX_LRCLK_INV 0x0004 /* AIF3TX_LRCLK_INV */
  3515. #define ARIZONA_AIF3TX_LRCLK_INV_MASK 0x0004 /* AIF3TX_LRCLK_INV */
  3516. #define ARIZONA_AIF3TX_LRCLK_INV_SHIFT 2 /* AIF3TX_LRCLK_INV */
  3517. #define ARIZONA_AIF3TX_LRCLK_INV_WIDTH 1 /* AIF3TX_LRCLK_INV */
  3518. #define ARIZONA_AIF3TX_LRCLK_FRC 0x0002 /* AIF3TX_LRCLK_FRC */
  3519. #define ARIZONA_AIF3TX_LRCLK_FRC_MASK 0x0002 /* AIF3TX_LRCLK_FRC */
  3520. #define ARIZONA_AIF3TX_LRCLK_FRC_SHIFT 1 /* AIF3TX_LRCLK_FRC */
  3521. #define ARIZONA_AIF3TX_LRCLK_FRC_WIDTH 1 /* AIF3TX_LRCLK_FRC */
  3522. #define ARIZONA_AIF3TX_LRCLK_MSTR 0x0001 /* AIF3TX_LRCLK_MSTR */
  3523. #define ARIZONA_AIF3TX_LRCLK_MSTR_MASK 0x0001 /* AIF3TX_LRCLK_MSTR */
  3524. #define ARIZONA_AIF3TX_LRCLK_MSTR_SHIFT 0 /* AIF3TX_LRCLK_MSTR */
  3525. #define ARIZONA_AIF3TX_LRCLK_MSTR_WIDTH 1 /* AIF3TX_LRCLK_MSTR */
  3526. /*
  3527. * R1410 (0x582) - AIF3 Rx Pin Ctrl
  3528. */
  3529. #define ARIZONA_AIF3RX_LRCLK_INV 0x0004 /* AIF3RX_LRCLK_INV */
  3530. #define ARIZONA_AIF3RX_LRCLK_INV_MASK 0x0004 /* AIF3RX_LRCLK_INV */
  3531. #define ARIZONA_AIF3RX_LRCLK_INV_SHIFT 2 /* AIF3RX_LRCLK_INV */
  3532. #define ARIZONA_AIF3RX_LRCLK_INV_WIDTH 1 /* AIF3RX_LRCLK_INV */
  3533. #define ARIZONA_AIF3RX_LRCLK_FRC 0x0002 /* AIF3RX_LRCLK_FRC */
  3534. #define ARIZONA_AIF3RX_LRCLK_FRC_MASK 0x0002 /* AIF3RX_LRCLK_FRC */
  3535. #define ARIZONA_AIF3RX_LRCLK_FRC_SHIFT 1 /* AIF3RX_LRCLK_FRC */
  3536. #define ARIZONA_AIF3RX_LRCLK_FRC_WIDTH 1 /* AIF3RX_LRCLK_FRC */
  3537. #define ARIZONA_AIF3RX_LRCLK_MSTR 0x0001 /* AIF3RX_LRCLK_MSTR */
  3538. #define ARIZONA_AIF3RX_LRCLK_MSTR_MASK 0x0001 /* AIF3RX_LRCLK_MSTR */
  3539. #define ARIZONA_AIF3RX_LRCLK_MSTR_SHIFT 0 /* AIF3RX_LRCLK_MSTR */
  3540. #define ARIZONA_AIF3RX_LRCLK_MSTR_WIDTH 1 /* AIF3RX_LRCLK_MSTR */
  3541. /*
  3542. * R1411 (0x583) - AIF3 Rate Ctrl
  3543. */
  3544. #define ARIZONA_AIF3_RATE_MASK 0x7800 /* AIF3_RATE - [14:11] */
  3545. #define ARIZONA_AIF3_RATE_SHIFT 11 /* AIF3_RATE - [14:11] */
  3546. #define ARIZONA_AIF3_RATE_WIDTH 4 /* AIF3_RATE - [14:11] */
  3547. #define ARIZONA_AIF3_TRI 0x0040 /* AIF3_TRI */
  3548. #define ARIZONA_AIF3_TRI_MASK 0x0040 /* AIF3_TRI */
  3549. #define ARIZONA_AIF3_TRI_SHIFT 6 /* AIF3_TRI */
  3550. #define ARIZONA_AIF3_TRI_WIDTH 1 /* AIF3_TRI */
  3551. /*
  3552. * R1412 (0x584) - AIF3 Format
  3553. */
  3554. #define ARIZONA_AIF3_FMT_MASK 0x0007 /* AIF3_FMT - [2:0] */
  3555. #define ARIZONA_AIF3_FMT_SHIFT 0 /* AIF3_FMT - [2:0] */
  3556. #define ARIZONA_AIF3_FMT_WIDTH 3 /* AIF3_FMT - [2:0] */
  3557. /*
  3558. * R1413 (0x585) - AIF3 Tx BCLK Rate
  3559. */
  3560. #define ARIZONA_AIF3TX_BCPF_MASK 0x1FFF /* AIF3TX_BCPF - [12:0] */
  3561. #define ARIZONA_AIF3TX_BCPF_SHIFT 0 /* AIF3TX_BCPF - [12:0] */
  3562. #define ARIZONA_AIF3TX_BCPF_WIDTH 13 /* AIF3TX_BCPF - [12:0] */
  3563. /*
  3564. * R1414 (0x586) - AIF3 Rx BCLK Rate
  3565. */
  3566. #define ARIZONA_AIF3RX_BCPF_MASK 0x1FFF /* AIF3RX_BCPF - [12:0] */
  3567. #define ARIZONA_AIF3RX_BCPF_SHIFT 0 /* AIF3RX_BCPF - [12:0] */
  3568. #define ARIZONA_AIF3RX_BCPF_WIDTH 13 /* AIF3RX_BCPF - [12:0] */
  3569. /*
  3570. * R1415 (0x587) - AIF3 Frame Ctrl 1
  3571. */
  3572. #define ARIZONA_AIF3TX_WL_MASK 0x3F00 /* AIF3TX_WL - [13:8] */
  3573. #define ARIZONA_AIF3TX_WL_SHIFT 8 /* AIF3TX_WL - [13:8] */
  3574. #define ARIZONA_AIF3TX_WL_WIDTH 6 /* AIF3TX_WL - [13:8] */
  3575. #define ARIZONA_AIF3TX_SLOT_LEN_MASK 0x00FF /* AIF3TX_SLOT_LEN - [7:0] */
  3576. #define ARIZONA_AIF3TX_SLOT_LEN_SHIFT 0 /* AIF3TX_SLOT_LEN - [7:0] */
  3577. #define ARIZONA_AIF3TX_SLOT_LEN_WIDTH 8 /* AIF3TX_SLOT_LEN - [7:0] */
  3578. /*
  3579. * R1416 (0x588) - AIF3 Frame Ctrl 2
  3580. */
  3581. #define ARIZONA_AIF3RX_WL_MASK 0x3F00 /* AIF3RX_WL - [13:8] */
  3582. #define ARIZONA_AIF3RX_WL_SHIFT 8 /* AIF3RX_WL - [13:8] */
  3583. #define ARIZONA_AIF3RX_WL_WIDTH 6 /* AIF3RX_WL - [13:8] */
  3584. #define ARIZONA_AIF3RX_SLOT_LEN_MASK 0x00FF /* AIF3RX_SLOT_LEN - [7:0] */
  3585. #define ARIZONA_AIF3RX_SLOT_LEN_SHIFT 0 /* AIF3RX_SLOT_LEN - [7:0] */
  3586. #define ARIZONA_AIF3RX_SLOT_LEN_WIDTH 8 /* AIF3RX_SLOT_LEN - [7:0] */
  3587. /*
  3588. * R1417 (0x589) - AIF3 Frame Ctrl 3
  3589. */
  3590. #define ARIZONA_AIF3TX1_SLOT_MASK 0x003F /* AIF3TX1_SLOT - [5:0] */
  3591. #define ARIZONA_AIF3TX1_SLOT_SHIFT 0 /* AIF3TX1_SLOT - [5:0] */
  3592. #define ARIZONA_AIF3TX1_SLOT_WIDTH 6 /* AIF3TX1_SLOT - [5:0] */
  3593. /*
  3594. * R1418 (0x58A) - AIF3 Frame Ctrl 4
  3595. */
  3596. #define ARIZONA_AIF3TX2_SLOT_MASK 0x003F /* AIF3TX2_SLOT - [5:0] */
  3597. #define ARIZONA_AIF3TX2_SLOT_SHIFT 0 /* AIF3TX2_SLOT - [5:0] */
  3598. #define ARIZONA_AIF3TX2_SLOT_WIDTH 6 /* AIF3TX2_SLOT - [5:0] */
  3599. /*
  3600. * R1425 (0x591) - AIF3 Frame Ctrl 11
  3601. */
  3602. #define ARIZONA_AIF3RX1_SLOT_MASK 0x003F /* AIF3RX1_SLOT - [5:0] */
  3603. #define ARIZONA_AIF3RX1_SLOT_SHIFT 0 /* AIF3RX1_SLOT - [5:0] */
  3604. #define ARIZONA_AIF3RX1_SLOT_WIDTH 6 /* AIF3RX1_SLOT - [5:0] */
  3605. /*
  3606. * R1426 (0x592) - AIF3 Frame Ctrl 12
  3607. */
  3608. #define ARIZONA_AIF3RX2_SLOT_MASK 0x003F /* AIF3RX2_SLOT - [5:0] */
  3609. #define ARIZONA_AIF3RX2_SLOT_SHIFT 0 /* AIF3RX2_SLOT - [5:0] */
  3610. #define ARIZONA_AIF3RX2_SLOT_WIDTH 6 /* AIF3RX2_SLOT - [5:0] */
  3611. /*
  3612. * R1433 (0x599) - AIF3 Tx Enables
  3613. */
  3614. #define ARIZONA_AIF3TX2_ENA 0x0002 /* AIF3TX2_ENA */
  3615. #define ARIZONA_AIF3TX2_ENA_MASK 0x0002 /* AIF3TX2_ENA */
  3616. #define ARIZONA_AIF3TX2_ENA_SHIFT 1 /* AIF3TX2_ENA */
  3617. #define ARIZONA_AIF3TX2_ENA_WIDTH 1 /* AIF3TX2_ENA */
  3618. #define ARIZONA_AIF3TX1_ENA 0x0001 /* AIF3TX1_ENA */
  3619. #define ARIZONA_AIF3TX1_ENA_MASK 0x0001 /* AIF3TX1_ENA */
  3620. #define ARIZONA_AIF3TX1_ENA_SHIFT 0 /* AIF3TX1_ENA */
  3621. #define ARIZONA_AIF3TX1_ENA_WIDTH 1 /* AIF3TX1_ENA */
  3622. /*
  3623. * R1434 (0x59A) - AIF3 Rx Enables
  3624. */
  3625. #define ARIZONA_AIF3RX2_ENA 0x0002 /* AIF3RX2_ENA */
  3626. #define ARIZONA_AIF3RX2_ENA_MASK 0x0002 /* AIF3RX2_ENA */
  3627. #define ARIZONA_AIF3RX2_ENA_SHIFT 1 /* AIF3RX2_ENA */
  3628. #define ARIZONA_AIF3RX2_ENA_WIDTH 1 /* AIF3RX2_ENA */
  3629. #define ARIZONA_AIF3RX1_ENA 0x0001 /* AIF3RX1_ENA */
  3630. #define ARIZONA_AIF3RX1_ENA_MASK 0x0001 /* AIF3RX1_ENA */
  3631. #define ARIZONA_AIF3RX1_ENA_SHIFT 0 /* AIF3RX1_ENA */
  3632. #define ARIZONA_AIF3RX1_ENA_WIDTH 1 /* AIF3RX1_ENA */
  3633. /*
  3634. * R1435 (0x59B) - AIF3 Force Write
  3635. */
  3636. #define ARIZONA_AIF3_FRC_WR 0x0001 /* AIF3_FRC_WR */
  3637. #define ARIZONA_AIF3_FRC_WR_MASK 0x0001 /* AIF3_FRC_WR */
  3638. #define ARIZONA_AIF3_FRC_WR_SHIFT 0 /* AIF3_FRC_WR */
  3639. #define ARIZONA_AIF3_FRC_WR_WIDTH 1 /* AIF3_FRC_WR */
  3640. /*
  3641. * R1507 (0x5E3) - SLIMbus Framer Ref Gear
  3642. */
  3643. #define ARIZONA_SLIMCLK_SRC 0x0010 /* SLIMCLK_SRC */
  3644. #define ARIZONA_SLIMCLK_SRC_MASK 0x0010 /* SLIMCLK_SRC */
  3645. #define ARIZONA_SLIMCLK_SRC_SHIFT 4 /* SLIMCLK_SRC */
  3646. #define ARIZONA_SLIMCLK_SRC_WIDTH 1 /* SLIMCLK_SRC */
  3647. #define ARIZONA_FRAMER_REF_GEAR_MASK 0x000F /* FRAMER_REF_GEAR - [3:0] */
  3648. #define ARIZONA_FRAMER_REF_GEAR_SHIFT 0 /* FRAMER_REF_GEAR - [3:0] */
  3649. #define ARIZONA_FRAMER_REF_GEAR_WIDTH 4 /* FRAMER_REF_GEAR - [3:0] */
  3650. /*
  3651. * R1509 (0x5E5) - SLIMbus Rates 1
  3652. */
  3653. #define ARIZONA_SLIMRX2_RATE_MASK 0x7800 /* SLIMRX2_RATE - [14:11] */
  3654. #define ARIZONA_SLIMRX2_RATE_SHIFT 11 /* SLIMRX2_RATE - [14:11] */
  3655. #define ARIZONA_SLIMRX2_RATE_WIDTH 4 /* SLIMRX2_RATE - [14:11] */
  3656. #define ARIZONA_SLIMRX1_RATE_MASK 0x0078 /* SLIMRX1_RATE - [6:3] */
  3657. #define ARIZONA_SLIMRX1_RATE_SHIFT 3 /* SLIMRX1_RATE - [6:3] */
  3658. #define ARIZONA_SLIMRX1_RATE_WIDTH 4 /* SLIMRX1_RATE - [6:3] */
  3659. /*
  3660. * R1510 (0x5E6) - SLIMbus Rates 2
  3661. */
  3662. #define ARIZONA_SLIMRX4_RATE_MASK 0x7800 /* SLIMRX4_RATE - [14:11] */
  3663. #define ARIZONA_SLIMRX4_RATE_SHIFT 11 /* SLIMRX4_RATE - [14:11] */
  3664. #define ARIZONA_SLIMRX4_RATE_WIDTH 4 /* SLIMRX4_RATE - [14:11] */
  3665. #define ARIZONA_SLIMRX3_RATE_MASK 0x0078 /* SLIMRX3_RATE - [6:3] */
  3666. #define ARIZONA_SLIMRX3_RATE_SHIFT 3 /* SLIMRX3_RATE - [6:3] */
  3667. #define ARIZONA_SLIMRX3_RATE_WIDTH 4 /* SLIMRX3_RATE - [6:3] */
  3668. /*
  3669. * R1511 (0x5E7) - SLIMbus Rates 3
  3670. */
  3671. #define ARIZONA_SLIMRX6_RATE_MASK 0x7800 /* SLIMRX6_RATE - [14:11] */
  3672. #define ARIZONA_SLIMRX6_RATE_SHIFT 11 /* SLIMRX6_RATE - [14:11] */
  3673. #define ARIZONA_SLIMRX6_RATE_WIDTH 4 /* SLIMRX6_RATE - [14:11] */
  3674. #define ARIZONA_SLIMRX5_RATE_MASK 0x0078 /* SLIMRX5_RATE - [6:3] */
  3675. #define ARIZONA_SLIMRX5_RATE_SHIFT 3 /* SLIMRX5_RATE - [6:3] */
  3676. #define ARIZONA_SLIMRX5_RATE_WIDTH 4 /* SLIMRX5_RATE - [6:3] */
  3677. /*
  3678. * R1512 (0x5E8) - SLIMbus Rates 4
  3679. */
  3680. #define ARIZONA_SLIMRX8_RATE_MASK 0x7800 /* SLIMRX8_RATE - [14:11] */
  3681. #define ARIZONA_SLIMRX8_RATE_SHIFT 11 /* SLIMRX8_RATE - [14:11] */
  3682. #define ARIZONA_SLIMRX8_RATE_WIDTH 4 /* SLIMRX8_RATE - [14:11] */
  3683. #define ARIZONA_SLIMRX7_RATE_MASK 0x0078 /* SLIMRX7_RATE - [6:3] */
  3684. #define ARIZONA_SLIMRX7_RATE_SHIFT 3 /* SLIMRX7_RATE - [6:3] */
  3685. #define ARIZONA_SLIMRX7_RATE_WIDTH 4 /* SLIMRX7_RATE - [6:3] */
  3686. /*
  3687. * R1513 (0x5E9) - SLIMbus Rates 5
  3688. */
  3689. #define ARIZONA_SLIMTX2_RATE_MASK 0x7800 /* SLIMTX2_RATE - [14:11] */
  3690. #define ARIZONA_SLIMTX2_RATE_SHIFT 11 /* SLIMTX2_RATE - [14:11] */
  3691. #define ARIZONA_SLIMTX2_RATE_WIDTH 4 /* SLIMTX2_RATE - [14:11] */
  3692. #define ARIZONA_SLIMTX1_RATE_MASK 0x0078 /* SLIMTX1_RATE - [6:3] */
  3693. #define ARIZONA_SLIMTX1_RATE_SHIFT 3 /* SLIMTX1_RATE - [6:3] */
  3694. #define ARIZONA_SLIMTX1_RATE_WIDTH 4 /* SLIMTX1_RATE - [6:3] */
  3695. /*
  3696. * R1514 (0x5EA) - SLIMbus Rates 6
  3697. */
  3698. #define ARIZONA_SLIMTX4_RATE_MASK 0x7800 /* SLIMTX4_RATE - [14:11] */
  3699. #define ARIZONA_SLIMTX4_RATE_SHIFT 11 /* SLIMTX4_RATE - [14:11] */
  3700. #define ARIZONA_SLIMTX4_RATE_WIDTH 4 /* SLIMTX4_RATE - [14:11] */
  3701. #define ARIZONA_SLIMTX3_RATE_MASK 0x0078 /* SLIMTX3_RATE - [6:3] */
  3702. #define ARIZONA_SLIMTX3_RATE_SHIFT 3 /* SLIMTX3_RATE - [6:3] */
  3703. #define ARIZONA_SLIMTX3_RATE_WIDTH 4 /* SLIMTX3_RATE - [6:3] */
  3704. /*
  3705. * R1515 (0x5EB) - SLIMbus Rates 7
  3706. */
  3707. #define ARIZONA_SLIMTX6_RATE_MASK 0x7800 /* SLIMTX6_RATE - [14:11] */
  3708. #define ARIZONA_SLIMTX6_RATE_SHIFT 11 /* SLIMTX6_RATE - [14:11] */
  3709. #define ARIZONA_SLIMTX6_RATE_WIDTH 4 /* SLIMTX6_RATE - [14:11] */
  3710. #define ARIZONA_SLIMTX5_RATE_MASK 0x0078 /* SLIMTX5_RATE - [6:3] */
  3711. #define ARIZONA_SLIMTX5_RATE_SHIFT 3 /* SLIMTX5_RATE - [6:3] */
  3712. #define ARIZONA_SLIMTX5_RATE_WIDTH 4 /* SLIMTX5_RATE - [6:3] */
  3713. /*
  3714. * R1516 (0x5EC) - SLIMbus Rates 8
  3715. */
  3716. #define ARIZONA_SLIMTX8_RATE_MASK 0x7800 /* SLIMTX8_RATE - [14:11] */
  3717. #define ARIZONA_SLIMTX8_RATE_SHIFT 11 /* SLIMTX8_RATE - [14:11] */
  3718. #define ARIZONA_SLIMTX8_RATE_WIDTH 4 /* SLIMTX8_RATE - [14:11] */
  3719. #define ARIZONA_SLIMTX7_RATE_MASK 0x0078 /* SLIMTX7_RATE - [6:3] */
  3720. #define ARIZONA_SLIMTX7_RATE_SHIFT 3 /* SLIMTX7_RATE - [6:3] */
  3721. #define ARIZONA_SLIMTX7_RATE_WIDTH 4 /* SLIMTX7_RATE - [6:3] */
  3722. /*
  3723. * R1525 (0x5F5) - SLIMbus RX Channel Enable
  3724. */
  3725. #define ARIZONA_SLIMRX8_ENA 0x0080 /* SLIMRX8_ENA */
  3726. #define ARIZONA_SLIMRX8_ENA_MASK 0x0080 /* SLIMRX8_ENA */
  3727. #define ARIZONA_SLIMRX8_ENA_SHIFT 7 /* SLIMRX8_ENA */
  3728. #define ARIZONA_SLIMRX8_ENA_WIDTH 1 /* SLIMRX8_ENA */
  3729. #define ARIZONA_SLIMRX7_ENA 0x0040 /* SLIMRX7_ENA */
  3730. #define ARIZONA_SLIMRX7_ENA_MASK 0x0040 /* SLIMRX7_ENA */
  3731. #define ARIZONA_SLIMRX7_ENA_SHIFT 6 /* SLIMRX7_ENA */
  3732. #define ARIZONA_SLIMRX7_ENA_WIDTH 1 /* SLIMRX7_ENA */
  3733. #define ARIZONA_SLIMRX6_ENA 0x0020 /* SLIMRX6_ENA */
  3734. #define ARIZONA_SLIMRX6_ENA_MASK 0x0020 /* SLIMRX6_ENA */
  3735. #define ARIZONA_SLIMRX6_ENA_SHIFT 5 /* SLIMRX6_ENA */
  3736. #define ARIZONA_SLIMRX6_ENA_WIDTH 1 /* SLIMRX6_ENA */
  3737. #define ARIZONA_SLIMRX5_ENA 0x0010 /* SLIMRX5_ENA */
  3738. #define ARIZONA_SLIMRX5_ENA_MASK 0x0010 /* SLIMRX5_ENA */
  3739. #define ARIZONA_SLIMRX5_ENA_SHIFT 4 /* SLIMRX5_ENA */
  3740. #define ARIZONA_SLIMRX5_ENA_WIDTH 1 /* SLIMRX5_ENA */
  3741. #define ARIZONA_SLIMRX4_ENA 0x0008 /* SLIMRX4_ENA */
  3742. #define ARIZONA_SLIMRX4_ENA_MASK 0x0008 /* SLIMRX4_ENA */
  3743. #define ARIZONA_SLIMRX4_ENA_SHIFT 3 /* SLIMRX4_ENA */
  3744. #define ARIZONA_SLIMRX4_ENA_WIDTH 1 /* SLIMRX4_ENA */
  3745. #define ARIZONA_SLIMRX3_ENA 0x0004 /* SLIMRX3_ENA */
  3746. #define ARIZONA_SLIMRX3_ENA_MASK 0x0004 /* SLIMRX3_ENA */
  3747. #define ARIZONA_SLIMRX3_ENA_SHIFT 2 /* SLIMRX3_ENA */
  3748. #define ARIZONA_SLIMRX3_ENA_WIDTH 1 /* SLIMRX3_ENA */
  3749. #define ARIZONA_SLIMRX2_ENA 0x0002 /* SLIMRX2_ENA */
  3750. #define ARIZONA_SLIMRX2_ENA_MASK 0x0002 /* SLIMRX2_ENA */
  3751. #define ARIZONA_SLIMRX2_ENA_SHIFT 1 /* SLIMRX2_ENA */
  3752. #define ARIZONA_SLIMRX2_ENA_WIDTH 1 /* SLIMRX2_ENA */
  3753. #define ARIZONA_SLIMRX1_ENA 0x0001 /* SLIMRX1_ENA */
  3754. #define ARIZONA_SLIMRX1_ENA_MASK 0x0001 /* SLIMRX1_ENA */
  3755. #define ARIZONA_SLIMRX1_ENA_SHIFT 0 /* SLIMRX1_ENA */
  3756. #define ARIZONA_SLIMRX1_ENA_WIDTH 1 /* SLIMRX1_ENA */
  3757. /*
  3758. * R1526 (0x5F6) - SLIMbus TX Channel Enable
  3759. */
  3760. #define ARIZONA_SLIMTX8_ENA 0x0080 /* SLIMTX8_ENA */
  3761. #define ARIZONA_SLIMTX8_ENA_MASK 0x0080 /* SLIMTX8_ENA */
  3762. #define ARIZONA_SLIMTX8_ENA_SHIFT 7 /* SLIMTX8_ENA */
  3763. #define ARIZONA_SLIMTX8_ENA_WIDTH 1 /* SLIMTX8_ENA */
  3764. #define ARIZONA_SLIMTX7_ENA 0x0040 /* SLIMTX7_ENA */
  3765. #define ARIZONA_SLIMTX7_ENA_MASK 0x0040 /* SLIMTX7_ENA */
  3766. #define ARIZONA_SLIMTX7_ENA_SHIFT 6 /* SLIMTX7_ENA */
  3767. #define ARIZONA_SLIMTX7_ENA_WIDTH 1 /* SLIMTX7_ENA */
  3768. #define ARIZONA_SLIMTX6_ENA 0x0020 /* SLIMTX6_ENA */
  3769. #define ARIZONA_SLIMTX6_ENA_MASK 0x0020 /* SLIMTX6_ENA */
  3770. #define ARIZONA_SLIMTX6_ENA_SHIFT 5 /* SLIMTX6_ENA */
  3771. #define ARIZONA_SLIMTX6_ENA_WIDTH 1 /* SLIMTX6_ENA */
  3772. #define ARIZONA_SLIMTX5_ENA 0x0010 /* SLIMTX5_ENA */
  3773. #define ARIZONA_SLIMTX5_ENA_MASK 0x0010 /* SLIMTX5_ENA */
  3774. #define ARIZONA_SLIMTX5_ENA_SHIFT 4 /* SLIMTX5_ENA */
  3775. #define ARIZONA_SLIMTX5_ENA_WIDTH 1 /* SLIMTX5_ENA */
  3776. #define ARIZONA_SLIMTX4_ENA 0x0008 /* SLIMTX4_ENA */
  3777. #define ARIZONA_SLIMTX4_ENA_MASK 0x0008 /* SLIMTX4_ENA */
  3778. #define ARIZONA_SLIMTX4_ENA_SHIFT 3 /* SLIMTX4_ENA */
  3779. #define ARIZONA_SLIMTX4_ENA_WIDTH 1 /* SLIMTX4_ENA */
  3780. #define ARIZONA_SLIMTX3_ENA 0x0004 /* SLIMTX3_ENA */
  3781. #define ARIZONA_SLIMTX3_ENA_MASK 0x0004 /* SLIMTX3_ENA */
  3782. #define ARIZONA_SLIMTX3_ENA_SHIFT 2 /* SLIMTX3_ENA */
  3783. #define ARIZONA_SLIMTX3_ENA_WIDTH 1 /* SLIMTX3_ENA */
  3784. #define ARIZONA_SLIMTX2_ENA 0x0002 /* SLIMTX2_ENA */
  3785. #define ARIZONA_SLIMTX2_ENA_MASK 0x0002 /* SLIMTX2_ENA */
  3786. #define ARIZONA_SLIMTX2_ENA_SHIFT 1 /* SLIMTX2_ENA */
  3787. #define ARIZONA_SLIMTX2_ENA_WIDTH 1 /* SLIMTX2_ENA */
  3788. #define ARIZONA_SLIMTX1_ENA 0x0001 /* SLIMTX1_ENA */
  3789. #define ARIZONA_SLIMTX1_ENA_MASK 0x0001 /* SLIMTX1_ENA */
  3790. #define ARIZONA_SLIMTX1_ENA_SHIFT 0 /* SLIMTX1_ENA */
  3791. #define ARIZONA_SLIMTX1_ENA_WIDTH 1 /* SLIMTX1_ENA */
  3792. /*
  3793. * R1527 (0x5F7) - SLIMbus RX Port Status
  3794. */
  3795. #define ARIZONA_SLIMRX8_PORT_STS 0x0080 /* SLIMRX8_PORT_STS */
  3796. #define ARIZONA_SLIMRX8_PORT_STS_MASK 0x0080 /* SLIMRX8_PORT_STS */
  3797. #define ARIZONA_SLIMRX8_PORT_STS_SHIFT 7 /* SLIMRX8_PORT_STS */
  3798. #define ARIZONA_SLIMRX8_PORT_STS_WIDTH 1 /* SLIMRX8_PORT_STS */
  3799. #define ARIZONA_SLIMRX7_PORT_STS 0x0040 /* SLIMRX7_PORT_STS */
  3800. #define ARIZONA_SLIMRX7_PORT_STS_MASK 0x0040 /* SLIMRX7_PORT_STS */
  3801. #define ARIZONA_SLIMRX7_PORT_STS_SHIFT 6 /* SLIMRX7_PORT_STS */
  3802. #define ARIZONA_SLIMRX7_PORT_STS_WIDTH 1 /* SLIMRX7_PORT_STS */
  3803. #define ARIZONA_SLIMRX6_PORT_STS 0x0020 /* SLIMRX6_PORT_STS */
  3804. #define ARIZONA_SLIMRX6_PORT_STS_MASK 0x0020 /* SLIMRX6_PORT_STS */
  3805. #define ARIZONA_SLIMRX6_PORT_STS_SHIFT 5 /* SLIMRX6_PORT_STS */
  3806. #define ARIZONA_SLIMRX6_PORT_STS_WIDTH 1 /* SLIMRX6_PORT_STS */
  3807. #define ARIZONA_SLIMRX5_PORT_STS 0x0010 /* SLIMRX5_PORT_STS */
  3808. #define ARIZONA_SLIMRX5_PORT_STS_MASK 0x0010 /* SLIMRX5_PORT_STS */
  3809. #define ARIZONA_SLIMRX5_PORT_STS_SHIFT 4 /* SLIMRX5_PORT_STS */
  3810. #define ARIZONA_SLIMRX5_PORT_STS_WIDTH 1 /* SLIMRX5_PORT_STS */
  3811. #define ARIZONA_SLIMRX4_PORT_STS 0x0008 /* SLIMRX4_PORT_STS */
  3812. #define ARIZONA_SLIMRX4_PORT_STS_MASK 0x0008 /* SLIMRX4_PORT_STS */
  3813. #define ARIZONA_SLIMRX4_PORT_STS_SHIFT 3 /* SLIMRX4_PORT_STS */
  3814. #define ARIZONA_SLIMRX4_PORT_STS_WIDTH 1 /* SLIMRX4_PORT_STS */
  3815. #define ARIZONA_SLIMRX3_PORT_STS 0x0004 /* SLIMRX3_PORT_STS */
  3816. #define ARIZONA_SLIMRX3_PORT_STS_MASK 0x0004 /* SLIMRX3_PORT_STS */
  3817. #define ARIZONA_SLIMRX3_PORT_STS_SHIFT 2 /* SLIMRX3_PORT_STS */
  3818. #define ARIZONA_SLIMRX3_PORT_STS_WIDTH 1 /* SLIMRX3_PORT_STS */
  3819. #define ARIZONA_SLIMRX2_PORT_STS 0x0002 /* SLIMRX2_PORT_STS */
  3820. #define ARIZONA_SLIMRX2_PORT_STS_MASK 0x0002 /* SLIMRX2_PORT_STS */
  3821. #define ARIZONA_SLIMRX2_PORT_STS_SHIFT 1 /* SLIMRX2_PORT_STS */
  3822. #define ARIZONA_SLIMRX2_PORT_STS_WIDTH 1 /* SLIMRX2_PORT_STS */
  3823. #define ARIZONA_SLIMRX1_PORT_STS 0x0001 /* SLIMRX1_PORT_STS */
  3824. #define ARIZONA_SLIMRX1_PORT_STS_MASK 0x0001 /* SLIMRX1_PORT_STS */
  3825. #define ARIZONA_SLIMRX1_PORT_STS_SHIFT 0 /* SLIMRX1_PORT_STS */
  3826. #define ARIZONA_SLIMRX1_PORT_STS_WIDTH 1 /* SLIMRX1_PORT_STS */
  3827. /*
  3828. * R1528 (0x5F8) - SLIMbus TX Port Status
  3829. */
  3830. #define ARIZONA_SLIMTX8_PORT_STS 0x0080 /* SLIMTX8_PORT_STS */
  3831. #define ARIZONA_SLIMTX8_PORT_STS_MASK 0x0080 /* SLIMTX8_PORT_STS */
  3832. #define ARIZONA_SLIMTX8_PORT_STS_SHIFT 7 /* SLIMTX8_PORT_STS */
  3833. #define ARIZONA_SLIMTX8_PORT_STS_WIDTH 1 /* SLIMTX8_PORT_STS */
  3834. #define ARIZONA_SLIMTX7_PORT_STS 0x0040 /* SLIMTX7_PORT_STS */
  3835. #define ARIZONA_SLIMTX7_PORT_STS_MASK 0x0040 /* SLIMTX7_PORT_STS */
  3836. #define ARIZONA_SLIMTX7_PORT_STS_SHIFT 6 /* SLIMTX7_PORT_STS */
  3837. #define ARIZONA_SLIMTX7_PORT_STS_WIDTH 1 /* SLIMTX7_PORT_STS */
  3838. #define ARIZONA_SLIMTX6_PORT_STS 0x0020 /* SLIMTX6_PORT_STS */
  3839. #define ARIZONA_SLIMTX6_PORT_STS_MASK 0x0020 /* SLIMTX6_PORT_STS */
  3840. #define ARIZONA_SLIMTX6_PORT_STS_SHIFT 5 /* SLIMTX6_PORT_STS */
  3841. #define ARIZONA_SLIMTX6_PORT_STS_WIDTH 1 /* SLIMTX6_PORT_STS */
  3842. #define ARIZONA_SLIMTX5_PORT_STS 0x0010 /* SLIMTX5_PORT_STS */
  3843. #define ARIZONA_SLIMTX5_PORT_STS_MASK 0x0010 /* SLIMTX5_PORT_STS */
  3844. #define ARIZONA_SLIMTX5_PORT_STS_SHIFT 4 /* SLIMTX5_PORT_STS */
  3845. #define ARIZONA_SLIMTX5_PORT_STS_WIDTH 1 /* SLIMTX5_PORT_STS */
  3846. #define ARIZONA_SLIMTX4_PORT_STS 0x0008 /* SLIMTX4_PORT_STS */
  3847. #define ARIZONA_SLIMTX4_PORT_STS_MASK 0x0008 /* SLIMTX4_PORT_STS */
  3848. #define ARIZONA_SLIMTX4_PORT_STS_SHIFT 3 /* SLIMTX4_PORT_STS */
  3849. #define ARIZONA_SLIMTX4_PORT_STS_WIDTH 1 /* SLIMTX4_PORT_STS */
  3850. #define ARIZONA_SLIMTX3_PORT_STS 0x0004 /* SLIMTX3_PORT_STS */
  3851. #define ARIZONA_SLIMTX3_PORT_STS_MASK 0x0004 /* SLIMTX3_PORT_STS */
  3852. #define ARIZONA_SLIMTX3_PORT_STS_SHIFT 2 /* SLIMTX3_PORT_STS */
  3853. #define ARIZONA_SLIMTX3_PORT_STS_WIDTH 1 /* SLIMTX3_PORT_STS */
  3854. #define ARIZONA_SLIMTX2_PORT_STS 0x0002 /* SLIMTX2_PORT_STS */
  3855. #define ARIZONA_SLIMTX2_PORT_STS_MASK 0x0002 /* SLIMTX2_PORT_STS */
  3856. #define ARIZONA_SLIMTX2_PORT_STS_SHIFT 1 /* SLIMTX2_PORT_STS */
  3857. #define ARIZONA_SLIMTX2_PORT_STS_WIDTH 1 /* SLIMTX2_PORT_STS */
  3858. #define ARIZONA_SLIMTX1_PORT_STS 0x0001 /* SLIMTX1_PORT_STS */
  3859. #define ARIZONA_SLIMTX1_PORT_STS_MASK 0x0001 /* SLIMTX1_PORT_STS */
  3860. #define ARIZONA_SLIMTX1_PORT_STS_SHIFT 0 /* SLIMTX1_PORT_STS */
  3861. #define ARIZONA_SLIMTX1_PORT_STS_WIDTH 1 /* SLIMTX1_PORT_STS */
  3862. /*
  3863. * R3087 (0xC0F) - IRQ CTRL 1
  3864. */
  3865. #define ARIZONA_IRQ_POL 0x0400 /* IRQ_POL */
  3866. #define ARIZONA_IRQ_POL_MASK 0x0400 /* IRQ_POL */
  3867. #define ARIZONA_IRQ_POL_SHIFT 10 /* IRQ_POL */
  3868. #define ARIZONA_IRQ_POL_WIDTH 1 /* IRQ_POL */
  3869. #define ARIZONA_IRQ_OP_CFG 0x0200 /* IRQ_OP_CFG */
  3870. #define ARIZONA_IRQ_OP_CFG_MASK 0x0200 /* IRQ_OP_CFG */
  3871. #define ARIZONA_IRQ_OP_CFG_SHIFT 9 /* IRQ_OP_CFG */
  3872. #define ARIZONA_IRQ_OP_CFG_WIDTH 1 /* IRQ_OP_CFG */
  3873. /*
  3874. * R3088 (0xC10) - GPIO Debounce Config
  3875. */
  3876. #define ARIZONA_GP_DBTIME_MASK 0xF000 /* GP_DBTIME - [15:12] */
  3877. #define ARIZONA_GP_DBTIME_SHIFT 12 /* GP_DBTIME - [15:12] */
  3878. #define ARIZONA_GP_DBTIME_WIDTH 4 /* GP_DBTIME - [15:12] */
  3879. /*
  3880. * R3104 (0xC20) - Misc Pad Ctrl 1
  3881. */
  3882. #define ARIZONA_LDO1ENA_PD 0x8000 /* LDO1ENA_PD */
  3883. #define ARIZONA_LDO1ENA_PD_MASK 0x8000 /* LDO1ENA_PD */
  3884. #define ARIZONA_LDO1ENA_PD_SHIFT 15 /* LDO1ENA_PD */
  3885. #define ARIZONA_LDO1ENA_PD_WIDTH 1 /* LDO1ENA_PD */
  3886. #define ARIZONA_MCLK2_PD 0x2000 /* MCLK2_PD */
  3887. #define ARIZONA_MCLK2_PD_MASK 0x2000 /* MCLK2_PD */
  3888. #define ARIZONA_MCLK2_PD_SHIFT 13 /* MCLK2_PD */
  3889. #define ARIZONA_MCLK2_PD_WIDTH 1 /* MCLK2_PD */
  3890. #define ARIZONA_RSTB_PU 0x0002 /* RSTB_PU */
  3891. #define ARIZONA_RSTB_PU_MASK 0x0002 /* RSTB_PU */
  3892. #define ARIZONA_RSTB_PU_SHIFT 1 /* RSTB_PU */
  3893. #define ARIZONA_RSTB_PU_WIDTH 1 /* RSTB_PU */
  3894. /*
  3895. * R3105 (0xC21) - Misc Pad Ctrl 2
  3896. */
  3897. #define ARIZONA_MCLK1_PD 0x1000 /* MCLK1_PD */
  3898. #define ARIZONA_MCLK1_PD_MASK 0x1000 /* MCLK1_PD */
  3899. #define ARIZONA_MCLK1_PD_SHIFT 12 /* MCLK1_PD */
  3900. #define ARIZONA_MCLK1_PD_WIDTH 1 /* MCLK1_PD */
  3901. #define ARIZONA_MICD_PD 0x0100 /* MICD_PD */
  3902. #define ARIZONA_MICD_PD_MASK 0x0100 /* MICD_PD */
  3903. #define ARIZONA_MICD_PD_SHIFT 8 /* MICD_PD */
  3904. #define ARIZONA_MICD_PD_WIDTH 1 /* MICD_PD */
  3905. #define ARIZONA_ADDR_PD 0x0001 /* ADDR_PD */
  3906. #define ARIZONA_ADDR_PD_MASK 0x0001 /* ADDR_PD */
  3907. #define ARIZONA_ADDR_PD_SHIFT 0 /* ADDR_PD */
  3908. #define ARIZONA_ADDR_PD_WIDTH 1 /* ADDR_PD */
  3909. /*
  3910. * R3106 (0xC22) - Misc Pad Ctrl 3
  3911. */
  3912. #define ARIZONA_DMICDAT4_PD 0x0008 /* DMICDAT4_PD */
  3913. #define ARIZONA_DMICDAT4_PD_MASK 0x0008 /* DMICDAT4_PD */
  3914. #define ARIZONA_DMICDAT4_PD_SHIFT 3 /* DMICDAT4_PD */
  3915. #define ARIZONA_DMICDAT4_PD_WIDTH 1 /* DMICDAT4_PD */
  3916. #define ARIZONA_DMICDAT3_PD 0x0004 /* DMICDAT3_PD */
  3917. #define ARIZONA_DMICDAT3_PD_MASK 0x0004 /* DMICDAT3_PD */
  3918. #define ARIZONA_DMICDAT3_PD_SHIFT 2 /* DMICDAT3_PD */
  3919. #define ARIZONA_DMICDAT3_PD_WIDTH 1 /* DMICDAT3_PD */
  3920. #define ARIZONA_DMICDAT2_PD 0x0002 /* DMICDAT2_PD */
  3921. #define ARIZONA_DMICDAT2_PD_MASK 0x0002 /* DMICDAT2_PD */
  3922. #define ARIZONA_DMICDAT2_PD_SHIFT 1 /* DMICDAT2_PD */
  3923. #define ARIZONA_DMICDAT2_PD_WIDTH 1 /* DMICDAT2_PD */
  3924. #define ARIZONA_DMICDAT1_PD 0x0001 /* DMICDAT1_PD */
  3925. #define ARIZONA_DMICDAT1_PD_MASK 0x0001 /* DMICDAT1_PD */
  3926. #define ARIZONA_DMICDAT1_PD_SHIFT 0 /* DMICDAT1_PD */
  3927. #define ARIZONA_DMICDAT1_PD_WIDTH 1 /* DMICDAT1_PD */
  3928. /*
  3929. * R3107 (0xC23) - Misc Pad Ctrl 4
  3930. */
  3931. #define ARIZONA_AIF1RXLRCLK_PU 0x0020 /* AIF1RXLRCLK_PU */
  3932. #define ARIZONA_AIF1RXLRCLK_PU_MASK 0x0020 /* AIF1RXLRCLK_PU */
  3933. #define ARIZONA_AIF1RXLRCLK_PU_SHIFT 5 /* AIF1RXLRCLK_PU */
  3934. #define ARIZONA_AIF1RXLRCLK_PU_WIDTH 1 /* AIF1RXLRCLK_PU */
  3935. #define ARIZONA_AIF1RXLRCLK_PD 0x0010 /* AIF1RXLRCLK_PD */
  3936. #define ARIZONA_AIF1RXLRCLK_PD_MASK 0x0010 /* AIF1RXLRCLK_PD */
  3937. #define ARIZONA_AIF1RXLRCLK_PD_SHIFT 4 /* AIF1RXLRCLK_PD */
  3938. #define ARIZONA_AIF1RXLRCLK_PD_WIDTH 1 /* AIF1RXLRCLK_PD */
  3939. #define ARIZONA_AIF1BCLK_PU 0x0008 /* AIF1BCLK_PU */
  3940. #define ARIZONA_AIF1BCLK_PU_MASK 0x0008 /* AIF1BCLK_PU */
  3941. #define ARIZONA_AIF1BCLK_PU_SHIFT 3 /* AIF1BCLK_PU */
  3942. #define ARIZONA_AIF1BCLK_PU_WIDTH 1 /* AIF1BCLK_PU */
  3943. #define ARIZONA_AIF1BCLK_PD 0x0004 /* AIF1BCLK_PD */
  3944. #define ARIZONA_AIF1BCLK_PD_MASK 0x0004 /* AIF1BCLK_PD */
  3945. #define ARIZONA_AIF1BCLK_PD_SHIFT 2 /* AIF1BCLK_PD */
  3946. #define ARIZONA_AIF1BCLK_PD_WIDTH 1 /* AIF1BCLK_PD */
  3947. #define ARIZONA_AIF1RXDAT_PU 0x0002 /* AIF1RXDAT_PU */
  3948. #define ARIZONA_AIF1RXDAT_PU_MASK 0x0002 /* AIF1RXDAT_PU */
  3949. #define ARIZONA_AIF1RXDAT_PU_SHIFT 1 /* AIF1RXDAT_PU */
  3950. #define ARIZONA_AIF1RXDAT_PU_WIDTH 1 /* AIF1RXDAT_PU */
  3951. #define ARIZONA_AIF1RXDAT_PD 0x0001 /* AIF1RXDAT_PD */
  3952. #define ARIZONA_AIF1RXDAT_PD_MASK 0x0001 /* AIF1RXDAT_PD */
  3953. #define ARIZONA_AIF1RXDAT_PD_SHIFT 0 /* AIF1RXDAT_PD */
  3954. #define ARIZONA_AIF1RXDAT_PD_WIDTH 1 /* AIF1RXDAT_PD */
  3955. /*
  3956. * R3108 (0xC24) - Misc Pad Ctrl 5
  3957. */
  3958. #define ARIZONA_AIF2RXLRCLK_PU 0x0020 /* AIF2RXLRCLK_PU */
  3959. #define ARIZONA_AIF2RXLRCLK_PU_MASK 0x0020 /* AIF2RXLRCLK_PU */
  3960. #define ARIZONA_AIF2RXLRCLK_PU_SHIFT 5 /* AIF2RXLRCLK_PU */
  3961. #define ARIZONA_AIF2RXLRCLK_PU_WIDTH 1 /* AIF2RXLRCLK_PU */
  3962. #define ARIZONA_AIF2RXLRCLK_PD 0x0010 /* AIF2RXLRCLK_PD */
  3963. #define ARIZONA_AIF2RXLRCLK_PD_MASK 0x0010 /* AIF2RXLRCLK_PD */
  3964. #define ARIZONA_AIF2RXLRCLK_PD_SHIFT 4 /* AIF2RXLRCLK_PD */
  3965. #define ARIZONA_AIF2RXLRCLK_PD_WIDTH 1 /* AIF2RXLRCLK_PD */
  3966. #define ARIZONA_AIF2BCLK_PU 0x0008 /* AIF2BCLK_PU */
  3967. #define ARIZONA_AIF2BCLK_PU_MASK 0x0008 /* AIF2BCLK_PU */
  3968. #define ARIZONA_AIF2BCLK_PU_SHIFT 3 /* AIF2BCLK_PU */
  3969. #define ARIZONA_AIF2BCLK_PU_WIDTH 1 /* AIF2BCLK_PU */
  3970. #define ARIZONA_AIF2BCLK_PD 0x0004 /* AIF2BCLK_PD */
  3971. #define ARIZONA_AIF2BCLK_PD_MASK 0x0004 /* AIF2BCLK_PD */
  3972. #define ARIZONA_AIF2BCLK_PD_SHIFT 2 /* AIF2BCLK_PD */
  3973. #define ARIZONA_AIF2BCLK_PD_WIDTH 1 /* AIF2BCLK_PD */
  3974. #define ARIZONA_AIF2RXDAT_PU 0x0002 /* AIF2RXDAT_PU */
  3975. #define ARIZONA_AIF2RXDAT_PU_MASK 0x0002 /* AIF2RXDAT_PU */
  3976. #define ARIZONA_AIF2RXDAT_PU_SHIFT 1 /* AIF2RXDAT_PU */
  3977. #define ARIZONA_AIF2RXDAT_PU_WIDTH 1 /* AIF2RXDAT_PU */
  3978. #define ARIZONA_AIF2RXDAT_PD 0x0001 /* AIF2RXDAT_PD */
  3979. #define ARIZONA_AIF2RXDAT_PD_MASK 0x0001 /* AIF2RXDAT_PD */
  3980. #define ARIZONA_AIF2RXDAT_PD_SHIFT 0 /* AIF2RXDAT_PD */
  3981. #define ARIZONA_AIF2RXDAT_PD_WIDTH 1 /* AIF2RXDAT_PD */
  3982. /*
  3983. * R3109 (0xC25) - Misc Pad Ctrl 6
  3984. */
  3985. #define ARIZONA_AIF3RXLRCLK_PU 0x0020 /* AIF3RXLRCLK_PU */
  3986. #define ARIZONA_AIF3RXLRCLK_PU_MASK 0x0020 /* AIF3RXLRCLK_PU */
  3987. #define ARIZONA_AIF3RXLRCLK_PU_SHIFT 5 /* AIF3RXLRCLK_PU */
  3988. #define ARIZONA_AIF3RXLRCLK_PU_WIDTH 1 /* AIF3RXLRCLK_PU */
  3989. #define ARIZONA_AIF3RXLRCLK_PD 0x0010 /* AIF3RXLRCLK_PD */
  3990. #define ARIZONA_AIF3RXLRCLK_PD_MASK 0x0010 /* AIF3RXLRCLK_PD */
  3991. #define ARIZONA_AIF3RXLRCLK_PD_SHIFT 4 /* AIF3RXLRCLK_PD */
  3992. #define ARIZONA_AIF3RXLRCLK_PD_WIDTH 1 /* AIF3RXLRCLK_PD */
  3993. #define ARIZONA_AIF3BCLK_PU 0x0008 /* AIF3BCLK_PU */
  3994. #define ARIZONA_AIF3BCLK_PU_MASK 0x0008 /* AIF3BCLK_PU */
  3995. #define ARIZONA_AIF3BCLK_PU_SHIFT 3 /* AIF3BCLK_PU */
  3996. #define ARIZONA_AIF3BCLK_PU_WIDTH 1 /* AIF3BCLK_PU */
  3997. #define ARIZONA_AIF3BCLK_PD 0x0004 /* AIF3BCLK_PD */
  3998. #define ARIZONA_AIF3BCLK_PD_MASK 0x0004 /* AIF3BCLK_PD */
  3999. #define ARIZONA_AIF3BCLK_PD_SHIFT 2 /* AIF3BCLK_PD */
  4000. #define ARIZONA_AIF3BCLK_PD_WIDTH 1 /* AIF3BCLK_PD */
  4001. #define ARIZONA_AIF3RXDAT_PU 0x0002 /* AIF3RXDAT_PU */
  4002. #define ARIZONA_AIF3RXDAT_PU_MASK 0x0002 /* AIF3RXDAT_PU */
  4003. #define ARIZONA_AIF3RXDAT_PU_SHIFT 1 /* AIF3RXDAT_PU */
  4004. #define ARIZONA_AIF3RXDAT_PU_WIDTH 1 /* AIF3RXDAT_PU */
  4005. #define ARIZONA_AIF3RXDAT_PD 0x0001 /* AIF3RXDAT_PD */
  4006. #define ARIZONA_AIF3RXDAT_PD_MASK 0x0001 /* AIF3RXDAT_PD */
  4007. #define ARIZONA_AIF3RXDAT_PD_SHIFT 0 /* AIF3RXDAT_PD */
  4008. #define ARIZONA_AIF3RXDAT_PD_WIDTH 1 /* AIF3RXDAT_PD */
  4009. /*
  4010. * R3328 (0xD00) - Interrupt Status 1
  4011. */
  4012. #define ARIZONA_GP4_EINT1 0x0008 /* GP4_EINT1 */
  4013. #define ARIZONA_GP4_EINT1_MASK 0x0008 /* GP4_EINT1 */
  4014. #define ARIZONA_GP4_EINT1_SHIFT 3 /* GP4_EINT1 */
  4015. #define ARIZONA_GP4_EINT1_WIDTH 1 /* GP4_EINT1 */
  4016. #define ARIZONA_GP3_EINT1 0x0004 /* GP3_EINT1 */
  4017. #define ARIZONA_GP3_EINT1_MASK 0x0004 /* GP3_EINT1 */
  4018. #define ARIZONA_GP3_EINT1_SHIFT 2 /* GP3_EINT1 */
  4019. #define ARIZONA_GP3_EINT1_WIDTH 1 /* GP3_EINT1 */
  4020. #define ARIZONA_GP2_EINT1 0x0002 /* GP2_EINT1 */
  4021. #define ARIZONA_GP2_EINT1_MASK 0x0002 /* GP2_EINT1 */
  4022. #define ARIZONA_GP2_EINT1_SHIFT 1 /* GP2_EINT1 */
  4023. #define ARIZONA_GP2_EINT1_WIDTH 1 /* GP2_EINT1 */
  4024. #define ARIZONA_GP1_EINT1 0x0001 /* GP1_EINT1 */
  4025. #define ARIZONA_GP1_EINT1_MASK 0x0001 /* GP1_EINT1 */
  4026. #define ARIZONA_GP1_EINT1_SHIFT 0 /* GP1_EINT1 */
  4027. #define ARIZONA_GP1_EINT1_WIDTH 1 /* GP1_EINT1 */
  4028. /*
  4029. * R3329 (0xD01) - Interrupt Status 2
  4030. */
  4031. #define ARIZONA_DSP4_RAM_RDY_EINT1 0x0800 /* DSP4_RAM_RDY_EINT1 */
  4032. #define ARIZONA_DSP4_RAM_RDY_EINT1_MASK 0x0800 /* DSP4_RAM_RDY_EINT1 */
  4033. #define ARIZONA_DSP4_RAM_RDY_EINT1_SHIFT 11 /* DSP4_RAM_RDY_EINT1 */
  4034. #define ARIZONA_DSP4_RAM_RDY_EINT1_WIDTH 1 /* DSP4_RAM_RDY_EINT1 */
  4035. #define ARIZONA_DSP3_RAM_RDY_EINT1 0x0400 /* DSP3_RAM_RDY_EINT1 */
  4036. #define ARIZONA_DSP3_RAM_RDY_EINT1_MASK 0x0400 /* DSP3_RAM_RDY_EINT1 */
  4037. #define ARIZONA_DSP3_RAM_RDY_EINT1_SHIFT 10 /* DSP3_RAM_RDY_EINT1 */
  4038. #define ARIZONA_DSP3_RAM_RDY_EINT1_WIDTH 1 /* DSP3_RAM_RDY_EINT1 */
  4039. #define ARIZONA_DSP2_RAM_RDY_EINT1 0x0200 /* DSP2_RAM_RDY_EINT1 */
  4040. #define ARIZONA_DSP2_RAM_RDY_EINT1_MASK 0x0200 /* DSP2_RAM_RDY_EINT1 */
  4041. #define ARIZONA_DSP2_RAM_RDY_EINT1_SHIFT 9 /* DSP2_RAM_RDY_EINT1 */
  4042. #define ARIZONA_DSP2_RAM_RDY_EINT1_WIDTH 1 /* DSP2_RAM_RDY_EINT1 */
  4043. #define ARIZONA_DSP1_RAM_RDY_EINT1 0x0100 /* DSP1_RAM_RDY_EINT1 */
  4044. #define ARIZONA_DSP1_RAM_RDY_EINT1_MASK 0x0100 /* DSP1_RAM_RDY_EINT1 */
  4045. #define ARIZONA_DSP1_RAM_RDY_EINT1_SHIFT 8 /* DSP1_RAM_RDY_EINT1 */
  4046. #define ARIZONA_DSP1_RAM_RDY_EINT1_WIDTH 1 /* DSP1_RAM_RDY_EINT1 */
  4047. #define ARIZONA_DSP_IRQ8_EINT1 0x0080 /* DSP_IRQ8_EINT1 */
  4048. #define ARIZONA_DSP_IRQ8_EINT1_MASK 0x0080 /* DSP_IRQ8_EINT1 */
  4049. #define ARIZONA_DSP_IRQ8_EINT1_SHIFT 7 /* DSP_IRQ8_EINT1 */
  4050. #define ARIZONA_DSP_IRQ8_EINT1_WIDTH 1 /* DSP_IRQ8_EINT1 */
  4051. #define ARIZONA_DSP_IRQ7_EINT1 0x0040 /* DSP_IRQ7_EINT1 */
  4052. #define ARIZONA_DSP_IRQ7_EINT1_MASK 0x0040 /* DSP_IRQ7_EINT1 */
  4053. #define ARIZONA_DSP_IRQ7_EINT1_SHIFT 6 /* DSP_IRQ7_EINT1 */
  4054. #define ARIZONA_DSP_IRQ7_EINT1_WIDTH 1 /* DSP_IRQ7_EINT1 */
  4055. #define ARIZONA_DSP_IRQ6_EINT1 0x0020 /* DSP_IRQ6_EINT1 */
  4056. #define ARIZONA_DSP_IRQ6_EINT1_MASK 0x0020 /* DSP_IRQ6_EINT1 */
  4057. #define ARIZONA_DSP_IRQ6_EINT1_SHIFT 5 /* DSP_IRQ6_EINT1 */
  4058. #define ARIZONA_DSP_IRQ6_EINT1_WIDTH 1 /* DSP_IRQ6_EINT1 */
  4059. #define ARIZONA_DSP_IRQ5_EINT1 0x0010 /* DSP_IRQ5_EINT1 */
  4060. #define ARIZONA_DSP_IRQ5_EINT1_MASK 0x0010 /* DSP_IRQ5_EINT1 */
  4061. #define ARIZONA_DSP_IRQ5_EINT1_SHIFT 4 /* DSP_IRQ5_EINT1 */
  4062. #define ARIZONA_DSP_IRQ5_EINT1_WIDTH 1 /* DSP_IRQ5_EINT1 */
  4063. #define ARIZONA_DSP_IRQ4_EINT1 0x0008 /* DSP_IRQ4_EINT1 */
  4064. #define ARIZONA_DSP_IRQ4_EINT1_MASK 0x0008 /* DSP_IRQ4_EINT1 */
  4065. #define ARIZONA_DSP_IRQ4_EINT1_SHIFT 3 /* DSP_IRQ4_EINT1 */
  4066. #define ARIZONA_DSP_IRQ4_EINT1_WIDTH 1 /* DSP_IRQ4_EINT1 */
  4067. #define ARIZONA_DSP_IRQ3_EINT1 0x0004 /* DSP_IRQ3_EINT1 */
  4068. #define ARIZONA_DSP_IRQ3_EINT1_MASK 0x0004 /* DSP_IRQ3_EINT1 */
  4069. #define ARIZONA_DSP_IRQ3_EINT1_SHIFT 2 /* DSP_IRQ3_EINT1 */
  4070. #define ARIZONA_DSP_IRQ3_EINT1_WIDTH 1 /* DSP_IRQ3_EINT1 */
  4071. #define ARIZONA_DSP_IRQ2_EINT1 0x0002 /* DSP_IRQ2_EINT1 */
  4072. #define ARIZONA_DSP_IRQ2_EINT1_MASK 0x0002 /* DSP_IRQ2_EINT1 */
  4073. #define ARIZONA_DSP_IRQ2_EINT1_SHIFT 1 /* DSP_IRQ2_EINT1 */
  4074. #define ARIZONA_DSP_IRQ2_EINT1_WIDTH 1 /* DSP_IRQ2_EINT1 */
  4075. #define ARIZONA_DSP_IRQ1_EINT1 0x0001 /* DSP_IRQ1_EINT1 */
  4076. #define ARIZONA_DSP_IRQ1_EINT1_MASK 0x0001 /* DSP_IRQ1_EINT1 */
  4077. #define ARIZONA_DSP_IRQ1_EINT1_SHIFT 0 /* DSP_IRQ1_EINT1 */
  4078. #define ARIZONA_DSP_IRQ1_EINT1_WIDTH 1 /* DSP_IRQ1_EINT1 */
  4079. /*
  4080. * R3330 (0xD02) - Interrupt Status 3
  4081. */
  4082. #define ARIZONA_SPK_SHUTDOWN_WARN_EINT1 0x8000 /* SPK_SHUTDOWN_WARN_EINT1 */
  4083. #define ARIZONA_SPK_SHUTDOWN_WARN_EINT1_MASK 0x8000 /* SPK_SHUTDOWN_WARN_EINT1 */
  4084. #define ARIZONA_SPK_SHUTDOWN_WARN_EINT1_SHIFT 15 /* SPK_SHUTDOWN_WARN_EINT1 */
  4085. #define ARIZONA_SPK_SHUTDOWN_WARN_EINT1_WIDTH 1 /* SPK_SHUTDOWN_WARN_EINT1 */
  4086. #define ARIZONA_SPK_SHUTDOWN_EINT1 0x4000 /* SPK_SHUTDOWN_EINT1 */
  4087. #define ARIZONA_SPK_SHUTDOWN_EINT1_MASK 0x4000 /* SPK_SHUTDOWN_EINT1 */
  4088. #define ARIZONA_SPK_SHUTDOWN_EINT1_SHIFT 14 /* SPK_SHUTDOWN_EINT1 */
  4089. #define ARIZONA_SPK_SHUTDOWN_EINT1_WIDTH 1 /* SPK_SHUTDOWN_EINT1 */
  4090. #define ARIZONA_HPDET_EINT1 0x2000 /* HPDET_EINT1 */
  4091. #define ARIZONA_HPDET_EINT1_MASK 0x2000 /* HPDET_EINT1 */
  4092. #define ARIZONA_HPDET_EINT1_SHIFT 13 /* HPDET_EINT1 */
  4093. #define ARIZONA_HPDET_EINT1_WIDTH 1 /* HPDET_EINT1 */
  4094. #define ARIZONA_MICDET_EINT1 0x1000 /* MICDET_EINT1 */
  4095. #define ARIZONA_MICDET_EINT1_MASK 0x1000 /* MICDET_EINT1 */
  4096. #define ARIZONA_MICDET_EINT1_SHIFT 12 /* MICDET_EINT1 */
  4097. #define ARIZONA_MICDET_EINT1_WIDTH 1 /* MICDET_EINT1 */
  4098. #define ARIZONA_WSEQ_DONE_EINT1 0x0800 /* WSEQ_DONE_EINT1 */
  4099. #define ARIZONA_WSEQ_DONE_EINT1_MASK 0x0800 /* WSEQ_DONE_EINT1 */
  4100. #define ARIZONA_WSEQ_DONE_EINT1_SHIFT 11 /* WSEQ_DONE_EINT1 */
  4101. #define ARIZONA_WSEQ_DONE_EINT1_WIDTH 1 /* WSEQ_DONE_EINT1 */
  4102. #define ARIZONA_DRC2_SIG_DET_EINT1 0x0400 /* DRC2_SIG_DET_EINT1 */
  4103. #define ARIZONA_DRC2_SIG_DET_EINT1_MASK 0x0400 /* DRC2_SIG_DET_EINT1 */
  4104. #define ARIZONA_DRC2_SIG_DET_EINT1_SHIFT 10 /* DRC2_SIG_DET_EINT1 */
  4105. #define ARIZONA_DRC2_SIG_DET_EINT1_WIDTH 1 /* DRC2_SIG_DET_EINT1 */
  4106. #define ARIZONA_DRC1_SIG_DET_EINT1 0x0200 /* DRC1_SIG_DET_EINT1 */
  4107. #define ARIZONA_DRC1_SIG_DET_EINT1_MASK 0x0200 /* DRC1_SIG_DET_EINT1 */
  4108. #define ARIZONA_DRC1_SIG_DET_EINT1_SHIFT 9 /* DRC1_SIG_DET_EINT1 */
  4109. #define ARIZONA_DRC1_SIG_DET_EINT1_WIDTH 1 /* DRC1_SIG_DET_EINT1 */
  4110. #define ARIZONA_ASRC2_LOCK_EINT1 0x0100 /* ASRC2_LOCK_EINT1 */
  4111. #define ARIZONA_ASRC2_LOCK_EINT1_MASK 0x0100 /* ASRC2_LOCK_EINT1 */
  4112. #define ARIZONA_ASRC2_LOCK_EINT1_SHIFT 8 /* ASRC2_LOCK_EINT1 */
  4113. #define ARIZONA_ASRC2_LOCK_EINT1_WIDTH 1 /* ASRC2_LOCK_EINT1 */
  4114. #define ARIZONA_ASRC1_LOCK_EINT1 0x0080 /* ASRC1_LOCK_EINT1 */
  4115. #define ARIZONA_ASRC1_LOCK_EINT1_MASK 0x0080 /* ASRC1_LOCK_EINT1 */
  4116. #define ARIZONA_ASRC1_LOCK_EINT1_SHIFT 7 /* ASRC1_LOCK_EINT1 */
  4117. #define ARIZONA_ASRC1_LOCK_EINT1_WIDTH 1 /* ASRC1_LOCK_EINT1 */
  4118. #define ARIZONA_UNDERCLOCKED_EINT1 0x0040 /* UNDERCLOCKED_EINT1 */
  4119. #define ARIZONA_UNDERCLOCKED_EINT1_MASK 0x0040 /* UNDERCLOCKED_EINT1 */
  4120. #define ARIZONA_UNDERCLOCKED_EINT1_SHIFT 6 /* UNDERCLOCKED_EINT1 */
  4121. #define ARIZONA_UNDERCLOCKED_EINT1_WIDTH 1 /* UNDERCLOCKED_EINT1 */
  4122. #define ARIZONA_OVERCLOCKED_EINT1 0x0020 /* OVERCLOCKED_EINT1 */
  4123. #define ARIZONA_OVERCLOCKED_EINT1_MASK 0x0020 /* OVERCLOCKED_EINT1 */
  4124. #define ARIZONA_OVERCLOCKED_EINT1_SHIFT 5 /* OVERCLOCKED_EINT1 */
  4125. #define ARIZONA_OVERCLOCKED_EINT1_WIDTH 1 /* OVERCLOCKED_EINT1 */
  4126. #define ARIZONA_FLL2_LOCK_EINT1 0x0008 /* FLL2_LOCK_EINT1 */
  4127. #define ARIZONA_FLL2_LOCK_EINT1_MASK 0x0008 /* FLL2_LOCK_EINT1 */
  4128. #define ARIZONA_FLL2_LOCK_EINT1_SHIFT 3 /* FLL2_LOCK_EINT1 */
  4129. #define ARIZONA_FLL2_LOCK_EINT1_WIDTH 1 /* FLL2_LOCK_EINT1 */
  4130. #define ARIZONA_FLL1_LOCK_EINT1 0x0004 /* FLL1_LOCK_EINT1 */
  4131. #define ARIZONA_FLL1_LOCK_EINT1_MASK 0x0004 /* FLL1_LOCK_EINT1 */
  4132. #define ARIZONA_FLL1_LOCK_EINT1_SHIFT 2 /* FLL1_LOCK_EINT1 */
  4133. #define ARIZONA_FLL1_LOCK_EINT1_WIDTH 1 /* FLL1_LOCK_EINT1 */
  4134. #define ARIZONA_CLKGEN_ERR_EINT1 0x0002 /* CLKGEN_ERR_EINT1 */
  4135. #define ARIZONA_CLKGEN_ERR_EINT1_MASK 0x0002 /* CLKGEN_ERR_EINT1 */
  4136. #define ARIZONA_CLKGEN_ERR_EINT1_SHIFT 1 /* CLKGEN_ERR_EINT1 */
  4137. #define ARIZONA_CLKGEN_ERR_EINT1_WIDTH 1 /* CLKGEN_ERR_EINT1 */
  4138. #define ARIZONA_CLKGEN_ERR_ASYNC_EINT1 0x0001 /* CLKGEN_ERR_ASYNC_EINT1 */
  4139. #define ARIZONA_CLKGEN_ERR_ASYNC_EINT1_MASK 0x0001 /* CLKGEN_ERR_ASYNC_EINT1 */
  4140. #define ARIZONA_CLKGEN_ERR_ASYNC_EINT1_SHIFT 0 /* CLKGEN_ERR_ASYNC_EINT1 */
  4141. #define ARIZONA_CLKGEN_ERR_ASYNC_EINT1_WIDTH 1 /* CLKGEN_ERR_ASYNC_EINT1 */
  4142. /*
  4143. * R3331 (0xD03) - Interrupt Status 4
  4144. */
  4145. #define ARIZONA_ASRC_CFG_ERR_EINT1 0x8000 /* ASRC_CFG_ERR_EINT1 */
  4146. #define ARIZONA_ASRC_CFG_ERR_EINT1_MASK 0x8000 /* ASRC_CFG_ERR_EINT1 */
  4147. #define ARIZONA_ASRC_CFG_ERR_EINT1_SHIFT 15 /* ASRC_CFG_ERR_EINT1 */
  4148. #define ARIZONA_ASRC_CFG_ERR_EINT1_WIDTH 1 /* ASRC_CFG_ERR_EINT1 */
  4149. #define ARIZONA_AIF3_ERR_EINT1 0x4000 /* AIF3_ERR_EINT1 */
  4150. #define ARIZONA_AIF3_ERR_EINT1_MASK 0x4000 /* AIF3_ERR_EINT1 */
  4151. #define ARIZONA_AIF3_ERR_EINT1_SHIFT 14 /* AIF3_ERR_EINT1 */
  4152. #define ARIZONA_AIF3_ERR_EINT1_WIDTH 1 /* AIF3_ERR_EINT1 */
  4153. #define ARIZONA_AIF2_ERR_EINT1 0x2000 /* AIF2_ERR_EINT1 */
  4154. #define ARIZONA_AIF2_ERR_EINT1_MASK 0x2000 /* AIF2_ERR_EINT1 */
  4155. #define ARIZONA_AIF2_ERR_EINT1_SHIFT 13 /* AIF2_ERR_EINT1 */
  4156. #define ARIZONA_AIF2_ERR_EINT1_WIDTH 1 /* AIF2_ERR_EINT1 */
  4157. #define ARIZONA_AIF1_ERR_EINT1 0x1000 /* AIF1_ERR_EINT1 */
  4158. #define ARIZONA_AIF1_ERR_EINT1_MASK 0x1000 /* AIF1_ERR_EINT1 */
  4159. #define ARIZONA_AIF1_ERR_EINT1_SHIFT 12 /* AIF1_ERR_EINT1 */
  4160. #define ARIZONA_AIF1_ERR_EINT1_WIDTH 1 /* AIF1_ERR_EINT1 */
  4161. #define ARIZONA_CTRLIF_ERR_EINT1 0x0800 /* CTRLIF_ERR_EINT1 */
  4162. #define ARIZONA_CTRLIF_ERR_EINT1_MASK 0x0800 /* CTRLIF_ERR_EINT1 */
  4163. #define ARIZONA_CTRLIF_ERR_EINT1_SHIFT 11 /* CTRLIF_ERR_EINT1 */
  4164. #define ARIZONA_CTRLIF_ERR_EINT1_WIDTH 1 /* CTRLIF_ERR_EINT1 */
  4165. #define ARIZONA_MIXER_DROPPED_SAMPLE_EINT1 0x0400 /* MIXER_DROPPED_SAMPLE_EINT1 */
  4166. #define ARIZONA_MIXER_DROPPED_SAMPLE_EINT1_MASK 0x0400 /* MIXER_DROPPED_SAMPLE_EINT1 */
  4167. #define ARIZONA_MIXER_DROPPED_SAMPLE_EINT1_SHIFT 10 /* MIXER_DROPPED_SAMPLE_EINT1 */
  4168. #define ARIZONA_MIXER_DROPPED_SAMPLE_EINT1_WIDTH 1 /* MIXER_DROPPED_SAMPLE_EINT1 */
  4169. #define ARIZONA_ASYNC_CLK_ENA_LOW_EINT1 0x0200 /* ASYNC_CLK_ENA_LOW_EINT1 */
  4170. #define ARIZONA_ASYNC_CLK_ENA_LOW_EINT1_MASK 0x0200 /* ASYNC_CLK_ENA_LOW_EINT1 */
  4171. #define ARIZONA_ASYNC_CLK_ENA_LOW_EINT1_SHIFT 9 /* ASYNC_CLK_ENA_LOW_EINT1 */
  4172. #define ARIZONA_ASYNC_CLK_ENA_LOW_EINT1_WIDTH 1 /* ASYNC_CLK_ENA_LOW_EINT1 */
  4173. #define ARIZONA_SYSCLK_ENA_LOW_EINT1 0x0100 /* SYSCLK_ENA_LOW_EINT1 */
  4174. #define ARIZONA_SYSCLK_ENA_LOW_EINT1_MASK 0x0100 /* SYSCLK_ENA_LOW_EINT1 */
  4175. #define ARIZONA_SYSCLK_ENA_LOW_EINT1_SHIFT 8 /* SYSCLK_ENA_LOW_EINT1 */
  4176. #define ARIZONA_SYSCLK_ENA_LOW_EINT1_WIDTH 1 /* SYSCLK_ENA_LOW_EINT1 */
  4177. #define ARIZONA_ISRC1_CFG_ERR_EINT1 0x0080 /* ISRC1_CFG_ERR_EINT1 */
  4178. #define ARIZONA_ISRC1_CFG_ERR_EINT1_MASK 0x0080 /* ISRC1_CFG_ERR_EINT1 */
  4179. #define ARIZONA_ISRC1_CFG_ERR_EINT1_SHIFT 7 /* ISRC1_CFG_ERR_EINT1 */
  4180. #define ARIZONA_ISRC1_CFG_ERR_EINT1_WIDTH 1 /* ISRC1_CFG_ERR_EINT1 */
  4181. #define ARIZONA_ISRC2_CFG_ERR_EINT1 0x0040 /* ISRC2_CFG_ERR_EINT1 */
  4182. #define ARIZONA_ISRC2_CFG_ERR_EINT1_MASK 0x0040 /* ISRC2_CFG_ERR_EINT1 */
  4183. #define ARIZONA_ISRC2_CFG_ERR_EINT1_SHIFT 6 /* ISRC2_CFG_ERR_EINT1 */
  4184. #define ARIZONA_ISRC2_CFG_ERR_EINT1_WIDTH 1 /* ISRC2_CFG_ERR_EINT1 */
  4185. /*
  4186. * R3332 (0xD04) - Interrupt Status 5
  4187. */
  4188. #define ARIZONA_BOOT_DONE_EINT1 0x0100 /* BOOT_DONE_EINT1 */
  4189. #define ARIZONA_BOOT_DONE_EINT1_MASK 0x0100 /* BOOT_DONE_EINT1 */
  4190. #define ARIZONA_BOOT_DONE_EINT1_SHIFT 8 /* BOOT_DONE_EINT1 */
  4191. #define ARIZONA_BOOT_DONE_EINT1_WIDTH 1 /* BOOT_DONE_EINT1 */
  4192. #define ARIZONA_DCS_DAC_DONE_EINT1 0x0080 /* DCS_DAC_DONE_EINT1 */
  4193. #define ARIZONA_DCS_DAC_DONE_EINT1_MASK 0x0080 /* DCS_DAC_DONE_EINT1 */
  4194. #define ARIZONA_DCS_DAC_DONE_EINT1_SHIFT 7 /* DCS_DAC_DONE_EINT1 */
  4195. #define ARIZONA_DCS_DAC_DONE_EINT1_WIDTH 1 /* DCS_DAC_DONE_EINT1 */
  4196. #define ARIZONA_DCS_HP_DONE_EINT1 0x0040 /* DCS_HP_DONE_EINT1 */
  4197. #define ARIZONA_DCS_HP_DONE_EINT1_MASK 0x0040 /* DCS_HP_DONE_EINT1 */
  4198. #define ARIZONA_DCS_HP_DONE_EINT1_SHIFT 6 /* DCS_HP_DONE_EINT1 */
  4199. #define ARIZONA_DCS_HP_DONE_EINT1_WIDTH 1 /* DCS_HP_DONE_EINT1 */
  4200. #define ARIZONA_FLL2_CLOCK_OK_EINT1 0x0002 /* FLL2_CLOCK_OK_EINT1 */
  4201. #define ARIZONA_FLL2_CLOCK_OK_EINT1_MASK 0x0002 /* FLL2_CLOCK_OK_EINT1 */
  4202. #define ARIZONA_FLL2_CLOCK_OK_EINT1_SHIFT 1 /* FLL2_CLOCK_OK_EINT1 */
  4203. #define ARIZONA_FLL2_CLOCK_OK_EINT1_WIDTH 1 /* FLL2_CLOCK_OK_EINT1 */
  4204. #define ARIZONA_FLL1_CLOCK_OK_EINT1 0x0001 /* FLL1_CLOCK_OK_EINT1 */
  4205. #define ARIZONA_FLL1_CLOCK_OK_EINT1_MASK 0x0001 /* FLL1_CLOCK_OK_EINT1 */
  4206. #define ARIZONA_FLL1_CLOCK_OK_EINT1_SHIFT 0 /* FLL1_CLOCK_OK_EINT1 */
  4207. #define ARIZONA_FLL1_CLOCK_OK_EINT1_WIDTH 1 /* FLL1_CLOCK_OK_EINT1 */
  4208. /*
  4209. * R3336 (0xD08) - Interrupt Status 1 Mask
  4210. */
  4211. #define ARIZONA_IM_GP4_EINT1 0x0008 /* IM_GP4_EINT1 */
  4212. #define ARIZONA_IM_GP4_EINT1_MASK 0x0008 /* IM_GP4_EINT1 */
  4213. #define ARIZONA_IM_GP4_EINT1_SHIFT 3 /* IM_GP4_EINT1 */
  4214. #define ARIZONA_IM_GP4_EINT1_WIDTH 1 /* IM_GP4_EINT1 */
  4215. #define ARIZONA_IM_GP3_EINT1 0x0004 /* IM_GP3_EINT1 */
  4216. #define ARIZONA_IM_GP3_EINT1_MASK 0x0004 /* IM_GP3_EINT1 */
  4217. #define ARIZONA_IM_GP3_EINT1_SHIFT 2 /* IM_GP3_EINT1 */
  4218. #define ARIZONA_IM_GP3_EINT1_WIDTH 1 /* IM_GP3_EINT1 */
  4219. #define ARIZONA_IM_GP2_EINT1 0x0002 /* IM_GP2_EINT1 */
  4220. #define ARIZONA_IM_GP2_EINT1_MASK 0x0002 /* IM_GP2_EINT1 */
  4221. #define ARIZONA_IM_GP2_EINT1_SHIFT 1 /* IM_GP2_EINT1 */
  4222. #define ARIZONA_IM_GP2_EINT1_WIDTH 1 /* IM_GP2_EINT1 */
  4223. #define ARIZONA_IM_GP1_EINT1 0x0001 /* IM_GP1_EINT1 */
  4224. #define ARIZONA_IM_GP1_EINT1_MASK 0x0001 /* IM_GP1_EINT1 */
  4225. #define ARIZONA_IM_GP1_EINT1_SHIFT 0 /* IM_GP1_EINT1 */
  4226. #define ARIZONA_IM_GP1_EINT1_WIDTH 1 /* IM_GP1_EINT1 */
  4227. /*
  4228. * R3337 (0xD09) - Interrupt Status 2 Mask
  4229. */
  4230. #define ARIZONA_IM_DSP1_RAM_RDY_EINT1 0x0100 /* IM_DSP1_RAM_RDY_EINT1 */
  4231. #define ARIZONA_IM_DSP1_RAM_RDY_EINT1_MASK 0x0100 /* IM_DSP1_RAM_RDY_EINT1 */
  4232. #define ARIZONA_IM_DSP1_RAM_RDY_EINT1_SHIFT 8 /* IM_DSP1_RAM_RDY_EINT1 */
  4233. #define ARIZONA_IM_DSP1_RAM_RDY_EINT1_WIDTH 1 /* IM_DSP1_RAM_RDY_EINT1 */
  4234. #define ARIZONA_IM_DSP_IRQ2_EINT1 0x0002 /* IM_DSP_IRQ2_EINT1 */
  4235. #define ARIZONA_IM_DSP_IRQ2_EINT1_MASK 0x0002 /* IM_DSP_IRQ2_EINT1 */
  4236. #define ARIZONA_IM_DSP_IRQ2_EINT1_SHIFT 1 /* IM_DSP_IRQ2_EINT1 */
  4237. #define ARIZONA_IM_DSP_IRQ2_EINT1_WIDTH 1 /* IM_DSP_IRQ2_EINT1 */
  4238. #define ARIZONA_IM_DSP_IRQ1_EINT1 0x0001 /* IM_DSP_IRQ1_EINT1 */
  4239. #define ARIZONA_IM_DSP_IRQ1_EINT1_MASK 0x0001 /* IM_DSP_IRQ1_EINT1 */
  4240. #define ARIZONA_IM_DSP_IRQ1_EINT1_SHIFT 0 /* IM_DSP_IRQ1_EINT1 */
  4241. #define ARIZONA_IM_DSP_IRQ1_EINT1_WIDTH 1 /* IM_DSP_IRQ1_EINT1 */
  4242. /*
  4243. * R3338 (0xD0A) - Interrupt Status 3 Mask
  4244. */
  4245. #define ARIZONA_IM_SPK_SHUTDOWN_WARN_EINT1 0x8000 /* IM_SPK_SHUTDOWN_WARN_EINT1 */
  4246. #define ARIZONA_IM_SPK_SHUTDOWN_WARN_EINT1_MASK 0x8000 /* IM_SPK_SHUTDOWN_WARN_EINT1 */
  4247. #define ARIZONA_IM_SPK_SHUTDOWN_WARN_EINT1_SHIFT 15 /* IM_SPK_SHUTDOWN_WARN_EINT1 */
  4248. #define ARIZONA_IM_SPK_SHUTDOWN_WARN_EINT1_WIDTH 1 /* IM_SPK_SHUTDOWN_WARN_EINT1 */
  4249. #define ARIZONA_IM_SPK_SHUTDOWN_EINT1 0x4000 /* IM_SPK_SHUTDOWN_EINT1 */
  4250. #define ARIZONA_IM_SPK_SHUTDOWN_EINT1_MASK 0x4000 /* IM_SPK_SHUTDOWN_EINT1 */
  4251. #define ARIZONA_IM_SPK_SHUTDOWN_EINT1_SHIFT 14 /* IM_SPK_SHUTDOWN_EINT1 */
  4252. #define ARIZONA_IM_SPK_SHUTDOWN_EINT1_WIDTH 1 /* IM_SPK_SHUTDOWN_EINT1 */
  4253. #define ARIZONA_IM_HPDET_EINT1 0x2000 /* IM_HPDET_EINT1 */
  4254. #define ARIZONA_IM_HPDET_EINT1_MASK 0x2000 /* IM_HPDET_EINT1 */
  4255. #define ARIZONA_IM_HPDET_EINT1_SHIFT 13 /* IM_HPDET_EINT1 */
  4256. #define ARIZONA_IM_HPDET_EINT1_WIDTH 1 /* IM_HPDET_EINT1 */
  4257. #define ARIZONA_IM_MICDET_EINT1 0x1000 /* IM_MICDET_EINT1 */
  4258. #define ARIZONA_IM_MICDET_EINT1_MASK 0x1000 /* IM_MICDET_EINT1 */
  4259. #define ARIZONA_IM_MICDET_EINT1_SHIFT 12 /* IM_MICDET_EINT1 */
  4260. #define ARIZONA_IM_MICDET_EINT1_WIDTH 1 /* IM_MICDET_EINT1 */
  4261. #define ARIZONA_IM_WSEQ_DONE_EINT1 0x0800 /* IM_WSEQ_DONE_EINT1 */
  4262. #define ARIZONA_IM_WSEQ_DONE_EINT1_MASK 0x0800 /* IM_WSEQ_DONE_EINT1 */
  4263. #define ARIZONA_IM_WSEQ_DONE_EINT1_SHIFT 11 /* IM_WSEQ_DONE_EINT1 */
  4264. #define ARIZONA_IM_WSEQ_DONE_EINT1_WIDTH 1 /* IM_WSEQ_DONE_EINT1 */
  4265. #define ARIZONA_IM_DRC2_SIG_DET_EINT1 0x0400 /* IM_DRC2_SIG_DET_EINT1 */
  4266. #define ARIZONA_IM_DRC2_SIG_DET_EINT1_MASK 0x0400 /* IM_DRC2_SIG_DET_EINT1 */
  4267. #define ARIZONA_IM_DRC2_SIG_DET_EINT1_SHIFT 10 /* IM_DRC2_SIG_DET_EINT1 */
  4268. #define ARIZONA_IM_DRC2_SIG_DET_EINT1_WIDTH 1 /* IM_DRC2_SIG_DET_EINT1 */
  4269. #define ARIZONA_IM_DRC1_SIG_DET_EINT1 0x0200 /* IM_DRC1_SIG_DET_EINT1 */
  4270. #define ARIZONA_IM_DRC1_SIG_DET_EINT1_MASK 0x0200 /* IM_DRC1_SIG_DET_EINT1 */
  4271. #define ARIZONA_IM_DRC1_SIG_DET_EINT1_SHIFT 9 /* IM_DRC1_SIG_DET_EINT1 */
  4272. #define ARIZONA_IM_DRC1_SIG_DET_EINT1_WIDTH 1 /* IM_DRC1_SIG_DET_EINT1 */
  4273. #define ARIZONA_IM_ASRC2_LOCK_EINT1 0x0100 /* IM_ASRC2_LOCK_EINT1 */
  4274. #define ARIZONA_IM_ASRC2_LOCK_EINT1_MASK 0x0100 /* IM_ASRC2_LOCK_EINT1 */
  4275. #define ARIZONA_IM_ASRC2_LOCK_EINT1_SHIFT 8 /* IM_ASRC2_LOCK_EINT1 */
  4276. #define ARIZONA_IM_ASRC2_LOCK_EINT1_WIDTH 1 /* IM_ASRC2_LOCK_EINT1 */
  4277. #define ARIZONA_IM_ASRC1_LOCK_EINT1 0x0080 /* IM_ASRC1_LOCK_EINT1 */
  4278. #define ARIZONA_IM_ASRC1_LOCK_EINT1_MASK 0x0080 /* IM_ASRC1_LOCK_EINT1 */
  4279. #define ARIZONA_IM_ASRC1_LOCK_EINT1_SHIFT 7 /* IM_ASRC1_LOCK_EINT1 */
  4280. #define ARIZONA_IM_ASRC1_LOCK_EINT1_WIDTH 1 /* IM_ASRC1_LOCK_EINT1 */
  4281. #define ARIZONA_IM_UNDERCLOCKED_EINT1 0x0040 /* IM_UNDERCLOCKED_EINT1 */
  4282. #define ARIZONA_IM_UNDERCLOCKED_EINT1_MASK 0x0040 /* IM_UNDERCLOCKED_EINT1 */
  4283. #define ARIZONA_IM_UNDERCLOCKED_EINT1_SHIFT 6 /* IM_UNDERCLOCKED_EINT1 */
  4284. #define ARIZONA_IM_UNDERCLOCKED_EINT1_WIDTH 1 /* IM_UNDERCLOCKED_EINT1 */
  4285. #define ARIZONA_IM_OVERCLOCKED_EINT1 0x0020 /* IM_OVERCLOCKED_EINT1 */
  4286. #define ARIZONA_IM_OVERCLOCKED_EINT1_MASK 0x0020 /* IM_OVERCLOCKED_EINT1 */
  4287. #define ARIZONA_IM_OVERCLOCKED_EINT1_SHIFT 5 /* IM_OVERCLOCKED_EINT1 */
  4288. #define ARIZONA_IM_OVERCLOCKED_EINT1_WIDTH 1 /* IM_OVERCLOCKED_EINT1 */
  4289. #define ARIZONA_IM_FLL2_LOCK_EINT1 0x0008 /* IM_FLL2_LOCK_EINT1 */
  4290. #define ARIZONA_IM_FLL2_LOCK_EINT1_MASK 0x0008 /* IM_FLL2_LOCK_EINT1 */
  4291. #define ARIZONA_IM_FLL2_LOCK_EINT1_SHIFT 3 /* IM_FLL2_LOCK_EINT1 */
  4292. #define ARIZONA_IM_FLL2_LOCK_EINT1_WIDTH 1 /* IM_FLL2_LOCK_EINT1 */
  4293. #define ARIZONA_IM_FLL1_LOCK_EINT1 0x0004 /* IM_FLL1_LOCK_EINT1 */
  4294. #define ARIZONA_IM_FLL1_LOCK_EINT1_MASK 0x0004 /* IM_FLL1_LOCK_EINT1 */
  4295. #define ARIZONA_IM_FLL1_LOCK_EINT1_SHIFT 2 /* IM_FLL1_LOCK_EINT1 */
  4296. #define ARIZONA_IM_FLL1_LOCK_EINT1_WIDTH 1 /* IM_FLL1_LOCK_EINT1 */
  4297. #define ARIZONA_IM_CLKGEN_ERR_EINT1 0x0002 /* IM_CLKGEN_ERR_EINT1 */
  4298. #define ARIZONA_IM_CLKGEN_ERR_EINT1_MASK 0x0002 /* IM_CLKGEN_ERR_EINT1 */
  4299. #define ARIZONA_IM_CLKGEN_ERR_EINT1_SHIFT 1 /* IM_CLKGEN_ERR_EINT1 */
  4300. #define ARIZONA_IM_CLKGEN_ERR_EINT1_WIDTH 1 /* IM_CLKGEN_ERR_EINT1 */
  4301. #define ARIZONA_IM_CLKGEN_ERR_ASYNC_EINT1 0x0001 /* IM_CLKGEN_ERR_ASYNC_EINT1 */
  4302. #define ARIZONA_IM_CLKGEN_ERR_ASYNC_EINT1_MASK 0x0001 /* IM_CLKGEN_ERR_ASYNC_EINT1 */
  4303. #define ARIZONA_IM_CLKGEN_ERR_ASYNC_EINT1_SHIFT 0 /* IM_CLKGEN_ERR_ASYNC_EINT1 */
  4304. #define ARIZONA_IM_CLKGEN_ERR_ASYNC_EINT1_WIDTH 1 /* IM_CLKGEN_ERR_ASYNC_EINT1 */
  4305. /*
  4306. * R3339 (0xD0B) - Interrupt Status 4 Mask
  4307. */
  4308. #define ARIZONA_IM_ASRC_CFG_ERR_EINT1 0x8000 /* IM_ASRC_CFG_ERR_EINT1 */
  4309. #define ARIZONA_IM_ASRC_CFG_ERR_EINT1_MASK 0x8000 /* IM_ASRC_CFG_ERR_EINT1 */
  4310. #define ARIZONA_IM_ASRC_CFG_ERR_EINT1_SHIFT 15 /* IM_ASRC_CFG_ERR_EINT1 */
  4311. #define ARIZONA_IM_ASRC_CFG_ERR_EINT1_WIDTH 1 /* IM_ASRC_CFG_ERR_EINT1 */
  4312. #define ARIZONA_IM_AIF3_ERR_EINT1 0x4000 /* IM_AIF3_ERR_EINT1 */
  4313. #define ARIZONA_IM_AIF3_ERR_EINT1_MASK 0x4000 /* IM_AIF3_ERR_EINT1 */
  4314. #define ARIZONA_IM_AIF3_ERR_EINT1_SHIFT 14 /* IM_AIF3_ERR_EINT1 */
  4315. #define ARIZONA_IM_AIF3_ERR_EINT1_WIDTH 1 /* IM_AIF3_ERR_EINT1 */
  4316. #define ARIZONA_IM_AIF2_ERR_EINT1 0x2000 /* IM_AIF2_ERR_EINT1 */
  4317. #define ARIZONA_IM_AIF2_ERR_EINT1_MASK 0x2000 /* IM_AIF2_ERR_EINT1 */
  4318. #define ARIZONA_IM_AIF2_ERR_EINT1_SHIFT 13 /* IM_AIF2_ERR_EINT1 */
  4319. #define ARIZONA_IM_AIF2_ERR_EINT1_WIDTH 1 /* IM_AIF2_ERR_EINT1 */
  4320. #define ARIZONA_IM_AIF1_ERR_EINT1 0x1000 /* IM_AIF1_ERR_EINT1 */
  4321. #define ARIZONA_IM_AIF1_ERR_EINT1_MASK 0x1000 /* IM_AIF1_ERR_EINT1 */
  4322. #define ARIZONA_IM_AIF1_ERR_EINT1_SHIFT 12 /* IM_AIF1_ERR_EINT1 */
  4323. #define ARIZONA_IM_AIF1_ERR_EINT1_WIDTH 1 /* IM_AIF1_ERR_EINT1 */
  4324. #define ARIZONA_IM_CTRLIF_ERR_EINT1 0x0800 /* IM_CTRLIF_ERR_EINT1 */
  4325. #define ARIZONA_IM_CTRLIF_ERR_EINT1_MASK 0x0800 /* IM_CTRLIF_ERR_EINT1 */
  4326. #define ARIZONA_IM_CTRLIF_ERR_EINT1_SHIFT 11 /* IM_CTRLIF_ERR_EINT1 */
  4327. #define ARIZONA_IM_CTRLIF_ERR_EINT1_WIDTH 1 /* IM_CTRLIF_ERR_EINT1 */
  4328. #define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT1 0x0400 /* IM_MIXER_DROPPED_SAMPLE_EINT1 */
  4329. #define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT1_MASK 0x0400 /* IM_MIXER_DROPPED_SAMPLE_EINT1 */
  4330. #define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT1_SHIFT 10 /* IM_MIXER_DROPPED_SAMPLE_EINT1 */
  4331. #define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT1_WIDTH 1 /* IM_MIXER_DROPPED_SAMPLE_EINT1 */
  4332. #define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT1 0x0200 /* IM_ASYNC_CLK_ENA_LOW_EINT1 */
  4333. #define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT1_MASK 0x0200 /* IM_ASYNC_CLK_ENA_LOW_EINT1 */
  4334. #define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT1_SHIFT 9 /* IM_ASYNC_CLK_ENA_LOW_EINT1 */
  4335. #define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT1_WIDTH 1 /* IM_ASYNC_CLK_ENA_LOW_EINT1 */
  4336. #define ARIZONA_IM_SYSCLK_ENA_LOW_EINT1 0x0100 /* IM_SYSCLK_ENA_LOW_EINT1 */
  4337. #define ARIZONA_IM_SYSCLK_ENA_LOW_EINT1_MASK 0x0100 /* IM_SYSCLK_ENA_LOW_EINT1 */
  4338. #define ARIZONA_IM_SYSCLK_ENA_LOW_EINT1_SHIFT 8 /* IM_SYSCLK_ENA_LOW_EINT1 */
  4339. #define ARIZONA_IM_SYSCLK_ENA_LOW_EINT1_WIDTH 1 /* IM_SYSCLK_ENA_LOW_EINT1 */
  4340. #define ARIZONA_IM_ISRC1_CFG_ERR_EINT1 0x0080 /* IM_ISRC1_CFG_ERR_EINT1 */
  4341. #define ARIZONA_IM_ISRC1_CFG_ERR_EINT1_MASK 0x0080 /* IM_ISRC1_CFG_ERR_EINT1 */
  4342. #define ARIZONA_IM_ISRC1_CFG_ERR_EINT1_SHIFT 7 /* IM_ISRC1_CFG_ERR_EINT1 */
  4343. #define ARIZONA_IM_ISRC1_CFG_ERR_EINT1_WIDTH 1 /* IM_ISRC1_CFG_ERR_EINT1 */
  4344. #define ARIZONA_IM_ISRC2_CFG_ERR_EINT1 0x0040 /* IM_ISRC2_CFG_ERR_EINT1 */
  4345. #define ARIZONA_IM_ISRC2_CFG_ERR_EINT1_MASK 0x0040 /* IM_ISRC2_CFG_ERR_EINT1 */
  4346. #define ARIZONA_IM_ISRC2_CFG_ERR_EINT1_SHIFT 6 /* IM_ISRC2_CFG_ERR_EINT1 */
  4347. #define ARIZONA_IM_ISRC2_CFG_ERR_EINT1_WIDTH 1 /* IM_ISRC2_CFG_ERR_EINT1 */
  4348. /*
  4349. * R3340 (0xD0C) - Interrupt Status 5 Mask
  4350. */
  4351. #define ARIZONA_IM_BOOT_DONE_EINT1 0x0100 /* IM_BOOT_DONE_EINT1 */
  4352. #define ARIZONA_IM_BOOT_DONE_EINT1_MASK 0x0100 /* IM_BOOT_DONE_EINT1 */
  4353. #define ARIZONA_IM_BOOT_DONE_EINT1_SHIFT 8 /* IM_BOOT_DONE_EINT1 */
  4354. #define ARIZONA_IM_BOOT_DONE_EINT1_WIDTH 1 /* IM_BOOT_DONE_EINT1 */
  4355. #define ARIZONA_IM_DCS_DAC_DONE_EINT1 0x0080 /* IM_DCS_DAC_DONE_EINT1 */
  4356. #define ARIZONA_IM_DCS_DAC_DONE_EINT1_MASK 0x0080 /* IM_DCS_DAC_DONE_EINT1 */
  4357. #define ARIZONA_IM_DCS_DAC_DONE_EINT1_SHIFT 7 /* IM_DCS_DAC_DONE_EINT1 */
  4358. #define ARIZONA_IM_DCS_DAC_DONE_EINT1_WIDTH 1 /* IM_DCS_DAC_DONE_EINT1 */
  4359. #define ARIZONA_IM_DCS_HP_DONE_EINT1 0x0040 /* IM_DCS_HP_DONE_EINT1 */
  4360. #define ARIZONA_IM_DCS_HP_DONE_EINT1_MASK 0x0040 /* IM_DCS_HP_DONE_EINT1 */
  4361. #define ARIZONA_IM_DCS_HP_DONE_EINT1_SHIFT 6 /* IM_DCS_HP_DONE_EINT1 */
  4362. #define ARIZONA_IM_DCS_HP_DONE_EINT1_WIDTH 1 /* IM_DCS_HP_DONE_EINT1 */
  4363. #define ARIZONA_IM_FLL2_CLOCK_OK_EINT1 0x0002 /* IM_FLL2_CLOCK_OK_EINT1 */
  4364. #define ARIZONA_IM_FLL2_CLOCK_OK_EINT1_MASK 0x0002 /* IM_FLL2_CLOCK_OK_EINT1 */
  4365. #define ARIZONA_IM_FLL2_CLOCK_OK_EINT1_SHIFT 1 /* IM_FLL2_CLOCK_OK_EINT1 */
  4366. #define ARIZONA_IM_FLL2_CLOCK_OK_EINT1_WIDTH 1 /* IM_FLL2_CLOCK_OK_EINT1 */
  4367. #define ARIZONA_IM_FLL1_CLOCK_OK_EINT1 0x0001 /* IM_FLL1_CLOCK_OK_EINT1 */
  4368. #define ARIZONA_IM_FLL1_CLOCK_OK_EINT1_MASK 0x0001 /* IM_FLL1_CLOCK_OK_EINT1 */
  4369. #define ARIZONA_IM_FLL1_CLOCK_OK_EINT1_SHIFT 0 /* IM_FLL1_CLOCK_OK_EINT1 */
  4370. #define ARIZONA_IM_FLL1_CLOCK_OK_EINT1_WIDTH 1 /* IM_FLL1_CLOCK_OK_EINT1 */
  4371. /*
  4372. * R3343 (0xD0F) - Interrupt Control
  4373. */
  4374. #define ARIZONA_IM_IRQ1 0x0001 /* IM_IRQ1 */
  4375. #define ARIZONA_IM_IRQ1_MASK 0x0001 /* IM_IRQ1 */
  4376. #define ARIZONA_IM_IRQ1_SHIFT 0 /* IM_IRQ1 */
  4377. #define ARIZONA_IM_IRQ1_WIDTH 1 /* IM_IRQ1 */
  4378. /*
  4379. * R3344 (0xD10) - IRQ2 Status 1
  4380. */
  4381. #define ARIZONA_GP4_EINT2 0x0008 /* GP4_EINT2 */
  4382. #define ARIZONA_GP4_EINT2_MASK 0x0008 /* GP4_EINT2 */
  4383. #define ARIZONA_GP4_EINT2_SHIFT 3 /* GP4_EINT2 */
  4384. #define ARIZONA_GP4_EINT2_WIDTH 1 /* GP4_EINT2 */
  4385. #define ARIZONA_GP3_EINT2 0x0004 /* GP3_EINT2 */
  4386. #define ARIZONA_GP3_EINT2_MASK 0x0004 /* GP3_EINT2 */
  4387. #define ARIZONA_GP3_EINT2_SHIFT 2 /* GP3_EINT2 */
  4388. #define ARIZONA_GP3_EINT2_WIDTH 1 /* GP3_EINT2 */
  4389. #define ARIZONA_GP2_EINT2 0x0002 /* GP2_EINT2 */
  4390. #define ARIZONA_GP2_EINT2_MASK 0x0002 /* GP2_EINT2 */
  4391. #define ARIZONA_GP2_EINT2_SHIFT 1 /* GP2_EINT2 */
  4392. #define ARIZONA_GP2_EINT2_WIDTH 1 /* GP2_EINT2 */
  4393. #define ARIZONA_GP1_EINT2 0x0001 /* GP1_EINT2 */
  4394. #define ARIZONA_GP1_EINT2_MASK 0x0001 /* GP1_EINT2 */
  4395. #define ARIZONA_GP1_EINT2_SHIFT 0 /* GP1_EINT2 */
  4396. #define ARIZONA_GP1_EINT2_WIDTH 1 /* GP1_EINT2 */
  4397. /*
  4398. * R3345 (0xD11) - IRQ2 Status 2
  4399. */
  4400. #define ARIZONA_DSP1_RAM_RDY_EINT2 0x0100 /* DSP1_RAM_RDY_EINT2 */
  4401. #define ARIZONA_DSP1_RAM_RDY_EINT2_MASK 0x0100 /* DSP1_RAM_RDY_EINT2 */
  4402. #define ARIZONA_DSP1_RAM_RDY_EINT2_SHIFT 8 /* DSP1_RAM_RDY_EINT2 */
  4403. #define ARIZONA_DSP1_RAM_RDY_EINT2_WIDTH 1 /* DSP1_RAM_RDY_EINT2 */
  4404. #define ARIZONA_DSP_IRQ2_EINT2 0x0002 /* DSP_IRQ2_EINT2 */
  4405. #define ARIZONA_DSP_IRQ2_EINT2_MASK 0x0002 /* DSP_IRQ2_EINT2 */
  4406. #define ARIZONA_DSP_IRQ2_EINT2_SHIFT 1 /* DSP_IRQ2_EINT2 */
  4407. #define ARIZONA_DSP_IRQ2_EINT2_WIDTH 1 /* DSP_IRQ2_EINT2 */
  4408. #define ARIZONA_DSP_IRQ1_EINT2 0x0001 /* DSP_IRQ1_EINT2 */
  4409. #define ARIZONA_DSP_IRQ1_EINT2_MASK 0x0001 /* DSP_IRQ1_EINT2 */
  4410. #define ARIZONA_DSP_IRQ1_EINT2_SHIFT 0 /* DSP_IRQ1_EINT2 */
  4411. #define ARIZONA_DSP_IRQ1_EINT2_WIDTH 1 /* DSP_IRQ1_EINT2 */
  4412. /*
  4413. * R3346 (0xD12) - IRQ2 Status 3
  4414. */
  4415. #define ARIZONA_SPK_SHUTDOWN_WARN_EINT2 0x8000 /* SPK_SHUTDOWN_WARN_EINT2 */
  4416. #define ARIZONA_SPK_SHUTDOWN_WARN_EINT2_MASK 0x8000 /* SPK_SHUTDOWN_WARN_EINT2 */
  4417. #define ARIZONA_SPK_SHUTDOWN_WARN_EINT2_SHIFT 15 /* SPK_SHUTDOWN_WARN_EINT2 */
  4418. #define ARIZONA_SPK_SHUTDOWN_WARN_EINT2_WIDTH 1 /* SPK_SHUTDOWN_WARN_EINT2 */
  4419. #define ARIZONA_SPK_SHUTDOWN_EINT2 0x4000 /* SPK_SHUTDOWN_EINT2 */
  4420. #define ARIZONA_SPK_SHUTDOWN_EINT2_MASK 0x4000 /* SPK_SHUTDOWN_EINT2 */
  4421. #define ARIZONA_SPK_SHUTDOWN_EINT2_SHIFT 14 /* SPK_SHUTDOWN_EINT2 */
  4422. #define ARIZONA_SPK_SHUTDOWN_EINT2_WIDTH 1 /* SPK_SHUTDOWN_EINT2 */
  4423. #define ARIZONA_HPDET_EINT2 0x2000 /* HPDET_EINT2 */
  4424. #define ARIZONA_HPDET_EINT2_MASK 0x2000 /* HPDET_EINT2 */
  4425. #define ARIZONA_HPDET_EINT2_SHIFT 13 /* HPDET_EINT2 */
  4426. #define ARIZONA_HPDET_EINT2_WIDTH 1 /* HPDET_EINT2 */
  4427. #define ARIZONA_MICDET_EINT2 0x1000 /* MICDET_EINT2 */
  4428. #define ARIZONA_MICDET_EINT2_MASK 0x1000 /* MICDET_EINT2 */
  4429. #define ARIZONA_MICDET_EINT2_SHIFT 12 /* MICDET_EINT2 */
  4430. #define ARIZONA_MICDET_EINT2_WIDTH 1 /* MICDET_EINT2 */
  4431. #define ARIZONA_WSEQ_DONE_EINT2 0x0800 /* WSEQ_DONE_EINT2 */
  4432. #define ARIZONA_WSEQ_DONE_EINT2_MASK 0x0800 /* WSEQ_DONE_EINT2 */
  4433. #define ARIZONA_WSEQ_DONE_EINT2_SHIFT 11 /* WSEQ_DONE_EINT2 */
  4434. #define ARIZONA_WSEQ_DONE_EINT2_WIDTH 1 /* WSEQ_DONE_EINT2 */
  4435. #define ARIZONA_DRC2_SIG_DET_EINT2 0x0400 /* DRC2_SIG_DET_EINT2 */
  4436. #define ARIZONA_DRC2_SIG_DET_EINT2_MASK 0x0400 /* DRC2_SIG_DET_EINT2 */
  4437. #define ARIZONA_DRC2_SIG_DET_EINT2_SHIFT 10 /* DRC2_SIG_DET_EINT2 */
  4438. #define ARIZONA_DRC2_SIG_DET_EINT2_WIDTH 1 /* DRC2_SIG_DET_EINT2 */
  4439. #define ARIZONA_DRC1_SIG_DET_EINT2 0x0200 /* DRC1_SIG_DET_EINT2 */
  4440. #define ARIZONA_DRC1_SIG_DET_EINT2_MASK 0x0200 /* DRC1_SIG_DET_EINT2 */
  4441. #define ARIZONA_DRC1_SIG_DET_EINT2_SHIFT 9 /* DRC1_SIG_DET_EINT2 */
  4442. #define ARIZONA_DRC1_SIG_DET_EINT2_WIDTH 1 /* DRC1_SIG_DET_EINT2 */
  4443. #define ARIZONA_ASRC2_LOCK_EINT2 0x0100 /* ASRC2_LOCK_EINT2 */
  4444. #define ARIZONA_ASRC2_LOCK_EINT2_MASK 0x0100 /* ASRC2_LOCK_EINT2 */
  4445. #define ARIZONA_ASRC2_LOCK_EINT2_SHIFT 8 /* ASRC2_LOCK_EINT2 */
  4446. #define ARIZONA_ASRC2_LOCK_EINT2_WIDTH 1 /* ASRC2_LOCK_EINT2 */
  4447. #define ARIZONA_ASRC1_LOCK_EINT2 0x0080 /* ASRC1_LOCK_EINT2 */
  4448. #define ARIZONA_ASRC1_LOCK_EINT2_MASK 0x0080 /* ASRC1_LOCK_EINT2 */
  4449. #define ARIZONA_ASRC1_LOCK_EINT2_SHIFT 7 /* ASRC1_LOCK_EINT2 */
  4450. #define ARIZONA_ASRC1_LOCK_EINT2_WIDTH 1 /* ASRC1_LOCK_EINT2 */
  4451. #define ARIZONA_UNDERCLOCKED_EINT2 0x0040 /* UNDERCLOCKED_EINT2 */
  4452. #define ARIZONA_UNDERCLOCKED_EINT2_MASK 0x0040 /* UNDERCLOCKED_EINT2 */
  4453. #define ARIZONA_UNDERCLOCKED_EINT2_SHIFT 6 /* UNDERCLOCKED_EINT2 */
  4454. #define ARIZONA_UNDERCLOCKED_EINT2_WIDTH 1 /* UNDERCLOCKED_EINT2 */
  4455. #define ARIZONA_OVERCLOCKED_EINT2 0x0020 /* OVERCLOCKED_EINT2 */
  4456. #define ARIZONA_OVERCLOCKED_EINT2_MASK 0x0020 /* OVERCLOCKED_EINT2 */
  4457. #define ARIZONA_OVERCLOCKED_EINT2_SHIFT 5 /* OVERCLOCKED_EINT2 */
  4458. #define ARIZONA_OVERCLOCKED_EINT2_WIDTH 1 /* OVERCLOCKED_EINT2 */
  4459. #define ARIZONA_FLL2_LOCK_EINT2 0x0008 /* FLL2_LOCK_EINT2 */
  4460. #define ARIZONA_FLL2_LOCK_EINT2_MASK 0x0008 /* FLL2_LOCK_EINT2 */
  4461. #define ARIZONA_FLL2_LOCK_EINT2_SHIFT 3 /* FLL2_LOCK_EINT2 */
  4462. #define ARIZONA_FLL2_LOCK_EINT2_WIDTH 1 /* FLL2_LOCK_EINT2 */
  4463. #define ARIZONA_FLL1_LOCK_EINT2 0x0004 /* FLL1_LOCK_EINT2 */
  4464. #define ARIZONA_FLL1_LOCK_EINT2_MASK 0x0004 /* FLL1_LOCK_EINT2 */
  4465. #define ARIZONA_FLL1_LOCK_EINT2_SHIFT 2 /* FLL1_LOCK_EINT2 */
  4466. #define ARIZONA_FLL1_LOCK_EINT2_WIDTH 1 /* FLL1_LOCK_EINT2 */
  4467. #define ARIZONA_CLKGEN_ERR_EINT2 0x0002 /* CLKGEN_ERR_EINT2 */
  4468. #define ARIZONA_CLKGEN_ERR_EINT2_MASK 0x0002 /* CLKGEN_ERR_EINT2 */
  4469. #define ARIZONA_CLKGEN_ERR_EINT2_SHIFT 1 /* CLKGEN_ERR_EINT2 */
  4470. #define ARIZONA_CLKGEN_ERR_EINT2_WIDTH 1 /* CLKGEN_ERR_EINT2 */
  4471. #define ARIZONA_CLKGEN_ERR_ASYNC_EINT2 0x0001 /* CLKGEN_ERR_ASYNC_EINT2 */
  4472. #define ARIZONA_CLKGEN_ERR_ASYNC_EINT2_MASK 0x0001 /* CLKGEN_ERR_ASYNC_EINT2 */
  4473. #define ARIZONA_CLKGEN_ERR_ASYNC_EINT2_SHIFT 0 /* CLKGEN_ERR_ASYNC_EINT2 */
  4474. #define ARIZONA_CLKGEN_ERR_ASYNC_EINT2_WIDTH 1 /* CLKGEN_ERR_ASYNC_EINT2 */
  4475. /*
  4476. * R3347 (0xD13) - IRQ2 Status 4
  4477. */
  4478. #define ARIZONA_ASRC_CFG_ERR_EINT2 0x8000 /* ASRC_CFG_ERR_EINT2 */
  4479. #define ARIZONA_ASRC_CFG_ERR_EINT2_MASK 0x8000 /* ASRC_CFG_ERR_EINT2 */
  4480. #define ARIZONA_ASRC_CFG_ERR_EINT2_SHIFT 15 /* ASRC_CFG_ERR_EINT2 */
  4481. #define ARIZONA_ASRC_CFG_ERR_EINT2_WIDTH 1 /* ASRC_CFG_ERR_EINT2 */
  4482. #define ARIZONA_AIF3_ERR_EINT2 0x4000 /* AIF3_ERR_EINT2 */
  4483. #define ARIZONA_AIF3_ERR_EINT2_MASK 0x4000 /* AIF3_ERR_EINT2 */
  4484. #define ARIZONA_AIF3_ERR_EINT2_SHIFT 14 /* AIF3_ERR_EINT2 */
  4485. #define ARIZONA_AIF3_ERR_EINT2_WIDTH 1 /* AIF3_ERR_EINT2 */
  4486. #define ARIZONA_AIF2_ERR_EINT2 0x2000 /* AIF2_ERR_EINT2 */
  4487. #define ARIZONA_AIF2_ERR_EINT2_MASK 0x2000 /* AIF2_ERR_EINT2 */
  4488. #define ARIZONA_AIF2_ERR_EINT2_SHIFT 13 /* AIF2_ERR_EINT2 */
  4489. #define ARIZONA_AIF2_ERR_EINT2_WIDTH 1 /* AIF2_ERR_EINT2 */
  4490. #define ARIZONA_AIF1_ERR_EINT2 0x1000 /* AIF1_ERR_EINT2 */
  4491. #define ARIZONA_AIF1_ERR_EINT2_MASK 0x1000 /* AIF1_ERR_EINT2 */
  4492. #define ARIZONA_AIF1_ERR_EINT2_SHIFT 12 /* AIF1_ERR_EINT2 */
  4493. #define ARIZONA_AIF1_ERR_EINT2_WIDTH 1 /* AIF1_ERR_EINT2 */
  4494. #define ARIZONA_CTRLIF_ERR_EINT2 0x0800 /* CTRLIF_ERR_EINT2 */
  4495. #define ARIZONA_CTRLIF_ERR_EINT2_MASK 0x0800 /* CTRLIF_ERR_EINT2 */
  4496. #define ARIZONA_CTRLIF_ERR_EINT2_SHIFT 11 /* CTRLIF_ERR_EINT2 */
  4497. #define ARIZONA_CTRLIF_ERR_EINT2_WIDTH 1 /* CTRLIF_ERR_EINT2 */
  4498. #define ARIZONA_MIXER_DROPPED_SAMPLE_EINT2 0x0400 /* MIXER_DROPPED_SAMPLE_EINT2 */
  4499. #define ARIZONA_MIXER_DROPPED_SAMPLE_EINT2_MASK 0x0400 /* MIXER_DROPPED_SAMPLE_EINT2 */
  4500. #define ARIZONA_MIXER_DROPPED_SAMPLE_EINT2_SHIFT 10 /* MIXER_DROPPED_SAMPLE_EINT2 */
  4501. #define ARIZONA_MIXER_DROPPED_SAMPLE_EINT2_WIDTH 1 /* MIXER_DROPPED_SAMPLE_EINT2 */
  4502. #define ARIZONA_ASYNC_CLK_ENA_LOW_EINT2 0x0200 /* ASYNC_CLK_ENA_LOW_EINT2 */
  4503. #define ARIZONA_ASYNC_CLK_ENA_LOW_EINT2_MASK 0x0200 /* ASYNC_CLK_ENA_LOW_EINT2 */
  4504. #define ARIZONA_ASYNC_CLK_ENA_LOW_EINT2_SHIFT 9 /* ASYNC_CLK_ENA_LOW_EINT2 */
  4505. #define ARIZONA_ASYNC_CLK_ENA_LOW_EINT2_WIDTH 1 /* ASYNC_CLK_ENA_LOW_EINT2 */
  4506. #define ARIZONA_SYSCLK_ENA_LOW_EINT2 0x0100 /* SYSCLK_ENA_LOW_EINT2 */
  4507. #define ARIZONA_SYSCLK_ENA_LOW_EINT2_MASK 0x0100 /* SYSCLK_ENA_LOW_EINT2 */
  4508. #define ARIZONA_SYSCLK_ENA_LOW_EINT2_SHIFT 8 /* SYSCLK_ENA_LOW_EINT2 */
  4509. #define ARIZONA_SYSCLK_ENA_LOW_EINT2_WIDTH 1 /* SYSCLK_ENA_LOW_EINT2 */
  4510. #define ARIZONA_ISRC1_CFG_ERR_EINT2 0x0080 /* ISRC1_CFG_ERR_EINT2 */
  4511. #define ARIZONA_ISRC1_CFG_ERR_EINT2_MASK 0x0080 /* ISRC1_CFG_ERR_EINT2 */
  4512. #define ARIZONA_ISRC1_CFG_ERR_EINT2_SHIFT 7 /* ISRC1_CFG_ERR_EINT2 */
  4513. #define ARIZONA_ISRC1_CFG_ERR_EINT2_WIDTH 1 /* ISRC1_CFG_ERR_EINT2 */
  4514. #define ARIZONA_ISRC2_CFG_ERR_EINT2 0x0040 /* ISRC2_CFG_ERR_EINT2 */
  4515. #define ARIZONA_ISRC2_CFG_ERR_EINT2_MASK 0x0040 /* ISRC2_CFG_ERR_EINT2 */
  4516. #define ARIZONA_ISRC2_CFG_ERR_EINT2_SHIFT 6 /* ISRC2_CFG_ERR_EINT2 */
  4517. #define ARIZONA_ISRC2_CFG_ERR_EINT2_WIDTH 1 /* ISRC2_CFG_ERR_EINT2 */
  4518. /*
  4519. * R3348 (0xD14) - IRQ2 Status 5
  4520. */
  4521. #define ARIZONA_BOOT_DONE_EINT2 0x0100 /* BOOT_DONE_EINT2 */
  4522. #define ARIZONA_BOOT_DONE_EINT2_MASK 0x0100 /* BOOT_DONE_EINT2 */
  4523. #define ARIZONA_BOOT_DONE_EINT2_SHIFT 8 /* BOOT_DONE_EINT2 */
  4524. #define ARIZONA_BOOT_DONE_EINT2_WIDTH 1 /* BOOT_DONE_EINT2 */
  4525. #define ARIZONA_DCS_DAC_DONE_EINT2 0x0080 /* DCS_DAC_DONE_EINT2 */
  4526. #define ARIZONA_DCS_DAC_DONE_EINT2_MASK 0x0080 /* DCS_DAC_DONE_EINT2 */
  4527. #define ARIZONA_DCS_DAC_DONE_EINT2_SHIFT 7 /* DCS_DAC_DONE_EINT2 */
  4528. #define ARIZONA_DCS_DAC_DONE_EINT2_WIDTH 1 /* DCS_DAC_DONE_EINT2 */
  4529. #define ARIZONA_DCS_HP_DONE_EINT2 0x0040 /* DCS_HP_DONE_EINT2 */
  4530. #define ARIZONA_DCS_HP_DONE_EINT2_MASK 0x0040 /* DCS_HP_DONE_EINT2 */
  4531. #define ARIZONA_DCS_HP_DONE_EINT2_SHIFT 6 /* DCS_HP_DONE_EINT2 */
  4532. #define ARIZONA_DCS_HP_DONE_EINT2_WIDTH 1 /* DCS_HP_DONE_EINT2 */
  4533. #define ARIZONA_FLL2_CLOCK_OK_EINT2 0x0002 /* FLL2_CLOCK_OK_EINT2 */
  4534. #define ARIZONA_FLL2_CLOCK_OK_EINT2_MASK 0x0002 /* FLL2_CLOCK_OK_EINT2 */
  4535. #define ARIZONA_FLL2_CLOCK_OK_EINT2_SHIFT 1 /* FLL2_CLOCK_OK_EINT2 */
  4536. #define ARIZONA_FLL2_CLOCK_OK_EINT2_WIDTH 1 /* FLL2_CLOCK_OK_EINT2 */
  4537. #define ARIZONA_FLL1_CLOCK_OK_EINT2 0x0001 /* FLL1_CLOCK_OK_EINT2 */
  4538. #define ARIZONA_FLL1_CLOCK_OK_EINT2_MASK 0x0001 /* FLL1_CLOCK_OK_EINT2 */
  4539. #define ARIZONA_FLL1_CLOCK_OK_EINT2_SHIFT 0 /* FLL1_CLOCK_OK_EINT2 */
  4540. #define ARIZONA_FLL1_CLOCK_OK_EINT2_WIDTH 1 /* FLL1_CLOCK_OK_EINT2 */
  4541. /*
  4542. * R3352 (0xD18) - IRQ2 Status 1 Mask
  4543. */
  4544. #define ARIZONA_IM_GP4_EINT2 0x0008 /* IM_GP4_EINT2 */
  4545. #define ARIZONA_IM_GP4_EINT2_MASK 0x0008 /* IM_GP4_EINT2 */
  4546. #define ARIZONA_IM_GP4_EINT2_SHIFT 3 /* IM_GP4_EINT2 */
  4547. #define ARIZONA_IM_GP4_EINT2_WIDTH 1 /* IM_GP4_EINT2 */
  4548. #define ARIZONA_IM_GP3_EINT2 0x0004 /* IM_GP3_EINT2 */
  4549. #define ARIZONA_IM_GP3_EINT2_MASK 0x0004 /* IM_GP3_EINT2 */
  4550. #define ARIZONA_IM_GP3_EINT2_SHIFT 2 /* IM_GP3_EINT2 */
  4551. #define ARIZONA_IM_GP3_EINT2_WIDTH 1 /* IM_GP3_EINT2 */
  4552. #define ARIZONA_IM_GP2_EINT2 0x0002 /* IM_GP2_EINT2 */
  4553. #define ARIZONA_IM_GP2_EINT2_MASK 0x0002 /* IM_GP2_EINT2 */
  4554. #define ARIZONA_IM_GP2_EINT2_SHIFT 1 /* IM_GP2_EINT2 */
  4555. #define ARIZONA_IM_GP2_EINT2_WIDTH 1 /* IM_GP2_EINT2 */
  4556. #define ARIZONA_IM_GP1_EINT2 0x0001 /* IM_GP1_EINT2 */
  4557. #define ARIZONA_IM_GP1_EINT2_MASK 0x0001 /* IM_GP1_EINT2 */
  4558. #define ARIZONA_IM_GP1_EINT2_SHIFT 0 /* IM_GP1_EINT2 */
  4559. #define ARIZONA_IM_GP1_EINT2_WIDTH 1 /* IM_GP1_EINT2 */
  4560. /*
  4561. * R3353 (0xD19) - IRQ2 Status 2 Mask
  4562. */
  4563. #define ARIZONA_IM_DSP1_RAM_RDY_EINT2 0x0100 /* IM_DSP1_RAM_RDY_EINT2 */
  4564. #define ARIZONA_IM_DSP1_RAM_RDY_EINT2_MASK 0x0100 /* IM_DSP1_RAM_RDY_EINT2 */
  4565. #define ARIZONA_IM_DSP1_RAM_RDY_EINT2_SHIFT 8 /* IM_DSP1_RAM_RDY_EINT2 */
  4566. #define ARIZONA_IM_DSP1_RAM_RDY_EINT2_WIDTH 1 /* IM_DSP1_RAM_RDY_EINT2 */
  4567. #define ARIZONA_IM_DSP_IRQ2_EINT2 0x0002 /* IM_DSP_IRQ2_EINT2 */
  4568. #define ARIZONA_IM_DSP_IRQ2_EINT2_MASK 0x0002 /* IM_DSP_IRQ2_EINT2 */
  4569. #define ARIZONA_IM_DSP_IRQ2_EINT2_SHIFT 1 /* IM_DSP_IRQ2_EINT2 */
  4570. #define ARIZONA_IM_DSP_IRQ2_EINT2_WIDTH 1 /* IM_DSP_IRQ2_EINT2 */
  4571. #define ARIZONA_IM_DSP_IRQ1_EINT2 0x0001 /* IM_DSP_IRQ1_EINT2 */
  4572. #define ARIZONA_IM_DSP_IRQ1_EINT2_MASK 0x0001 /* IM_DSP_IRQ1_EINT2 */
  4573. #define ARIZONA_IM_DSP_IRQ1_EINT2_SHIFT 0 /* IM_DSP_IRQ1_EINT2 */
  4574. #define ARIZONA_IM_DSP_IRQ1_EINT2_WIDTH 1 /* IM_DSP_IRQ1_EINT2 */
  4575. /*
  4576. * R3354 (0xD1A) - IRQ2 Status 3 Mask
  4577. */
  4578. #define ARIZONA_IM_SPK_SHUTDOWN_WARN_EINT2 0x8000 /* IM_SPK_SHUTDOWN_WARN_EINT2 */
  4579. #define ARIZONA_IM_SPK_SHUTDOWN_WARN_EINT2_MASK 0x8000 /* IM_SPK_SHUTDOWN_WARN_EINT2 */
  4580. #define ARIZONA_IM_SPK_SHUTDOWN_WARN_EINT2_SHIFT 15 /* IM_SPK_SHUTDOWN_WARN_EINT2 */
  4581. #define ARIZONA_IM_SPK_SHUTDOWN_WARN_EINT2_WIDTH 1 /* IM_SPK_SHUTDOWN_WARN_EINT2 */
  4582. #define ARIZONA_IM_SPK_SHUTDOWN_EINT2 0x4000 /* IM_SPK_SHUTDOWN_EINT2 */
  4583. #define ARIZONA_IM_SPK_SHUTDOWN_EINT2_MASK 0x4000 /* IM_SPK_SHUTDOWN_EINT2 */
  4584. #define ARIZONA_IM_SPK_SHUTDOWN_EINT2_SHIFT 14 /* IM_SPK_SHUTDOWN_EINT2 */
  4585. #define ARIZONA_IM_SPK_SHUTDOWN_EINT2_WIDTH 1 /* IM_SPK_SHUTDOWN_EINT2 */
  4586. #define ARIZONA_IM_HPDET_EINT2 0x2000 /* IM_HPDET_EINT2 */
  4587. #define ARIZONA_IM_HPDET_EINT2_MASK 0x2000 /* IM_HPDET_EINT2 */
  4588. #define ARIZONA_IM_HPDET_EINT2_SHIFT 13 /* IM_HPDET_EINT2 */
  4589. #define ARIZONA_IM_HPDET_EINT2_WIDTH 1 /* IM_HPDET_EINT2 */
  4590. #define ARIZONA_IM_MICDET_EINT2 0x1000 /* IM_MICDET_EINT2 */
  4591. #define ARIZONA_IM_MICDET_EINT2_MASK 0x1000 /* IM_MICDET_EINT2 */
  4592. #define ARIZONA_IM_MICDET_EINT2_SHIFT 12 /* IM_MICDET_EINT2 */
  4593. #define ARIZONA_IM_MICDET_EINT2_WIDTH 1 /* IM_MICDET_EINT2 */
  4594. #define ARIZONA_IM_WSEQ_DONE_EINT2 0x0800 /* IM_WSEQ_DONE_EINT2 */
  4595. #define ARIZONA_IM_WSEQ_DONE_EINT2_MASK 0x0800 /* IM_WSEQ_DONE_EINT2 */
  4596. #define ARIZONA_IM_WSEQ_DONE_EINT2_SHIFT 11 /* IM_WSEQ_DONE_EINT2 */
  4597. #define ARIZONA_IM_WSEQ_DONE_EINT2_WIDTH 1 /* IM_WSEQ_DONE_EINT2 */
  4598. #define ARIZONA_IM_DRC2_SIG_DET_EINT2 0x0400 /* IM_DRC2_SIG_DET_EINT2 */
  4599. #define ARIZONA_IM_DRC2_SIG_DET_EINT2_MASK 0x0400 /* IM_DRC2_SIG_DET_EINT2 */
  4600. #define ARIZONA_IM_DRC2_SIG_DET_EINT2_SHIFT 10 /* IM_DRC2_SIG_DET_EINT2 */
  4601. #define ARIZONA_IM_DRC2_SIG_DET_EINT2_WIDTH 1 /* IM_DRC2_SIG_DET_EINT2 */
  4602. #define ARIZONA_IM_DRC1_SIG_DET_EINT2 0x0200 /* IM_DRC1_SIG_DET_EINT2 */
  4603. #define ARIZONA_IM_DRC1_SIG_DET_EINT2_MASK 0x0200 /* IM_DRC1_SIG_DET_EINT2 */
  4604. #define ARIZONA_IM_DRC1_SIG_DET_EINT2_SHIFT 9 /* IM_DRC1_SIG_DET_EINT2 */
  4605. #define ARIZONA_IM_DRC1_SIG_DET_EINT2_WIDTH 1 /* IM_DRC1_SIG_DET_EINT2 */
  4606. #define ARIZONA_IM_ASRC2_LOCK_EINT2 0x0100 /* IM_ASRC2_LOCK_EINT2 */
  4607. #define ARIZONA_IM_ASRC2_LOCK_EINT2_MASK 0x0100 /* IM_ASRC2_LOCK_EINT2 */
  4608. #define ARIZONA_IM_ASRC2_LOCK_EINT2_SHIFT 8 /* IM_ASRC2_LOCK_EINT2 */
  4609. #define ARIZONA_IM_ASRC2_LOCK_EINT2_WIDTH 1 /* IM_ASRC2_LOCK_EINT2 */
  4610. #define ARIZONA_IM_ASRC1_LOCK_EINT2 0x0080 /* IM_ASRC1_LOCK_EINT2 */
  4611. #define ARIZONA_IM_ASRC1_LOCK_EINT2_MASK 0x0080 /* IM_ASRC1_LOCK_EINT2 */
  4612. #define ARIZONA_IM_ASRC1_LOCK_EINT2_SHIFT 7 /* IM_ASRC1_LOCK_EINT2 */
  4613. #define ARIZONA_IM_ASRC1_LOCK_EINT2_WIDTH 1 /* IM_ASRC1_LOCK_EINT2 */
  4614. #define ARIZONA_IM_UNDERCLOCKED_EINT2 0x0040 /* IM_UNDERCLOCKED_EINT2 */
  4615. #define ARIZONA_IM_UNDERCLOCKED_EINT2_MASK 0x0040 /* IM_UNDERCLOCKED_EINT2 */
  4616. #define ARIZONA_IM_UNDERCLOCKED_EINT2_SHIFT 6 /* IM_UNDERCLOCKED_EINT2 */
  4617. #define ARIZONA_IM_UNDERCLOCKED_EINT2_WIDTH 1 /* IM_UNDERCLOCKED_EINT2 */
  4618. #define ARIZONA_IM_OVERCLOCKED_EINT2 0x0020 /* IM_OVERCLOCKED_EINT2 */
  4619. #define ARIZONA_IM_OVERCLOCKED_EINT2_MASK 0x0020 /* IM_OVERCLOCKED_EINT2 */
  4620. #define ARIZONA_IM_OVERCLOCKED_EINT2_SHIFT 5 /* IM_OVERCLOCKED_EINT2 */
  4621. #define ARIZONA_IM_OVERCLOCKED_EINT2_WIDTH 1 /* IM_OVERCLOCKED_EINT2 */
  4622. #define ARIZONA_IM_FLL2_LOCK_EINT2 0x0008 /* IM_FLL2_LOCK_EINT2 */
  4623. #define ARIZONA_IM_FLL2_LOCK_EINT2_MASK 0x0008 /* IM_FLL2_LOCK_EINT2 */
  4624. #define ARIZONA_IM_FLL2_LOCK_EINT2_SHIFT 3 /* IM_FLL2_LOCK_EINT2 */
  4625. #define ARIZONA_IM_FLL2_LOCK_EINT2_WIDTH 1 /* IM_FLL2_LOCK_EINT2 */
  4626. #define ARIZONA_IM_FLL1_LOCK_EINT2 0x0004 /* IM_FLL1_LOCK_EINT2 */
  4627. #define ARIZONA_IM_FLL1_LOCK_EINT2_MASK 0x0004 /* IM_FLL1_LOCK_EINT2 */
  4628. #define ARIZONA_IM_FLL1_LOCK_EINT2_SHIFT 2 /* IM_FLL1_LOCK_EINT2 */
  4629. #define ARIZONA_IM_FLL1_LOCK_EINT2_WIDTH 1 /* IM_FLL1_LOCK_EINT2 */
  4630. #define ARIZONA_IM_CLKGEN_ERR_EINT2 0x0002 /* IM_CLKGEN_ERR_EINT2 */
  4631. #define ARIZONA_IM_CLKGEN_ERR_EINT2_MASK 0x0002 /* IM_CLKGEN_ERR_EINT2 */
  4632. #define ARIZONA_IM_CLKGEN_ERR_EINT2_SHIFT 1 /* IM_CLKGEN_ERR_EINT2 */
  4633. #define ARIZONA_IM_CLKGEN_ERR_EINT2_WIDTH 1 /* IM_CLKGEN_ERR_EINT2 */
  4634. #define ARIZONA_IM_CLKGEN_ERR_ASYNC_EINT2 0x0001 /* IM_CLKGEN_ERR_ASYNC_EINT2 */
  4635. #define ARIZONA_IM_CLKGEN_ERR_ASYNC_EINT2_MASK 0x0001 /* IM_CLKGEN_ERR_ASYNC_EINT2 */
  4636. #define ARIZONA_IM_CLKGEN_ERR_ASYNC_EINT2_SHIFT 0 /* IM_CLKGEN_ERR_ASYNC_EINT2 */
  4637. #define ARIZONA_IM_CLKGEN_ERR_ASYNC_EINT2_WIDTH 1 /* IM_CLKGEN_ERR_ASYNC_EINT2 */
  4638. /*
  4639. * R3355 (0xD1B) - IRQ2 Status 4 Mask
  4640. */
  4641. #define ARIZONA_IM_ASRC_CFG_ERR_EINT2 0x8000 /* IM_ASRC_CFG_ERR_EINT2 */
  4642. #define ARIZONA_IM_ASRC_CFG_ERR_EINT2_MASK 0x8000 /* IM_ASRC_CFG_ERR_EINT2 */
  4643. #define ARIZONA_IM_ASRC_CFG_ERR_EINT2_SHIFT 15 /* IM_ASRC_CFG_ERR_EINT2 */
  4644. #define ARIZONA_IM_ASRC_CFG_ERR_EINT2_WIDTH 1 /* IM_ASRC_CFG_ERR_EINT2 */
  4645. #define ARIZONA_IM_AIF3_ERR_EINT2 0x4000 /* IM_AIF3_ERR_EINT2 */
  4646. #define ARIZONA_IM_AIF3_ERR_EINT2_MASK 0x4000 /* IM_AIF3_ERR_EINT2 */
  4647. #define ARIZONA_IM_AIF3_ERR_EINT2_SHIFT 14 /* IM_AIF3_ERR_EINT2 */
  4648. #define ARIZONA_IM_AIF3_ERR_EINT2_WIDTH 1 /* IM_AIF3_ERR_EINT2 */
  4649. #define ARIZONA_IM_AIF2_ERR_EINT2 0x2000 /* IM_AIF2_ERR_EINT2 */
  4650. #define ARIZONA_IM_AIF2_ERR_EINT2_MASK 0x2000 /* IM_AIF2_ERR_EINT2 */
  4651. #define ARIZONA_IM_AIF2_ERR_EINT2_SHIFT 13 /* IM_AIF2_ERR_EINT2 */
  4652. #define ARIZONA_IM_AIF2_ERR_EINT2_WIDTH 1 /* IM_AIF2_ERR_EINT2 */
  4653. #define ARIZONA_IM_AIF1_ERR_EINT2 0x1000 /* IM_AIF1_ERR_EINT2 */
  4654. #define ARIZONA_IM_AIF1_ERR_EINT2_MASK 0x1000 /* IM_AIF1_ERR_EINT2 */
  4655. #define ARIZONA_IM_AIF1_ERR_EINT2_SHIFT 12 /* IM_AIF1_ERR_EINT2 */
  4656. #define ARIZONA_IM_AIF1_ERR_EINT2_WIDTH 1 /* IM_AIF1_ERR_EINT2 */
  4657. #define ARIZONA_IM_CTRLIF_ERR_EINT2 0x0800 /* IM_CTRLIF_ERR_EINT2 */
  4658. #define ARIZONA_IM_CTRLIF_ERR_EINT2_MASK 0x0800 /* IM_CTRLIF_ERR_EINT2 */
  4659. #define ARIZONA_IM_CTRLIF_ERR_EINT2_SHIFT 11 /* IM_CTRLIF_ERR_EINT2 */
  4660. #define ARIZONA_IM_CTRLIF_ERR_EINT2_WIDTH 1 /* IM_CTRLIF_ERR_EINT2 */
  4661. #define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT2 0x0400 /* IM_MIXER_DROPPED_SAMPLE_EINT2 */
  4662. #define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT2_MASK 0x0400 /* IM_MIXER_DROPPED_SAMPLE_EINT2 */
  4663. #define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT2_SHIFT 10 /* IM_MIXER_DROPPED_SAMPLE_EINT2 */
  4664. #define ARIZONA_IM_MIXER_DROPPED_SAMPLE_EINT2_WIDTH 1 /* IM_MIXER_DROPPED_SAMPLE_EINT2 */
  4665. #define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT2 0x0200 /* IM_ASYNC_CLK_ENA_LOW_EINT2 */
  4666. #define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT2_MASK 0x0200 /* IM_ASYNC_CLK_ENA_LOW_EINT2 */
  4667. #define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT2_SHIFT 9 /* IM_ASYNC_CLK_ENA_LOW_EINT2 */
  4668. #define ARIZONA_IM_ASYNC_CLK_ENA_LOW_EINT2_WIDTH 1 /* IM_ASYNC_CLK_ENA_LOW_EINT2 */
  4669. #define ARIZONA_IM_SYSCLK_ENA_LOW_EINT2 0x0100 /* IM_SYSCLK_ENA_LOW_EINT2 */
  4670. #define ARIZONA_IM_SYSCLK_ENA_LOW_EINT2_MASK 0x0100 /* IM_SYSCLK_ENA_LOW_EINT2 */
  4671. #define ARIZONA_IM_SYSCLK_ENA_LOW_EINT2_SHIFT 8 /* IM_SYSCLK_ENA_LOW_EINT2 */
  4672. #define ARIZONA_IM_SYSCLK_ENA_LOW_EINT2_WIDTH 1 /* IM_SYSCLK_ENA_LOW_EINT2 */
  4673. #define ARIZONA_IM_ISRC1_CFG_ERR_EINT2 0x0080 /* IM_ISRC1_CFG_ERR_EINT2 */
  4674. #define ARIZONA_IM_ISRC1_CFG_ERR_EINT2_MASK 0x0080 /* IM_ISRC1_CFG_ERR_EINT2 */
  4675. #define ARIZONA_IM_ISRC1_CFG_ERR_EINT2_SHIFT 7 /* IM_ISRC1_CFG_ERR_EINT2 */
  4676. #define ARIZONA_IM_ISRC1_CFG_ERR_EINT2_WIDTH 1 /* IM_ISRC1_CFG_ERR_EINT2 */
  4677. #define ARIZONA_IM_ISRC2_CFG_ERR_EINT2 0x0040 /* IM_ISRC2_CFG_ERR_EINT2 */
  4678. #define ARIZONA_IM_ISRC2_CFG_ERR_EINT2_MASK 0x0040 /* IM_ISRC2_CFG_ERR_EINT2 */
  4679. #define ARIZONA_IM_ISRC2_CFG_ERR_EINT2_SHIFT 6 /* IM_ISRC2_CFG_ERR_EINT2 */
  4680. #define ARIZONA_IM_ISRC2_CFG_ERR_EINT2_WIDTH 1 /* IM_ISRC2_CFG_ERR_EINT2 */
  4681. /*
  4682. * R3356 (0xD1C) - IRQ2 Status 5 Mask
  4683. */
  4684. #define ARIZONA_IM_BOOT_DONE_EINT2 0x0100 /* IM_BOOT_DONE_EINT2 */
  4685. #define ARIZONA_IM_BOOT_DONE_EINT2_MASK 0x0100 /* IM_BOOT_DONE_EINT2 */
  4686. #define ARIZONA_IM_BOOT_DONE_EINT2_SHIFT 8 /* IM_BOOT_DONE_EINT2 */
  4687. #define ARIZONA_IM_BOOT_DONE_EINT2_WIDTH 1 /* IM_BOOT_DONE_EINT2 */
  4688. #define ARIZONA_IM_DCS_DAC_DONE_EINT2 0x0080 /* IM_DCS_DAC_DONE_EINT2 */
  4689. #define ARIZONA_IM_DCS_DAC_DONE_EINT2_MASK 0x0080 /* IM_DCS_DAC_DONE_EINT2 */
  4690. #define ARIZONA_IM_DCS_DAC_DONE_EINT2_SHIFT 7 /* IM_DCS_DAC_DONE_EINT2 */
  4691. #define ARIZONA_IM_DCS_DAC_DONE_EINT2_WIDTH 1 /* IM_DCS_DAC_DONE_EINT2 */
  4692. #define ARIZONA_IM_DCS_HP_DONE_EINT2 0x0040 /* IM_DCS_HP_DONE_EINT2 */
  4693. #define ARIZONA_IM_DCS_HP_DONE_EINT2_MASK 0x0040 /* IM_DCS_HP_DONE_EINT2 */
  4694. #define ARIZONA_IM_DCS_HP_DONE_EINT2_SHIFT 6 /* IM_DCS_HP_DONE_EINT2 */
  4695. #define ARIZONA_IM_DCS_HP_DONE_EINT2_WIDTH 1 /* IM_DCS_HP_DONE_EINT2 */
  4696. #define ARIZONA_IM_FLL2_CLOCK_OK_EINT2 0x0002 /* IM_FLL2_CLOCK_OK_EINT2 */
  4697. #define ARIZONA_IM_FLL2_CLOCK_OK_EINT2_MASK 0x0002 /* IM_FLL2_CLOCK_OK_EINT2 */
  4698. #define ARIZONA_IM_FLL2_CLOCK_OK_EINT2_SHIFT 1 /* IM_FLL2_CLOCK_OK_EINT2 */
  4699. #define ARIZONA_IM_FLL2_CLOCK_OK_EINT2_WIDTH 1 /* IM_FLL2_CLOCK_OK_EINT2 */
  4700. #define ARIZONA_IM_FLL1_CLOCK_OK_EINT2 0x0001 /* IM_FLL1_CLOCK_OK_EINT2 */
  4701. #define ARIZONA_IM_FLL1_CLOCK_OK_EINT2_MASK 0x0001 /* IM_FLL1_CLOCK_OK_EINT2 */
  4702. #define ARIZONA_IM_FLL1_CLOCK_OK_EINT2_SHIFT 0 /* IM_FLL1_CLOCK_OK_EINT2 */
  4703. #define ARIZONA_IM_FLL1_CLOCK_OK_EINT2_WIDTH 1 /* IM_FLL1_CLOCK_OK_EINT2 */
  4704. /*
  4705. * R3359 (0xD1F) - IRQ2 Control
  4706. */
  4707. #define ARIZONA_IM_IRQ2 0x0001 /* IM_IRQ2 */
  4708. #define ARIZONA_IM_IRQ2_MASK 0x0001 /* IM_IRQ2 */
  4709. #define ARIZONA_IM_IRQ2_SHIFT 0 /* IM_IRQ2 */
  4710. #define ARIZONA_IM_IRQ2_WIDTH 1 /* IM_IRQ2 */
  4711. /*
  4712. * R3360 (0xD20) - Interrupt Raw Status 2
  4713. */
  4714. #define ARIZONA_DSP1_RAM_RDY_STS 0x0100 /* DSP1_RAM_RDY_STS */
  4715. #define ARIZONA_DSP1_RAM_RDY_STS_MASK 0x0100 /* DSP1_RAM_RDY_STS */
  4716. #define ARIZONA_DSP1_RAM_RDY_STS_SHIFT 8 /* DSP1_RAM_RDY_STS */
  4717. #define ARIZONA_DSP1_RAM_RDY_STS_WIDTH 1 /* DSP1_RAM_RDY_STS */
  4718. #define ARIZONA_DSP_IRQ2_STS 0x0002 /* DSP_IRQ2_STS */
  4719. #define ARIZONA_DSP_IRQ2_STS_MASK 0x0002 /* DSP_IRQ2_STS */
  4720. #define ARIZONA_DSP_IRQ2_STS_SHIFT 1 /* DSP_IRQ2_STS */
  4721. #define ARIZONA_DSP_IRQ2_STS_WIDTH 1 /* DSP_IRQ2_STS */
  4722. #define ARIZONA_DSP_IRQ1_STS 0x0001 /* DSP_IRQ1_STS */
  4723. #define ARIZONA_DSP_IRQ1_STS_MASK 0x0001 /* DSP_IRQ1_STS */
  4724. #define ARIZONA_DSP_IRQ1_STS_SHIFT 0 /* DSP_IRQ1_STS */
  4725. #define ARIZONA_DSP_IRQ1_STS_WIDTH 1 /* DSP_IRQ1_STS */
  4726. /*
  4727. * R3361 (0xD21) - Interrupt Raw Status 3
  4728. */
  4729. #define ARIZONA_SPK_SHUTDOWN_WARN_STS 0x8000 /* SPK_SHUTDOWN_WARN_STS */
  4730. #define ARIZONA_SPK_SHUTDOWN_WARN_STS_MASK 0x8000 /* SPK_SHUTDOWN_WARN_STS */
  4731. #define ARIZONA_SPK_SHUTDOWN_WARN_STS_SHIFT 15 /* SPK_SHUTDOWN_WARN_STS */
  4732. #define ARIZONA_SPK_SHUTDOWN_WARN_STS_WIDTH 1 /* SPK_SHUTDOWN_WARN_STS */
  4733. #define ARIZONA_SPK_SHUTDOWN_STS 0x4000 /* SPK_SHUTDOWN_STS */
  4734. #define ARIZONA_SPK_SHUTDOWN_STS_MASK 0x4000 /* SPK_SHUTDOWN_STS */
  4735. #define ARIZONA_SPK_SHUTDOWN_STS_SHIFT 14 /* SPK_SHUTDOWN_STS */
  4736. #define ARIZONA_SPK_SHUTDOWN_STS_WIDTH 1 /* SPK_SHUTDOWN_STS */
  4737. #define ARIZONA_HPDET_STS 0x2000 /* HPDET_STS */
  4738. #define ARIZONA_HPDET_STS_MASK 0x2000 /* HPDET_STS */
  4739. #define ARIZONA_HPDET_STS_SHIFT 13 /* HPDET_STS */
  4740. #define ARIZONA_HPDET_STS_WIDTH 1 /* HPDET_STS */
  4741. #define ARIZONA_MICDET_STS 0x1000 /* MICDET_STS */
  4742. #define ARIZONA_MICDET_STS_MASK 0x1000 /* MICDET_STS */
  4743. #define ARIZONA_MICDET_STS_SHIFT 12 /* MICDET_STS */
  4744. #define ARIZONA_MICDET_STS_WIDTH 1 /* MICDET_STS */
  4745. #define ARIZONA_WSEQ_DONE_STS 0x0800 /* WSEQ_DONE_STS */
  4746. #define ARIZONA_WSEQ_DONE_STS_MASK 0x0800 /* WSEQ_DONE_STS */
  4747. #define ARIZONA_WSEQ_DONE_STS_SHIFT 11 /* WSEQ_DONE_STS */
  4748. #define ARIZONA_WSEQ_DONE_STS_WIDTH 1 /* WSEQ_DONE_STS */
  4749. #define ARIZONA_DRC2_SIG_DET_STS 0x0400 /* DRC2_SIG_DET_STS */
  4750. #define ARIZONA_DRC2_SIG_DET_STS_MASK 0x0400 /* DRC2_SIG_DET_STS */
  4751. #define ARIZONA_DRC2_SIG_DET_STS_SHIFT 10 /* DRC2_SIG_DET_STS */
  4752. #define ARIZONA_DRC2_SIG_DET_STS_WIDTH 1 /* DRC2_SIG_DET_STS */
  4753. #define ARIZONA_DRC1_SIG_DET_STS 0x0200 /* DRC1_SIG_DET_STS */
  4754. #define ARIZONA_DRC1_SIG_DET_STS_MASK 0x0200 /* DRC1_SIG_DET_STS */
  4755. #define ARIZONA_DRC1_SIG_DET_STS_SHIFT 9 /* DRC1_SIG_DET_STS */
  4756. #define ARIZONA_DRC1_SIG_DET_STS_WIDTH 1 /* DRC1_SIG_DET_STS */
  4757. #define ARIZONA_ASRC2_LOCK_STS 0x0100 /* ASRC2_LOCK_STS */
  4758. #define ARIZONA_ASRC2_LOCK_STS_MASK 0x0100 /* ASRC2_LOCK_STS */
  4759. #define ARIZONA_ASRC2_LOCK_STS_SHIFT 8 /* ASRC2_LOCK_STS */
  4760. #define ARIZONA_ASRC2_LOCK_STS_WIDTH 1 /* ASRC2_LOCK_STS */
  4761. #define ARIZONA_ASRC1_LOCK_STS 0x0080 /* ASRC1_LOCK_STS */
  4762. #define ARIZONA_ASRC1_LOCK_STS_MASK 0x0080 /* ASRC1_LOCK_STS */
  4763. #define ARIZONA_ASRC1_LOCK_STS_SHIFT 7 /* ASRC1_LOCK_STS */
  4764. #define ARIZONA_ASRC1_LOCK_STS_WIDTH 1 /* ASRC1_LOCK_STS */
  4765. #define ARIZONA_UNDERCLOCKED_STS 0x0040 /* UNDERCLOCKED_STS */
  4766. #define ARIZONA_UNDERCLOCKED_STS_MASK 0x0040 /* UNDERCLOCKED_STS */
  4767. #define ARIZONA_UNDERCLOCKED_STS_SHIFT 6 /* UNDERCLOCKED_STS */
  4768. #define ARIZONA_UNDERCLOCKED_STS_WIDTH 1 /* UNDERCLOCKED_STS */
  4769. #define ARIZONA_OVERCLOCKED_STS 0x0020 /* OVERCLOCKED_STS */
  4770. #define ARIZONA_OVERCLOCKED_STS_MASK 0x0020 /* OVERCLOCKED_STS */
  4771. #define ARIZONA_OVERCLOCKED_STS_SHIFT 5 /* OVERCLOCKED_STS */
  4772. #define ARIZONA_OVERCLOCKED_STS_WIDTH 1 /* OVERCLOCKED_STS */
  4773. #define ARIZONA_FLL2_LOCK_STS 0x0008 /* FLL2_LOCK_STS */
  4774. #define ARIZONA_FLL2_LOCK_STS_MASK 0x0008 /* FLL2_LOCK_STS */
  4775. #define ARIZONA_FLL2_LOCK_STS_SHIFT 3 /* FLL2_LOCK_STS */
  4776. #define ARIZONA_FLL2_LOCK_STS_WIDTH 1 /* FLL2_LOCK_STS */
  4777. #define ARIZONA_FLL1_LOCK_STS 0x0004 /* FLL1_LOCK_STS */
  4778. #define ARIZONA_FLL1_LOCK_STS_MASK 0x0004 /* FLL1_LOCK_STS */
  4779. #define ARIZONA_FLL1_LOCK_STS_SHIFT 2 /* FLL1_LOCK_STS */
  4780. #define ARIZONA_FLL1_LOCK_STS_WIDTH 1 /* FLL1_LOCK_STS */
  4781. #define ARIZONA_CLKGEN_ERR_STS 0x0002 /* CLKGEN_ERR_STS */
  4782. #define ARIZONA_CLKGEN_ERR_STS_MASK 0x0002 /* CLKGEN_ERR_STS */
  4783. #define ARIZONA_CLKGEN_ERR_STS_SHIFT 1 /* CLKGEN_ERR_STS */
  4784. #define ARIZONA_CLKGEN_ERR_STS_WIDTH 1 /* CLKGEN_ERR_STS */
  4785. #define ARIZONA_CLKGEN_ERR_ASYNC_STS 0x0001 /* CLKGEN_ERR_ASYNC_STS */
  4786. #define ARIZONA_CLKGEN_ERR_ASYNC_STS_MASK 0x0001 /* CLKGEN_ERR_ASYNC_STS */
  4787. #define ARIZONA_CLKGEN_ERR_ASYNC_STS_SHIFT 0 /* CLKGEN_ERR_ASYNC_STS */
  4788. #define ARIZONA_CLKGEN_ERR_ASYNC_STS_WIDTH 1 /* CLKGEN_ERR_ASYNC_STS */
  4789. /*
  4790. * R3362 (0xD22) - Interrupt Raw Status 4
  4791. */
  4792. #define ARIZONA_ASRC_CFG_ERR_STS 0x8000 /* ASRC_CFG_ERR_STS */
  4793. #define ARIZONA_ASRC_CFG_ERR_STS_MASK 0x8000 /* ASRC_CFG_ERR_STS */
  4794. #define ARIZONA_ASRC_CFG_ERR_STS_SHIFT 15 /* ASRC_CFG_ERR_STS */
  4795. #define ARIZONA_ASRC_CFG_ERR_STS_WIDTH 1 /* ASRC_CFG_ERR_STS */
  4796. #define ARIZONA_AIF3_ERR_STS 0x4000 /* AIF3_ERR_STS */
  4797. #define ARIZONA_AIF3_ERR_STS_MASK 0x4000 /* AIF3_ERR_STS */
  4798. #define ARIZONA_AIF3_ERR_STS_SHIFT 14 /* AIF3_ERR_STS */
  4799. #define ARIZONA_AIF3_ERR_STS_WIDTH 1 /* AIF3_ERR_STS */
  4800. #define ARIZONA_AIF2_ERR_STS 0x2000 /* AIF2_ERR_STS */
  4801. #define ARIZONA_AIF2_ERR_STS_MASK 0x2000 /* AIF2_ERR_STS */
  4802. #define ARIZONA_AIF2_ERR_STS_SHIFT 13 /* AIF2_ERR_STS */
  4803. #define ARIZONA_AIF2_ERR_STS_WIDTH 1 /* AIF2_ERR_STS */
  4804. #define ARIZONA_AIF1_ERR_STS 0x1000 /* AIF1_ERR_STS */
  4805. #define ARIZONA_AIF1_ERR_STS_MASK 0x1000 /* AIF1_ERR_STS */
  4806. #define ARIZONA_AIF1_ERR_STS_SHIFT 12 /* AIF1_ERR_STS */
  4807. #define ARIZONA_AIF1_ERR_STS_WIDTH 1 /* AIF1_ERR_STS */
  4808. #define ARIZONA_CTRLIF_ERR_STS 0x0800 /* CTRLIF_ERR_STS */
  4809. #define ARIZONA_CTRLIF_ERR_STS_MASK 0x0800 /* CTRLIF_ERR_STS */
  4810. #define ARIZONA_CTRLIF_ERR_STS_SHIFT 11 /* CTRLIF_ERR_STS */
  4811. #define ARIZONA_CTRLIF_ERR_STS_WIDTH 1 /* CTRLIF_ERR_STS */
  4812. #define ARIZONA_MIXER_DROPPED_SAMPLE_STS 0x0400 /* MIXER_DROPPED_SAMPLE_STS */
  4813. #define ARIZONA_MIXER_DROPPED_SAMPLE_STS_MASK 0x0400 /* MIXER_DROPPED_SAMPLE_STS */
  4814. #define ARIZONA_MIXER_DROPPED_SAMPLE_STS_SHIFT 10 /* MIXER_DROPPED_SAMPLE_STS */
  4815. #define ARIZONA_MIXER_DROPPED_SAMPLE_STS_WIDTH 1 /* MIXER_DROPPED_SAMPLE_STS */
  4816. #define ARIZONA_ASYNC_CLK_ENA_LOW_STS 0x0200 /* ASYNC_CLK_ENA_LOW_STS */
  4817. #define ARIZONA_ASYNC_CLK_ENA_LOW_STS_MASK 0x0200 /* ASYNC_CLK_ENA_LOW_STS */
  4818. #define ARIZONA_ASYNC_CLK_ENA_LOW_STS_SHIFT 9 /* ASYNC_CLK_ENA_LOW_STS */
  4819. #define ARIZONA_ASYNC_CLK_ENA_LOW_STS_WIDTH 1 /* ASYNC_CLK_ENA_LOW_STS */
  4820. #define ARIZONA_SYSCLK_ENA_LOW_STS 0x0100 /* SYSCLK_ENA_LOW_STS */
  4821. #define ARIZONA_SYSCLK_ENA_LOW_STS_MASK 0x0100 /* SYSCLK_ENA_LOW_STS */
  4822. #define ARIZONA_SYSCLK_ENA_LOW_STS_SHIFT 8 /* SYSCLK_ENA_LOW_STS */
  4823. #define ARIZONA_SYSCLK_ENA_LOW_STS_WIDTH 1 /* SYSCLK_ENA_LOW_STS */
  4824. #define ARIZONA_ISRC1_CFG_ERR_STS 0x0080 /* ISRC1_CFG_ERR_STS */
  4825. #define ARIZONA_ISRC1_CFG_ERR_STS_MASK 0x0080 /* ISRC1_CFG_ERR_STS */
  4826. #define ARIZONA_ISRC1_CFG_ERR_STS_SHIFT 7 /* ISRC1_CFG_ERR_STS */
  4827. #define ARIZONA_ISRC1_CFG_ERR_STS_WIDTH 1 /* ISRC1_CFG_ERR_STS */
  4828. #define ARIZONA_ISRC2_CFG_ERR_STS 0x0040 /* ISRC2_CFG_ERR_STS */
  4829. #define ARIZONA_ISRC2_CFG_ERR_STS_MASK 0x0040 /* ISRC2_CFG_ERR_STS */
  4830. #define ARIZONA_ISRC2_CFG_ERR_STS_SHIFT 6 /* ISRC2_CFG_ERR_STS */
  4831. #define ARIZONA_ISRC2_CFG_ERR_STS_WIDTH 1 /* ISRC2_CFG_ERR_STS */
  4832. /*
  4833. * R3363 (0xD23) - Interrupt Raw Status 5
  4834. */
  4835. #define ARIZONA_BOOT_DONE_STS 0x0100 /* BOOT_DONE_STS */
  4836. #define ARIZONA_BOOT_DONE_STS_MASK 0x0100 /* BOOT_DONE_STS */
  4837. #define ARIZONA_BOOT_DONE_STS_SHIFT 8 /* BOOT_DONE_STS */
  4838. #define ARIZONA_BOOT_DONE_STS_WIDTH 1 /* BOOT_DONE_STS */
  4839. #define ARIZONA_DCS_DAC_DONE_STS 0x0080 /* DCS_DAC_DONE_STS */
  4840. #define ARIZONA_DCS_DAC_DONE_STS_MASK 0x0080 /* DCS_DAC_DONE_STS */
  4841. #define ARIZONA_DCS_DAC_DONE_STS_SHIFT 7 /* DCS_DAC_DONE_STS */
  4842. #define ARIZONA_DCS_DAC_DONE_STS_WIDTH 1 /* DCS_DAC_DONE_STS */
  4843. #define ARIZONA_DCS_HP_DONE_STS 0x0040 /* DCS_HP_DONE_STS */
  4844. #define ARIZONA_DCS_HP_DONE_STS_MASK 0x0040 /* DCS_HP_DONE_STS */
  4845. #define ARIZONA_DCS_HP_DONE_STS_SHIFT 6 /* DCS_HP_DONE_STS */
  4846. #define ARIZONA_DCS_HP_DONE_STS_WIDTH 1 /* DCS_HP_DONE_STS */
  4847. #define ARIZONA_FLL2_CLOCK_OK_STS 0x0002 /* FLL2_CLOCK_OK_STS */
  4848. #define ARIZONA_FLL2_CLOCK_OK_STS_MASK 0x0002 /* FLL2_CLOCK_OK_STS */
  4849. #define ARIZONA_FLL2_CLOCK_OK_STS_SHIFT 1 /* FLL2_CLOCK_OK_STS */
  4850. #define ARIZONA_FLL2_CLOCK_OK_STS_WIDTH 1 /* FLL2_CLOCK_OK_STS */
  4851. #define ARIZONA_FLL1_CLOCK_OK_STS 0x0001 /* FLL1_CLOCK_OK_STS */
  4852. #define ARIZONA_FLL1_CLOCK_OK_STS_MASK 0x0001 /* FLL1_CLOCK_OK_STS */
  4853. #define ARIZONA_FLL1_CLOCK_OK_STS_SHIFT 0 /* FLL1_CLOCK_OK_STS */
  4854. #define ARIZONA_FLL1_CLOCK_OK_STS_WIDTH 1 /* FLL1_CLOCK_OK_STS */
  4855. /*
  4856. * R3364 (0xD24) - Interrupt Raw Status 6
  4857. */
  4858. #define ARIZONA_PWM_OVERCLOCKED_STS 0x2000 /* PWM_OVERCLOCKED_STS */
  4859. #define ARIZONA_PWM_OVERCLOCKED_STS_MASK 0x2000 /* PWM_OVERCLOCKED_STS */
  4860. #define ARIZONA_PWM_OVERCLOCKED_STS_SHIFT 13 /* PWM_OVERCLOCKED_STS */
  4861. #define ARIZONA_PWM_OVERCLOCKED_STS_WIDTH 1 /* PWM_OVERCLOCKED_STS */
  4862. #define ARIZONA_FX_CORE_OVERCLOCKED_STS 0x1000 /* FX_CORE_OVERCLOCKED_STS */
  4863. #define ARIZONA_FX_CORE_OVERCLOCKED_STS_MASK 0x1000 /* FX_CORE_OVERCLOCKED_STS */
  4864. #define ARIZONA_FX_CORE_OVERCLOCKED_STS_SHIFT 12 /* FX_CORE_OVERCLOCKED_STS */
  4865. #define ARIZONA_FX_CORE_OVERCLOCKED_STS_WIDTH 1 /* FX_CORE_OVERCLOCKED_STS */
  4866. #define ARIZONA_DAC_SYS_OVERCLOCKED_STS 0x0400 /* DAC_SYS_OVERCLOCKED_STS */
  4867. #define ARIZONA_DAC_SYS_OVERCLOCKED_STS_MASK 0x0400 /* DAC_SYS_OVERCLOCKED_STS */
  4868. #define ARIZONA_DAC_SYS_OVERCLOCKED_STS_SHIFT 10 /* DAC_SYS_OVERCLOCKED_STS */
  4869. #define ARIZONA_DAC_SYS_OVERCLOCKED_STS_WIDTH 1 /* DAC_SYS_OVERCLOCKED_STS */
  4870. #define ARIZONA_DAC_WARP_OVERCLOCKED_STS 0x0200 /* DAC_WARP_OVERCLOCKED_STS */
  4871. #define ARIZONA_DAC_WARP_OVERCLOCKED_STS_MASK 0x0200 /* DAC_WARP_OVERCLOCKED_STS */
  4872. #define ARIZONA_DAC_WARP_OVERCLOCKED_STS_SHIFT 9 /* DAC_WARP_OVERCLOCKED_STS */
  4873. #define ARIZONA_DAC_WARP_OVERCLOCKED_STS_WIDTH 1 /* DAC_WARP_OVERCLOCKED_STS */
  4874. #define ARIZONA_ADC_OVERCLOCKED_STS 0x0100 /* ADC_OVERCLOCKED_STS */
  4875. #define ARIZONA_ADC_OVERCLOCKED_STS_MASK 0x0100 /* ADC_OVERCLOCKED_STS */
  4876. #define ARIZONA_ADC_OVERCLOCKED_STS_SHIFT 8 /* ADC_OVERCLOCKED_STS */
  4877. #define ARIZONA_ADC_OVERCLOCKED_STS_WIDTH 1 /* ADC_OVERCLOCKED_STS */
  4878. #define ARIZONA_MIXER_OVERCLOCKED_STS 0x0080 /* MIXER_OVERCLOCKED_STS */
  4879. #define ARIZONA_MIXER_OVERCLOCKED_STS_MASK 0x0080 /* MIXER_OVERCLOCKED_STS */
  4880. #define ARIZONA_MIXER_OVERCLOCKED_STS_SHIFT 7 /* MIXER_OVERCLOCKED_STS */
  4881. #define ARIZONA_MIXER_OVERCLOCKED_STS_WIDTH 1 /* MIXER_OVERCLOCKED_STS */
  4882. #define ARIZONA_AIF3_ASYNC_OVERCLOCKED_STS 0x0040 /* AIF3_ASYNC_OVERCLOCKED_STS */
  4883. #define ARIZONA_AIF3_ASYNC_OVERCLOCKED_STS_MASK 0x0040 /* AIF3_ASYNC_OVERCLOCKED_STS */
  4884. #define ARIZONA_AIF3_ASYNC_OVERCLOCKED_STS_SHIFT 6 /* AIF3_ASYNC_OVERCLOCKED_STS */
  4885. #define ARIZONA_AIF3_ASYNC_OVERCLOCKED_STS_WIDTH 1 /* AIF3_ASYNC_OVERCLOCKED_STS */
  4886. #define ARIZONA_AIF2_ASYNC_OVERCLOCKED_STS 0x0020 /* AIF2_ASYNC_OVERCLOCKED_STS */
  4887. #define ARIZONA_AIF2_ASYNC_OVERCLOCKED_STS_MASK 0x0020 /* AIF2_ASYNC_OVERCLOCKED_STS */
  4888. #define ARIZONA_AIF2_ASYNC_OVERCLOCKED_STS_SHIFT 5 /* AIF2_ASYNC_OVERCLOCKED_STS */
  4889. #define ARIZONA_AIF2_ASYNC_OVERCLOCKED_STS_WIDTH 1 /* AIF2_ASYNC_OVERCLOCKED_STS */
  4890. #define ARIZONA_AIF1_ASYNC_OVERCLOCKED_STS 0x0010 /* AIF1_ASYNC_OVERCLOCKED_STS */
  4891. #define ARIZONA_AIF1_ASYNC_OVERCLOCKED_STS_MASK 0x0010 /* AIF1_ASYNC_OVERCLOCKED_STS */
  4892. #define ARIZONA_AIF1_ASYNC_OVERCLOCKED_STS_SHIFT 4 /* AIF1_ASYNC_OVERCLOCKED_STS */
  4893. #define ARIZONA_AIF1_ASYNC_OVERCLOCKED_STS_WIDTH 1 /* AIF1_ASYNC_OVERCLOCKED_STS */
  4894. #define ARIZONA_AIF3_SYNC_OVERCLOCKED_STS 0x0008 /* AIF3_SYNC_OVERCLOCKED_STS */
  4895. #define ARIZONA_AIF3_SYNC_OVERCLOCKED_STS_MASK 0x0008 /* AIF3_SYNC_OVERCLOCKED_STS */
  4896. #define ARIZONA_AIF3_SYNC_OVERCLOCKED_STS_SHIFT 3 /* AIF3_SYNC_OVERCLOCKED_STS */
  4897. #define ARIZONA_AIF3_SYNC_OVERCLOCKED_STS_WIDTH 1 /* AIF3_SYNC_OVERCLOCKED_STS */
  4898. #define ARIZONA_AIF2_SYNC_OVERCLOCKED_STS 0x0004 /* AIF2_SYNC_OVERCLOCKED_STS */
  4899. #define ARIZONA_AIF2_SYNC_OVERCLOCKED_STS_MASK 0x0004 /* AIF2_SYNC_OVERCLOCKED_STS */
  4900. #define ARIZONA_AIF2_SYNC_OVERCLOCKED_STS_SHIFT 2 /* AIF2_SYNC_OVERCLOCKED_STS */
  4901. #define ARIZONA_AIF2_SYNC_OVERCLOCKED_STS_WIDTH 1 /* AIF2_SYNC_OVERCLOCKED_STS */
  4902. #define ARIZONA_AIF1_SYNC_OVERCLOCKED_STS 0x0002 /* AIF1_SYNC_OVERCLOCKED_STS */
  4903. #define ARIZONA_AIF1_SYNC_OVERCLOCKED_STS_MASK 0x0002 /* AIF1_SYNC_OVERCLOCKED_STS */
  4904. #define ARIZONA_AIF1_SYNC_OVERCLOCKED_STS_SHIFT 1 /* AIF1_SYNC_OVERCLOCKED_STS */
  4905. #define ARIZONA_AIF1_SYNC_OVERCLOCKED_STS_WIDTH 1 /* AIF1_SYNC_OVERCLOCKED_STS */
  4906. #define ARIZONA_PAD_CTRL_OVERCLOCKED_STS 0x0001 /* PAD_CTRL_OVERCLOCKED_STS */
  4907. #define ARIZONA_PAD_CTRL_OVERCLOCKED_STS_MASK 0x0001 /* PAD_CTRL_OVERCLOCKED_STS */
  4908. #define ARIZONA_PAD_CTRL_OVERCLOCKED_STS_SHIFT 0 /* PAD_CTRL_OVERCLOCKED_STS */
  4909. #define ARIZONA_PAD_CTRL_OVERCLOCKED_STS_WIDTH 1 /* PAD_CTRL_OVERCLOCKED_STS */
  4910. /*
  4911. * R3365 (0xD25) - Interrupt Raw Status 7
  4912. */
  4913. #define ARIZONA_SLIMBUS_SUBSYS_OVERCLOCKED_STS 0x8000 /* SLIMBUS_SUBSYS_OVERCLOCKED_STS */
  4914. #define ARIZONA_SLIMBUS_SUBSYS_OVERCLOCKED_STS_MASK 0x8000 /* SLIMBUS_SUBSYS_OVERCLOCKED_STS */
  4915. #define ARIZONA_SLIMBUS_SUBSYS_OVERCLOCKED_STS_SHIFT 15 /* SLIMBUS_SUBSYS_OVERCLOCKED_STS */
  4916. #define ARIZONA_SLIMBUS_SUBSYS_OVERCLOCKED_STS_WIDTH 1 /* SLIMBUS_SUBSYS_OVERCLOCKED_STS */
  4917. #define ARIZONA_SLIMBUS_ASYNC_OVERCLOCKED_STS 0x4000 /* SLIMBUS_ASYNC_OVERCLOCKED_STS */
  4918. #define ARIZONA_SLIMBUS_ASYNC_OVERCLOCKED_STS_MASK 0x4000 /* SLIMBUS_ASYNC_OVERCLOCKED_STS */
  4919. #define ARIZONA_SLIMBUS_ASYNC_OVERCLOCKED_STS_SHIFT 14 /* SLIMBUS_ASYNC_OVERCLOCKED_STS */
  4920. #define ARIZONA_SLIMBUS_ASYNC_OVERCLOCKED_STS_WIDTH 1 /* SLIMBUS_ASYNC_OVERCLOCKED_STS */
  4921. #define ARIZONA_SLIMBUS_SYNC_OVERCLOCKED_STS 0x2000 /* SLIMBUS_SYNC_OVERCLOCKED_STS */
  4922. #define ARIZONA_SLIMBUS_SYNC_OVERCLOCKED_STS_MASK 0x2000 /* SLIMBUS_SYNC_OVERCLOCKED_STS */
  4923. #define ARIZONA_SLIMBUS_SYNC_OVERCLOCKED_STS_SHIFT 13 /* SLIMBUS_SYNC_OVERCLOCKED_STS */
  4924. #define ARIZONA_SLIMBUS_SYNC_OVERCLOCKED_STS_WIDTH 1 /* SLIMBUS_SYNC_OVERCLOCKED_STS */
  4925. #define ARIZONA_ASRC_ASYNC_SYS_OVERCLOCKED_STS 0x1000 /* ASRC_ASYNC_SYS_OVERCLOCKED_STS */
  4926. #define ARIZONA_ASRC_ASYNC_SYS_OVERCLOCKED_STS_MASK 0x1000 /* ASRC_ASYNC_SYS_OVERCLOCKED_STS */
  4927. #define ARIZONA_ASRC_ASYNC_SYS_OVERCLOCKED_STS_SHIFT 12 /* ASRC_ASYNC_SYS_OVERCLOCKED_STS */
  4928. #define ARIZONA_ASRC_ASYNC_SYS_OVERCLOCKED_STS_WIDTH 1 /* ASRC_ASYNC_SYS_OVERCLOCKED_STS */
  4929. #define ARIZONA_ASRC_ASYNC_WARP_OVERCLOCKED_STS 0x0800 /* ASRC_ASYNC_WARP_OVERCLOCKED_STS */
  4930. #define ARIZONA_ASRC_ASYNC_WARP_OVERCLOCKED_STS_MASK 0x0800 /* ASRC_ASYNC_WARP_OVERCLOCKED_STS */
  4931. #define ARIZONA_ASRC_ASYNC_WARP_OVERCLOCKED_STS_SHIFT 11 /* ASRC_ASYNC_WARP_OVERCLOCKED_STS */
  4932. #define ARIZONA_ASRC_ASYNC_WARP_OVERCLOCKED_STS_WIDTH 1 /* ASRC_ASYNC_WARP_OVERCLOCKED_STS */
  4933. #define ARIZONA_ASRC_SYNC_SYS_OVERCLOCKED_STS 0x0400 /* ASRC_SYNC_SYS_OVERCLOCKED_STS */
  4934. #define ARIZONA_ASRC_SYNC_SYS_OVERCLOCKED_STS_MASK 0x0400 /* ASRC_SYNC_SYS_OVERCLOCKED_STS */
  4935. #define ARIZONA_ASRC_SYNC_SYS_OVERCLOCKED_STS_SHIFT 10 /* ASRC_SYNC_SYS_OVERCLOCKED_STS */
  4936. #define ARIZONA_ASRC_SYNC_SYS_OVERCLOCKED_STS_WIDTH 1 /* ASRC_SYNC_SYS_OVERCLOCKED_STS */
  4937. #define ARIZONA_ASRC_SYNC_WARP_OVERCLOCKED_STS 0x0200 /* ASRC_SYNC_WARP_OVERCLOCKED_STS */
  4938. #define ARIZONA_ASRC_SYNC_WARP_OVERCLOCKED_STS_MASK 0x0200 /* ASRC_SYNC_WARP_OVERCLOCKED_STS */
  4939. #define ARIZONA_ASRC_SYNC_WARP_OVERCLOCKED_STS_SHIFT 9 /* ASRC_SYNC_WARP_OVERCLOCKED_STS */
  4940. #define ARIZONA_ASRC_SYNC_WARP_OVERCLOCKED_STS_WIDTH 1 /* ASRC_SYNC_WARP_OVERCLOCKED_STS */
  4941. #define ARIZONA_ADSP2_1_OVERCLOCKED_STS 0x0008 /* ADSP2_1_OVERCLOCKED_STS */
  4942. #define ARIZONA_ADSP2_1_OVERCLOCKED_STS_MASK 0x0008 /* ADSP2_1_OVERCLOCKED_STS */
  4943. #define ARIZONA_ADSP2_1_OVERCLOCKED_STS_SHIFT 3 /* ADSP2_1_OVERCLOCKED_STS */
  4944. #define ARIZONA_ADSP2_1_OVERCLOCKED_STS_WIDTH 1 /* ADSP2_1_OVERCLOCKED_STS */
  4945. #define ARIZONA_ISRC2_OVERCLOCKED_STS 0x0002 /* ISRC2_OVERCLOCKED_STS */
  4946. #define ARIZONA_ISRC2_OVERCLOCKED_STS_MASK 0x0002 /* ISRC2_OVERCLOCKED_STS */
  4947. #define ARIZONA_ISRC2_OVERCLOCKED_STS_SHIFT 1 /* ISRC2_OVERCLOCKED_STS */
  4948. #define ARIZONA_ISRC2_OVERCLOCKED_STS_WIDTH 1 /* ISRC2_OVERCLOCKED_STS */
  4949. #define ARIZONA_ISRC1_OVERCLOCKED_STS 0x0001 /* ISRC1_OVERCLOCKED_STS */
  4950. #define ARIZONA_ISRC1_OVERCLOCKED_STS_MASK 0x0001 /* ISRC1_OVERCLOCKED_STS */
  4951. #define ARIZONA_ISRC1_OVERCLOCKED_STS_SHIFT 0 /* ISRC1_OVERCLOCKED_STS */
  4952. #define ARIZONA_ISRC1_OVERCLOCKED_STS_WIDTH 1 /* ISRC1_OVERCLOCKED_STS */
  4953. /*
  4954. * R3366 (0xD26) - Interrupt Raw Status 8
  4955. */
  4956. #define ARIZONA_AIF3_UNDERCLOCKED_STS 0x0400 /* AIF3_UNDERCLOCKED_STS */
  4957. #define ARIZONA_AIF3_UNDERCLOCKED_STS_MASK 0x0400 /* AIF3_UNDERCLOCKED_STS */
  4958. #define ARIZONA_AIF3_UNDERCLOCKED_STS_SHIFT 10 /* AIF3_UNDERCLOCKED_STS */
  4959. #define ARIZONA_AIF3_UNDERCLOCKED_STS_WIDTH 1 /* AIF3_UNDERCLOCKED_STS */
  4960. #define ARIZONA_AIF2_UNDERCLOCKED_STS 0x0200 /* AIF2_UNDERCLOCKED_STS */
  4961. #define ARIZONA_AIF2_UNDERCLOCKED_STS_MASK 0x0200 /* AIF2_UNDERCLOCKED_STS */
  4962. #define ARIZONA_AIF2_UNDERCLOCKED_STS_SHIFT 9 /* AIF2_UNDERCLOCKED_STS */
  4963. #define ARIZONA_AIF2_UNDERCLOCKED_STS_WIDTH 1 /* AIF2_UNDERCLOCKED_STS */
  4964. #define ARIZONA_AIF1_UNDERCLOCKED_STS 0x0100 /* AIF1_UNDERCLOCKED_STS */
  4965. #define ARIZONA_AIF1_UNDERCLOCKED_STS_MASK 0x0100 /* AIF1_UNDERCLOCKED_STS */
  4966. #define ARIZONA_AIF1_UNDERCLOCKED_STS_SHIFT 8 /* AIF1_UNDERCLOCKED_STS */
  4967. #define ARIZONA_AIF1_UNDERCLOCKED_STS_WIDTH 1 /* AIF1_UNDERCLOCKED_STS */
  4968. #define ARIZONA_ISRC2_UNDERCLOCKED_STS 0x0040 /* ISRC2_UNDERCLOCKED_STS */
  4969. #define ARIZONA_ISRC2_UNDERCLOCKED_STS_MASK 0x0040 /* ISRC2_UNDERCLOCKED_STS */
  4970. #define ARIZONA_ISRC2_UNDERCLOCKED_STS_SHIFT 6 /* ISRC2_UNDERCLOCKED_STS */
  4971. #define ARIZONA_ISRC2_UNDERCLOCKED_STS_WIDTH 1 /* ISRC2_UNDERCLOCKED_STS */
  4972. #define ARIZONA_ISRC1_UNDERCLOCKED_STS 0x0020 /* ISRC1_UNDERCLOCKED_STS */
  4973. #define ARIZONA_ISRC1_UNDERCLOCKED_STS_MASK 0x0020 /* ISRC1_UNDERCLOCKED_STS */
  4974. #define ARIZONA_ISRC1_UNDERCLOCKED_STS_SHIFT 5 /* ISRC1_UNDERCLOCKED_STS */
  4975. #define ARIZONA_ISRC1_UNDERCLOCKED_STS_WIDTH 1 /* ISRC1_UNDERCLOCKED_STS */
  4976. #define ARIZONA_FX_UNDERCLOCKED_STS 0x0010 /* FX_UNDERCLOCKED_STS */
  4977. #define ARIZONA_FX_UNDERCLOCKED_STS_MASK 0x0010 /* FX_UNDERCLOCKED_STS */
  4978. #define ARIZONA_FX_UNDERCLOCKED_STS_SHIFT 4 /* FX_UNDERCLOCKED_STS */
  4979. #define ARIZONA_FX_UNDERCLOCKED_STS_WIDTH 1 /* FX_UNDERCLOCKED_STS */
  4980. #define ARIZONA_ASRC_UNDERCLOCKED_STS 0x0008 /* ASRC_UNDERCLOCKED_STS */
  4981. #define ARIZONA_ASRC_UNDERCLOCKED_STS_MASK 0x0008 /* ASRC_UNDERCLOCKED_STS */
  4982. #define ARIZONA_ASRC_UNDERCLOCKED_STS_SHIFT 3 /* ASRC_UNDERCLOCKED_STS */
  4983. #define ARIZONA_ASRC_UNDERCLOCKED_STS_WIDTH 1 /* ASRC_UNDERCLOCKED_STS */
  4984. #define ARIZONA_DAC_UNDERCLOCKED_STS 0x0004 /* DAC_UNDERCLOCKED_STS */
  4985. #define ARIZONA_DAC_UNDERCLOCKED_STS_MASK 0x0004 /* DAC_UNDERCLOCKED_STS */
  4986. #define ARIZONA_DAC_UNDERCLOCKED_STS_SHIFT 2 /* DAC_UNDERCLOCKED_STS */
  4987. #define ARIZONA_DAC_UNDERCLOCKED_STS_WIDTH 1 /* DAC_UNDERCLOCKED_STS */
  4988. #define ARIZONA_ADC_UNDERCLOCKED_STS 0x0002 /* ADC_UNDERCLOCKED_STS */
  4989. #define ARIZONA_ADC_UNDERCLOCKED_STS_MASK 0x0002 /* ADC_UNDERCLOCKED_STS */
  4990. #define ARIZONA_ADC_UNDERCLOCKED_STS_SHIFT 1 /* ADC_UNDERCLOCKED_STS */
  4991. #define ARIZONA_ADC_UNDERCLOCKED_STS_WIDTH 1 /* ADC_UNDERCLOCKED_STS */
  4992. #define ARIZONA_MIXER_UNDERCLOCKED_STS 0x0001 /* MIXER_UNDERCLOCKED_STS */
  4993. #define ARIZONA_MIXER_UNDERCLOCKED_STS_MASK 0x0001 /* MIXER_UNDERCLOCKED_STS */
  4994. #define ARIZONA_MIXER_UNDERCLOCKED_STS_SHIFT 0 /* MIXER_UNDERCLOCKED_STS */
  4995. #define ARIZONA_MIXER_UNDERCLOCKED_STS_WIDTH 1 /* MIXER_UNDERCLOCKED_STS */
  4996. /*
  4997. * R3392 (0xD40) - IRQ Pin Status
  4998. */
  4999. #define ARIZONA_IRQ2_STS 0x0002 /* IRQ2_STS */
  5000. #define ARIZONA_IRQ2_STS_MASK 0x0002 /* IRQ2_STS */
  5001. #define ARIZONA_IRQ2_STS_SHIFT 1 /* IRQ2_STS */
  5002. #define ARIZONA_IRQ2_STS_WIDTH 1 /* IRQ2_STS */
  5003. #define ARIZONA_IRQ1_STS 0x0001 /* IRQ1_STS */
  5004. #define ARIZONA_IRQ1_STS_MASK 0x0001 /* IRQ1_STS */
  5005. #define ARIZONA_IRQ1_STS_SHIFT 0 /* IRQ1_STS */
  5006. #define ARIZONA_IRQ1_STS_WIDTH 1 /* IRQ1_STS */
  5007. /*
  5008. * R3393 (0xD41) - ADSP2 IRQ0
  5009. */
  5010. #define ARIZONA_DSP_IRQ2 0x0002 /* DSP_IRQ2 */
  5011. #define ARIZONA_DSP_IRQ2_MASK 0x0002 /* DSP_IRQ2 */
  5012. #define ARIZONA_DSP_IRQ2_SHIFT 1 /* DSP_IRQ2 */
  5013. #define ARIZONA_DSP_IRQ2_WIDTH 1 /* DSP_IRQ2 */
  5014. #define ARIZONA_DSP_IRQ1 0x0001 /* DSP_IRQ1 */
  5015. #define ARIZONA_DSP_IRQ1_MASK 0x0001 /* DSP_IRQ1 */
  5016. #define ARIZONA_DSP_IRQ1_SHIFT 0 /* DSP_IRQ1 */
  5017. #define ARIZONA_DSP_IRQ1_WIDTH 1 /* DSP_IRQ1 */
  5018. /*
  5019. * R3408 (0xD50) - AOD wkup and trig
  5020. */
  5021. #define ARIZONA_MICD_CLAMP_FALL_TRIG_STS 0x0080 /* MICD_CLAMP_FALL_TRIG_STS */
  5022. #define ARIZONA_MICD_CLAMP_FALL_TRIG_STS_MASK 0x0080 /* MICD_CLAMP_FALL_TRIG_STS */
  5023. #define ARIZONA_MICD_CLAMP_FALL_TRIG_STS_SHIFT 7 /* MICD_CLAMP_FALL_TRIG_STS */
  5024. #define ARIZONA_MICD_CLAMP_FALL_TRIG_STS_WIDTH 1 /* MICD_CLAMP_FALL_TRIG_STS */
  5025. #define ARIZONA_MICD_CLAMP_RISE_TRIG_STS 0x0040 /* MICD_CLAMP_RISE_TRIG_STS */
  5026. #define ARIZONA_MICD_CLAMP_RISE_TRIG_STS_MASK 0x0040 /* MICD_CLAMP_RISE_TRIG_STS */
  5027. #define ARIZONA_MICD_CLAMP_RISE_TRIG_STS_SHIFT 6 /* MICD_CLAMP_RISE_TRIG_STS */
  5028. #define ARIZONA_MICD_CLAMP_RISE_TRIG_STS_WIDTH 1 /* MICD_CLAMP_RISE_TRIG_STS */
  5029. #define ARIZONA_GP5_FALL_TRIG_STS 0x0020 /* GP5_FALL_TRIG_STS */
  5030. #define ARIZONA_GP5_FALL_TRIG_STS_MASK 0x0020 /* GP5_FALL_TRIG_STS */
  5031. #define ARIZONA_GP5_FALL_TRIG_STS_SHIFT 5 /* GP5_FALL_TRIG_STS */
  5032. #define ARIZONA_GP5_FALL_TRIG_STS_WIDTH 1 /* GP5_FALL_TRIG_STS */
  5033. #define ARIZONA_GP5_RISE_TRIG_STS 0x0010 /* GP5_RISE_TRIG_STS */
  5034. #define ARIZONA_GP5_RISE_TRIG_STS_MASK 0x0010 /* GP5_RISE_TRIG_STS */
  5035. #define ARIZONA_GP5_RISE_TRIG_STS_SHIFT 4 /* GP5_RISE_TRIG_STS */
  5036. #define ARIZONA_GP5_RISE_TRIG_STS_WIDTH 1 /* GP5_RISE_TRIG_STS */
  5037. #define ARIZONA_JD1_FALL_TRIG_STS 0x0008 /* JD1_FALL_TRIG_STS */
  5038. #define ARIZONA_JD1_FALL_TRIG_STS_MASK 0x0008 /* JD1_FALL_TRIG_STS */
  5039. #define ARIZONA_JD1_FALL_TRIG_STS_SHIFT 3 /* JD1_FALL_TRIG_STS */
  5040. #define ARIZONA_JD1_FALL_TRIG_STS_WIDTH 1 /* JD1_FALL_TRIG_STS */
  5041. #define ARIZONA_JD1_RISE_TRIG_STS 0x0004 /* JD1_RISE_TRIG_STS */
  5042. #define ARIZONA_JD1_RISE_TRIG_STS_MASK 0x0004 /* JD1_RISE_TRIG_STS */
  5043. #define ARIZONA_JD1_RISE_TRIG_STS_SHIFT 2 /* JD1_RISE_TRIG_STS */
  5044. #define ARIZONA_JD1_RISE_TRIG_STS_WIDTH 1 /* JD1_RISE_TRIG_STS */
  5045. #define ARIZONA_JD2_FALL_TRIG_STS 0x0002 /* JD2_FALL_TRIG_STS */
  5046. #define ARIZONA_JD2_FALL_TRIG_STS_MASK 0x0002 /* JD2_FALL_TRIG_STS */
  5047. #define ARIZONA_JD2_FALL_TRIG_STS_SHIFT 1 /* JD2_FALL_TRIG_STS */
  5048. #define ARIZONA_JD2_FALL_TRIG_STS_WIDTH 1 /* JD2_FALL_TRIG_STS */
  5049. #define ARIZONA_JD2_RISE_TRIG_STS 0x0001 /* JD2_RISE_TRIG_STS */
  5050. #define ARIZONA_JD2_RISE_TRIG_STS_MASK 0x0001 /* JD2_RISE_TRIG_STS */
  5051. #define ARIZONA_JD2_RISE_TRIG_STS_SHIFT 0 /* JD2_RISE_TRIG_STS */
  5052. #define ARIZONA_JD2_RISE_TRIG_STS_WIDTH 1 /* JD2_RISE_TRIG_STS */
  5053. /*
  5054. * R3409 (0xD51) - AOD IRQ1
  5055. */
  5056. #define ARIZONA_MICD_CLAMP_FALL_EINT1 0x0080 /* MICD_CLAMP_FALL_EINT1 */
  5057. #define ARIZONA_MICD_CLAMP_FALL_EINT1_MASK 0x0080 /* MICD_CLAMP_FALL_EINT1 */
  5058. #define ARIZONA_MICD_CLAMP_FALL_EINT1_SHIFT 7 /* MICD_CLAMP_FALL_EINT1 */
  5059. #define ARIZONA_MICD_CLAMP_RISE_EINT1 0x0040 /* MICD_CLAMP_RISE_EINT1 */
  5060. #define ARIZONA_MICD_CLAMP_RISE_EINT1_MASK 0x0040 /* MICD_CLAMP_RISE_EINT1 */
  5061. #define ARIZONA_MICD_CLAMP_RISE_EINT1_SHIFT 6 /* MICD_CLAMP_RISE_EINT1 */
  5062. #define ARIZONA_GP5_FALL_EINT1 0x0020 /* GP5_FALL_EINT1 */
  5063. #define ARIZONA_GP5_FALL_EINT1_MASK 0x0020 /* GP5_FALL_EINT1 */
  5064. #define ARIZONA_GP5_FALL_EINT1_SHIFT 5 /* GP5_FALL_EINT1 */
  5065. #define ARIZONA_GP5_FALL_EINT1_WIDTH 1 /* GP5_FALL_EINT1 */
  5066. #define ARIZONA_GP5_RISE_EINT1 0x0010 /* GP5_RISE_EINT1 */
  5067. #define ARIZONA_GP5_RISE_EINT1_MASK 0x0010 /* GP5_RISE_EINT1 */
  5068. #define ARIZONA_GP5_RISE_EINT1_SHIFT 4 /* GP5_RISE_EINT1 */
  5069. #define ARIZONA_GP5_RISE_EINT1_WIDTH 1 /* GP5_RISE_EINT1 */
  5070. #define ARIZONA_JD1_FALL_EINT1 0x0008 /* JD1_FALL_EINT1 */
  5071. #define ARIZONA_JD1_FALL_EINT1_MASK 0x0008 /* JD1_FALL_EINT1 */
  5072. #define ARIZONA_JD1_FALL_EINT1_SHIFT 3 /* JD1_FALL_EINT1 */
  5073. #define ARIZONA_JD1_FALL_EINT1_WIDTH 1 /* JD1_FALL_EINT1 */
  5074. #define ARIZONA_JD1_RISE_EINT1 0x0004 /* JD1_RISE_EINT1 */
  5075. #define ARIZONA_JD1_RISE_EINT1_MASK 0x0004 /* JD1_RISE_EINT1 */
  5076. #define ARIZONA_JD1_RISE_EINT1_SHIFT 2 /* JD1_RISE_EINT1 */
  5077. #define ARIZONA_JD1_RISE_EINT1_WIDTH 1 /* JD1_RISE_EINT1 */
  5078. #define ARIZONA_JD2_FALL_EINT1 0x0002 /* JD2_FALL_EINT1 */
  5079. #define ARIZONA_JD2_FALL_EINT1_MASK 0x0002 /* JD2_FALL_EINT1 */
  5080. #define ARIZONA_JD2_FALL_EINT1_SHIFT 1 /* JD2_FALL_EINT1 */
  5081. #define ARIZONA_JD2_FALL_EINT1_WIDTH 1 /* JD2_FALL_EINT1 */
  5082. #define ARIZONA_JD2_RISE_EINT1 0x0001 /* JD2_RISE_EINT1 */
  5083. #define ARIZONA_JD2_RISE_EINT1_MASK 0x0001 /* JD2_RISE_EINT1 */
  5084. #define ARIZONA_JD2_RISE_EINT1_SHIFT 0 /* JD2_RISE_EINT1 */
  5085. #define ARIZONA_JD2_RISE_EINT1_WIDTH 1 /* JD2_RISE_EINT1 */
  5086. /*
  5087. * R3410 (0xD52) - AOD IRQ2
  5088. */
  5089. #define ARIZONA_MICD_CLAMP_FALL_EINT2 0x0080 /* MICD_CLAMP_FALL_EINT2 */
  5090. #define ARIZONA_MICD_CLAMP_FALL_EINT2_MASK 0x0080 /* MICD_CLAMP_FALL_EINT2 */
  5091. #define ARIZONA_MICD_CLAMP_FALL_EINT2_SHIFT 7 /* MICD_CLAMP_FALL_EINT2 */
  5092. #define ARIZONA_MICD_CLAMP_RISE_EINT2 0x0040 /* MICD_CLAMP_RISE_EINT2 */
  5093. #define ARIZONA_MICD_CLAMP_RISE_EINT2_MASK 0x0040 /* MICD_CLAMP_RISE_EINT2 */
  5094. #define ARIZONA_MICD_CLAMP_RISE_EINT2_SHIFT 6 /* MICD_CLAMP_RISE_EINT2 */
  5095. #define ARIZONA_GP5_FALL_EINT2 0x0020 /* GP5_FALL_EINT2 */
  5096. #define ARIZONA_GP5_FALL_EINT2_MASK 0x0020 /* GP5_FALL_EINT2 */
  5097. #define ARIZONA_GP5_FALL_EINT2_SHIFT 5 /* GP5_FALL_EINT2 */
  5098. #define ARIZONA_GP5_FALL_EINT2_WIDTH 1 /* GP5_FALL_EINT2 */
  5099. #define ARIZONA_GP5_RISE_EINT2 0x0010 /* GP5_RISE_EINT2 */
  5100. #define ARIZONA_GP5_RISE_EINT2_MASK 0x0010 /* GP5_RISE_EINT2 */
  5101. #define ARIZONA_GP5_RISE_EINT2_SHIFT 4 /* GP5_RISE_EINT2 */
  5102. #define ARIZONA_GP5_RISE_EINT2_WIDTH 1 /* GP5_RISE_EINT2 */
  5103. #define ARIZONA_JD1_FALL_EINT2 0x0008 /* JD1_FALL_EINT2 */
  5104. #define ARIZONA_JD1_FALL_EINT2_MASK 0x0008 /* JD1_FALL_EINT2 */
  5105. #define ARIZONA_JD1_FALL_EINT2_SHIFT 3 /* JD1_FALL_EINT2 */
  5106. #define ARIZONA_JD1_FALL_EINT2_WIDTH 1 /* JD1_FALL_EINT2 */
  5107. #define ARIZONA_JD1_RISE_EINT2 0x0004 /* JD1_RISE_EINT2 */
  5108. #define ARIZONA_JD1_RISE_EINT2_MASK 0x0004 /* JD1_RISE_EINT2 */
  5109. #define ARIZONA_JD1_RISE_EINT2_SHIFT 2 /* JD1_RISE_EINT2 */
  5110. #define ARIZONA_JD1_RISE_EINT2_WIDTH 1 /* JD1_RISE_EINT2 */
  5111. #define ARIZONA_JD2_FALL_EINT2 0x0002 /* JD2_FALL_EINT2 */
  5112. #define ARIZONA_JD2_FALL_EINT2_MASK 0x0002 /* JD2_FALL_EINT2 */
  5113. #define ARIZONA_JD2_FALL_EINT2_SHIFT 1 /* JD2_FALL_EINT2 */
  5114. #define ARIZONA_JD2_FALL_EINT2_WIDTH 1 /* JD2_FALL_EINT2 */
  5115. #define ARIZONA_JD2_RISE_EINT2 0x0001 /* JD2_RISE_EINT2 */
  5116. #define ARIZONA_JD2_RISE_EINT2_MASK 0x0001 /* JD2_RISE_EINT2 */
  5117. #define ARIZONA_JD2_RISE_EINT2_SHIFT 0 /* JD2_RISE_EINT2 */
  5118. #define ARIZONA_JD2_RISE_EINT2_WIDTH 1 /* JD2_RISE_EINT2 */
  5119. /*
  5120. * R3411 (0xD53) - AOD IRQ Mask IRQ1
  5121. */
  5122. #define ARIZONA_IM_GP5_FALL_EINT1 0x0020 /* IM_GP5_FALL_EINT1 */
  5123. #define ARIZONA_IM_GP5_FALL_EINT1_MASK 0x0020 /* IM_GP5_FALL_EINT1 */
  5124. #define ARIZONA_IM_GP5_FALL_EINT1_SHIFT 5 /* IM_GP5_FALL_EINT1 */
  5125. #define ARIZONA_IM_GP5_FALL_EINT1_WIDTH 1 /* IM_GP5_FALL_EINT1 */
  5126. #define ARIZONA_IM_GP5_RISE_EINT1 0x0010 /* IM_GP5_RISE_EINT1 */
  5127. #define ARIZONA_IM_GP5_RISE_EINT1_MASK 0x0010 /* IM_GP5_RISE_EINT1 */
  5128. #define ARIZONA_IM_GP5_RISE_EINT1_SHIFT 4 /* IM_GP5_RISE_EINT1 */
  5129. #define ARIZONA_IM_GP5_RISE_EINT1_WIDTH 1 /* IM_GP5_RISE_EINT1 */
  5130. #define ARIZONA_IM_JD1_FALL_EINT1 0x0008 /* IM_JD1_FALL_EINT1 */
  5131. #define ARIZONA_IM_JD1_FALL_EINT1_MASK 0x0008 /* IM_JD1_FALL_EINT1 */
  5132. #define ARIZONA_IM_JD1_FALL_EINT1_SHIFT 3 /* IM_JD1_FALL_EINT1 */
  5133. #define ARIZONA_IM_JD1_FALL_EINT1_WIDTH 1 /* IM_JD1_FALL_EINT1 */
  5134. #define ARIZONA_IM_JD1_RISE_EINT1 0x0004 /* IM_JD1_RISE_EINT1 */
  5135. #define ARIZONA_IM_JD1_RISE_EINT1_MASK 0x0004 /* IM_JD1_RISE_EINT1 */
  5136. #define ARIZONA_IM_JD1_RISE_EINT1_SHIFT 2 /* IM_JD1_RISE_EINT1 */
  5137. #define ARIZONA_IM_JD1_RISE_EINT1_WIDTH 1 /* IM_JD1_RISE_EINT1 */
  5138. #define ARIZONA_IM_JD2_FALL_EINT1 0x0002 /* IM_JD2_FALL_EINT1 */
  5139. #define ARIZONA_IM_JD2_FALL_EINT1_MASK 0x0002 /* IM_JD2_FALL_EINT1 */
  5140. #define ARIZONA_IM_JD2_FALL_EINT1_SHIFT 1 /* IM_JD2_FALL_EINT1 */
  5141. #define ARIZONA_IM_JD2_FALL_EINT1_WIDTH 1 /* IM_JD2_FALL_EINT1 */
  5142. #define ARIZONA_IM_JD2_RISE_EINT1 0x0001 /* IM_JD2_RISE_EINT1 */
  5143. #define ARIZONA_IM_JD2_RISE_EINT1_MASK 0x0001 /* IM_JD2_RISE_EINT1 */
  5144. #define ARIZONA_IM_JD2_RISE_EINT1_SHIFT 0 /* IM_JD2_RISE_EINT1 */
  5145. #define ARIZONA_IM_JD2_RISE_EINT1_WIDTH 1 /* IM_JD2_RISE_EINT1 */
  5146. /*
  5147. * R3412 (0xD54) - AOD IRQ Mask IRQ2
  5148. */
  5149. #define ARIZONA_IM_GP5_FALL_EINT2 0x0020 /* IM_GP5_FALL_EINT2 */
  5150. #define ARIZONA_IM_GP5_FALL_EINT2_MASK 0x0020 /* IM_GP5_FALL_EINT2 */
  5151. #define ARIZONA_IM_GP5_FALL_EINT2_SHIFT 5 /* IM_GP5_FALL_EINT2 */
  5152. #define ARIZONA_IM_GP5_FALL_EINT2_WIDTH 1 /* IM_GP5_FALL_EINT2 */
  5153. #define ARIZONA_IM_GP5_RISE_EINT2 0x0010 /* IM_GP5_RISE_EINT2 */
  5154. #define ARIZONA_IM_GP5_RISE_EINT2_MASK 0x0010 /* IM_GP5_RISE_EINT2 */
  5155. #define ARIZONA_IM_GP5_RISE_EINT2_SHIFT 4 /* IM_GP5_RISE_EINT2 */
  5156. #define ARIZONA_IM_GP5_RISE_EINT2_WIDTH 1 /* IM_GP5_RISE_EINT2 */
  5157. #define ARIZONA_IM_JD1_FALL_EINT2 0x0008 /* IM_JD1_FALL_EINT2 */
  5158. #define ARIZONA_IM_JD1_FALL_EINT2_MASK 0x0008 /* IM_JD1_FALL_EINT2 */
  5159. #define ARIZONA_IM_JD1_FALL_EINT2_SHIFT 3 /* IM_JD1_FALL_EINT2 */
  5160. #define ARIZONA_IM_JD1_FALL_EINT2_WIDTH 1 /* IM_JD1_FALL_EINT2 */
  5161. #define ARIZONA_IM_JD1_RISE_EINT2 0x0004 /* IM_JD1_RISE_EINT2 */
  5162. #define ARIZONA_IM_JD1_RISE_EINT2_MASK 0x0004 /* IM_JD1_RISE_EINT2 */
  5163. #define ARIZONA_IM_JD1_RISE_EINT2_SHIFT 2 /* IM_JD1_RISE_EINT2 */
  5164. #define ARIZONA_IM_JD1_RISE_EINT2_WIDTH 1 /* IM_JD1_RISE_EINT2 */
  5165. #define ARIZONA_IM_JD2_FALL_EINT2 0x0002 /* IM_JD2_FALL_EINT2 */
  5166. #define ARIZONA_IM_JD2_FALL_EINT2_MASK 0x0002 /* IM_JD2_FALL_EINT2 */
  5167. #define ARIZONA_IM_JD2_FALL_EINT2_SHIFT 1 /* IM_JD2_FALL_EINT2 */
  5168. #define ARIZONA_IM_JD2_FALL_EINT2_WIDTH 1 /* IM_JD2_FALL_EINT2 */
  5169. #define ARIZONA_IM_JD2_RISE_EINT2 0x0001 /* IM_JD2_RISE_EINT2 */
  5170. #define ARIZONA_IM_JD2_RISE_EINT2_MASK 0x0001 /* IM_JD2_RISE_EINT2 */
  5171. #define ARIZONA_IM_JD2_RISE_EINT2_SHIFT 0 /* IM_JD2_RISE_EINT2 */
  5172. #define ARIZONA_IM_JD2_RISE_EINT2_WIDTH 1 /* IM_JD2_RISE_EINT2 */
  5173. /*
  5174. * R3413 (0xD55) - AOD IRQ Raw Status
  5175. */
  5176. #define ARIZONA_MICD_CLAMP_STS 0x0008 /* MICD_CLAMP_STS */
  5177. #define ARIZONA_MICD_CLAMP_STS_MASK 0x0008 /* MICD_CLAMP_STS */
  5178. #define ARIZONA_MICD_CLAMP_STS_SHIFT 3 /* MICD_CLAMP_STS */
  5179. #define ARIZONA_MICD_CLAMP_STS_WIDTH 1 /* MICD_CLAMP_STS */
  5180. #define ARIZONA_GP5_STS 0x0004 /* GP5_STS */
  5181. #define ARIZONA_GP5_STS_MASK 0x0004 /* GP5_STS */
  5182. #define ARIZONA_GP5_STS_SHIFT 2 /* GP5_STS */
  5183. #define ARIZONA_GP5_STS_WIDTH 1 /* GP5_STS */
  5184. #define ARIZONA_JD2_STS 0x0002 /* JD2_STS */
  5185. #define ARIZONA_JD2_STS_MASK 0x0002 /* JD2_STS */
  5186. #define ARIZONA_JD2_STS_SHIFT 1 /* JD2_STS */
  5187. #define ARIZONA_JD2_STS_WIDTH 1 /* JD2_STS */
  5188. #define ARIZONA_JD1_STS 0x0001 /* JD1_STS */
  5189. #define ARIZONA_JD1_STS_MASK 0x0001 /* JD1_STS */
  5190. #define ARIZONA_JD1_STS_SHIFT 0 /* JD1_STS */
  5191. #define ARIZONA_JD1_STS_WIDTH 1 /* JD1_STS */
  5192. /*
  5193. * R3414 (0xD56) - Jack detect debounce
  5194. */
  5195. #define ARIZONA_MICD_CLAMP_DB 0x0008 /* MICD_CLAMP_DB */
  5196. #define ARIZONA_MICD_CLAMP_DB_MASK 0x0008 /* MICD_CLAMP_DB */
  5197. #define ARIZONA_MICD_CLAMP_DB_SHIFT 3 /* MICD_CLAMP_DB */
  5198. #define ARIZONA_MICD_CLAMP_DB_WIDTH 1 /* MICD_CLAMP_DB */
  5199. #define ARIZONA_JD2_DB 0x0002 /* JD2_DB */
  5200. #define ARIZONA_JD2_DB_MASK 0x0002 /* JD2_DB */
  5201. #define ARIZONA_JD2_DB_SHIFT 1 /* JD2_DB */
  5202. #define ARIZONA_JD2_DB_WIDTH 1 /* JD2_DB */
  5203. #define ARIZONA_JD1_DB 0x0001 /* JD1_DB */
  5204. #define ARIZONA_JD1_DB_MASK 0x0001 /* JD1_DB */
  5205. #define ARIZONA_JD1_DB_SHIFT 0 /* JD1_DB */
  5206. #define ARIZONA_JD1_DB_WIDTH 1 /* JD1_DB */
  5207. /*
  5208. * R3584 (0xE00) - FX_Ctrl1
  5209. */
  5210. #define ARIZONA_FX_RATE_MASK 0x7800 /* FX_RATE - [14:11] */
  5211. #define ARIZONA_FX_RATE_SHIFT 11 /* FX_RATE - [14:11] */
  5212. #define ARIZONA_FX_RATE_WIDTH 4 /* FX_RATE - [14:11] */
  5213. /*
  5214. * R3585 (0xE01) - FX_Ctrl2
  5215. */
  5216. #define ARIZONA_FX_STS_MASK 0xFFF0 /* FX_STS - [15:4] */
  5217. #define ARIZONA_FX_STS_SHIFT 4 /* FX_STS - [15:4] */
  5218. #define ARIZONA_FX_STS_WIDTH 12 /* FX_STS - [15:4] */
  5219. /*
  5220. * R3600 (0xE10) - EQ1_1
  5221. */
  5222. #define ARIZONA_EQ1_B1_GAIN_MASK 0xF800 /* EQ1_B1_GAIN - [15:11] */
  5223. #define ARIZONA_EQ1_B1_GAIN_SHIFT 11 /* EQ1_B1_GAIN - [15:11] */
  5224. #define ARIZONA_EQ1_B1_GAIN_WIDTH 5 /* EQ1_B1_GAIN - [15:11] */
  5225. #define ARIZONA_EQ1_B2_GAIN_MASK 0x07C0 /* EQ1_B2_GAIN - [10:6] */
  5226. #define ARIZONA_EQ1_B2_GAIN_SHIFT 6 /* EQ1_B2_GAIN - [10:6] */
  5227. #define ARIZONA_EQ1_B2_GAIN_WIDTH 5 /* EQ1_B2_GAIN - [10:6] */
  5228. #define ARIZONA_EQ1_B3_GAIN_MASK 0x003E /* EQ1_B3_GAIN - [5:1] */
  5229. #define ARIZONA_EQ1_B3_GAIN_SHIFT 1 /* EQ1_B3_GAIN - [5:1] */
  5230. #define ARIZONA_EQ1_B3_GAIN_WIDTH 5 /* EQ1_B3_GAIN - [5:1] */
  5231. #define ARIZONA_EQ1_ENA 0x0001 /* EQ1_ENA */
  5232. #define ARIZONA_EQ1_ENA_MASK 0x0001 /* EQ1_ENA */
  5233. #define ARIZONA_EQ1_ENA_SHIFT 0 /* EQ1_ENA */
  5234. #define ARIZONA_EQ1_ENA_WIDTH 1 /* EQ1_ENA */
  5235. /*
  5236. * R3601 (0xE11) - EQ1_2
  5237. */
  5238. #define ARIZONA_EQ1_B4_GAIN_MASK 0xF800 /* EQ1_B4_GAIN - [15:11] */
  5239. #define ARIZONA_EQ1_B4_GAIN_SHIFT 11 /* EQ1_B4_GAIN - [15:11] */
  5240. #define ARIZONA_EQ1_B4_GAIN_WIDTH 5 /* EQ1_B4_GAIN - [15:11] */
  5241. #define ARIZONA_EQ1_B5_GAIN_MASK 0x07C0 /* EQ1_B5_GAIN - [10:6] */
  5242. #define ARIZONA_EQ1_B5_GAIN_SHIFT 6 /* EQ1_B5_GAIN - [10:6] */
  5243. #define ARIZONA_EQ1_B5_GAIN_WIDTH 5 /* EQ1_B5_GAIN - [10:6] */
  5244. #define ARIZONA_EQ1_B1_MODE 0x0001 /* EQ1_B1_MODE */
  5245. #define ARIZONA_EQ1_B1_MODE_MASK 0x0001 /* EQ1_B1_MODE */
  5246. #define ARIZONA_EQ1_B1_MODE_SHIFT 0 /* EQ1_B1_MODE */
  5247. #define ARIZONA_EQ1_B1_MODE_WIDTH 1 /* EQ1_B1_MODE */
  5248. /*
  5249. * R3602 (0xE12) - EQ1_3
  5250. */
  5251. #define ARIZONA_EQ1_B1_A_MASK 0xFFFF /* EQ1_B1_A - [15:0] */
  5252. #define ARIZONA_EQ1_B1_A_SHIFT 0 /* EQ1_B1_A - [15:0] */
  5253. #define ARIZONA_EQ1_B1_A_WIDTH 16 /* EQ1_B1_A - [15:0] */
  5254. /*
  5255. * R3603 (0xE13) - EQ1_4
  5256. */
  5257. #define ARIZONA_EQ1_B1_B_MASK 0xFFFF /* EQ1_B1_B - [15:0] */
  5258. #define ARIZONA_EQ1_B1_B_SHIFT 0 /* EQ1_B1_B - [15:0] */
  5259. #define ARIZONA_EQ1_B1_B_WIDTH 16 /* EQ1_B1_B - [15:0] */
  5260. /*
  5261. * R3604 (0xE14) - EQ1_5
  5262. */
  5263. #define ARIZONA_EQ1_B1_PG_MASK 0xFFFF /* EQ1_B1_PG - [15:0] */
  5264. #define ARIZONA_EQ1_B1_PG_SHIFT 0 /* EQ1_B1_PG - [15:0] */
  5265. #define ARIZONA_EQ1_B1_PG_WIDTH 16 /* EQ1_B1_PG - [15:0] */
  5266. /*
  5267. * R3605 (0xE15) - EQ1_6
  5268. */
  5269. #define ARIZONA_EQ1_B2_A_MASK 0xFFFF /* EQ1_B2_A - [15:0] */
  5270. #define ARIZONA_EQ1_B2_A_SHIFT 0 /* EQ1_B2_A - [15:0] */
  5271. #define ARIZONA_EQ1_B2_A_WIDTH 16 /* EQ1_B2_A - [15:0] */
  5272. /*
  5273. * R3606 (0xE16) - EQ1_7
  5274. */
  5275. #define ARIZONA_EQ1_B2_B_MASK 0xFFFF /* EQ1_B2_B - [15:0] */
  5276. #define ARIZONA_EQ1_B2_B_SHIFT 0 /* EQ1_B2_B - [15:0] */
  5277. #define ARIZONA_EQ1_B2_B_WIDTH 16 /* EQ1_B2_B - [15:0] */
  5278. /*
  5279. * R3607 (0xE17) - EQ1_8
  5280. */
  5281. #define ARIZONA_EQ1_B2_C_MASK 0xFFFF /* EQ1_B2_C - [15:0] */
  5282. #define ARIZONA_EQ1_B2_C_SHIFT 0 /* EQ1_B2_C - [15:0] */
  5283. #define ARIZONA_EQ1_B2_C_WIDTH 16 /* EQ1_B2_C - [15:0] */
  5284. /*
  5285. * R3608 (0xE18) - EQ1_9
  5286. */
  5287. #define ARIZONA_EQ1_B2_PG_MASK 0xFFFF /* EQ1_B2_PG - [15:0] */
  5288. #define ARIZONA_EQ1_B2_PG_SHIFT 0 /* EQ1_B2_PG - [15:0] */
  5289. #define ARIZONA_EQ1_B2_PG_WIDTH 16 /* EQ1_B2_PG - [15:0] */
  5290. /*
  5291. * R3609 (0xE19) - EQ1_10
  5292. */
  5293. #define ARIZONA_EQ1_B3_A_MASK 0xFFFF /* EQ1_B3_A - [15:0] */
  5294. #define ARIZONA_EQ1_B3_A_SHIFT 0 /* EQ1_B3_A - [15:0] */
  5295. #define ARIZONA_EQ1_B3_A_WIDTH 16 /* EQ1_B3_A - [15:0] */
  5296. /*
  5297. * R3610 (0xE1A) - EQ1_11
  5298. */
  5299. #define ARIZONA_EQ1_B3_B_MASK 0xFFFF /* EQ1_B3_B - [15:0] */
  5300. #define ARIZONA_EQ1_B3_B_SHIFT 0 /* EQ1_B3_B - [15:0] */
  5301. #define ARIZONA_EQ1_B3_B_WIDTH 16 /* EQ1_B3_B - [15:0] */
  5302. /*
  5303. * R3611 (0xE1B) - EQ1_12
  5304. */
  5305. #define ARIZONA_EQ1_B3_C_MASK 0xFFFF /* EQ1_B3_C - [15:0] */
  5306. #define ARIZONA_EQ1_B3_C_SHIFT 0 /* EQ1_B3_C - [15:0] */
  5307. #define ARIZONA_EQ1_B3_C_WIDTH 16 /* EQ1_B3_C - [15:0] */
  5308. /*
  5309. * R3612 (0xE1C) - EQ1_13
  5310. */
  5311. #define ARIZONA_EQ1_B3_PG_MASK 0xFFFF /* EQ1_B3_PG - [15:0] */
  5312. #define ARIZONA_EQ1_B3_PG_SHIFT 0 /* EQ1_B3_PG - [15:0] */
  5313. #define ARIZONA_EQ1_B3_PG_WIDTH 16 /* EQ1_B3_PG - [15:0] */
  5314. /*
  5315. * R3613 (0xE1D) - EQ1_14
  5316. */
  5317. #define ARIZONA_EQ1_B4_A_MASK 0xFFFF /* EQ1_B4_A - [15:0] */
  5318. #define ARIZONA_EQ1_B4_A_SHIFT 0 /* EQ1_B4_A - [15:0] */
  5319. #define ARIZONA_EQ1_B4_A_WIDTH 16 /* EQ1_B4_A - [15:0] */
  5320. /*
  5321. * R3614 (0xE1E) - EQ1_15
  5322. */
  5323. #define ARIZONA_EQ1_B4_B_MASK 0xFFFF /* EQ1_B4_B - [15:0] */
  5324. #define ARIZONA_EQ1_B4_B_SHIFT 0 /* EQ1_B4_B - [15:0] */
  5325. #define ARIZONA_EQ1_B4_B_WIDTH 16 /* EQ1_B4_B - [15:0] */
  5326. /*
  5327. * R3615 (0xE1F) - EQ1_16
  5328. */
  5329. #define ARIZONA_EQ1_B4_C_MASK 0xFFFF /* EQ1_B4_C - [15:0] */
  5330. #define ARIZONA_EQ1_B4_C_SHIFT 0 /* EQ1_B4_C - [15:0] */
  5331. #define ARIZONA_EQ1_B4_C_WIDTH 16 /* EQ1_B4_C - [15:0] */
  5332. /*
  5333. * R3616 (0xE20) - EQ1_17
  5334. */
  5335. #define ARIZONA_EQ1_B4_PG_MASK 0xFFFF /* EQ1_B4_PG - [15:0] */
  5336. #define ARIZONA_EQ1_B4_PG_SHIFT 0 /* EQ1_B4_PG - [15:0] */
  5337. #define ARIZONA_EQ1_B4_PG_WIDTH 16 /* EQ1_B4_PG - [15:0] */
  5338. /*
  5339. * R3617 (0xE21) - EQ1_18
  5340. */
  5341. #define ARIZONA_EQ1_B5_A_MASK 0xFFFF /* EQ1_B5_A - [15:0] */
  5342. #define ARIZONA_EQ1_B5_A_SHIFT 0 /* EQ1_B5_A - [15:0] */
  5343. #define ARIZONA_EQ1_B5_A_WIDTH 16 /* EQ1_B5_A - [15:0] */
  5344. /*
  5345. * R3618 (0xE22) - EQ1_19
  5346. */
  5347. #define ARIZONA_EQ1_B5_B_MASK 0xFFFF /* EQ1_B5_B - [15:0] */
  5348. #define ARIZONA_EQ1_B5_B_SHIFT 0 /* EQ1_B5_B - [15:0] */
  5349. #define ARIZONA_EQ1_B5_B_WIDTH 16 /* EQ1_B5_B - [15:0] */
  5350. /*
  5351. * R3619 (0xE23) - EQ1_20
  5352. */
  5353. #define ARIZONA_EQ1_B5_PG_MASK 0xFFFF /* EQ1_B5_PG - [15:0] */
  5354. #define ARIZONA_EQ1_B5_PG_SHIFT 0 /* EQ1_B5_PG - [15:0] */
  5355. #define ARIZONA_EQ1_B5_PG_WIDTH 16 /* EQ1_B5_PG - [15:0] */
  5356. /*
  5357. * R3620 (0xE24) - EQ1_21
  5358. */
  5359. #define ARIZONA_EQ1_B1_C_MASK 0xFFFF /* EQ1_B1_C - [15:0] */
  5360. #define ARIZONA_EQ1_B1_C_SHIFT 0 /* EQ1_B1_C - [15:0] */
  5361. #define ARIZONA_EQ1_B1_C_WIDTH 16 /* EQ1_B1_C - [15:0] */
  5362. /*
  5363. * R3622 (0xE26) - EQ2_1
  5364. */
  5365. #define ARIZONA_EQ2_B1_GAIN_MASK 0xF800 /* EQ2_B1_GAIN - [15:11] */
  5366. #define ARIZONA_EQ2_B1_GAIN_SHIFT 11 /* EQ2_B1_GAIN - [15:11] */
  5367. #define ARIZONA_EQ2_B1_GAIN_WIDTH 5 /* EQ2_B1_GAIN - [15:11] */
  5368. #define ARIZONA_EQ2_B2_GAIN_MASK 0x07C0 /* EQ2_B2_GAIN - [10:6] */
  5369. #define ARIZONA_EQ2_B2_GAIN_SHIFT 6 /* EQ2_B2_GAIN - [10:6] */
  5370. #define ARIZONA_EQ2_B2_GAIN_WIDTH 5 /* EQ2_B2_GAIN - [10:6] */
  5371. #define ARIZONA_EQ2_B3_GAIN_MASK 0x003E /* EQ2_B3_GAIN - [5:1] */
  5372. #define ARIZONA_EQ2_B3_GAIN_SHIFT 1 /* EQ2_B3_GAIN - [5:1] */
  5373. #define ARIZONA_EQ2_B3_GAIN_WIDTH 5 /* EQ2_B3_GAIN - [5:1] */
  5374. #define ARIZONA_EQ2_ENA 0x0001 /* EQ2_ENA */
  5375. #define ARIZONA_EQ2_ENA_MASK 0x0001 /* EQ2_ENA */
  5376. #define ARIZONA_EQ2_ENA_SHIFT 0 /* EQ2_ENA */
  5377. #define ARIZONA_EQ2_ENA_WIDTH 1 /* EQ2_ENA */
  5378. /*
  5379. * R3623 (0xE27) - EQ2_2
  5380. */
  5381. #define ARIZONA_EQ2_B4_GAIN_MASK 0xF800 /* EQ2_B4_GAIN - [15:11] */
  5382. #define ARIZONA_EQ2_B4_GAIN_SHIFT 11 /* EQ2_B4_GAIN - [15:11] */
  5383. #define ARIZONA_EQ2_B4_GAIN_WIDTH 5 /* EQ2_B4_GAIN - [15:11] */
  5384. #define ARIZONA_EQ2_B5_GAIN_MASK 0x07C0 /* EQ2_B5_GAIN - [10:6] */
  5385. #define ARIZONA_EQ2_B5_GAIN_SHIFT 6 /* EQ2_B5_GAIN - [10:6] */
  5386. #define ARIZONA_EQ2_B5_GAIN_WIDTH 5 /* EQ2_B5_GAIN - [10:6] */
  5387. #define ARIZONA_EQ2_B1_MODE 0x0001 /* EQ2_B1_MODE */
  5388. #define ARIZONA_EQ2_B1_MODE_MASK 0x0001 /* EQ2_B1_MODE */
  5389. #define ARIZONA_EQ2_B1_MODE_SHIFT 0 /* EQ2_B1_MODE */
  5390. #define ARIZONA_EQ2_B1_MODE_WIDTH 1 /* EQ2_B1_MODE */
  5391. /*
  5392. * R3624 (0xE28) - EQ2_3
  5393. */
  5394. #define ARIZONA_EQ2_B1_A_MASK 0xFFFF /* EQ2_B1_A - [15:0] */
  5395. #define ARIZONA_EQ2_B1_A_SHIFT 0 /* EQ2_B1_A - [15:0] */
  5396. #define ARIZONA_EQ2_B1_A_WIDTH 16 /* EQ2_B1_A - [15:0] */
  5397. /*
  5398. * R3625 (0xE29) - EQ2_4
  5399. */
  5400. #define ARIZONA_EQ2_B1_B_MASK 0xFFFF /* EQ2_B1_B - [15:0] */
  5401. #define ARIZONA_EQ2_B1_B_SHIFT 0 /* EQ2_B1_B - [15:0] */
  5402. #define ARIZONA_EQ2_B1_B_WIDTH 16 /* EQ2_B1_B - [15:0] */
  5403. /*
  5404. * R3626 (0xE2A) - EQ2_5
  5405. */
  5406. #define ARIZONA_EQ2_B1_PG_MASK 0xFFFF /* EQ2_B1_PG - [15:0] */
  5407. #define ARIZONA_EQ2_B1_PG_SHIFT 0 /* EQ2_B1_PG - [15:0] */
  5408. #define ARIZONA_EQ2_B1_PG_WIDTH 16 /* EQ2_B1_PG - [15:0] */
  5409. /*
  5410. * R3627 (0xE2B) - EQ2_6
  5411. */
  5412. #define ARIZONA_EQ2_B2_A_MASK 0xFFFF /* EQ2_B2_A - [15:0] */
  5413. #define ARIZONA_EQ2_B2_A_SHIFT 0 /* EQ2_B2_A - [15:0] */
  5414. #define ARIZONA_EQ2_B2_A_WIDTH 16 /* EQ2_B2_A - [15:0] */
  5415. /*
  5416. * R3628 (0xE2C) - EQ2_7
  5417. */
  5418. #define ARIZONA_EQ2_B2_B_MASK 0xFFFF /* EQ2_B2_B - [15:0] */
  5419. #define ARIZONA_EQ2_B2_B_SHIFT 0 /* EQ2_B2_B - [15:0] */
  5420. #define ARIZONA_EQ2_B2_B_WIDTH 16 /* EQ2_B2_B - [15:0] */
  5421. /*
  5422. * R3629 (0xE2D) - EQ2_8
  5423. */
  5424. #define ARIZONA_EQ2_B2_C_MASK 0xFFFF /* EQ2_B2_C - [15:0] */
  5425. #define ARIZONA_EQ2_B2_C_SHIFT 0 /* EQ2_B2_C - [15:0] */
  5426. #define ARIZONA_EQ2_B2_C_WIDTH 16 /* EQ2_B2_C - [15:0] */
  5427. /*
  5428. * R3630 (0xE2E) - EQ2_9
  5429. */
  5430. #define ARIZONA_EQ2_B2_PG_MASK 0xFFFF /* EQ2_B2_PG - [15:0] */
  5431. #define ARIZONA_EQ2_B2_PG_SHIFT 0 /* EQ2_B2_PG - [15:0] */
  5432. #define ARIZONA_EQ2_B2_PG_WIDTH 16 /* EQ2_B2_PG - [15:0] */
  5433. /*
  5434. * R3631 (0xE2F) - EQ2_10
  5435. */
  5436. #define ARIZONA_EQ2_B3_A_MASK 0xFFFF /* EQ2_B3_A - [15:0] */
  5437. #define ARIZONA_EQ2_B3_A_SHIFT 0 /* EQ2_B3_A - [15:0] */
  5438. #define ARIZONA_EQ2_B3_A_WIDTH 16 /* EQ2_B3_A - [15:0] */
  5439. /*
  5440. * R3632 (0xE30) - EQ2_11
  5441. */
  5442. #define ARIZONA_EQ2_B3_B_MASK 0xFFFF /* EQ2_B3_B - [15:0] */
  5443. #define ARIZONA_EQ2_B3_B_SHIFT 0 /* EQ2_B3_B - [15:0] */
  5444. #define ARIZONA_EQ2_B3_B_WIDTH 16 /* EQ2_B3_B - [15:0] */
  5445. /*
  5446. * R3633 (0xE31) - EQ2_12
  5447. */
  5448. #define ARIZONA_EQ2_B3_C_MASK 0xFFFF /* EQ2_B3_C - [15:0] */
  5449. #define ARIZONA_EQ2_B3_C_SHIFT 0 /* EQ2_B3_C - [15:0] */
  5450. #define ARIZONA_EQ2_B3_C_WIDTH 16 /* EQ2_B3_C - [15:0] */
  5451. /*
  5452. * R3634 (0xE32) - EQ2_13
  5453. */
  5454. #define ARIZONA_EQ2_B3_PG_MASK 0xFFFF /* EQ2_B3_PG - [15:0] */
  5455. #define ARIZONA_EQ2_B3_PG_SHIFT 0 /* EQ2_B3_PG - [15:0] */
  5456. #define ARIZONA_EQ2_B3_PG_WIDTH 16 /* EQ2_B3_PG - [15:0] */
  5457. /*
  5458. * R3635 (0xE33) - EQ2_14
  5459. */
  5460. #define ARIZONA_EQ2_B4_A_MASK 0xFFFF /* EQ2_B4_A - [15:0] */
  5461. #define ARIZONA_EQ2_B4_A_SHIFT 0 /* EQ2_B4_A - [15:0] */
  5462. #define ARIZONA_EQ2_B4_A_WIDTH 16 /* EQ2_B4_A - [15:0] */
  5463. /*
  5464. * R3636 (0xE34) - EQ2_15
  5465. */
  5466. #define ARIZONA_EQ2_B4_B_MASK 0xFFFF /* EQ2_B4_B - [15:0] */
  5467. #define ARIZONA_EQ2_B4_B_SHIFT 0 /* EQ2_B4_B - [15:0] */
  5468. #define ARIZONA_EQ2_B4_B_WIDTH 16 /* EQ2_B4_B - [15:0] */
  5469. /*
  5470. * R3637 (0xE35) - EQ2_16
  5471. */
  5472. #define ARIZONA_EQ2_B4_C_MASK 0xFFFF /* EQ2_B4_C - [15:0] */
  5473. #define ARIZONA_EQ2_B4_C_SHIFT 0 /* EQ2_B4_C - [15:0] */
  5474. #define ARIZONA_EQ2_B4_C_WIDTH 16 /* EQ2_B4_C - [15:0] */
  5475. /*
  5476. * R3638 (0xE36) - EQ2_17
  5477. */
  5478. #define ARIZONA_EQ2_B4_PG_MASK 0xFFFF /* EQ2_B4_PG - [15:0] */
  5479. #define ARIZONA_EQ2_B4_PG_SHIFT 0 /* EQ2_B4_PG - [15:0] */
  5480. #define ARIZONA_EQ2_B4_PG_WIDTH 16 /* EQ2_B4_PG - [15:0] */
  5481. /*
  5482. * R3639 (0xE37) - EQ2_18
  5483. */
  5484. #define ARIZONA_EQ2_B5_A_MASK 0xFFFF /* EQ2_B5_A - [15:0] */
  5485. #define ARIZONA_EQ2_B5_A_SHIFT 0 /* EQ2_B5_A - [15:0] */
  5486. #define ARIZONA_EQ2_B5_A_WIDTH 16 /* EQ2_B5_A - [15:0] */
  5487. /*
  5488. * R3640 (0xE38) - EQ2_19
  5489. */
  5490. #define ARIZONA_EQ2_B5_B_MASK 0xFFFF /* EQ2_B5_B - [15:0] */
  5491. #define ARIZONA_EQ2_B5_B_SHIFT 0 /* EQ2_B5_B - [15:0] */
  5492. #define ARIZONA_EQ2_B5_B_WIDTH 16 /* EQ2_B5_B - [15:0] */
  5493. /*
  5494. * R3641 (0xE39) - EQ2_20
  5495. */
  5496. #define ARIZONA_EQ2_B5_PG_MASK 0xFFFF /* EQ2_B5_PG - [15:0] */
  5497. #define ARIZONA_EQ2_B5_PG_SHIFT 0 /* EQ2_B5_PG - [15:0] */
  5498. #define ARIZONA_EQ2_B5_PG_WIDTH 16 /* EQ2_B5_PG - [15:0] */
  5499. /*
  5500. * R3642 (0xE3A) - EQ2_21
  5501. */
  5502. #define ARIZONA_EQ2_B1_C_MASK 0xFFFF /* EQ2_B1_C - [15:0] */
  5503. #define ARIZONA_EQ2_B1_C_SHIFT 0 /* EQ2_B1_C - [15:0] */
  5504. #define ARIZONA_EQ2_B1_C_WIDTH 16 /* EQ2_B1_C - [15:0] */
  5505. /*
  5506. * R3644 (0xE3C) - EQ3_1
  5507. */
  5508. #define ARIZONA_EQ3_B1_GAIN_MASK 0xF800 /* EQ3_B1_GAIN - [15:11] */
  5509. #define ARIZONA_EQ3_B1_GAIN_SHIFT 11 /* EQ3_B1_GAIN - [15:11] */
  5510. #define ARIZONA_EQ3_B1_GAIN_WIDTH 5 /* EQ3_B1_GAIN - [15:11] */
  5511. #define ARIZONA_EQ3_B2_GAIN_MASK 0x07C0 /* EQ3_B2_GAIN - [10:6] */
  5512. #define ARIZONA_EQ3_B2_GAIN_SHIFT 6 /* EQ3_B2_GAIN - [10:6] */
  5513. #define ARIZONA_EQ3_B2_GAIN_WIDTH 5 /* EQ3_B2_GAIN - [10:6] */
  5514. #define ARIZONA_EQ3_B3_GAIN_MASK 0x003E /* EQ3_B3_GAIN - [5:1] */
  5515. #define ARIZONA_EQ3_B3_GAIN_SHIFT 1 /* EQ3_B3_GAIN - [5:1] */
  5516. #define ARIZONA_EQ3_B3_GAIN_WIDTH 5 /* EQ3_B3_GAIN - [5:1] */
  5517. #define ARIZONA_EQ3_ENA 0x0001 /* EQ3_ENA */
  5518. #define ARIZONA_EQ3_ENA_MASK 0x0001 /* EQ3_ENA */
  5519. #define ARIZONA_EQ3_ENA_SHIFT 0 /* EQ3_ENA */
  5520. #define ARIZONA_EQ3_ENA_WIDTH 1 /* EQ3_ENA */
  5521. /*
  5522. * R3645 (0xE3D) - EQ3_2
  5523. */
  5524. #define ARIZONA_EQ3_B4_GAIN_MASK 0xF800 /* EQ3_B4_GAIN - [15:11] */
  5525. #define ARIZONA_EQ3_B4_GAIN_SHIFT 11 /* EQ3_B4_GAIN - [15:11] */
  5526. #define ARIZONA_EQ3_B4_GAIN_WIDTH 5 /* EQ3_B4_GAIN - [15:11] */
  5527. #define ARIZONA_EQ3_B5_GAIN_MASK 0x07C0 /* EQ3_B5_GAIN - [10:6] */
  5528. #define ARIZONA_EQ3_B5_GAIN_SHIFT 6 /* EQ3_B5_GAIN - [10:6] */
  5529. #define ARIZONA_EQ3_B5_GAIN_WIDTH 5 /* EQ3_B5_GAIN - [10:6] */
  5530. #define ARIZONA_EQ3_B1_MODE 0x0001 /* EQ3_B1_MODE */
  5531. #define ARIZONA_EQ3_B1_MODE_MASK 0x0001 /* EQ3_B1_MODE */
  5532. #define ARIZONA_EQ3_B1_MODE_SHIFT 0 /* EQ3_B1_MODE */
  5533. #define ARIZONA_EQ3_B1_MODE_WIDTH 1 /* EQ3_B1_MODE */
  5534. /*
  5535. * R3646 (0xE3E) - EQ3_3
  5536. */
  5537. #define ARIZONA_EQ3_B1_A_MASK 0xFFFF /* EQ3_B1_A - [15:0] */
  5538. #define ARIZONA_EQ3_B1_A_SHIFT 0 /* EQ3_B1_A - [15:0] */
  5539. #define ARIZONA_EQ3_B1_A_WIDTH 16 /* EQ3_B1_A - [15:0] */
  5540. /*
  5541. * R3647 (0xE3F) - EQ3_4
  5542. */
  5543. #define ARIZONA_EQ3_B1_B_MASK 0xFFFF /* EQ3_B1_B - [15:0] */
  5544. #define ARIZONA_EQ3_B1_B_SHIFT 0 /* EQ3_B1_B - [15:0] */
  5545. #define ARIZONA_EQ3_B1_B_WIDTH 16 /* EQ3_B1_B - [15:0] */
  5546. /*
  5547. * R3648 (0xE40) - EQ3_5
  5548. */
  5549. #define ARIZONA_EQ3_B1_PG_MASK 0xFFFF /* EQ3_B1_PG - [15:0] */
  5550. #define ARIZONA_EQ3_B1_PG_SHIFT 0 /* EQ3_B1_PG - [15:0] */
  5551. #define ARIZONA_EQ3_B1_PG_WIDTH 16 /* EQ3_B1_PG - [15:0] */
  5552. /*
  5553. * R3649 (0xE41) - EQ3_6
  5554. */
  5555. #define ARIZONA_EQ3_B2_A_MASK 0xFFFF /* EQ3_B2_A - [15:0] */
  5556. #define ARIZONA_EQ3_B2_A_SHIFT 0 /* EQ3_B2_A - [15:0] */
  5557. #define ARIZONA_EQ3_B2_A_WIDTH 16 /* EQ3_B2_A - [15:0] */
  5558. /*
  5559. * R3650 (0xE42) - EQ3_7
  5560. */
  5561. #define ARIZONA_EQ3_B2_B_MASK 0xFFFF /* EQ3_B2_B - [15:0] */
  5562. #define ARIZONA_EQ3_B2_B_SHIFT 0 /* EQ3_B2_B - [15:0] */
  5563. #define ARIZONA_EQ3_B2_B_WIDTH 16 /* EQ3_B2_B - [15:0] */
  5564. /*
  5565. * R3651 (0xE43) - EQ3_8
  5566. */
  5567. #define ARIZONA_EQ3_B2_C_MASK 0xFFFF /* EQ3_B2_C - [15:0] */
  5568. #define ARIZONA_EQ3_B2_C_SHIFT 0 /* EQ3_B2_C - [15:0] */
  5569. #define ARIZONA_EQ3_B2_C_WIDTH 16 /* EQ3_B2_C - [15:0] */
  5570. /*
  5571. * R3652 (0xE44) - EQ3_9
  5572. */
  5573. #define ARIZONA_EQ3_B2_PG_MASK 0xFFFF /* EQ3_B2_PG - [15:0] */
  5574. #define ARIZONA_EQ3_B2_PG_SHIFT 0 /* EQ3_B2_PG - [15:0] */
  5575. #define ARIZONA_EQ3_B2_PG_WIDTH 16 /* EQ3_B2_PG - [15:0] */
  5576. /*
  5577. * R3653 (0xE45) - EQ3_10
  5578. */
  5579. #define ARIZONA_EQ3_B3_A_MASK 0xFFFF /* EQ3_B3_A - [15:0] */
  5580. #define ARIZONA_EQ3_B3_A_SHIFT 0 /* EQ3_B3_A - [15:0] */
  5581. #define ARIZONA_EQ3_B3_A_WIDTH 16 /* EQ3_B3_A - [15:0] */
  5582. /*
  5583. * R3654 (0xE46) - EQ3_11
  5584. */
  5585. #define ARIZONA_EQ3_B3_B_MASK 0xFFFF /* EQ3_B3_B - [15:0] */
  5586. #define ARIZONA_EQ3_B3_B_SHIFT 0 /* EQ3_B3_B - [15:0] */
  5587. #define ARIZONA_EQ3_B3_B_WIDTH 16 /* EQ3_B3_B - [15:0] */
  5588. /*
  5589. * R3655 (0xE47) - EQ3_12
  5590. */
  5591. #define ARIZONA_EQ3_B3_C_MASK 0xFFFF /* EQ3_B3_C - [15:0] */
  5592. #define ARIZONA_EQ3_B3_C_SHIFT 0 /* EQ3_B3_C - [15:0] */
  5593. #define ARIZONA_EQ3_B3_C_WIDTH 16 /* EQ3_B3_C - [15:0] */
  5594. /*
  5595. * R3656 (0xE48) - EQ3_13
  5596. */
  5597. #define ARIZONA_EQ3_B3_PG_MASK 0xFFFF /* EQ3_B3_PG - [15:0] */
  5598. #define ARIZONA_EQ3_B3_PG_SHIFT 0 /* EQ3_B3_PG - [15:0] */
  5599. #define ARIZONA_EQ3_B3_PG_WIDTH 16 /* EQ3_B3_PG - [15:0] */
  5600. /*
  5601. * R3657 (0xE49) - EQ3_14
  5602. */
  5603. #define ARIZONA_EQ3_B4_A_MASK 0xFFFF /* EQ3_B4_A - [15:0] */
  5604. #define ARIZONA_EQ3_B4_A_SHIFT 0 /* EQ3_B4_A - [15:0] */
  5605. #define ARIZONA_EQ3_B4_A_WIDTH 16 /* EQ3_B4_A - [15:0] */
  5606. /*
  5607. * R3658 (0xE4A) - EQ3_15
  5608. */
  5609. #define ARIZONA_EQ3_B4_B_MASK 0xFFFF /* EQ3_B4_B - [15:0] */
  5610. #define ARIZONA_EQ3_B4_B_SHIFT 0 /* EQ3_B4_B - [15:0] */
  5611. #define ARIZONA_EQ3_B4_B_WIDTH 16 /* EQ3_B4_B - [15:0] */
  5612. /*
  5613. * R3659 (0xE4B) - EQ3_16
  5614. */
  5615. #define ARIZONA_EQ3_B4_C_MASK 0xFFFF /* EQ3_B4_C - [15:0] */
  5616. #define ARIZONA_EQ3_B4_C_SHIFT 0 /* EQ3_B4_C - [15:0] */
  5617. #define ARIZONA_EQ3_B4_C_WIDTH 16 /* EQ3_B4_C - [15:0] */
  5618. /*
  5619. * R3660 (0xE4C) - EQ3_17
  5620. */
  5621. #define ARIZONA_EQ3_B4_PG_MASK 0xFFFF /* EQ3_B4_PG - [15:0] */
  5622. #define ARIZONA_EQ3_B4_PG_SHIFT 0 /* EQ3_B4_PG - [15:0] */
  5623. #define ARIZONA_EQ3_B4_PG_WIDTH 16 /* EQ3_B4_PG - [15:0] */
  5624. /*
  5625. * R3661 (0xE4D) - EQ3_18
  5626. */
  5627. #define ARIZONA_EQ3_B5_A_MASK 0xFFFF /* EQ3_B5_A - [15:0] */
  5628. #define ARIZONA_EQ3_B5_A_SHIFT 0 /* EQ3_B5_A - [15:0] */
  5629. #define ARIZONA_EQ3_B5_A_WIDTH 16 /* EQ3_B5_A - [15:0] */
  5630. /*
  5631. * R3662 (0xE4E) - EQ3_19
  5632. */
  5633. #define ARIZONA_EQ3_B5_B_MASK 0xFFFF /* EQ3_B5_B - [15:0] */
  5634. #define ARIZONA_EQ3_B5_B_SHIFT 0 /* EQ3_B5_B - [15:0] */
  5635. #define ARIZONA_EQ3_B5_B_WIDTH 16 /* EQ3_B5_B - [15:0] */
  5636. /*
  5637. * R3663 (0xE4F) - EQ3_20
  5638. */
  5639. #define ARIZONA_EQ3_B5_PG_MASK 0xFFFF /* EQ3_B5_PG - [15:0] */
  5640. #define ARIZONA_EQ3_B5_PG_SHIFT 0 /* EQ3_B5_PG - [15:0] */
  5641. #define ARIZONA_EQ3_B5_PG_WIDTH 16 /* EQ3_B5_PG - [15:0] */
  5642. /*
  5643. * R3664 (0xE50) - EQ3_21
  5644. */
  5645. #define ARIZONA_EQ3_B1_C_MASK 0xFFFF /* EQ3_B1_C - [15:0] */
  5646. #define ARIZONA_EQ3_B1_C_SHIFT 0 /* EQ3_B1_C - [15:0] */
  5647. #define ARIZONA_EQ3_B1_C_WIDTH 16 /* EQ3_B1_C - [15:0] */
  5648. /*
  5649. * R3666 (0xE52) - EQ4_1
  5650. */
  5651. #define ARIZONA_EQ4_B1_GAIN_MASK 0xF800 /* EQ4_B1_GAIN - [15:11] */
  5652. #define ARIZONA_EQ4_B1_GAIN_SHIFT 11 /* EQ4_B1_GAIN - [15:11] */
  5653. #define ARIZONA_EQ4_B1_GAIN_WIDTH 5 /* EQ4_B1_GAIN - [15:11] */
  5654. #define ARIZONA_EQ4_B2_GAIN_MASK 0x07C0 /* EQ4_B2_GAIN - [10:6] */
  5655. #define ARIZONA_EQ4_B2_GAIN_SHIFT 6 /* EQ4_B2_GAIN - [10:6] */
  5656. #define ARIZONA_EQ4_B2_GAIN_WIDTH 5 /* EQ4_B2_GAIN - [10:6] */
  5657. #define ARIZONA_EQ4_B3_GAIN_MASK 0x003E /* EQ4_B3_GAIN - [5:1] */
  5658. #define ARIZONA_EQ4_B3_GAIN_SHIFT 1 /* EQ4_B3_GAIN - [5:1] */
  5659. #define ARIZONA_EQ4_B3_GAIN_WIDTH 5 /* EQ4_B3_GAIN - [5:1] */
  5660. #define ARIZONA_EQ4_ENA 0x0001 /* EQ4_ENA */
  5661. #define ARIZONA_EQ4_ENA_MASK 0x0001 /* EQ4_ENA */
  5662. #define ARIZONA_EQ4_ENA_SHIFT 0 /* EQ4_ENA */
  5663. #define ARIZONA_EQ4_ENA_WIDTH 1 /* EQ4_ENA */
  5664. /*
  5665. * R3667 (0xE53) - EQ4_2
  5666. */
  5667. #define ARIZONA_EQ4_B4_GAIN_MASK 0xF800 /* EQ4_B4_GAIN - [15:11] */
  5668. #define ARIZONA_EQ4_B4_GAIN_SHIFT 11 /* EQ4_B4_GAIN - [15:11] */
  5669. #define ARIZONA_EQ4_B4_GAIN_WIDTH 5 /* EQ4_B4_GAIN - [15:11] */
  5670. #define ARIZONA_EQ4_B5_GAIN_MASK 0x07C0 /* EQ4_B5_GAIN - [10:6] */
  5671. #define ARIZONA_EQ4_B5_GAIN_SHIFT 6 /* EQ4_B5_GAIN - [10:6] */
  5672. #define ARIZONA_EQ4_B5_GAIN_WIDTH 5 /* EQ4_B5_GAIN - [10:6] */
  5673. #define ARIZONA_EQ4_B1_MODE 0x0001 /* EQ4_B1_MODE */
  5674. #define ARIZONA_EQ4_B1_MODE_MASK 0x0001 /* EQ4_B1_MODE */
  5675. #define ARIZONA_EQ4_B1_MODE_SHIFT 0 /* EQ4_B1_MODE */
  5676. #define ARIZONA_EQ4_B1_MODE_WIDTH 1 /* EQ4_B1_MODE */
  5677. /*
  5678. * R3668 (0xE54) - EQ4_3
  5679. */
  5680. #define ARIZONA_EQ4_B1_A_MASK 0xFFFF /* EQ4_B1_A - [15:0] */
  5681. #define ARIZONA_EQ4_B1_A_SHIFT 0 /* EQ4_B1_A - [15:0] */
  5682. #define ARIZONA_EQ4_B1_A_WIDTH 16 /* EQ4_B1_A - [15:0] */
  5683. /*
  5684. * R3669 (0xE55) - EQ4_4
  5685. */
  5686. #define ARIZONA_EQ4_B1_B_MASK 0xFFFF /* EQ4_B1_B - [15:0] */
  5687. #define ARIZONA_EQ4_B1_B_SHIFT 0 /* EQ4_B1_B - [15:0] */
  5688. #define ARIZONA_EQ4_B1_B_WIDTH 16 /* EQ4_B1_B - [15:0] */
  5689. /*
  5690. * R3670 (0xE56) - EQ4_5
  5691. */
  5692. #define ARIZONA_EQ4_B1_PG_MASK 0xFFFF /* EQ4_B1_PG - [15:0] */
  5693. #define ARIZONA_EQ4_B1_PG_SHIFT 0 /* EQ4_B1_PG - [15:0] */
  5694. #define ARIZONA_EQ4_B1_PG_WIDTH 16 /* EQ4_B1_PG - [15:0] */
  5695. /*
  5696. * R3671 (0xE57) - EQ4_6
  5697. */
  5698. #define ARIZONA_EQ4_B2_A_MASK 0xFFFF /* EQ4_B2_A - [15:0] */
  5699. #define ARIZONA_EQ4_B2_A_SHIFT 0 /* EQ4_B2_A - [15:0] */
  5700. #define ARIZONA_EQ4_B2_A_WIDTH 16 /* EQ4_B2_A - [15:0] */
  5701. /*
  5702. * R3672 (0xE58) - EQ4_7
  5703. */
  5704. #define ARIZONA_EQ4_B2_B_MASK 0xFFFF /* EQ4_B2_B - [15:0] */
  5705. #define ARIZONA_EQ4_B2_B_SHIFT 0 /* EQ4_B2_B - [15:0] */
  5706. #define ARIZONA_EQ4_B2_B_WIDTH 16 /* EQ4_B2_B - [15:0] */
  5707. /*
  5708. * R3673 (0xE59) - EQ4_8
  5709. */
  5710. #define ARIZONA_EQ4_B2_C_MASK 0xFFFF /* EQ4_B2_C - [15:0] */
  5711. #define ARIZONA_EQ4_B2_C_SHIFT 0 /* EQ4_B2_C - [15:0] */
  5712. #define ARIZONA_EQ4_B2_C_WIDTH 16 /* EQ4_B2_C - [15:0] */
  5713. /*
  5714. * R3674 (0xE5A) - EQ4_9
  5715. */
  5716. #define ARIZONA_EQ4_B2_PG_MASK 0xFFFF /* EQ4_B2_PG - [15:0] */
  5717. #define ARIZONA_EQ4_B2_PG_SHIFT 0 /* EQ4_B2_PG - [15:0] */
  5718. #define ARIZONA_EQ4_B2_PG_WIDTH 16 /* EQ4_B2_PG - [15:0] */
  5719. /*
  5720. * R3675 (0xE5B) - EQ4_10
  5721. */
  5722. #define ARIZONA_EQ4_B3_A_MASK 0xFFFF /* EQ4_B3_A - [15:0] */
  5723. #define ARIZONA_EQ4_B3_A_SHIFT 0 /* EQ4_B3_A - [15:0] */
  5724. #define ARIZONA_EQ4_B3_A_WIDTH 16 /* EQ4_B3_A - [15:0] */
  5725. /*
  5726. * R3676 (0xE5C) - EQ4_11
  5727. */
  5728. #define ARIZONA_EQ4_B3_B_MASK 0xFFFF /* EQ4_B3_B - [15:0] */
  5729. #define ARIZONA_EQ4_B3_B_SHIFT 0 /* EQ4_B3_B - [15:0] */
  5730. #define ARIZONA_EQ4_B3_B_WIDTH 16 /* EQ4_B3_B - [15:0] */
  5731. /*
  5732. * R3677 (0xE5D) - EQ4_12
  5733. */
  5734. #define ARIZONA_EQ4_B3_C_MASK 0xFFFF /* EQ4_B3_C - [15:0] */
  5735. #define ARIZONA_EQ4_B3_C_SHIFT 0 /* EQ4_B3_C - [15:0] */
  5736. #define ARIZONA_EQ4_B3_C_WIDTH 16 /* EQ4_B3_C - [15:0] */
  5737. /*
  5738. * R3678 (0xE5E) - EQ4_13
  5739. */
  5740. #define ARIZONA_EQ4_B3_PG_MASK 0xFFFF /* EQ4_B3_PG - [15:0] */
  5741. #define ARIZONA_EQ4_B3_PG_SHIFT 0 /* EQ4_B3_PG - [15:0] */
  5742. #define ARIZONA_EQ4_B3_PG_WIDTH 16 /* EQ4_B3_PG - [15:0] */
  5743. /*
  5744. * R3679 (0xE5F) - EQ4_14
  5745. */
  5746. #define ARIZONA_EQ4_B4_A_MASK 0xFFFF /* EQ4_B4_A - [15:0] */
  5747. #define ARIZONA_EQ4_B4_A_SHIFT 0 /* EQ4_B4_A - [15:0] */
  5748. #define ARIZONA_EQ4_B4_A_WIDTH 16 /* EQ4_B4_A - [15:0] */
  5749. /*
  5750. * R3680 (0xE60) - EQ4_15
  5751. */
  5752. #define ARIZONA_EQ4_B4_B_MASK 0xFFFF /* EQ4_B4_B - [15:0] */
  5753. #define ARIZONA_EQ4_B4_B_SHIFT 0 /* EQ4_B4_B - [15:0] */
  5754. #define ARIZONA_EQ4_B4_B_WIDTH 16 /* EQ4_B4_B - [15:0] */
  5755. /*
  5756. * R3681 (0xE61) - EQ4_16
  5757. */
  5758. #define ARIZONA_EQ4_B4_C_MASK 0xFFFF /* EQ4_B4_C - [15:0] */
  5759. #define ARIZONA_EQ4_B4_C_SHIFT 0 /* EQ4_B4_C - [15:0] */
  5760. #define ARIZONA_EQ4_B4_C_WIDTH 16 /* EQ4_B4_C - [15:0] */
  5761. /*
  5762. * R3682 (0xE62) - EQ4_17
  5763. */
  5764. #define ARIZONA_EQ4_B4_PG_MASK 0xFFFF /* EQ4_B4_PG - [15:0] */
  5765. #define ARIZONA_EQ4_B4_PG_SHIFT 0 /* EQ4_B4_PG - [15:0] */
  5766. #define ARIZONA_EQ4_B4_PG_WIDTH 16 /* EQ4_B4_PG - [15:0] */
  5767. /*
  5768. * R3683 (0xE63) - EQ4_18
  5769. */
  5770. #define ARIZONA_EQ4_B5_A_MASK 0xFFFF /* EQ4_B5_A - [15:0] */
  5771. #define ARIZONA_EQ4_B5_A_SHIFT 0 /* EQ4_B5_A - [15:0] */
  5772. #define ARIZONA_EQ4_B5_A_WIDTH 16 /* EQ4_B5_A - [15:0] */
  5773. /*
  5774. * R3684 (0xE64) - EQ4_19
  5775. */
  5776. #define ARIZONA_EQ4_B5_B_MASK 0xFFFF /* EQ4_B5_B - [15:0] */
  5777. #define ARIZONA_EQ4_B5_B_SHIFT 0 /* EQ4_B5_B - [15:0] */
  5778. #define ARIZONA_EQ4_B5_B_WIDTH 16 /* EQ4_B5_B - [15:0] */
  5779. /*
  5780. * R3685 (0xE65) - EQ4_20
  5781. */
  5782. #define ARIZONA_EQ4_B5_PG_MASK 0xFFFF /* EQ4_B5_PG - [15:0] */
  5783. #define ARIZONA_EQ4_B5_PG_SHIFT 0 /* EQ4_B5_PG - [15:0] */
  5784. #define ARIZONA_EQ4_B5_PG_WIDTH 16 /* EQ4_B5_PG - [15:0] */
  5785. /*
  5786. * R3686 (0xE66) - EQ4_21
  5787. */
  5788. #define ARIZONA_EQ4_B1_C_MASK 0xFFFF /* EQ4_B1_C - [15:0] */
  5789. #define ARIZONA_EQ4_B1_C_SHIFT 0 /* EQ4_B1_C - [15:0] */
  5790. #define ARIZONA_EQ4_B1_C_WIDTH 16 /* EQ4_B1_C - [15:0] */
  5791. /*
  5792. * R3712 (0xE80) - DRC1 ctrl1
  5793. */
  5794. #define ARIZONA_DRC1_SIG_DET_RMS_MASK 0xF800 /* DRC1_SIG_DET_RMS - [15:11] */
  5795. #define ARIZONA_DRC1_SIG_DET_RMS_SHIFT 11 /* DRC1_SIG_DET_RMS - [15:11] */
  5796. #define ARIZONA_DRC1_SIG_DET_RMS_WIDTH 5 /* DRC1_SIG_DET_RMS - [15:11] */
  5797. #define ARIZONA_DRC1_SIG_DET_PK_MASK 0x0600 /* DRC1_SIG_DET_PK - [10:9] */
  5798. #define ARIZONA_DRC1_SIG_DET_PK_SHIFT 9 /* DRC1_SIG_DET_PK - [10:9] */
  5799. #define ARIZONA_DRC1_SIG_DET_PK_WIDTH 2 /* DRC1_SIG_DET_PK - [10:9] */
  5800. #define ARIZONA_DRC1_NG_ENA 0x0100 /* DRC1_NG_ENA */
  5801. #define ARIZONA_DRC1_NG_ENA_MASK 0x0100 /* DRC1_NG_ENA */
  5802. #define ARIZONA_DRC1_NG_ENA_SHIFT 8 /* DRC1_NG_ENA */
  5803. #define ARIZONA_DRC1_NG_ENA_WIDTH 1 /* DRC1_NG_ENA */
  5804. #define ARIZONA_DRC1_SIG_DET_MODE 0x0080 /* DRC1_SIG_DET_MODE */
  5805. #define ARIZONA_DRC1_SIG_DET_MODE_MASK 0x0080 /* DRC1_SIG_DET_MODE */
  5806. #define ARIZONA_DRC1_SIG_DET_MODE_SHIFT 7 /* DRC1_SIG_DET_MODE */
  5807. #define ARIZONA_DRC1_SIG_DET_MODE_WIDTH 1 /* DRC1_SIG_DET_MODE */
  5808. #define ARIZONA_DRC1_SIG_DET 0x0040 /* DRC1_SIG_DET */
  5809. #define ARIZONA_DRC1_SIG_DET_MASK 0x0040 /* DRC1_SIG_DET */
  5810. #define ARIZONA_DRC1_SIG_DET_SHIFT 6 /* DRC1_SIG_DET */
  5811. #define ARIZONA_DRC1_SIG_DET_WIDTH 1 /* DRC1_SIG_DET */
  5812. #define ARIZONA_DRC1_KNEE2_OP_ENA 0x0020 /* DRC1_KNEE2_OP_ENA */
  5813. #define ARIZONA_DRC1_KNEE2_OP_ENA_MASK 0x0020 /* DRC1_KNEE2_OP_ENA */
  5814. #define ARIZONA_DRC1_KNEE2_OP_ENA_SHIFT 5 /* DRC1_KNEE2_OP_ENA */
  5815. #define ARIZONA_DRC1_KNEE2_OP_ENA_WIDTH 1 /* DRC1_KNEE2_OP_ENA */
  5816. #define ARIZONA_DRC1_QR 0x0010 /* DRC1_QR */
  5817. #define ARIZONA_DRC1_QR_MASK 0x0010 /* DRC1_QR */
  5818. #define ARIZONA_DRC1_QR_SHIFT 4 /* DRC1_QR */
  5819. #define ARIZONA_DRC1_QR_WIDTH 1 /* DRC1_QR */
  5820. #define ARIZONA_DRC1_ANTICLIP 0x0008 /* DRC1_ANTICLIP */
  5821. #define ARIZONA_DRC1_ANTICLIP_MASK 0x0008 /* DRC1_ANTICLIP */
  5822. #define ARIZONA_DRC1_ANTICLIP_SHIFT 3 /* DRC1_ANTICLIP */
  5823. #define ARIZONA_DRC1_ANTICLIP_WIDTH 1 /* DRC1_ANTICLIP */
  5824. #define ARIZONA_DRC1L_ENA 0x0002 /* DRC1L_ENA */
  5825. #define ARIZONA_DRC1L_ENA_MASK 0x0002 /* DRC1L_ENA */
  5826. #define ARIZONA_DRC1L_ENA_SHIFT 1 /* DRC1L_ENA */
  5827. #define ARIZONA_DRC1L_ENA_WIDTH 1 /* DRC1L_ENA */
  5828. #define ARIZONA_DRC1R_ENA 0x0001 /* DRC1R_ENA */
  5829. #define ARIZONA_DRC1R_ENA_MASK 0x0001 /* DRC1R_ENA */
  5830. #define ARIZONA_DRC1R_ENA_SHIFT 0 /* DRC1R_ENA */
  5831. #define ARIZONA_DRC1R_ENA_WIDTH 1 /* DRC1R_ENA */
  5832. /*
  5833. * R3713 (0xE81) - DRC1 ctrl2
  5834. */
  5835. #define ARIZONA_DRC1_ATK_MASK 0x1E00 /* DRC1_ATK - [12:9] */
  5836. #define ARIZONA_DRC1_ATK_SHIFT 9 /* DRC1_ATK - [12:9] */
  5837. #define ARIZONA_DRC1_ATK_WIDTH 4 /* DRC1_ATK - [12:9] */
  5838. #define ARIZONA_DRC1_DCY_MASK 0x01E0 /* DRC1_DCY - [8:5] */
  5839. #define ARIZONA_DRC1_DCY_SHIFT 5 /* DRC1_DCY - [8:5] */
  5840. #define ARIZONA_DRC1_DCY_WIDTH 4 /* DRC1_DCY - [8:5] */
  5841. #define ARIZONA_DRC1_MINGAIN_MASK 0x001C /* DRC1_MINGAIN - [4:2] */
  5842. #define ARIZONA_DRC1_MINGAIN_SHIFT 2 /* DRC1_MINGAIN - [4:2] */
  5843. #define ARIZONA_DRC1_MINGAIN_WIDTH 3 /* DRC1_MINGAIN - [4:2] */
  5844. #define ARIZONA_DRC1_MAXGAIN_MASK 0x0003 /* DRC1_MAXGAIN - [1:0] */
  5845. #define ARIZONA_DRC1_MAXGAIN_SHIFT 0 /* DRC1_MAXGAIN - [1:0] */
  5846. #define ARIZONA_DRC1_MAXGAIN_WIDTH 2 /* DRC1_MAXGAIN - [1:0] */
  5847. /*
  5848. * R3714 (0xE82) - DRC1 ctrl3
  5849. */
  5850. #define ARIZONA_DRC1_NG_MINGAIN_MASK 0xF000 /* DRC1_NG_MINGAIN - [15:12] */
  5851. #define ARIZONA_DRC1_NG_MINGAIN_SHIFT 12 /* DRC1_NG_MINGAIN - [15:12] */
  5852. #define ARIZONA_DRC1_NG_MINGAIN_WIDTH 4 /* DRC1_NG_MINGAIN - [15:12] */
  5853. #define ARIZONA_DRC1_NG_EXP_MASK 0x0C00 /* DRC1_NG_EXP - [11:10] */
  5854. #define ARIZONA_DRC1_NG_EXP_SHIFT 10 /* DRC1_NG_EXP - [11:10] */
  5855. #define ARIZONA_DRC1_NG_EXP_WIDTH 2 /* DRC1_NG_EXP - [11:10] */
  5856. #define ARIZONA_DRC1_QR_THR_MASK 0x0300 /* DRC1_QR_THR - [9:8] */
  5857. #define ARIZONA_DRC1_QR_THR_SHIFT 8 /* DRC1_QR_THR - [9:8] */
  5858. #define ARIZONA_DRC1_QR_THR_WIDTH 2 /* DRC1_QR_THR - [9:8] */
  5859. #define ARIZONA_DRC1_QR_DCY_MASK 0x00C0 /* DRC1_QR_DCY - [7:6] */
  5860. #define ARIZONA_DRC1_QR_DCY_SHIFT 6 /* DRC1_QR_DCY - [7:6] */
  5861. #define ARIZONA_DRC1_QR_DCY_WIDTH 2 /* DRC1_QR_DCY - [7:6] */
  5862. #define ARIZONA_DRC1_HI_COMP_MASK 0x0038 /* DRC1_HI_COMP - [5:3] */
  5863. #define ARIZONA_DRC1_HI_COMP_SHIFT 3 /* DRC1_HI_COMP - [5:3] */
  5864. #define ARIZONA_DRC1_HI_COMP_WIDTH 3 /* DRC1_HI_COMP - [5:3] */
  5865. #define ARIZONA_DRC1_LO_COMP_MASK 0x0007 /* DRC1_LO_COMP - [2:0] */
  5866. #define ARIZONA_DRC1_LO_COMP_SHIFT 0 /* DRC1_LO_COMP - [2:0] */
  5867. #define ARIZONA_DRC1_LO_COMP_WIDTH 3 /* DRC1_LO_COMP - [2:0] */
  5868. /*
  5869. * R3715 (0xE83) - DRC1 ctrl4
  5870. */
  5871. #define ARIZONA_DRC1_KNEE_IP_MASK 0x07E0 /* DRC1_KNEE_IP - [10:5] */
  5872. #define ARIZONA_DRC1_KNEE_IP_SHIFT 5 /* DRC1_KNEE_IP - [10:5] */
  5873. #define ARIZONA_DRC1_KNEE_IP_WIDTH 6 /* DRC1_KNEE_IP - [10:5] */
  5874. #define ARIZONA_DRC1_KNEE_OP_MASK 0x001F /* DRC1_KNEE_OP - [4:0] */
  5875. #define ARIZONA_DRC1_KNEE_OP_SHIFT 0 /* DRC1_KNEE_OP - [4:0] */
  5876. #define ARIZONA_DRC1_KNEE_OP_WIDTH 5 /* DRC1_KNEE_OP - [4:0] */
  5877. /*
  5878. * R3716 (0xE84) - DRC1 ctrl5
  5879. */
  5880. #define ARIZONA_DRC1_KNEE2_IP_MASK 0x03E0 /* DRC1_KNEE2_IP - [9:5] */
  5881. #define ARIZONA_DRC1_KNEE2_IP_SHIFT 5 /* DRC1_KNEE2_IP - [9:5] */
  5882. #define ARIZONA_DRC1_KNEE2_IP_WIDTH 5 /* DRC1_KNEE2_IP - [9:5] */
  5883. #define ARIZONA_DRC1_KNEE2_OP_MASK 0x001F /* DRC1_KNEE2_OP - [4:0] */
  5884. #define ARIZONA_DRC1_KNEE2_OP_SHIFT 0 /* DRC1_KNEE2_OP - [4:0] */
  5885. #define ARIZONA_DRC1_KNEE2_OP_WIDTH 5 /* DRC1_KNEE2_OP - [4:0] */
  5886. /*
  5887. * R3721 (0xE89) - DRC2 ctrl1
  5888. */
  5889. #define ARIZONA_DRC2_SIG_DET_RMS_MASK 0xF800 /* DRC2_SIG_DET_RMS - [15:11] */
  5890. #define ARIZONA_DRC2_SIG_DET_RMS_SHIFT 11 /* DRC2_SIG_DET_RMS - [15:11] */
  5891. #define ARIZONA_DRC2_SIG_DET_RMS_WIDTH 5 /* DRC2_SIG_DET_RMS - [15:11] */
  5892. #define ARIZONA_DRC2_SIG_DET_PK_MASK 0x0600 /* DRC2_SIG_DET_PK - [10:9] */
  5893. #define ARIZONA_DRC2_SIG_DET_PK_SHIFT 9 /* DRC2_SIG_DET_PK - [10:9] */
  5894. #define ARIZONA_DRC2_SIG_DET_PK_WIDTH 2 /* DRC2_SIG_DET_PK - [10:9] */
  5895. #define ARIZONA_DRC2_NG_ENA 0x0100 /* DRC2_NG_ENA */
  5896. #define ARIZONA_DRC2_NG_ENA_MASK 0x0100 /* DRC2_NG_ENA */
  5897. #define ARIZONA_DRC2_NG_ENA_SHIFT 8 /* DRC2_NG_ENA */
  5898. #define ARIZONA_DRC2_NG_ENA_WIDTH 1 /* DRC2_NG_ENA */
  5899. #define ARIZONA_DRC2_SIG_DET_MODE 0x0080 /* DRC2_SIG_DET_MODE */
  5900. #define ARIZONA_DRC2_SIG_DET_MODE_MASK 0x0080 /* DRC2_SIG_DET_MODE */
  5901. #define ARIZONA_DRC2_SIG_DET_MODE_SHIFT 7 /* DRC2_SIG_DET_MODE */
  5902. #define ARIZONA_DRC2_SIG_DET_MODE_WIDTH 1 /* DRC2_SIG_DET_MODE */
  5903. #define ARIZONA_DRC2_SIG_DET 0x0040 /* DRC2_SIG_DET */
  5904. #define ARIZONA_DRC2_SIG_DET_MASK 0x0040 /* DRC2_SIG_DET */
  5905. #define ARIZONA_DRC2_SIG_DET_SHIFT 6 /* DRC2_SIG_DET */
  5906. #define ARIZONA_DRC2_SIG_DET_WIDTH 1 /* DRC2_SIG_DET */
  5907. #define ARIZONA_DRC2_KNEE2_OP_ENA 0x0020 /* DRC2_KNEE2_OP_ENA */
  5908. #define ARIZONA_DRC2_KNEE2_OP_ENA_MASK 0x0020 /* DRC2_KNEE2_OP_ENA */
  5909. #define ARIZONA_DRC2_KNEE2_OP_ENA_SHIFT 5 /* DRC2_KNEE2_OP_ENA */
  5910. #define ARIZONA_DRC2_KNEE2_OP_ENA_WIDTH 1 /* DRC2_KNEE2_OP_ENA */
  5911. #define ARIZONA_DRC2_QR 0x0010 /* DRC2_QR */
  5912. #define ARIZONA_DRC2_QR_MASK 0x0010 /* DRC2_QR */
  5913. #define ARIZONA_DRC2_QR_SHIFT 4 /* DRC2_QR */
  5914. #define ARIZONA_DRC2_QR_WIDTH 1 /* DRC2_QR */
  5915. #define ARIZONA_DRC2_ANTICLIP 0x0008 /* DRC2_ANTICLIP */
  5916. #define ARIZONA_DRC2_ANTICLIP_MASK 0x0008 /* DRC2_ANTICLIP */
  5917. #define ARIZONA_DRC2_ANTICLIP_SHIFT 3 /* DRC2_ANTICLIP */
  5918. #define ARIZONA_DRC2_ANTICLIP_WIDTH 1 /* DRC2_ANTICLIP */
  5919. #define ARIZONA_DRC2L_ENA 0x0002 /* DRC2L_ENA */
  5920. #define ARIZONA_DRC2L_ENA_MASK 0x0002 /* DRC2L_ENA */
  5921. #define ARIZONA_DRC2L_ENA_SHIFT 1 /* DRC2L_ENA */
  5922. #define ARIZONA_DRC2L_ENA_WIDTH 1 /* DRC2L_ENA */
  5923. #define ARIZONA_DRC2R_ENA 0x0001 /* DRC2R_ENA */
  5924. #define ARIZONA_DRC2R_ENA_MASK 0x0001 /* DRC2R_ENA */
  5925. #define ARIZONA_DRC2R_ENA_SHIFT 0 /* DRC2R_ENA */
  5926. #define ARIZONA_DRC2R_ENA_WIDTH 1 /* DRC2R_ENA */
  5927. /*
  5928. * R3722 (0xE8A) - DRC2 ctrl2
  5929. */
  5930. #define ARIZONA_DRC2_ATK_MASK 0x1E00 /* DRC2_ATK - [12:9] */
  5931. #define ARIZONA_DRC2_ATK_SHIFT 9 /* DRC2_ATK - [12:9] */
  5932. #define ARIZONA_DRC2_ATK_WIDTH 4 /* DRC2_ATK - [12:9] */
  5933. #define ARIZONA_DRC2_DCY_MASK 0x01E0 /* DRC2_DCY - [8:5] */
  5934. #define ARIZONA_DRC2_DCY_SHIFT 5 /* DRC2_DCY - [8:5] */
  5935. #define ARIZONA_DRC2_DCY_WIDTH 4 /* DRC2_DCY - [8:5] */
  5936. #define ARIZONA_DRC2_MINGAIN_MASK 0x001C /* DRC2_MINGAIN - [4:2] */
  5937. #define ARIZONA_DRC2_MINGAIN_SHIFT 2 /* DRC2_MINGAIN - [4:2] */
  5938. #define ARIZONA_DRC2_MINGAIN_WIDTH 3 /* DRC2_MINGAIN - [4:2] */
  5939. #define ARIZONA_DRC2_MAXGAIN_MASK 0x0003 /* DRC2_MAXGAIN - [1:0] */
  5940. #define ARIZONA_DRC2_MAXGAIN_SHIFT 0 /* DRC2_MAXGAIN - [1:0] */
  5941. #define ARIZONA_DRC2_MAXGAIN_WIDTH 2 /* DRC2_MAXGAIN - [1:0] */
  5942. /*
  5943. * R3723 (0xE8B) - DRC2 ctrl3
  5944. */
  5945. #define ARIZONA_DRC2_NG_MINGAIN_MASK 0xF000 /* DRC2_NG_MINGAIN - [15:12] */
  5946. #define ARIZONA_DRC2_NG_MINGAIN_SHIFT 12 /* DRC2_NG_MINGAIN - [15:12] */
  5947. #define ARIZONA_DRC2_NG_MINGAIN_WIDTH 4 /* DRC2_NG_MINGAIN - [15:12] */
  5948. #define ARIZONA_DRC2_NG_EXP_MASK 0x0C00 /* DRC2_NG_EXP - [11:10] */
  5949. #define ARIZONA_DRC2_NG_EXP_SHIFT 10 /* DRC2_NG_EXP - [11:10] */
  5950. #define ARIZONA_DRC2_NG_EXP_WIDTH 2 /* DRC2_NG_EXP - [11:10] */
  5951. #define ARIZONA_DRC2_QR_THR_MASK 0x0300 /* DRC2_QR_THR - [9:8] */
  5952. #define ARIZONA_DRC2_QR_THR_SHIFT 8 /* DRC2_QR_THR - [9:8] */
  5953. #define ARIZONA_DRC2_QR_THR_WIDTH 2 /* DRC2_QR_THR - [9:8] */
  5954. #define ARIZONA_DRC2_QR_DCY_MASK 0x00C0 /* DRC2_QR_DCY - [7:6] */
  5955. #define ARIZONA_DRC2_QR_DCY_SHIFT 6 /* DRC2_QR_DCY - [7:6] */
  5956. #define ARIZONA_DRC2_QR_DCY_WIDTH 2 /* DRC2_QR_DCY - [7:6] */
  5957. #define ARIZONA_DRC2_HI_COMP_MASK 0x0038 /* DRC2_HI_COMP - [5:3] */
  5958. #define ARIZONA_DRC2_HI_COMP_SHIFT 3 /* DRC2_HI_COMP - [5:3] */
  5959. #define ARIZONA_DRC2_HI_COMP_WIDTH 3 /* DRC2_HI_COMP - [5:3] */
  5960. #define ARIZONA_DRC2_LO_COMP_MASK 0x0007 /* DRC2_LO_COMP - [2:0] */
  5961. #define ARIZONA_DRC2_LO_COMP_SHIFT 0 /* DRC2_LO_COMP - [2:0] */
  5962. #define ARIZONA_DRC2_LO_COMP_WIDTH 3 /* DRC2_LO_COMP - [2:0] */
  5963. /*
  5964. * R3724 (0xE8C) - DRC2 ctrl4
  5965. */
  5966. #define ARIZONA_DRC2_KNEE_IP_MASK 0x07E0 /* DRC2_KNEE_IP - [10:5] */
  5967. #define ARIZONA_DRC2_KNEE_IP_SHIFT 5 /* DRC2_KNEE_IP - [10:5] */
  5968. #define ARIZONA_DRC2_KNEE_IP_WIDTH 6 /* DRC2_KNEE_IP - [10:5] */
  5969. #define ARIZONA_DRC2_KNEE_OP_MASK 0x001F /* DRC2_KNEE_OP - [4:0] */
  5970. #define ARIZONA_DRC2_KNEE_OP_SHIFT 0 /* DRC2_KNEE_OP - [4:0] */
  5971. #define ARIZONA_DRC2_KNEE_OP_WIDTH 5 /* DRC2_KNEE_OP - [4:0] */
  5972. /*
  5973. * R3725 (0xE8D) - DRC2 ctrl5
  5974. */
  5975. #define ARIZONA_DRC2_KNEE2_IP_MASK 0x03E0 /* DRC2_KNEE2_IP - [9:5] */
  5976. #define ARIZONA_DRC2_KNEE2_IP_SHIFT 5 /* DRC2_KNEE2_IP - [9:5] */
  5977. #define ARIZONA_DRC2_KNEE2_IP_WIDTH 5 /* DRC2_KNEE2_IP - [9:5] */
  5978. #define ARIZONA_DRC2_KNEE2_OP_MASK 0x001F /* DRC2_KNEE2_OP - [4:0] */
  5979. #define ARIZONA_DRC2_KNEE2_OP_SHIFT 0 /* DRC2_KNEE2_OP - [4:0] */
  5980. #define ARIZONA_DRC2_KNEE2_OP_WIDTH 5 /* DRC2_KNEE2_OP - [4:0] */
  5981. /*
  5982. * R3776 (0xEC0) - HPLPF1_1
  5983. */
  5984. #define ARIZONA_LHPF1_MODE 0x0002 /* LHPF1_MODE */
  5985. #define ARIZONA_LHPF1_MODE_MASK 0x0002 /* LHPF1_MODE */
  5986. #define ARIZONA_LHPF1_MODE_SHIFT 1 /* LHPF1_MODE */
  5987. #define ARIZONA_LHPF1_MODE_WIDTH 1 /* LHPF1_MODE */
  5988. #define ARIZONA_LHPF1_ENA 0x0001 /* LHPF1_ENA */
  5989. #define ARIZONA_LHPF1_ENA_MASK 0x0001 /* LHPF1_ENA */
  5990. #define ARIZONA_LHPF1_ENA_SHIFT 0 /* LHPF1_ENA */
  5991. #define ARIZONA_LHPF1_ENA_WIDTH 1 /* LHPF1_ENA */
  5992. /*
  5993. * R3777 (0xEC1) - HPLPF1_2
  5994. */
  5995. #define ARIZONA_LHPF1_COEFF_MASK 0xFFFF /* LHPF1_COEFF - [15:0] */
  5996. #define ARIZONA_LHPF1_COEFF_SHIFT 0 /* LHPF1_COEFF - [15:0] */
  5997. #define ARIZONA_LHPF1_COEFF_WIDTH 16 /* LHPF1_COEFF - [15:0] */
  5998. /*
  5999. * R3780 (0xEC4) - HPLPF2_1
  6000. */
  6001. #define ARIZONA_LHPF2_MODE 0x0002 /* LHPF2_MODE */
  6002. #define ARIZONA_LHPF2_MODE_MASK 0x0002 /* LHPF2_MODE */
  6003. #define ARIZONA_LHPF2_MODE_SHIFT 1 /* LHPF2_MODE */
  6004. #define ARIZONA_LHPF2_MODE_WIDTH 1 /* LHPF2_MODE */
  6005. #define ARIZONA_LHPF2_ENA 0x0001 /* LHPF2_ENA */
  6006. #define ARIZONA_LHPF2_ENA_MASK 0x0001 /* LHPF2_ENA */
  6007. #define ARIZONA_LHPF2_ENA_SHIFT 0 /* LHPF2_ENA */
  6008. #define ARIZONA_LHPF2_ENA_WIDTH 1 /* LHPF2_ENA */
  6009. /*
  6010. * R3781 (0xEC5) - HPLPF2_2
  6011. */
  6012. #define ARIZONA_LHPF2_COEFF_MASK 0xFFFF /* LHPF2_COEFF - [15:0] */
  6013. #define ARIZONA_LHPF2_COEFF_SHIFT 0 /* LHPF2_COEFF - [15:0] */
  6014. #define ARIZONA_LHPF2_COEFF_WIDTH 16 /* LHPF2_COEFF - [15:0] */
  6015. /*
  6016. * R3784 (0xEC8) - HPLPF3_1
  6017. */
  6018. #define ARIZONA_LHPF3_MODE 0x0002 /* LHPF3_MODE */
  6019. #define ARIZONA_LHPF3_MODE_MASK 0x0002 /* LHPF3_MODE */
  6020. #define ARIZONA_LHPF3_MODE_SHIFT 1 /* LHPF3_MODE */
  6021. #define ARIZONA_LHPF3_MODE_WIDTH 1 /* LHPF3_MODE */
  6022. #define ARIZONA_LHPF3_ENA 0x0001 /* LHPF3_ENA */
  6023. #define ARIZONA_LHPF3_ENA_MASK 0x0001 /* LHPF3_ENA */
  6024. #define ARIZONA_LHPF3_ENA_SHIFT 0 /* LHPF3_ENA */
  6025. #define ARIZONA_LHPF3_ENA_WIDTH 1 /* LHPF3_ENA */
  6026. /*
  6027. * R3785 (0xEC9) - HPLPF3_2
  6028. */
  6029. #define ARIZONA_LHPF3_COEFF_MASK 0xFFFF /* LHPF3_COEFF - [15:0] */
  6030. #define ARIZONA_LHPF3_COEFF_SHIFT 0 /* LHPF3_COEFF - [15:0] */
  6031. #define ARIZONA_LHPF3_COEFF_WIDTH 16 /* LHPF3_COEFF - [15:0] */
  6032. /*
  6033. * R3788 (0xECC) - HPLPF4_1
  6034. */
  6035. #define ARIZONA_LHPF4_MODE 0x0002 /* LHPF4_MODE */
  6036. #define ARIZONA_LHPF4_MODE_MASK 0x0002 /* LHPF4_MODE */
  6037. #define ARIZONA_LHPF4_MODE_SHIFT 1 /* LHPF4_MODE */
  6038. #define ARIZONA_LHPF4_MODE_WIDTH 1 /* LHPF4_MODE */
  6039. #define ARIZONA_LHPF4_ENA 0x0001 /* LHPF4_ENA */
  6040. #define ARIZONA_LHPF4_ENA_MASK 0x0001 /* LHPF4_ENA */
  6041. #define ARIZONA_LHPF4_ENA_SHIFT 0 /* LHPF4_ENA */
  6042. #define ARIZONA_LHPF4_ENA_WIDTH 1 /* LHPF4_ENA */
  6043. /*
  6044. * R3789 (0xECD) - HPLPF4_2
  6045. */
  6046. #define ARIZONA_LHPF4_COEFF_MASK 0xFFFF /* LHPF4_COEFF - [15:0] */
  6047. #define ARIZONA_LHPF4_COEFF_SHIFT 0 /* LHPF4_COEFF - [15:0] */
  6048. #define ARIZONA_LHPF4_COEFF_WIDTH 16 /* LHPF4_COEFF - [15:0] */
  6049. /*
  6050. * R3808 (0xEE0) - ASRC_ENABLE
  6051. */
  6052. #define ARIZONA_ASRC2L_ENA 0x0008 /* ASRC2L_ENA */
  6053. #define ARIZONA_ASRC2L_ENA_MASK 0x0008 /* ASRC2L_ENA */
  6054. #define ARIZONA_ASRC2L_ENA_SHIFT 3 /* ASRC2L_ENA */
  6055. #define ARIZONA_ASRC2L_ENA_WIDTH 1 /* ASRC2L_ENA */
  6056. #define ARIZONA_ASRC2R_ENA 0x0004 /* ASRC2R_ENA */
  6057. #define ARIZONA_ASRC2R_ENA_MASK 0x0004 /* ASRC2R_ENA */
  6058. #define ARIZONA_ASRC2R_ENA_SHIFT 2 /* ASRC2R_ENA */
  6059. #define ARIZONA_ASRC2R_ENA_WIDTH 1 /* ASRC2R_ENA */
  6060. #define ARIZONA_ASRC1L_ENA 0x0002 /* ASRC1L_ENA */
  6061. #define ARIZONA_ASRC1L_ENA_MASK 0x0002 /* ASRC1L_ENA */
  6062. #define ARIZONA_ASRC1L_ENA_SHIFT 1 /* ASRC1L_ENA */
  6063. #define ARIZONA_ASRC1L_ENA_WIDTH 1 /* ASRC1L_ENA */
  6064. #define ARIZONA_ASRC1R_ENA 0x0001 /* ASRC1R_ENA */
  6065. #define ARIZONA_ASRC1R_ENA_MASK 0x0001 /* ASRC1R_ENA */
  6066. #define ARIZONA_ASRC1R_ENA_SHIFT 0 /* ASRC1R_ENA */
  6067. #define ARIZONA_ASRC1R_ENA_WIDTH 1 /* ASRC1R_ENA */
  6068. /*
  6069. * R3810 (0xEE2) - ASRC_RATE1
  6070. */
  6071. #define ARIZONA_ASRC_RATE1_MASK 0x7800 /* ASRC_RATE1 - [14:11] */
  6072. #define ARIZONA_ASRC_RATE1_SHIFT 11 /* ASRC_RATE1 - [14:11] */
  6073. #define ARIZONA_ASRC_RATE1_WIDTH 4 /* ASRC_RATE1 - [14:11] */
  6074. /*
  6075. * R3811 (0xEE3) - ASRC_RATE2
  6076. */
  6077. #define ARIZONA_ASRC_RATE2_MASK 0x7800 /* ASRC_RATE2 - [14:11] */
  6078. #define ARIZONA_ASRC_RATE2_SHIFT 11 /* ASRC_RATE2 - [14:11] */
  6079. #define ARIZONA_ASRC_RATE2_WIDTH 4 /* ASRC_RATE2 - [14:11] */
  6080. /*
  6081. * R3824 (0xEF0) - ISRC 1 CTRL 1
  6082. */
  6083. #define ARIZONA_ISRC1_FSH_MASK 0x7800 /* ISRC1_FSH - [14:11] */
  6084. #define ARIZONA_ISRC1_FSH_SHIFT 11 /* ISRC1_FSH - [14:11] */
  6085. #define ARIZONA_ISRC1_FSH_WIDTH 4 /* ISRC1_FSH - [14:11] */
  6086. #define ARIZONA_ISRC1_CLK_SEL_MASK 0x0700 /* ISRC1_CLK_SEL - [10:8] */
  6087. #define ARIZONA_ISRC1_CLK_SEL_SHIFT 8 /* ISRC1_CLK_SEL - [10:8] */
  6088. #define ARIZONA_ISRC1_CLK_SEL_WIDTH 3 /* ISRC1_CLK_SEL - [10:8] */
  6089. /*
  6090. * R3825 (0xEF1) - ISRC 1 CTRL 2
  6091. */
  6092. #define ARIZONA_ISRC1_FSL_MASK 0x7800 /* ISRC1_FSL - [14:11] */
  6093. #define ARIZONA_ISRC1_FSL_SHIFT 11 /* ISRC1_FSL - [14:11] */
  6094. #define ARIZONA_ISRC1_FSL_WIDTH 4 /* ISRC1_FSL - [14:11] */
  6095. /*
  6096. * R3826 (0xEF2) - ISRC 1 CTRL 3
  6097. */
  6098. #define ARIZONA_ISRC1_INT0_ENA 0x8000 /* ISRC1_INT0_ENA */
  6099. #define ARIZONA_ISRC1_INT0_ENA_MASK 0x8000 /* ISRC1_INT0_ENA */
  6100. #define ARIZONA_ISRC1_INT0_ENA_SHIFT 15 /* ISRC1_INT0_ENA */
  6101. #define ARIZONA_ISRC1_INT0_ENA_WIDTH 1 /* ISRC1_INT0_ENA */
  6102. #define ARIZONA_ISRC1_INT1_ENA 0x4000 /* ISRC1_INT1_ENA */
  6103. #define ARIZONA_ISRC1_INT1_ENA_MASK 0x4000 /* ISRC1_INT1_ENA */
  6104. #define ARIZONA_ISRC1_INT1_ENA_SHIFT 14 /* ISRC1_INT1_ENA */
  6105. #define ARIZONA_ISRC1_INT1_ENA_WIDTH 1 /* ISRC1_INT1_ENA */
  6106. #define ARIZONA_ISRC1_INT2_ENA 0x2000 /* ISRC1_INT2_ENA */
  6107. #define ARIZONA_ISRC1_INT2_ENA_MASK 0x2000 /* ISRC1_INT2_ENA */
  6108. #define ARIZONA_ISRC1_INT2_ENA_SHIFT 13 /* ISRC1_INT2_ENA */
  6109. #define ARIZONA_ISRC1_INT2_ENA_WIDTH 1 /* ISRC1_INT2_ENA */
  6110. #define ARIZONA_ISRC1_INT3_ENA 0x1000 /* ISRC1_INT3_ENA */
  6111. #define ARIZONA_ISRC1_INT3_ENA_MASK 0x1000 /* ISRC1_INT3_ENA */
  6112. #define ARIZONA_ISRC1_INT3_ENA_SHIFT 12 /* ISRC1_INT3_ENA */
  6113. #define ARIZONA_ISRC1_INT3_ENA_WIDTH 1 /* ISRC1_INT3_ENA */
  6114. #define ARIZONA_ISRC1_DEC0_ENA 0x0200 /* ISRC1_DEC0_ENA */
  6115. #define ARIZONA_ISRC1_DEC0_ENA_MASK 0x0200 /* ISRC1_DEC0_ENA */
  6116. #define ARIZONA_ISRC1_DEC0_ENA_SHIFT 9 /* ISRC1_DEC0_ENA */
  6117. #define ARIZONA_ISRC1_DEC0_ENA_WIDTH 1 /* ISRC1_DEC0_ENA */
  6118. #define ARIZONA_ISRC1_DEC1_ENA 0x0100 /* ISRC1_DEC1_ENA */
  6119. #define ARIZONA_ISRC1_DEC1_ENA_MASK 0x0100 /* ISRC1_DEC1_ENA */
  6120. #define ARIZONA_ISRC1_DEC1_ENA_SHIFT 8 /* ISRC1_DEC1_ENA */
  6121. #define ARIZONA_ISRC1_DEC1_ENA_WIDTH 1 /* ISRC1_DEC1_ENA */
  6122. #define ARIZONA_ISRC1_DEC2_ENA 0x0080 /* ISRC1_DEC2_ENA */
  6123. #define ARIZONA_ISRC1_DEC2_ENA_MASK 0x0080 /* ISRC1_DEC2_ENA */
  6124. #define ARIZONA_ISRC1_DEC2_ENA_SHIFT 7 /* ISRC1_DEC2_ENA */
  6125. #define ARIZONA_ISRC1_DEC2_ENA_WIDTH 1 /* ISRC1_DEC2_ENA */
  6126. #define ARIZONA_ISRC1_DEC3_ENA 0x0040 /* ISRC1_DEC3_ENA */
  6127. #define ARIZONA_ISRC1_DEC3_ENA_MASK 0x0040 /* ISRC1_DEC3_ENA */
  6128. #define ARIZONA_ISRC1_DEC3_ENA_SHIFT 6 /* ISRC1_DEC3_ENA */
  6129. #define ARIZONA_ISRC1_DEC3_ENA_WIDTH 1 /* ISRC1_DEC3_ENA */
  6130. #define ARIZONA_ISRC1_NOTCH_ENA 0x0001 /* ISRC1_NOTCH_ENA */
  6131. #define ARIZONA_ISRC1_NOTCH_ENA_MASK 0x0001 /* ISRC1_NOTCH_ENA */
  6132. #define ARIZONA_ISRC1_NOTCH_ENA_SHIFT 0 /* ISRC1_NOTCH_ENA */
  6133. #define ARIZONA_ISRC1_NOTCH_ENA_WIDTH 1 /* ISRC1_NOTCH_ENA */
  6134. /*
  6135. * R3827 (0xEF3) - ISRC 2 CTRL 1
  6136. */
  6137. #define ARIZONA_ISRC2_FSH_MASK 0x7800 /* ISRC2_FSH - [14:11] */
  6138. #define ARIZONA_ISRC2_FSH_SHIFT 11 /* ISRC2_FSH - [14:11] */
  6139. #define ARIZONA_ISRC2_FSH_WIDTH 4 /* ISRC2_FSH - [14:11] */
  6140. #define ARIZONA_ISRC2_CLK_SEL_MASK 0x0700 /* ISRC2_CLK_SEL - [10:8] */
  6141. #define ARIZONA_ISRC2_CLK_SEL_SHIFT 8 /* ISRC2_CLK_SEL - [10:8] */
  6142. #define ARIZONA_ISRC2_CLK_SEL_WIDTH 3 /* ISRC2_CLK_SEL - [10:8] */
  6143. /*
  6144. * R3828 (0xEF4) - ISRC 2 CTRL 2
  6145. */
  6146. #define ARIZONA_ISRC2_FSL_MASK 0x7800 /* ISRC2_FSL - [14:11] */
  6147. #define ARIZONA_ISRC2_FSL_SHIFT 11 /* ISRC2_FSL - [14:11] */
  6148. #define ARIZONA_ISRC2_FSL_WIDTH 4 /* ISRC2_FSL - [14:11] */
  6149. /*
  6150. * R3829 (0xEF5) - ISRC 2 CTRL 3
  6151. */
  6152. #define ARIZONA_ISRC2_INT0_ENA 0x8000 /* ISRC2_INT0_ENA */
  6153. #define ARIZONA_ISRC2_INT0_ENA_MASK 0x8000 /* ISRC2_INT0_ENA */
  6154. #define ARIZONA_ISRC2_INT0_ENA_SHIFT 15 /* ISRC2_INT0_ENA */
  6155. #define ARIZONA_ISRC2_INT0_ENA_WIDTH 1 /* ISRC2_INT0_ENA */
  6156. #define ARIZONA_ISRC2_INT1_ENA 0x4000 /* ISRC2_INT1_ENA */
  6157. #define ARIZONA_ISRC2_INT1_ENA_MASK 0x4000 /* ISRC2_INT1_ENA */
  6158. #define ARIZONA_ISRC2_INT1_ENA_SHIFT 14 /* ISRC2_INT1_ENA */
  6159. #define ARIZONA_ISRC2_INT1_ENA_WIDTH 1 /* ISRC2_INT1_ENA */
  6160. #define ARIZONA_ISRC2_INT2_ENA 0x2000 /* ISRC2_INT2_ENA */
  6161. #define ARIZONA_ISRC2_INT2_ENA_MASK 0x2000 /* ISRC2_INT2_ENA */
  6162. #define ARIZONA_ISRC2_INT2_ENA_SHIFT 13 /* ISRC2_INT2_ENA */
  6163. #define ARIZONA_ISRC2_INT2_ENA_WIDTH 1 /* ISRC2_INT2_ENA */
  6164. #define ARIZONA_ISRC2_INT3_ENA 0x1000 /* ISRC2_INT3_ENA */
  6165. #define ARIZONA_ISRC2_INT3_ENA_MASK 0x1000 /* ISRC2_INT3_ENA */
  6166. #define ARIZONA_ISRC2_INT3_ENA_SHIFT 12 /* ISRC2_INT3_ENA */
  6167. #define ARIZONA_ISRC2_INT3_ENA_WIDTH 1 /* ISRC2_INT3_ENA */
  6168. #define ARIZONA_ISRC2_DEC0_ENA 0x0200 /* ISRC2_DEC0_ENA */
  6169. #define ARIZONA_ISRC2_DEC0_ENA_MASK 0x0200 /* ISRC2_DEC0_ENA */
  6170. #define ARIZONA_ISRC2_DEC0_ENA_SHIFT 9 /* ISRC2_DEC0_ENA */
  6171. #define ARIZONA_ISRC2_DEC0_ENA_WIDTH 1 /* ISRC2_DEC0_ENA */
  6172. #define ARIZONA_ISRC2_DEC1_ENA 0x0100 /* ISRC2_DEC1_ENA */
  6173. #define ARIZONA_ISRC2_DEC1_ENA_MASK 0x0100 /* ISRC2_DEC1_ENA */
  6174. #define ARIZONA_ISRC2_DEC1_ENA_SHIFT 8 /* ISRC2_DEC1_ENA */
  6175. #define ARIZONA_ISRC2_DEC1_ENA_WIDTH 1 /* ISRC2_DEC1_ENA */
  6176. #define ARIZONA_ISRC2_DEC2_ENA 0x0080 /* ISRC2_DEC2_ENA */
  6177. #define ARIZONA_ISRC2_DEC2_ENA_MASK 0x0080 /* ISRC2_DEC2_ENA */
  6178. #define ARIZONA_ISRC2_DEC2_ENA_SHIFT 7 /* ISRC2_DEC2_ENA */
  6179. #define ARIZONA_ISRC2_DEC2_ENA_WIDTH 1 /* ISRC2_DEC2_ENA */
  6180. #define ARIZONA_ISRC2_DEC3_ENA 0x0040 /* ISRC2_DEC3_ENA */
  6181. #define ARIZONA_ISRC2_DEC3_ENA_MASK 0x0040 /* ISRC2_DEC3_ENA */
  6182. #define ARIZONA_ISRC2_DEC3_ENA_SHIFT 6 /* ISRC2_DEC3_ENA */
  6183. #define ARIZONA_ISRC2_DEC3_ENA_WIDTH 1 /* ISRC2_DEC3_ENA */
  6184. #define ARIZONA_ISRC2_NOTCH_ENA 0x0001 /* ISRC2_NOTCH_ENA */
  6185. #define ARIZONA_ISRC2_NOTCH_ENA_MASK 0x0001 /* ISRC2_NOTCH_ENA */
  6186. #define ARIZONA_ISRC2_NOTCH_ENA_SHIFT 0 /* ISRC2_NOTCH_ENA */
  6187. #define ARIZONA_ISRC2_NOTCH_ENA_WIDTH 1 /* ISRC2_NOTCH_ENA */
  6188. /*
  6189. * R3830 (0xEF6) - ISRC 3 CTRL 1
  6190. */
  6191. #define ARIZONA_ISRC3_FSH_MASK 0x7800 /* ISRC3_FSH - [14:11] */
  6192. #define ARIZONA_ISRC3_FSH_SHIFT 11 /* ISRC3_FSH - [14:11] */
  6193. #define ARIZONA_ISRC3_FSH_WIDTH 4 /* ISRC3_FSH - [14:11] */
  6194. #define ARIZONA_ISRC3_CLK_SEL_MASK 0x0700 /* ISRC3_CLK_SEL - [10:8] */
  6195. #define ARIZONA_ISRC3_CLK_SEL_SHIFT 8 /* ISRC3_CLK_SEL - [10:8] */
  6196. #define ARIZONA_ISRC3_CLK_SEL_WIDTH 3 /* ISRC3_CLK_SEL - [10:8] */
  6197. /*
  6198. * R3831 (0xEF7) - ISRC 3 CTRL 2
  6199. */
  6200. #define ARIZONA_ISRC3_FSL_MASK 0x7800 /* ISRC3_FSL - [14:11] */
  6201. #define ARIZONA_ISRC3_FSL_SHIFT 11 /* ISRC3_FSL - [14:11] */
  6202. #define ARIZONA_ISRC3_FSL_WIDTH 4 /* ISRC3_FSL - [14:11] */
  6203. /*
  6204. * R3832 (0xEF8) - ISRC 3 CTRL 3
  6205. */
  6206. #define ARIZONA_ISRC3_INT0_ENA 0x8000 /* ISRC3_INT0_ENA */
  6207. #define ARIZONA_ISRC3_INT0_ENA_MASK 0x8000 /* ISRC3_INT0_ENA */
  6208. #define ARIZONA_ISRC3_INT0_ENA_SHIFT 15 /* ISRC3_INT0_ENA */
  6209. #define ARIZONA_ISRC3_INT0_ENA_WIDTH 1 /* ISRC3_INT0_ENA */
  6210. #define ARIZONA_ISRC3_INT1_ENA 0x4000 /* ISRC3_INT1_ENA */
  6211. #define ARIZONA_ISRC3_INT1_ENA_MASK 0x4000 /* ISRC3_INT1_ENA */
  6212. #define ARIZONA_ISRC3_INT1_ENA_SHIFT 14 /* ISRC3_INT1_ENA */
  6213. #define ARIZONA_ISRC3_INT1_ENA_WIDTH 1 /* ISRC3_INT1_ENA */
  6214. #define ARIZONA_ISRC3_INT2_ENA 0x2000 /* ISRC3_INT2_ENA */
  6215. #define ARIZONA_ISRC3_INT2_ENA_MASK 0x2000 /* ISRC3_INT2_ENA */
  6216. #define ARIZONA_ISRC3_INT2_ENA_SHIFT 13 /* ISRC3_INT2_ENA */
  6217. #define ARIZONA_ISRC3_INT2_ENA_WIDTH 1 /* ISRC3_INT2_ENA */
  6218. #define ARIZONA_ISRC3_INT3_ENA 0x1000 /* ISRC3_INT3_ENA */
  6219. #define ARIZONA_ISRC3_INT3_ENA_MASK 0x1000 /* ISRC3_INT3_ENA */
  6220. #define ARIZONA_ISRC3_INT3_ENA_SHIFT 12 /* ISRC3_INT3_ENA */
  6221. #define ARIZONA_ISRC3_INT3_ENA_WIDTH 1 /* ISRC3_INT3_ENA */
  6222. #define ARIZONA_ISRC3_DEC0_ENA 0x0200 /* ISRC3_DEC0_ENA */
  6223. #define ARIZONA_ISRC3_DEC0_ENA_MASK 0x0200 /* ISRC3_DEC0_ENA */
  6224. #define ARIZONA_ISRC3_DEC0_ENA_SHIFT 9 /* ISRC3_DEC0_ENA */
  6225. #define ARIZONA_ISRC3_DEC0_ENA_WIDTH 1 /* ISRC3_DEC0_ENA */
  6226. #define ARIZONA_ISRC3_DEC1_ENA 0x0100 /* ISRC3_DEC1_ENA */
  6227. #define ARIZONA_ISRC3_DEC1_ENA_MASK 0x0100 /* ISRC3_DEC1_ENA */
  6228. #define ARIZONA_ISRC3_DEC1_ENA_SHIFT 8 /* ISRC3_DEC1_ENA */
  6229. #define ARIZONA_ISRC3_DEC1_ENA_WIDTH 1 /* ISRC3_DEC1_ENA */
  6230. #define ARIZONA_ISRC3_DEC2_ENA 0x0080 /* ISRC3_DEC2_ENA */
  6231. #define ARIZONA_ISRC3_DEC2_ENA_MASK 0x0080 /* ISRC3_DEC2_ENA */
  6232. #define ARIZONA_ISRC3_DEC2_ENA_SHIFT 7 /* ISRC3_DEC2_ENA */
  6233. #define ARIZONA_ISRC3_DEC2_ENA_WIDTH 1 /* ISRC3_DEC2_ENA */
  6234. #define ARIZONA_ISRC3_DEC3_ENA 0x0040 /* ISRC3_DEC3_ENA */
  6235. #define ARIZONA_ISRC3_DEC3_ENA_MASK 0x0040 /* ISRC3_DEC3_ENA */
  6236. #define ARIZONA_ISRC3_DEC3_ENA_SHIFT 6 /* ISRC3_DEC3_ENA */
  6237. #define ARIZONA_ISRC3_DEC3_ENA_WIDTH 1 /* ISRC3_DEC3_ENA */
  6238. #define ARIZONA_ISRC3_NOTCH_ENA 0x0001 /* ISRC3_NOTCH_ENA */
  6239. #define ARIZONA_ISRC3_NOTCH_ENA_MASK 0x0001 /* ISRC3_NOTCH_ENA */
  6240. #define ARIZONA_ISRC3_NOTCH_ENA_SHIFT 0 /* ISRC3_NOTCH_ENA */
  6241. #define ARIZONA_ISRC3_NOTCH_ENA_WIDTH 1 /* ISRC3_NOTCH_ENA */
  6242. /*
  6243. * R4352 (0x1100) - DSP1 Control 1
  6244. */
  6245. #define ARIZONA_DSP1_RATE_MASK 0x7800 /* DSP1_RATE - [14:11] */
  6246. #define ARIZONA_DSP1_RATE_SHIFT 11 /* DSP1_RATE - [14:11] */
  6247. #define ARIZONA_DSP1_RATE_WIDTH 4 /* DSP1_RATE - [14:11] */
  6248. #define ARIZONA_DSP1_MEM_ENA 0x0010 /* DSP1_MEM_ENA */
  6249. #define ARIZONA_DSP1_MEM_ENA_MASK 0x0010 /* DSP1_MEM_ENA */
  6250. #define ARIZONA_DSP1_MEM_ENA_SHIFT 4 /* DSP1_MEM_ENA */
  6251. #define ARIZONA_DSP1_MEM_ENA_WIDTH 1 /* DSP1_MEM_ENA */
  6252. #define ARIZONA_DSP1_SYS_ENA 0x0004 /* DSP1_SYS_ENA */
  6253. #define ARIZONA_DSP1_SYS_ENA_MASK 0x0004 /* DSP1_SYS_ENA */
  6254. #define ARIZONA_DSP1_SYS_ENA_SHIFT 2 /* DSP1_SYS_ENA */
  6255. #define ARIZONA_DSP1_SYS_ENA_WIDTH 1 /* DSP1_SYS_ENA */
  6256. #define ARIZONA_DSP1_CORE_ENA 0x0002 /* DSP1_CORE_ENA */
  6257. #define ARIZONA_DSP1_CORE_ENA_MASK 0x0002 /* DSP1_CORE_ENA */
  6258. #define ARIZONA_DSP1_CORE_ENA_SHIFT 1 /* DSP1_CORE_ENA */
  6259. #define ARIZONA_DSP1_CORE_ENA_WIDTH 1 /* DSP1_CORE_ENA */
  6260. #define ARIZONA_DSP1_START 0x0001 /* DSP1_START */
  6261. #define ARIZONA_DSP1_START_MASK 0x0001 /* DSP1_START */
  6262. #define ARIZONA_DSP1_START_SHIFT 0 /* DSP1_START */
  6263. #define ARIZONA_DSP1_START_WIDTH 1 /* DSP1_START */
  6264. /*
  6265. * R4353 (0x1101) - DSP1 Clocking 1
  6266. */
  6267. #define ARIZONA_DSP1_CLK_SEL_MASK 0x0007 /* DSP1_CLK_SEL - [2:0] */
  6268. #define ARIZONA_DSP1_CLK_SEL_SHIFT 0 /* DSP1_CLK_SEL - [2:0] */
  6269. #define ARIZONA_DSP1_CLK_SEL_WIDTH 3 /* DSP1_CLK_SEL - [2:0] */
  6270. /*
  6271. * R4356 (0x1104) - DSP1 Status 1
  6272. */
  6273. #define ARIZONA_DSP1_RAM_RDY 0x0001 /* DSP1_RAM_RDY */
  6274. #define ARIZONA_DSP1_RAM_RDY_MASK 0x0001 /* DSP1_RAM_RDY */
  6275. #define ARIZONA_DSP1_RAM_RDY_SHIFT 0 /* DSP1_RAM_RDY */
  6276. #define ARIZONA_DSP1_RAM_RDY_WIDTH 1 /* DSP1_RAM_RDY */
  6277. /*
  6278. * R4357 (0x1105) - DSP1 Status 2
  6279. */
  6280. #define ARIZONA_DSP1_PING_FULL 0x8000 /* DSP1_PING_FULL */
  6281. #define ARIZONA_DSP1_PING_FULL_MASK 0x8000 /* DSP1_PING_FULL */
  6282. #define ARIZONA_DSP1_PING_FULL_SHIFT 15 /* DSP1_PING_FULL */
  6283. #define ARIZONA_DSP1_PING_FULL_WIDTH 1 /* DSP1_PING_FULL */
  6284. #define ARIZONA_DSP1_PONG_FULL 0x4000 /* DSP1_PONG_FULL */
  6285. #define ARIZONA_DSP1_PONG_FULL_MASK 0x4000 /* DSP1_PONG_FULL */
  6286. #define ARIZONA_DSP1_PONG_FULL_SHIFT 14 /* DSP1_PONG_FULL */
  6287. #define ARIZONA_DSP1_PONG_FULL_WIDTH 1 /* DSP1_PONG_FULL */
  6288. #define ARIZONA_DSP1_WDMA_ACTIVE_CHANNELS_MASK 0x00FF /* DSP1_WDMA_ACTIVE_CHANNELS - [7:0] */
  6289. #define ARIZONA_DSP1_WDMA_ACTIVE_CHANNELS_SHIFT 0 /* DSP1_WDMA_ACTIVE_CHANNELS - [7:0] */
  6290. #define ARIZONA_DSP1_WDMA_ACTIVE_CHANNELS_WIDTH 8 /* DSP1_WDMA_ACTIVE_CHANNELS - [7:0] */
  6291. #endif