gianfar_mii.c 6.3 KB

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  1. /*
  2. * drivers/net/gianfar_mii.c
  3. *
  4. * Gianfar Ethernet Driver -- MIIM bus implementation
  5. * Provides Bus interface for MIIM regs
  6. *
  7. * Author: Andy Fleming
  8. * Maintainer: Kumar Gala
  9. *
  10. * Copyright (c) 2002-2004 Freescale Semiconductor, Inc.
  11. *
  12. * This program is free software; you can redistribute it and/or modify it
  13. * under the terms of the GNU General Public License as published by the
  14. * Free Software Foundation; either version 2 of the License, or (at your
  15. * option) any later version.
  16. *
  17. */
  18. #include <linux/kernel.h>
  19. #include <linux/string.h>
  20. #include <linux/errno.h>
  21. #include <linux/unistd.h>
  22. #include <linux/slab.h>
  23. #include <linux/interrupt.h>
  24. #include <linux/init.h>
  25. #include <linux/delay.h>
  26. #include <linux/netdevice.h>
  27. #include <linux/etherdevice.h>
  28. #include <linux/skbuff.h>
  29. #include <linux/spinlock.h>
  30. #include <linux/mm.h>
  31. #include <linux/module.h>
  32. #include <linux/platform_device.h>
  33. #include <asm/ocp.h>
  34. #include <linux/crc32.h>
  35. #include <linux/mii.h>
  36. #include <linux/phy.h>
  37. #include <asm/io.h>
  38. #include <asm/irq.h>
  39. #include <asm/uaccess.h>
  40. #include "gianfar.h"
  41. #include "gianfar_mii.h"
  42. /*
  43. * Write value to the PHY at mii_id at register regnum,
  44. * on the bus attached to the local interface, which may be different from the
  45. * generic mdio bus (tied to a single interface), waiting until the write is
  46. * done before returning. This is helpful in programming interfaces like
  47. * the TBI which control interfaces like onchip SERDES and are always tied to
  48. * the local mdio pins, which may not be the same as system mdio bus, used for
  49. * controlling the external PHYs, for example.
  50. */
  51. int gfar_local_mdio_write(struct gfar_mii *regs, int mii_id,
  52. int regnum, u16 value)
  53. {
  54. /* Set the PHY address and the register address we want to write */
  55. gfar_write(&regs->miimadd, (mii_id << 8) | regnum);
  56. /* Write out the value we want */
  57. gfar_write(&regs->miimcon, value);
  58. /* Wait for the transaction to finish */
  59. while (gfar_read(&regs->miimind) & MIIMIND_BUSY)
  60. cpu_relax();
  61. return 0;
  62. }
  63. /*
  64. * Read the bus for PHY at addr mii_id, register regnum, and
  65. * return the value. Clears miimcom first. All PHY operation
  66. * done on the bus attached to the local interface,
  67. * which may be different from the generic mdio bus
  68. * This is helpful in programming interfaces like
  69. * the TBI which, inturn, control interfaces like onchip SERDES
  70. * and are always tied to the local mdio pins, which may not be the
  71. * same as system mdio bus, used for controlling the external PHYs, for eg.
  72. */
  73. int gfar_local_mdio_read(struct gfar_mii *regs, int mii_id, int regnum)
  74. {
  75. u16 value;
  76. /* Set the PHY address and the register address we want to read */
  77. gfar_write(&regs->miimadd, (mii_id << 8) | regnum);
  78. /* Clear miimcom, and then initiate a read */
  79. gfar_write(&regs->miimcom, 0);
  80. gfar_write(&regs->miimcom, MII_READ_COMMAND);
  81. /* Wait for the transaction to finish */
  82. while (gfar_read(&regs->miimind) & (MIIMIND_NOTVALID | MIIMIND_BUSY))
  83. cpu_relax();
  84. /* Grab the value of the register from miimstat */
  85. value = gfar_read(&regs->miimstat);
  86. return value;
  87. }
  88. /* Write value to the PHY at mii_id at register regnum,
  89. * on the bus, waiting until the write is done before returning.
  90. * All PHY configuration is done through the TSEC1 MIIM regs */
  91. int gfar_mdio_write(struct mii_bus *bus, int mii_id, int regnum, u16 value)
  92. {
  93. struct gfar_mii __iomem *regs = (void __iomem *)bus->priv;
  94. /* Write to the local MII regs */
  95. return(gfar_local_mdio_write(regs, mii_id, regnum, value));
  96. }
  97. /* Read the bus for PHY at addr mii_id, register regnum, and
  98. * return the value. Clears miimcom first. All PHY
  99. * configuration has to be done through the TSEC1 MIIM regs */
  100. int gfar_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
  101. {
  102. struct gfar_mii __iomem *regs = (void __iomem *)bus->priv;
  103. /* Read the local MII regs */
  104. return(gfar_local_mdio_read(regs, mii_id, regnum));
  105. }
  106. /* Reset the MIIM registers, and wait for the bus to free */
  107. int gfar_mdio_reset(struct mii_bus *bus)
  108. {
  109. struct gfar_mii __iomem *regs = (void __iomem *)bus->priv;
  110. unsigned int timeout = PHY_INIT_TIMEOUT;
  111. spin_lock_bh(&bus->mdio_lock);
  112. /* Reset the management interface */
  113. gfar_write(&regs->miimcfg, MIIMCFG_RESET);
  114. /* Setup the MII Mgmt clock speed */
  115. gfar_write(&regs->miimcfg, MIIMCFG_INIT_VALUE);
  116. /* Wait until the bus is free */
  117. while ((gfar_read(&regs->miimind) & MIIMIND_BUSY) &&
  118. timeout--)
  119. cpu_relax();
  120. spin_unlock_bh(&bus->mdio_lock);
  121. if(timeout <= 0) {
  122. printk(KERN_ERR "%s: The MII Bus is stuck!\n",
  123. bus->name);
  124. return -EBUSY;
  125. }
  126. return 0;
  127. }
  128. int gfar_mdio_probe(struct device *dev)
  129. {
  130. struct platform_device *pdev = to_platform_device(dev);
  131. struct gianfar_mdio_data *pdata;
  132. struct gfar_mii __iomem *regs;
  133. struct mii_bus *new_bus;
  134. struct resource *r;
  135. int err = 0;
  136. if (NULL == dev)
  137. return -EINVAL;
  138. new_bus = kzalloc(sizeof(struct mii_bus), GFP_KERNEL);
  139. if (NULL == new_bus)
  140. return -ENOMEM;
  141. new_bus->name = "Gianfar MII Bus",
  142. new_bus->read = &gfar_mdio_read,
  143. new_bus->write = &gfar_mdio_write,
  144. new_bus->reset = &gfar_mdio_reset,
  145. new_bus->id = pdev->id;
  146. pdata = (struct gianfar_mdio_data *)pdev->dev.platform_data;
  147. if (NULL == pdata) {
  148. printk(KERN_ERR "gfar mdio %d: Missing platform data!\n", pdev->id);
  149. return -ENODEV;
  150. }
  151. r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  152. /* Set the PHY base address */
  153. regs = ioremap(r->start, sizeof (struct gfar_mii));
  154. if (NULL == regs) {
  155. err = -ENOMEM;
  156. goto reg_map_fail;
  157. }
  158. new_bus->priv = (void __force *)regs;
  159. new_bus->irq = pdata->irq;
  160. new_bus->dev = dev;
  161. dev_set_drvdata(dev, new_bus);
  162. err = mdiobus_register(new_bus);
  163. if (0 != err) {
  164. printk (KERN_ERR "%s: Cannot register as MDIO bus\n",
  165. new_bus->name);
  166. goto bus_register_fail;
  167. }
  168. return 0;
  169. bus_register_fail:
  170. iounmap(regs);
  171. reg_map_fail:
  172. kfree(new_bus);
  173. return err;
  174. }
  175. int gfar_mdio_remove(struct device *dev)
  176. {
  177. struct mii_bus *bus = dev_get_drvdata(dev);
  178. mdiobus_unregister(bus);
  179. dev_set_drvdata(dev, NULL);
  180. iounmap((void __iomem *)bus->priv);
  181. bus->priv = NULL;
  182. kfree(bus);
  183. return 0;
  184. }
  185. static struct device_driver gianfar_mdio_driver = {
  186. .name = "fsl-gianfar_mdio",
  187. .bus = &platform_bus_type,
  188. .probe = gfar_mdio_probe,
  189. .remove = gfar_mdio_remove,
  190. };
  191. int __init gfar_mdio_init(void)
  192. {
  193. return driver_register(&gianfar_mdio_driver);
  194. }
  195. void __exit gfar_mdio_exit(void)
  196. {
  197. driver_unregister(&gianfar_mdio_driver);
  198. }