i915_gem_context.c 18 KB

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  1. /*
  2. * Copyright © 2011-2012 Intel Corporation
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21. * IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Ben Widawsky <ben@bwidawsk.net>
  25. *
  26. */
  27. /*
  28. * This file implements HW context support. On gen5+ a HW context consists of an
  29. * opaque GPU object which is referenced at times of context saves and restores.
  30. * With RC6 enabled, the context is also referenced as the GPU enters and exists
  31. * from RC6 (GPU has it's own internal power context, except on gen5). Though
  32. * something like a context does exist for the media ring, the code only
  33. * supports contexts for the render ring.
  34. *
  35. * In software, there is a distinction between contexts created by the user,
  36. * and the default HW context. The default HW context is used by GPU clients
  37. * that do not request setup of their own hardware context. The default
  38. * context's state is never restored to help prevent programming errors. This
  39. * would happen if a client ran and piggy-backed off another clients GPU state.
  40. * The default context only exists to give the GPU some offset to load as the
  41. * current to invoke a save of the context we actually care about. In fact, the
  42. * code could likely be constructed, albeit in a more complicated fashion, to
  43. * never use the default context, though that limits the driver's ability to
  44. * swap out, and/or destroy other contexts.
  45. *
  46. * All other contexts are created as a request by the GPU client. These contexts
  47. * store GPU state, and thus allow GPU clients to not re-emit state (and
  48. * potentially query certain state) at any time. The kernel driver makes
  49. * certain that the appropriate commands are inserted.
  50. *
  51. * The context life cycle is semi-complicated in that context BOs may live
  52. * longer than the context itself because of the way the hardware, and object
  53. * tracking works. Below is a very crude representation of the state machine
  54. * describing the context life.
  55. * refcount pincount active
  56. * S0: initial state 0 0 0
  57. * S1: context created 1 0 0
  58. * S2: context is currently running 2 1 X
  59. * S3: GPU referenced, but not current 2 0 1
  60. * S4: context is current, but destroyed 1 1 0
  61. * S5: like S3, but destroyed 1 0 1
  62. *
  63. * The most common (but not all) transitions:
  64. * S0->S1: client creates a context
  65. * S1->S2: client submits execbuf with context
  66. * S2->S3: other clients submits execbuf with context
  67. * S3->S1: context object was retired
  68. * S3->S2: clients submits another execbuf
  69. * S2->S4: context destroy called with current context
  70. * S3->S5->S0: destroy path
  71. * S4->S5->S0: destroy path on current context
  72. *
  73. * There are two confusing terms used above:
  74. * The "current context" means the context which is currently running on the
  75. * GPU. The GPU has loaded its state already and has stored away the gtt
  76. * offset of the BO. The GPU is not actively referencing the data at this
  77. * offset, but it will on the next context switch. The only way to avoid this
  78. * is to do a GPU reset.
  79. *
  80. * An "active context' is one which was previously the "current context" and is
  81. * on the active list waiting for the next context switch to occur. Until this
  82. * happens, the object must remain at the same gtt offset. It is therefore
  83. * possible to destroy a context, but it is still active.
  84. *
  85. */
  86. #include <drm/drmP.h>
  87. #include <drm/i915_drm.h>
  88. #include "i915_drv.h"
  89. /* This is a HW constraint. The value below is the largest known requirement
  90. * I've seen in a spec to date, and that was a workaround for a non-shipping
  91. * part. It should be safe to decrease this, but it's more future proof as is.
  92. */
  93. #define CONTEXT_ALIGN (64<<10)
  94. static struct i915_hw_context *
  95. i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id);
  96. static int do_switch(struct i915_hw_context *to);
  97. static int get_context_size(struct drm_device *dev)
  98. {
  99. struct drm_i915_private *dev_priv = dev->dev_private;
  100. int ret;
  101. u32 reg;
  102. switch (INTEL_INFO(dev)->gen) {
  103. case 6:
  104. reg = I915_READ(CXT_SIZE);
  105. ret = GEN6_CXT_TOTAL_SIZE(reg) * 64;
  106. break;
  107. case 7:
  108. reg = I915_READ(GEN7_CXT_SIZE);
  109. if (IS_HASWELL(dev))
  110. ret = HSW_CXT_TOTAL_SIZE;
  111. else
  112. ret = GEN7_CXT_TOTAL_SIZE(reg) * 64;
  113. break;
  114. default:
  115. BUG();
  116. }
  117. return ret;
  118. }
  119. void i915_gem_context_free(struct kref *ctx_ref)
  120. {
  121. struct i915_hw_context *ctx = container_of(ctx_ref,
  122. typeof(*ctx), ref);
  123. list_del(&ctx->link);
  124. drm_gem_object_unreference(&ctx->obj->base);
  125. kfree(ctx);
  126. }
  127. static struct i915_hw_context *
  128. create_hw_context(struct drm_device *dev,
  129. struct drm_i915_file_private *file_priv)
  130. {
  131. struct drm_i915_private *dev_priv = dev->dev_private;
  132. struct i915_hw_context *ctx;
  133. int ret;
  134. ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
  135. if (ctx == NULL)
  136. return ERR_PTR(-ENOMEM);
  137. kref_init(&ctx->ref);
  138. ctx->obj = i915_gem_alloc_object(dev, dev_priv->hw_context_size);
  139. INIT_LIST_HEAD(&ctx->link);
  140. if (ctx->obj == NULL) {
  141. kfree(ctx);
  142. DRM_DEBUG_DRIVER("Context object allocated failed\n");
  143. return ERR_PTR(-ENOMEM);
  144. }
  145. if (INTEL_INFO(dev)->gen >= 7) {
  146. ret = i915_gem_object_set_cache_level(ctx->obj,
  147. I915_CACHE_L3_LLC);
  148. /* Failure shouldn't ever happen this early */
  149. if (WARN_ON(ret))
  150. goto err_out;
  151. }
  152. /* The ring associated with the context object is handled by the normal
  153. * object tracking code. We give an initial ring value simple to pass an
  154. * assertion in the context switch code.
  155. */
  156. ctx->ring = &dev_priv->ring[RCS];
  157. list_add_tail(&ctx->link, &dev_priv->context_list);
  158. /* Default context will never have a file_priv */
  159. if (file_priv == NULL)
  160. return ctx;
  161. ret = idr_alloc(&file_priv->context_idr, ctx, DEFAULT_CONTEXT_ID + 1, 0,
  162. GFP_KERNEL);
  163. if (ret < 0)
  164. goto err_out;
  165. ctx->file_priv = file_priv;
  166. ctx->id = ret;
  167. /* NB: Mark all slices as needing a remap so that when the context first
  168. * loads it will restore whatever remap state already exists. If there
  169. * is no remap info, it will be a NOP. */
  170. ctx->remap_slice = (1 << NUM_L3_SLICES(dev)) - 1;
  171. return ctx;
  172. err_out:
  173. i915_gem_context_unreference(ctx);
  174. return ERR_PTR(ret);
  175. }
  176. static inline bool is_default_context(struct i915_hw_context *ctx)
  177. {
  178. return (ctx == ctx->ring->default_context);
  179. }
  180. /**
  181. * The default context needs to exist per ring that uses contexts. It stores the
  182. * context state of the GPU for applications that don't utilize HW contexts, as
  183. * well as an idle case.
  184. */
  185. static int create_default_context(struct drm_i915_private *dev_priv)
  186. {
  187. struct i915_hw_context *ctx;
  188. int ret;
  189. BUG_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
  190. ctx = create_hw_context(dev_priv->dev, NULL);
  191. if (IS_ERR(ctx))
  192. return PTR_ERR(ctx);
  193. /* We may need to do things with the shrinker which require us to
  194. * immediately switch back to the default context. This can cause a
  195. * problem as pinning the default context also requires GTT space which
  196. * may not be available. To avoid this we always pin the
  197. * default context.
  198. */
  199. ret = i915_gem_obj_ggtt_pin(ctx->obj, CONTEXT_ALIGN, false, false);
  200. if (ret) {
  201. DRM_DEBUG_DRIVER("Couldn't pin %d\n", ret);
  202. goto err_destroy;
  203. }
  204. ret = do_switch(ctx);
  205. if (ret) {
  206. DRM_DEBUG_DRIVER("Switch failed %d\n", ret);
  207. goto err_unpin;
  208. }
  209. dev_priv->ring[RCS].default_context = ctx;
  210. DRM_DEBUG_DRIVER("Default HW context loaded\n");
  211. return 0;
  212. err_unpin:
  213. i915_gem_object_unpin(ctx->obj);
  214. err_destroy:
  215. i915_gem_context_unreference(ctx);
  216. return ret;
  217. }
  218. void i915_gem_context_init(struct drm_device *dev)
  219. {
  220. struct drm_i915_private *dev_priv = dev->dev_private;
  221. if (!HAS_HW_CONTEXTS(dev)) {
  222. dev_priv->hw_contexts_disabled = true;
  223. DRM_DEBUG_DRIVER("Disabling HW Contexts; old hardware\n");
  224. return;
  225. }
  226. /* If called from reset, or thaw... we've been here already */
  227. if (dev_priv->hw_contexts_disabled ||
  228. dev_priv->ring[RCS].default_context)
  229. return;
  230. dev_priv->hw_context_size = round_up(get_context_size(dev), 4096);
  231. if (dev_priv->hw_context_size > (1<<20)) {
  232. dev_priv->hw_contexts_disabled = true;
  233. DRM_DEBUG_DRIVER("Disabling HW Contexts; invalid size\n");
  234. return;
  235. }
  236. if (create_default_context(dev_priv)) {
  237. dev_priv->hw_contexts_disabled = true;
  238. DRM_DEBUG_DRIVER("Disabling HW Contexts; create failed\n");
  239. return;
  240. }
  241. DRM_DEBUG_DRIVER("HW context support initialized\n");
  242. }
  243. void i915_gem_context_fini(struct drm_device *dev)
  244. {
  245. struct drm_i915_private *dev_priv = dev->dev_private;
  246. struct i915_hw_context *dctx = dev_priv->ring[RCS].default_context;
  247. if (dev_priv->hw_contexts_disabled)
  248. return;
  249. /* The only known way to stop the gpu from accessing the hw context is
  250. * to reset it. Do this as the very last operation to avoid confusing
  251. * other code, leading to spurious errors. */
  252. intel_gpu_reset(dev);
  253. /* When default context is created and switched to, base object refcount
  254. * will be 2 (+1 from object creation and +1 from do_switch()).
  255. * i915_gem_context_fini() will be called after gpu_idle() has switched
  256. * to default context. So we need to unreference the base object once
  257. * to offset the do_switch part, so that i915_gem_context_unreference()
  258. * can then free the base object correctly. */
  259. WARN_ON(!dev_priv->ring[RCS].last_context);
  260. if (dev_priv->ring[RCS].last_context == dctx) {
  261. /* Fake switch to NULL context */
  262. WARN_ON(dctx->obj->active);
  263. i915_gem_object_unpin(dctx->obj);
  264. i915_gem_context_unreference(dctx);
  265. }
  266. i915_gem_object_unpin(dctx->obj);
  267. i915_gem_context_unreference(dctx);
  268. dev_priv->ring[RCS].default_context = NULL;
  269. dev_priv->ring[RCS].last_context = NULL;
  270. }
  271. static int context_idr_cleanup(int id, void *p, void *data)
  272. {
  273. struct i915_hw_context *ctx = p;
  274. BUG_ON(id == DEFAULT_CONTEXT_ID);
  275. i915_gem_context_unreference(ctx);
  276. return 0;
  277. }
  278. struct i915_ctx_hang_stats *
  279. i915_gem_context_get_hang_stats(struct drm_device *dev,
  280. struct drm_file *file,
  281. u32 id)
  282. {
  283. struct drm_i915_private *dev_priv = dev->dev_private;
  284. struct drm_i915_file_private *file_priv = file->driver_priv;
  285. struct i915_hw_context *ctx;
  286. if (id == DEFAULT_CONTEXT_ID)
  287. return &file_priv->hang_stats;
  288. ctx = NULL;
  289. if (!dev_priv->hw_contexts_disabled)
  290. ctx = i915_gem_context_get(file->driver_priv, id);
  291. if (ctx == NULL)
  292. return ERR_PTR(-ENOENT);
  293. return &ctx->hang_stats;
  294. }
  295. void i915_gem_context_close(struct drm_device *dev, struct drm_file *file)
  296. {
  297. struct drm_i915_file_private *file_priv = file->driver_priv;
  298. mutex_lock(&dev->struct_mutex);
  299. idr_for_each(&file_priv->context_idr, context_idr_cleanup, NULL);
  300. idr_destroy(&file_priv->context_idr);
  301. mutex_unlock(&dev->struct_mutex);
  302. }
  303. static struct i915_hw_context *
  304. i915_gem_context_get(struct drm_i915_file_private *file_priv, u32 id)
  305. {
  306. return (struct i915_hw_context *)idr_find(&file_priv->context_idr, id);
  307. }
  308. static inline int
  309. mi_set_context(struct intel_ring_buffer *ring,
  310. struct i915_hw_context *new_context,
  311. u32 hw_flags)
  312. {
  313. int ret;
  314. /* w/a: If Flush TLB Invalidation Mode is enabled, driver must do a TLB
  315. * invalidation prior to MI_SET_CONTEXT. On GEN6 we don't set the value
  316. * explicitly, so we rely on the value at ring init, stored in
  317. * itlb_before_ctx_switch.
  318. */
  319. if (IS_GEN6(ring->dev) && ring->itlb_before_ctx_switch) {
  320. ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, 0);
  321. if (ret)
  322. return ret;
  323. }
  324. ret = intel_ring_begin(ring, 6);
  325. if (ret)
  326. return ret;
  327. /* WaProgramMiArbOnOffAroundMiSetContext:ivb,vlv,hsw */
  328. if (IS_GEN7(ring->dev))
  329. intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_DISABLE);
  330. else
  331. intel_ring_emit(ring, MI_NOOP);
  332. intel_ring_emit(ring, MI_NOOP);
  333. intel_ring_emit(ring, MI_SET_CONTEXT);
  334. intel_ring_emit(ring, i915_gem_obj_ggtt_offset(new_context->obj) |
  335. MI_MM_SPACE_GTT |
  336. MI_SAVE_EXT_STATE_EN |
  337. MI_RESTORE_EXT_STATE_EN |
  338. hw_flags);
  339. /* w/a: MI_SET_CONTEXT must always be followed by MI_NOOP */
  340. intel_ring_emit(ring, MI_NOOP);
  341. if (IS_GEN7(ring->dev))
  342. intel_ring_emit(ring, MI_ARB_ON_OFF | MI_ARB_ENABLE);
  343. else
  344. intel_ring_emit(ring, MI_NOOP);
  345. intel_ring_advance(ring);
  346. return ret;
  347. }
  348. static int do_switch(struct i915_hw_context *to)
  349. {
  350. struct intel_ring_buffer *ring = to->ring;
  351. struct i915_hw_context *from = ring->last_context;
  352. u32 hw_flags = 0;
  353. int ret, i;
  354. BUG_ON(from != NULL && from->obj != NULL && from->obj->pin_count == 0);
  355. if (from == to && !to->remap_slice)
  356. return 0;
  357. ret = i915_gem_obj_ggtt_pin(to->obj, CONTEXT_ALIGN, false, false);
  358. if (ret)
  359. return ret;
  360. /* Clear this page out of any CPU caches for coherent swap-in/out. Note
  361. * that thanks to write = false in this call and us not setting any gpu
  362. * write domains when putting a context object onto the active list
  363. * (when switching away from it), this won't block.
  364. * XXX: We need a real interface to do this instead of trickery. */
  365. ret = i915_gem_object_set_to_gtt_domain(to->obj, false);
  366. if (ret) {
  367. i915_gem_object_unpin(to->obj);
  368. return ret;
  369. }
  370. if (!to->obj->has_global_gtt_mapping)
  371. i915_gem_gtt_bind_object(to->obj, to->obj->cache_level);
  372. if (!to->is_initialized || is_default_context(to))
  373. hw_flags |= MI_RESTORE_INHIBIT;
  374. ret = mi_set_context(ring, to, hw_flags);
  375. if (ret) {
  376. i915_gem_object_unpin(to->obj);
  377. return ret;
  378. }
  379. for (i = 0; i < MAX_L3_SLICES; i++) {
  380. if (!(to->remap_slice & (1<<i)))
  381. continue;
  382. ret = i915_gem_l3_remap(ring, i);
  383. /* If it failed, try again next round */
  384. if (ret)
  385. DRM_DEBUG_DRIVER("L3 remapping failed\n");
  386. else
  387. to->remap_slice &= ~(1<<i);
  388. }
  389. /* The backing object for the context is done after switching to the
  390. * *next* context. Therefore we cannot retire the previous context until
  391. * the next context has already started running. In fact, the below code
  392. * is a bit suboptimal because the retiring can occur simply after the
  393. * MI_SET_CONTEXT instead of when the next seqno has completed.
  394. */
  395. if (from != NULL) {
  396. from->obj->base.read_domains = I915_GEM_DOMAIN_INSTRUCTION;
  397. i915_vma_move_to_active(i915_gem_obj_to_ggtt(from->obj), ring);
  398. /* As long as MI_SET_CONTEXT is serializing, ie. it flushes the
  399. * whole damn pipeline, we don't need to explicitly mark the
  400. * object dirty. The only exception is that the context must be
  401. * correct in case the object gets swapped out. Ideally we'd be
  402. * able to defer doing this until we know the object would be
  403. * swapped, but there is no way to do that yet.
  404. */
  405. from->obj->dirty = 1;
  406. BUG_ON(from->obj->ring != ring);
  407. /* obj is kept alive until the next request by its active ref */
  408. i915_gem_object_unpin(from->obj);
  409. i915_gem_context_unreference(from);
  410. }
  411. i915_gem_context_reference(to);
  412. ring->last_context = to;
  413. to->is_initialized = true;
  414. return 0;
  415. }
  416. /**
  417. * i915_switch_context() - perform a GPU context switch.
  418. * @ring: ring for which we'll execute the context switch
  419. * @file_priv: file_priv associated with the context, may be NULL
  420. * @id: context id number
  421. * @seqno: sequence number by which the new context will be switched to
  422. * @flags:
  423. *
  424. * The context life cycle is simple. The context refcount is incremented and
  425. * decremented by 1 and create and destroy. If the context is in use by the GPU,
  426. * it will have a refoucnt > 1. This allows us to destroy the context abstract
  427. * object while letting the normal object tracking destroy the backing BO.
  428. */
  429. int i915_switch_context(struct intel_ring_buffer *ring,
  430. struct drm_file *file,
  431. int to_id)
  432. {
  433. struct drm_i915_private *dev_priv = ring->dev->dev_private;
  434. struct i915_hw_context *to;
  435. if (dev_priv->hw_contexts_disabled)
  436. return 0;
  437. WARN_ON(!mutex_is_locked(&dev_priv->dev->struct_mutex));
  438. if (ring != &dev_priv->ring[RCS])
  439. return 0;
  440. if (to_id == DEFAULT_CONTEXT_ID) {
  441. to = ring->default_context;
  442. } else {
  443. if (file == NULL)
  444. return -EINVAL;
  445. to = i915_gem_context_get(file->driver_priv, to_id);
  446. if (to == NULL)
  447. return -ENOENT;
  448. }
  449. return do_switch(to);
  450. }
  451. int i915_gem_context_create_ioctl(struct drm_device *dev, void *data,
  452. struct drm_file *file)
  453. {
  454. struct drm_i915_private *dev_priv = dev->dev_private;
  455. struct drm_i915_gem_context_create *args = data;
  456. struct drm_i915_file_private *file_priv = file->driver_priv;
  457. struct i915_hw_context *ctx;
  458. int ret;
  459. if (!(dev->driver->driver_features & DRIVER_GEM))
  460. return -ENODEV;
  461. if (dev_priv->hw_contexts_disabled)
  462. return -ENODEV;
  463. ret = i915_mutex_lock_interruptible(dev);
  464. if (ret)
  465. return ret;
  466. ctx = create_hw_context(dev, file_priv);
  467. mutex_unlock(&dev->struct_mutex);
  468. if (IS_ERR(ctx))
  469. return PTR_ERR(ctx);
  470. args->ctx_id = ctx->id;
  471. DRM_DEBUG_DRIVER("HW context %d created\n", args->ctx_id);
  472. return 0;
  473. }
  474. int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
  475. struct drm_file *file)
  476. {
  477. struct drm_i915_gem_context_destroy *args = data;
  478. struct drm_i915_file_private *file_priv = file->driver_priv;
  479. struct i915_hw_context *ctx;
  480. int ret;
  481. if (!(dev->driver->driver_features & DRIVER_GEM))
  482. return -ENODEV;
  483. ret = i915_mutex_lock_interruptible(dev);
  484. if (ret)
  485. return ret;
  486. ctx = i915_gem_context_get(file_priv, args->ctx_id);
  487. if (!ctx) {
  488. mutex_unlock(&dev->struct_mutex);
  489. return -ENOENT;
  490. }
  491. idr_remove(&ctx->file_priv->context_idr, ctx->id);
  492. i915_gem_context_unreference(ctx);
  493. mutex_unlock(&dev->struct_mutex);
  494. DRM_DEBUG_DRIVER("HW context %d destroyed\n", args->ctx_id);
  495. return 0;
  496. }