sh_mipi_dsi.c 13 KB

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  1. /*
  2. * Renesas SH-mobile MIPI DSI support
  3. *
  4. * Copyright (C) 2010 Guennadi Liakhovetski <g.liakhovetski@gmx.de>
  5. *
  6. * This is free software; you can redistribute it and/or modify
  7. * it under the terms of version 2 of the GNU General Public License as
  8. * published by the Free Software Foundation.
  9. */
  10. #include <linux/clk.h>
  11. #include <linux/delay.h>
  12. #include <linux/init.h>
  13. #include <linux/io.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/slab.h>
  16. #include <linux/string.h>
  17. #include <linux/types.h>
  18. #include <video/mipi_display.h>
  19. #include <video/sh_mipi_dsi.h>
  20. #include <video/sh_mobile_lcdc.h>
  21. #define SYSCTRL 0x0000
  22. #define SYSCONF 0x0004
  23. #define TIMSET 0x0008
  24. #define RESREQSET0 0x0018
  25. #define RESREQSET1 0x001c
  26. #define HSTTOVSET 0x0020
  27. #define LPRTOVSET 0x0024
  28. #define TATOVSET 0x0028
  29. #define PRTOVSET 0x002c
  30. #define DSICTRL 0x0030
  31. #define DSIINTE 0x0060
  32. #define PHYCTRL 0x0070
  33. #define DTCTR 0x8000
  34. #define VMCTR1 0x8020
  35. #define VMCTR2 0x8024
  36. #define VMLEN1 0x8028
  37. #define CMTSRTREQ 0x8070
  38. #define CMTSRTCTR 0x80d0
  39. /* E.g., sh7372 has 2 MIPI-DSIs - one for each LCDC */
  40. #define MAX_SH_MIPI_DSI 2
  41. struct sh_mipi {
  42. void __iomem *base;
  43. struct clk *dsit_clk;
  44. struct clk *dsip_clk;
  45. };
  46. static struct sh_mipi *mipi_dsi[MAX_SH_MIPI_DSI];
  47. /* Protect the above array */
  48. static DEFINE_MUTEX(array_lock);
  49. static struct sh_mipi *sh_mipi_by_handle(int handle)
  50. {
  51. if (handle >= ARRAY_SIZE(mipi_dsi) || handle < 0)
  52. return NULL;
  53. return mipi_dsi[handle];
  54. }
  55. static int sh_mipi_send_short(struct sh_mipi *mipi, u8 dsi_cmd,
  56. u8 cmd, u8 param)
  57. {
  58. u32 data = (dsi_cmd << 24) | (cmd << 16) | (param << 8);
  59. int cnt = 100;
  60. /* transmit a short packet to LCD panel */
  61. iowrite32(1 | data, mipi->base + CMTSRTCTR);
  62. iowrite32(1, mipi->base + CMTSRTREQ);
  63. while ((ioread32(mipi->base + CMTSRTREQ) & 1) && --cnt)
  64. udelay(1);
  65. return cnt ? 0 : -ETIMEDOUT;
  66. }
  67. #define LCD_CHAN2MIPI(c) ((c) < LCDC_CHAN_MAINLCD || (c) > LCDC_CHAN_SUBLCD ? \
  68. -EINVAL : (c) - 1)
  69. static int sh_mipi_dcs(int handle, u8 cmd)
  70. {
  71. struct sh_mipi *mipi = sh_mipi_by_handle(LCD_CHAN2MIPI(handle));
  72. if (!mipi)
  73. return -ENODEV;
  74. return sh_mipi_send_short(mipi, MIPI_DSI_DCS_SHORT_WRITE, cmd, 0);
  75. }
  76. static int sh_mipi_dcs_param(int handle, u8 cmd, u8 param)
  77. {
  78. struct sh_mipi *mipi = sh_mipi_by_handle(LCD_CHAN2MIPI(handle));
  79. if (!mipi)
  80. return -ENODEV;
  81. return sh_mipi_send_short(mipi, MIPI_DSI_DCS_SHORT_WRITE_PARAM, cmd,
  82. param);
  83. }
  84. static void sh_mipi_dsi_enable(struct sh_mipi *mipi, bool enable)
  85. {
  86. /*
  87. * enable LCDC data tx, transition to LPS after completion of each HS
  88. * packet
  89. */
  90. iowrite32(0x00000002 | enable, mipi->base + DTCTR);
  91. }
  92. static void sh_mipi_shutdown(struct platform_device *pdev)
  93. {
  94. struct sh_mipi *mipi = platform_get_drvdata(pdev);
  95. sh_mipi_dsi_enable(mipi, false);
  96. }
  97. static void mipi_display_on(void *arg, struct fb_info *info)
  98. {
  99. struct sh_mipi *mipi = arg;
  100. sh_mipi_dsi_enable(mipi, true);
  101. }
  102. static void mipi_display_off(void *arg)
  103. {
  104. struct sh_mipi *mipi = arg;
  105. sh_mipi_dsi_enable(mipi, false);
  106. }
  107. static int __init sh_mipi_setup(struct sh_mipi *mipi,
  108. struct sh_mipi_dsi_info *pdata)
  109. {
  110. void __iomem *base = mipi->base;
  111. struct sh_mobile_lcdc_chan_cfg *ch = pdata->lcd_chan;
  112. u32 pctype, datatype, pixfmt;
  113. u32 linelength;
  114. bool yuv;
  115. /*
  116. * Select data format. MIPI DSI is not hot-pluggable, so, we just use
  117. * the default videomode. If this ever becomes a problem, We'll have to
  118. * move this to mipi_display_on() above and use info->var.xres
  119. */
  120. switch (pdata->data_format) {
  121. case MIPI_RGB888:
  122. pctype = 0;
  123. datatype = MIPI_DSI_PACKED_PIXEL_STREAM_24;
  124. pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
  125. linelength = ch->lcd_cfg[0].xres * 3;
  126. yuv = false;
  127. break;
  128. case MIPI_RGB565:
  129. pctype = 1;
  130. datatype = MIPI_DSI_PACKED_PIXEL_STREAM_16;
  131. pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
  132. linelength = ch->lcd_cfg[0].xres * 2;
  133. yuv = false;
  134. break;
  135. case MIPI_RGB666_LP:
  136. pctype = 2;
  137. datatype = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
  138. pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
  139. linelength = ch->lcd_cfg[0].xres * 3;
  140. yuv = false;
  141. break;
  142. case MIPI_RGB666:
  143. pctype = 3;
  144. datatype = MIPI_DSI_PACKED_PIXEL_STREAM_18;
  145. pixfmt = MIPI_DCS_PIXEL_FMT_18BIT;
  146. linelength = (ch->lcd_cfg[0].xres * 18 + 7) / 8;
  147. yuv = false;
  148. break;
  149. case MIPI_BGR888:
  150. pctype = 8;
  151. datatype = MIPI_DSI_PACKED_PIXEL_STREAM_24;
  152. pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
  153. linelength = ch->lcd_cfg[0].xres * 3;
  154. yuv = false;
  155. break;
  156. case MIPI_BGR565:
  157. pctype = 9;
  158. datatype = MIPI_DSI_PACKED_PIXEL_STREAM_16;
  159. pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
  160. linelength = ch->lcd_cfg[0].xres * 2;
  161. yuv = false;
  162. break;
  163. case MIPI_BGR666_LP:
  164. pctype = 0xa;
  165. datatype = MIPI_DSI_PIXEL_STREAM_3BYTE_18;
  166. pixfmt = MIPI_DCS_PIXEL_FMT_24BIT;
  167. linelength = ch->lcd_cfg[0].xres * 3;
  168. yuv = false;
  169. break;
  170. case MIPI_BGR666:
  171. pctype = 0xb;
  172. datatype = MIPI_DSI_PACKED_PIXEL_STREAM_18;
  173. pixfmt = MIPI_DCS_PIXEL_FMT_18BIT;
  174. linelength = (ch->lcd_cfg[0].xres * 18 + 7) / 8;
  175. yuv = false;
  176. break;
  177. case MIPI_YUYV:
  178. pctype = 4;
  179. datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16;
  180. pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
  181. linelength = ch->lcd_cfg[0].xres * 2;
  182. yuv = true;
  183. break;
  184. case MIPI_UYVY:
  185. pctype = 5;
  186. datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16;
  187. pixfmt = MIPI_DCS_PIXEL_FMT_16BIT;
  188. linelength = ch->lcd_cfg[0].xres * 2;
  189. yuv = true;
  190. break;
  191. case MIPI_YUV420_L:
  192. pctype = 6;
  193. datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12;
  194. pixfmt = MIPI_DCS_PIXEL_FMT_12BIT;
  195. linelength = (ch->lcd_cfg[0].xres * 12 + 7) / 8;
  196. yuv = true;
  197. break;
  198. case MIPI_YUV420:
  199. pctype = 7;
  200. datatype = MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12;
  201. pixfmt = MIPI_DCS_PIXEL_FMT_12BIT;
  202. /* Length of U/V line */
  203. linelength = (ch->lcd_cfg[0].xres + 1) / 2;
  204. yuv = true;
  205. break;
  206. default:
  207. return -EINVAL;
  208. }
  209. if ((yuv && ch->interface_type != YUV422) ||
  210. (!yuv && ch->interface_type != RGB24))
  211. return -EINVAL;
  212. /* reset DSI link */
  213. iowrite32(0x00000001, base + SYSCTRL);
  214. /* Hold reset for 100 cycles of the slowest of bus, HS byte and LP clock */
  215. udelay(50);
  216. iowrite32(0x00000000, base + SYSCTRL);
  217. /* setup DSI link */
  218. /*
  219. * Default = ULPS enable |
  220. * Contention detection enabled |
  221. * EoT packet transmission enable |
  222. * CRC check enable |
  223. * ECC check enable
  224. * additionally enable first two lanes
  225. */
  226. iowrite32(0x00003703, base + SYSCONF);
  227. /*
  228. * T_wakeup = 0x7000
  229. * T_hs-trail = 3
  230. * T_hs-prepare = 3
  231. * T_clk-trail = 3
  232. * T_clk-prepare = 2
  233. */
  234. iowrite32(0x70003332, base + TIMSET);
  235. /* no responses requested */
  236. iowrite32(0x00000000, base + RESREQSET0);
  237. /* request response to packets of type 0x28 */
  238. iowrite32(0x00000100, base + RESREQSET1);
  239. /* High-speed transmission timeout, default 0xffffffff */
  240. iowrite32(0x0fffffff, base + HSTTOVSET);
  241. /* LP reception timeout, default 0xffffffff */
  242. iowrite32(0x0fffffff, base + LPRTOVSET);
  243. /* Turn-around timeout, default 0xffffffff */
  244. iowrite32(0x0fffffff, base + TATOVSET);
  245. /* Peripheral reset timeout, default 0xffffffff */
  246. iowrite32(0x0fffffff, base + PRTOVSET);
  247. /* Enable timeout counters */
  248. iowrite32(0x00000f00, base + DSICTRL);
  249. /* Interrupts not used, disable all */
  250. iowrite32(0, base + DSIINTE);
  251. /* DSI-Tx bias on */
  252. iowrite32(0x00000001, base + PHYCTRL);
  253. udelay(200);
  254. /* Deassert resets, power on, set multiplier */
  255. iowrite32(0x03070b01, base + PHYCTRL);
  256. /* setup l-bridge */
  257. /*
  258. * Enable transmission of all packets,
  259. * transmit LPS after each HS packet completion
  260. */
  261. iowrite32(0x00000006, base + DTCTR);
  262. /* VSYNC width = 2 (<< 17) */
  263. iowrite32(0x00040000 | (pctype << 12) | datatype, base + VMCTR1);
  264. /*
  265. * Non-burst mode with sync pulses: VSE and HSE are output,
  266. * HSA period allowed, no commands in LP
  267. */
  268. iowrite32(0x00e00000, base + VMCTR2);
  269. /*
  270. * 0x660 = 1632 bytes per line (RGB24, 544 pixels: see
  271. * sh_mobile_lcdc_info.ch[0].lcd_cfg[0].xres), HSALEN = 1 - default
  272. * (unused, since VMCTR2[HSABM] = 0)
  273. */
  274. iowrite32(1 | (linelength << 16), base + VMLEN1);
  275. msleep(5);
  276. /* setup LCD panel */
  277. /* cf. drivers/video/omap/lcd_mipid.c */
  278. sh_mipi_dcs(ch->chan, MIPI_DCS_EXIT_SLEEP_MODE);
  279. msleep(120);
  280. /*
  281. * [7] - Page Address Mode
  282. * [6] - Column Address Mode
  283. * [5] - Page / Column Address Mode
  284. * [4] - Display Device Line Refresh Order
  285. * [3] - RGB/BGR Order
  286. * [2] - Display Data Latch Data Order
  287. * [1] - Flip Horizontal
  288. * [0] - Flip Vertical
  289. */
  290. sh_mipi_dcs_param(ch->chan, MIPI_DCS_SET_ADDRESS_MODE, 0x00);
  291. /* cf. set_data_lines() */
  292. sh_mipi_dcs_param(ch->chan, MIPI_DCS_SET_PIXEL_FORMAT,
  293. pixfmt << 4);
  294. sh_mipi_dcs(ch->chan, MIPI_DCS_SET_DISPLAY_ON);
  295. return 0;
  296. }
  297. static int __init sh_mipi_probe(struct platform_device *pdev)
  298. {
  299. struct sh_mipi *mipi;
  300. struct sh_mipi_dsi_info *pdata = pdev->dev.platform_data;
  301. struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  302. unsigned long rate, f_current;
  303. int idx = pdev->id, ret;
  304. char dsip_clk[] = "dsi.p_clk";
  305. if (!res || idx >= ARRAY_SIZE(mipi_dsi) || !pdata)
  306. return -ENODEV;
  307. mutex_lock(&array_lock);
  308. if (idx < 0)
  309. for (idx = 0; idx < ARRAY_SIZE(mipi_dsi) && mipi_dsi[idx]; idx++)
  310. ;
  311. if (idx == ARRAY_SIZE(mipi_dsi)) {
  312. ret = -EBUSY;
  313. goto efindslot;
  314. }
  315. mipi = kzalloc(sizeof(*mipi), GFP_KERNEL);
  316. if (!mipi) {
  317. ret = -ENOMEM;
  318. goto ealloc;
  319. }
  320. if (!request_mem_region(res->start, resource_size(res), pdev->name)) {
  321. dev_err(&pdev->dev, "MIPI register region already claimed\n");
  322. ret = -EBUSY;
  323. goto ereqreg;
  324. }
  325. mipi->base = ioremap(res->start, resource_size(res));
  326. if (!mipi->base) {
  327. ret = -ENOMEM;
  328. goto emap;
  329. }
  330. mipi->dsit_clk = clk_get(&pdev->dev, "dsit_clk");
  331. if (IS_ERR(mipi->dsit_clk)) {
  332. ret = PTR_ERR(mipi->dsit_clk);
  333. goto eclktget;
  334. }
  335. f_current = clk_get_rate(mipi->dsit_clk);
  336. /* 80MHz required by the datasheet */
  337. rate = clk_round_rate(mipi->dsit_clk, 80000000);
  338. if (rate > 0 && rate != f_current)
  339. ret = clk_set_rate(mipi->dsit_clk, rate);
  340. else
  341. ret = rate;
  342. if (ret < 0)
  343. goto esettrate;
  344. dev_dbg(&pdev->dev, "DSI-T clk %lu -> %lu\n", f_current, rate);
  345. sprintf(dsip_clk, "dsi%1.1dp_clk", idx);
  346. mipi->dsip_clk = clk_get(&pdev->dev, dsip_clk);
  347. if (IS_ERR(mipi->dsip_clk)) {
  348. ret = PTR_ERR(mipi->dsip_clk);
  349. goto eclkpget;
  350. }
  351. f_current = clk_get_rate(mipi->dsip_clk);
  352. /* Between 10 and 50MHz */
  353. rate = clk_round_rate(mipi->dsip_clk, 24000000);
  354. if (rate > 0 && rate != f_current)
  355. ret = clk_set_rate(mipi->dsip_clk, rate);
  356. else
  357. ret = rate;
  358. if (ret < 0)
  359. goto esetprate;
  360. dev_dbg(&pdev->dev, "DSI-P clk %lu -> %lu\n", f_current, rate);
  361. msleep(10);
  362. ret = clk_enable(mipi->dsit_clk);
  363. if (ret < 0)
  364. goto eclkton;
  365. ret = clk_enable(mipi->dsip_clk);
  366. if (ret < 0)
  367. goto eclkpon;
  368. mipi_dsi[idx] = mipi;
  369. ret = sh_mipi_setup(mipi, pdata);
  370. if (ret < 0)
  371. goto emipisetup;
  372. mutex_unlock(&array_lock);
  373. platform_set_drvdata(pdev, mipi);
  374. /* Set up LCDC callbacks */
  375. pdata->lcd_chan->board_cfg.board_data = mipi;
  376. pdata->lcd_chan->board_cfg.display_on = mipi_display_on;
  377. pdata->lcd_chan->board_cfg.display_off = mipi_display_off;
  378. return 0;
  379. emipisetup:
  380. mipi_dsi[idx] = NULL;
  381. clk_disable(mipi->dsip_clk);
  382. eclkpon:
  383. clk_disable(mipi->dsit_clk);
  384. eclkton:
  385. esetprate:
  386. clk_put(mipi->dsip_clk);
  387. eclkpget:
  388. esettrate:
  389. clk_put(mipi->dsit_clk);
  390. eclktget:
  391. iounmap(mipi->base);
  392. emap:
  393. release_mem_region(res->start, resource_size(res));
  394. ereqreg:
  395. kfree(mipi);
  396. ealloc:
  397. efindslot:
  398. mutex_unlock(&array_lock);
  399. return ret;
  400. }
  401. static int __exit sh_mipi_remove(struct platform_device *pdev)
  402. {
  403. struct sh_mipi_dsi_info *pdata = pdev->dev.platform_data;
  404. struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  405. struct sh_mipi *mipi = platform_get_drvdata(pdev);
  406. int i, ret;
  407. mutex_lock(&array_lock);
  408. for (i = 0; i < ARRAY_SIZE(mipi_dsi) && mipi_dsi[i] != mipi; i++)
  409. ;
  410. if (i == ARRAY_SIZE(mipi_dsi)) {
  411. ret = -EINVAL;
  412. } else {
  413. ret = 0;
  414. mipi_dsi[i] = NULL;
  415. }
  416. mutex_unlock(&array_lock);
  417. if (ret < 0)
  418. return ret;
  419. pdata->lcd_chan->board_cfg.display_on = NULL;
  420. pdata->lcd_chan->board_cfg.display_off = NULL;
  421. pdata->lcd_chan->board_cfg.board_data = NULL;
  422. clk_disable(mipi->dsip_clk);
  423. clk_disable(mipi->dsit_clk);
  424. clk_put(mipi->dsit_clk);
  425. clk_put(mipi->dsip_clk);
  426. iounmap(mipi->base);
  427. if (res)
  428. release_mem_region(res->start, resource_size(res));
  429. platform_set_drvdata(pdev, NULL);
  430. kfree(mipi);
  431. return 0;
  432. }
  433. static struct platform_driver sh_mipi_driver = {
  434. .remove = __exit_p(sh_mipi_remove),
  435. .shutdown = sh_mipi_shutdown,
  436. .driver = {
  437. .name = "sh-mipi-dsi",
  438. },
  439. };
  440. static int __init sh_mipi_init(void)
  441. {
  442. return platform_driver_probe(&sh_mipi_driver, sh_mipi_probe);
  443. }
  444. module_init(sh_mipi_init);
  445. static void __exit sh_mipi_exit(void)
  446. {
  447. platform_driver_unregister(&sh_mipi_driver);
  448. }
  449. module_exit(sh_mipi_exit);
  450. MODULE_AUTHOR("Guennadi Liakhovetski <g.liakhovetski@gmx.de>");
  451. MODULE_DESCRIPTION("SuperH / ARM-shmobile MIPI DSI driver");
  452. MODULE_LICENSE("GPL v2");