dw_mmc.c 67 KB

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  1. /*
  2. * Synopsys DesignWare Multimedia Card Interface driver
  3. * (Based on NXP driver for lpc 31xx)
  4. *
  5. * Copyright (C) 2009 NXP Semiconductors
  6. * Copyright (C) 2009, 2010 Imagination Technologies Ltd.
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. */
  13. #include <linux/blkdev.h>
  14. #include <linux/clk.h>
  15. #include <linux/debugfs.h>
  16. #include <linux/device.h>
  17. #include <linux/dma-mapping.h>
  18. #include <linux/err.h>
  19. #include <linux/init.h>
  20. #include <linux/interrupt.h>
  21. #include <linux/ioport.h>
  22. #include <linux/module.h>
  23. #include <linux/platform_device.h>
  24. #include <linux/seq_file.h>
  25. #include <linux/slab.h>
  26. #include <linux/stat.h>
  27. #include <linux/delay.h>
  28. #include <linux/irq.h>
  29. #include <linux/mmc/host.h>
  30. #include <linux/mmc/mmc.h>
  31. #include <linux/mmc/dw_mmc.h>
  32. #include <linux/bitops.h>
  33. #include <linux/regulator/consumer.h>
  34. #include <linux/workqueue.h>
  35. #include <linux/of.h>
  36. #include <linux/of_gpio.h>
  37. #include "dw_mmc.h"
  38. /* Common flag combinations */
  39. #define DW_MCI_DATA_ERROR_FLAGS (SDMMC_INT_DRTO | SDMMC_INT_DCRC | \
  40. SDMMC_INT_HTO | SDMMC_INT_SBE | \
  41. SDMMC_INT_EBE)
  42. #define DW_MCI_CMD_ERROR_FLAGS (SDMMC_INT_RTO | SDMMC_INT_RCRC | \
  43. SDMMC_INT_RESP_ERR)
  44. #define DW_MCI_ERROR_FLAGS (DW_MCI_DATA_ERROR_FLAGS | \
  45. DW_MCI_CMD_ERROR_FLAGS | SDMMC_INT_HLE)
  46. #define DW_MCI_SEND_STATUS 1
  47. #define DW_MCI_RECV_STATUS 2
  48. #define DW_MCI_DMA_THRESHOLD 16
  49. #define DW_MCI_FREQ_MAX 200000000 /* unit: HZ */
  50. #define DW_MCI_FREQ_MIN 400000 /* unit: HZ */
  51. #ifdef CONFIG_MMC_DW_IDMAC
  52. #define IDMAC_INT_CLR (SDMMC_IDMAC_INT_AI | SDMMC_IDMAC_INT_NI | \
  53. SDMMC_IDMAC_INT_CES | SDMMC_IDMAC_INT_DU | \
  54. SDMMC_IDMAC_INT_FBE | SDMMC_IDMAC_INT_RI | \
  55. SDMMC_IDMAC_INT_TI)
  56. struct idmac_desc {
  57. u32 des0; /* Control Descriptor */
  58. #define IDMAC_DES0_DIC BIT(1)
  59. #define IDMAC_DES0_LD BIT(2)
  60. #define IDMAC_DES0_FD BIT(3)
  61. #define IDMAC_DES0_CH BIT(4)
  62. #define IDMAC_DES0_ER BIT(5)
  63. #define IDMAC_DES0_CES BIT(30)
  64. #define IDMAC_DES0_OWN BIT(31)
  65. u32 des1; /* Buffer sizes */
  66. #define IDMAC_SET_BUFFER1_SIZE(d, s) \
  67. ((d)->des1 = ((d)->des1 & 0x03ffe000) | ((s) & 0x1fff))
  68. u32 des2; /* buffer 1 physical address */
  69. u32 des3; /* buffer 2 physical address */
  70. };
  71. #endif /* CONFIG_MMC_DW_IDMAC */
  72. static const u8 tuning_blk_pattern_4bit[] = {
  73. 0xff, 0x0f, 0xff, 0x00, 0xff, 0xcc, 0xc3, 0xcc,
  74. 0xc3, 0x3c, 0xcc, 0xff, 0xfe, 0xff, 0xfe, 0xef,
  75. 0xff, 0xdf, 0xff, 0xdd, 0xff, 0xfb, 0xff, 0xfb,
  76. 0xbf, 0xff, 0x7f, 0xff, 0x77, 0xf7, 0xbd, 0xef,
  77. 0xff, 0xf0, 0xff, 0xf0, 0x0f, 0xfc, 0xcc, 0x3c,
  78. 0xcc, 0x33, 0xcc, 0xcf, 0xff, 0xef, 0xff, 0xee,
  79. 0xff, 0xfd, 0xff, 0xfd, 0xdf, 0xff, 0xbf, 0xff,
  80. 0xbb, 0xff, 0xf7, 0xff, 0xf7, 0x7f, 0x7b, 0xde,
  81. };
  82. static const u8 tuning_blk_pattern_8bit[] = {
  83. 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00, 0x00,
  84. 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc, 0xcc,
  85. 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff, 0xff,
  86. 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee, 0xff,
  87. 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd, 0xdd,
  88. 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff, 0xbb,
  89. 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff, 0xff,
  90. 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee, 0xff,
  91. 0xff, 0xff, 0xff, 0x00, 0xff, 0xff, 0xff, 0x00,
  92. 0x00, 0xff, 0xff, 0xcc, 0xcc, 0xcc, 0x33, 0xcc,
  93. 0xcc, 0xcc, 0x33, 0x33, 0xcc, 0xcc, 0xcc, 0xff,
  94. 0xff, 0xff, 0xee, 0xff, 0xff, 0xff, 0xee, 0xee,
  95. 0xff, 0xff, 0xff, 0xdd, 0xff, 0xff, 0xff, 0xdd,
  96. 0xdd, 0xff, 0xff, 0xff, 0xbb, 0xff, 0xff, 0xff,
  97. 0xbb, 0xbb, 0xff, 0xff, 0xff, 0x77, 0xff, 0xff,
  98. 0xff, 0x77, 0x77, 0xff, 0x77, 0xbb, 0xdd, 0xee,
  99. };
  100. #if defined(CONFIG_DEBUG_FS)
  101. static int dw_mci_req_show(struct seq_file *s, void *v)
  102. {
  103. struct dw_mci_slot *slot = s->private;
  104. struct mmc_request *mrq;
  105. struct mmc_command *cmd;
  106. struct mmc_command *stop;
  107. struct mmc_data *data;
  108. /* Make sure we get a consistent snapshot */
  109. spin_lock_bh(&slot->host->lock);
  110. mrq = slot->mrq;
  111. if (mrq) {
  112. cmd = mrq->cmd;
  113. data = mrq->data;
  114. stop = mrq->stop;
  115. if (cmd)
  116. seq_printf(s,
  117. "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
  118. cmd->opcode, cmd->arg, cmd->flags,
  119. cmd->resp[0], cmd->resp[1], cmd->resp[2],
  120. cmd->resp[2], cmd->error);
  121. if (data)
  122. seq_printf(s, "DATA %u / %u * %u flg %x err %d\n",
  123. data->bytes_xfered, data->blocks,
  124. data->blksz, data->flags, data->error);
  125. if (stop)
  126. seq_printf(s,
  127. "CMD%u(0x%x) flg %x rsp %x %x %x %x err %d\n",
  128. stop->opcode, stop->arg, stop->flags,
  129. stop->resp[0], stop->resp[1], stop->resp[2],
  130. stop->resp[2], stop->error);
  131. }
  132. spin_unlock_bh(&slot->host->lock);
  133. return 0;
  134. }
  135. static int dw_mci_req_open(struct inode *inode, struct file *file)
  136. {
  137. return single_open(file, dw_mci_req_show, inode->i_private);
  138. }
  139. static const struct file_operations dw_mci_req_fops = {
  140. .owner = THIS_MODULE,
  141. .open = dw_mci_req_open,
  142. .read = seq_read,
  143. .llseek = seq_lseek,
  144. .release = single_release,
  145. };
  146. static int dw_mci_regs_show(struct seq_file *s, void *v)
  147. {
  148. seq_printf(s, "STATUS:\t0x%08x\n", SDMMC_STATUS);
  149. seq_printf(s, "RINTSTS:\t0x%08x\n", SDMMC_RINTSTS);
  150. seq_printf(s, "CMD:\t0x%08x\n", SDMMC_CMD);
  151. seq_printf(s, "CTRL:\t0x%08x\n", SDMMC_CTRL);
  152. seq_printf(s, "INTMASK:\t0x%08x\n", SDMMC_INTMASK);
  153. seq_printf(s, "CLKENA:\t0x%08x\n", SDMMC_CLKENA);
  154. return 0;
  155. }
  156. static int dw_mci_regs_open(struct inode *inode, struct file *file)
  157. {
  158. return single_open(file, dw_mci_regs_show, inode->i_private);
  159. }
  160. static const struct file_operations dw_mci_regs_fops = {
  161. .owner = THIS_MODULE,
  162. .open = dw_mci_regs_open,
  163. .read = seq_read,
  164. .llseek = seq_lseek,
  165. .release = single_release,
  166. };
  167. static void dw_mci_init_debugfs(struct dw_mci_slot *slot)
  168. {
  169. struct mmc_host *mmc = slot->mmc;
  170. struct dw_mci *host = slot->host;
  171. struct dentry *root;
  172. struct dentry *node;
  173. root = mmc->debugfs_root;
  174. if (!root)
  175. return;
  176. node = debugfs_create_file("regs", S_IRUSR, root, host,
  177. &dw_mci_regs_fops);
  178. if (!node)
  179. goto err;
  180. node = debugfs_create_file("req", S_IRUSR, root, slot,
  181. &dw_mci_req_fops);
  182. if (!node)
  183. goto err;
  184. node = debugfs_create_u32("state", S_IRUSR, root, (u32 *)&host->state);
  185. if (!node)
  186. goto err;
  187. node = debugfs_create_x32("pending_events", S_IRUSR, root,
  188. (u32 *)&host->pending_events);
  189. if (!node)
  190. goto err;
  191. node = debugfs_create_x32("completed_events", S_IRUSR, root,
  192. (u32 *)&host->completed_events);
  193. if (!node)
  194. goto err;
  195. return;
  196. err:
  197. dev_err(&mmc->class_dev, "failed to initialize debugfs for slot\n");
  198. }
  199. #endif /* defined(CONFIG_DEBUG_FS) */
  200. static void dw_mci_set_timeout(struct dw_mci *host)
  201. {
  202. /* timeout (maximum) */
  203. mci_writel(host, TMOUT, 0xffffffff);
  204. }
  205. static u32 dw_mci_prepare_command(struct mmc_host *mmc, struct mmc_command *cmd)
  206. {
  207. struct mmc_data *data;
  208. struct dw_mci_slot *slot = mmc_priv(mmc);
  209. const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
  210. u32 cmdr;
  211. cmd->error = -EINPROGRESS;
  212. cmdr = cmd->opcode;
  213. if (cmdr == MMC_STOP_TRANSMISSION)
  214. cmdr |= SDMMC_CMD_STOP;
  215. else
  216. cmdr |= SDMMC_CMD_PRV_DAT_WAIT;
  217. if (cmd->flags & MMC_RSP_PRESENT) {
  218. /* We expect a response, so set this bit */
  219. cmdr |= SDMMC_CMD_RESP_EXP;
  220. if (cmd->flags & MMC_RSP_136)
  221. cmdr |= SDMMC_CMD_RESP_LONG;
  222. }
  223. if (cmd->flags & MMC_RSP_CRC)
  224. cmdr |= SDMMC_CMD_RESP_CRC;
  225. data = cmd->data;
  226. if (data) {
  227. cmdr |= SDMMC_CMD_DAT_EXP;
  228. if (data->flags & MMC_DATA_STREAM)
  229. cmdr |= SDMMC_CMD_STRM_MODE;
  230. if (data->flags & MMC_DATA_WRITE)
  231. cmdr |= SDMMC_CMD_DAT_WR;
  232. }
  233. if (drv_data && drv_data->prepare_command)
  234. drv_data->prepare_command(slot->host, &cmdr);
  235. return cmdr;
  236. }
  237. static void dw_mci_start_command(struct dw_mci *host,
  238. struct mmc_command *cmd, u32 cmd_flags)
  239. {
  240. host->cmd = cmd;
  241. dev_vdbg(host->dev,
  242. "start command: ARGR=0x%08x CMDR=0x%08x\n",
  243. cmd->arg, cmd_flags);
  244. mci_writel(host, CMDARG, cmd->arg);
  245. wmb();
  246. mci_writel(host, CMD, cmd_flags | SDMMC_CMD_START);
  247. }
  248. static void send_stop_cmd(struct dw_mci *host, struct mmc_data *data)
  249. {
  250. dw_mci_start_command(host, data->stop, host->stop_cmdr);
  251. }
  252. /* DMA interface functions */
  253. static void dw_mci_stop_dma(struct dw_mci *host)
  254. {
  255. if (host->using_dma) {
  256. host->dma_ops->stop(host);
  257. host->dma_ops->cleanup(host);
  258. } else {
  259. /* Data transfer was stopped by the interrupt handler */
  260. set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
  261. }
  262. }
  263. static int dw_mci_get_dma_dir(struct mmc_data *data)
  264. {
  265. if (data->flags & MMC_DATA_WRITE)
  266. return DMA_TO_DEVICE;
  267. else
  268. return DMA_FROM_DEVICE;
  269. }
  270. #ifdef CONFIG_MMC_DW_IDMAC
  271. static void dw_mci_dma_cleanup(struct dw_mci *host)
  272. {
  273. struct mmc_data *data = host->data;
  274. if (data)
  275. if (!data->host_cookie)
  276. dma_unmap_sg(host->dev,
  277. data->sg,
  278. data->sg_len,
  279. dw_mci_get_dma_dir(data));
  280. }
  281. static void dw_mci_idmac_stop_dma(struct dw_mci *host)
  282. {
  283. u32 temp;
  284. /* Disable and reset the IDMAC interface */
  285. temp = mci_readl(host, CTRL);
  286. temp &= ~SDMMC_CTRL_USE_IDMAC;
  287. temp |= SDMMC_CTRL_DMA_RESET;
  288. mci_writel(host, CTRL, temp);
  289. /* Stop the IDMAC running */
  290. temp = mci_readl(host, BMOD);
  291. temp &= ~(SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB);
  292. mci_writel(host, BMOD, temp);
  293. }
  294. static void dw_mci_idmac_complete_dma(struct dw_mci *host)
  295. {
  296. struct mmc_data *data = host->data;
  297. dev_vdbg(host->dev, "DMA complete\n");
  298. host->dma_ops->cleanup(host);
  299. /*
  300. * If the card was removed, data will be NULL. No point in trying to
  301. * send the stop command or waiting for NBUSY in this case.
  302. */
  303. if (data) {
  304. set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
  305. tasklet_schedule(&host->tasklet);
  306. }
  307. }
  308. static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data,
  309. unsigned int sg_len)
  310. {
  311. int i;
  312. struct idmac_desc *desc = host->sg_cpu;
  313. for (i = 0; i < sg_len; i++, desc++) {
  314. unsigned int length = sg_dma_len(&data->sg[i]);
  315. u32 mem_addr = sg_dma_address(&data->sg[i]);
  316. /* Set the OWN bit and disable interrupts for this descriptor */
  317. desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | IDMAC_DES0_CH;
  318. /* Buffer length */
  319. IDMAC_SET_BUFFER1_SIZE(desc, length);
  320. /* Physical address to DMA to/from */
  321. desc->des2 = mem_addr;
  322. }
  323. /* Set first descriptor */
  324. desc = host->sg_cpu;
  325. desc->des0 |= IDMAC_DES0_FD;
  326. /* Set last descriptor */
  327. desc = host->sg_cpu + (i - 1) * sizeof(struct idmac_desc);
  328. desc->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
  329. desc->des0 |= IDMAC_DES0_LD;
  330. wmb();
  331. }
  332. static void dw_mci_idmac_start_dma(struct dw_mci *host, unsigned int sg_len)
  333. {
  334. u32 temp;
  335. dw_mci_translate_sglist(host, host->data, sg_len);
  336. /* Select IDMAC interface */
  337. temp = mci_readl(host, CTRL);
  338. temp |= SDMMC_CTRL_USE_IDMAC;
  339. mci_writel(host, CTRL, temp);
  340. wmb();
  341. /* Enable the IDMAC */
  342. temp = mci_readl(host, BMOD);
  343. temp |= SDMMC_IDMAC_ENABLE | SDMMC_IDMAC_FB;
  344. mci_writel(host, BMOD, temp);
  345. /* Start it running */
  346. mci_writel(host, PLDMND, 1);
  347. }
  348. static int dw_mci_idmac_init(struct dw_mci *host)
  349. {
  350. struct idmac_desc *p;
  351. int i;
  352. /* Number of descriptors in the ring buffer */
  353. host->ring_size = PAGE_SIZE / sizeof(struct idmac_desc);
  354. /* Forward link the descriptor list */
  355. for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; i++, p++)
  356. p->des3 = host->sg_dma + (sizeof(struct idmac_desc) * (i + 1));
  357. /* Set the last descriptor as the end-of-ring descriptor */
  358. p->des3 = host->sg_dma;
  359. p->des0 = IDMAC_DES0_ER;
  360. mci_writel(host, BMOD, SDMMC_IDMAC_SWRESET);
  361. /* Mask out interrupts - get Tx & Rx complete only */
  362. mci_writel(host, IDSTS, IDMAC_INT_CLR);
  363. mci_writel(host, IDINTEN, SDMMC_IDMAC_INT_NI | SDMMC_IDMAC_INT_RI |
  364. SDMMC_IDMAC_INT_TI);
  365. /* Set the descriptor base address */
  366. mci_writel(host, DBADDR, host->sg_dma);
  367. return 0;
  368. }
  369. static const struct dw_mci_dma_ops dw_mci_idmac_ops = {
  370. .init = dw_mci_idmac_init,
  371. .start = dw_mci_idmac_start_dma,
  372. .stop = dw_mci_idmac_stop_dma,
  373. .complete = dw_mci_idmac_complete_dma,
  374. .cleanup = dw_mci_dma_cleanup,
  375. };
  376. #endif /* CONFIG_MMC_DW_IDMAC */
  377. static int dw_mci_pre_dma_transfer(struct dw_mci *host,
  378. struct mmc_data *data,
  379. bool next)
  380. {
  381. struct scatterlist *sg;
  382. unsigned int i, sg_len;
  383. if (!next && data->host_cookie)
  384. return data->host_cookie;
  385. /*
  386. * We don't do DMA on "complex" transfers, i.e. with
  387. * non-word-aligned buffers or lengths. Also, we don't bother
  388. * with all the DMA setup overhead for short transfers.
  389. */
  390. if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD)
  391. return -EINVAL;
  392. if (data->blksz & 3)
  393. return -EINVAL;
  394. for_each_sg(data->sg, sg, data->sg_len, i) {
  395. if (sg->offset & 3 || sg->length & 3)
  396. return -EINVAL;
  397. }
  398. sg_len = dma_map_sg(host->dev,
  399. data->sg,
  400. data->sg_len,
  401. dw_mci_get_dma_dir(data));
  402. if (sg_len == 0)
  403. return -EINVAL;
  404. if (next)
  405. data->host_cookie = sg_len;
  406. return sg_len;
  407. }
  408. static void dw_mci_pre_req(struct mmc_host *mmc,
  409. struct mmc_request *mrq,
  410. bool is_first_req)
  411. {
  412. struct dw_mci_slot *slot = mmc_priv(mmc);
  413. struct mmc_data *data = mrq->data;
  414. if (!slot->host->use_dma || !data)
  415. return;
  416. if (data->host_cookie) {
  417. data->host_cookie = 0;
  418. return;
  419. }
  420. if (dw_mci_pre_dma_transfer(slot->host, mrq->data, 1) < 0)
  421. data->host_cookie = 0;
  422. }
  423. static void dw_mci_post_req(struct mmc_host *mmc,
  424. struct mmc_request *mrq,
  425. int err)
  426. {
  427. struct dw_mci_slot *slot = mmc_priv(mmc);
  428. struct mmc_data *data = mrq->data;
  429. if (!slot->host->use_dma || !data)
  430. return;
  431. if (data->host_cookie)
  432. dma_unmap_sg(slot->host->dev,
  433. data->sg,
  434. data->sg_len,
  435. dw_mci_get_dma_dir(data));
  436. data->host_cookie = 0;
  437. }
  438. static void dw_mci_adjust_fifoth(struct dw_mci *host, struct mmc_data *data)
  439. {
  440. #ifdef CONFIG_MMC_DW_IDMAC
  441. unsigned int blksz = data->blksz;
  442. const u32 mszs[] = {1, 4, 8, 16, 32, 64, 128, 256};
  443. u32 fifo_width = 1 << host->data_shift;
  444. u32 blksz_depth = blksz / fifo_width, fifoth_val;
  445. u32 msize = 0, rx_wmark = 1, tx_wmark, tx_wmark_invers;
  446. int idx = (sizeof(mszs) / sizeof(mszs[0])) - 1;
  447. tx_wmark = (host->fifo_depth) / 2;
  448. tx_wmark_invers = host->fifo_depth - tx_wmark;
  449. /*
  450. * MSIZE is '1',
  451. * if blksz is not a multiple of the FIFO width
  452. */
  453. if (blksz % fifo_width) {
  454. msize = 0;
  455. rx_wmark = 1;
  456. goto done;
  457. }
  458. do {
  459. if (!((blksz_depth % mszs[idx]) ||
  460. (tx_wmark_invers % mszs[idx]))) {
  461. msize = idx;
  462. rx_wmark = mszs[idx] - 1;
  463. break;
  464. }
  465. } while (--idx > 0);
  466. /*
  467. * If idx is '0', it won't be tried
  468. * Thus, initial values are uesed
  469. */
  470. done:
  471. fifoth_val = SDMMC_SET_FIFOTH(msize, rx_wmark, tx_wmark);
  472. mci_writel(host, FIFOTH, fifoth_val);
  473. #endif
  474. }
  475. static void dw_mci_ctrl_rd_thld(struct dw_mci *host, struct mmc_data *data)
  476. {
  477. unsigned int blksz = data->blksz;
  478. u32 blksz_depth, fifo_depth;
  479. u16 thld_size;
  480. WARN_ON(!(data->flags & MMC_DATA_READ));
  481. if (host->timing != MMC_TIMING_MMC_HS200 &&
  482. host->timing != MMC_TIMING_UHS_SDR104)
  483. goto disable;
  484. blksz_depth = blksz / (1 << host->data_shift);
  485. fifo_depth = host->fifo_depth;
  486. if (blksz_depth > fifo_depth)
  487. goto disable;
  488. /*
  489. * If (blksz_depth) >= (fifo_depth >> 1), should be 'thld_size <= blksz'
  490. * If (blksz_depth) < (fifo_depth >> 1), should be thld_size = blksz
  491. * Currently just choose blksz.
  492. */
  493. thld_size = blksz;
  494. mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(thld_size, 1));
  495. return;
  496. disable:
  497. mci_writel(host, CDTHRCTL, SDMMC_SET_RD_THLD(0, 0));
  498. }
  499. static int dw_mci_submit_data_dma(struct dw_mci *host, struct mmc_data *data)
  500. {
  501. int sg_len;
  502. u32 temp;
  503. host->using_dma = 0;
  504. /* If we don't have a channel, we can't do DMA */
  505. if (!host->use_dma)
  506. return -ENODEV;
  507. sg_len = dw_mci_pre_dma_transfer(host, data, 0);
  508. if (sg_len < 0) {
  509. host->dma_ops->stop(host);
  510. return sg_len;
  511. }
  512. host->using_dma = 1;
  513. dev_vdbg(host->dev,
  514. "sd sg_cpu: %#lx sg_dma: %#lx sg_len: %d\n",
  515. (unsigned long)host->sg_cpu, (unsigned long)host->sg_dma,
  516. sg_len);
  517. /*
  518. * Decide the MSIZE and RX/TX Watermark.
  519. * If current block size is same with previous size,
  520. * no need to update fifoth.
  521. */
  522. if (host->prev_blksz != data->blksz)
  523. dw_mci_adjust_fifoth(host, data);
  524. /* Enable the DMA interface */
  525. temp = mci_readl(host, CTRL);
  526. temp |= SDMMC_CTRL_DMA_ENABLE;
  527. mci_writel(host, CTRL, temp);
  528. /* Disable RX/TX IRQs, let DMA handle it */
  529. temp = mci_readl(host, INTMASK);
  530. temp &= ~(SDMMC_INT_RXDR | SDMMC_INT_TXDR);
  531. mci_writel(host, INTMASK, temp);
  532. host->dma_ops->start(host, sg_len);
  533. return 0;
  534. }
  535. static void dw_mci_submit_data(struct dw_mci *host, struct mmc_data *data)
  536. {
  537. u32 temp;
  538. data->error = -EINPROGRESS;
  539. WARN_ON(host->data);
  540. host->sg = NULL;
  541. host->data = data;
  542. if (data->flags & MMC_DATA_READ) {
  543. host->dir_status = DW_MCI_RECV_STATUS;
  544. dw_mci_ctrl_rd_thld(host, data);
  545. } else {
  546. host->dir_status = DW_MCI_SEND_STATUS;
  547. }
  548. if (dw_mci_submit_data_dma(host, data)) {
  549. int flags = SG_MITER_ATOMIC;
  550. if (host->data->flags & MMC_DATA_READ)
  551. flags |= SG_MITER_TO_SG;
  552. else
  553. flags |= SG_MITER_FROM_SG;
  554. sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
  555. host->sg = data->sg;
  556. host->part_buf_start = 0;
  557. host->part_buf_count = 0;
  558. mci_writel(host, RINTSTS, SDMMC_INT_TXDR | SDMMC_INT_RXDR);
  559. temp = mci_readl(host, INTMASK);
  560. temp |= SDMMC_INT_TXDR | SDMMC_INT_RXDR;
  561. mci_writel(host, INTMASK, temp);
  562. temp = mci_readl(host, CTRL);
  563. temp &= ~SDMMC_CTRL_DMA_ENABLE;
  564. mci_writel(host, CTRL, temp);
  565. /*
  566. * Use the initial fifoth_val for PIO mode.
  567. * If next issued data may be transfered by DMA mode,
  568. * prev_blksz should be invalidated.
  569. */
  570. mci_writel(host, FIFOTH, host->fifoth_val);
  571. host->prev_blksz = 0;
  572. } else {
  573. /*
  574. * Keep the current block size.
  575. * It will be used to decide whether to update
  576. * fifoth register next time.
  577. */
  578. host->prev_blksz = data->blksz;
  579. }
  580. }
  581. static void mci_send_cmd(struct dw_mci_slot *slot, u32 cmd, u32 arg)
  582. {
  583. struct dw_mci *host = slot->host;
  584. unsigned long timeout = jiffies + msecs_to_jiffies(500);
  585. unsigned int cmd_status = 0;
  586. mci_writel(host, CMDARG, arg);
  587. wmb();
  588. mci_writel(host, CMD, SDMMC_CMD_START | cmd);
  589. while (time_before(jiffies, timeout)) {
  590. cmd_status = mci_readl(host, CMD);
  591. if (!(cmd_status & SDMMC_CMD_START))
  592. return;
  593. }
  594. dev_err(&slot->mmc->class_dev,
  595. "Timeout sending command (cmd %#x arg %#x status %#x)\n",
  596. cmd, arg, cmd_status);
  597. }
  598. static void dw_mci_setup_bus(struct dw_mci_slot *slot, bool force_clkinit)
  599. {
  600. struct dw_mci *host = slot->host;
  601. unsigned int clock = slot->clock;
  602. u32 div;
  603. u32 clk_en_a;
  604. if (!clock) {
  605. mci_writel(host, CLKENA, 0);
  606. mci_send_cmd(slot,
  607. SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
  608. } else if (clock != host->current_speed || force_clkinit) {
  609. div = host->bus_hz / clock;
  610. if (host->bus_hz % clock && host->bus_hz > clock)
  611. /*
  612. * move the + 1 after the divide to prevent
  613. * over-clocking the card.
  614. */
  615. div += 1;
  616. div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0;
  617. if ((clock << div) != slot->__clk_old || force_clkinit)
  618. dev_info(&slot->mmc->class_dev,
  619. "Bus speed (slot %d) = %dHz (slot req %dHz, actual %dHZ div = %d)\n",
  620. slot->id, host->bus_hz, clock,
  621. div ? ((host->bus_hz / div) >> 1) :
  622. host->bus_hz, div);
  623. /* disable clock */
  624. mci_writel(host, CLKENA, 0);
  625. mci_writel(host, CLKSRC, 0);
  626. /* inform CIU */
  627. mci_send_cmd(slot,
  628. SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
  629. /* set clock to desired speed */
  630. mci_writel(host, CLKDIV, div);
  631. /* inform CIU */
  632. mci_send_cmd(slot,
  633. SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
  634. /* enable clock; only low power if no SDIO */
  635. clk_en_a = SDMMC_CLKEN_ENABLE << slot->id;
  636. if (!(mci_readl(host, INTMASK) & SDMMC_INT_SDIO(slot->id)))
  637. clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id;
  638. mci_writel(host, CLKENA, clk_en_a);
  639. /* inform CIU */
  640. mci_send_cmd(slot,
  641. SDMMC_CMD_UPD_CLK | SDMMC_CMD_PRV_DAT_WAIT, 0);
  642. /* keep the clock with reflecting clock dividor */
  643. slot->__clk_old = clock << div;
  644. }
  645. host->current_speed = clock;
  646. /* Set the current slot bus width */
  647. mci_writel(host, CTYPE, (slot->ctype << slot->id));
  648. }
  649. static void __dw_mci_start_request(struct dw_mci *host,
  650. struct dw_mci_slot *slot,
  651. struct mmc_command *cmd)
  652. {
  653. struct mmc_request *mrq;
  654. struct mmc_data *data;
  655. u32 cmdflags;
  656. mrq = slot->mrq;
  657. if (host->pdata->select_slot)
  658. host->pdata->select_slot(slot->id);
  659. host->cur_slot = slot;
  660. host->mrq = mrq;
  661. host->pending_events = 0;
  662. host->completed_events = 0;
  663. host->data_status = 0;
  664. data = cmd->data;
  665. if (data) {
  666. dw_mci_set_timeout(host);
  667. mci_writel(host, BYTCNT, data->blksz*data->blocks);
  668. mci_writel(host, BLKSIZ, data->blksz);
  669. }
  670. cmdflags = dw_mci_prepare_command(slot->mmc, cmd);
  671. /* this is the first command, send the initialization clock */
  672. if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags))
  673. cmdflags |= SDMMC_CMD_INIT;
  674. if (data) {
  675. dw_mci_submit_data(host, data);
  676. wmb();
  677. }
  678. dw_mci_start_command(host, cmd, cmdflags);
  679. if (mrq->stop)
  680. host->stop_cmdr = dw_mci_prepare_command(slot->mmc, mrq->stop);
  681. }
  682. static void dw_mci_start_request(struct dw_mci *host,
  683. struct dw_mci_slot *slot)
  684. {
  685. struct mmc_request *mrq = slot->mrq;
  686. struct mmc_command *cmd;
  687. cmd = mrq->sbc ? mrq->sbc : mrq->cmd;
  688. __dw_mci_start_request(host, slot, cmd);
  689. }
  690. /* must be called with host->lock held */
  691. static void dw_mci_queue_request(struct dw_mci *host, struct dw_mci_slot *slot,
  692. struct mmc_request *mrq)
  693. {
  694. dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n",
  695. host->state);
  696. slot->mrq = mrq;
  697. if (host->state == STATE_IDLE) {
  698. host->state = STATE_SENDING_CMD;
  699. dw_mci_start_request(host, slot);
  700. } else {
  701. list_add_tail(&slot->queue_node, &host->queue);
  702. }
  703. }
  704. static void dw_mci_request(struct mmc_host *mmc, struct mmc_request *mrq)
  705. {
  706. struct dw_mci_slot *slot = mmc_priv(mmc);
  707. struct dw_mci *host = slot->host;
  708. WARN_ON(slot->mrq);
  709. /*
  710. * The check for card presence and queueing of the request must be
  711. * atomic, otherwise the card could be removed in between and the
  712. * request wouldn't fail until another card was inserted.
  713. */
  714. spin_lock_bh(&host->lock);
  715. if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) {
  716. spin_unlock_bh(&host->lock);
  717. mrq->cmd->error = -ENOMEDIUM;
  718. mmc_request_done(mmc, mrq);
  719. return;
  720. }
  721. dw_mci_queue_request(host, slot, mrq);
  722. spin_unlock_bh(&host->lock);
  723. }
  724. static void dw_mci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
  725. {
  726. struct dw_mci_slot *slot = mmc_priv(mmc);
  727. const struct dw_mci_drv_data *drv_data = slot->host->drv_data;
  728. u32 regs;
  729. switch (ios->bus_width) {
  730. case MMC_BUS_WIDTH_4:
  731. slot->ctype = SDMMC_CTYPE_4BIT;
  732. break;
  733. case MMC_BUS_WIDTH_8:
  734. slot->ctype = SDMMC_CTYPE_8BIT;
  735. break;
  736. default:
  737. /* set default 1 bit mode */
  738. slot->ctype = SDMMC_CTYPE_1BIT;
  739. }
  740. regs = mci_readl(slot->host, UHS_REG);
  741. /* DDR mode set */
  742. if (ios->timing == MMC_TIMING_UHS_DDR50)
  743. regs |= ((0x1 << slot->id) << 16);
  744. else
  745. regs &= ~((0x1 << slot->id) << 16);
  746. mci_writel(slot->host, UHS_REG, regs);
  747. slot->host->timing = ios->timing;
  748. /*
  749. * Use mirror of ios->clock to prevent race with mmc
  750. * core ios update when finding the minimum.
  751. */
  752. slot->clock = ios->clock;
  753. if (drv_data && drv_data->set_ios)
  754. drv_data->set_ios(slot->host, ios);
  755. /* Slot specific timing and width adjustment */
  756. dw_mci_setup_bus(slot, false);
  757. switch (ios->power_mode) {
  758. case MMC_POWER_UP:
  759. set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags);
  760. /* Power up slot */
  761. if (slot->host->pdata->setpower)
  762. slot->host->pdata->setpower(slot->id, mmc->ocr_avail);
  763. regs = mci_readl(slot->host, PWREN);
  764. regs |= (1 << slot->id);
  765. mci_writel(slot->host, PWREN, regs);
  766. break;
  767. case MMC_POWER_OFF:
  768. /* Power down slot */
  769. if (slot->host->pdata->setpower)
  770. slot->host->pdata->setpower(slot->id, 0);
  771. regs = mci_readl(slot->host, PWREN);
  772. regs &= ~(1 << slot->id);
  773. mci_writel(slot->host, PWREN, regs);
  774. break;
  775. default:
  776. break;
  777. }
  778. }
  779. static int dw_mci_get_ro(struct mmc_host *mmc)
  780. {
  781. int read_only;
  782. struct dw_mci_slot *slot = mmc_priv(mmc);
  783. struct dw_mci_board *brd = slot->host->pdata;
  784. /* Use platform get_ro function, else try on board write protect */
  785. if (slot->quirks & DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT)
  786. read_only = 0;
  787. else if (brd->get_ro)
  788. read_only = brd->get_ro(slot->id);
  789. else if (gpio_is_valid(slot->wp_gpio))
  790. read_only = gpio_get_value(slot->wp_gpio);
  791. else
  792. read_only =
  793. mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0;
  794. dev_dbg(&mmc->class_dev, "card is %s\n",
  795. read_only ? "read-only" : "read-write");
  796. return read_only;
  797. }
  798. static int dw_mci_get_cd(struct mmc_host *mmc)
  799. {
  800. int present;
  801. struct dw_mci_slot *slot = mmc_priv(mmc);
  802. struct dw_mci_board *brd = slot->host->pdata;
  803. /* Use platform get_cd function, else try onboard card detect */
  804. if (brd->quirks & DW_MCI_QUIRK_BROKEN_CARD_DETECTION)
  805. present = 1;
  806. else if (brd->get_cd)
  807. present = !brd->get_cd(slot->id);
  808. else
  809. present = (mci_readl(slot->host, CDETECT) & (1 << slot->id))
  810. == 0 ? 1 : 0;
  811. if (present)
  812. dev_dbg(&mmc->class_dev, "card is present\n");
  813. else
  814. dev_dbg(&mmc->class_dev, "card is not present\n");
  815. return present;
  816. }
  817. /*
  818. * Disable lower power mode.
  819. *
  820. * Low power mode will stop the card clock when idle. According to the
  821. * description of the CLKENA register we should disable low power mode
  822. * for SDIO cards if we need SDIO interrupts to work.
  823. *
  824. * This function is fast if low power mode is already disabled.
  825. */
  826. static void dw_mci_disable_low_power(struct dw_mci_slot *slot)
  827. {
  828. struct dw_mci *host = slot->host;
  829. u32 clk_en_a;
  830. const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id;
  831. clk_en_a = mci_readl(host, CLKENA);
  832. if (clk_en_a & clken_low_pwr) {
  833. mci_writel(host, CLKENA, clk_en_a & ~clken_low_pwr);
  834. mci_send_cmd(slot, SDMMC_CMD_UPD_CLK |
  835. SDMMC_CMD_PRV_DAT_WAIT, 0);
  836. }
  837. }
  838. static void dw_mci_enable_sdio_irq(struct mmc_host *mmc, int enb)
  839. {
  840. struct dw_mci_slot *slot = mmc_priv(mmc);
  841. struct dw_mci *host = slot->host;
  842. u32 int_mask;
  843. /* Enable/disable Slot Specific SDIO interrupt */
  844. int_mask = mci_readl(host, INTMASK);
  845. if (enb) {
  846. /*
  847. * Turn off low power mode if it was enabled. This is a bit of
  848. * a heavy operation and we disable / enable IRQs a lot, so
  849. * we'll leave low power mode disabled and it will get
  850. * re-enabled again in dw_mci_setup_bus().
  851. */
  852. dw_mci_disable_low_power(slot);
  853. mci_writel(host, INTMASK,
  854. (int_mask | SDMMC_INT_SDIO(slot->id)));
  855. } else {
  856. mci_writel(host, INTMASK,
  857. (int_mask & ~SDMMC_INT_SDIO(slot->id)));
  858. }
  859. }
  860. static int dw_mci_execute_tuning(struct mmc_host *mmc, u32 opcode)
  861. {
  862. struct dw_mci_slot *slot = mmc_priv(mmc);
  863. struct dw_mci *host = slot->host;
  864. const struct dw_mci_drv_data *drv_data = host->drv_data;
  865. struct dw_mci_tuning_data tuning_data;
  866. int err = -ENOSYS;
  867. if (opcode == MMC_SEND_TUNING_BLOCK_HS200) {
  868. if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) {
  869. tuning_data.blk_pattern = tuning_blk_pattern_8bit;
  870. tuning_data.blksz = sizeof(tuning_blk_pattern_8bit);
  871. } else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4) {
  872. tuning_data.blk_pattern = tuning_blk_pattern_4bit;
  873. tuning_data.blksz = sizeof(tuning_blk_pattern_4bit);
  874. } else {
  875. return -EINVAL;
  876. }
  877. } else if (opcode == MMC_SEND_TUNING_BLOCK) {
  878. tuning_data.blk_pattern = tuning_blk_pattern_4bit;
  879. tuning_data.blksz = sizeof(tuning_blk_pattern_4bit);
  880. } else {
  881. dev_err(host->dev,
  882. "Undefined command(%d) for tuning\n", opcode);
  883. return -EINVAL;
  884. }
  885. if (drv_data && drv_data->execute_tuning)
  886. err = drv_data->execute_tuning(slot, opcode, &tuning_data);
  887. return err;
  888. }
  889. static const struct mmc_host_ops dw_mci_ops = {
  890. .request = dw_mci_request,
  891. .pre_req = dw_mci_pre_req,
  892. .post_req = dw_mci_post_req,
  893. .set_ios = dw_mci_set_ios,
  894. .get_ro = dw_mci_get_ro,
  895. .get_cd = dw_mci_get_cd,
  896. .enable_sdio_irq = dw_mci_enable_sdio_irq,
  897. .execute_tuning = dw_mci_execute_tuning,
  898. };
  899. static void dw_mci_request_end(struct dw_mci *host, struct mmc_request *mrq)
  900. __releases(&host->lock)
  901. __acquires(&host->lock)
  902. {
  903. struct dw_mci_slot *slot;
  904. struct mmc_host *prev_mmc = host->cur_slot->mmc;
  905. WARN_ON(host->cmd || host->data);
  906. host->cur_slot->mrq = NULL;
  907. host->mrq = NULL;
  908. if (!list_empty(&host->queue)) {
  909. slot = list_entry(host->queue.next,
  910. struct dw_mci_slot, queue_node);
  911. list_del(&slot->queue_node);
  912. dev_vdbg(host->dev, "list not empty: %s is next\n",
  913. mmc_hostname(slot->mmc));
  914. host->state = STATE_SENDING_CMD;
  915. dw_mci_start_request(host, slot);
  916. } else {
  917. dev_vdbg(host->dev, "list empty\n");
  918. host->state = STATE_IDLE;
  919. }
  920. spin_unlock(&host->lock);
  921. mmc_request_done(prev_mmc, mrq);
  922. spin_lock(&host->lock);
  923. }
  924. static void dw_mci_command_complete(struct dw_mci *host, struct mmc_command *cmd)
  925. {
  926. u32 status = host->cmd_status;
  927. host->cmd_status = 0;
  928. /* Read the response from the card (up to 16 bytes) */
  929. if (cmd->flags & MMC_RSP_PRESENT) {
  930. if (cmd->flags & MMC_RSP_136) {
  931. cmd->resp[3] = mci_readl(host, RESP0);
  932. cmd->resp[2] = mci_readl(host, RESP1);
  933. cmd->resp[1] = mci_readl(host, RESP2);
  934. cmd->resp[0] = mci_readl(host, RESP3);
  935. } else {
  936. cmd->resp[0] = mci_readl(host, RESP0);
  937. cmd->resp[1] = 0;
  938. cmd->resp[2] = 0;
  939. cmd->resp[3] = 0;
  940. }
  941. }
  942. if (status & SDMMC_INT_RTO)
  943. cmd->error = -ETIMEDOUT;
  944. else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC))
  945. cmd->error = -EILSEQ;
  946. else if (status & SDMMC_INT_RESP_ERR)
  947. cmd->error = -EIO;
  948. else
  949. cmd->error = 0;
  950. if (cmd->error) {
  951. /* newer ip versions need a delay between retries */
  952. if (host->quirks & DW_MCI_QUIRK_RETRY_DELAY)
  953. mdelay(20);
  954. }
  955. }
  956. static void dw_mci_tasklet_func(unsigned long priv)
  957. {
  958. struct dw_mci *host = (struct dw_mci *)priv;
  959. struct mmc_data *data;
  960. struct mmc_command *cmd;
  961. enum dw_mci_state state;
  962. enum dw_mci_state prev_state;
  963. u32 status, ctrl;
  964. spin_lock(&host->lock);
  965. state = host->state;
  966. data = host->data;
  967. do {
  968. prev_state = state;
  969. switch (state) {
  970. case STATE_IDLE:
  971. break;
  972. case STATE_SENDING_CMD:
  973. if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
  974. &host->pending_events))
  975. break;
  976. cmd = host->cmd;
  977. host->cmd = NULL;
  978. set_bit(EVENT_CMD_COMPLETE, &host->completed_events);
  979. dw_mci_command_complete(host, cmd);
  980. if (cmd == host->mrq->sbc && !cmd->error) {
  981. prev_state = state = STATE_SENDING_CMD;
  982. __dw_mci_start_request(host, host->cur_slot,
  983. host->mrq->cmd);
  984. goto unlock;
  985. }
  986. if (cmd->data && cmd->error) {
  987. dw_mci_stop_dma(host);
  988. if (data->stop) {
  989. send_stop_cmd(host, data);
  990. state = STATE_SENDING_STOP;
  991. break;
  992. } else {
  993. host->data = NULL;
  994. }
  995. }
  996. if (!host->mrq->data || cmd->error) {
  997. dw_mci_request_end(host, host->mrq);
  998. goto unlock;
  999. }
  1000. prev_state = state = STATE_SENDING_DATA;
  1001. /* fall through */
  1002. case STATE_SENDING_DATA:
  1003. if (test_and_clear_bit(EVENT_DATA_ERROR,
  1004. &host->pending_events)) {
  1005. dw_mci_stop_dma(host);
  1006. if (data->stop)
  1007. send_stop_cmd(host, data);
  1008. state = STATE_DATA_ERROR;
  1009. break;
  1010. }
  1011. if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
  1012. &host->pending_events))
  1013. break;
  1014. set_bit(EVENT_XFER_COMPLETE, &host->completed_events);
  1015. prev_state = state = STATE_DATA_BUSY;
  1016. /* fall through */
  1017. case STATE_DATA_BUSY:
  1018. if (!test_and_clear_bit(EVENT_DATA_COMPLETE,
  1019. &host->pending_events))
  1020. break;
  1021. host->data = NULL;
  1022. set_bit(EVENT_DATA_COMPLETE, &host->completed_events);
  1023. status = host->data_status;
  1024. if (status & DW_MCI_DATA_ERROR_FLAGS) {
  1025. if (status & SDMMC_INT_DRTO) {
  1026. data->error = -ETIMEDOUT;
  1027. } else if (status & SDMMC_INT_DCRC) {
  1028. data->error = -EILSEQ;
  1029. } else if (status & SDMMC_INT_EBE &&
  1030. host->dir_status ==
  1031. DW_MCI_SEND_STATUS) {
  1032. /*
  1033. * No data CRC status was returned.
  1034. * The number of bytes transferred will
  1035. * be exaggerated in PIO mode.
  1036. */
  1037. data->bytes_xfered = 0;
  1038. data->error = -ETIMEDOUT;
  1039. } else {
  1040. dev_err(host->dev,
  1041. "data FIFO error "
  1042. "(status=%08x)\n",
  1043. status);
  1044. data->error = -EIO;
  1045. }
  1046. /*
  1047. * After an error, there may be data lingering
  1048. * in the FIFO, so reset it - doing so
  1049. * generates a block interrupt, hence setting
  1050. * the scatter-gather pointer to NULL.
  1051. */
  1052. sg_miter_stop(&host->sg_miter);
  1053. host->sg = NULL;
  1054. ctrl = mci_readl(host, CTRL);
  1055. ctrl |= SDMMC_CTRL_FIFO_RESET;
  1056. mci_writel(host, CTRL, ctrl);
  1057. } else {
  1058. data->bytes_xfered = data->blocks * data->blksz;
  1059. data->error = 0;
  1060. }
  1061. if (!data->stop) {
  1062. dw_mci_request_end(host, host->mrq);
  1063. goto unlock;
  1064. }
  1065. if (host->mrq->sbc && !data->error) {
  1066. data->stop->error = 0;
  1067. dw_mci_request_end(host, host->mrq);
  1068. goto unlock;
  1069. }
  1070. prev_state = state = STATE_SENDING_STOP;
  1071. if (!data->error)
  1072. send_stop_cmd(host, data);
  1073. /* fall through */
  1074. case STATE_SENDING_STOP:
  1075. if (!test_and_clear_bit(EVENT_CMD_COMPLETE,
  1076. &host->pending_events))
  1077. break;
  1078. /* CMD error in data command */
  1079. if (host->mrq->cmd->error && host->mrq->data) {
  1080. sg_miter_stop(&host->sg_miter);
  1081. host->sg = NULL;
  1082. ctrl = mci_readl(host, CTRL);
  1083. ctrl |= SDMMC_CTRL_FIFO_RESET;
  1084. mci_writel(host, CTRL, ctrl);
  1085. }
  1086. host->cmd = NULL;
  1087. host->data = NULL;
  1088. dw_mci_command_complete(host, host->mrq->stop);
  1089. dw_mci_request_end(host, host->mrq);
  1090. goto unlock;
  1091. case STATE_DATA_ERROR:
  1092. if (!test_and_clear_bit(EVENT_XFER_COMPLETE,
  1093. &host->pending_events))
  1094. break;
  1095. state = STATE_DATA_BUSY;
  1096. break;
  1097. }
  1098. } while (state != prev_state);
  1099. host->state = state;
  1100. unlock:
  1101. spin_unlock(&host->lock);
  1102. }
  1103. /* push final bytes to part_buf, only use during push */
  1104. static void dw_mci_set_part_bytes(struct dw_mci *host, void *buf, int cnt)
  1105. {
  1106. memcpy((void *)&host->part_buf, buf, cnt);
  1107. host->part_buf_count = cnt;
  1108. }
  1109. /* append bytes to part_buf, only use during push */
  1110. static int dw_mci_push_part_bytes(struct dw_mci *host, void *buf, int cnt)
  1111. {
  1112. cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count);
  1113. memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt);
  1114. host->part_buf_count += cnt;
  1115. return cnt;
  1116. }
  1117. /* pull first bytes from part_buf, only use during pull */
  1118. static int dw_mci_pull_part_bytes(struct dw_mci *host, void *buf, int cnt)
  1119. {
  1120. cnt = min(cnt, (int)host->part_buf_count);
  1121. if (cnt) {
  1122. memcpy(buf, (void *)&host->part_buf + host->part_buf_start,
  1123. cnt);
  1124. host->part_buf_count -= cnt;
  1125. host->part_buf_start += cnt;
  1126. }
  1127. return cnt;
  1128. }
  1129. /* pull final bytes from the part_buf, assuming it's just been filled */
  1130. static void dw_mci_pull_final_bytes(struct dw_mci *host, void *buf, int cnt)
  1131. {
  1132. memcpy(buf, &host->part_buf, cnt);
  1133. host->part_buf_start = cnt;
  1134. host->part_buf_count = (1 << host->data_shift) - cnt;
  1135. }
  1136. static void dw_mci_push_data16(struct dw_mci *host, void *buf, int cnt)
  1137. {
  1138. struct mmc_data *data = host->data;
  1139. int init_cnt = cnt;
  1140. /* try and push anything in the part_buf */
  1141. if (unlikely(host->part_buf_count)) {
  1142. int len = dw_mci_push_part_bytes(host, buf, cnt);
  1143. buf += len;
  1144. cnt -= len;
  1145. if (host->part_buf_count == 2) {
  1146. mci_writew(host, DATA(host->data_offset),
  1147. host->part_buf16);
  1148. host->part_buf_count = 0;
  1149. }
  1150. }
  1151. #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
  1152. if (unlikely((unsigned long)buf & 0x1)) {
  1153. while (cnt >= 2) {
  1154. u16 aligned_buf[64];
  1155. int len = min(cnt & -2, (int)sizeof(aligned_buf));
  1156. int items = len >> 1;
  1157. int i;
  1158. /* memcpy from input buffer into aligned buffer */
  1159. memcpy(aligned_buf, buf, len);
  1160. buf += len;
  1161. cnt -= len;
  1162. /* push data from aligned buffer into fifo */
  1163. for (i = 0; i < items; ++i)
  1164. mci_writew(host, DATA(host->data_offset),
  1165. aligned_buf[i]);
  1166. }
  1167. } else
  1168. #endif
  1169. {
  1170. u16 *pdata = buf;
  1171. for (; cnt >= 2; cnt -= 2)
  1172. mci_writew(host, DATA(host->data_offset), *pdata++);
  1173. buf = pdata;
  1174. }
  1175. /* put anything remaining in the part_buf */
  1176. if (cnt) {
  1177. dw_mci_set_part_bytes(host, buf, cnt);
  1178. /* Push data if we have reached the expected data length */
  1179. if ((data->bytes_xfered + init_cnt) ==
  1180. (data->blksz * data->blocks))
  1181. mci_writew(host, DATA(host->data_offset),
  1182. host->part_buf16);
  1183. }
  1184. }
  1185. static void dw_mci_pull_data16(struct dw_mci *host, void *buf, int cnt)
  1186. {
  1187. #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
  1188. if (unlikely((unsigned long)buf & 0x1)) {
  1189. while (cnt >= 2) {
  1190. /* pull data from fifo into aligned buffer */
  1191. u16 aligned_buf[64];
  1192. int len = min(cnt & -2, (int)sizeof(aligned_buf));
  1193. int items = len >> 1;
  1194. int i;
  1195. for (i = 0; i < items; ++i)
  1196. aligned_buf[i] = mci_readw(host,
  1197. DATA(host->data_offset));
  1198. /* memcpy from aligned buffer into output buffer */
  1199. memcpy(buf, aligned_buf, len);
  1200. buf += len;
  1201. cnt -= len;
  1202. }
  1203. } else
  1204. #endif
  1205. {
  1206. u16 *pdata = buf;
  1207. for (; cnt >= 2; cnt -= 2)
  1208. *pdata++ = mci_readw(host, DATA(host->data_offset));
  1209. buf = pdata;
  1210. }
  1211. if (cnt) {
  1212. host->part_buf16 = mci_readw(host, DATA(host->data_offset));
  1213. dw_mci_pull_final_bytes(host, buf, cnt);
  1214. }
  1215. }
  1216. static void dw_mci_push_data32(struct dw_mci *host, void *buf, int cnt)
  1217. {
  1218. struct mmc_data *data = host->data;
  1219. int init_cnt = cnt;
  1220. /* try and push anything in the part_buf */
  1221. if (unlikely(host->part_buf_count)) {
  1222. int len = dw_mci_push_part_bytes(host, buf, cnt);
  1223. buf += len;
  1224. cnt -= len;
  1225. if (host->part_buf_count == 4) {
  1226. mci_writel(host, DATA(host->data_offset),
  1227. host->part_buf32);
  1228. host->part_buf_count = 0;
  1229. }
  1230. }
  1231. #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
  1232. if (unlikely((unsigned long)buf & 0x3)) {
  1233. while (cnt >= 4) {
  1234. u32 aligned_buf[32];
  1235. int len = min(cnt & -4, (int)sizeof(aligned_buf));
  1236. int items = len >> 2;
  1237. int i;
  1238. /* memcpy from input buffer into aligned buffer */
  1239. memcpy(aligned_buf, buf, len);
  1240. buf += len;
  1241. cnt -= len;
  1242. /* push data from aligned buffer into fifo */
  1243. for (i = 0; i < items; ++i)
  1244. mci_writel(host, DATA(host->data_offset),
  1245. aligned_buf[i]);
  1246. }
  1247. } else
  1248. #endif
  1249. {
  1250. u32 *pdata = buf;
  1251. for (; cnt >= 4; cnt -= 4)
  1252. mci_writel(host, DATA(host->data_offset), *pdata++);
  1253. buf = pdata;
  1254. }
  1255. /* put anything remaining in the part_buf */
  1256. if (cnt) {
  1257. dw_mci_set_part_bytes(host, buf, cnt);
  1258. /* Push data if we have reached the expected data length */
  1259. if ((data->bytes_xfered + init_cnt) ==
  1260. (data->blksz * data->blocks))
  1261. mci_writel(host, DATA(host->data_offset),
  1262. host->part_buf32);
  1263. }
  1264. }
  1265. static void dw_mci_pull_data32(struct dw_mci *host, void *buf, int cnt)
  1266. {
  1267. #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
  1268. if (unlikely((unsigned long)buf & 0x3)) {
  1269. while (cnt >= 4) {
  1270. /* pull data from fifo into aligned buffer */
  1271. u32 aligned_buf[32];
  1272. int len = min(cnt & -4, (int)sizeof(aligned_buf));
  1273. int items = len >> 2;
  1274. int i;
  1275. for (i = 0; i < items; ++i)
  1276. aligned_buf[i] = mci_readl(host,
  1277. DATA(host->data_offset));
  1278. /* memcpy from aligned buffer into output buffer */
  1279. memcpy(buf, aligned_buf, len);
  1280. buf += len;
  1281. cnt -= len;
  1282. }
  1283. } else
  1284. #endif
  1285. {
  1286. u32 *pdata = buf;
  1287. for (; cnt >= 4; cnt -= 4)
  1288. *pdata++ = mci_readl(host, DATA(host->data_offset));
  1289. buf = pdata;
  1290. }
  1291. if (cnt) {
  1292. host->part_buf32 = mci_readl(host, DATA(host->data_offset));
  1293. dw_mci_pull_final_bytes(host, buf, cnt);
  1294. }
  1295. }
  1296. static void dw_mci_push_data64(struct dw_mci *host, void *buf, int cnt)
  1297. {
  1298. struct mmc_data *data = host->data;
  1299. int init_cnt = cnt;
  1300. /* try and push anything in the part_buf */
  1301. if (unlikely(host->part_buf_count)) {
  1302. int len = dw_mci_push_part_bytes(host, buf, cnt);
  1303. buf += len;
  1304. cnt -= len;
  1305. if (host->part_buf_count == 8) {
  1306. mci_writeq(host, DATA(host->data_offset),
  1307. host->part_buf);
  1308. host->part_buf_count = 0;
  1309. }
  1310. }
  1311. #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
  1312. if (unlikely((unsigned long)buf & 0x7)) {
  1313. while (cnt >= 8) {
  1314. u64 aligned_buf[16];
  1315. int len = min(cnt & -8, (int)sizeof(aligned_buf));
  1316. int items = len >> 3;
  1317. int i;
  1318. /* memcpy from input buffer into aligned buffer */
  1319. memcpy(aligned_buf, buf, len);
  1320. buf += len;
  1321. cnt -= len;
  1322. /* push data from aligned buffer into fifo */
  1323. for (i = 0; i < items; ++i)
  1324. mci_writeq(host, DATA(host->data_offset),
  1325. aligned_buf[i]);
  1326. }
  1327. } else
  1328. #endif
  1329. {
  1330. u64 *pdata = buf;
  1331. for (; cnt >= 8; cnt -= 8)
  1332. mci_writeq(host, DATA(host->data_offset), *pdata++);
  1333. buf = pdata;
  1334. }
  1335. /* put anything remaining in the part_buf */
  1336. if (cnt) {
  1337. dw_mci_set_part_bytes(host, buf, cnt);
  1338. /* Push data if we have reached the expected data length */
  1339. if ((data->bytes_xfered + init_cnt) ==
  1340. (data->blksz * data->blocks))
  1341. mci_writeq(host, DATA(host->data_offset),
  1342. host->part_buf);
  1343. }
  1344. }
  1345. static void dw_mci_pull_data64(struct dw_mci *host, void *buf, int cnt)
  1346. {
  1347. #ifndef CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS
  1348. if (unlikely((unsigned long)buf & 0x7)) {
  1349. while (cnt >= 8) {
  1350. /* pull data from fifo into aligned buffer */
  1351. u64 aligned_buf[16];
  1352. int len = min(cnt & -8, (int)sizeof(aligned_buf));
  1353. int items = len >> 3;
  1354. int i;
  1355. for (i = 0; i < items; ++i)
  1356. aligned_buf[i] = mci_readq(host,
  1357. DATA(host->data_offset));
  1358. /* memcpy from aligned buffer into output buffer */
  1359. memcpy(buf, aligned_buf, len);
  1360. buf += len;
  1361. cnt -= len;
  1362. }
  1363. } else
  1364. #endif
  1365. {
  1366. u64 *pdata = buf;
  1367. for (; cnt >= 8; cnt -= 8)
  1368. *pdata++ = mci_readq(host, DATA(host->data_offset));
  1369. buf = pdata;
  1370. }
  1371. if (cnt) {
  1372. host->part_buf = mci_readq(host, DATA(host->data_offset));
  1373. dw_mci_pull_final_bytes(host, buf, cnt);
  1374. }
  1375. }
  1376. static void dw_mci_pull_data(struct dw_mci *host, void *buf, int cnt)
  1377. {
  1378. int len;
  1379. /* get remaining partial bytes */
  1380. len = dw_mci_pull_part_bytes(host, buf, cnt);
  1381. if (unlikely(len == cnt))
  1382. return;
  1383. buf += len;
  1384. cnt -= len;
  1385. /* get the rest of the data */
  1386. host->pull_data(host, buf, cnt);
  1387. }
  1388. static void dw_mci_read_data_pio(struct dw_mci *host, bool dto)
  1389. {
  1390. struct sg_mapping_iter *sg_miter = &host->sg_miter;
  1391. void *buf;
  1392. unsigned int offset;
  1393. struct mmc_data *data = host->data;
  1394. int shift = host->data_shift;
  1395. u32 status;
  1396. unsigned int len;
  1397. unsigned int remain, fcnt;
  1398. do {
  1399. if (!sg_miter_next(sg_miter))
  1400. goto done;
  1401. host->sg = sg_miter->piter.sg;
  1402. buf = sg_miter->addr;
  1403. remain = sg_miter->length;
  1404. offset = 0;
  1405. do {
  1406. fcnt = (SDMMC_GET_FCNT(mci_readl(host, STATUS))
  1407. << shift) + host->part_buf_count;
  1408. len = min(remain, fcnt);
  1409. if (!len)
  1410. break;
  1411. dw_mci_pull_data(host, (void *)(buf + offset), len);
  1412. data->bytes_xfered += len;
  1413. offset += len;
  1414. remain -= len;
  1415. } while (remain);
  1416. sg_miter->consumed = offset;
  1417. status = mci_readl(host, MINTSTS);
  1418. mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
  1419. /* if the RXDR is ready read again */
  1420. } while ((status & SDMMC_INT_RXDR) ||
  1421. (dto && SDMMC_GET_FCNT(mci_readl(host, STATUS))));
  1422. if (!remain) {
  1423. if (!sg_miter_next(sg_miter))
  1424. goto done;
  1425. sg_miter->consumed = 0;
  1426. }
  1427. sg_miter_stop(sg_miter);
  1428. return;
  1429. done:
  1430. sg_miter_stop(sg_miter);
  1431. host->sg = NULL;
  1432. smp_wmb();
  1433. set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
  1434. }
  1435. static void dw_mci_write_data_pio(struct dw_mci *host)
  1436. {
  1437. struct sg_mapping_iter *sg_miter = &host->sg_miter;
  1438. void *buf;
  1439. unsigned int offset;
  1440. struct mmc_data *data = host->data;
  1441. int shift = host->data_shift;
  1442. u32 status;
  1443. unsigned int len;
  1444. unsigned int fifo_depth = host->fifo_depth;
  1445. unsigned int remain, fcnt;
  1446. do {
  1447. if (!sg_miter_next(sg_miter))
  1448. goto done;
  1449. host->sg = sg_miter->piter.sg;
  1450. buf = sg_miter->addr;
  1451. remain = sg_miter->length;
  1452. offset = 0;
  1453. do {
  1454. fcnt = ((fifo_depth -
  1455. SDMMC_GET_FCNT(mci_readl(host, STATUS)))
  1456. << shift) - host->part_buf_count;
  1457. len = min(remain, fcnt);
  1458. if (!len)
  1459. break;
  1460. host->push_data(host, (void *)(buf + offset), len);
  1461. data->bytes_xfered += len;
  1462. offset += len;
  1463. remain -= len;
  1464. } while (remain);
  1465. sg_miter->consumed = offset;
  1466. status = mci_readl(host, MINTSTS);
  1467. mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
  1468. } while (status & SDMMC_INT_TXDR); /* if TXDR write again */
  1469. if (!remain) {
  1470. if (!sg_miter_next(sg_miter))
  1471. goto done;
  1472. sg_miter->consumed = 0;
  1473. }
  1474. sg_miter_stop(sg_miter);
  1475. return;
  1476. done:
  1477. sg_miter_stop(sg_miter);
  1478. host->sg = NULL;
  1479. smp_wmb();
  1480. set_bit(EVENT_XFER_COMPLETE, &host->pending_events);
  1481. }
  1482. static void dw_mci_cmd_interrupt(struct dw_mci *host, u32 status)
  1483. {
  1484. if (!host->cmd_status)
  1485. host->cmd_status = status;
  1486. smp_wmb();
  1487. set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
  1488. tasklet_schedule(&host->tasklet);
  1489. }
  1490. static irqreturn_t dw_mci_interrupt(int irq, void *dev_id)
  1491. {
  1492. struct dw_mci *host = dev_id;
  1493. u32 pending;
  1494. int i;
  1495. pending = mci_readl(host, MINTSTS); /* read-only mask reg */
  1496. /*
  1497. * DTO fix - version 2.10a and below, and only if internal DMA
  1498. * is configured.
  1499. */
  1500. if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO) {
  1501. if (!pending &&
  1502. ((mci_readl(host, STATUS) >> 17) & 0x1fff))
  1503. pending |= SDMMC_INT_DATA_OVER;
  1504. }
  1505. if (pending) {
  1506. if (pending & DW_MCI_CMD_ERROR_FLAGS) {
  1507. mci_writel(host, RINTSTS, DW_MCI_CMD_ERROR_FLAGS);
  1508. host->cmd_status = pending;
  1509. smp_wmb();
  1510. set_bit(EVENT_CMD_COMPLETE, &host->pending_events);
  1511. }
  1512. if (pending & DW_MCI_DATA_ERROR_FLAGS) {
  1513. /* if there is an error report DATA_ERROR */
  1514. mci_writel(host, RINTSTS, DW_MCI_DATA_ERROR_FLAGS);
  1515. host->data_status = pending;
  1516. smp_wmb();
  1517. set_bit(EVENT_DATA_ERROR, &host->pending_events);
  1518. tasklet_schedule(&host->tasklet);
  1519. }
  1520. if (pending & SDMMC_INT_DATA_OVER) {
  1521. mci_writel(host, RINTSTS, SDMMC_INT_DATA_OVER);
  1522. if (!host->data_status)
  1523. host->data_status = pending;
  1524. smp_wmb();
  1525. if (host->dir_status == DW_MCI_RECV_STATUS) {
  1526. if (host->sg != NULL)
  1527. dw_mci_read_data_pio(host, true);
  1528. }
  1529. set_bit(EVENT_DATA_COMPLETE, &host->pending_events);
  1530. tasklet_schedule(&host->tasklet);
  1531. }
  1532. if (pending & SDMMC_INT_RXDR) {
  1533. mci_writel(host, RINTSTS, SDMMC_INT_RXDR);
  1534. if (host->dir_status == DW_MCI_RECV_STATUS && host->sg)
  1535. dw_mci_read_data_pio(host, false);
  1536. }
  1537. if (pending & SDMMC_INT_TXDR) {
  1538. mci_writel(host, RINTSTS, SDMMC_INT_TXDR);
  1539. if (host->dir_status == DW_MCI_SEND_STATUS && host->sg)
  1540. dw_mci_write_data_pio(host);
  1541. }
  1542. if (pending & SDMMC_INT_CMD_DONE) {
  1543. mci_writel(host, RINTSTS, SDMMC_INT_CMD_DONE);
  1544. dw_mci_cmd_interrupt(host, pending);
  1545. }
  1546. if (pending & SDMMC_INT_CD) {
  1547. mci_writel(host, RINTSTS, SDMMC_INT_CD);
  1548. queue_work(host->card_workqueue, &host->card_work);
  1549. }
  1550. /* Handle SDIO Interrupts */
  1551. for (i = 0; i < host->num_slots; i++) {
  1552. struct dw_mci_slot *slot = host->slot[i];
  1553. if (pending & SDMMC_INT_SDIO(i)) {
  1554. mci_writel(host, RINTSTS, SDMMC_INT_SDIO(i));
  1555. mmc_signal_sdio_irq(slot->mmc);
  1556. }
  1557. }
  1558. }
  1559. #ifdef CONFIG_MMC_DW_IDMAC
  1560. /* Handle DMA interrupts */
  1561. pending = mci_readl(host, IDSTS);
  1562. if (pending & (SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI)) {
  1563. mci_writel(host, IDSTS, SDMMC_IDMAC_INT_TI | SDMMC_IDMAC_INT_RI);
  1564. mci_writel(host, IDSTS, SDMMC_IDMAC_INT_NI);
  1565. host->dma_ops->complete(host);
  1566. }
  1567. #endif
  1568. return IRQ_HANDLED;
  1569. }
  1570. static void dw_mci_work_routine_card(struct work_struct *work)
  1571. {
  1572. struct dw_mci *host = container_of(work, struct dw_mci, card_work);
  1573. int i;
  1574. for (i = 0; i < host->num_slots; i++) {
  1575. struct dw_mci_slot *slot = host->slot[i];
  1576. struct mmc_host *mmc = slot->mmc;
  1577. struct mmc_request *mrq;
  1578. int present;
  1579. u32 ctrl;
  1580. present = dw_mci_get_cd(mmc);
  1581. while (present != slot->last_detect_state) {
  1582. dev_dbg(&slot->mmc->class_dev, "card %s\n",
  1583. present ? "inserted" : "removed");
  1584. spin_lock_bh(&host->lock);
  1585. /* Card change detected */
  1586. slot->last_detect_state = present;
  1587. /* Mark card as present if applicable */
  1588. if (present != 0)
  1589. set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
  1590. /* Clean up queue if present */
  1591. mrq = slot->mrq;
  1592. if (mrq) {
  1593. if (mrq == host->mrq) {
  1594. host->data = NULL;
  1595. host->cmd = NULL;
  1596. switch (host->state) {
  1597. case STATE_IDLE:
  1598. break;
  1599. case STATE_SENDING_CMD:
  1600. mrq->cmd->error = -ENOMEDIUM;
  1601. if (!mrq->data)
  1602. break;
  1603. /* fall through */
  1604. case STATE_SENDING_DATA:
  1605. mrq->data->error = -ENOMEDIUM;
  1606. dw_mci_stop_dma(host);
  1607. break;
  1608. case STATE_DATA_BUSY:
  1609. case STATE_DATA_ERROR:
  1610. if (mrq->data->error == -EINPROGRESS)
  1611. mrq->data->error = -ENOMEDIUM;
  1612. if (!mrq->stop)
  1613. break;
  1614. /* fall through */
  1615. case STATE_SENDING_STOP:
  1616. mrq->stop->error = -ENOMEDIUM;
  1617. break;
  1618. }
  1619. dw_mci_request_end(host, mrq);
  1620. } else {
  1621. list_del(&slot->queue_node);
  1622. mrq->cmd->error = -ENOMEDIUM;
  1623. if (mrq->data)
  1624. mrq->data->error = -ENOMEDIUM;
  1625. if (mrq->stop)
  1626. mrq->stop->error = -ENOMEDIUM;
  1627. spin_unlock(&host->lock);
  1628. mmc_request_done(slot->mmc, mrq);
  1629. spin_lock(&host->lock);
  1630. }
  1631. }
  1632. /* Power down slot */
  1633. if (present == 0) {
  1634. clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
  1635. /*
  1636. * Clear down the FIFO - doing so generates a
  1637. * block interrupt, hence setting the
  1638. * scatter-gather pointer to NULL.
  1639. */
  1640. sg_miter_stop(&host->sg_miter);
  1641. host->sg = NULL;
  1642. ctrl = mci_readl(host, CTRL);
  1643. ctrl |= SDMMC_CTRL_FIFO_RESET;
  1644. mci_writel(host, CTRL, ctrl);
  1645. #ifdef CONFIG_MMC_DW_IDMAC
  1646. ctrl = mci_readl(host, BMOD);
  1647. /* Software reset of DMA */
  1648. ctrl |= SDMMC_IDMAC_SWRESET;
  1649. mci_writel(host, BMOD, ctrl);
  1650. #endif
  1651. }
  1652. spin_unlock_bh(&host->lock);
  1653. present = dw_mci_get_cd(mmc);
  1654. }
  1655. mmc_detect_change(slot->mmc,
  1656. msecs_to_jiffies(host->pdata->detect_delay_ms));
  1657. }
  1658. }
  1659. #ifdef CONFIG_OF
  1660. /* given a slot id, find out the device node representing that slot */
  1661. static struct device_node *dw_mci_of_find_slot_node(struct device *dev, u8 slot)
  1662. {
  1663. struct device_node *np;
  1664. const __be32 *addr;
  1665. int len;
  1666. if (!dev || !dev->of_node)
  1667. return NULL;
  1668. for_each_child_of_node(dev->of_node, np) {
  1669. addr = of_get_property(np, "reg", &len);
  1670. if (!addr || (len < sizeof(int)))
  1671. continue;
  1672. if (be32_to_cpup(addr) == slot)
  1673. return np;
  1674. }
  1675. return NULL;
  1676. }
  1677. static struct dw_mci_of_slot_quirks {
  1678. char *quirk;
  1679. int id;
  1680. } of_slot_quirks[] = {
  1681. {
  1682. .quirk = "disable-wp",
  1683. .id = DW_MCI_SLOT_QUIRK_NO_WRITE_PROTECT,
  1684. },
  1685. };
  1686. static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot)
  1687. {
  1688. struct device_node *np = dw_mci_of_find_slot_node(dev, slot);
  1689. int quirks = 0;
  1690. int idx;
  1691. /* get quirks */
  1692. for (idx = 0; idx < ARRAY_SIZE(of_slot_quirks); idx++)
  1693. if (of_get_property(np, of_slot_quirks[idx].quirk, NULL))
  1694. quirks |= of_slot_quirks[idx].id;
  1695. return quirks;
  1696. }
  1697. /* find out bus-width for a given slot */
  1698. static u32 dw_mci_of_get_bus_wd(struct device *dev, u8 slot)
  1699. {
  1700. struct device_node *np = dw_mci_of_find_slot_node(dev, slot);
  1701. u32 bus_wd = 1;
  1702. if (!np)
  1703. return 1;
  1704. if (of_property_read_u32(np, "bus-width", &bus_wd))
  1705. dev_err(dev, "bus-width property not found, assuming width"
  1706. " as 1\n");
  1707. return bus_wd;
  1708. }
  1709. /* find the write protect gpio for a given slot; or -1 if none specified */
  1710. static int dw_mci_of_get_wp_gpio(struct device *dev, u8 slot)
  1711. {
  1712. struct device_node *np = dw_mci_of_find_slot_node(dev, slot);
  1713. int gpio;
  1714. if (!np)
  1715. return -EINVAL;
  1716. gpio = of_get_named_gpio(np, "wp-gpios", 0);
  1717. /* Having a missing entry is valid; return silently */
  1718. if (!gpio_is_valid(gpio))
  1719. return -EINVAL;
  1720. if (devm_gpio_request(dev, gpio, "dw-mci-wp")) {
  1721. dev_warn(dev, "gpio [%d] request failed\n", gpio);
  1722. return -EINVAL;
  1723. }
  1724. return gpio;
  1725. }
  1726. #else /* CONFIG_OF */
  1727. static int dw_mci_of_get_slot_quirks(struct device *dev, u8 slot)
  1728. {
  1729. return 0;
  1730. }
  1731. static u32 dw_mci_of_get_bus_wd(struct device *dev, u8 slot)
  1732. {
  1733. return 1;
  1734. }
  1735. static struct device_node *dw_mci_of_find_slot_node(struct device *dev, u8 slot)
  1736. {
  1737. return NULL;
  1738. }
  1739. static int dw_mci_of_get_wp_gpio(struct device *dev, u8 slot)
  1740. {
  1741. return -EINVAL;
  1742. }
  1743. #endif /* CONFIG_OF */
  1744. static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
  1745. {
  1746. struct mmc_host *mmc;
  1747. struct dw_mci_slot *slot;
  1748. const struct dw_mci_drv_data *drv_data = host->drv_data;
  1749. int ctrl_id, ret;
  1750. u32 freq[2];
  1751. u8 bus_width;
  1752. mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev);
  1753. if (!mmc)
  1754. return -ENOMEM;
  1755. slot = mmc_priv(mmc);
  1756. slot->id = id;
  1757. slot->mmc = mmc;
  1758. slot->host = host;
  1759. host->slot[id] = slot;
  1760. slot->quirks = dw_mci_of_get_slot_quirks(host->dev, slot->id);
  1761. mmc->ops = &dw_mci_ops;
  1762. if (of_property_read_u32_array(host->dev->of_node,
  1763. "clock-freq-min-max", freq, 2)) {
  1764. mmc->f_min = DW_MCI_FREQ_MIN;
  1765. mmc->f_max = DW_MCI_FREQ_MAX;
  1766. } else {
  1767. mmc->f_min = freq[0];
  1768. mmc->f_max = freq[1];
  1769. }
  1770. if (host->pdata->get_ocr)
  1771. mmc->ocr_avail = host->pdata->get_ocr(id);
  1772. else
  1773. mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34;
  1774. /*
  1775. * Start with slot power disabled, it will be enabled when a card
  1776. * is detected.
  1777. */
  1778. if (host->pdata->setpower)
  1779. host->pdata->setpower(id, 0);
  1780. if (host->pdata->caps)
  1781. mmc->caps = host->pdata->caps;
  1782. if (host->pdata->pm_caps)
  1783. mmc->pm_caps = host->pdata->pm_caps;
  1784. if (host->dev->of_node) {
  1785. ctrl_id = of_alias_get_id(host->dev->of_node, "mshc");
  1786. if (ctrl_id < 0)
  1787. ctrl_id = 0;
  1788. } else {
  1789. ctrl_id = to_platform_device(host->dev)->id;
  1790. }
  1791. if (drv_data && drv_data->caps)
  1792. mmc->caps |= drv_data->caps[ctrl_id];
  1793. if (host->pdata->caps2)
  1794. mmc->caps2 = host->pdata->caps2;
  1795. if (host->pdata->get_bus_wd)
  1796. bus_width = host->pdata->get_bus_wd(slot->id);
  1797. else if (host->dev->of_node)
  1798. bus_width = dw_mci_of_get_bus_wd(host->dev, slot->id);
  1799. else
  1800. bus_width = 1;
  1801. switch (bus_width) {
  1802. case 8:
  1803. mmc->caps |= MMC_CAP_8_BIT_DATA;
  1804. case 4:
  1805. mmc->caps |= MMC_CAP_4_BIT_DATA;
  1806. }
  1807. if (host->pdata->blk_settings) {
  1808. mmc->max_segs = host->pdata->blk_settings->max_segs;
  1809. mmc->max_blk_size = host->pdata->blk_settings->max_blk_size;
  1810. mmc->max_blk_count = host->pdata->blk_settings->max_blk_count;
  1811. mmc->max_req_size = host->pdata->blk_settings->max_req_size;
  1812. mmc->max_seg_size = host->pdata->blk_settings->max_seg_size;
  1813. } else {
  1814. /* Useful defaults if platform data is unset. */
  1815. #ifdef CONFIG_MMC_DW_IDMAC
  1816. mmc->max_segs = host->ring_size;
  1817. mmc->max_blk_size = 65536;
  1818. mmc->max_blk_count = host->ring_size;
  1819. mmc->max_seg_size = 0x1000;
  1820. mmc->max_req_size = mmc->max_seg_size * mmc->max_blk_count;
  1821. #else
  1822. mmc->max_segs = 64;
  1823. mmc->max_blk_size = 65536; /* BLKSIZ is 16 bits */
  1824. mmc->max_blk_count = 512;
  1825. mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
  1826. mmc->max_seg_size = mmc->max_req_size;
  1827. #endif /* CONFIG_MMC_DW_IDMAC */
  1828. }
  1829. if (dw_mci_get_cd(mmc))
  1830. set_bit(DW_MMC_CARD_PRESENT, &slot->flags);
  1831. else
  1832. clear_bit(DW_MMC_CARD_PRESENT, &slot->flags);
  1833. slot->wp_gpio = dw_mci_of_get_wp_gpio(host->dev, slot->id);
  1834. ret = mmc_add_host(mmc);
  1835. if (ret)
  1836. goto err_setup_bus;
  1837. #if defined(CONFIG_DEBUG_FS)
  1838. dw_mci_init_debugfs(slot);
  1839. #endif
  1840. /* Card initially undetected */
  1841. slot->last_detect_state = 0;
  1842. return 0;
  1843. err_setup_bus:
  1844. mmc_free_host(mmc);
  1845. return -EINVAL;
  1846. }
  1847. static void dw_mci_cleanup_slot(struct dw_mci_slot *slot, unsigned int id)
  1848. {
  1849. /* Shutdown detect IRQ */
  1850. if (slot->host->pdata->exit)
  1851. slot->host->pdata->exit(id);
  1852. /* Debugfs stuff is cleaned up by mmc core */
  1853. mmc_remove_host(slot->mmc);
  1854. slot->host->slot[id] = NULL;
  1855. mmc_free_host(slot->mmc);
  1856. }
  1857. static void dw_mci_init_dma(struct dw_mci *host)
  1858. {
  1859. /* Alloc memory for sg translation */
  1860. host->sg_cpu = dmam_alloc_coherent(host->dev, PAGE_SIZE,
  1861. &host->sg_dma, GFP_KERNEL);
  1862. if (!host->sg_cpu) {
  1863. dev_err(host->dev, "%s: could not alloc DMA memory\n",
  1864. __func__);
  1865. goto no_dma;
  1866. }
  1867. /* Determine which DMA interface to use */
  1868. #ifdef CONFIG_MMC_DW_IDMAC
  1869. host->dma_ops = &dw_mci_idmac_ops;
  1870. dev_info(host->dev, "Using internal DMA controller.\n");
  1871. #endif
  1872. if (!host->dma_ops)
  1873. goto no_dma;
  1874. if (host->dma_ops->init && host->dma_ops->start &&
  1875. host->dma_ops->stop && host->dma_ops->cleanup) {
  1876. if (host->dma_ops->init(host)) {
  1877. dev_err(host->dev, "%s: Unable to initialize "
  1878. "DMA Controller.\n", __func__);
  1879. goto no_dma;
  1880. }
  1881. } else {
  1882. dev_err(host->dev, "DMA initialization not found.\n");
  1883. goto no_dma;
  1884. }
  1885. host->use_dma = 1;
  1886. return;
  1887. no_dma:
  1888. dev_info(host->dev, "Using PIO mode.\n");
  1889. host->use_dma = 0;
  1890. return;
  1891. }
  1892. static bool mci_wait_reset(struct device *dev, struct dw_mci *host)
  1893. {
  1894. unsigned long timeout = jiffies + msecs_to_jiffies(500);
  1895. unsigned int ctrl;
  1896. mci_writel(host, CTRL, (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET |
  1897. SDMMC_CTRL_DMA_RESET));
  1898. /* wait till resets clear */
  1899. do {
  1900. ctrl = mci_readl(host, CTRL);
  1901. if (!(ctrl & (SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET |
  1902. SDMMC_CTRL_DMA_RESET)))
  1903. return true;
  1904. } while (time_before(jiffies, timeout));
  1905. dev_err(dev, "Timeout resetting block (ctrl %#x)\n", ctrl);
  1906. return false;
  1907. }
  1908. #ifdef CONFIG_OF
  1909. static struct dw_mci_of_quirks {
  1910. char *quirk;
  1911. int id;
  1912. } of_quirks[] = {
  1913. {
  1914. .quirk = "broken-cd",
  1915. .id = DW_MCI_QUIRK_BROKEN_CARD_DETECTION,
  1916. },
  1917. };
  1918. static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
  1919. {
  1920. struct dw_mci_board *pdata;
  1921. struct device *dev = host->dev;
  1922. struct device_node *np = dev->of_node;
  1923. const struct dw_mci_drv_data *drv_data = host->drv_data;
  1924. int idx, ret;
  1925. u32 clock_frequency;
  1926. pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
  1927. if (!pdata) {
  1928. dev_err(dev, "could not allocate memory for pdata\n");
  1929. return ERR_PTR(-ENOMEM);
  1930. }
  1931. /* find out number of slots supported */
  1932. if (of_property_read_u32(dev->of_node, "num-slots",
  1933. &pdata->num_slots)) {
  1934. dev_info(dev, "num-slots property not found, "
  1935. "assuming 1 slot is available\n");
  1936. pdata->num_slots = 1;
  1937. }
  1938. /* get quirks */
  1939. for (idx = 0; idx < ARRAY_SIZE(of_quirks); idx++)
  1940. if (of_get_property(np, of_quirks[idx].quirk, NULL))
  1941. pdata->quirks |= of_quirks[idx].id;
  1942. if (of_property_read_u32(np, "fifo-depth", &pdata->fifo_depth))
  1943. dev_info(dev, "fifo-depth property not found, using "
  1944. "value of FIFOTH register as default\n");
  1945. of_property_read_u32(np, "card-detect-delay", &pdata->detect_delay_ms);
  1946. if (!of_property_read_u32(np, "clock-frequency", &clock_frequency))
  1947. pdata->bus_hz = clock_frequency;
  1948. if (drv_data && drv_data->parse_dt) {
  1949. ret = drv_data->parse_dt(host);
  1950. if (ret)
  1951. return ERR_PTR(ret);
  1952. }
  1953. if (of_find_property(np, "keep-power-in-suspend", NULL))
  1954. pdata->pm_caps |= MMC_PM_KEEP_POWER;
  1955. if (of_find_property(np, "enable-sdio-wakeup", NULL))
  1956. pdata->pm_caps |= MMC_PM_WAKE_SDIO_IRQ;
  1957. if (of_find_property(np, "supports-highspeed", NULL))
  1958. pdata->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED;
  1959. if (of_find_property(np, "caps2-mmc-hs200-1_8v", NULL))
  1960. pdata->caps2 |= MMC_CAP2_HS200_1_8V_SDR;
  1961. if (of_find_property(np, "caps2-mmc-hs200-1_2v", NULL))
  1962. pdata->caps2 |= MMC_CAP2_HS200_1_2V_SDR;
  1963. return pdata;
  1964. }
  1965. #else /* CONFIG_OF */
  1966. static struct dw_mci_board *dw_mci_parse_dt(struct dw_mci *host)
  1967. {
  1968. return ERR_PTR(-EINVAL);
  1969. }
  1970. #endif /* CONFIG_OF */
  1971. int dw_mci_probe(struct dw_mci *host)
  1972. {
  1973. const struct dw_mci_drv_data *drv_data = host->drv_data;
  1974. int width, i, ret = 0;
  1975. u32 fifo_size;
  1976. int init_slots = 0;
  1977. if (!host->pdata) {
  1978. host->pdata = dw_mci_parse_dt(host);
  1979. if (IS_ERR(host->pdata)) {
  1980. dev_err(host->dev, "platform data not available\n");
  1981. return -EINVAL;
  1982. }
  1983. }
  1984. if (!host->pdata->select_slot && host->pdata->num_slots > 1) {
  1985. dev_err(host->dev,
  1986. "Platform data must supply select_slot function\n");
  1987. return -ENODEV;
  1988. }
  1989. host->biu_clk = devm_clk_get(host->dev, "biu");
  1990. if (IS_ERR(host->biu_clk)) {
  1991. dev_dbg(host->dev, "biu clock not available\n");
  1992. } else {
  1993. ret = clk_prepare_enable(host->biu_clk);
  1994. if (ret) {
  1995. dev_err(host->dev, "failed to enable biu clock\n");
  1996. return ret;
  1997. }
  1998. }
  1999. host->ciu_clk = devm_clk_get(host->dev, "ciu");
  2000. if (IS_ERR(host->ciu_clk)) {
  2001. dev_dbg(host->dev, "ciu clock not available\n");
  2002. host->bus_hz = host->pdata->bus_hz;
  2003. } else {
  2004. ret = clk_prepare_enable(host->ciu_clk);
  2005. if (ret) {
  2006. dev_err(host->dev, "failed to enable ciu clock\n");
  2007. goto err_clk_biu;
  2008. }
  2009. if (host->pdata->bus_hz) {
  2010. ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz);
  2011. if (ret)
  2012. dev_warn(host->dev,
  2013. "Unable to set bus rate to %ul\n",
  2014. host->pdata->bus_hz);
  2015. }
  2016. host->bus_hz = clk_get_rate(host->ciu_clk);
  2017. }
  2018. if (drv_data && drv_data->init) {
  2019. ret = drv_data->init(host);
  2020. if (ret) {
  2021. dev_err(host->dev,
  2022. "implementation specific init failed\n");
  2023. goto err_clk_ciu;
  2024. }
  2025. }
  2026. if (drv_data && drv_data->setup_clock) {
  2027. ret = drv_data->setup_clock(host);
  2028. if (ret) {
  2029. dev_err(host->dev,
  2030. "implementation specific clock setup failed\n");
  2031. goto err_clk_ciu;
  2032. }
  2033. }
  2034. host->vmmc = devm_regulator_get_optional(host->dev, "vmmc");
  2035. if (IS_ERR(host->vmmc)) {
  2036. ret = PTR_ERR(host->vmmc);
  2037. if (ret == -EPROBE_DEFER)
  2038. goto err_clk_ciu;
  2039. dev_info(host->dev, "no vmmc regulator found: %d\n", ret);
  2040. host->vmmc = NULL;
  2041. } else {
  2042. ret = regulator_enable(host->vmmc);
  2043. if (ret) {
  2044. if (ret != -EPROBE_DEFER)
  2045. dev_err(host->dev,
  2046. "regulator_enable fail: %d\n", ret);
  2047. goto err_clk_ciu;
  2048. }
  2049. }
  2050. if (!host->bus_hz) {
  2051. dev_err(host->dev,
  2052. "Platform data must supply bus speed\n");
  2053. ret = -ENODEV;
  2054. goto err_regulator;
  2055. }
  2056. host->quirks = host->pdata->quirks;
  2057. spin_lock_init(&host->lock);
  2058. INIT_LIST_HEAD(&host->queue);
  2059. /*
  2060. * Get the host data width - this assumes that HCON has been set with
  2061. * the correct values.
  2062. */
  2063. i = (mci_readl(host, HCON) >> 7) & 0x7;
  2064. if (!i) {
  2065. host->push_data = dw_mci_push_data16;
  2066. host->pull_data = dw_mci_pull_data16;
  2067. width = 16;
  2068. host->data_shift = 1;
  2069. } else if (i == 2) {
  2070. host->push_data = dw_mci_push_data64;
  2071. host->pull_data = dw_mci_pull_data64;
  2072. width = 64;
  2073. host->data_shift = 3;
  2074. } else {
  2075. /* Check for a reserved value, and warn if it is */
  2076. WARN((i != 1),
  2077. "HCON reports a reserved host data width!\n"
  2078. "Defaulting to 32-bit access.\n");
  2079. host->push_data = dw_mci_push_data32;
  2080. host->pull_data = dw_mci_pull_data32;
  2081. width = 32;
  2082. host->data_shift = 2;
  2083. }
  2084. /* Reset all blocks */
  2085. if (!mci_wait_reset(host->dev, host))
  2086. return -ENODEV;
  2087. host->dma_ops = host->pdata->dma_ops;
  2088. dw_mci_init_dma(host);
  2089. /* Clear the interrupts for the host controller */
  2090. mci_writel(host, RINTSTS, 0xFFFFFFFF);
  2091. mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
  2092. /* Put in max timeout */
  2093. mci_writel(host, TMOUT, 0xFFFFFFFF);
  2094. /*
  2095. * FIFO threshold settings RxMark = fifo_size / 2 - 1,
  2096. * Tx Mark = fifo_size / 2 DMA Size = 8
  2097. */
  2098. if (!host->pdata->fifo_depth) {
  2099. /*
  2100. * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may
  2101. * have been overwritten by the bootloader, just like we're
  2102. * about to do, so if you know the value for your hardware, you
  2103. * should put it in the platform data.
  2104. */
  2105. fifo_size = mci_readl(host, FIFOTH);
  2106. fifo_size = 1 + ((fifo_size >> 16) & 0xfff);
  2107. } else {
  2108. fifo_size = host->pdata->fifo_depth;
  2109. }
  2110. host->fifo_depth = fifo_size;
  2111. host->fifoth_val =
  2112. SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2);
  2113. mci_writel(host, FIFOTH, host->fifoth_val);
  2114. /* disable clock to CIU */
  2115. mci_writel(host, CLKENA, 0);
  2116. mci_writel(host, CLKSRC, 0);
  2117. /*
  2118. * In 2.40a spec, Data offset is changed.
  2119. * Need to check the version-id and set data-offset for DATA register.
  2120. */
  2121. host->verid = SDMMC_GET_VERID(mci_readl(host, VERID));
  2122. dev_info(host->dev, "Version ID is %04x\n", host->verid);
  2123. if (host->verid < DW_MMC_240A)
  2124. host->data_offset = DATA_OFFSET;
  2125. else
  2126. host->data_offset = DATA_240A_OFFSET;
  2127. tasklet_init(&host->tasklet, dw_mci_tasklet_func, (unsigned long)host);
  2128. host->card_workqueue = alloc_workqueue("dw-mci-card",
  2129. WQ_MEM_RECLAIM | WQ_NON_REENTRANT, 1);
  2130. if (!host->card_workqueue) {
  2131. ret = -ENOMEM;
  2132. goto err_dmaunmap;
  2133. }
  2134. INIT_WORK(&host->card_work, dw_mci_work_routine_card);
  2135. ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt,
  2136. host->irq_flags, "dw-mci", host);
  2137. if (ret)
  2138. goto err_workqueue;
  2139. if (host->pdata->num_slots)
  2140. host->num_slots = host->pdata->num_slots;
  2141. else
  2142. host->num_slots = ((mci_readl(host, HCON) >> 1) & 0x1F) + 1;
  2143. /*
  2144. * Enable interrupts for command done, data over, data empty, card det,
  2145. * receive ready and error such as transmit, receive timeout, crc error
  2146. */
  2147. mci_writel(host, RINTSTS, 0xFFFFFFFF);
  2148. mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
  2149. SDMMC_INT_TXDR | SDMMC_INT_RXDR |
  2150. DW_MCI_ERROR_FLAGS | SDMMC_INT_CD);
  2151. mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); /* Enable mci interrupt */
  2152. dev_info(host->dev, "DW MMC controller at irq %d, "
  2153. "%d bit host data width, "
  2154. "%u deep fifo\n",
  2155. host->irq, width, fifo_size);
  2156. /* We need at least one slot to succeed */
  2157. for (i = 0; i < host->num_slots; i++) {
  2158. ret = dw_mci_init_slot(host, i);
  2159. if (ret)
  2160. dev_dbg(host->dev, "slot %d init failed\n", i);
  2161. else
  2162. init_slots++;
  2163. }
  2164. if (init_slots) {
  2165. dev_info(host->dev, "%d slots initialized\n", init_slots);
  2166. } else {
  2167. dev_dbg(host->dev, "attempted to initialize %d slots, "
  2168. "but failed on all\n", host->num_slots);
  2169. goto err_workqueue;
  2170. }
  2171. if (host->quirks & DW_MCI_QUIRK_IDMAC_DTO)
  2172. dev_info(host->dev, "Internal DMAC interrupt fix enabled.\n");
  2173. return 0;
  2174. err_workqueue:
  2175. destroy_workqueue(host->card_workqueue);
  2176. err_dmaunmap:
  2177. if (host->use_dma && host->dma_ops->exit)
  2178. host->dma_ops->exit(host);
  2179. err_regulator:
  2180. if (host->vmmc)
  2181. regulator_disable(host->vmmc);
  2182. err_clk_ciu:
  2183. if (!IS_ERR(host->ciu_clk))
  2184. clk_disable_unprepare(host->ciu_clk);
  2185. err_clk_biu:
  2186. if (!IS_ERR(host->biu_clk))
  2187. clk_disable_unprepare(host->biu_clk);
  2188. return ret;
  2189. }
  2190. EXPORT_SYMBOL(dw_mci_probe);
  2191. void dw_mci_remove(struct dw_mci *host)
  2192. {
  2193. int i;
  2194. mci_writel(host, RINTSTS, 0xFFFFFFFF);
  2195. mci_writel(host, INTMASK, 0); /* disable all mmc interrupt first */
  2196. for (i = 0; i < host->num_slots; i++) {
  2197. dev_dbg(host->dev, "remove slot %d\n", i);
  2198. if (host->slot[i])
  2199. dw_mci_cleanup_slot(host->slot[i], i);
  2200. }
  2201. /* disable clock to CIU */
  2202. mci_writel(host, CLKENA, 0);
  2203. mci_writel(host, CLKSRC, 0);
  2204. destroy_workqueue(host->card_workqueue);
  2205. if (host->use_dma && host->dma_ops->exit)
  2206. host->dma_ops->exit(host);
  2207. if (host->vmmc)
  2208. regulator_disable(host->vmmc);
  2209. if (!IS_ERR(host->ciu_clk))
  2210. clk_disable_unprepare(host->ciu_clk);
  2211. if (!IS_ERR(host->biu_clk))
  2212. clk_disable_unprepare(host->biu_clk);
  2213. }
  2214. EXPORT_SYMBOL(dw_mci_remove);
  2215. #ifdef CONFIG_PM_SLEEP
  2216. /*
  2217. * TODO: we should probably disable the clock to the card in the suspend path.
  2218. */
  2219. int dw_mci_suspend(struct dw_mci *host)
  2220. {
  2221. int i, ret = 0;
  2222. for (i = 0; i < host->num_slots; i++) {
  2223. struct dw_mci_slot *slot = host->slot[i];
  2224. if (!slot)
  2225. continue;
  2226. ret = mmc_suspend_host(slot->mmc);
  2227. if (ret < 0) {
  2228. while (--i >= 0) {
  2229. slot = host->slot[i];
  2230. if (slot)
  2231. mmc_resume_host(host->slot[i]->mmc);
  2232. }
  2233. return ret;
  2234. }
  2235. }
  2236. if (host->vmmc)
  2237. regulator_disable(host->vmmc);
  2238. return 0;
  2239. }
  2240. EXPORT_SYMBOL(dw_mci_suspend);
  2241. int dw_mci_resume(struct dw_mci *host)
  2242. {
  2243. int i, ret;
  2244. if (host->vmmc) {
  2245. ret = regulator_enable(host->vmmc);
  2246. if (ret) {
  2247. dev_err(host->dev,
  2248. "failed to enable regulator: %d\n", ret);
  2249. return ret;
  2250. }
  2251. }
  2252. if (!mci_wait_reset(host->dev, host)) {
  2253. ret = -ENODEV;
  2254. return ret;
  2255. }
  2256. if (host->use_dma && host->dma_ops->init)
  2257. host->dma_ops->init(host);
  2258. /*
  2259. * Restore the initial value at FIFOTH register
  2260. * And Invalidate the prev_blksz with zero
  2261. */
  2262. mci_writel(host, FIFOTH, host->fifoth_val);
  2263. host->prev_blksz = 0;
  2264. /* Put in max timeout */
  2265. mci_writel(host, TMOUT, 0xFFFFFFFF);
  2266. mci_writel(host, RINTSTS, 0xFFFFFFFF);
  2267. mci_writel(host, INTMASK, SDMMC_INT_CMD_DONE | SDMMC_INT_DATA_OVER |
  2268. SDMMC_INT_TXDR | SDMMC_INT_RXDR |
  2269. DW_MCI_ERROR_FLAGS | SDMMC_INT_CD);
  2270. mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE);
  2271. for (i = 0; i < host->num_slots; i++) {
  2272. struct dw_mci_slot *slot = host->slot[i];
  2273. if (!slot)
  2274. continue;
  2275. if (slot->mmc->pm_flags & MMC_PM_KEEP_POWER) {
  2276. dw_mci_set_ios(slot->mmc, &slot->mmc->ios);
  2277. dw_mci_setup_bus(slot, true);
  2278. }
  2279. ret = mmc_resume_host(host->slot[i]->mmc);
  2280. if (ret < 0)
  2281. return ret;
  2282. }
  2283. return 0;
  2284. }
  2285. EXPORT_SYMBOL(dw_mci_resume);
  2286. #endif /* CONFIG_PM_SLEEP */
  2287. static int __init dw_mci_init(void)
  2288. {
  2289. pr_info("Synopsys Designware Multimedia Card Interface Driver\n");
  2290. return 0;
  2291. }
  2292. static void __exit dw_mci_exit(void)
  2293. {
  2294. }
  2295. module_init(dw_mci_init);
  2296. module_exit(dw_mci_exit);
  2297. MODULE_DESCRIPTION("DW Multimedia Card Interface driver");
  2298. MODULE_AUTHOR("NXP Semiconductor VietNam");
  2299. MODULE_AUTHOR("Imagination Technologies Ltd");
  2300. MODULE_LICENSE("GPL v2");