en_rx.c 29 KB

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  1. /*
  2. * Copyright (c) 2007 Mellanox Technologies. All rights reserved.
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * OpenIB.org BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and/or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. *
  32. */
  33. #include <net/busy_poll.h>
  34. #include <linux/mlx4/cq.h>
  35. #include <linux/slab.h>
  36. #include <linux/mlx4/qp.h>
  37. #include <linux/skbuff.h>
  38. #include <linux/rculist.h>
  39. #include <linux/if_ether.h>
  40. #include <linux/if_vlan.h>
  41. #include <linux/vmalloc.h>
  42. #include "mlx4_en.h"
  43. static int mlx4_alloc_pages(struct mlx4_en_priv *priv,
  44. struct mlx4_en_rx_alloc *page_alloc,
  45. const struct mlx4_en_frag_info *frag_info,
  46. gfp_t _gfp)
  47. {
  48. int order;
  49. struct page *page;
  50. dma_addr_t dma;
  51. for (order = MLX4_EN_ALLOC_PREFER_ORDER; ;) {
  52. gfp_t gfp = _gfp;
  53. if (order)
  54. gfp |= __GFP_COMP | __GFP_NOWARN;
  55. page = alloc_pages(gfp, order);
  56. if (likely(page))
  57. break;
  58. if (--order < 0 ||
  59. ((PAGE_SIZE << order) < frag_info->frag_size))
  60. return -ENOMEM;
  61. }
  62. dma = dma_map_page(priv->ddev, page, 0, PAGE_SIZE << order,
  63. PCI_DMA_FROMDEVICE);
  64. if (dma_mapping_error(priv->ddev, dma)) {
  65. put_page(page);
  66. return -ENOMEM;
  67. }
  68. page_alloc->page_size = PAGE_SIZE << order;
  69. page_alloc->page = page;
  70. page_alloc->dma = dma;
  71. page_alloc->page_offset = frag_info->frag_align;
  72. /* Not doing get_page() for each frag is a big win
  73. * on asymetric workloads.
  74. */
  75. atomic_set(&page->_count,
  76. page_alloc->page_size / frag_info->frag_stride);
  77. return 0;
  78. }
  79. static int mlx4_en_alloc_frags(struct mlx4_en_priv *priv,
  80. struct mlx4_en_rx_desc *rx_desc,
  81. struct mlx4_en_rx_alloc *frags,
  82. struct mlx4_en_rx_alloc *ring_alloc,
  83. gfp_t gfp)
  84. {
  85. struct mlx4_en_rx_alloc page_alloc[MLX4_EN_MAX_RX_FRAGS];
  86. const struct mlx4_en_frag_info *frag_info;
  87. struct page *page;
  88. dma_addr_t dma;
  89. int i;
  90. for (i = 0; i < priv->num_frags; i++) {
  91. frag_info = &priv->frag_info[i];
  92. page_alloc[i] = ring_alloc[i];
  93. page_alloc[i].page_offset += frag_info->frag_stride;
  94. if (page_alloc[i].page_offset + frag_info->frag_stride <=
  95. ring_alloc[i].page_size)
  96. continue;
  97. if (mlx4_alloc_pages(priv, &page_alloc[i], frag_info, gfp))
  98. goto out;
  99. }
  100. for (i = 0; i < priv->num_frags; i++) {
  101. frags[i] = ring_alloc[i];
  102. dma = ring_alloc[i].dma + ring_alloc[i].page_offset;
  103. ring_alloc[i] = page_alloc[i];
  104. rx_desc->data[i].addr = cpu_to_be64(dma);
  105. }
  106. return 0;
  107. out:
  108. while (i--) {
  109. frag_info = &priv->frag_info[i];
  110. if (page_alloc[i].page != ring_alloc[i].page) {
  111. dma_unmap_page(priv->ddev, page_alloc[i].dma,
  112. page_alloc[i].page_size, PCI_DMA_FROMDEVICE);
  113. page = page_alloc[i].page;
  114. atomic_set(&page->_count, 1);
  115. put_page(page);
  116. }
  117. }
  118. return -ENOMEM;
  119. }
  120. static void mlx4_en_free_frag(struct mlx4_en_priv *priv,
  121. struct mlx4_en_rx_alloc *frags,
  122. int i)
  123. {
  124. const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
  125. if (frags[i].page_offset + frag_info->frag_stride >
  126. frags[i].page_size)
  127. dma_unmap_page(priv->ddev, frags[i].dma, frags[i].page_size,
  128. PCI_DMA_FROMDEVICE);
  129. if (frags[i].page)
  130. put_page(frags[i].page);
  131. }
  132. static int mlx4_en_init_allocator(struct mlx4_en_priv *priv,
  133. struct mlx4_en_rx_ring *ring)
  134. {
  135. int i;
  136. struct mlx4_en_rx_alloc *page_alloc;
  137. for (i = 0; i < priv->num_frags; i++) {
  138. const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
  139. if (mlx4_alloc_pages(priv, &ring->page_alloc[i],
  140. frag_info, GFP_KERNEL))
  141. goto out;
  142. }
  143. return 0;
  144. out:
  145. while (i--) {
  146. struct page *page;
  147. page_alloc = &ring->page_alloc[i];
  148. dma_unmap_page(priv->ddev, page_alloc->dma,
  149. page_alloc->page_size, PCI_DMA_FROMDEVICE);
  150. page = page_alloc->page;
  151. atomic_set(&page->_count, 1);
  152. put_page(page);
  153. page_alloc->page = NULL;
  154. }
  155. return -ENOMEM;
  156. }
  157. static void mlx4_en_destroy_allocator(struct mlx4_en_priv *priv,
  158. struct mlx4_en_rx_ring *ring)
  159. {
  160. struct mlx4_en_rx_alloc *page_alloc;
  161. int i;
  162. for (i = 0; i < priv->num_frags; i++) {
  163. const struct mlx4_en_frag_info *frag_info = &priv->frag_info[i];
  164. page_alloc = &ring->page_alloc[i];
  165. en_dbg(DRV, priv, "Freeing allocator:%d count:%d\n",
  166. i, page_count(page_alloc->page));
  167. dma_unmap_page(priv->ddev, page_alloc->dma,
  168. page_alloc->page_size, PCI_DMA_FROMDEVICE);
  169. while (page_alloc->page_offset + frag_info->frag_stride <
  170. page_alloc->page_size) {
  171. put_page(page_alloc->page);
  172. page_alloc->page_offset += frag_info->frag_stride;
  173. }
  174. page_alloc->page = NULL;
  175. }
  176. }
  177. static void mlx4_en_init_rx_desc(struct mlx4_en_priv *priv,
  178. struct mlx4_en_rx_ring *ring, int index)
  179. {
  180. struct mlx4_en_rx_desc *rx_desc = ring->buf + ring->stride * index;
  181. int possible_frags;
  182. int i;
  183. /* Set size and memtype fields */
  184. for (i = 0; i < priv->num_frags; i++) {
  185. rx_desc->data[i].byte_count =
  186. cpu_to_be32(priv->frag_info[i].frag_size);
  187. rx_desc->data[i].lkey = cpu_to_be32(priv->mdev->mr.key);
  188. }
  189. /* If the number of used fragments does not fill up the ring stride,
  190. * remaining (unused) fragments must be padded with null address/size
  191. * and a special memory key */
  192. possible_frags = (ring->stride - sizeof(struct mlx4_en_rx_desc)) / DS_SIZE;
  193. for (i = priv->num_frags; i < possible_frags; i++) {
  194. rx_desc->data[i].byte_count = 0;
  195. rx_desc->data[i].lkey = cpu_to_be32(MLX4_EN_MEMTYPE_PAD);
  196. rx_desc->data[i].addr = 0;
  197. }
  198. }
  199. static int mlx4_en_prepare_rx_desc(struct mlx4_en_priv *priv,
  200. struct mlx4_en_rx_ring *ring, int index,
  201. gfp_t gfp)
  202. {
  203. struct mlx4_en_rx_desc *rx_desc = ring->buf + (index * ring->stride);
  204. struct mlx4_en_rx_alloc *frags = ring->rx_info +
  205. (index << priv->log_rx_info);
  206. return mlx4_en_alloc_frags(priv, rx_desc, frags, ring->page_alloc, gfp);
  207. }
  208. static inline void mlx4_en_update_rx_prod_db(struct mlx4_en_rx_ring *ring)
  209. {
  210. *ring->wqres.db.db = cpu_to_be32(ring->prod & 0xffff);
  211. }
  212. static void mlx4_en_free_rx_desc(struct mlx4_en_priv *priv,
  213. struct mlx4_en_rx_ring *ring,
  214. int index)
  215. {
  216. struct mlx4_en_rx_alloc *frags;
  217. int nr;
  218. frags = ring->rx_info + (index << priv->log_rx_info);
  219. for (nr = 0; nr < priv->num_frags; nr++) {
  220. en_dbg(DRV, priv, "Freeing fragment:%d\n", nr);
  221. mlx4_en_free_frag(priv, frags, nr);
  222. }
  223. }
  224. static int mlx4_en_fill_rx_buffers(struct mlx4_en_priv *priv)
  225. {
  226. struct mlx4_en_rx_ring *ring;
  227. int ring_ind;
  228. int buf_ind;
  229. int new_size;
  230. for (buf_ind = 0; buf_ind < priv->prof->rx_ring_size; buf_ind++) {
  231. for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
  232. ring = &priv->rx_ring[ring_ind];
  233. if (mlx4_en_prepare_rx_desc(priv, ring,
  234. ring->actual_size,
  235. GFP_KERNEL)) {
  236. if (ring->actual_size < MLX4_EN_MIN_RX_SIZE) {
  237. en_err(priv, "Failed to allocate "
  238. "enough rx buffers\n");
  239. return -ENOMEM;
  240. } else {
  241. new_size = rounddown_pow_of_two(ring->actual_size);
  242. en_warn(priv, "Only %d buffers allocated "
  243. "reducing ring size to %d",
  244. ring->actual_size, new_size);
  245. goto reduce_rings;
  246. }
  247. }
  248. ring->actual_size++;
  249. ring->prod++;
  250. }
  251. }
  252. return 0;
  253. reduce_rings:
  254. for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
  255. ring = &priv->rx_ring[ring_ind];
  256. while (ring->actual_size > new_size) {
  257. ring->actual_size--;
  258. ring->prod--;
  259. mlx4_en_free_rx_desc(priv, ring, ring->actual_size);
  260. }
  261. }
  262. return 0;
  263. }
  264. static void mlx4_en_free_rx_buf(struct mlx4_en_priv *priv,
  265. struct mlx4_en_rx_ring *ring)
  266. {
  267. int index;
  268. en_dbg(DRV, priv, "Freeing Rx buf - cons:%d prod:%d\n",
  269. ring->cons, ring->prod);
  270. /* Unmap and free Rx buffers */
  271. BUG_ON((u32) (ring->prod - ring->cons) > ring->actual_size);
  272. while (ring->cons != ring->prod) {
  273. index = ring->cons & ring->size_mask;
  274. en_dbg(DRV, priv, "Processing descriptor:%d\n", index);
  275. mlx4_en_free_rx_desc(priv, ring, index);
  276. ++ring->cons;
  277. }
  278. }
  279. int mlx4_en_create_rx_ring(struct mlx4_en_priv *priv,
  280. struct mlx4_en_rx_ring *ring, u32 size, u16 stride)
  281. {
  282. struct mlx4_en_dev *mdev = priv->mdev;
  283. int err = -ENOMEM;
  284. int tmp;
  285. ring->prod = 0;
  286. ring->cons = 0;
  287. ring->size = size;
  288. ring->size_mask = size - 1;
  289. ring->stride = stride;
  290. ring->log_stride = ffs(ring->stride) - 1;
  291. ring->buf_size = ring->size * ring->stride + TXBB_SIZE;
  292. tmp = size * roundup_pow_of_two(MLX4_EN_MAX_RX_FRAGS *
  293. sizeof(struct mlx4_en_rx_alloc));
  294. ring->rx_info = vmalloc(tmp);
  295. if (!ring->rx_info)
  296. return -ENOMEM;
  297. en_dbg(DRV, priv, "Allocated rx_info ring at addr:%p size:%d\n",
  298. ring->rx_info, tmp);
  299. err = mlx4_alloc_hwq_res(mdev->dev, &ring->wqres,
  300. ring->buf_size, 2 * PAGE_SIZE);
  301. if (err)
  302. goto err_ring;
  303. err = mlx4_en_map_buffer(&ring->wqres.buf);
  304. if (err) {
  305. en_err(priv, "Failed to map RX buffer\n");
  306. goto err_hwq;
  307. }
  308. ring->buf = ring->wqres.buf.direct.buf;
  309. ring->hwtstamp_rx_filter = priv->hwtstamp_config.rx_filter;
  310. return 0;
  311. err_hwq:
  312. mlx4_free_hwq_res(mdev->dev, &ring->wqres, ring->buf_size);
  313. err_ring:
  314. vfree(ring->rx_info);
  315. ring->rx_info = NULL;
  316. return err;
  317. }
  318. int mlx4_en_activate_rx_rings(struct mlx4_en_priv *priv)
  319. {
  320. struct mlx4_en_rx_ring *ring;
  321. int i;
  322. int ring_ind;
  323. int err;
  324. int stride = roundup_pow_of_two(sizeof(struct mlx4_en_rx_desc) +
  325. DS_SIZE * priv->num_frags);
  326. for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
  327. ring = &priv->rx_ring[ring_ind];
  328. ring->prod = 0;
  329. ring->cons = 0;
  330. ring->actual_size = 0;
  331. ring->cqn = priv->rx_cq[ring_ind].mcq.cqn;
  332. ring->stride = stride;
  333. if (ring->stride <= TXBB_SIZE)
  334. ring->buf += TXBB_SIZE;
  335. ring->log_stride = ffs(ring->stride) - 1;
  336. ring->buf_size = ring->size * ring->stride;
  337. memset(ring->buf, 0, ring->buf_size);
  338. mlx4_en_update_rx_prod_db(ring);
  339. /* Initialize all descriptors */
  340. for (i = 0; i < ring->size; i++)
  341. mlx4_en_init_rx_desc(priv, ring, i);
  342. /* Initialize page allocators */
  343. err = mlx4_en_init_allocator(priv, ring);
  344. if (err) {
  345. en_err(priv, "Failed initializing ring allocator\n");
  346. if (ring->stride <= TXBB_SIZE)
  347. ring->buf -= TXBB_SIZE;
  348. ring_ind--;
  349. goto err_allocator;
  350. }
  351. }
  352. err = mlx4_en_fill_rx_buffers(priv);
  353. if (err)
  354. goto err_buffers;
  355. for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++) {
  356. ring = &priv->rx_ring[ring_ind];
  357. ring->size_mask = ring->actual_size - 1;
  358. mlx4_en_update_rx_prod_db(ring);
  359. }
  360. return 0;
  361. err_buffers:
  362. for (ring_ind = 0; ring_ind < priv->rx_ring_num; ring_ind++)
  363. mlx4_en_free_rx_buf(priv, &priv->rx_ring[ring_ind]);
  364. ring_ind = priv->rx_ring_num - 1;
  365. err_allocator:
  366. while (ring_ind >= 0) {
  367. if (priv->rx_ring[ring_ind].stride <= TXBB_SIZE)
  368. priv->rx_ring[ring_ind].buf -= TXBB_SIZE;
  369. mlx4_en_destroy_allocator(priv, &priv->rx_ring[ring_ind]);
  370. ring_ind--;
  371. }
  372. return err;
  373. }
  374. void mlx4_en_destroy_rx_ring(struct mlx4_en_priv *priv,
  375. struct mlx4_en_rx_ring *ring, u32 size, u16 stride)
  376. {
  377. struct mlx4_en_dev *mdev = priv->mdev;
  378. mlx4_en_unmap_buffer(&ring->wqres.buf);
  379. mlx4_free_hwq_res(mdev->dev, &ring->wqres, size * stride + TXBB_SIZE);
  380. vfree(ring->rx_info);
  381. ring->rx_info = NULL;
  382. #ifdef CONFIG_RFS_ACCEL
  383. mlx4_en_cleanup_filters(priv, ring);
  384. #endif
  385. }
  386. void mlx4_en_deactivate_rx_ring(struct mlx4_en_priv *priv,
  387. struct mlx4_en_rx_ring *ring)
  388. {
  389. mlx4_en_free_rx_buf(priv, ring);
  390. if (ring->stride <= TXBB_SIZE)
  391. ring->buf -= TXBB_SIZE;
  392. mlx4_en_destroy_allocator(priv, ring);
  393. }
  394. static int mlx4_en_complete_rx_desc(struct mlx4_en_priv *priv,
  395. struct mlx4_en_rx_desc *rx_desc,
  396. struct mlx4_en_rx_alloc *frags,
  397. struct sk_buff *skb,
  398. int length)
  399. {
  400. struct skb_frag_struct *skb_frags_rx = skb_shinfo(skb)->frags;
  401. struct mlx4_en_frag_info *frag_info;
  402. int nr;
  403. dma_addr_t dma;
  404. /* Collect used fragments while replacing them in the HW descriptors */
  405. for (nr = 0; nr < priv->num_frags; nr++) {
  406. frag_info = &priv->frag_info[nr];
  407. if (length <= frag_info->frag_prefix_size)
  408. break;
  409. if (!frags[nr].page)
  410. goto fail;
  411. dma = be64_to_cpu(rx_desc->data[nr].addr);
  412. dma_sync_single_for_cpu(priv->ddev, dma, frag_info->frag_size,
  413. DMA_FROM_DEVICE);
  414. /* Save page reference in skb */
  415. __skb_frag_set_page(&skb_frags_rx[nr], frags[nr].page);
  416. skb_frag_size_set(&skb_frags_rx[nr], frag_info->frag_size);
  417. skb_frags_rx[nr].page_offset = frags[nr].page_offset;
  418. skb->truesize += frag_info->frag_stride;
  419. frags[nr].page = NULL;
  420. }
  421. /* Adjust size of last fragment to match actual length */
  422. if (nr > 0)
  423. skb_frag_size_set(&skb_frags_rx[nr - 1],
  424. length - priv->frag_info[nr - 1].frag_prefix_size);
  425. return nr;
  426. fail:
  427. while (nr > 0) {
  428. nr--;
  429. __skb_frag_unref(&skb_frags_rx[nr]);
  430. }
  431. return 0;
  432. }
  433. static struct sk_buff *mlx4_en_rx_skb(struct mlx4_en_priv *priv,
  434. struct mlx4_en_rx_desc *rx_desc,
  435. struct mlx4_en_rx_alloc *frags,
  436. unsigned int length)
  437. {
  438. struct sk_buff *skb;
  439. void *va;
  440. int used_frags;
  441. dma_addr_t dma;
  442. skb = netdev_alloc_skb(priv->dev, SMALL_PACKET_SIZE + NET_IP_ALIGN);
  443. if (!skb) {
  444. en_dbg(RX_ERR, priv, "Failed allocating skb\n");
  445. return NULL;
  446. }
  447. skb_reserve(skb, NET_IP_ALIGN);
  448. skb->len = length;
  449. /* Get pointer to first fragment so we could copy the headers into the
  450. * (linear part of the) skb */
  451. va = page_address(frags[0].page) + frags[0].page_offset;
  452. if (length <= SMALL_PACKET_SIZE) {
  453. /* We are copying all relevant data to the skb - temporarily
  454. * sync buffers for the copy */
  455. dma = be64_to_cpu(rx_desc->data[0].addr);
  456. dma_sync_single_for_cpu(priv->ddev, dma, length,
  457. DMA_FROM_DEVICE);
  458. skb_copy_to_linear_data(skb, va, length);
  459. skb->tail += length;
  460. } else {
  461. /* Move relevant fragments to skb */
  462. used_frags = mlx4_en_complete_rx_desc(priv, rx_desc, frags,
  463. skb, length);
  464. if (unlikely(!used_frags)) {
  465. kfree_skb(skb);
  466. return NULL;
  467. }
  468. skb_shinfo(skb)->nr_frags = used_frags;
  469. /* Copy headers into the skb linear buffer */
  470. memcpy(skb->data, va, HEADER_COPY_SIZE);
  471. skb->tail += HEADER_COPY_SIZE;
  472. /* Skip headers in first fragment */
  473. skb_shinfo(skb)->frags[0].page_offset += HEADER_COPY_SIZE;
  474. /* Adjust size of first fragment */
  475. skb_frag_size_sub(&skb_shinfo(skb)->frags[0], HEADER_COPY_SIZE);
  476. skb->data_len = length - HEADER_COPY_SIZE;
  477. }
  478. return skb;
  479. }
  480. static void validate_loopback(struct mlx4_en_priv *priv, struct sk_buff *skb)
  481. {
  482. int i;
  483. int offset = ETH_HLEN;
  484. for (i = 0; i < MLX4_LOOPBACK_TEST_PAYLOAD; i++, offset++) {
  485. if (*(skb->data + offset) != (unsigned char) (i & 0xff))
  486. goto out_loopback;
  487. }
  488. /* Loopback found */
  489. priv->loopback_ok = 1;
  490. out_loopback:
  491. dev_kfree_skb_any(skb);
  492. }
  493. static void mlx4_en_refill_rx_buffers(struct mlx4_en_priv *priv,
  494. struct mlx4_en_rx_ring *ring)
  495. {
  496. int index = ring->prod & ring->size_mask;
  497. while ((u32) (ring->prod - ring->cons) < ring->actual_size) {
  498. if (mlx4_en_prepare_rx_desc(priv, ring, index, GFP_ATOMIC))
  499. break;
  500. ring->prod++;
  501. index = ring->prod & ring->size_mask;
  502. }
  503. }
  504. int mlx4_en_process_rx_cq(struct net_device *dev, struct mlx4_en_cq *cq, int budget)
  505. {
  506. struct mlx4_en_priv *priv = netdev_priv(dev);
  507. struct mlx4_en_dev *mdev = priv->mdev;
  508. struct mlx4_cqe *cqe;
  509. struct mlx4_en_rx_ring *ring = &priv->rx_ring[cq->ring];
  510. struct mlx4_en_rx_alloc *frags;
  511. struct mlx4_en_rx_desc *rx_desc;
  512. struct sk_buff *skb;
  513. int index;
  514. int nr;
  515. unsigned int length;
  516. int polled = 0;
  517. int ip_summed;
  518. int factor = priv->cqe_factor;
  519. u64 timestamp;
  520. if (!priv->port_up)
  521. return 0;
  522. /* We assume a 1:1 mapping between CQEs and Rx descriptors, so Rx
  523. * descriptor offset can be deduced from the CQE index instead of
  524. * reading 'cqe->index' */
  525. index = cq->mcq.cons_index & ring->size_mask;
  526. cqe = &cq->buf[(index << factor) + factor];
  527. /* Process all completed CQEs */
  528. while (XNOR(cqe->owner_sr_opcode & MLX4_CQE_OWNER_MASK,
  529. cq->mcq.cons_index & cq->size)) {
  530. frags = ring->rx_info + (index << priv->log_rx_info);
  531. rx_desc = ring->buf + (index << ring->log_stride);
  532. /*
  533. * make sure we read the CQE after we read the ownership bit
  534. */
  535. rmb();
  536. /* Drop packet on bad receive or bad checksum */
  537. if (unlikely((cqe->owner_sr_opcode & MLX4_CQE_OPCODE_MASK) ==
  538. MLX4_CQE_OPCODE_ERROR)) {
  539. en_err(priv, "CQE completed in error - vendor "
  540. "syndrom:%d syndrom:%d\n",
  541. ((struct mlx4_err_cqe *) cqe)->vendor_err_syndrome,
  542. ((struct mlx4_err_cqe *) cqe)->syndrome);
  543. goto next;
  544. }
  545. if (unlikely(cqe->badfcs_enc & MLX4_CQE_BAD_FCS)) {
  546. en_dbg(RX_ERR, priv, "Accepted frame with bad FCS\n");
  547. goto next;
  548. }
  549. /* Check if we need to drop the packet if SRIOV is not enabled
  550. * and not performing the selftest or flb disabled
  551. */
  552. if (priv->flags & MLX4_EN_FLAG_RX_FILTER_NEEDED) {
  553. struct ethhdr *ethh;
  554. dma_addr_t dma;
  555. /* Get pointer to first fragment since we haven't
  556. * skb yet and cast it to ethhdr struct
  557. */
  558. dma = be64_to_cpu(rx_desc->data[0].addr);
  559. dma_sync_single_for_cpu(priv->ddev, dma, sizeof(*ethh),
  560. DMA_FROM_DEVICE);
  561. ethh = (struct ethhdr *)(page_address(frags[0].page) +
  562. frags[0].page_offset);
  563. if (is_multicast_ether_addr(ethh->h_dest)) {
  564. struct mlx4_mac_entry *entry;
  565. struct hlist_head *bucket;
  566. unsigned int mac_hash;
  567. /* Drop the packet, since HW loopback-ed it */
  568. mac_hash = ethh->h_source[MLX4_EN_MAC_HASH_IDX];
  569. bucket = &priv->mac_hash[mac_hash];
  570. rcu_read_lock();
  571. hlist_for_each_entry_rcu(entry, bucket, hlist) {
  572. if (ether_addr_equal_64bits(entry->mac,
  573. ethh->h_source)) {
  574. rcu_read_unlock();
  575. goto next;
  576. }
  577. }
  578. rcu_read_unlock();
  579. }
  580. }
  581. /*
  582. * Packet is OK - process it.
  583. */
  584. length = be32_to_cpu(cqe->byte_cnt);
  585. length -= ring->fcs_del;
  586. ring->bytes += length;
  587. ring->packets++;
  588. if (likely(dev->features & NETIF_F_RXCSUM)) {
  589. if ((cqe->status & cpu_to_be16(MLX4_CQE_STATUS_IPOK)) &&
  590. (cqe->checksum == cpu_to_be16(0xffff))) {
  591. ring->csum_ok++;
  592. /* This packet is eligible for GRO if it is:
  593. * - DIX Ethernet (type interpretation)
  594. * - TCP/IP (v4)
  595. * - without IP options
  596. * - not an IP fragment
  597. * - no LLS polling in progress
  598. */
  599. if (!mlx4_en_cq_ll_polling(cq) &&
  600. (dev->features & NETIF_F_GRO)) {
  601. struct sk_buff *gro_skb = napi_get_frags(&cq->napi);
  602. if (!gro_skb)
  603. goto next;
  604. nr = mlx4_en_complete_rx_desc(priv,
  605. rx_desc, frags, gro_skb,
  606. length);
  607. if (!nr)
  608. goto next;
  609. skb_shinfo(gro_skb)->nr_frags = nr;
  610. gro_skb->len = length;
  611. gro_skb->data_len = length;
  612. gro_skb->ip_summed = CHECKSUM_UNNECESSARY;
  613. if ((cqe->vlan_my_qpn &
  614. cpu_to_be32(MLX4_CQE_VLAN_PRESENT_MASK)) &&
  615. (dev->features & NETIF_F_HW_VLAN_CTAG_RX)) {
  616. u16 vid = be16_to_cpu(cqe->sl_vid);
  617. __vlan_hwaccel_put_tag(gro_skb, htons(ETH_P_8021Q), vid);
  618. }
  619. if (dev->features & NETIF_F_RXHASH)
  620. gro_skb->rxhash = be32_to_cpu(cqe->immed_rss_invalid);
  621. skb_record_rx_queue(gro_skb, cq->ring);
  622. if (ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL) {
  623. timestamp = mlx4_en_get_cqe_ts(cqe);
  624. mlx4_en_fill_hwtstamps(mdev,
  625. skb_hwtstamps(gro_skb),
  626. timestamp);
  627. }
  628. napi_gro_frags(&cq->napi);
  629. goto next;
  630. }
  631. /* GRO not possible, complete processing here */
  632. ip_summed = CHECKSUM_UNNECESSARY;
  633. } else {
  634. ip_summed = CHECKSUM_NONE;
  635. ring->csum_none++;
  636. }
  637. } else {
  638. ip_summed = CHECKSUM_NONE;
  639. ring->csum_none++;
  640. }
  641. skb = mlx4_en_rx_skb(priv, rx_desc, frags, length);
  642. if (!skb) {
  643. priv->stats.rx_dropped++;
  644. goto next;
  645. }
  646. if (unlikely(priv->validate_loopback)) {
  647. validate_loopback(priv, skb);
  648. goto next;
  649. }
  650. skb->ip_summed = ip_summed;
  651. skb->protocol = eth_type_trans(skb, dev);
  652. skb_record_rx_queue(skb, cq->ring);
  653. if (dev->features & NETIF_F_RXHASH)
  654. skb->rxhash = be32_to_cpu(cqe->immed_rss_invalid);
  655. if ((be32_to_cpu(cqe->vlan_my_qpn) &
  656. MLX4_CQE_VLAN_PRESENT_MASK) &&
  657. (dev->features & NETIF_F_HW_VLAN_CTAG_RX))
  658. __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), be16_to_cpu(cqe->sl_vid));
  659. if (ring->hwtstamp_rx_filter == HWTSTAMP_FILTER_ALL) {
  660. timestamp = mlx4_en_get_cqe_ts(cqe);
  661. mlx4_en_fill_hwtstamps(mdev, skb_hwtstamps(skb),
  662. timestamp);
  663. }
  664. skb_mark_napi_id(skb, &cq->napi);
  665. /* Push it up the stack */
  666. netif_receive_skb(skb);
  667. next:
  668. for (nr = 0; nr < priv->num_frags; nr++)
  669. mlx4_en_free_frag(priv, frags, nr);
  670. ++cq->mcq.cons_index;
  671. index = (cq->mcq.cons_index) & ring->size_mask;
  672. cqe = &cq->buf[(index << factor) + factor];
  673. if (++polled == budget)
  674. goto out;
  675. }
  676. out:
  677. AVG_PERF_COUNTER(priv->pstats.rx_coal_avg, polled);
  678. mlx4_cq_set_ci(&cq->mcq);
  679. wmb(); /* ensure HW sees CQ consumer before we post new buffers */
  680. ring->cons = cq->mcq.cons_index;
  681. mlx4_en_refill_rx_buffers(priv, ring);
  682. mlx4_en_update_rx_prod_db(ring);
  683. return polled;
  684. }
  685. void mlx4_en_rx_irq(struct mlx4_cq *mcq)
  686. {
  687. struct mlx4_en_cq *cq = container_of(mcq, struct mlx4_en_cq, mcq);
  688. struct mlx4_en_priv *priv = netdev_priv(cq->dev);
  689. if (priv->port_up)
  690. napi_schedule(&cq->napi);
  691. else
  692. mlx4_en_arm_cq(priv, cq);
  693. }
  694. /* Rx CQ polling - called by NAPI */
  695. int mlx4_en_poll_rx_cq(struct napi_struct *napi, int budget)
  696. {
  697. struct mlx4_en_cq *cq = container_of(napi, struct mlx4_en_cq, napi);
  698. struct net_device *dev = cq->dev;
  699. struct mlx4_en_priv *priv = netdev_priv(dev);
  700. int done;
  701. if (!mlx4_en_cq_lock_napi(cq))
  702. return budget;
  703. done = mlx4_en_process_rx_cq(dev, cq, budget);
  704. mlx4_en_cq_unlock_napi(cq);
  705. /* If we used up all the quota - we're probably not done yet... */
  706. if (done == budget)
  707. INC_PERF_COUNTER(priv->pstats.napi_quota);
  708. else {
  709. /* Done for now */
  710. napi_complete(napi);
  711. mlx4_en_arm_cq(priv, cq);
  712. }
  713. return done;
  714. }
  715. static const int frag_sizes[] = {
  716. FRAG_SZ0,
  717. FRAG_SZ1,
  718. FRAG_SZ2,
  719. FRAG_SZ3
  720. };
  721. void mlx4_en_calc_rx_buf(struct net_device *dev)
  722. {
  723. struct mlx4_en_priv *priv = netdev_priv(dev);
  724. int eff_mtu = dev->mtu + ETH_HLEN + VLAN_HLEN + ETH_LLC_SNAP_SIZE;
  725. int buf_size = 0;
  726. int i = 0;
  727. while (buf_size < eff_mtu) {
  728. priv->frag_info[i].frag_size =
  729. (eff_mtu > buf_size + frag_sizes[i]) ?
  730. frag_sizes[i] : eff_mtu - buf_size;
  731. priv->frag_info[i].frag_prefix_size = buf_size;
  732. if (!i) {
  733. priv->frag_info[i].frag_align = NET_IP_ALIGN;
  734. priv->frag_info[i].frag_stride =
  735. ALIGN(frag_sizes[i] + NET_IP_ALIGN, SMP_CACHE_BYTES);
  736. } else {
  737. priv->frag_info[i].frag_align = 0;
  738. priv->frag_info[i].frag_stride =
  739. ALIGN(frag_sizes[i], SMP_CACHE_BYTES);
  740. }
  741. buf_size += priv->frag_info[i].frag_size;
  742. i++;
  743. }
  744. priv->num_frags = i;
  745. priv->rx_skb_size = eff_mtu;
  746. priv->log_rx_info = ROUNDUP_LOG2(i * sizeof(struct mlx4_en_rx_alloc));
  747. en_dbg(DRV, priv, "Rx buffer scatter-list (effective-mtu:%d "
  748. "num_frags:%d):\n", eff_mtu, priv->num_frags);
  749. for (i = 0; i < priv->num_frags; i++) {
  750. en_err(priv,
  751. " frag:%d - size:%d prefix:%d align:%d stride:%d\n",
  752. i,
  753. priv->frag_info[i].frag_size,
  754. priv->frag_info[i].frag_prefix_size,
  755. priv->frag_info[i].frag_align,
  756. priv->frag_info[i].frag_stride);
  757. }
  758. }
  759. /* RSS related functions */
  760. static int mlx4_en_config_rss_qp(struct mlx4_en_priv *priv, int qpn,
  761. struct mlx4_en_rx_ring *ring,
  762. enum mlx4_qp_state *state,
  763. struct mlx4_qp *qp)
  764. {
  765. struct mlx4_en_dev *mdev = priv->mdev;
  766. struct mlx4_qp_context *context;
  767. int err = 0;
  768. context = kmalloc(sizeof(*context), GFP_KERNEL);
  769. if (!context)
  770. return -ENOMEM;
  771. err = mlx4_qp_alloc(mdev->dev, qpn, qp);
  772. if (err) {
  773. en_err(priv, "Failed to allocate qp #%x\n", qpn);
  774. goto out;
  775. }
  776. qp->event = mlx4_en_sqp_event;
  777. memset(context, 0, sizeof *context);
  778. mlx4_en_fill_qp_context(priv, ring->actual_size, ring->stride, 0, 0,
  779. qpn, ring->cqn, -1, context);
  780. context->db_rec_addr = cpu_to_be64(ring->wqres.db.dma);
  781. /* Cancel FCS removal if FW allows */
  782. if (mdev->dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP) {
  783. context->param3 |= cpu_to_be32(1 << 29);
  784. ring->fcs_del = ETH_FCS_LEN;
  785. } else
  786. ring->fcs_del = 0;
  787. err = mlx4_qp_to_ready(mdev->dev, &ring->wqres.mtt, context, qp, state);
  788. if (err) {
  789. mlx4_qp_remove(mdev->dev, qp);
  790. mlx4_qp_free(mdev->dev, qp);
  791. }
  792. mlx4_en_update_rx_prod_db(ring);
  793. out:
  794. kfree(context);
  795. return err;
  796. }
  797. int mlx4_en_create_drop_qp(struct mlx4_en_priv *priv)
  798. {
  799. int err;
  800. u32 qpn;
  801. err = mlx4_qp_reserve_range(priv->mdev->dev, 1, 1, &qpn);
  802. if (err) {
  803. en_err(priv, "Failed reserving drop qpn\n");
  804. return err;
  805. }
  806. err = mlx4_qp_alloc(priv->mdev->dev, qpn, &priv->drop_qp);
  807. if (err) {
  808. en_err(priv, "Failed allocating drop qp\n");
  809. mlx4_qp_release_range(priv->mdev->dev, qpn, 1);
  810. return err;
  811. }
  812. return 0;
  813. }
  814. void mlx4_en_destroy_drop_qp(struct mlx4_en_priv *priv)
  815. {
  816. u32 qpn;
  817. qpn = priv->drop_qp.qpn;
  818. mlx4_qp_remove(priv->mdev->dev, &priv->drop_qp);
  819. mlx4_qp_free(priv->mdev->dev, &priv->drop_qp);
  820. mlx4_qp_release_range(priv->mdev->dev, qpn, 1);
  821. }
  822. /* Allocate rx qp's and configure them according to rss map */
  823. int mlx4_en_config_rss_steer(struct mlx4_en_priv *priv)
  824. {
  825. struct mlx4_en_dev *mdev = priv->mdev;
  826. struct mlx4_en_rss_map *rss_map = &priv->rss_map;
  827. struct mlx4_qp_context context;
  828. struct mlx4_rss_context *rss_context;
  829. int rss_rings;
  830. void *ptr;
  831. u8 rss_mask = (MLX4_RSS_IPV4 | MLX4_RSS_TCP_IPV4 | MLX4_RSS_IPV6 |
  832. MLX4_RSS_TCP_IPV6);
  833. int i, qpn;
  834. int err = 0;
  835. int good_qps = 0;
  836. static const u32 rsskey[10] = { 0xD181C62C, 0xF7F4DB5B, 0x1983A2FC,
  837. 0x943E1ADB, 0xD9389E6B, 0xD1039C2C, 0xA74499AD,
  838. 0x593D56D9, 0xF3253C06, 0x2ADC1FFC};
  839. en_dbg(DRV, priv, "Configuring rss steering\n");
  840. err = mlx4_qp_reserve_range(mdev->dev, priv->rx_ring_num,
  841. priv->rx_ring_num,
  842. &rss_map->base_qpn);
  843. if (err) {
  844. en_err(priv, "Failed reserving %d qps\n", priv->rx_ring_num);
  845. return err;
  846. }
  847. for (i = 0; i < priv->rx_ring_num; i++) {
  848. qpn = rss_map->base_qpn + i;
  849. err = mlx4_en_config_rss_qp(priv, qpn, &priv->rx_ring[i],
  850. &rss_map->state[i],
  851. &rss_map->qps[i]);
  852. if (err)
  853. goto rss_err;
  854. ++good_qps;
  855. }
  856. /* Configure RSS indirection qp */
  857. err = mlx4_qp_alloc(mdev->dev, priv->base_qpn, &rss_map->indir_qp);
  858. if (err) {
  859. en_err(priv, "Failed to allocate RSS indirection QP\n");
  860. goto rss_err;
  861. }
  862. rss_map->indir_qp.event = mlx4_en_sqp_event;
  863. mlx4_en_fill_qp_context(priv, 0, 0, 0, 1, priv->base_qpn,
  864. priv->rx_ring[0].cqn, -1, &context);
  865. if (!priv->prof->rss_rings || priv->prof->rss_rings > priv->rx_ring_num)
  866. rss_rings = priv->rx_ring_num;
  867. else
  868. rss_rings = priv->prof->rss_rings;
  869. ptr = ((void *) &context) + offsetof(struct mlx4_qp_context, pri_path)
  870. + MLX4_RSS_OFFSET_IN_QPC_PRI_PATH;
  871. rss_context = ptr;
  872. rss_context->base_qpn = cpu_to_be32(ilog2(rss_rings) << 24 |
  873. (rss_map->base_qpn));
  874. rss_context->default_qpn = cpu_to_be32(rss_map->base_qpn);
  875. if (priv->mdev->profile.udp_rss) {
  876. rss_mask |= MLX4_RSS_UDP_IPV4 | MLX4_RSS_UDP_IPV6;
  877. rss_context->base_qpn_udp = rss_context->default_qpn;
  878. }
  879. rss_context->flags = rss_mask;
  880. rss_context->hash_fn = MLX4_RSS_HASH_TOP;
  881. for (i = 0; i < 10; i++)
  882. rss_context->rss_key[i] = cpu_to_be32(rsskey[i]);
  883. err = mlx4_qp_to_ready(mdev->dev, &priv->res.mtt, &context,
  884. &rss_map->indir_qp, &rss_map->indir_state);
  885. if (err)
  886. goto indir_err;
  887. return 0;
  888. indir_err:
  889. mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
  890. MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
  891. mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
  892. mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
  893. rss_err:
  894. for (i = 0; i < good_qps; i++) {
  895. mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
  896. MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
  897. mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
  898. mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
  899. }
  900. mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);
  901. return err;
  902. }
  903. void mlx4_en_release_rss_steer(struct mlx4_en_priv *priv)
  904. {
  905. struct mlx4_en_dev *mdev = priv->mdev;
  906. struct mlx4_en_rss_map *rss_map = &priv->rss_map;
  907. int i;
  908. mlx4_qp_modify(mdev->dev, NULL, rss_map->indir_state,
  909. MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->indir_qp);
  910. mlx4_qp_remove(mdev->dev, &rss_map->indir_qp);
  911. mlx4_qp_free(mdev->dev, &rss_map->indir_qp);
  912. for (i = 0; i < priv->rx_ring_num; i++) {
  913. mlx4_qp_modify(mdev->dev, NULL, rss_map->state[i],
  914. MLX4_QP_STATE_RST, NULL, 0, 0, &rss_map->qps[i]);
  915. mlx4_qp_remove(mdev->dev, &rss_map->qps[i]);
  916. mlx4_qp_free(mdev->dev, &rss_map->qps[i]);
  917. }
  918. mlx4_qp_release_range(mdev->dev, rss_map->base_qpn, priv->rx_ring_num);
  919. }