Kconfig 28 KB

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  1. #
  2. # For a description of the syntax of this configuration file,
  3. # see Documentation/kbuild/kconfig-language.txt.
  4. #
  5. mainmenu "Blackfin Kernel Configuration"
  6. config MMU
  7. bool
  8. default n
  9. config FPU
  10. bool
  11. default n
  12. config RWSEM_GENERIC_SPINLOCK
  13. bool
  14. default y
  15. config RWSEM_XCHGADD_ALGORITHM
  16. bool
  17. default n
  18. config BLACKFIN
  19. bool
  20. default y
  21. select HAVE_IDE
  22. select HAVE_OPROFILE
  23. select ARCH_WANT_OPTIONAL_GPIOLIB
  24. config GENERIC_BUG
  25. def_bool y
  26. depends on BUG
  27. config ZONE_DMA
  28. bool
  29. default y
  30. config GENERIC_FIND_NEXT_BIT
  31. bool
  32. default y
  33. config GENERIC_HWEIGHT
  34. bool
  35. default y
  36. config GENERIC_HARDIRQS
  37. bool
  38. default y
  39. config GENERIC_IRQ_PROBE
  40. bool
  41. default y
  42. config GENERIC_GPIO
  43. bool
  44. default y
  45. config FORCE_MAX_ZONEORDER
  46. int
  47. default "14"
  48. config GENERIC_CALIBRATE_DELAY
  49. bool
  50. default y
  51. source "init/Kconfig"
  52. source "kernel/Kconfig.preempt"
  53. source "kernel/Kconfig.freezer"
  54. menu "Blackfin Processor Options"
  55. comment "Processor and Board Settings"
  56. choice
  57. prompt "CPU"
  58. default BF533
  59. config BF512
  60. bool "BF512"
  61. help
  62. BF512 Processor Support.
  63. config BF514
  64. bool "BF514"
  65. help
  66. BF514 Processor Support.
  67. config BF516
  68. bool "BF516"
  69. help
  70. BF516 Processor Support.
  71. config BF518
  72. bool "BF518"
  73. help
  74. BF518 Processor Support.
  75. config BF522
  76. bool "BF522"
  77. help
  78. BF522 Processor Support.
  79. config BF523
  80. bool "BF523"
  81. help
  82. BF523 Processor Support.
  83. config BF524
  84. bool "BF524"
  85. help
  86. BF524 Processor Support.
  87. config BF525
  88. bool "BF525"
  89. help
  90. BF525 Processor Support.
  91. config BF526
  92. bool "BF526"
  93. help
  94. BF526 Processor Support.
  95. config BF527
  96. bool "BF527"
  97. help
  98. BF527 Processor Support.
  99. config BF531
  100. bool "BF531"
  101. help
  102. BF531 Processor Support.
  103. config BF532
  104. bool "BF532"
  105. help
  106. BF532 Processor Support.
  107. config BF533
  108. bool "BF533"
  109. help
  110. BF533 Processor Support.
  111. config BF534
  112. bool "BF534"
  113. help
  114. BF534 Processor Support.
  115. config BF536
  116. bool "BF536"
  117. help
  118. BF536 Processor Support.
  119. config BF537
  120. bool "BF537"
  121. help
  122. BF537 Processor Support.
  123. config BF538
  124. bool "BF538"
  125. help
  126. BF538 Processor Support.
  127. config BF539
  128. bool "BF539"
  129. help
  130. BF539 Processor Support.
  131. config BF542
  132. bool "BF542"
  133. help
  134. BF542 Processor Support.
  135. config BF542M
  136. bool "BF542m"
  137. help
  138. BF542 Processor Support.
  139. config BF544
  140. bool "BF544"
  141. help
  142. BF544 Processor Support.
  143. config BF544M
  144. bool "BF544m"
  145. help
  146. BF544 Processor Support.
  147. config BF547
  148. bool "BF547"
  149. help
  150. BF547 Processor Support.
  151. config BF547M
  152. bool "BF547m"
  153. help
  154. BF547 Processor Support.
  155. config BF548
  156. bool "BF548"
  157. help
  158. BF548 Processor Support.
  159. config BF548M
  160. bool "BF548m"
  161. help
  162. BF548 Processor Support.
  163. config BF549
  164. bool "BF549"
  165. help
  166. BF549 Processor Support.
  167. config BF549M
  168. bool "BF549m"
  169. help
  170. BF549 Processor Support.
  171. config BF561
  172. bool "BF561"
  173. help
  174. BF561 Processor Support.
  175. endchoice
  176. config SMP
  177. depends on BF561
  178. select GENERIC_TIME
  179. bool "Symmetric multi-processing support"
  180. ---help---
  181. This enables support for systems with more than one CPU,
  182. like the dual core BF561. If you have a system with only one
  183. CPU, say N. If you have a system with more than one CPU, say Y.
  184. If you don't know what to do here, say N.
  185. config NR_CPUS
  186. int
  187. depends on SMP
  188. default 2 if BF561
  189. config IRQ_PER_CPU
  190. bool
  191. depends on SMP
  192. default y
  193. config BF_REV_MIN
  194. int
  195. default 0 if (BF51x || BF52x || (BF54x && !BF54xM))
  196. default 2 if (BF537 || BF536 || BF534)
  197. default 3 if (BF561 || BF533 || BF532 || BF531 || BF54xM)
  198. default 4 if (BF538 || BF539)
  199. config BF_REV_MAX
  200. int
  201. default 2 if (BF51x || BF52x || (BF54x && !BF54xM))
  202. default 3 if (BF537 || BF536 || BF534 || BF54xM)
  203. default 5 if (BF561 || BF538 || BF539)
  204. default 6 if (BF533 || BF532 || BF531)
  205. choice
  206. prompt "Silicon Rev"
  207. default BF_REV_0_0 if (BF51x || BF52x)
  208. default BF_REV_0_2 if (BF534 || BF536 || BF537 || (BF54x && !BF54xM))
  209. default BF_REV_0_3 if (BF531 || BF532 || BF533 || BF54xM || BF561)
  210. config BF_REV_0_0
  211. bool "0.0"
  212. depends on (BF51x || BF52x || (BF54x && !BF54xM))
  213. config BF_REV_0_1
  214. bool "0.1"
  215. depends on (BF52x || (BF54x && !BF54xM))
  216. config BF_REV_0_2
  217. bool "0.2"
  218. depends on (BF52x || BF537 || BF536 || BF534 || (BF54x && !BF54xM))
  219. config BF_REV_0_3
  220. bool "0.3"
  221. depends on (BF54xM || BF561 || BF537 || BF536 || BF534 || BF533 || BF532 || BF531)
  222. config BF_REV_0_4
  223. bool "0.4"
  224. depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
  225. config BF_REV_0_5
  226. bool "0.5"
  227. depends on (BF561 || BF533 || BF532 || BF531 || BF538 || BF539)
  228. config BF_REV_0_6
  229. bool "0.6"
  230. depends on (BF533 || BF532 || BF531)
  231. config BF_REV_ANY
  232. bool "any"
  233. config BF_REV_NONE
  234. bool "none"
  235. endchoice
  236. config BF51x
  237. bool
  238. depends on (BF512 || BF514 || BF516 || BF518)
  239. default y
  240. config BF52x
  241. bool
  242. depends on (BF522 || BF523 || BF524 || BF525 || BF526 || BF527)
  243. default y
  244. config BF53x
  245. bool
  246. depends on (BF531 || BF532 || BF533 || BF534 || BF536 || BF537)
  247. default y
  248. config BF54xM
  249. bool
  250. depends on (BF542M || BF544M || BF547M || BF548M || BF549M)
  251. default y
  252. config BF54x
  253. bool
  254. depends on (BF542 || BF544 || BF547 || BF548 || BF549 || BF54xM)
  255. default y
  256. config MEM_GENERIC_BOARD
  257. bool
  258. depends on GENERIC_BOARD
  259. default y
  260. config MEM_MT48LC64M4A2FB_7E
  261. bool
  262. depends on (BFIN533_STAMP)
  263. default y
  264. config MEM_MT48LC16M16A2TG_75
  265. bool
  266. depends on (BFIN533_EZKIT || BFIN561_EZKIT \
  267. || BFIN533_BLUETECHNIX_CM || BFIN537_BLUETECHNIX_CM \
  268. || H8606_HVSISTEMAS || BFIN527_BLUETECHNIX_CM)
  269. default y
  270. config MEM_MT48LC32M8A2_75
  271. bool
  272. depends on (BFIN537_STAMP || PNAV10 || BFIN538_EZKIT)
  273. default y
  274. config MEM_MT48LC8M32B2B5_7
  275. bool
  276. depends on (BFIN561_BLUETECHNIX_CM)
  277. default y
  278. config MEM_MT48LC32M16A2TG_75
  279. bool
  280. depends on (BFIN527_EZKIT || BFIN532_IP0X || BLACKSTAMP || BFIN526_EZBRD)
  281. default y
  282. config MEM_MT48LC32M8A2_75
  283. bool
  284. depends on (BFIN518F_EZBRD)
  285. default y
  286. source "arch/blackfin/mach-bf518/Kconfig"
  287. source "arch/blackfin/mach-bf527/Kconfig"
  288. source "arch/blackfin/mach-bf533/Kconfig"
  289. source "arch/blackfin/mach-bf561/Kconfig"
  290. source "arch/blackfin/mach-bf537/Kconfig"
  291. source "arch/blackfin/mach-bf538/Kconfig"
  292. source "arch/blackfin/mach-bf548/Kconfig"
  293. menu "Board customizations"
  294. config CMDLINE_BOOL
  295. bool "Default bootloader kernel arguments"
  296. config CMDLINE
  297. string "Initial kernel command string"
  298. depends on CMDLINE_BOOL
  299. default "console=ttyBF0,57600"
  300. help
  301. If you don't have a boot loader capable of passing a command line string
  302. to the kernel, you may specify one here. As a minimum, you should specify
  303. the memory size and the root device (e.g., mem=8M, root=/dev/nfs).
  304. config BOOT_LOAD
  305. hex "Kernel load address for booting"
  306. default "0x1000"
  307. range 0x1000 0x20000000
  308. help
  309. This option allows you to set the load address of the kernel.
  310. This can be useful if you are on a board which has a small amount
  311. of memory or you wish to reserve some memory at the beginning of
  312. the address space.
  313. Note that you need to keep this value above 4k (0x1000) as this
  314. memory region is used to capture NULL pointer references as well
  315. as some core kernel functions.
  316. config ROM_BASE
  317. hex "Kernel ROM Base"
  318. depends on ROMKERNEL
  319. default "0x20040000"
  320. range 0x20000000 0x20400000 if !(BF54x || BF561)
  321. range 0x20000000 0x30000000 if (BF54x || BF561)
  322. help
  323. comment "Clock/PLL Setup"
  324. config CLKIN_HZ
  325. int "Frequency of the crystal on the board in Hz"
  326. default "11059200" if BFIN533_STAMP
  327. default "27000000" if BFIN533_EZKIT
  328. default "25000000" if (BFIN537_STAMP || BFIN527_EZKIT || H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN538_EZKIT || BFIN518F-EZBRD)
  329. default "30000000" if BFIN561_EZKIT
  330. default "24576000" if PNAV10
  331. default "10000000" if BFIN532_IP0X
  332. help
  333. The frequency of CLKIN crystal oscillator on the board in Hz.
  334. Warning: This value should match the crystal on the board. Otherwise,
  335. peripherals won't work properly.
  336. config BFIN_KERNEL_CLOCK
  337. bool "Re-program Clocks while Kernel boots?"
  338. default n
  339. help
  340. This option decides if kernel clocks are re-programed from the
  341. bootloader settings. If the clocks are not set, the SDRAM settings
  342. are also not changed, and the Bootloader does 100% of the hardware
  343. configuration.
  344. config PLL_BYPASS
  345. bool "Bypass PLL"
  346. depends on BFIN_KERNEL_CLOCK
  347. default n
  348. config CLKIN_HALF
  349. bool "Half Clock In"
  350. depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
  351. default n
  352. help
  353. If this is set the clock will be divided by 2, before it goes to the PLL.
  354. config VCO_MULT
  355. int "VCO Multiplier"
  356. depends on BFIN_KERNEL_CLOCK && (! PLL_BYPASS)
  357. range 1 64
  358. default "22" if BFIN533_EZKIT
  359. default "45" if BFIN533_STAMP
  360. default "20" if (BFIN537_STAMP || BFIN527_EZKIT || BFIN548_EZKIT || BFIN548_BLUETECHNIX_CM || BFIN538_EZKIT)
  361. default "22" if BFIN533_BLUETECHNIX_CM
  362. default "20" if (BFIN537_BLUETECHNIX_CM || BFIN527_BLUETECHNIX_CM || BFIN561_BLUETECHNIX_CM)
  363. default "20" if BFIN561_EZKIT
  364. default "16" if (H8606_HVSISTEMAS || BLACKSTAMP || BFIN526_EZBRD || BFIN518F_EZBRD)
  365. help
  366. This controls the frequency of the on-chip PLL. This can be between 1 and 64.
  367. PLL Frequency = (Crystal Frequency) * (this setting)
  368. choice
  369. prompt "Core Clock Divider"
  370. depends on BFIN_KERNEL_CLOCK
  371. default CCLK_DIV_1
  372. help
  373. This sets the frequency of the core. It can be 1, 2, 4 or 8
  374. Core Frequency = (PLL frequency) / (this setting)
  375. config CCLK_DIV_1
  376. bool "1"
  377. config CCLK_DIV_2
  378. bool "2"
  379. config CCLK_DIV_4
  380. bool "4"
  381. config CCLK_DIV_8
  382. bool "8"
  383. endchoice
  384. config SCLK_DIV
  385. int "System Clock Divider"
  386. depends on BFIN_KERNEL_CLOCK
  387. range 1 15
  388. default 5
  389. help
  390. This sets the frequency of the system clock (including SDRAM or DDR).
  391. This can be between 1 and 15
  392. System Clock = (PLL frequency) / (this setting)
  393. choice
  394. prompt "DDR SDRAM Chip Type"
  395. depends on BFIN_KERNEL_CLOCK
  396. depends on BF54x
  397. default MEM_MT46V32M16_5B
  398. config MEM_MT46V32M16_6T
  399. bool "MT46V32M16_6T"
  400. config MEM_MT46V32M16_5B
  401. bool "MT46V32M16_5B"
  402. endchoice
  403. choice
  404. prompt "DDR/SDRAM Timing"
  405. depends on BFIN_KERNEL_CLOCK
  406. default BFIN_KERNEL_CLOCK_MEMINIT_CALC
  407. help
  408. This option allows you to specify Blackfin SDRAM/DDR Timing parameters
  409. The calculated SDRAM timing parameters may not be 100%
  410. accurate - This option is therefore marked experimental.
  411. config BFIN_KERNEL_CLOCK_MEMINIT_CALC
  412. bool "Calculate Timings (EXPERIMENTAL)"
  413. depends on EXPERIMENTAL
  414. config BFIN_KERNEL_CLOCK_MEMINIT_SPEC
  415. bool "Provide accurate Timings based on target SCLK"
  416. help
  417. Please consult the Blackfin Hardware Reference Manuals as well
  418. as the memory device datasheet.
  419. http://docs.blackfin.uclinux.org/doku.php?id=bfin:sdram
  420. endchoice
  421. menu "Memory Init Control"
  422. depends on BFIN_KERNEL_CLOCK_MEMINIT_SPEC
  423. config MEM_DDRCTL0
  424. depends on BF54x
  425. hex "DDRCTL0"
  426. default 0x0
  427. config MEM_DDRCTL1
  428. depends on BF54x
  429. hex "DDRCTL1"
  430. default 0x0
  431. config MEM_DDRCTL2
  432. depends on BF54x
  433. hex "DDRCTL2"
  434. default 0x0
  435. config MEM_EBIU_DDRQUE
  436. depends on BF54x
  437. hex "DDRQUE"
  438. default 0x0
  439. config MEM_SDRRC
  440. depends on !BF54x
  441. hex "SDRRC"
  442. default 0x0
  443. config MEM_SDGCTL
  444. depends on !BF54x
  445. hex "SDGCTL"
  446. default 0x0
  447. endmenu
  448. #
  449. # Max & Min Speeds for various Chips
  450. #
  451. config MAX_VCO_HZ
  452. int
  453. default 400000000 if BF512
  454. default 400000000 if BF514
  455. default 400000000 if BF516
  456. default 400000000 if BF518
  457. default 600000000 if BF522
  458. default 400000000 if BF523
  459. default 400000000 if BF524
  460. default 600000000 if BF525
  461. default 400000000 if BF526
  462. default 600000000 if BF527
  463. default 400000000 if BF531
  464. default 400000000 if BF532
  465. default 750000000 if BF533
  466. default 500000000 if BF534
  467. default 400000000 if BF536
  468. default 600000000 if BF537
  469. default 533333333 if BF538
  470. default 533333333 if BF539
  471. default 600000000 if BF542
  472. default 533333333 if BF544
  473. default 600000000 if BF547
  474. default 600000000 if BF548
  475. default 533333333 if BF549
  476. default 600000000 if BF561
  477. config MIN_VCO_HZ
  478. int
  479. default 50000000
  480. config MAX_SCLK_HZ
  481. int
  482. default 133333333
  483. config MIN_SCLK_HZ
  484. int
  485. default 27000000
  486. comment "Kernel Timer/Scheduler"
  487. source kernel/Kconfig.hz
  488. config GENERIC_TIME
  489. bool "Generic time"
  490. default y
  491. config GENERIC_CLOCKEVENTS
  492. bool "Generic clock events"
  493. depends on GENERIC_TIME
  494. default y
  495. choice
  496. prompt "Kernel Tick Source"
  497. depends on GENERIC_CLOCKEVENTS
  498. default TICKSOURCE_CORETMR
  499. config TICKSOURCE_GPTMR0
  500. bool "Gptimer0 (SCLK domain)"
  501. select BFIN_GPTIMERS
  502. depends on !IPIPE
  503. config TICKSOURCE_CORETMR
  504. bool "Core timer (CCLK domain)"
  505. endchoice
  506. config CYCLES_CLOCKSOURCE
  507. bool "Use 'CYCLES' as a clocksource"
  508. depends on GENERIC_CLOCKEVENTS
  509. depends on !BFIN_SCRATCH_REG_CYCLES
  510. depends on !SMP
  511. help
  512. If you say Y here, you will enable support for using the 'cycles'
  513. registers as a clock source. Doing so means you will be unable to
  514. safely write to the 'cycles' register during runtime. You will
  515. still be able to read it (such as for performance monitoring), but
  516. writing the registers will most likely crash the kernel.
  517. config GPTMR0_CLOCKSOURCE
  518. bool "Use GPTimer0 as a clocksource (higher rating)"
  519. depends on GENERIC_CLOCKEVENTS
  520. depends on !TICKSOURCE_GPTMR0
  521. source kernel/time/Kconfig
  522. comment "Misc"
  523. choice
  524. prompt "Blackfin Exception Scratch Register"
  525. default BFIN_SCRATCH_REG_RETN
  526. help
  527. Select the resource to reserve for the Exception handler:
  528. - RETN: Non-Maskable Interrupt (NMI)
  529. - RETE: Exception Return (JTAG/ICE)
  530. - CYCLES: Performance counter
  531. If you are unsure, please select "RETN".
  532. config BFIN_SCRATCH_REG_RETN
  533. bool "RETN"
  534. help
  535. Use the RETN register in the Blackfin exception handler
  536. as a stack scratch register. This means you cannot
  537. safely use NMI on the Blackfin while running Linux, but
  538. you can debug the system with a JTAG ICE and use the
  539. CYCLES performance registers.
  540. If you are unsure, please select "RETN".
  541. config BFIN_SCRATCH_REG_RETE
  542. bool "RETE"
  543. help
  544. Use the RETE register in the Blackfin exception handler
  545. as a stack scratch register. This means you cannot
  546. safely use a JTAG ICE while debugging a Blackfin board,
  547. but you can safely use the CYCLES performance registers
  548. and the NMI.
  549. If you are unsure, please select "RETN".
  550. config BFIN_SCRATCH_REG_CYCLES
  551. bool "CYCLES"
  552. help
  553. Use the CYCLES register in the Blackfin exception handler
  554. as a stack scratch register. This means you cannot
  555. safely use the CYCLES performance registers on a Blackfin
  556. board at anytime, but you can debug the system with a JTAG
  557. ICE and use the NMI.
  558. If you are unsure, please select "RETN".
  559. endchoice
  560. endmenu
  561. menu "Blackfin Kernel Optimizations"
  562. depends on !SMP
  563. comment "Memory Optimizations"
  564. config I_ENTRY_L1
  565. bool "Locate interrupt entry code in L1 Memory"
  566. default y
  567. help
  568. If enabled, interrupt entry code (STORE/RESTORE CONTEXT) is linked
  569. into L1 instruction memory. (less latency)
  570. config EXCPT_IRQ_SYSC_L1
  571. bool "Locate entire ASM lowlevel exception / interrupt - Syscall and CPLB handler code in L1 Memory"
  572. default y
  573. help
  574. If enabled, the entire ASM lowlevel exception and interrupt entry code
  575. (STORE/RESTORE CONTEXT) is linked into L1 instruction memory.
  576. (less latency)
  577. config DO_IRQ_L1
  578. bool "Locate frequently called do_irq dispatcher function in L1 Memory"
  579. default y
  580. help
  581. If enabled, the frequently called do_irq dispatcher function is linked
  582. into L1 instruction memory. (less latency)
  583. config CORE_TIMER_IRQ_L1
  584. bool "Locate frequently called timer_interrupt() function in L1 Memory"
  585. default y
  586. help
  587. If enabled, the frequently called timer_interrupt() function is linked
  588. into L1 instruction memory. (less latency)
  589. config IDLE_L1
  590. bool "Locate frequently idle function in L1 Memory"
  591. default y
  592. help
  593. If enabled, the frequently called idle function is linked
  594. into L1 instruction memory. (less latency)
  595. config SCHEDULE_L1
  596. bool "Locate kernel schedule function in L1 Memory"
  597. default y
  598. help
  599. If enabled, the frequently called kernel schedule is linked
  600. into L1 instruction memory. (less latency)
  601. config ARITHMETIC_OPS_L1
  602. bool "Locate kernel owned arithmetic functions in L1 Memory"
  603. default y
  604. help
  605. If enabled, arithmetic functions are linked
  606. into L1 instruction memory. (less latency)
  607. config ACCESS_OK_L1
  608. bool "Locate access_ok function in L1 Memory"
  609. default y
  610. help
  611. If enabled, the access_ok function is linked
  612. into L1 instruction memory. (less latency)
  613. config MEMSET_L1
  614. bool "Locate memset function in L1 Memory"
  615. default y
  616. help
  617. If enabled, the memset function is linked
  618. into L1 instruction memory. (less latency)
  619. config MEMCPY_L1
  620. bool "Locate memcpy function in L1 Memory"
  621. default y
  622. help
  623. If enabled, the memcpy function is linked
  624. into L1 instruction memory. (less latency)
  625. config SYS_BFIN_SPINLOCK_L1
  626. bool "Locate sys_bfin_spinlock function in L1 Memory"
  627. default y
  628. help
  629. If enabled, sys_bfin_spinlock function is linked
  630. into L1 instruction memory. (less latency)
  631. config IP_CHECKSUM_L1
  632. bool "Locate IP Checksum function in L1 Memory"
  633. default n
  634. help
  635. If enabled, the IP Checksum function is linked
  636. into L1 instruction memory. (less latency)
  637. config CACHELINE_ALIGNED_L1
  638. bool "Locate cacheline_aligned data to L1 Data Memory"
  639. default y if !BF54x
  640. default n if BF54x
  641. depends on !BF531
  642. help
  643. If enabled, cacheline_aligned data is linked
  644. into L1 data memory. (less latency)
  645. config SYSCALL_TAB_L1
  646. bool "Locate Syscall Table L1 Data Memory"
  647. default n
  648. depends on !BF531
  649. help
  650. If enabled, the Syscall LUT is linked
  651. into L1 data memory. (less latency)
  652. config CPLB_SWITCH_TAB_L1
  653. bool "Locate CPLB Switch Tables L1 Data Memory"
  654. default n
  655. depends on !BF531
  656. help
  657. If enabled, the CPLB Switch Tables are linked
  658. into L1 data memory. (less latency)
  659. config APP_STACK_L1
  660. bool "Support locating application stack in L1 Scratch Memory"
  661. default y
  662. help
  663. If enabled the application stack can be located in L1
  664. scratch memory (less latency).
  665. Currently only works with FLAT binaries.
  666. config EXCEPTION_L1_SCRATCH
  667. bool "Locate exception stack in L1 Scratch Memory"
  668. default n
  669. depends on !APP_STACK_L1
  670. help
  671. Whenever an exception occurs, use the L1 Scratch memory for
  672. stack storage. You cannot place the stacks of FLAT binaries
  673. in L1 when using this option.
  674. If you don't use L1 Scratch, then you should say Y here.
  675. comment "Speed Optimizations"
  676. config BFIN_INS_LOWOVERHEAD
  677. bool "ins[bwl] low overhead, higher interrupt latency"
  678. default y
  679. help
  680. Reads on the Blackfin are speculative. In Blackfin terms, this means
  681. they can be interrupted at any time (even after they have been issued
  682. on to the external bus), and re-issued after the interrupt occurs.
  683. For memory - this is not a big deal, since memory does not change if
  684. it sees a read.
  685. If a FIFO is sitting on the end of the read, it will see two reads,
  686. when the core only sees one since the FIFO receives both the read
  687. which is cancelled (and not delivered to the core) and the one which
  688. is re-issued (which is delivered to the core).
  689. To solve this, interrupts are turned off before reads occur to
  690. I/O space. This option controls which the overhead/latency of
  691. controlling interrupts during this time
  692. "n" turns interrupts off every read
  693. (higher overhead, but lower interrupt latency)
  694. "y" turns interrupts off every loop
  695. (low overhead, but longer interrupt latency)
  696. default behavior is to leave this set to on (type "Y"). If you are experiencing
  697. interrupt latency issues, it is safe and OK to turn this off.
  698. endmenu
  699. choice
  700. prompt "Kernel executes from"
  701. help
  702. Choose the memory type that the kernel will be running in.
  703. config RAMKERNEL
  704. bool "RAM"
  705. help
  706. The kernel will be resident in RAM when running.
  707. config ROMKERNEL
  708. bool "ROM"
  709. help
  710. The kernel will be resident in FLASH/ROM when running.
  711. endchoice
  712. source "mm/Kconfig"
  713. config BFIN_GPTIMERS
  714. tristate "Enable Blackfin General Purpose Timers API"
  715. default n
  716. help
  717. Enable support for the General Purpose Timers API. If you
  718. are unsure, say N.
  719. To compile this driver as a module, choose M here: the module
  720. will be called gptimers.ko.
  721. choice
  722. prompt "Uncached DMA region"
  723. default DMA_UNCACHED_1M
  724. config DMA_UNCACHED_4M
  725. bool "Enable 4M DMA region"
  726. config DMA_UNCACHED_2M
  727. bool "Enable 2M DMA region"
  728. config DMA_UNCACHED_1M
  729. bool "Enable 1M DMA region"
  730. config DMA_UNCACHED_NONE
  731. bool "Disable DMA region"
  732. endchoice
  733. comment "Cache Support"
  734. config BFIN_ICACHE
  735. bool "Enable ICACHE"
  736. config BFIN_DCACHE
  737. bool "Enable DCACHE"
  738. config BFIN_DCACHE_BANKA
  739. bool "Enable only 16k BankA DCACHE - BankB is SRAM"
  740. depends on BFIN_DCACHE && !BF531
  741. default n
  742. config BFIN_ICACHE_LOCK
  743. bool "Enable Instruction Cache Locking"
  744. choice
  745. prompt "External memory cache policy"
  746. depends on BFIN_DCACHE
  747. default BFIN_WB if !SMP
  748. default BFIN_WT if SMP
  749. config BFIN_WB
  750. bool "Write back"
  751. depends on !SMP
  752. help
  753. Write Back Policy:
  754. Cached data will be written back to SDRAM only when needed.
  755. This can give a nice increase in performance, but beware of
  756. broken drivers that do not properly invalidate/flush their
  757. cache.
  758. Write Through Policy:
  759. Cached data will always be written back to SDRAM when the
  760. cache is updated. This is a completely safe setting, but
  761. performance is worse than Write Back.
  762. If you are unsure of the options and you want to be safe,
  763. then go with Write Through.
  764. config BFIN_WT
  765. bool "Write through"
  766. help
  767. Write Back Policy:
  768. Cached data will be written back to SDRAM only when needed.
  769. This can give a nice increase in performance, but beware of
  770. broken drivers that do not properly invalidate/flush their
  771. cache.
  772. Write Through Policy:
  773. Cached data will always be written back to SDRAM when the
  774. cache is updated. This is a completely safe setting, but
  775. performance is worse than Write Back.
  776. If you are unsure of the options and you want to be safe,
  777. then go with Write Through.
  778. endchoice
  779. choice
  780. prompt "L2 SRAM cache policy"
  781. depends on (BF54x || BF561)
  782. default BFIN_L2_WT
  783. config BFIN_L2_WB
  784. bool "Write back"
  785. depends on !SMP
  786. config BFIN_L2_WT
  787. bool "Write through"
  788. depends on !SMP
  789. config BFIN_L2_NOT_CACHED
  790. bool "Not cached"
  791. endchoice
  792. config MPU
  793. bool "Enable the memory protection unit (EXPERIMENTAL)"
  794. default n
  795. help
  796. Use the processor's MPU to protect applications from accessing
  797. memory they do not own. This comes at a performance penalty
  798. and is recommended only for debugging.
  799. comment "Asynchronous Memory Configuration"
  800. menu "EBIU_AMGCTL Global Control"
  801. config C_AMCKEN
  802. bool "Enable CLKOUT"
  803. default y
  804. config C_CDPRIO
  805. bool "DMA has priority over core for ext. accesses"
  806. default n
  807. config C_B0PEN
  808. depends on BF561
  809. bool "Bank 0 16 bit packing enable"
  810. default y
  811. config C_B1PEN
  812. depends on BF561
  813. bool "Bank 1 16 bit packing enable"
  814. default y
  815. config C_B2PEN
  816. depends on BF561
  817. bool "Bank 2 16 bit packing enable"
  818. default y
  819. config C_B3PEN
  820. depends on BF561
  821. bool "Bank 3 16 bit packing enable"
  822. default n
  823. choice
  824. prompt "Enable Asynchronous Memory Banks"
  825. default C_AMBEN_ALL
  826. config C_AMBEN
  827. bool "Disable All Banks"
  828. config C_AMBEN_B0
  829. bool "Enable Bank 0"
  830. config C_AMBEN_B0_B1
  831. bool "Enable Bank 0 & 1"
  832. config C_AMBEN_B0_B1_B2
  833. bool "Enable Bank 0 & 1 & 2"
  834. config C_AMBEN_ALL
  835. bool "Enable All Banks"
  836. endchoice
  837. endmenu
  838. menu "EBIU_AMBCTL Control"
  839. config BANK_0
  840. hex "Bank 0 (AMBCTL0.L)"
  841. default 0x7BB0
  842. help
  843. These are the low 16 bits of the EBIU_AMBCTL0 MMR which are
  844. used to control the Asynchronous Memory Bank 0 settings.
  845. config BANK_1
  846. hex "Bank 1 (AMBCTL0.H)"
  847. default 0x7BB0
  848. default 0x5558 if BF54x
  849. help
  850. These are the high 16 bits of the EBIU_AMBCTL0 MMR which are
  851. used to control the Asynchronous Memory Bank 1 settings.
  852. config BANK_2
  853. hex "Bank 2 (AMBCTL1.L)"
  854. default 0x7BB0
  855. help
  856. These are the low 16 bits of the EBIU_AMBCTL1 MMR which are
  857. used to control the Asynchronous Memory Bank 2 settings.
  858. config BANK_3
  859. hex "Bank 3 (AMBCTL1.H)"
  860. default 0x99B3
  861. help
  862. These are the high 16 bits of the EBIU_AMBCTL1 MMR which are
  863. used to control the Asynchronous Memory Bank 3 settings.
  864. endmenu
  865. config EBIU_MBSCTLVAL
  866. hex "EBIU Bank Select Control Register"
  867. depends on BF54x
  868. default 0
  869. config EBIU_MODEVAL
  870. hex "Flash Memory Mode Control Register"
  871. depends on BF54x
  872. default 1
  873. config EBIU_FCTLVAL
  874. hex "Flash Memory Bank Control Register"
  875. depends on BF54x
  876. default 6
  877. endmenu
  878. #############################################################################
  879. menu "Bus options (PCI, PCMCIA, EISA, MCA, ISA)"
  880. config PCI
  881. bool "PCI support"
  882. depends on BROKEN
  883. help
  884. Support for PCI bus.
  885. source "drivers/pci/Kconfig"
  886. config HOTPLUG
  887. bool "Support for hot-pluggable device"
  888. help
  889. Say Y here if you want to plug devices into your computer while
  890. the system is running, and be able to use them quickly. In many
  891. cases, the devices can likewise be unplugged at any time too.
  892. One well known example of this is PCMCIA- or PC-cards, credit-card
  893. size devices such as network cards, modems or hard drives which are
  894. plugged into slots found on all modern laptop computers. Another
  895. example, used on modern desktops as well as laptops, is USB.
  896. Enable HOTPLUG and build a modular kernel. Get agent software
  897. (from <http://linux-hotplug.sourceforge.net/>) and install it.
  898. Then your kernel will automatically call out to a user mode "policy
  899. agent" (/sbin/hotplug) to load modules and set up software needed
  900. to use devices as you hotplug them.
  901. source "drivers/pcmcia/Kconfig"
  902. source "drivers/pci/hotplug/Kconfig"
  903. endmenu
  904. menu "Executable file formats"
  905. source "fs/Kconfig.binfmt"
  906. endmenu
  907. menu "Power management options"
  908. source "kernel/power/Kconfig"
  909. config ARCH_SUSPEND_POSSIBLE
  910. def_bool y
  911. depends on !SMP
  912. choice
  913. prompt "Standby Power Saving Mode"
  914. depends on PM
  915. default PM_BFIN_SLEEP_DEEPER
  916. config PM_BFIN_SLEEP_DEEPER
  917. bool "Sleep Deeper"
  918. help
  919. Sleep "Deeper" Mode (High Power Savings) - This mode reduces dynamic
  920. power dissipation by disabling the clock to the processor core (CCLK).
  921. Furthermore, Standby sets the internal power supply voltage (VDDINT)
  922. to 0.85 V to provide the greatest power savings, while preserving the
  923. processor state.
  924. The PLL and system clock (SCLK) continue to operate at a very low
  925. frequency of about 3.3 MHz. To preserve data integrity in the SDRAM,
  926. the SDRAM is put into Self Refresh Mode. Typically an external event
  927. such as GPIO interrupt or RTC activity wakes up the processor.
  928. Various Peripherals such as UART, SPORT, PPI may not function as
  929. normal during Sleep Deeper, due to the reduced SCLK frequency.
  930. When in the sleep mode, system DMA access to L1 memory is not supported.
  931. If unsure, select "Sleep Deeper".
  932. config PM_BFIN_SLEEP
  933. bool "Sleep"
  934. help
  935. Sleep Mode (High Power Savings) - The sleep mode reduces power
  936. dissipation by disabling the clock to the processor core (CCLK).
  937. The PLL and system clock (SCLK), however, continue to operate in
  938. this mode. Typically an external event or RTC activity will wake
  939. up the processor. When in the sleep mode, system DMA access to L1
  940. memory is not supported.
  941. If unsure, select "Sleep Deeper".
  942. endchoice
  943. config PM_WAKEUP_BY_GPIO
  944. bool "Allow Wakeup from Standby by GPIO"
  945. depends on PM && !BF54x
  946. config PM_WAKEUP_GPIO_NUMBER
  947. int "GPIO number"
  948. range 0 47
  949. depends on PM_WAKEUP_BY_GPIO
  950. default 2
  951. choice
  952. prompt "GPIO Polarity"
  953. depends on PM_WAKEUP_BY_GPIO
  954. default PM_WAKEUP_GPIO_POLAR_H
  955. config PM_WAKEUP_GPIO_POLAR_H
  956. bool "Active High"
  957. config PM_WAKEUP_GPIO_POLAR_L
  958. bool "Active Low"
  959. config PM_WAKEUP_GPIO_POLAR_EDGE_F
  960. bool "Falling EDGE"
  961. config PM_WAKEUP_GPIO_POLAR_EDGE_R
  962. bool "Rising EDGE"
  963. config PM_WAKEUP_GPIO_POLAR_EDGE_B
  964. bool "Both EDGE"
  965. endchoice
  966. comment "Possible Suspend Mem / Hibernate Wake-Up Sources"
  967. depends on PM
  968. config PM_BFIN_WAKE_PH6
  969. bool "Allow Wake-Up from on-chip PHY or PH6 GP"
  970. depends on PM && (BF51x || BF52x || BF534 || BF536 || BF537)
  971. default n
  972. help
  973. Enable PHY and PH6 GP Wake-Up (Voltage Regulator Power-Up)
  974. config PM_BFIN_WAKE_GP
  975. bool "Allow Wake-Up from GPIOs"
  976. depends on PM && BF54x
  977. default n
  978. help
  979. Enable General-Purpose Wake-Up (Voltage Regulator Power-Up)
  980. (all processors, except ADSP-BF549). This option sets
  981. the general-purpose wake-up enable (GPWE) control bit to enable
  982. wake-up upon detection of an active low signal on the /GPW (PH7) pin.
  983. On ADSP-BF549 this option enables the the same functionality on the
  984. /MRXON pin also PH7.
  985. endmenu
  986. menu "CPU Frequency scaling"
  987. source "drivers/cpufreq/Kconfig"
  988. config BFIN_CPU_FREQ
  989. bool
  990. depends on CPU_FREQ
  991. select CPU_FREQ_TABLE
  992. default y
  993. config CPU_VOLTAGE
  994. bool "CPU Voltage scaling"
  995. depends on EXPERIMENTAL
  996. depends on CPU_FREQ
  997. default n
  998. help
  999. Say Y here if you want CPU voltage scaling according to the CPU frequency.
  1000. This option violates the PLL BYPASS recommendation in the Blackfin Processor
  1001. manuals. There is a theoretical risk that during VDDINT transitions
  1002. the PLL may unlock.
  1003. endmenu
  1004. source "net/Kconfig"
  1005. source "drivers/Kconfig"
  1006. source "fs/Kconfig"
  1007. source "arch/blackfin/Kconfig.debug"
  1008. source "security/Kconfig"
  1009. source "crypto/Kconfig"
  1010. source "lib/Kconfig"