devs.c 39 KB

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  1. /* linux/arch/arm/plat-samsung/devs.c
  2. *
  3. * Copyright (c) 2011 Samsung Electronics Co., Ltd.
  4. * http://www.samsung.com
  5. *
  6. * Base SAMSUNG platform device definitions
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/kernel.h>
  13. #include <linux/types.h>
  14. #include <linux/interrupt.h>
  15. #include <linux/list.h>
  16. #include <linux/timer.h>
  17. #include <linux/init.h>
  18. #include <linux/serial_core.h>
  19. #include <linux/platform_device.h>
  20. #include <linux/io.h>
  21. #include <linux/slab.h>
  22. #include <linux/string.h>
  23. #include <linux/dma-mapping.h>
  24. #include <linux/fb.h>
  25. #include <linux/gfp.h>
  26. #include <linux/mtd/mtd.h>
  27. #include <linux/mtd/onenand.h>
  28. #include <linux/mtd/partitions.h>
  29. #include <linux/mmc/host.h>
  30. #include <linux/ioport.h>
  31. #include <linux/platform_data/s3c-hsudc.h>
  32. #include <linux/platform_data/s3c-hsotg.h>
  33. #include <asm/irq.h>
  34. #include <asm/pmu.h>
  35. #include <asm/mach/arch.h>
  36. #include <asm/mach/map.h>
  37. #include <asm/mach/irq.h>
  38. #include <mach/hardware.h>
  39. #include <mach/dma.h>
  40. #include <mach/irqs.h>
  41. #include <mach/map.h>
  42. #include <plat/cpu.h>
  43. #include <plat/devs.h>
  44. #include <plat/adc.h>
  45. #include <plat/ata.h>
  46. #include <plat/ehci.h>
  47. #include <plat/fb.h>
  48. #include <plat/fb-s3c2410.h>
  49. #include <plat/hwmon.h>
  50. #include <plat/iic.h>
  51. #include <plat/keypad.h>
  52. #include <plat/mci.h>
  53. #include <plat/nand.h>
  54. #include <plat/sdhci.h>
  55. #include <plat/ts.h>
  56. #include <plat/udc.h>
  57. #include <plat/usb-control.h>
  58. #include <plat/usb-phy.h>
  59. #include <plat/regs-iic.h>
  60. #include <plat/regs-serial.h>
  61. #include <plat/regs-spi.h>
  62. #include <plat/s3c64xx-spi.h>
  63. static u64 samsung_device_dma_mask = DMA_BIT_MASK(32);
  64. /* AC97 */
  65. #ifdef CONFIG_CPU_S3C2440
  66. static struct resource s3c_ac97_resource[] = {
  67. [0] = DEFINE_RES_MEM(S3C2440_PA_AC97, S3C2440_SZ_AC97),
  68. [1] = DEFINE_RES_IRQ(IRQ_S3C244X_AC97),
  69. [2] = DEFINE_RES_DMA_NAMED(DMACH_PCM_OUT, "PCM out"),
  70. [3] = DEFINE_RES_DMA_NAMED(DMACH_PCM_IN, "PCM in"),
  71. [4] = DEFINE_RES_DMA_NAMED(DMACH_MIC_IN, "Mic in"),
  72. };
  73. struct platform_device s3c_device_ac97 = {
  74. .name = "samsung-ac97",
  75. .id = -1,
  76. .num_resources = ARRAY_SIZE(s3c_ac97_resource),
  77. .resource = s3c_ac97_resource,
  78. .dev = {
  79. .dma_mask = &samsung_device_dma_mask,
  80. .coherent_dma_mask = DMA_BIT_MASK(32),
  81. }
  82. };
  83. #endif /* CONFIG_CPU_S3C2440 */
  84. /* ADC */
  85. #ifdef CONFIG_PLAT_S3C24XX
  86. static struct resource s3c_adc_resource[] = {
  87. [0] = DEFINE_RES_MEM(S3C24XX_PA_ADC, S3C24XX_SZ_ADC),
  88. [1] = DEFINE_RES_IRQ(IRQ_TC),
  89. [2] = DEFINE_RES_IRQ(IRQ_ADC),
  90. };
  91. struct platform_device s3c_device_adc = {
  92. .name = "s3c24xx-adc",
  93. .id = -1,
  94. .num_resources = ARRAY_SIZE(s3c_adc_resource),
  95. .resource = s3c_adc_resource,
  96. };
  97. #endif /* CONFIG_PLAT_S3C24XX */
  98. #if defined(CONFIG_SAMSUNG_DEV_ADC)
  99. static struct resource s3c_adc_resource[] = {
  100. [0] = DEFINE_RES_MEM(SAMSUNG_PA_ADC, SZ_256),
  101. [1] = DEFINE_RES_IRQ(IRQ_TC),
  102. [2] = DEFINE_RES_IRQ(IRQ_ADC),
  103. };
  104. struct platform_device s3c_device_adc = {
  105. .name = "samsung-adc",
  106. .id = -1,
  107. .num_resources = ARRAY_SIZE(s3c_adc_resource),
  108. .resource = s3c_adc_resource,
  109. };
  110. #endif /* CONFIG_SAMSUNG_DEV_ADC */
  111. /* Camif Controller */
  112. #ifdef CONFIG_CPU_S3C2440
  113. static struct resource s3c_camif_resource[] = {
  114. [0] = DEFINE_RES_MEM(S3C2440_PA_CAMIF, S3C2440_SZ_CAMIF),
  115. [1] = DEFINE_RES_IRQ(IRQ_S3C2440_CAM_C),
  116. [2] = DEFINE_RES_IRQ(IRQ_S3C2440_CAM_P),
  117. };
  118. struct platform_device s3c_device_camif = {
  119. .name = "s3c2440-camif",
  120. .id = -1,
  121. .num_resources = ARRAY_SIZE(s3c_camif_resource),
  122. .resource = s3c_camif_resource,
  123. .dev = {
  124. .dma_mask = &samsung_device_dma_mask,
  125. .coherent_dma_mask = DMA_BIT_MASK(32),
  126. }
  127. };
  128. #endif /* CONFIG_CPU_S3C2440 */
  129. /* ASOC DMA */
  130. struct platform_device samsung_asoc_dma = {
  131. .name = "samsung-audio",
  132. .id = -1,
  133. .dev = {
  134. .dma_mask = &samsung_device_dma_mask,
  135. .coherent_dma_mask = DMA_BIT_MASK(32),
  136. }
  137. };
  138. struct platform_device samsung_asoc_idma = {
  139. .name = "samsung-idma",
  140. .id = -1,
  141. .dev = {
  142. .dma_mask = &samsung_device_dma_mask,
  143. .coherent_dma_mask = DMA_BIT_MASK(32),
  144. }
  145. };
  146. /* FB */
  147. #ifdef CONFIG_S3C_DEV_FB
  148. static struct resource s3c_fb_resource[] = {
  149. [0] = DEFINE_RES_MEM(S3C_PA_FB, SZ_16K),
  150. [1] = DEFINE_RES_IRQ(IRQ_LCD_VSYNC),
  151. [2] = DEFINE_RES_IRQ(IRQ_LCD_FIFO),
  152. [3] = DEFINE_RES_IRQ(IRQ_LCD_SYSTEM),
  153. };
  154. struct platform_device s3c_device_fb = {
  155. .name = "s3c-fb",
  156. .id = -1,
  157. .num_resources = ARRAY_SIZE(s3c_fb_resource),
  158. .resource = s3c_fb_resource,
  159. .dev = {
  160. .dma_mask = &samsung_device_dma_mask,
  161. .coherent_dma_mask = DMA_BIT_MASK(32),
  162. },
  163. };
  164. void __init s3c_fb_set_platdata(struct s3c_fb_platdata *pd)
  165. {
  166. s3c_set_platdata(pd, sizeof(struct s3c_fb_platdata),
  167. &s3c_device_fb);
  168. }
  169. #endif /* CONFIG_S3C_DEV_FB */
  170. /* FIMC */
  171. #ifdef CONFIG_S5P_DEV_FIMC0
  172. static struct resource s5p_fimc0_resource[] = {
  173. [0] = DEFINE_RES_MEM(S5P_PA_FIMC0, SZ_4K),
  174. [1] = DEFINE_RES_IRQ(IRQ_FIMC0),
  175. };
  176. struct platform_device s5p_device_fimc0 = {
  177. .name = "s5p-fimc",
  178. .id = 0,
  179. .num_resources = ARRAY_SIZE(s5p_fimc0_resource),
  180. .resource = s5p_fimc0_resource,
  181. .dev = {
  182. .dma_mask = &samsung_device_dma_mask,
  183. .coherent_dma_mask = DMA_BIT_MASK(32),
  184. },
  185. };
  186. struct platform_device s5p_device_fimc_md = {
  187. .name = "s5p-fimc-md",
  188. .id = -1,
  189. };
  190. #endif /* CONFIG_S5P_DEV_FIMC0 */
  191. #ifdef CONFIG_S5P_DEV_FIMC1
  192. static struct resource s5p_fimc1_resource[] = {
  193. [0] = DEFINE_RES_MEM(S5P_PA_FIMC1, SZ_4K),
  194. [1] = DEFINE_RES_IRQ(IRQ_FIMC1),
  195. };
  196. struct platform_device s5p_device_fimc1 = {
  197. .name = "s5p-fimc",
  198. .id = 1,
  199. .num_resources = ARRAY_SIZE(s5p_fimc1_resource),
  200. .resource = s5p_fimc1_resource,
  201. .dev = {
  202. .dma_mask = &samsung_device_dma_mask,
  203. .coherent_dma_mask = DMA_BIT_MASK(32),
  204. },
  205. };
  206. #endif /* CONFIG_S5P_DEV_FIMC1 */
  207. #ifdef CONFIG_S5P_DEV_FIMC2
  208. static struct resource s5p_fimc2_resource[] = {
  209. [0] = DEFINE_RES_MEM(S5P_PA_FIMC2, SZ_4K),
  210. [1] = DEFINE_RES_IRQ(IRQ_FIMC2),
  211. };
  212. struct platform_device s5p_device_fimc2 = {
  213. .name = "s5p-fimc",
  214. .id = 2,
  215. .num_resources = ARRAY_SIZE(s5p_fimc2_resource),
  216. .resource = s5p_fimc2_resource,
  217. .dev = {
  218. .dma_mask = &samsung_device_dma_mask,
  219. .coherent_dma_mask = DMA_BIT_MASK(32),
  220. },
  221. };
  222. #endif /* CONFIG_S5P_DEV_FIMC2 */
  223. #ifdef CONFIG_S5P_DEV_FIMC3
  224. static struct resource s5p_fimc3_resource[] = {
  225. [0] = DEFINE_RES_MEM(S5P_PA_FIMC3, SZ_4K),
  226. [1] = DEFINE_RES_IRQ(IRQ_FIMC3),
  227. };
  228. struct platform_device s5p_device_fimc3 = {
  229. .name = "s5p-fimc",
  230. .id = 3,
  231. .num_resources = ARRAY_SIZE(s5p_fimc3_resource),
  232. .resource = s5p_fimc3_resource,
  233. .dev = {
  234. .dma_mask = &samsung_device_dma_mask,
  235. .coherent_dma_mask = DMA_BIT_MASK(32),
  236. },
  237. };
  238. #endif /* CONFIG_S5P_DEV_FIMC3 */
  239. /* G2D */
  240. #ifdef CONFIG_S5P_DEV_G2D
  241. static struct resource s5p_g2d_resource[] = {
  242. [0] = DEFINE_RES_MEM(S5P_PA_G2D, SZ_4K),
  243. [1] = DEFINE_RES_IRQ(IRQ_2D),
  244. };
  245. struct platform_device s5p_device_g2d = {
  246. .name = "s5p-g2d",
  247. .id = 0,
  248. .num_resources = ARRAY_SIZE(s5p_g2d_resource),
  249. .resource = s5p_g2d_resource,
  250. .dev = {
  251. .dma_mask = &samsung_device_dma_mask,
  252. .coherent_dma_mask = DMA_BIT_MASK(32),
  253. },
  254. };
  255. #endif /* CONFIG_S5P_DEV_G2D */
  256. #ifdef CONFIG_S5P_DEV_JPEG
  257. static struct resource s5p_jpeg_resource[] = {
  258. [0] = DEFINE_RES_MEM(S5P_PA_JPEG, SZ_4K),
  259. [1] = DEFINE_RES_IRQ(IRQ_JPEG),
  260. };
  261. struct platform_device s5p_device_jpeg = {
  262. .name = "s5p-jpeg",
  263. .id = 0,
  264. .num_resources = ARRAY_SIZE(s5p_jpeg_resource),
  265. .resource = s5p_jpeg_resource,
  266. .dev = {
  267. .dma_mask = &samsung_device_dma_mask,
  268. .coherent_dma_mask = DMA_BIT_MASK(32),
  269. },
  270. };
  271. #endif /* CONFIG_S5P_DEV_JPEG */
  272. /* FIMD0 */
  273. #ifdef CONFIG_S5P_DEV_FIMD0
  274. static struct resource s5p_fimd0_resource[] = {
  275. [0] = DEFINE_RES_MEM(S5P_PA_FIMD0, SZ_32K),
  276. [1] = DEFINE_RES_IRQ(IRQ_FIMD0_VSYNC),
  277. [2] = DEFINE_RES_IRQ(IRQ_FIMD0_FIFO),
  278. [3] = DEFINE_RES_IRQ(IRQ_FIMD0_SYSTEM),
  279. };
  280. struct platform_device s5p_device_fimd0 = {
  281. .name = "s5p-fb",
  282. .id = 0,
  283. .num_resources = ARRAY_SIZE(s5p_fimd0_resource),
  284. .resource = s5p_fimd0_resource,
  285. .dev = {
  286. .dma_mask = &samsung_device_dma_mask,
  287. .coherent_dma_mask = DMA_BIT_MASK(32),
  288. },
  289. };
  290. void __init s5p_fimd0_set_platdata(struct s3c_fb_platdata *pd)
  291. {
  292. s3c_set_platdata(pd, sizeof(struct s3c_fb_platdata),
  293. &s5p_device_fimd0);
  294. }
  295. #endif /* CONFIG_S5P_DEV_FIMD0 */
  296. /* HWMON */
  297. #ifdef CONFIG_S3C_DEV_HWMON
  298. struct platform_device s3c_device_hwmon = {
  299. .name = "s3c-hwmon",
  300. .id = -1,
  301. .dev.parent = &s3c_device_adc.dev,
  302. };
  303. void __init s3c_hwmon_set_platdata(struct s3c_hwmon_pdata *pd)
  304. {
  305. s3c_set_platdata(pd, sizeof(struct s3c_hwmon_pdata),
  306. &s3c_device_hwmon);
  307. }
  308. #endif /* CONFIG_S3C_DEV_HWMON */
  309. /* HSMMC */
  310. #ifdef CONFIG_S3C_DEV_HSMMC
  311. static struct resource s3c_hsmmc_resource[] = {
  312. [0] = DEFINE_RES_MEM(S3C_PA_HSMMC0, SZ_4K),
  313. [1] = DEFINE_RES_IRQ(IRQ_HSMMC0),
  314. };
  315. struct s3c_sdhci_platdata s3c_hsmmc0_def_platdata = {
  316. .max_width = 4,
  317. .host_caps = (MMC_CAP_4_BIT_DATA |
  318. MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
  319. };
  320. struct platform_device s3c_device_hsmmc0 = {
  321. .name = "s3c-sdhci",
  322. .id = 0,
  323. .num_resources = ARRAY_SIZE(s3c_hsmmc_resource),
  324. .resource = s3c_hsmmc_resource,
  325. .dev = {
  326. .dma_mask = &samsung_device_dma_mask,
  327. .coherent_dma_mask = DMA_BIT_MASK(32),
  328. .platform_data = &s3c_hsmmc0_def_platdata,
  329. },
  330. };
  331. void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd)
  332. {
  333. s3c_sdhci_set_platdata(pd, &s3c_hsmmc0_def_platdata);
  334. }
  335. #endif /* CONFIG_S3C_DEV_HSMMC */
  336. #ifdef CONFIG_S3C_DEV_HSMMC1
  337. static struct resource s3c_hsmmc1_resource[] = {
  338. [0] = DEFINE_RES_MEM(S3C_PA_HSMMC1, SZ_4K),
  339. [1] = DEFINE_RES_IRQ(IRQ_HSMMC1),
  340. };
  341. struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata = {
  342. .max_width = 4,
  343. .host_caps = (MMC_CAP_4_BIT_DATA |
  344. MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
  345. };
  346. struct platform_device s3c_device_hsmmc1 = {
  347. .name = "s3c-sdhci",
  348. .id = 1,
  349. .num_resources = ARRAY_SIZE(s3c_hsmmc1_resource),
  350. .resource = s3c_hsmmc1_resource,
  351. .dev = {
  352. .dma_mask = &samsung_device_dma_mask,
  353. .coherent_dma_mask = DMA_BIT_MASK(32),
  354. .platform_data = &s3c_hsmmc1_def_platdata,
  355. },
  356. };
  357. void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd)
  358. {
  359. s3c_sdhci_set_platdata(pd, &s3c_hsmmc1_def_platdata);
  360. }
  361. #endif /* CONFIG_S3C_DEV_HSMMC1 */
  362. /* HSMMC2 */
  363. #ifdef CONFIG_S3C_DEV_HSMMC2
  364. static struct resource s3c_hsmmc2_resource[] = {
  365. [0] = DEFINE_RES_MEM(S3C_PA_HSMMC2, SZ_4K),
  366. [1] = DEFINE_RES_IRQ(IRQ_HSMMC2),
  367. };
  368. struct s3c_sdhci_platdata s3c_hsmmc2_def_platdata = {
  369. .max_width = 4,
  370. .host_caps = (MMC_CAP_4_BIT_DATA |
  371. MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
  372. };
  373. struct platform_device s3c_device_hsmmc2 = {
  374. .name = "s3c-sdhci",
  375. .id = 2,
  376. .num_resources = ARRAY_SIZE(s3c_hsmmc2_resource),
  377. .resource = s3c_hsmmc2_resource,
  378. .dev = {
  379. .dma_mask = &samsung_device_dma_mask,
  380. .coherent_dma_mask = DMA_BIT_MASK(32),
  381. .platform_data = &s3c_hsmmc2_def_platdata,
  382. },
  383. };
  384. void s3c_sdhci2_set_platdata(struct s3c_sdhci_platdata *pd)
  385. {
  386. s3c_sdhci_set_platdata(pd, &s3c_hsmmc2_def_platdata);
  387. }
  388. #endif /* CONFIG_S3C_DEV_HSMMC2 */
  389. #ifdef CONFIG_S3C_DEV_HSMMC3
  390. static struct resource s3c_hsmmc3_resource[] = {
  391. [0] = DEFINE_RES_MEM(S3C_PA_HSMMC3, SZ_4K),
  392. [1] = DEFINE_RES_IRQ(IRQ_HSMMC3),
  393. };
  394. struct s3c_sdhci_platdata s3c_hsmmc3_def_platdata = {
  395. .max_width = 4,
  396. .host_caps = (MMC_CAP_4_BIT_DATA |
  397. MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
  398. };
  399. struct platform_device s3c_device_hsmmc3 = {
  400. .name = "s3c-sdhci",
  401. .id = 3,
  402. .num_resources = ARRAY_SIZE(s3c_hsmmc3_resource),
  403. .resource = s3c_hsmmc3_resource,
  404. .dev = {
  405. .dma_mask = &samsung_device_dma_mask,
  406. .coherent_dma_mask = DMA_BIT_MASK(32),
  407. .platform_data = &s3c_hsmmc3_def_platdata,
  408. },
  409. };
  410. void s3c_sdhci3_set_platdata(struct s3c_sdhci_platdata *pd)
  411. {
  412. s3c_sdhci_set_platdata(pd, &s3c_hsmmc3_def_platdata);
  413. }
  414. #endif /* CONFIG_S3C_DEV_HSMMC3 */
  415. /* I2C */
  416. static struct resource s3c_i2c0_resource[] = {
  417. [0] = DEFINE_RES_MEM(S3C_PA_IIC, SZ_4K),
  418. [1] = DEFINE_RES_IRQ(IRQ_IIC),
  419. };
  420. struct platform_device s3c_device_i2c0 = {
  421. .name = "s3c2410-i2c",
  422. #ifdef CONFIG_S3C_DEV_I2C1
  423. .id = 0,
  424. #else
  425. .id = -1,
  426. #endif
  427. .num_resources = ARRAY_SIZE(s3c_i2c0_resource),
  428. .resource = s3c_i2c0_resource,
  429. };
  430. struct s3c2410_platform_i2c default_i2c_data __initdata = {
  431. .flags = 0,
  432. .slave_addr = 0x10,
  433. .frequency = 100*1000,
  434. .sda_delay = 100,
  435. };
  436. void __init s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *pd)
  437. {
  438. struct s3c2410_platform_i2c *npd;
  439. if (!pd) {
  440. pd = &default_i2c_data;
  441. pd->bus_num = 0;
  442. }
  443. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  444. &s3c_device_i2c0);
  445. if (!npd->cfg_gpio)
  446. npd->cfg_gpio = s3c_i2c0_cfg_gpio;
  447. }
  448. #ifdef CONFIG_S3C_DEV_I2C1
  449. static struct resource s3c_i2c1_resource[] = {
  450. [0] = DEFINE_RES_MEM(S3C_PA_IIC1, SZ_4K),
  451. [1] = DEFINE_RES_IRQ(IRQ_IIC1),
  452. };
  453. struct platform_device s3c_device_i2c1 = {
  454. .name = "s3c2410-i2c",
  455. .id = 1,
  456. .num_resources = ARRAY_SIZE(s3c_i2c1_resource),
  457. .resource = s3c_i2c1_resource,
  458. };
  459. void __init s3c_i2c1_set_platdata(struct s3c2410_platform_i2c *pd)
  460. {
  461. struct s3c2410_platform_i2c *npd;
  462. if (!pd) {
  463. pd = &default_i2c_data;
  464. pd->bus_num = 1;
  465. }
  466. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  467. &s3c_device_i2c1);
  468. if (!npd->cfg_gpio)
  469. npd->cfg_gpio = s3c_i2c1_cfg_gpio;
  470. }
  471. #endif /* CONFIG_S3C_DEV_I2C1 */
  472. #ifdef CONFIG_S3C_DEV_I2C2
  473. static struct resource s3c_i2c2_resource[] = {
  474. [0] = DEFINE_RES_MEM(S3C_PA_IIC2, SZ_4K),
  475. [1] = DEFINE_RES_IRQ(IRQ_IIC2),
  476. };
  477. struct platform_device s3c_device_i2c2 = {
  478. .name = "s3c2410-i2c",
  479. .id = 2,
  480. .num_resources = ARRAY_SIZE(s3c_i2c2_resource),
  481. .resource = s3c_i2c2_resource,
  482. };
  483. void __init s3c_i2c2_set_platdata(struct s3c2410_platform_i2c *pd)
  484. {
  485. struct s3c2410_platform_i2c *npd;
  486. if (!pd) {
  487. pd = &default_i2c_data;
  488. pd->bus_num = 2;
  489. }
  490. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  491. &s3c_device_i2c2);
  492. if (!npd->cfg_gpio)
  493. npd->cfg_gpio = s3c_i2c2_cfg_gpio;
  494. }
  495. #endif /* CONFIG_S3C_DEV_I2C2 */
  496. #ifdef CONFIG_S3C_DEV_I2C3
  497. static struct resource s3c_i2c3_resource[] = {
  498. [0] = DEFINE_RES_MEM(S3C_PA_IIC3, SZ_4K),
  499. [1] = DEFINE_RES_IRQ(IRQ_IIC3),
  500. };
  501. struct platform_device s3c_device_i2c3 = {
  502. .name = "s3c2440-i2c",
  503. .id = 3,
  504. .num_resources = ARRAY_SIZE(s3c_i2c3_resource),
  505. .resource = s3c_i2c3_resource,
  506. };
  507. void __init s3c_i2c3_set_platdata(struct s3c2410_platform_i2c *pd)
  508. {
  509. struct s3c2410_platform_i2c *npd;
  510. if (!pd) {
  511. pd = &default_i2c_data;
  512. pd->bus_num = 3;
  513. }
  514. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  515. &s3c_device_i2c3);
  516. if (!npd->cfg_gpio)
  517. npd->cfg_gpio = s3c_i2c3_cfg_gpio;
  518. }
  519. #endif /*CONFIG_S3C_DEV_I2C3 */
  520. #ifdef CONFIG_S3C_DEV_I2C4
  521. static struct resource s3c_i2c4_resource[] = {
  522. [0] = DEFINE_RES_MEM(S3C_PA_IIC4, SZ_4K),
  523. [1] = DEFINE_RES_IRQ(IRQ_IIC4),
  524. };
  525. struct platform_device s3c_device_i2c4 = {
  526. .name = "s3c2440-i2c",
  527. .id = 4,
  528. .num_resources = ARRAY_SIZE(s3c_i2c4_resource),
  529. .resource = s3c_i2c4_resource,
  530. };
  531. void __init s3c_i2c4_set_platdata(struct s3c2410_platform_i2c *pd)
  532. {
  533. struct s3c2410_platform_i2c *npd;
  534. if (!pd) {
  535. pd = &default_i2c_data;
  536. pd->bus_num = 4;
  537. }
  538. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  539. &s3c_device_i2c4);
  540. if (!npd->cfg_gpio)
  541. npd->cfg_gpio = s3c_i2c4_cfg_gpio;
  542. }
  543. #endif /*CONFIG_S3C_DEV_I2C4 */
  544. #ifdef CONFIG_S3C_DEV_I2C5
  545. static struct resource s3c_i2c5_resource[] = {
  546. [0] = DEFINE_RES_MEM(S3C_PA_IIC5, SZ_4K),
  547. [1] = DEFINE_RES_IRQ(IRQ_IIC5),
  548. };
  549. struct platform_device s3c_device_i2c5 = {
  550. .name = "s3c2440-i2c",
  551. .id = 5,
  552. .num_resources = ARRAY_SIZE(s3c_i2c5_resource),
  553. .resource = s3c_i2c5_resource,
  554. };
  555. void __init s3c_i2c5_set_platdata(struct s3c2410_platform_i2c *pd)
  556. {
  557. struct s3c2410_platform_i2c *npd;
  558. if (!pd) {
  559. pd = &default_i2c_data;
  560. pd->bus_num = 5;
  561. }
  562. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  563. &s3c_device_i2c5);
  564. if (!npd->cfg_gpio)
  565. npd->cfg_gpio = s3c_i2c5_cfg_gpio;
  566. }
  567. #endif /*CONFIG_S3C_DEV_I2C5 */
  568. #ifdef CONFIG_S3C_DEV_I2C6
  569. static struct resource s3c_i2c6_resource[] = {
  570. [0] = DEFINE_RES_MEM(S3C_PA_IIC6, SZ_4K),
  571. [1] = DEFINE_RES_IRQ(IRQ_IIC6),
  572. };
  573. struct platform_device s3c_device_i2c6 = {
  574. .name = "s3c2440-i2c",
  575. .id = 6,
  576. .num_resources = ARRAY_SIZE(s3c_i2c6_resource),
  577. .resource = s3c_i2c6_resource,
  578. };
  579. void __init s3c_i2c6_set_platdata(struct s3c2410_platform_i2c *pd)
  580. {
  581. struct s3c2410_platform_i2c *npd;
  582. if (!pd) {
  583. pd = &default_i2c_data;
  584. pd->bus_num = 6;
  585. }
  586. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  587. &s3c_device_i2c6);
  588. if (!npd->cfg_gpio)
  589. npd->cfg_gpio = s3c_i2c6_cfg_gpio;
  590. }
  591. #endif /* CONFIG_S3C_DEV_I2C6 */
  592. #ifdef CONFIG_S3C_DEV_I2C7
  593. static struct resource s3c_i2c7_resource[] = {
  594. [0] = DEFINE_RES_MEM(S3C_PA_IIC7, SZ_4K),
  595. [1] = DEFINE_RES_IRQ(IRQ_IIC7),
  596. };
  597. struct platform_device s3c_device_i2c7 = {
  598. .name = "s3c2440-i2c",
  599. .id = 7,
  600. .num_resources = ARRAY_SIZE(s3c_i2c7_resource),
  601. .resource = s3c_i2c7_resource,
  602. };
  603. void __init s3c_i2c7_set_platdata(struct s3c2410_platform_i2c *pd)
  604. {
  605. struct s3c2410_platform_i2c *npd;
  606. if (!pd) {
  607. pd = &default_i2c_data;
  608. pd->bus_num = 7;
  609. }
  610. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  611. &s3c_device_i2c7);
  612. if (!npd->cfg_gpio)
  613. npd->cfg_gpio = s3c_i2c7_cfg_gpio;
  614. }
  615. #endif /* CONFIG_S3C_DEV_I2C7 */
  616. /* I2C HDMIPHY */
  617. #ifdef CONFIG_S5P_DEV_I2C_HDMIPHY
  618. static struct resource s5p_i2c_resource[] = {
  619. [0] = DEFINE_RES_MEM(S5P_PA_IIC_HDMIPHY, SZ_4K),
  620. [1] = DEFINE_RES_IRQ(IRQ_IIC_HDMIPHY),
  621. };
  622. struct platform_device s5p_device_i2c_hdmiphy = {
  623. .name = "s3c2440-hdmiphy-i2c",
  624. .id = -1,
  625. .num_resources = ARRAY_SIZE(s5p_i2c_resource),
  626. .resource = s5p_i2c_resource,
  627. };
  628. void __init s5p_i2c_hdmiphy_set_platdata(struct s3c2410_platform_i2c *pd)
  629. {
  630. struct s3c2410_platform_i2c *npd;
  631. if (!pd) {
  632. pd = &default_i2c_data;
  633. if (soc_is_exynos4210() ||
  634. soc_is_exynos4212() || soc_is_exynos4412())
  635. pd->bus_num = 8;
  636. else if (soc_is_s5pv210())
  637. pd->bus_num = 3;
  638. else
  639. pd->bus_num = 0;
  640. }
  641. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  642. &s5p_device_i2c_hdmiphy);
  643. }
  644. #endif /* CONFIG_S5P_DEV_I2C_HDMIPHY */
  645. /* I2S */
  646. #ifdef CONFIG_PLAT_S3C24XX
  647. static struct resource s3c_iis_resource[] = {
  648. [0] = DEFINE_RES_MEM(S3C24XX_PA_IIS, S3C24XX_SZ_IIS),
  649. };
  650. struct platform_device s3c_device_iis = {
  651. .name = "s3c24xx-iis",
  652. .id = -1,
  653. .num_resources = ARRAY_SIZE(s3c_iis_resource),
  654. .resource = s3c_iis_resource,
  655. .dev = {
  656. .dma_mask = &samsung_device_dma_mask,
  657. .coherent_dma_mask = DMA_BIT_MASK(32),
  658. }
  659. };
  660. #endif /* CONFIG_PLAT_S3C24XX */
  661. /* IDE CFCON */
  662. #ifdef CONFIG_SAMSUNG_DEV_IDE
  663. static struct resource s3c_cfcon_resource[] = {
  664. [0] = DEFINE_RES_MEM(SAMSUNG_PA_CFCON, SZ_16K),
  665. [1] = DEFINE_RES_IRQ(IRQ_CFCON),
  666. };
  667. struct platform_device s3c_device_cfcon = {
  668. .id = 0,
  669. .num_resources = ARRAY_SIZE(s3c_cfcon_resource),
  670. .resource = s3c_cfcon_resource,
  671. };
  672. void __init s3c_ide_set_platdata(struct s3c_ide_platdata *pdata)
  673. {
  674. s3c_set_platdata(pdata, sizeof(struct s3c_ide_platdata),
  675. &s3c_device_cfcon);
  676. }
  677. #endif /* CONFIG_SAMSUNG_DEV_IDE */
  678. /* KEYPAD */
  679. #ifdef CONFIG_SAMSUNG_DEV_KEYPAD
  680. static struct resource samsung_keypad_resources[] = {
  681. [0] = DEFINE_RES_MEM(SAMSUNG_PA_KEYPAD, SZ_32),
  682. [1] = DEFINE_RES_IRQ(IRQ_KEYPAD),
  683. };
  684. struct platform_device samsung_device_keypad = {
  685. .name = "samsung-keypad",
  686. .id = -1,
  687. .num_resources = ARRAY_SIZE(samsung_keypad_resources),
  688. .resource = samsung_keypad_resources,
  689. };
  690. void __init samsung_keypad_set_platdata(struct samsung_keypad_platdata *pd)
  691. {
  692. struct samsung_keypad_platdata *npd;
  693. npd = s3c_set_platdata(pd, sizeof(struct samsung_keypad_platdata),
  694. &samsung_device_keypad);
  695. if (!npd->cfg_gpio)
  696. npd->cfg_gpio = samsung_keypad_cfg_gpio;
  697. }
  698. #endif /* CONFIG_SAMSUNG_DEV_KEYPAD */
  699. /* LCD Controller */
  700. #ifdef CONFIG_PLAT_S3C24XX
  701. static struct resource s3c_lcd_resource[] = {
  702. [0] = DEFINE_RES_MEM(S3C24XX_PA_LCD, S3C24XX_SZ_LCD),
  703. [1] = DEFINE_RES_IRQ(IRQ_LCD),
  704. };
  705. struct platform_device s3c_device_lcd = {
  706. .name = "s3c2410-lcd",
  707. .id = -1,
  708. .num_resources = ARRAY_SIZE(s3c_lcd_resource),
  709. .resource = s3c_lcd_resource,
  710. .dev = {
  711. .dma_mask = &samsung_device_dma_mask,
  712. .coherent_dma_mask = DMA_BIT_MASK(32),
  713. }
  714. };
  715. void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *pd)
  716. {
  717. struct s3c2410fb_mach_info *npd;
  718. npd = s3c_set_platdata(pd, sizeof(*npd), &s3c_device_lcd);
  719. if (npd) {
  720. npd->displays = kmemdup(pd->displays,
  721. sizeof(struct s3c2410fb_display) * npd->num_displays,
  722. GFP_KERNEL);
  723. if (!npd->displays)
  724. printk(KERN_ERR "no memory for LCD display data\n");
  725. } else {
  726. printk(KERN_ERR "no memory for LCD platform data\n");
  727. }
  728. }
  729. #endif /* CONFIG_PLAT_S3C24XX */
  730. /* MFC */
  731. #ifdef CONFIG_S5P_DEV_MFC
  732. static struct resource s5p_mfc_resource[] = {
  733. [0] = DEFINE_RES_MEM(S5P_PA_MFC, SZ_64K),
  734. [1] = DEFINE_RES_IRQ(IRQ_MFC),
  735. };
  736. struct platform_device s5p_device_mfc = {
  737. .name = "s5p-mfc",
  738. .id = -1,
  739. .num_resources = ARRAY_SIZE(s5p_mfc_resource),
  740. .resource = s5p_mfc_resource,
  741. };
  742. /*
  743. * MFC hardware has 2 memory interfaces which are modelled as two separate
  744. * platform devices to let dma-mapping distinguish between them.
  745. *
  746. * MFC parent device (s5p_device_mfc) must be registered before memory
  747. * interface specific devices (s5p_device_mfc_l and s5p_device_mfc_r).
  748. */
  749. struct platform_device s5p_device_mfc_l = {
  750. .name = "s5p-mfc-l",
  751. .id = -1,
  752. .dev = {
  753. .parent = &s5p_device_mfc.dev,
  754. .dma_mask = &samsung_device_dma_mask,
  755. .coherent_dma_mask = DMA_BIT_MASK(32),
  756. },
  757. };
  758. struct platform_device s5p_device_mfc_r = {
  759. .name = "s5p-mfc-r",
  760. .id = -1,
  761. .dev = {
  762. .parent = &s5p_device_mfc.dev,
  763. .dma_mask = &samsung_device_dma_mask,
  764. .coherent_dma_mask = DMA_BIT_MASK(32),
  765. },
  766. };
  767. #endif /* CONFIG_S5P_DEV_MFC */
  768. /* MIPI CSIS */
  769. #ifdef CONFIG_S5P_DEV_CSIS0
  770. static struct resource s5p_mipi_csis0_resource[] = {
  771. [0] = DEFINE_RES_MEM(S5P_PA_MIPI_CSIS0, SZ_16K),
  772. [1] = DEFINE_RES_IRQ(IRQ_MIPI_CSIS0),
  773. };
  774. struct platform_device s5p_device_mipi_csis0 = {
  775. .name = "s5p-mipi-csis",
  776. .id = 0,
  777. .num_resources = ARRAY_SIZE(s5p_mipi_csis0_resource),
  778. .resource = s5p_mipi_csis0_resource,
  779. };
  780. #endif /* CONFIG_S5P_DEV_CSIS0 */
  781. #ifdef CONFIG_S5P_DEV_CSIS1
  782. static struct resource s5p_mipi_csis1_resource[] = {
  783. [0] = DEFINE_RES_MEM(S5P_PA_MIPI_CSIS1, SZ_16K),
  784. [1] = DEFINE_RES_IRQ(IRQ_MIPI_CSIS1),
  785. };
  786. struct platform_device s5p_device_mipi_csis1 = {
  787. .name = "s5p-mipi-csis",
  788. .id = 1,
  789. .num_resources = ARRAY_SIZE(s5p_mipi_csis1_resource),
  790. .resource = s5p_mipi_csis1_resource,
  791. };
  792. #endif
  793. /* NAND */
  794. #ifdef CONFIG_S3C_DEV_NAND
  795. static struct resource s3c_nand_resource[] = {
  796. [0] = DEFINE_RES_MEM(S3C_PA_NAND, SZ_1M),
  797. };
  798. struct platform_device s3c_device_nand = {
  799. .name = "s3c2410-nand",
  800. .id = -1,
  801. .num_resources = ARRAY_SIZE(s3c_nand_resource),
  802. .resource = s3c_nand_resource,
  803. };
  804. /*
  805. * s3c_nand_copy_set() - copy nand set data
  806. * @set: The new structure, directly copied from the old.
  807. *
  808. * Copy all the fields from the NAND set field from what is probably __initdata
  809. * to new kernel memory. The code returns 0 if the copy happened correctly or
  810. * an error code for the calling function to display.
  811. *
  812. * Note, we currently do not try and look to see if we've already copied the
  813. * data in a previous set.
  814. */
  815. static int __init s3c_nand_copy_set(struct s3c2410_nand_set *set)
  816. {
  817. void *ptr;
  818. int size;
  819. size = sizeof(struct mtd_partition) * set->nr_partitions;
  820. if (size) {
  821. ptr = kmemdup(set->partitions, size, GFP_KERNEL);
  822. set->partitions = ptr;
  823. if (!ptr)
  824. return -ENOMEM;
  825. }
  826. if (set->nr_map && set->nr_chips) {
  827. size = sizeof(int) * set->nr_chips;
  828. ptr = kmemdup(set->nr_map, size, GFP_KERNEL);
  829. set->nr_map = ptr;
  830. if (!ptr)
  831. return -ENOMEM;
  832. }
  833. if (set->ecc_layout) {
  834. ptr = kmemdup(set->ecc_layout,
  835. sizeof(struct nand_ecclayout), GFP_KERNEL);
  836. set->ecc_layout = ptr;
  837. if (!ptr)
  838. return -ENOMEM;
  839. }
  840. return 0;
  841. }
  842. void __init s3c_nand_set_platdata(struct s3c2410_platform_nand *nand)
  843. {
  844. struct s3c2410_platform_nand *npd;
  845. int size;
  846. int ret;
  847. /* note, if we get a failure in allocation, we simply drop out of the
  848. * function. If there is so little memory available at initialisation
  849. * time then there is little chance the system is going to run.
  850. */
  851. npd = s3c_set_platdata(nand, sizeof(struct s3c2410_platform_nand),
  852. &s3c_device_nand);
  853. if (!npd)
  854. return;
  855. /* now see if we need to copy any of the nand set data */
  856. size = sizeof(struct s3c2410_nand_set) * npd->nr_sets;
  857. if (size) {
  858. struct s3c2410_nand_set *from = npd->sets;
  859. struct s3c2410_nand_set *to;
  860. int i;
  861. to = kmemdup(from, size, GFP_KERNEL);
  862. npd->sets = to; /* set, even if we failed */
  863. if (!to) {
  864. printk(KERN_ERR "%s: no memory for sets\n", __func__);
  865. return;
  866. }
  867. for (i = 0; i < npd->nr_sets; i++) {
  868. ret = s3c_nand_copy_set(to);
  869. if (ret) {
  870. printk(KERN_ERR "%s: failed to copy set %d\n",
  871. __func__, i);
  872. return;
  873. }
  874. to++;
  875. }
  876. }
  877. }
  878. #endif /* CONFIG_S3C_DEV_NAND */
  879. /* ONENAND */
  880. #ifdef CONFIG_S3C_DEV_ONENAND
  881. static struct resource s3c_onenand_resources[] = {
  882. [0] = DEFINE_RES_MEM(S3C_PA_ONENAND, SZ_1K),
  883. [1] = DEFINE_RES_MEM(S3C_PA_ONENAND_BUF, S3C_SZ_ONENAND_BUF),
  884. [2] = DEFINE_RES_IRQ(IRQ_ONENAND),
  885. };
  886. struct platform_device s3c_device_onenand = {
  887. .name = "samsung-onenand",
  888. .id = 0,
  889. .num_resources = ARRAY_SIZE(s3c_onenand_resources),
  890. .resource = s3c_onenand_resources,
  891. };
  892. #endif /* CONFIG_S3C_DEV_ONENAND */
  893. #ifdef CONFIG_S3C64XX_DEV_ONENAND1
  894. static struct resource s3c64xx_onenand1_resources[] = {
  895. [0] = DEFINE_RES_MEM(S3C64XX_PA_ONENAND1, SZ_1K),
  896. [1] = DEFINE_RES_MEM(S3C64XX_PA_ONENAND1_BUF, S3C64XX_SZ_ONENAND1_BUF),
  897. [2] = DEFINE_RES_IRQ(IRQ_ONENAND1),
  898. };
  899. struct platform_device s3c64xx_device_onenand1 = {
  900. .name = "samsung-onenand",
  901. .id = 1,
  902. .num_resources = ARRAY_SIZE(s3c64xx_onenand1_resources),
  903. .resource = s3c64xx_onenand1_resources,
  904. };
  905. void __init s3c64xx_onenand1_set_platdata(struct onenand_platform_data *pdata)
  906. {
  907. s3c_set_platdata(pdata, sizeof(struct onenand_platform_data),
  908. &s3c64xx_device_onenand1);
  909. }
  910. #endif /* CONFIG_S3C64XX_DEV_ONENAND1 */
  911. #ifdef CONFIG_S5P_DEV_ONENAND
  912. static struct resource s5p_onenand_resources[] = {
  913. [0] = DEFINE_RES_MEM(S5P_PA_ONENAND, SZ_128K),
  914. [1] = DEFINE_RES_MEM(S5P_PA_ONENAND_DMA, SZ_8K),
  915. [2] = DEFINE_RES_IRQ(IRQ_ONENAND_AUDI),
  916. };
  917. struct platform_device s5p_device_onenand = {
  918. .name = "s5pc110-onenand",
  919. .id = -1,
  920. .num_resources = ARRAY_SIZE(s5p_onenand_resources),
  921. .resource = s5p_onenand_resources,
  922. };
  923. #endif /* CONFIG_S5P_DEV_ONENAND */
  924. /* PMU */
  925. #ifdef CONFIG_PLAT_S5P
  926. static struct resource s5p_pmu_resource[] = {
  927. DEFINE_RES_IRQ(IRQ_PMU)
  928. };
  929. static struct platform_device s5p_device_pmu = {
  930. .name = "arm-pmu",
  931. .id = ARM_PMU_DEVICE_CPU,
  932. .num_resources = ARRAY_SIZE(s5p_pmu_resource),
  933. .resource = s5p_pmu_resource,
  934. };
  935. static int __init s5p_pmu_init(void)
  936. {
  937. platform_device_register(&s5p_device_pmu);
  938. return 0;
  939. }
  940. arch_initcall(s5p_pmu_init);
  941. #endif /* CONFIG_PLAT_S5P */
  942. /* PWM Timer */
  943. #ifdef CONFIG_SAMSUNG_DEV_PWM
  944. #define TIMER_RESOURCE_SIZE (1)
  945. #define TIMER_RESOURCE(_tmr, _irq) \
  946. (struct resource [TIMER_RESOURCE_SIZE]) { \
  947. [0] = { \
  948. .start = _irq, \
  949. .end = _irq, \
  950. .flags = IORESOURCE_IRQ \
  951. } \
  952. }
  953. #define DEFINE_S3C_TIMER(_tmr_no, _irq) \
  954. .name = "s3c24xx-pwm", \
  955. .id = _tmr_no, \
  956. .num_resources = TIMER_RESOURCE_SIZE, \
  957. .resource = TIMER_RESOURCE(_tmr_no, _irq), \
  958. /*
  959. * since we already have an static mapping for the timer,
  960. * we do not bother setting any IO resource for the base.
  961. */
  962. struct platform_device s3c_device_timer[] = {
  963. [0] = { DEFINE_S3C_TIMER(0, IRQ_TIMER0) },
  964. [1] = { DEFINE_S3C_TIMER(1, IRQ_TIMER1) },
  965. [2] = { DEFINE_S3C_TIMER(2, IRQ_TIMER2) },
  966. [3] = { DEFINE_S3C_TIMER(3, IRQ_TIMER3) },
  967. [4] = { DEFINE_S3C_TIMER(4, IRQ_TIMER4) },
  968. };
  969. #endif /* CONFIG_SAMSUNG_DEV_PWM */
  970. /* RTC */
  971. #ifdef CONFIG_PLAT_S3C24XX
  972. static struct resource s3c_rtc_resource[] = {
  973. [0] = DEFINE_RES_MEM(S3C24XX_PA_RTC, SZ_256),
  974. [1] = DEFINE_RES_IRQ(IRQ_RTC),
  975. [2] = DEFINE_RES_IRQ(IRQ_TICK),
  976. };
  977. struct platform_device s3c_device_rtc = {
  978. .name = "s3c2410-rtc",
  979. .id = -1,
  980. .num_resources = ARRAY_SIZE(s3c_rtc_resource),
  981. .resource = s3c_rtc_resource,
  982. };
  983. #endif /* CONFIG_PLAT_S3C24XX */
  984. #ifdef CONFIG_S3C_DEV_RTC
  985. static struct resource s3c_rtc_resource[] = {
  986. [0] = DEFINE_RES_MEM(S3C_PA_RTC, SZ_256),
  987. [1] = DEFINE_RES_IRQ(IRQ_RTC_ALARM),
  988. [2] = DEFINE_RES_IRQ(IRQ_RTC_TIC),
  989. };
  990. struct platform_device s3c_device_rtc = {
  991. .name = "s3c64xx-rtc",
  992. .id = -1,
  993. .num_resources = ARRAY_SIZE(s3c_rtc_resource),
  994. .resource = s3c_rtc_resource,
  995. };
  996. #endif /* CONFIG_S3C_DEV_RTC */
  997. /* SDI */
  998. #ifdef CONFIG_PLAT_S3C24XX
  999. static struct resource s3c_sdi_resource[] = {
  1000. [0] = DEFINE_RES_MEM(S3C24XX_PA_SDI, S3C24XX_SZ_SDI),
  1001. [1] = DEFINE_RES_IRQ(IRQ_SDI),
  1002. };
  1003. struct platform_device s3c_device_sdi = {
  1004. .name = "s3c2410-sdi",
  1005. .id = -1,
  1006. .num_resources = ARRAY_SIZE(s3c_sdi_resource),
  1007. .resource = s3c_sdi_resource,
  1008. };
  1009. void __init s3c24xx_mci_set_platdata(struct s3c24xx_mci_pdata *pdata)
  1010. {
  1011. s3c_set_platdata(pdata, sizeof(struct s3c24xx_mci_pdata),
  1012. &s3c_device_sdi);
  1013. }
  1014. #endif /* CONFIG_PLAT_S3C24XX */
  1015. /* SPI */
  1016. #ifdef CONFIG_PLAT_S3C24XX
  1017. static struct resource s3c_spi0_resource[] = {
  1018. [0] = DEFINE_RES_MEM(S3C24XX_PA_SPI, SZ_32),
  1019. [1] = DEFINE_RES_IRQ(IRQ_SPI0),
  1020. };
  1021. struct platform_device s3c_device_spi0 = {
  1022. .name = "s3c2410-spi",
  1023. .id = 0,
  1024. .num_resources = ARRAY_SIZE(s3c_spi0_resource),
  1025. .resource = s3c_spi0_resource,
  1026. .dev = {
  1027. .dma_mask = &samsung_device_dma_mask,
  1028. .coherent_dma_mask = DMA_BIT_MASK(32),
  1029. }
  1030. };
  1031. static struct resource s3c_spi1_resource[] = {
  1032. [0] = DEFINE_RES_MEM(S3C24XX_PA_SPI1, SZ_32),
  1033. [1] = DEFINE_RES_IRQ(IRQ_SPI1),
  1034. };
  1035. struct platform_device s3c_device_spi1 = {
  1036. .name = "s3c2410-spi",
  1037. .id = 1,
  1038. .num_resources = ARRAY_SIZE(s3c_spi1_resource),
  1039. .resource = s3c_spi1_resource,
  1040. .dev = {
  1041. .dma_mask = &samsung_device_dma_mask,
  1042. .coherent_dma_mask = DMA_BIT_MASK(32),
  1043. }
  1044. };
  1045. #endif /* CONFIG_PLAT_S3C24XX */
  1046. /* Touchscreen */
  1047. #ifdef CONFIG_PLAT_S3C24XX
  1048. static struct resource s3c_ts_resource[] = {
  1049. [0] = DEFINE_RES_MEM(S3C24XX_PA_ADC, S3C24XX_SZ_ADC),
  1050. [1] = DEFINE_RES_IRQ(IRQ_TC),
  1051. };
  1052. struct platform_device s3c_device_ts = {
  1053. .name = "s3c2410-ts",
  1054. .id = -1,
  1055. .dev.parent = &s3c_device_adc.dev,
  1056. .num_resources = ARRAY_SIZE(s3c_ts_resource),
  1057. .resource = s3c_ts_resource,
  1058. };
  1059. void __init s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *hard_s3c2410ts_info)
  1060. {
  1061. s3c_set_platdata(hard_s3c2410ts_info,
  1062. sizeof(struct s3c2410_ts_mach_info), &s3c_device_ts);
  1063. }
  1064. #endif /* CONFIG_PLAT_S3C24XX */
  1065. #ifdef CONFIG_SAMSUNG_DEV_TS
  1066. static struct resource s3c_ts_resource[] = {
  1067. [0] = DEFINE_RES_MEM(SAMSUNG_PA_ADC, SZ_256),
  1068. [1] = DEFINE_RES_IRQ(IRQ_TC),
  1069. };
  1070. static struct s3c2410_ts_mach_info default_ts_data __initdata = {
  1071. .delay = 10000,
  1072. .presc = 49,
  1073. .oversampling_shift = 2,
  1074. };
  1075. struct platform_device s3c_device_ts = {
  1076. .name = "s3c64xx-ts",
  1077. .id = -1,
  1078. .num_resources = ARRAY_SIZE(s3c_ts_resource),
  1079. .resource = s3c_ts_resource,
  1080. };
  1081. void __init s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *pd)
  1082. {
  1083. if (!pd)
  1084. pd = &default_ts_data;
  1085. s3c_set_platdata(pd, sizeof(struct s3c2410_ts_mach_info),
  1086. &s3c_device_ts);
  1087. }
  1088. #endif /* CONFIG_SAMSUNG_DEV_TS */
  1089. /* TV */
  1090. #ifdef CONFIG_S5P_DEV_TV
  1091. static struct resource s5p_hdmi_resources[] = {
  1092. [0] = DEFINE_RES_MEM(S5P_PA_HDMI, SZ_1M),
  1093. [1] = DEFINE_RES_IRQ(IRQ_HDMI),
  1094. };
  1095. struct platform_device s5p_device_hdmi = {
  1096. .name = "s5p-hdmi",
  1097. .id = -1,
  1098. .num_resources = ARRAY_SIZE(s5p_hdmi_resources),
  1099. .resource = s5p_hdmi_resources,
  1100. };
  1101. static struct resource s5p_sdo_resources[] = {
  1102. [0] = DEFINE_RES_MEM(S5P_PA_SDO, SZ_64K),
  1103. [1] = DEFINE_RES_IRQ(IRQ_SDO),
  1104. };
  1105. struct platform_device s5p_device_sdo = {
  1106. .name = "s5p-sdo",
  1107. .id = -1,
  1108. .num_resources = ARRAY_SIZE(s5p_sdo_resources),
  1109. .resource = s5p_sdo_resources,
  1110. };
  1111. static struct resource s5p_mixer_resources[] = {
  1112. [0] = DEFINE_RES_MEM_NAMED(S5P_PA_MIXER, SZ_64K, "mxr"),
  1113. [1] = DEFINE_RES_MEM_NAMED(S5P_PA_VP, SZ_64K, "vp"),
  1114. [2] = DEFINE_RES_IRQ_NAMED(IRQ_MIXER, "irq"),
  1115. };
  1116. struct platform_device s5p_device_mixer = {
  1117. .name = "s5p-mixer",
  1118. .id = -1,
  1119. .num_resources = ARRAY_SIZE(s5p_mixer_resources),
  1120. .resource = s5p_mixer_resources,
  1121. .dev = {
  1122. .dma_mask = &samsung_device_dma_mask,
  1123. .coherent_dma_mask = DMA_BIT_MASK(32),
  1124. }
  1125. };
  1126. #endif /* CONFIG_S5P_DEV_TV */
  1127. /* USB */
  1128. #ifdef CONFIG_S3C_DEV_USB_HOST
  1129. static struct resource s3c_usb_resource[] = {
  1130. [0] = DEFINE_RES_MEM(S3C_PA_USBHOST, SZ_256),
  1131. [1] = DEFINE_RES_IRQ(IRQ_USBH),
  1132. };
  1133. struct platform_device s3c_device_ohci = {
  1134. .name = "s3c2410-ohci",
  1135. .id = -1,
  1136. .num_resources = ARRAY_SIZE(s3c_usb_resource),
  1137. .resource = s3c_usb_resource,
  1138. .dev = {
  1139. .dma_mask = &samsung_device_dma_mask,
  1140. .coherent_dma_mask = DMA_BIT_MASK(32),
  1141. }
  1142. };
  1143. /*
  1144. * s3c_ohci_set_platdata - initialise OHCI device platform data
  1145. * @info: The platform data.
  1146. *
  1147. * This call copies the @info passed in and sets the device .platform_data
  1148. * field to that copy. The @info is copied so that the original can be marked
  1149. * __initdata.
  1150. */
  1151. void __init s3c_ohci_set_platdata(struct s3c2410_hcd_info *info)
  1152. {
  1153. s3c_set_platdata(info, sizeof(struct s3c2410_hcd_info),
  1154. &s3c_device_ohci);
  1155. }
  1156. #endif /* CONFIG_S3C_DEV_USB_HOST */
  1157. /* USB Device (Gadget) */
  1158. #ifdef CONFIG_PLAT_S3C24XX
  1159. static struct resource s3c_usbgadget_resource[] = {
  1160. [0] = DEFINE_RES_MEM(S3C24XX_PA_USBDEV, S3C24XX_SZ_USBDEV),
  1161. [1] = DEFINE_RES_IRQ(IRQ_USBD),
  1162. };
  1163. struct platform_device s3c_device_usbgadget = {
  1164. .name = "s3c2410-usbgadget",
  1165. .id = -1,
  1166. .num_resources = ARRAY_SIZE(s3c_usbgadget_resource),
  1167. .resource = s3c_usbgadget_resource,
  1168. };
  1169. void __init s3c24xx_udc_set_platdata(struct s3c2410_udc_mach_info *pd)
  1170. {
  1171. s3c_set_platdata(pd, sizeof(*pd), &s3c_device_usbgadget);
  1172. }
  1173. #endif /* CONFIG_PLAT_S3C24XX */
  1174. /* USB EHCI Host Controller */
  1175. #ifdef CONFIG_S5P_DEV_USB_EHCI
  1176. static struct resource s5p_ehci_resource[] = {
  1177. [0] = DEFINE_RES_MEM(S5P_PA_EHCI, SZ_256),
  1178. [1] = DEFINE_RES_IRQ(IRQ_USB_HOST),
  1179. };
  1180. struct platform_device s5p_device_ehci = {
  1181. .name = "s5p-ehci",
  1182. .id = -1,
  1183. .num_resources = ARRAY_SIZE(s5p_ehci_resource),
  1184. .resource = s5p_ehci_resource,
  1185. .dev = {
  1186. .dma_mask = &samsung_device_dma_mask,
  1187. .coherent_dma_mask = DMA_BIT_MASK(32),
  1188. }
  1189. };
  1190. void __init s5p_ehci_set_platdata(struct s5p_ehci_platdata *pd)
  1191. {
  1192. struct s5p_ehci_platdata *npd;
  1193. npd = s3c_set_platdata(pd, sizeof(struct s5p_ehci_platdata),
  1194. &s5p_device_ehci);
  1195. if (!npd->phy_init)
  1196. npd->phy_init = s5p_usb_phy_init;
  1197. if (!npd->phy_exit)
  1198. npd->phy_exit = s5p_usb_phy_exit;
  1199. }
  1200. #endif /* CONFIG_S5P_DEV_USB_EHCI */
  1201. /* USB HSOTG */
  1202. #ifdef CONFIG_S3C_DEV_USB_HSOTG
  1203. static struct resource s3c_usb_hsotg_resources[] = {
  1204. [0] = DEFINE_RES_MEM(S3C_PA_USB_HSOTG, SZ_128K),
  1205. [1] = DEFINE_RES_IRQ(IRQ_OTG),
  1206. };
  1207. struct platform_device s3c_device_usb_hsotg = {
  1208. .name = "s3c-hsotg",
  1209. .id = -1,
  1210. .num_resources = ARRAY_SIZE(s3c_usb_hsotg_resources),
  1211. .resource = s3c_usb_hsotg_resources,
  1212. .dev = {
  1213. .dma_mask = &samsung_device_dma_mask,
  1214. .coherent_dma_mask = DMA_BIT_MASK(32),
  1215. },
  1216. };
  1217. void __init s3c_hsotg_set_platdata(struct s3c_hsotg_plat *pd)
  1218. {
  1219. struct s3c_hsotg_plat *npd;
  1220. npd = s3c_set_platdata(pd, sizeof(struct s3c_hsotg_plat),
  1221. &s3c_device_usb_hsotg);
  1222. if (!npd->phy_init)
  1223. npd->phy_init = s5p_usb_phy_init;
  1224. if (!npd->phy_exit)
  1225. npd->phy_exit = s5p_usb_phy_exit;
  1226. }
  1227. #endif /* CONFIG_S3C_DEV_USB_HSOTG */
  1228. /* USB High Spped 2.0 Device (Gadget) */
  1229. #ifdef CONFIG_PLAT_S3C24XX
  1230. static struct resource s3c_hsudc_resource[] = {
  1231. [0] = DEFINE_RES_MEM(S3C2416_PA_HSUDC, S3C2416_SZ_HSUDC),
  1232. [1] = DEFINE_RES_IRQ(IRQ_USBD),
  1233. };
  1234. struct platform_device s3c_device_usb_hsudc = {
  1235. .name = "s3c-hsudc",
  1236. .id = -1,
  1237. .num_resources = ARRAY_SIZE(s3c_hsudc_resource),
  1238. .resource = s3c_hsudc_resource,
  1239. .dev = {
  1240. .dma_mask = &samsung_device_dma_mask,
  1241. .coherent_dma_mask = DMA_BIT_MASK(32),
  1242. },
  1243. };
  1244. void __init s3c24xx_hsudc_set_platdata(struct s3c24xx_hsudc_platdata *pd)
  1245. {
  1246. s3c_set_platdata(pd, sizeof(*pd), &s3c_device_usb_hsudc);
  1247. }
  1248. #endif /* CONFIG_PLAT_S3C24XX */
  1249. /* WDT */
  1250. #ifdef CONFIG_S3C_DEV_WDT
  1251. static struct resource s3c_wdt_resource[] = {
  1252. [0] = DEFINE_RES_MEM(S3C_PA_WDT, SZ_1K),
  1253. [1] = DEFINE_RES_IRQ(IRQ_WDT),
  1254. };
  1255. struct platform_device s3c_device_wdt = {
  1256. .name = "s3c2410-wdt",
  1257. .id = -1,
  1258. .num_resources = ARRAY_SIZE(s3c_wdt_resource),
  1259. .resource = s3c_wdt_resource,
  1260. };
  1261. #endif /* CONFIG_S3C_DEV_WDT */
  1262. #ifdef CONFIG_S3C64XX_DEV_SPI0
  1263. static struct resource s3c64xx_spi0_resource[] = {
  1264. [0] = DEFINE_RES_MEM(S3C_PA_SPI0, SZ_256),
  1265. [1] = DEFINE_RES_DMA(DMACH_SPI0_TX),
  1266. [2] = DEFINE_RES_DMA(DMACH_SPI0_RX),
  1267. [3] = DEFINE_RES_IRQ(IRQ_SPI0),
  1268. };
  1269. struct platform_device s3c64xx_device_spi0 = {
  1270. .name = "s3c6410-spi",
  1271. .id = 0,
  1272. .num_resources = ARRAY_SIZE(s3c64xx_spi0_resource),
  1273. .resource = s3c64xx_spi0_resource,
  1274. .dev = {
  1275. .dma_mask = &samsung_device_dma_mask,
  1276. .coherent_dma_mask = DMA_BIT_MASK(32),
  1277. },
  1278. };
  1279. void __init s3c64xx_spi0_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
  1280. int num_cs)
  1281. {
  1282. struct s3c64xx_spi_info pd;
  1283. /* Reject invalid configuration */
  1284. if (!num_cs || src_clk_nr < 0) {
  1285. pr_err("%s: Invalid SPI configuration\n", __func__);
  1286. return;
  1287. }
  1288. pd.num_cs = num_cs;
  1289. pd.src_clk_nr = src_clk_nr;
  1290. pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi0_cfg_gpio;
  1291. s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi0);
  1292. }
  1293. #endif /* CONFIG_S3C64XX_DEV_SPI0 */
  1294. #ifdef CONFIG_S3C64XX_DEV_SPI1
  1295. static struct resource s3c64xx_spi1_resource[] = {
  1296. [0] = DEFINE_RES_MEM(S3C_PA_SPI1, SZ_256),
  1297. [1] = DEFINE_RES_DMA(DMACH_SPI1_TX),
  1298. [2] = DEFINE_RES_DMA(DMACH_SPI1_RX),
  1299. [3] = DEFINE_RES_IRQ(IRQ_SPI1),
  1300. };
  1301. struct platform_device s3c64xx_device_spi1 = {
  1302. .name = "s3c6410-spi",
  1303. .id = 1,
  1304. .num_resources = ARRAY_SIZE(s3c64xx_spi1_resource),
  1305. .resource = s3c64xx_spi1_resource,
  1306. .dev = {
  1307. .dma_mask = &samsung_device_dma_mask,
  1308. .coherent_dma_mask = DMA_BIT_MASK(32),
  1309. },
  1310. };
  1311. void __init s3c64xx_spi1_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
  1312. int num_cs)
  1313. {
  1314. /* Reject invalid configuration */
  1315. if (!num_cs || src_clk_nr < 0) {
  1316. pr_err("%s: Invalid SPI configuration\n", __func__);
  1317. return;
  1318. }
  1319. pd.num_cs = num_cs;
  1320. pd.src_clk_nr = src_clk_nr;
  1321. pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi1_cfg_gpio;
  1322. s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi1);
  1323. }
  1324. #endif /* CONFIG_S3C64XX_DEV_SPI1 */
  1325. #ifdef CONFIG_S3C64XX_DEV_SPI2
  1326. static struct resource s3c64xx_spi2_resource[] = {
  1327. [0] = DEFINE_RES_MEM(S3C_PA_SPI2, SZ_256),
  1328. [1] = DEFINE_RES_DMA(DMACH_SPI2_TX),
  1329. [2] = DEFINE_RES_DMA(DMACH_SPI2_RX),
  1330. [3] = DEFINE_RES_IRQ(IRQ_SPI2),
  1331. };
  1332. struct platform_device s3c64xx_device_spi2 = {
  1333. .name = "s3c6410-spi",
  1334. .id = 2,
  1335. .num_resources = ARRAY_SIZE(s3c64xx_spi2_resource),
  1336. .resource = s3c64xx_spi2_resource,
  1337. .dev = {
  1338. .dma_mask = &samsung_device_dma_mask,
  1339. .coherent_dma_mask = DMA_BIT_MASK(32),
  1340. },
  1341. };
  1342. void __init s3c64xx_spi2_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
  1343. int num_cs)
  1344. {
  1345. struct s3c64xx_spi_info pd;
  1346. /* Reject invalid configuration */
  1347. if (!num_cs || src_clk_nr < 0) {
  1348. pr_err("%s: Invalid SPI configuration\n", __func__);
  1349. return;
  1350. }
  1351. pd.num_cs = num_cs;
  1352. pd.src_clk_nr = src_clk_nr;
  1353. pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi2_cfg_gpio;
  1354. s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi2);
  1355. }
  1356. #endif /* CONFIG_S3C64XX_DEV_SPI2 */