gpio-bcm-kona.c 17 KB

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  1. /*
  2. * Copyright (C) 2012-2013 Broadcom Corporation
  3. *
  4. * This program is free software; you can redistribute it and/or
  5. * modify it under the terms of the GNU General Public License as
  6. * published by the Free Software Foundation version 2.
  7. *
  8. * This program is distributed "as is" WITHOUT ANY WARRANTY of any
  9. * kind, whether express or implied; without even the implied warranty
  10. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  11. * GNU General Public License for more details.
  12. */
  13. #include <linux/bitops.h>
  14. #include <linux/err.h>
  15. #include <linux/io.h>
  16. #include <linux/gpio.h>
  17. #include <linux/of_device.h>
  18. #include <linux/of_irq.h>
  19. #include <linux/module.h>
  20. #include <linux/irqdomain.h>
  21. #include <linux/irqchip/chained_irq.h>
  22. #define BCM_GPIO_PASSWD 0x00a5a501
  23. #define GPIO_PER_BANK 32
  24. #define GPIO_MAX_BANK_NUM 8
  25. #define GPIO_BANK(gpio) ((gpio) >> 5)
  26. #define GPIO_BIT(gpio) ((gpio) & (GPIO_PER_BANK - 1))
  27. #define GPIO_OUT_STATUS(bank) (0x00000000 + ((bank) << 2))
  28. #define GPIO_IN_STATUS(bank) (0x00000020 + ((bank) << 2))
  29. #define GPIO_OUT_SET(bank) (0x00000040 + ((bank) << 2))
  30. #define GPIO_OUT_CLEAR(bank) (0x00000060 + ((bank) << 2))
  31. #define GPIO_INT_STATUS(bank) (0x00000080 + ((bank) << 2))
  32. #define GPIO_INT_MASK(bank) (0x000000a0 + ((bank) << 2))
  33. #define GPIO_INT_MSKCLR(bank) (0x000000c0 + ((bank) << 2))
  34. #define GPIO_CONTROL(bank) (0x00000100 + ((bank) << 2))
  35. #define GPIO_PWD_STATUS(bank) (0x00000500 + ((bank) << 2))
  36. #define GPIO_GPPWR_OFFSET 0x00000520
  37. #define GPIO_GPCTR0_DBR_SHIFT 5
  38. #define GPIO_GPCTR0_DBR_MASK 0x000001e0
  39. #define GPIO_GPCTR0_ITR_SHIFT 3
  40. #define GPIO_GPCTR0_ITR_MASK 0x00000018
  41. #define GPIO_GPCTR0_ITR_CMD_RISING_EDGE 0x00000001
  42. #define GPIO_GPCTR0_ITR_CMD_FALLING_EDGE 0x00000002
  43. #define GPIO_GPCTR0_ITR_CMD_BOTH_EDGE 0x00000003
  44. #define GPIO_GPCTR0_IOTR_MASK 0x00000001
  45. #define GPIO_GPCTR0_IOTR_CMD_0UTPUT 0x00000000
  46. #define GPIO_GPCTR0_IOTR_CMD_INPUT 0x00000001
  47. #define GPIO_GPCTR0_DB_ENABLE_MASK 0x00000100
  48. #define LOCK_CODE 0xffffffff
  49. #define UNLOCK_CODE 0x00000000
  50. struct bcm_kona_gpio {
  51. void __iomem *reg_base;
  52. int num_bank;
  53. spinlock_t lock;
  54. struct gpio_chip gpio_chip;
  55. struct irq_domain *irq_domain;
  56. struct bcm_kona_gpio_bank *banks;
  57. struct platform_device *pdev;
  58. };
  59. struct bcm_kona_gpio_bank {
  60. int id;
  61. int irq;
  62. /* Used in the interrupt handler */
  63. struct bcm_kona_gpio *kona_gpio;
  64. };
  65. static inline struct bcm_kona_gpio *to_kona_gpio(struct gpio_chip *chip)
  66. {
  67. return container_of(chip, struct bcm_kona_gpio, gpio_chip);
  68. }
  69. static void bcm_kona_gpio_set_lockcode_bank(void __iomem *reg_base,
  70. int bank_id, int lockcode)
  71. {
  72. writel(BCM_GPIO_PASSWD, reg_base + GPIO_GPPWR_OFFSET);
  73. writel(lockcode, reg_base + GPIO_PWD_STATUS(bank_id));
  74. }
  75. static inline void bcm_kona_gpio_lock_bank(void __iomem *reg_base, int bank_id)
  76. {
  77. bcm_kona_gpio_set_lockcode_bank(reg_base, bank_id, LOCK_CODE);
  78. }
  79. static inline void bcm_kona_gpio_unlock_bank(void __iomem *reg_base,
  80. int bank_id)
  81. {
  82. bcm_kona_gpio_set_lockcode_bank(reg_base, bank_id, UNLOCK_CODE);
  83. }
  84. static void bcm_kona_gpio_set(struct gpio_chip *chip, unsigned gpio, int value)
  85. {
  86. struct bcm_kona_gpio *kona_gpio;
  87. void __iomem *reg_base;
  88. int bank_id = GPIO_BANK(gpio);
  89. int bit = GPIO_BIT(gpio);
  90. u32 val, reg_offset;
  91. unsigned long flags;
  92. kona_gpio = to_kona_gpio(chip);
  93. reg_base = kona_gpio->reg_base;
  94. spin_lock_irqsave(&kona_gpio->lock, flags);
  95. bcm_kona_gpio_unlock_bank(reg_base, bank_id);
  96. /* determine the GPIO pin direction */
  97. val = readl(reg_base + GPIO_CONTROL(gpio));
  98. val &= GPIO_GPCTR0_IOTR_MASK;
  99. /* this function only applies to output pin */
  100. if (GPIO_GPCTR0_IOTR_CMD_INPUT == val)
  101. goto out;
  102. reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id);
  103. val = readl(reg_base + reg_offset);
  104. val |= BIT(bit);
  105. writel(val, reg_base + reg_offset);
  106. out:
  107. bcm_kona_gpio_lock_bank(reg_base, bank_id);
  108. spin_unlock_irqrestore(&kona_gpio->lock, flags);
  109. }
  110. static int bcm_kona_gpio_get(struct gpio_chip *chip, unsigned gpio)
  111. {
  112. struct bcm_kona_gpio *kona_gpio;
  113. void __iomem *reg_base;
  114. int bank_id = GPIO_BANK(gpio);
  115. int bit = GPIO_BIT(gpio);
  116. u32 val, reg_offset;
  117. unsigned long flags;
  118. kona_gpio = to_kona_gpio(chip);
  119. reg_base = kona_gpio->reg_base;
  120. spin_lock_irqsave(&kona_gpio->lock, flags);
  121. bcm_kona_gpio_unlock_bank(reg_base, bank_id);
  122. /* determine the GPIO pin direction */
  123. val = readl(reg_base + GPIO_CONTROL(gpio));
  124. val &= GPIO_GPCTR0_IOTR_MASK;
  125. /* read the GPIO bank status */
  126. reg_offset = (GPIO_GPCTR0_IOTR_CMD_INPUT == val) ?
  127. GPIO_IN_STATUS(bank_id) : GPIO_OUT_STATUS(bank_id);
  128. val = readl(reg_base + reg_offset);
  129. bcm_kona_gpio_lock_bank(reg_base, bank_id);
  130. spin_unlock_irqrestore(&kona_gpio->lock, flags);
  131. /* return the specified bit status */
  132. return !!(val & bit);
  133. }
  134. static int bcm_kona_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
  135. {
  136. struct bcm_kona_gpio *kona_gpio;
  137. void __iomem *reg_base;
  138. u32 val;
  139. unsigned long flags;
  140. int bank_id = GPIO_BANK(gpio);
  141. kona_gpio = to_kona_gpio(chip);
  142. reg_base = kona_gpio->reg_base;
  143. spin_lock_irqsave(&kona_gpio->lock, flags);
  144. bcm_kona_gpio_unlock_bank(reg_base, bank_id);
  145. val = readl(reg_base + GPIO_CONTROL(gpio));
  146. val &= ~GPIO_GPCTR0_IOTR_MASK;
  147. val |= GPIO_GPCTR0_IOTR_CMD_INPUT;
  148. writel(val, reg_base + GPIO_CONTROL(gpio));
  149. bcm_kona_gpio_lock_bank(reg_base, bank_id);
  150. spin_unlock_irqrestore(&kona_gpio->lock, flags);
  151. return 0;
  152. }
  153. static int bcm_kona_gpio_direction_output(struct gpio_chip *chip,
  154. unsigned gpio, int value)
  155. {
  156. struct bcm_kona_gpio *kona_gpio;
  157. void __iomem *reg_base;
  158. int bank_id = GPIO_BANK(gpio);
  159. int bit = GPIO_BIT(gpio);
  160. u32 val, reg_offset;
  161. unsigned long flags;
  162. kona_gpio = to_kona_gpio(chip);
  163. reg_base = kona_gpio->reg_base;
  164. spin_lock_irqsave(&kona_gpio->lock, flags);
  165. bcm_kona_gpio_unlock_bank(reg_base, bank_id);
  166. val = readl(reg_base + GPIO_CONTROL(gpio));
  167. val &= ~GPIO_GPCTR0_IOTR_MASK;
  168. val |= GPIO_GPCTR0_IOTR_CMD_0UTPUT;
  169. writel(val, reg_base + GPIO_CONTROL(gpio));
  170. reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id);
  171. val = readl(reg_base + reg_offset);
  172. val |= BIT(bit);
  173. writel(val, reg_base + reg_offset);
  174. bcm_kona_gpio_lock_bank(reg_base, bank_id);
  175. spin_unlock_irqrestore(&kona_gpio->lock, flags);
  176. return 0;
  177. }
  178. static int bcm_kona_gpio_to_irq(struct gpio_chip *chip, unsigned gpio)
  179. {
  180. struct bcm_kona_gpio *kona_gpio;
  181. kona_gpio = to_kona_gpio(chip);
  182. if (gpio >= kona_gpio->gpio_chip.ngpio)
  183. return -ENXIO;
  184. return irq_create_mapping(kona_gpio->irq_domain, gpio);
  185. }
  186. static int bcm_kona_gpio_set_debounce(struct gpio_chip *chip, unsigned gpio,
  187. unsigned debounce)
  188. {
  189. struct bcm_kona_gpio *kona_gpio;
  190. void __iomem *reg_base;
  191. u32 val, res;
  192. unsigned long flags;
  193. int bank_id = GPIO_BANK(gpio);
  194. kona_gpio = to_kona_gpio(chip);
  195. reg_base = kona_gpio->reg_base;
  196. /* debounce must be 1-128ms (or 0) */
  197. if ((debounce > 0 && debounce < 1000) || debounce > 128000) {
  198. dev_err(chip->dev, "Debounce value %u not in range\n",
  199. debounce);
  200. return -EINVAL;
  201. }
  202. /* calculate debounce bit value */
  203. if (debounce != 0) {
  204. /* Convert to ms */
  205. debounce /= 1000;
  206. /* find the MSB */
  207. res = fls(debounce) - 1;
  208. /* Check if MSB-1 is set (round up or down) */
  209. if (res > 0 && (debounce & BIT(res - 1)))
  210. res++;
  211. }
  212. /* spin lock for read-modify-write of the GPIO register */
  213. spin_lock_irqsave(&kona_gpio->lock, flags);
  214. bcm_kona_gpio_unlock_bank(reg_base, bank_id);
  215. val = readl(reg_base + GPIO_CONTROL(gpio));
  216. val &= ~GPIO_GPCTR0_DBR_MASK;
  217. if (debounce == 0) {
  218. /* disable debounce */
  219. val &= ~GPIO_GPCTR0_DB_ENABLE_MASK;
  220. } else {
  221. val |= GPIO_GPCTR0_DB_ENABLE_MASK |
  222. (res << GPIO_GPCTR0_DBR_SHIFT);
  223. }
  224. writel(val, reg_base + GPIO_CONTROL(gpio));
  225. bcm_kona_gpio_lock_bank(reg_base, bank_id);
  226. spin_unlock_irqrestore(&kona_gpio->lock, flags);
  227. return 0;
  228. }
  229. static struct gpio_chip template_chip = {
  230. .label = "bcm-kona-gpio",
  231. .direction_input = bcm_kona_gpio_direction_input,
  232. .get = bcm_kona_gpio_get,
  233. .direction_output = bcm_kona_gpio_direction_output,
  234. .set = bcm_kona_gpio_set,
  235. .set_debounce = bcm_kona_gpio_set_debounce,
  236. .to_irq = bcm_kona_gpio_to_irq,
  237. .base = 0,
  238. };
  239. static void bcm_kona_gpio_irq_ack(struct irq_data *d)
  240. {
  241. struct bcm_kona_gpio *kona_gpio;
  242. void __iomem *reg_base;
  243. int gpio = d->hwirq;
  244. int bank_id = GPIO_BANK(gpio);
  245. int bit = GPIO_BIT(gpio);
  246. u32 val;
  247. unsigned long flags;
  248. kona_gpio = irq_data_get_irq_chip_data(d);
  249. reg_base = kona_gpio->reg_base;
  250. spin_lock_irqsave(&kona_gpio->lock, flags);
  251. bcm_kona_gpio_unlock_bank(reg_base, bank_id);
  252. val = readl(reg_base + GPIO_INT_STATUS(bank_id));
  253. val |= BIT(bit);
  254. writel(val, reg_base + GPIO_INT_STATUS(bank_id));
  255. bcm_kona_gpio_lock_bank(reg_base, bank_id);
  256. spin_unlock_irqrestore(&kona_gpio->lock, flags);
  257. }
  258. static void bcm_kona_gpio_irq_mask(struct irq_data *d)
  259. {
  260. struct bcm_kona_gpio *kona_gpio;
  261. void __iomem *reg_base;
  262. int gpio = d->hwirq;
  263. int bank_id = GPIO_BANK(gpio);
  264. int bit = GPIO_BIT(gpio);
  265. u32 val;
  266. unsigned long flags;
  267. kona_gpio = irq_data_get_irq_chip_data(d);
  268. reg_base = kona_gpio->reg_base;
  269. spin_lock_irqsave(&kona_gpio->lock, flags);
  270. bcm_kona_gpio_unlock_bank(reg_base, bank_id);
  271. val = readl(reg_base + GPIO_INT_MASK(bank_id));
  272. val |= BIT(bit);
  273. writel(val, reg_base + GPIO_INT_MASK(bank_id));
  274. bcm_kona_gpio_lock_bank(reg_base, bank_id);
  275. spin_unlock_irqrestore(&kona_gpio->lock, flags);
  276. }
  277. static void bcm_kona_gpio_irq_unmask(struct irq_data *d)
  278. {
  279. struct bcm_kona_gpio *kona_gpio;
  280. void __iomem *reg_base;
  281. int gpio = d->hwirq;
  282. int bank_id = GPIO_BANK(gpio);
  283. int bit = GPIO_BIT(gpio);
  284. u32 val;
  285. unsigned long flags;
  286. kona_gpio = irq_data_get_irq_chip_data(d);
  287. reg_base = kona_gpio->reg_base;
  288. spin_lock_irqsave(&kona_gpio->lock, flags);
  289. bcm_kona_gpio_unlock_bank(reg_base, bank_id);
  290. val = readl(reg_base + GPIO_INT_MSKCLR(bank_id));
  291. val |= BIT(bit);
  292. writel(val, reg_base + GPIO_INT_MSKCLR(bank_id));
  293. bcm_kona_gpio_lock_bank(reg_base, bank_id);
  294. spin_unlock_irqrestore(&kona_gpio->lock, flags);
  295. }
  296. static int bcm_kona_gpio_irq_set_type(struct irq_data *d, unsigned int type)
  297. {
  298. struct bcm_kona_gpio *kona_gpio;
  299. void __iomem *reg_base;
  300. int gpio = d->hwirq;
  301. u32 lvl_type;
  302. u32 val;
  303. unsigned long flags;
  304. int bank_id = GPIO_BANK(gpio);
  305. kona_gpio = irq_data_get_irq_chip_data(d);
  306. reg_base = kona_gpio->reg_base;
  307. switch (type & IRQ_TYPE_SENSE_MASK) {
  308. case IRQ_TYPE_EDGE_RISING:
  309. lvl_type = GPIO_GPCTR0_ITR_CMD_RISING_EDGE;
  310. break;
  311. case IRQ_TYPE_EDGE_FALLING:
  312. lvl_type = GPIO_GPCTR0_ITR_CMD_FALLING_EDGE;
  313. break;
  314. case IRQ_TYPE_EDGE_BOTH:
  315. lvl_type = GPIO_GPCTR0_ITR_CMD_BOTH_EDGE;
  316. break;
  317. case IRQ_TYPE_LEVEL_HIGH:
  318. case IRQ_TYPE_LEVEL_LOW:
  319. /* BCM GPIO doesn't support level triggering */
  320. default:
  321. dev_err(kona_gpio->gpio_chip.dev,
  322. "Invalid BCM GPIO irq type 0x%x\n", type);
  323. return -EINVAL;
  324. }
  325. spin_lock_irqsave(&kona_gpio->lock, flags);
  326. bcm_kona_gpio_unlock_bank(reg_base, bank_id);
  327. val = readl(reg_base + GPIO_CONTROL(gpio));
  328. val &= ~GPIO_GPCTR0_ITR_MASK;
  329. val |= lvl_type << GPIO_GPCTR0_ITR_SHIFT;
  330. writel(val, reg_base + GPIO_CONTROL(gpio));
  331. bcm_kona_gpio_lock_bank(reg_base, bank_id);
  332. spin_unlock_irqrestore(&kona_gpio->lock, flags);
  333. return 0;
  334. }
  335. static void bcm_kona_gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
  336. {
  337. void __iomem *reg_base;
  338. int bit, bank_id;
  339. unsigned long sta;
  340. struct bcm_kona_gpio_bank *bank = irq_get_handler_data(irq);
  341. struct irq_chip *chip = irq_desc_get_chip(desc);
  342. chained_irq_enter(chip, desc);
  343. /*
  344. * For bank interrupts, we can't use chip_data to store the kona_gpio
  345. * pointer, since GIC needs it for its own purposes. Therefore, we get
  346. * our pointer from the bank structure.
  347. */
  348. reg_base = bank->kona_gpio->reg_base;
  349. bank_id = bank->id;
  350. bcm_kona_gpio_unlock_bank(reg_base, bank_id);
  351. while ((sta = readl(reg_base + GPIO_INT_STATUS(bank_id)) &
  352. (~(readl(reg_base + GPIO_INT_MASK(bank_id)))))) {
  353. for_each_set_bit(bit, &sta, 32) {
  354. int gpio = GPIO_PER_BANK * bank_id + bit;
  355. int virq = irq_find_mapping(bank->kona_gpio->irq_domain,
  356. gpio);
  357. /*
  358. * Clear interrupt before handler is called so we don't
  359. * miss any interrupt occurred during executing them.
  360. */
  361. writel(readl(reg_base + GPIO_INT_STATUS(bank_id)) |
  362. BIT(bit), reg_base + GPIO_INT_STATUS(bank_id));
  363. /* Invoke interrupt handler */
  364. generic_handle_irq(virq);
  365. }
  366. }
  367. bcm_kona_gpio_lock_bank(reg_base, bank_id);
  368. chained_irq_exit(chip, desc);
  369. }
  370. static struct irq_chip bcm_gpio_irq_chip = {
  371. .name = "bcm-kona-gpio",
  372. .irq_ack = bcm_kona_gpio_irq_ack,
  373. .irq_mask = bcm_kona_gpio_irq_mask,
  374. .irq_unmask = bcm_kona_gpio_irq_unmask,
  375. .irq_set_type = bcm_kona_gpio_irq_set_type,
  376. };
  377. static struct __initconst of_device_id bcm_kona_gpio_of_match[] = {
  378. { .compatible = "brcm,kona-gpio" },
  379. {}
  380. };
  381. MODULE_DEVICE_TABLE(of, bcm_kona_gpio_of_match);
  382. /*
  383. * This lock class tells lockdep that GPIO irqs are in a different
  384. * category than their parents, so it won't report false recursion.
  385. */
  386. static struct lock_class_key gpio_lock_class;
  387. static int bcm_kona_gpio_irq_map(struct irq_domain *d, unsigned int irq,
  388. irq_hw_number_t hwirq)
  389. {
  390. int ret;
  391. ret = irq_set_chip_data(irq, d->host_data);
  392. if (ret < 0)
  393. return ret;
  394. irq_set_lockdep_class(irq, &gpio_lock_class);
  395. irq_set_chip_and_handler(irq, &bcm_gpio_irq_chip, handle_simple_irq);
  396. irq_set_nested_thread(irq, 1);
  397. #ifdef CONFIG_ARM
  398. set_irq_flags(irq, IRQF_VALID);
  399. #else
  400. irq_set_noprobe(irq);
  401. #endif
  402. return 0;
  403. }
  404. static void bcm_kona_gpio_irq_unmap(struct irq_domain *d, unsigned int virq)
  405. {
  406. irq_set_chip_and_handler(virq, NULL, NULL);
  407. irq_set_chip_data(virq, NULL);
  408. }
  409. static struct irq_domain_ops bcm_kona_irq_ops = {
  410. .map = bcm_kona_gpio_irq_map,
  411. .unmap = bcm_kona_gpio_irq_unmap,
  412. .xlate = irq_domain_xlate_twocell,
  413. };
  414. static void bcm_kona_gpio_reset(struct bcm_kona_gpio *kona_gpio)
  415. {
  416. void __iomem *reg_base;
  417. int i;
  418. reg_base = kona_gpio->reg_base;
  419. /* disable interrupts and clear status */
  420. for (i = 0; i < kona_gpio->num_bank; i++) {
  421. bcm_kona_gpio_unlock_bank(reg_base, i);
  422. writel(0xffffffff, reg_base + GPIO_INT_MASK(i));
  423. writel(0xffffffff, reg_base + GPIO_INT_STATUS(i));
  424. bcm_kona_gpio_lock_bank(reg_base, i);
  425. }
  426. }
  427. static int bcm_kona_gpio_probe(struct platform_device *pdev)
  428. {
  429. struct device *dev = &pdev->dev;
  430. const struct of_device_id *match;
  431. struct resource *res;
  432. struct bcm_kona_gpio_bank *bank;
  433. struct bcm_kona_gpio *kona_gpio;
  434. struct gpio_chip *chip;
  435. int ret;
  436. int i;
  437. match = of_match_device(bcm_kona_gpio_of_match, dev);
  438. if (!match) {
  439. dev_err(dev, "Failed to find gpio controller\n");
  440. return -ENODEV;
  441. }
  442. kona_gpio = devm_kzalloc(dev, sizeof(*kona_gpio), GFP_KERNEL);
  443. if (!kona_gpio)
  444. return -ENOMEM;
  445. kona_gpio->gpio_chip = template_chip;
  446. chip = &kona_gpio->gpio_chip;
  447. kona_gpio->num_bank = of_irq_count(dev->of_node);
  448. if (kona_gpio->num_bank == 0) {
  449. dev_err(dev, "Couldn't determine # GPIO banks\n");
  450. return -ENOENT;
  451. }
  452. if (kona_gpio->num_bank > GPIO_MAX_BANK_NUM) {
  453. dev_err(dev, "Too many GPIO banks configured (max=%d)\n",
  454. GPIO_MAX_BANK_NUM);
  455. return -ENXIO;
  456. }
  457. kona_gpio->banks = devm_kzalloc(dev,
  458. kona_gpio->num_bank *
  459. sizeof(*kona_gpio->banks), GFP_KERNEL);
  460. if (!kona_gpio->banks)
  461. return -ENOMEM;
  462. kona_gpio->pdev = pdev;
  463. platform_set_drvdata(pdev, kona_gpio);
  464. chip->of_node = dev->of_node;
  465. chip->ngpio = kona_gpio->num_bank * GPIO_PER_BANK;
  466. kona_gpio->irq_domain = irq_domain_add_linear(dev->of_node,
  467. chip->ngpio,
  468. &bcm_kona_irq_ops,
  469. kona_gpio);
  470. if (!kona_gpio->irq_domain) {
  471. dev_err(dev, "Couldn't allocate IRQ domain\n");
  472. return -ENXIO;
  473. }
  474. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  475. kona_gpio->reg_base = devm_ioremap_resource(dev, res);
  476. if (IS_ERR(kona_gpio->reg_base)) {
  477. ret = -ENXIO;
  478. goto err_irq_domain;
  479. }
  480. for (i = 0; i < kona_gpio->num_bank; i++) {
  481. bank = &kona_gpio->banks[i];
  482. bank->id = i;
  483. bank->irq = platform_get_irq(pdev, i);
  484. bank->kona_gpio = kona_gpio;
  485. if (bank->irq < 0) {
  486. dev_err(dev, "Couldn't get IRQ for bank %d", i);
  487. ret = -ENOENT;
  488. goto err_irq_domain;
  489. }
  490. }
  491. dev_info(&pdev->dev, "Setting up Kona GPIO at 0x%p (phys %#x)\n",
  492. kona_gpio->reg_base, res->start);
  493. bcm_kona_gpio_reset(kona_gpio);
  494. ret = gpiochip_add(chip);
  495. if (ret < 0) {
  496. dev_err(dev, "Couldn't add GPIO chip -- %d\n", ret);
  497. goto err_irq_domain;
  498. }
  499. for (i = 0; i < chip->ngpio; i++) {
  500. int irq = bcm_kona_gpio_to_irq(chip, i);
  501. irq_set_lockdep_class(irq, &gpio_lock_class);
  502. irq_set_chip_and_handler(irq, &bcm_gpio_irq_chip,
  503. handle_simple_irq);
  504. #ifdef CONFIG_ARM
  505. set_irq_flags(irq, IRQF_VALID);
  506. #else
  507. irq_set_noprobe(irq);
  508. #endif
  509. }
  510. for (i = 0; i < kona_gpio->num_bank; i++) {
  511. bank = &kona_gpio->banks[i];
  512. irq_set_chained_handler(bank->irq, bcm_kona_gpio_irq_handler);
  513. irq_set_handler_data(bank->irq, bank);
  514. }
  515. spin_lock_init(&kona_gpio->lock);
  516. return 0;
  517. err_irq_domain:
  518. irq_domain_remove(kona_gpio->irq_domain);
  519. return ret;
  520. }
  521. static struct platform_driver bcm_kona_gpio_driver = {
  522. .driver = {
  523. .name = "bcm-kona-gpio",
  524. .owner = THIS_MODULE,
  525. .of_match_table = bcm_kona_gpio_of_match,
  526. },
  527. .probe = bcm_kona_gpio_probe,
  528. };
  529. module_platform_driver(bcm_kona_gpio_driver);
  530. MODULE_AUTHOR("Broadcom");
  531. MODULE_DESCRIPTION("Broadcom Kona GPIO Driver");
  532. MODULE_LICENSE("GPL v2");