r100.c 90 KB

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  1. /*
  2. * Copyright 2008 Advanced Micro Devices, Inc.
  3. * Copyright 2008 Red Hat Inc.
  4. * Copyright 2009 Jerome Glisse.
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice shall be included in
  14. * all copies or substantial portions of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22. * OTHER DEALINGS IN THE SOFTWARE.
  23. *
  24. * Authors: Dave Airlie
  25. * Alex Deucher
  26. * Jerome Glisse
  27. */
  28. #include <linux/seq_file.h>
  29. #include "drmP.h"
  30. #include "drm.h"
  31. #include "radeon_drm.h"
  32. #include "radeon_reg.h"
  33. #include "radeon.h"
  34. #include "r100d.h"
  35. #include "rs100d.h"
  36. #include "rv200d.h"
  37. #include "rv250d.h"
  38. #include <linux/firmware.h>
  39. #include <linux/platform_device.h>
  40. #include "r100_reg_safe.h"
  41. #include "rn50_reg_safe.h"
  42. /* Firmware Names */
  43. #define FIRMWARE_R100 "radeon/R100_cp.bin"
  44. #define FIRMWARE_R200 "radeon/R200_cp.bin"
  45. #define FIRMWARE_R300 "radeon/R300_cp.bin"
  46. #define FIRMWARE_R420 "radeon/R420_cp.bin"
  47. #define FIRMWARE_RS690 "radeon/RS690_cp.bin"
  48. #define FIRMWARE_RS600 "radeon/RS600_cp.bin"
  49. #define FIRMWARE_R520 "radeon/R520_cp.bin"
  50. MODULE_FIRMWARE(FIRMWARE_R100);
  51. MODULE_FIRMWARE(FIRMWARE_R200);
  52. MODULE_FIRMWARE(FIRMWARE_R300);
  53. MODULE_FIRMWARE(FIRMWARE_R420);
  54. MODULE_FIRMWARE(FIRMWARE_RS690);
  55. MODULE_FIRMWARE(FIRMWARE_RS600);
  56. MODULE_FIRMWARE(FIRMWARE_R520);
  57. #include "r100_track.h"
  58. /* This files gather functions specifics to:
  59. * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
  60. */
  61. /*
  62. * PCI GART
  63. */
  64. void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
  65. {
  66. /* TODO: can we do somethings here ? */
  67. /* It seems hw only cache one entry so we should discard this
  68. * entry otherwise if first GPU GART read hit this entry it
  69. * could end up in wrong address. */
  70. }
  71. int r100_pci_gart_init(struct radeon_device *rdev)
  72. {
  73. int r;
  74. if (rdev->gart.table.ram.ptr) {
  75. WARN(1, "R100 PCI GART already initialized.\n");
  76. return 0;
  77. }
  78. /* Initialize common gart structure */
  79. r = radeon_gart_init(rdev);
  80. if (r)
  81. return r;
  82. rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
  83. rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
  84. rdev->asic->gart_set_page = &r100_pci_gart_set_page;
  85. return radeon_gart_table_ram_alloc(rdev);
  86. }
  87. int r100_pci_gart_enable(struct radeon_device *rdev)
  88. {
  89. uint32_t tmp;
  90. /* discard memory request outside of configured range */
  91. tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
  92. WREG32(RADEON_AIC_CNTL, tmp);
  93. /* set address range for PCI address translate */
  94. WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_location);
  95. tmp = rdev->mc.gtt_location + rdev->mc.gtt_size - 1;
  96. WREG32(RADEON_AIC_HI_ADDR, tmp);
  97. /* Enable bus mastering */
  98. tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
  99. WREG32(RADEON_BUS_CNTL, tmp);
  100. /* set PCI GART page-table base address */
  101. WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
  102. tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
  103. WREG32(RADEON_AIC_CNTL, tmp);
  104. r100_pci_gart_tlb_flush(rdev);
  105. rdev->gart.ready = true;
  106. return 0;
  107. }
  108. void r100_pci_gart_disable(struct radeon_device *rdev)
  109. {
  110. uint32_t tmp;
  111. /* discard memory request outside of configured range */
  112. tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
  113. WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
  114. WREG32(RADEON_AIC_LO_ADDR, 0);
  115. WREG32(RADEON_AIC_HI_ADDR, 0);
  116. }
  117. int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
  118. {
  119. if (i < 0 || i > rdev->gart.num_gpu_pages) {
  120. return -EINVAL;
  121. }
  122. rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr));
  123. return 0;
  124. }
  125. void r100_pci_gart_fini(struct radeon_device *rdev)
  126. {
  127. r100_pci_gart_disable(rdev);
  128. radeon_gart_table_ram_free(rdev);
  129. radeon_gart_fini(rdev);
  130. }
  131. int r100_irq_set(struct radeon_device *rdev)
  132. {
  133. uint32_t tmp = 0;
  134. if (rdev->irq.sw_int) {
  135. tmp |= RADEON_SW_INT_ENABLE;
  136. }
  137. if (rdev->irq.crtc_vblank_int[0]) {
  138. tmp |= RADEON_CRTC_VBLANK_MASK;
  139. }
  140. if (rdev->irq.crtc_vblank_int[1]) {
  141. tmp |= RADEON_CRTC2_VBLANK_MASK;
  142. }
  143. WREG32(RADEON_GEN_INT_CNTL, tmp);
  144. return 0;
  145. }
  146. void r100_irq_disable(struct radeon_device *rdev)
  147. {
  148. u32 tmp;
  149. WREG32(R_000040_GEN_INT_CNTL, 0);
  150. /* Wait and acknowledge irq */
  151. mdelay(1);
  152. tmp = RREG32(R_000044_GEN_INT_STATUS);
  153. WREG32(R_000044_GEN_INT_STATUS, tmp);
  154. }
  155. static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
  156. {
  157. uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
  158. uint32_t irq_mask = RADEON_SW_INT_TEST | RADEON_CRTC_VBLANK_STAT |
  159. RADEON_CRTC2_VBLANK_STAT;
  160. if (irqs) {
  161. WREG32(RADEON_GEN_INT_STATUS, irqs);
  162. }
  163. return irqs & irq_mask;
  164. }
  165. int r100_irq_process(struct radeon_device *rdev)
  166. {
  167. uint32_t status;
  168. status = r100_irq_ack(rdev);
  169. if (!status) {
  170. return IRQ_NONE;
  171. }
  172. if (rdev->shutdown) {
  173. return IRQ_NONE;
  174. }
  175. while (status) {
  176. /* SW interrupt */
  177. if (status & RADEON_SW_INT_TEST) {
  178. radeon_fence_process(rdev);
  179. }
  180. /* Vertical blank interrupts */
  181. if (status & RADEON_CRTC_VBLANK_STAT) {
  182. drm_handle_vblank(rdev->ddev, 0);
  183. }
  184. if (status & RADEON_CRTC2_VBLANK_STAT) {
  185. drm_handle_vblank(rdev->ddev, 1);
  186. }
  187. status = r100_irq_ack(rdev);
  188. }
  189. return IRQ_HANDLED;
  190. }
  191. u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
  192. {
  193. if (crtc == 0)
  194. return RREG32(RADEON_CRTC_CRNT_FRAME);
  195. else
  196. return RREG32(RADEON_CRTC2_CRNT_FRAME);
  197. }
  198. void r100_fence_ring_emit(struct radeon_device *rdev,
  199. struct radeon_fence *fence)
  200. {
  201. /* Who ever call radeon_fence_emit should call ring_lock and ask
  202. * for enough space (today caller are ib schedule and buffer move) */
  203. /* Wait until IDLE & CLEAN */
  204. radeon_ring_write(rdev, PACKET0(0x1720, 0));
  205. radeon_ring_write(rdev, (1 << 16) | (1 << 17));
  206. /* Emit fence sequence & fire IRQ */
  207. radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
  208. radeon_ring_write(rdev, fence->seq);
  209. radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
  210. radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
  211. }
  212. int r100_wb_init(struct radeon_device *rdev)
  213. {
  214. int r;
  215. if (rdev->wb.wb_obj == NULL) {
  216. r = radeon_object_create(rdev, NULL, 4096,
  217. true,
  218. RADEON_GEM_DOMAIN_GTT,
  219. false, &rdev->wb.wb_obj);
  220. if (r) {
  221. DRM_ERROR("radeon: failed to create WB buffer (%d).\n", r);
  222. return r;
  223. }
  224. r = radeon_object_pin(rdev->wb.wb_obj,
  225. RADEON_GEM_DOMAIN_GTT,
  226. &rdev->wb.gpu_addr);
  227. if (r) {
  228. DRM_ERROR("radeon: failed to pin WB buffer (%d).\n", r);
  229. return r;
  230. }
  231. r = radeon_object_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
  232. if (r) {
  233. DRM_ERROR("radeon: failed to map WB buffer (%d).\n", r);
  234. return r;
  235. }
  236. }
  237. WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr);
  238. WREG32(R_00070C_CP_RB_RPTR_ADDR,
  239. S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + 1024) >> 2));
  240. WREG32(R_000770_SCRATCH_UMSK, 0xff);
  241. return 0;
  242. }
  243. void r100_wb_disable(struct radeon_device *rdev)
  244. {
  245. WREG32(R_000770_SCRATCH_UMSK, 0);
  246. }
  247. void r100_wb_fini(struct radeon_device *rdev)
  248. {
  249. r100_wb_disable(rdev);
  250. if (rdev->wb.wb_obj) {
  251. radeon_object_kunmap(rdev->wb.wb_obj);
  252. radeon_object_unpin(rdev->wb.wb_obj);
  253. radeon_object_unref(&rdev->wb.wb_obj);
  254. rdev->wb.wb = NULL;
  255. rdev->wb.wb_obj = NULL;
  256. }
  257. }
  258. int r100_copy_blit(struct radeon_device *rdev,
  259. uint64_t src_offset,
  260. uint64_t dst_offset,
  261. unsigned num_pages,
  262. struct radeon_fence *fence)
  263. {
  264. uint32_t cur_pages;
  265. uint32_t stride_bytes = PAGE_SIZE;
  266. uint32_t pitch;
  267. uint32_t stride_pixels;
  268. unsigned ndw;
  269. int num_loops;
  270. int r = 0;
  271. /* radeon limited to 16k stride */
  272. stride_bytes &= 0x3fff;
  273. /* radeon pitch is /64 */
  274. pitch = stride_bytes / 64;
  275. stride_pixels = stride_bytes / 4;
  276. num_loops = DIV_ROUND_UP(num_pages, 8191);
  277. /* Ask for enough room for blit + flush + fence */
  278. ndw = 64 + (10 * num_loops);
  279. r = radeon_ring_lock(rdev, ndw);
  280. if (r) {
  281. DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
  282. return -EINVAL;
  283. }
  284. while (num_pages > 0) {
  285. cur_pages = num_pages;
  286. if (cur_pages > 8191) {
  287. cur_pages = 8191;
  288. }
  289. num_pages -= cur_pages;
  290. /* pages are in Y direction - height
  291. page width in X direction - width */
  292. radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8));
  293. radeon_ring_write(rdev,
  294. RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
  295. RADEON_GMC_DST_PITCH_OFFSET_CNTL |
  296. RADEON_GMC_SRC_CLIPPING |
  297. RADEON_GMC_DST_CLIPPING |
  298. RADEON_GMC_BRUSH_NONE |
  299. (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
  300. RADEON_GMC_SRC_DATATYPE_COLOR |
  301. RADEON_ROP3_S |
  302. RADEON_DP_SRC_SOURCE_MEMORY |
  303. RADEON_GMC_CLR_CMP_CNTL_DIS |
  304. RADEON_GMC_WR_MSK_DIS);
  305. radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10));
  306. radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10));
  307. radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
  308. radeon_ring_write(rdev, 0);
  309. radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
  310. radeon_ring_write(rdev, num_pages);
  311. radeon_ring_write(rdev, num_pages);
  312. radeon_ring_write(rdev, cur_pages | (stride_pixels << 16));
  313. }
  314. radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
  315. radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
  316. radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
  317. radeon_ring_write(rdev,
  318. RADEON_WAIT_2D_IDLECLEAN |
  319. RADEON_WAIT_HOST_IDLECLEAN |
  320. RADEON_WAIT_DMA_GUI_IDLE);
  321. if (fence) {
  322. r = radeon_fence_emit(rdev, fence);
  323. }
  324. radeon_ring_unlock_commit(rdev);
  325. return r;
  326. }
  327. static int r100_cp_wait_for_idle(struct radeon_device *rdev)
  328. {
  329. unsigned i;
  330. u32 tmp;
  331. for (i = 0; i < rdev->usec_timeout; i++) {
  332. tmp = RREG32(R_000E40_RBBM_STATUS);
  333. if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
  334. return 0;
  335. }
  336. udelay(1);
  337. }
  338. return -1;
  339. }
  340. void r100_ring_start(struct radeon_device *rdev)
  341. {
  342. int r;
  343. r = radeon_ring_lock(rdev, 2);
  344. if (r) {
  345. return;
  346. }
  347. radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
  348. radeon_ring_write(rdev,
  349. RADEON_ISYNC_ANY2D_IDLE3D |
  350. RADEON_ISYNC_ANY3D_IDLE2D |
  351. RADEON_ISYNC_WAIT_IDLEGUI |
  352. RADEON_ISYNC_CPSCRATCH_IDLEGUI);
  353. radeon_ring_unlock_commit(rdev);
  354. }
  355. /* Load the microcode for the CP */
  356. static int r100_cp_init_microcode(struct radeon_device *rdev)
  357. {
  358. struct platform_device *pdev;
  359. const char *fw_name = NULL;
  360. int err;
  361. DRM_DEBUG("\n");
  362. pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
  363. err = IS_ERR(pdev);
  364. if (err) {
  365. printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
  366. return -EINVAL;
  367. }
  368. if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
  369. (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
  370. (rdev->family == CHIP_RS200)) {
  371. DRM_INFO("Loading R100 Microcode\n");
  372. fw_name = FIRMWARE_R100;
  373. } else if ((rdev->family == CHIP_R200) ||
  374. (rdev->family == CHIP_RV250) ||
  375. (rdev->family == CHIP_RV280) ||
  376. (rdev->family == CHIP_RS300)) {
  377. DRM_INFO("Loading R200 Microcode\n");
  378. fw_name = FIRMWARE_R200;
  379. } else if ((rdev->family == CHIP_R300) ||
  380. (rdev->family == CHIP_R350) ||
  381. (rdev->family == CHIP_RV350) ||
  382. (rdev->family == CHIP_RV380) ||
  383. (rdev->family == CHIP_RS400) ||
  384. (rdev->family == CHIP_RS480)) {
  385. DRM_INFO("Loading R300 Microcode\n");
  386. fw_name = FIRMWARE_R300;
  387. } else if ((rdev->family == CHIP_R420) ||
  388. (rdev->family == CHIP_R423) ||
  389. (rdev->family == CHIP_RV410)) {
  390. DRM_INFO("Loading R400 Microcode\n");
  391. fw_name = FIRMWARE_R420;
  392. } else if ((rdev->family == CHIP_RS690) ||
  393. (rdev->family == CHIP_RS740)) {
  394. DRM_INFO("Loading RS690/RS740 Microcode\n");
  395. fw_name = FIRMWARE_RS690;
  396. } else if (rdev->family == CHIP_RS600) {
  397. DRM_INFO("Loading RS600 Microcode\n");
  398. fw_name = FIRMWARE_RS600;
  399. } else if ((rdev->family == CHIP_RV515) ||
  400. (rdev->family == CHIP_R520) ||
  401. (rdev->family == CHIP_RV530) ||
  402. (rdev->family == CHIP_R580) ||
  403. (rdev->family == CHIP_RV560) ||
  404. (rdev->family == CHIP_RV570)) {
  405. DRM_INFO("Loading R500 Microcode\n");
  406. fw_name = FIRMWARE_R520;
  407. }
  408. err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
  409. platform_device_unregister(pdev);
  410. if (err) {
  411. printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
  412. fw_name);
  413. } else if (rdev->me_fw->size % 8) {
  414. printk(KERN_ERR
  415. "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
  416. rdev->me_fw->size, fw_name);
  417. err = -EINVAL;
  418. release_firmware(rdev->me_fw);
  419. rdev->me_fw = NULL;
  420. }
  421. return err;
  422. }
  423. static void r100_cp_load_microcode(struct radeon_device *rdev)
  424. {
  425. const __be32 *fw_data;
  426. int i, size;
  427. if (r100_gui_wait_for_idle(rdev)) {
  428. printk(KERN_WARNING "Failed to wait GUI idle while "
  429. "programming pipes. Bad things might happen.\n");
  430. }
  431. if (rdev->me_fw) {
  432. size = rdev->me_fw->size / 4;
  433. fw_data = (const __be32 *)&rdev->me_fw->data[0];
  434. WREG32(RADEON_CP_ME_RAM_ADDR, 0);
  435. for (i = 0; i < size; i += 2) {
  436. WREG32(RADEON_CP_ME_RAM_DATAH,
  437. be32_to_cpup(&fw_data[i]));
  438. WREG32(RADEON_CP_ME_RAM_DATAL,
  439. be32_to_cpup(&fw_data[i + 1]));
  440. }
  441. }
  442. }
  443. int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
  444. {
  445. unsigned rb_bufsz;
  446. unsigned rb_blksz;
  447. unsigned max_fetch;
  448. unsigned pre_write_timer;
  449. unsigned pre_write_limit;
  450. unsigned indirect2_start;
  451. unsigned indirect1_start;
  452. uint32_t tmp;
  453. int r;
  454. if (r100_debugfs_cp_init(rdev)) {
  455. DRM_ERROR("Failed to register debugfs file for CP !\n");
  456. }
  457. /* Reset CP */
  458. tmp = RREG32(RADEON_CP_CSQ_STAT);
  459. if ((tmp & (1 << 31))) {
  460. DRM_INFO("radeon: cp busy (0x%08X) resetting\n", tmp);
  461. WREG32(RADEON_CP_CSQ_MODE, 0);
  462. WREG32(RADEON_CP_CSQ_CNTL, 0);
  463. WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
  464. tmp = RREG32(RADEON_RBBM_SOFT_RESET);
  465. mdelay(2);
  466. WREG32(RADEON_RBBM_SOFT_RESET, 0);
  467. tmp = RREG32(RADEON_RBBM_SOFT_RESET);
  468. mdelay(2);
  469. tmp = RREG32(RADEON_CP_CSQ_STAT);
  470. if ((tmp & (1 << 31))) {
  471. DRM_INFO("radeon: cp reset failed (0x%08X)\n", tmp);
  472. }
  473. } else {
  474. DRM_INFO("radeon: cp idle (0x%08X)\n", tmp);
  475. }
  476. if (!rdev->me_fw) {
  477. r = r100_cp_init_microcode(rdev);
  478. if (r) {
  479. DRM_ERROR("Failed to load firmware!\n");
  480. return r;
  481. }
  482. }
  483. /* Align ring size */
  484. rb_bufsz = drm_order(ring_size / 8);
  485. ring_size = (1 << (rb_bufsz + 1)) * 4;
  486. r100_cp_load_microcode(rdev);
  487. r = radeon_ring_init(rdev, ring_size);
  488. if (r) {
  489. return r;
  490. }
  491. /* Each time the cp read 1024 bytes (16 dword/quadword) update
  492. * the rptr copy in system ram */
  493. rb_blksz = 9;
  494. /* cp will read 128bytes at a time (4 dwords) */
  495. max_fetch = 1;
  496. rdev->cp.align_mask = 16 - 1;
  497. /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
  498. pre_write_timer = 64;
  499. /* Force CP_RB_WPTR write if written more than one time before the
  500. * delay expire
  501. */
  502. pre_write_limit = 0;
  503. /* Setup the cp cache like this (cache size is 96 dwords) :
  504. * RING 0 to 15
  505. * INDIRECT1 16 to 79
  506. * INDIRECT2 80 to 95
  507. * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
  508. * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
  509. * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
  510. * Idea being that most of the gpu cmd will be through indirect1 buffer
  511. * so it gets the bigger cache.
  512. */
  513. indirect2_start = 80;
  514. indirect1_start = 16;
  515. /* cp setup */
  516. WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
  517. WREG32(RADEON_CP_RB_CNTL,
  518. #ifdef __BIG_ENDIAN
  519. RADEON_BUF_SWAP_32BIT |
  520. #endif
  521. REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
  522. REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
  523. REG_SET(RADEON_MAX_FETCH, max_fetch) |
  524. RADEON_RB_NO_UPDATE);
  525. /* Set ring address */
  526. DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
  527. WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
  528. /* Force read & write ptr to 0 */
  529. tmp = RREG32(RADEON_CP_RB_CNTL);
  530. WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
  531. WREG32(RADEON_CP_RB_RPTR_WR, 0);
  532. WREG32(RADEON_CP_RB_WPTR, 0);
  533. WREG32(RADEON_CP_RB_CNTL, tmp);
  534. udelay(10);
  535. rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
  536. rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR);
  537. /* Set cp mode to bus mastering & enable cp*/
  538. WREG32(RADEON_CP_CSQ_MODE,
  539. REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
  540. REG_SET(RADEON_INDIRECT1_START, indirect1_start));
  541. WREG32(0x718, 0);
  542. WREG32(0x744, 0x00004D4D);
  543. WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
  544. radeon_ring_start(rdev);
  545. r = radeon_ring_test(rdev);
  546. if (r) {
  547. DRM_ERROR("radeon: cp isn't working (%d).\n", r);
  548. return r;
  549. }
  550. rdev->cp.ready = true;
  551. return 0;
  552. }
  553. void r100_cp_fini(struct radeon_device *rdev)
  554. {
  555. if (r100_cp_wait_for_idle(rdev)) {
  556. DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
  557. }
  558. /* Disable ring */
  559. r100_cp_disable(rdev);
  560. radeon_ring_fini(rdev);
  561. DRM_INFO("radeon: cp finalized\n");
  562. }
  563. void r100_cp_disable(struct radeon_device *rdev)
  564. {
  565. /* Disable ring */
  566. rdev->cp.ready = false;
  567. WREG32(RADEON_CP_CSQ_MODE, 0);
  568. WREG32(RADEON_CP_CSQ_CNTL, 0);
  569. if (r100_gui_wait_for_idle(rdev)) {
  570. printk(KERN_WARNING "Failed to wait GUI idle while "
  571. "programming pipes. Bad things might happen.\n");
  572. }
  573. }
  574. int r100_cp_reset(struct radeon_device *rdev)
  575. {
  576. uint32_t tmp;
  577. bool reinit_cp;
  578. int i;
  579. reinit_cp = rdev->cp.ready;
  580. rdev->cp.ready = false;
  581. WREG32(RADEON_CP_CSQ_MODE, 0);
  582. WREG32(RADEON_CP_CSQ_CNTL, 0);
  583. WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
  584. (void)RREG32(RADEON_RBBM_SOFT_RESET);
  585. udelay(200);
  586. WREG32(RADEON_RBBM_SOFT_RESET, 0);
  587. /* Wait to prevent race in RBBM_STATUS */
  588. mdelay(1);
  589. for (i = 0; i < rdev->usec_timeout; i++) {
  590. tmp = RREG32(RADEON_RBBM_STATUS);
  591. if (!(tmp & (1 << 16))) {
  592. DRM_INFO("CP reset succeed (RBBM_STATUS=0x%08X)\n",
  593. tmp);
  594. if (reinit_cp) {
  595. return r100_cp_init(rdev, rdev->cp.ring_size);
  596. }
  597. return 0;
  598. }
  599. DRM_UDELAY(1);
  600. }
  601. tmp = RREG32(RADEON_RBBM_STATUS);
  602. DRM_ERROR("Failed to reset CP (RBBM_STATUS=0x%08X)!\n", tmp);
  603. return -1;
  604. }
  605. void r100_cp_commit(struct radeon_device *rdev)
  606. {
  607. WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
  608. (void)RREG32(RADEON_CP_RB_WPTR);
  609. }
  610. /*
  611. * CS functions
  612. */
  613. int r100_cs_parse_packet0(struct radeon_cs_parser *p,
  614. struct radeon_cs_packet *pkt,
  615. const unsigned *auth, unsigned n,
  616. radeon_packet0_check_t check)
  617. {
  618. unsigned reg;
  619. unsigned i, j, m;
  620. unsigned idx;
  621. int r;
  622. idx = pkt->idx + 1;
  623. reg = pkt->reg;
  624. /* Check that register fall into register range
  625. * determined by the number of entry (n) in the
  626. * safe register bitmap.
  627. */
  628. if (pkt->one_reg_wr) {
  629. if ((reg >> 7) > n) {
  630. return -EINVAL;
  631. }
  632. } else {
  633. if (((reg + (pkt->count << 2)) >> 7) > n) {
  634. return -EINVAL;
  635. }
  636. }
  637. for (i = 0; i <= pkt->count; i++, idx++) {
  638. j = (reg >> 7);
  639. m = 1 << ((reg >> 2) & 31);
  640. if (auth[j] & m) {
  641. r = check(p, pkt, idx, reg);
  642. if (r) {
  643. return r;
  644. }
  645. }
  646. if (pkt->one_reg_wr) {
  647. if (!(auth[j] & m)) {
  648. break;
  649. }
  650. } else {
  651. reg += 4;
  652. }
  653. }
  654. return 0;
  655. }
  656. void r100_cs_dump_packet(struct radeon_cs_parser *p,
  657. struct radeon_cs_packet *pkt)
  658. {
  659. volatile uint32_t *ib;
  660. unsigned i;
  661. unsigned idx;
  662. ib = p->ib->ptr;
  663. idx = pkt->idx;
  664. for (i = 0; i <= (pkt->count + 1); i++, idx++) {
  665. DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
  666. }
  667. }
  668. /**
  669. * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
  670. * @parser: parser structure holding parsing context.
  671. * @pkt: where to store packet informations
  672. *
  673. * Assume that chunk_ib_index is properly set. Will return -EINVAL
  674. * if packet is bigger than remaining ib size. or if packets is unknown.
  675. **/
  676. int r100_cs_packet_parse(struct radeon_cs_parser *p,
  677. struct radeon_cs_packet *pkt,
  678. unsigned idx)
  679. {
  680. struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
  681. uint32_t header;
  682. if (idx >= ib_chunk->length_dw) {
  683. DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
  684. idx, ib_chunk->length_dw);
  685. return -EINVAL;
  686. }
  687. header = radeon_get_ib_value(p, idx);
  688. pkt->idx = idx;
  689. pkt->type = CP_PACKET_GET_TYPE(header);
  690. pkt->count = CP_PACKET_GET_COUNT(header);
  691. switch (pkt->type) {
  692. case PACKET_TYPE0:
  693. pkt->reg = CP_PACKET0_GET_REG(header);
  694. pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
  695. break;
  696. case PACKET_TYPE3:
  697. pkt->opcode = CP_PACKET3_GET_OPCODE(header);
  698. break;
  699. case PACKET_TYPE2:
  700. pkt->count = -1;
  701. break;
  702. default:
  703. DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
  704. return -EINVAL;
  705. }
  706. if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
  707. DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
  708. pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
  709. return -EINVAL;
  710. }
  711. return 0;
  712. }
  713. /**
  714. * r100_cs_packet_next_vline() - parse userspace VLINE packet
  715. * @parser: parser structure holding parsing context.
  716. *
  717. * Userspace sends a special sequence for VLINE waits.
  718. * PACKET0 - VLINE_START_END + value
  719. * PACKET0 - WAIT_UNTIL +_value
  720. * RELOC (P3) - crtc_id in reloc.
  721. *
  722. * This function parses this and relocates the VLINE START END
  723. * and WAIT UNTIL packets to the correct crtc.
  724. * It also detects a switched off crtc and nulls out the
  725. * wait in that case.
  726. */
  727. int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
  728. {
  729. struct drm_mode_object *obj;
  730. struct drm_crtc *crtc;
  731. struct radeon_crtc *radeon_crtc;
  732. struct radeon_cs_packet p3reloc, waitreloc;
  733. int crtc_id;
  734. int r;
  735. uint32_t header, h_idx, reg;
  736. volatile uint32_t *ib;
  737. ib = p->ib->ptr;
  738. /* parse the wait until */
  739. r = r100_cs_packet_parse(p, &waitreloc, p->idx);
  740. if (r)
  741. return r;
  742. /* check its a wait until and only 1 count */
  743. if (waitreloc.reg != RADEON_WAIT_UNTIL ||
  744. waitreloc.count != 0) {
  745. DRM_ERROR("vline wait had illegal wait until segment\n");
  746. r = -EINVAL;
  747. return r;
  748. }
  749. if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
  750. DRM_ERROR("vline wait had illegal wait until\n");
  751. r = -EINVAL;
  752. return r;
  753. }
  754. /* jump over the NOP */
  755. r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
  756. if (r)
  757. return r;
  758. h_idx = p->idx - 2;
  759. p->idx += waitreloc.count + 2;
  760. p->idx += p3reloc.count + 2;
  761. header = radeon_get_ib_value(p, h_idx);
  762. crtc_id = radeon_get_ib_value(p, h_idx + 5);
  763. reg = CP_PACKET0_GET_REG(header);
  764. mutex_lock(&p->rdev->ddev->mode_config.mutex);
  765. obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
  766. if (!obj) {
  767. DRM_ERROR("cannot find crtc %d\n", crtc_id);
  768. r = -EINVAL;
  769. goto out;
  770. }
  771. crtc = obj_to_crtc(obj);
  772. radeon_crtc = to_radeon_crtc(crtc);
  773. crtc_id = radeon_crtc->crtc_id;
  774. if (!crtc->enabled) {
  775. /* if the CRTC isn't enabled - we need to nop out the wait until */
  776. ib[h_idx + 2] = PACKET2(0);
  777. ib[h_idx + 3] = PACKET2(0);
  778. } else if (crtc_id == 1) {
  779. switch (reg) {
  780. case AVIVO_D1MODE_VLINE_START_END:
  781. header &= ~R300_CP_PACKET0_REG_MASK;
  782. header |= AVIVO_D2MODE_VLINE_START_END >> 2;
  783. break;
  784. case RADEON_CRTC_GUI_TRIG_VLINE:
  785. header &= ~R300_CP_PACKET0_REG_MASK;
  786. header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
  787. break;
  788. default:
  789. DRM_ERROR("unknown crtc reloc\n");
  790. r = -EINVAL;
  791. goto out;
  792. }
  793. ib[h_idx] = header;
  794. ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
  795. }
  796. out:
  797. mutex_unlock(&p->rdev->ddev->mode_config.mutex);
  798. return r;
  799. }
  800. /**
  801. * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
  802. * @parser: parser structure holding parsing context.
  803. * @data: pointer to relocation data
  804. * @offset_start: starting offset
  805. * @offset_mask: offset mask (to align start offset on)
  806. * @reloc: reloc informations
  807. *
  808. * Check next packet is relocation packet3, do bo validation and compute
  809. * GPU offset using the provided start.
  810. **/
  811. int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
  812. struct radeon_cs_reloc **cs_reloc)
  813. {
  814. struct radeon_cs_chunk *relocs_chunk;
  815. struct radeon_cs_packet p3reloc;
  816. unsigned idx;
  817. int r;
  818. if (p->chunk_relocs_idx == -1) {
  819. DRM_ERROR("No relocation chunk !\n");
  820. return -EINVAL;
  821. }
  822. *cs_reloc = NULL;
  823. relocs_chunk = &p->chunks[p->chunk_relocs_idx];
  824. r = r100_cs_packet_parse(p, &p3reloc, p->idx);
  825. if (r) {
  826. return r;
  827. }
  828. p->idx += p3reloc.count + 2;
  829. if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
  830. DRM_ERROR("No packet3 for relocation for packet at %d.\n",
  831. p3reloc.idx);
  832. r100_cs_dump_packet(p, &p3reloc);
  833. return -EINVAL;
  834. }
  835. idx = radeon_get_ib_value(p, p3reloc.idx + 1);
  836. if (idx >= relocs_chunk->length_dw) {
  837. DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
  838. idx, relocs_chunk->length_dw);
  839. r100_cs_dump_packet(p, &p3reloc);
  840. return -EINVAL;
  841. }
  842. /* FIXME: we assume reloc size is 4 dwords */
  843. *cs_reloc = p->relocs_ptr[(idx / 4)];
  844. return 0;
  845. }
  846. static int r100_get_vtx_size(uint32_t vtx_fmt)
  847. {
  848. int vtx_size;
  849. vtx_size = 2;
  850. /* ordered according to bits in spec */
  851. if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
  852. vtx_size++;
  853. if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
  854. vtx_size += 3;
  855. if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
  856. vtx_size++;
  857. if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
  858. vtx_size++;
  859. if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
  860. vtx_size += 3;
  861. if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
  862. vtx_size++;
  863. if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
  864. vtx_size++;
  865. if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
  866. vtx_size += 2;
  867. if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
  868. vtx_size += 2;
  869. if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
  870. vtx_size++;
  871. if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
  872. vtx_size += 2;
  873. if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
  874. vtx_size++;
  875. if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
  876. vtx_size += 2;
  877. if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
  878. vtx_size++;
  879. if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
  880. vtx_size++;
  881. /* blend weight */
  882. if (vtx_fmt & (0x7 << 15))
  883. vtx_size += (vtx_fmt >> 15) & 0x7;
  884. if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
  885. vtx_size += 3;
  886. if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
  887. vtx_size += 2;
  888. if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
  889. vtx_size++;
  890. if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
  891. vtx_size++;
  892. if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
  893. vtx_size++;
  894. if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
  895. vtx_size++;
  896. return vtx_size;
  897. }
  898. static int r100_packet0_check(struct radeon_cs_parser *p,
  899. struct radeon_cs_packet *pkt,
  900. unsigned idx, unsigned reg)
  901. {
  902. struct radeon_cs_reloc *reloc;
  903. struct r100_cs_track *track;
  904. volatile uint32_t *ib;
  905. uint32_t tmp;
  906. int r;
  907. int i, face;
  908. u32 tile_flags = 0;
  909. u32 idx_value;
  910. ib = p->ib->ptr;
  911. track = (struct r100_cs_track *)p->track;
  912. idx_value = radeon_get_ib_value(p, idx);
  913. switch (reg) {
  914. case RADEON_CRTC_GUI_TRIG_VLINE:
  915. r = r100_cs_packet_parse_vline(p);
  916. if (r) {
  917. DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
  918. idx, reg);
  919. r100_cs_dump_packet(p, pkt);
  920. return r;
  921. }
  922. break;
  923. /* FIXME: only allow PACKET3 blit? easier to check for out of
  924. * range access */
  925. case RADEON_DST_PITCH_OFFSET:
  926. case RADEON_SRC_PITCH_OFFSET:
  927. r = r100_reloc_pitch_offset(p, pkt, idx, reg);
  928. if (r)
  929. return r;
  930. break;
  931. case RADEON_RB3D_DEPTHOFFSET:
  932. r = r100_cs_packet_next_reloc(p, &reloc);
  933. if (r) {
  934. DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
  935. idx, reg);
  936. r100_cs_dump_packet(p, pkt);
  937. return r;
  938. }
  939. track->zb.robj = reloc->robj;
  940. track->zb.offset = idx_value;
  941. ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
  942. break;
  943. case RADEON_RB3D_COLOROFFSET:
  944. r = r100_cs_packet_next_reloc(p, &reloc);
  945. if (r) {
  946. DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
  947. idx, reg);
  948. r100_cs_dump_packet(p, pkt);
  949. return r;
  950. }
  951. track->cb[0].robj = reloc->robj;
  952. track->cb[0].offset = idx_value;
  953. ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
  954. break;
  955. case RADEON_PP_TXOFFSET_0:
  956. case RADEON_PP_TXOFFSET_1:
  957. case RADEON_PP_TXOFFSET_2:
  958. i = (reg - RADEON_PP_TXOFFSET_0) / 24;
  959. r = r100_cs_packet_next_reloc(p, &reloc);
  960. if (r) {
  961. DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
  962. idx, reg);
  963. r100_cs_dump_packet(p, pkt);
  964. return r;
  965. }
  966. ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
  967. track->textures[i].robj = reloc->robj;
  968. break;
  969. case RADEON_PP_CUBIC_OFFSET_T0_0:
  970. case RADEON_PP_CUBIC_OFFSET_T0_1:
  971. case RADEON_PP_CUBIC_OFFSET_T0_2:
  972. case RADEON_PP_CUBIC_OFFSET_T0_3:
  973. case RADEON_PP_CUBIC_OFFSET_T0_4:
  974. i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
  975. r = r100_cs_packet_next_reloc(p, &reloc);
  976. if (r) {
  977. DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
  978. idx, reg);
  979. r100_cs_dump_packet(p, pkt);
  980. return r;
  981. }
  982. track->textures[0].cube_info[i].offset = idx_value;
  983. ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
  984. track->textures[0].cube_info[i].robj = reloc->robj;
  985. break;
  986. case RADEON_PP_CUBIC_OFFSET_T1_0:
  987. case RADEON_PP_CUBIC_OFFSET_T1_1:
  988. case RADEON_PP_CUBIC_OFFSET_T1_2:
  989. case RADEON_PP_CUBIC_OFFSET_T1_3:
  990. case RADEON_PP_CUBIC_OFFSET_T1_4:
  991. i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
  992. r = r100_cs_packet_next_reloc(p, &reloc);
  993. if (r) {
  994. DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
  995. idx, reg);
  996. r100_cs_dump_packet(p, pkt);
  997. return r;
  998. }
  999. track->textures[1].cube_info[i].offset = idx_value;
  1000. ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
  1001. track->textures[1].cube_info[i].robj = reloc->robj;
  1002. break;
  1003. case RADEON_PP_CUBIC_OFFSET_T2_0:
  1004. case RADEON_PP_CUBIC_OFFSET_T2_1:
  1005. case RADEON_PP_CUBIC_OFFSET_T2_2:
  1006. case RADEON_PP_CUBIC_OFFSET_T2_3:
  1007. case RADEON_PP_CUBIC_OFFSET_T2_4:
  1008. i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
  1009. r = r100_cs_packet_next_reloc(p, &reloc);
  1010. if (r) {
  1011. DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
  1012. idx, reg);
  1013. r100_cs_dump_packet(p, pkt);
  1014. return r;
  1015. }
  1016. track->textures[2].cube_info[i].offset = idx_value;
  1017. ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
  1018. track->textures[2].cube_info[i].robj = reloc->robj;
  1019. break;
  1020. case RADEON_RE_WIDTH_HEIGHT:
  1021. track->maxy = ((idx_value >> 16) & 0x7FF);
  1022. break;
  1023. case RADEON_RB3D_COLORPITCH:
  1024. r = r100_cs_packet_next_reloc(p, &reloc);
  1025. if (r) {
  1026. DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
  1027. idx, reg);
  1028. r100_cs_dump_packet(p, pkt);
  1029. return r;
  1030. }
  1031. if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
  1032. tile_flags |= RADEON_COLOR_TILE_ENABLE;
  1033. if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
  1034. tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
  1035. tmp = idx_value & ~(0x7 << 16);
  1036. tmp |= tile_flags;
  1037. ib[idx] = tmp;
  1038. track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
  1039. break;
  1040. case RADEON_RB3D_DEPTHPITCH:
  1041. track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
  1042. break;
  1043. case RADEON_RB3D_CNTL:
  1044. switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
  1045. case 7:
  1046. case 8:
  1047. case 9:
  1048. case 11:
  1049. case 12:
  1050. track->cb[0].cpp = 1;
  1051. break;
  1052. case 3:
  1053. case 4:
  1054. case 15:
  1055. track->cb[0].cpp = 2;
  1056. break;
  1057. case 6:
  1058. track->cb[0].cpp = 4;
  1059. break;
  1060. default:
  1061. DRM_ERROR("Invalid color buffer format (%d) !\n",
  1062. ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
  1063. return -EINVAL;
  1064. }
  1065. track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
  1066. break;
  1067. case RADEON_RB3D_ZSTENCILCNTL:
  1068. switch (idx_value & 0xf) {
  1069. case 0:
  1070. track->zb.cpp = 2;
  1071. break;
  1072. case 2:
  1073. case 3:
  1074. case 4:
  1075. case 5:
  1076. case 9:
  1077. case 11:
  1078. track->zb.cpp = 4;
  1079. break;
  1080. default:
  1081. break;
  1082. }
  1083. break;
  1084. case RADEON_RB3D_ZPASS_ADDR:
  1085. r = r100_cs_packet_next_reloc(p, &reloc);
  1086. if (r) {
  1087. DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
  1088. idx, reg);
  1089. r100_cs_dump_packet(p, pkt);
  1090. return r;
  1091. }
  1092. ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
  1093. break;
  1094. case RADEON_PP_CNTL:
  1095. {
  1096. uint32_t temp = idx_value >> 4;
  1097. for (i = 0; i < track->num_texture; i++)
  1098. track->textures[i].enabled = !!(temp & (1 << i));
  1099. }
  1100. break;
  1101. case RADEON_SE_VF_CNTL:
  1102. track->vap_vf_cntl = idx_value;
  1103. break;
  1104. case RADEON_SE_VTX_FMT:
  1105. track->vtx_size = r100_get_vtx_size(idx_value);
  1106. break;
  1107. case RADEON_PP_TEX_SIZE_0:
  1108. case RADEON_PP_TEX_SIZE_1:
  1109. case RADEON_PP_TEX_SIZE_2:
  1110. i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
  1111. track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
  1112. track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
  1113. break;
  1114. case RADEON_PP_TEX_PITCH_0:
  1115. case RADEON_PP_TEX_PITCH_1:
  1116. case RADEON_PP_TEX_PITCH_2:
  1117. i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
  1118. track->textures[i].pitch = idx_value + 32;
  1119. break;
  1120. case RADEON_PP_TXFILTER_0:
  1121. case RADEON_PP_TXFILTER_1:
  1122. case RADEON_PP_TXFILTER_2:
  1123. i = (reg - RADEON_PP_TXFILTER_0) / 24;
  1124. track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
  1125. >> RADEON_MAX_MIP_LEVEL_SHIFT);
  1126. tmp = (idx_value >> 23) & 0x7;
  1127. if (tmp == 2 || tmp == 6)
  1128. track->textures[i].roundup_w = false;
  1129. tmp = (idx_value >> 27) & 0x7;
  1130. if (tmp == 2 || tmp == 6)
  1131. track->textures[i].roundup_h = false;
  1132. break;
  1133. case RADEON_PP_TXFORMAT_0:
  1134. case RADEON_PP_TXFORMAT_1:
  1135. case RADEON_PP_TXFORMAT_2:
  1136. i = (reg - RADEON_PP_TXFORMAT_0) / 24;
  1137. if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
  1138. track->textures[i].use_pitch = 1;
  1139. } else {
  1140. track->textures[i].use_pitch = 0;
  1141. track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
  1142. track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
  1143. }
  1144. if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
  1145. track->textures[i].tex_coord_type = 2;
  1146. switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
  1147. case RADEON_TXFORMAT_I8:
  1148. case RADEON_TXFORMAT_RGB332:
  1149. case RADEON_TXFORMAT_Y8:
  1150. track->textures[i].cpp = 1;
  1151. break;
  1152. case RADEON_TXFORMAT_AI88:
  1153. case RADEON_TXFORMAT_ARGB1555:
  1154. case RADEON_TXFORMAT_RGB565:
  1155. case RADEON_TXFORMAT_ARGB4444:
  1156. case RADEON_TXFORMAT_VYUY422:
  1157. case RADEON_TXFORMAT_YVYU422:
  1158. case RADEON_TXFORMAT_DXT1:
  1159. case RADEON_TXFORMAT_SHADOW16:
  1160. case RADEON_TXFORMAT_LDUDV655:
  1161. case RADEON_TXFORMAT_DUDV88:
  1162. track->textures[i].cpp = 2;
  1163. break;
  1164. case RADEON_TXFORMAT_ARGB8888:
  1165. case RADEON_TXFORMAT_RGBA8888:
  1166. case RADEON_TXFORMAT_DXT23:
  1167. case RADEON_TXFORMAT_DXT45:
  1168. case RADEON_TXFORMAT_SHADOW32:
  1169. case RADEON_TXFORMAT_LDUDUV8888:
  1170. track->textures[i].cpp = 4;
  1171. break;
  1172. }
  1173. track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
  1174. track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
  1175. break;
  1176. case RADEON_PP_CUBIC_FACES_0:
  1177. case RADEON_PP_CUBIC_FACES_1:
  1178. case RADEON_PP_CUBIC_FACES_2:
  1179. tmp = idx_value;
  1180. i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
  1181. for (face = 0; face < 4; face++) {
  1182. track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
  1183. track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
  1184. }
  1185. break;
  1186. default:
  1187. printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
  1188. reg, idx);
  1189. return -EINVAL;
  1190. }
  1191. return 0;
  1192. }
  1193. int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
  1194. struct radeon_cs_packet *pkt,
  1195. struct radeon_object *robj)
  1196. {
  1197. unsigned idx;
  1198. u32 value;
  1199. idx = pkt->idx + 1;
  1200. value = radeon_get_ib_value(p, idx + 2);
  1201. if ((value + 1) > radeon_object_size(robj)) {
  1202. DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
  1203. "(need %u have %lu) !\n",
  1204. value + 1,
  1205. radeon_object_size(robj));
  1206. return -EINVAL;
  1207. }
  1208. return 0;
  1209. }
  1210. static int r100_packet3_check(struct radeon_cs_parser *p,
  1211. struct radeon_cs_packet *pkt)
  1212. {
  1213. struct radeon_cs_reloc *reloc;
  1214. struct r100_cs_track *track;
  1215. unsigned idx;
  1216. volatile uint32_t *ib;
  1217. int r;
  1218. ib = p->ib->ptr;
  1219. idx = pkt->idx + 1;
  1220. track = (struct r100_cs_track *)p->track;
  1221. switch (pkt->opcode) {
  1222. case PACKET3_3D_LOAD_VBPNTR:
  1223. r = r100_packet3_load_vbpntr(p, pkt, idx);
  1224. if (r)
  1225. return r;
  1226. break;
  1227. case PACKET3_INDX_BUFFER:
  1228. r = r100_cs_packet_next_reloc(p, &reloc);
  1229. if (r) {
  1230. DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
  1231. r100_cs_dump_packet(p, pkt);
  1232. return r;
  1233. }
  1234. ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
  1235. r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
  1236. if (r) {
  1237. return r;
  1238. }
  1239. break;
  1240. case 0x23:
  1241. /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
  1242. r = r100_cs_packet_next_reloc(p, &reloc);
  1243. if (r) {
  1244. DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
  1245. r100_cs_dump_packet(p, pkt);
  1246. return r;
  1247. }
  1248. ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
  1249. track->num_arrays = 1;
  1250. track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
  1251. track->arrays[0].robj = reloc->robj;
  1252. track->arrays[0].esize = track->vtx_size;
  1253. track->max_indx = radeon_get_ib_value(p, idx+1);
  1254. track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
  1255. track->immd_dwords = pkt->count - 1;
  1256. r = r100_cs_track_check(p->rdev, track);
  1257. if (r)
  1258. return r;
  1259. break;
  1260. case PACKET3_3D_DRAW_IMMD:
  1261. if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
  1262. DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
  1263. return -EINVAL;
  1264. }
  1265. track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
  1266. track->immd_dwords = pkt->count - 1;
  1267. r = r100_cs_track_check(p->rdev, track);
  1268. if (r)
  1269. return r;
  1270. break;
  1271. /* triggers drawing using in-packet vertex data */
  1272. case PACKET3_3D_DRAW_IMMD_2:
  1273. if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
  1274. DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
  1275. return -EINVAL;
  1276. }
  1277. track->vap_vf_cntl = radeon_get_ib_value(p, idx);
  1278. track->immd_dwords = pkt->count;
  1279. r = r100_cs_track_check(p->rdev, track);
  1280. if (r)
  1281. return r;
  1282. break;
  1283. /* triggers drawing using in-packet vertex data */
  1284. case PACKET3_3D_DRAW_VBUF_2:
  1285. track->vap_vf_cntl = radeon_get_ib_value(p, idx);
  1286. r = r100_cs_track_check(p->rdev, track);
  1287. if (r)
  1288. return r;
  1289. break;
  1290. /* triggers drawing of vertex buffers setup elsewhere */
  1291. case PACKET3_3D_DRAW_INDX_2:
  1292. track->vap_vf_cntl = radeon_get_ib_value(p, idx);
  1293. r = r100_cs_track_check(p->rdev, track);
  1294. if (r)
  1295. return r;
  1296. break;
  1297. /* triggers drawing using indices to vertex buffer */
  1298. case PACKET3_3D_DRAW_VBUF:
  1299. track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
  1300. r = r100_cs_track_check(p->rdev, track);
  1301. if (r)
  1302. return r;
  1303. break;
  1304. /* triggers drawing of vertex buffers setup elsewhere */
  1305. case PACKET3_3D_DRAW_INDX:
  1306. track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
  1307. r = r100_cs_track_check(p->rdev, track);
  1308. if (r)
  1309. return r;
  1310. break;
  1311. /* triggers drawing using indices to vertex buffer */
  1312. case PACKET3_NOP:
  1313. break;
  1314. default:
  1315. DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
  1316. return -EINVAL;
  1317. }
  1318. return 0;
  1319. }
  1320. int r100_cs_parse(struct radeon_cs_parser *p)
  1321. {
  1322. struct radeon_cs_packet pkt;
  1323. struct r100_cs_track *track;
  1324. int r;
  1325. track = kzalloc(sizeof(*track), GFP_KERNEL);
  1326. r100_cs_track_clear(p->rdev, track);
  1327. p->track = track;
  1328. do {
  1329. r = r100_cs_packet_parse(p, &pkt, p->idx);
  1330. if (r) {
  1331. return r;
  1332. }
  1333. p->idx += pkt.count + 2;
  1334. switch (pkt.type) {
  1335. case PACKET_TYPE0:
  1336. if (p->rdev->family >= CHIP_R200)
  1337. r = r100_cs_parse_packet0(p, &pkt,
  1338. p->rdev->config.r100.reg_safe_bm,
  1339. p->rdev->config.r100.reg_safe_bm_size,
  1340. &r200_packet0_check);
  1341. else
  1342. r = r100_cs_parse_packet0(p, &pkt,
  1343. p->rdev->config.r100.reg_safe_bm,
  1344. p->rdev->config.r100.reg_safe_bm_size,
  1345. &r100_packet0_check);
  1346. break;
  1347. case PACKET_TYPE2:
  1348. break;
  1349. case PACKET_TYPE3:
  1350. r = r100_packet3_check(p, &pkt);
  1351. break;
  1352. default:
  1353. DRM_ERROR("Unknown packet type %d !\n",
  1354. pkt.type);
  1355. return -EINVAL;
  1356. }
  1357. if (r) {
  1358. return r;
  1359. }
  1360. } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
  1361. return 0;
  1362. }
  1363. /*
  1364. * Global GPU functions
  1365. */
  1366. void r100_errata(struct radeon_device *rdev)
  1367. {
  1368. rdev->pll_errata = 0;
  1369. if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
  1370. rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
  1371. }
  1372. if (rdev->family == CHIP_RV100 ||
  1373. rdev->family == CHIP_RS100 ||
  1374. rdev->family == CHIP_RS200) {
  1375. rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
  1376. }
  1377. }
  1378. /* Wait for vertical sync on primary CRTC */
  1379. void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
  1380. {
  1381. uint32_t crtc_gen_cntl, tmp;
  1382. int i;
  1383. crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
  1384. if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
  1385. !(crtc_gen_cntl & RADEON_CRTC_EN)) {
  1386. return;
  1387. }
  1388. /* Clear the CRTC_VBLANK_SAVE bit */
  1389. WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
  1390. for (i = 0; i < rdev->usec_timeout; i++) {
  1391. tmp = RREG32(RADEON_CRTC_STATUS);
  1392. if (tmp & RADEON_CRTC_VBLANK_SAVE) {
  1393. return;
  1394. }
  1395. DRM_UDELAY(1);
  1396. }
  1397. }
  1398. /* Wait for vertical sync on secondary CRTC */
  1399. void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
  1400. {
  1401. uint32_t crtc2_gen_cntl, tmp;
  1402. int i;
  1403. crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
  1404. if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
  1405. !(crtc2_gen_cntl & RADEON_CRTC2_EN))
  1406. return;
  1407. /* Clear the CRTC_VBLANK_SAVE bit */
  1408. WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
  1409. for (i = 0; i < rdev->usec_timeout; i++) {
  1410. tmp = RREG32(RADEON_CRTC2_STATUS);
  1411. if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
  1412. return;
  1413. }
  1414. DRM_UDELAY(1);
  1415. }
  1416. }
  1417. int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
  1418. {
  1419. unsigned i;
  1420. uint32_t tmp;
  1421. for (i = 0; i < rdev->usec_timeout; i++) {
  1422. tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
  1423. if (tmp >= n) {
  1424. return 0;
  1425. }
  1426. DRM_UDELAY(1);
  1427. }
  1428. return -1;
  1429. }
  1430. int r100_gui_wait_for_idle(struct radeon_device *rdev)
  1431. {
  1432. unsigned i;
  1433. uint32_t tmp;
  1434. if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
  1435. printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
  1436. " Bad things might happen.\n");
  1437. }
  1438. for (i = 0; i < rdev->usec_timeout; i++) {
  1439. tmp = RREG32(RADEON_RBBM_STATUS);
  1440. if (!(tmp & (1 << 31))) {
  1441. return 0;
  1442. }
  1443. DRM_UDELAY(1);
  1444. }
  1445. return -1;
  1446. }
  1447. int r100_mc_wait_for_idle(struct radeon_device *rdev)
  1448. {
  1449. unsigned i;
  1450. uint32_t tmp;
  1451. for (i = 0; i < rdev->usec_timeout; i++) {
  1452. /* read MC_STATUS */
  1453. tmp = RREG32(0x0150);
  1454. if (tmp & (1 << 2)) {
  1455. return 0;
  1456. }
  1457. DRM_UDELAY(1);
  1458. }
  1459. return -1;
  1460. }
  1461. void r100_gpu_init(struct radeon_device *rdev)
  1462. {
  1463. /* TODO: anythings to do here ? pipes ? */
  1464. r100_hdp_reset(rdev);
  1465. }
  1466. void r100_hdp_reset(struct radeon_device *rdev)
  1467. {
  1468. uint32_t tmp;
  1469. tmp = RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL;
  1470. tmp |= (7 << 28);
  1471. WREG32(RADEON_HOST_PATH_CNTL, tmp | RADEON_HDP_SOFT_RESET | RADEON_HDP_READ_BUFFER_INVALIDATE);
  1472. (void)RREG32(RADEON_HOST_PATH_CNTL);
  1473. udelay(200);
  1474. WREG32(RADEON_RBBM_SOFT_RESET, 0);
  1475. WREG32(RADEON_HOST_PATH_CNTL, tmp);
  1476. (void)RREG32(RADEON_HOST_PATH_CNTL);
  1477. }
  1478. int r100_rb2d_reset(struct radeon_device *rdev)
  1479. {
  1480. uint32_t tmp;
  1481. int i;
  1482. WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_E2);
  1483. (void)RREG32(RADEON_RBBM_SOFT_RESET);
  1484. udelay(200);
  1485. WREG32(RADEON_RBBM_SOFT_RESET, 0);
  1486. /* Wait to prevent race in RBBM_STATUS */
  1487. mdelay(1);
  1488. for (i = 0; i < rdev->usec_timeout; i++) {
  1489. tmp = RREG32(RADEON_RBBM_STATUS);
  1490. if (!(tmp & (1 << 26))) {
  1491. DRM_INFO("RB2D reset succeed (RBBM_STATUS=0x%08X)\n",
  1492. tmp);
  1493. return 0;
  1494. }
  1495. DRM_UDELAY(1);
  1496. }
  1497. tmp = RREG32(RADEON_RBBM_STATUS);
  1498. DRM_ERROR("Failed to reset RB2D (RBBM_STATUS=0x%08X)!\n", tmp);
  1499. return -1;
  1500. }
  1501. int r100_gpu_reset(struct radeon_device *rdev)
  1502. {
  1503. uint32_t status;
  1504. /* reset order likely matter */
  1505. status = RREG32(RADEON_RBBM_STATUS);
  1506. /* reset HDP */
  1507. r100_hdp_reset(rdev);
  1508. /* reset rb2d */
  1509. if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
  1510. r100_rb2d_reset(rdev);
  1511. }
  1512. /* TODO: reset 3D engine */
  1513. /* reset CP */
  1514. status = RREG32(RADEON_RBBM_STATUS);
  1515. if (status & (1 << 16)) {
  1516. r100_cp_reset(rdev);
  1517. }
  1518. /* Check if GPU is idle */
  1519. status = RREG32(RADEON_RBBM_STATUS);
  1520. if (status & (1 << 31)) {
  1521. DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
  1522. return -1;
  1523. }
  1524. DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
  1525. return 0;
  1526. }
  1527. /*
  1528. * VRAM info
  1529. */
  1530. static void r100_vram_get_type(struct radeon_device *rdev)
  1531. {
  1532. uint32_t tmp;
  1533. rdev->mc.vram_is_ddr = false;
  1534. if (rdev->flags & RADEON_IS_IGP)
  1535. rdev->mc.vram_is_ddr = true;
  1536. else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
  1537. rdev->mc.vram_is_ddr = true;
  1538. if ((rdev->family == CHIP_RV100) ||
  1539. (rdev->family == CHIP_RS100) ||
  1540. (rdev->family == CHIP_RS200)) {
  1541. tmp = RREG32(RADEON_MEM_CNTL);
  1542. if (tmp & RV100_HALF_MODE) {
  1543. rdev->mc.vram_width = 32;
  1544. } else {
  1545. rdev->mc.vram_width = 64;
  1546. }
  1547. if (rdev->flags & RADEON_SINGLE_CRTC) {
  1548. rdev->mc.vram_width /= 4;
  1549. rdev->mc.vram_is_ddr = true;
  1550. }
  1551. } else if (rdev->family <= CHIP_RV280) {
  1552. tmp = RREG32(RADEON_MEM_CNTL);
  1553. if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
  1554. rdev->mc.vram_width = 128;
  1555. } else {
  1556. rdev->mc.vram_width = 64;
  1557. }
  1558. } else {
  1559. /* newer IGPs */
  1560. rdev->mc.vram_width = 128;
  1561. }
  1562. }
  1563. static u32 r100_get_accessible_vram(struct radeon_device *rdev)
  1564. {
  1565. u32 aper_size;
  1566. u8 byte;
  1567. aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
  1568. /* Set HDP_APER_CNTL only on cards that are known not to be broken,
  1569. * that is has the 2nd generation multifunction PCI interface
  1570. */
  1571. if (rdev->family == CHIP_RV280 ||
  1572. rdev->family >= CHIP_RV350) {
  1573. WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
  1574. ~RADEON_HDP_APER_CNTL);
  1575. DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
  1576. return aper_size * 2;
  1577. }
  1578. /* Older cards have all sorts of funny issues to deal with. First
  1579. * check if it's a multifunction card by reading the PCI config
  1580. * header type... Limit those to one aperture size
  1581. */
  1582. pci_read_config_byte(rdev->pdev, 0xe, &byte);
  1583. if (byte & 0x80) {
  1584. DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
  1585. DRM_INFO("Limiting VRAM to one aperture\n");
  1586. return aper_size;
  1587. }
  1588. /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
  1589. * have set it up. We don't write this as it's broken on some ASICs but
  1590. * we expect the BIOS to have done the right thing (might be too optimistic...)
  1591. */
  1592. if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
  1593. return aper_size * 2;
  1594. return aper_size;
  1595. }
  1596. void r100_vram_init_sizes(struct radeon_device *rdev)
  1597. {
  1598. u64 config_aper_size;
  1599. u32 accessible;
  1600. config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
  1601. if (rdev->flags & RADEON_IS_IGP) {
  1602. uint32_t tom;
  1603. /* read NB_TOM to get the amount of ram stolen for the GPU */
  1604. tom = RREG32(RADEON_NB_TOM);
  1605. rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
  1606. /* for IGPs we need to keep VRAM where it was put by the BIOS */
  1607. rdev->mc.vram_location = (tom & 0xffff) << 16;
  1608. WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
  1609. rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
  1610. } else {
  1611. rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
  1612. /* Some production boards of m6 will report 0
  1613. * if it's 8 MB
  1614. */
  1615. if (rdev->mc.real_vram_size == 0) {
  1616. rdev->mc.real_vram_size = 8192 * 1024;
  1617. WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
  1618. }
  1619. /* let driver place VRAM */
  1620. rdev->mc.vram_location = 0xFFFFFFFFUL;
  1621. /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
  1622. * Novell bug 204882 + along with lots of ubuntu ones */
  1623. if (config_aper_size > rdev->mc.real_vram_size)
  1624. rdev->mc.mc_vram_size = config_aper_size;
  1625. else
  1626. rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
  1627. }
  1628. /* work out accessible VRAM */
  1629. accessible = r100_get_accessible_vram(rdev);
  1630. rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
  1631. rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
  1632. if (accessible > rdev->mc.aper_size)
  1633. accessible = rdev->mc.aper_size;
  1634. if (rdev->mc.mc_vram_size > rdev->mc.aper_size)
  1635. rdev->mc.mc_vram_size = rdev->mc.aper_size;
  1636. if (rdev->mc.real_vram_size > rdev->mc.aper_size)
  1637. rdev->mc.real_vram_size = rdev->mc.aper_size;
  1638. }
  1639. void r100_vga_set_state(struct radeon_device *rdev, bool state)
  1640. {
  1641. uint32_t temp;
  1642. temp = RREG32(RADEON_CONFIG_CNTL);
  1643. if (state == false) {
  1644. temp &= ~(1<<8);
  1645. temp |= (1<<9);
  1646. } else {
  1647. temp &= ~(1<<9);
  1648. }
  1649. WREG32(RADEON_CONFIG_CNTL, temp);
  1650. }
  1651. void r100_vram_info(struct radeon_device *rdev)
  1652. {
  1653. r100_vram_get_type(rdev);
  1654. r100_vram_init_sizes(rdev);
  1655. }
  1656. /*
  1657. * Indirect registers accessor
  1658. */
  1659. void r100_pll_errata_after_index(struct radeon_device *rdev)
  1660. {
  1661. if (!(rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS)) {
  1662. return;
  1663. }
  1664. (void)RREG32(RADEON_CLOCK_CNTL_DATA);
  1665. (void)RREG32(RADEON_CRTC_GEN_CNTL);
  1666. }
  1667. static void r100_pll_errata_after_data(struct radeon_device *rdev)
  1668. {
  1669. /* This workarounds is necessary on RV100, RS100 and RS200 chips
  1670. * or the chip could hang on a subsequent access
  1671. */
  1672. if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
  1673. udelay(5000);
  1674. }
  1675. /* This function is required to workaround a hardware bug in some (all?)
  1676. * revisions of the R300. This workaround should be called after every
  1677. * CLOCK_CNTL_INDEX register access. If not, register reads afterward
  1678. * may not be correct.
  1679. */
  1680. if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
  1681. uint32_t save, tmp;
  1682. save = RREG32(RADEON_CLOCK_CNTL_INDEX);
  1683. tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
  1684. WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
  1685. tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
  1686. WREG32(RADEON_CLOCK_CNTL_INDEX, save);
  1687. }
  1688. }
  1689. uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
  1690. {
  1691. uint32_t data;
  1692. WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
  1693. r100_pll_errata_after_index(rdev);
  1694. data = RREG32(RADEON_CLOCK_CNTL_DATA);
  1695. r100_pll_errata_after_data(rdev);
  1696. return data;
  1697. }
  1698. void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
  1699. {
  1700. WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
  1701. r100_pll_errata_after_index(rdev);
  1702. WREG32(RADEON_CLOCK_CNTL_DATA, v);
  1703. r100_pll_errata_after_data(rdev);
  1704. }
  1705. void r100_set_safe_registers(struct radeon_device *rdev)
  1706. {
  1707. if (ASIC_IS_RN50(rdev)) {
  1708. rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
  1709. rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
  1710. } else if (rdev->family < CHIP_R200) {
  1711. rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
  1712. rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
  1713. } else {
  1714. r200_set_safe_registers(rdev);
  1715. }
  1716. }
  1717. /*
  1718. * Debugfs info
  1719. */
  1720. #if defined(CONFIG_DEBUG_FS)
  1721. static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
  1722. {
  1723. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1724. struct drm_device *dev = node->minor->dev;
  1725. struct radeon_device *rdev = dev->dev_private;
  1726. uint32_t reg, value;
  1727. unsigned i;
  1728. seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
  1729. seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
  1730. seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
  1731. for (i = 0; i < 64; i++) {
  1732. WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
  1733. reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
  1734. WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
  1735. value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
  1736. seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
  1737. }
  1738. return 0;
  1739. }
  1740. static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
  1741. {
  1742. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1743. struct drm_device *dev = node->minor->dev;
  1744. struct radeon_device *rdev = dev->dev_private;
  1745. uint32_t rdp, wdp;
  1746. unsigned count, i, j;
  1747. radeon_ring_free_size(rdev);
  1748. rdp = RREG32(RADEON_CP_RB_RPTR);
  1749. wdp = RREG32(RADEON_CP_RB_WPTR);
  1750. count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
  1751. seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
  1752. seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
  1753. seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
  1754. seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
  1755. seq_printf(m, "%u dwords in ring\n", count);
  1756. for (j = 0; j <= count; j++) {
  1757. i = (rdp + j) & rdev->cp.ptr_mask;
  1758. seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
  1759. }
  1760. return 0;
  1761. }
  1762. static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
  1763. {
  1764. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1765. struct drm_device *dev = node->minor->dev;
  1766. struct radeon_device *rdev = dev->dev_private;
  1767. uint32_t csq_stat, csq2_stat, tmp;
  1768. unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
  1769. unsigned i;
  1770. seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
  1771. seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
  1772. csq_stat = RREG32(RADEON_CP_CSQ_STAT);
  1773. csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
  1774. r_rptr = (csq_stat >> 0) & 0x3ff;
  1775. r_wptr = (csq_stat >> 10) & 0x3ff;
  1776. ib1_rptr = (csq_stat >> 20) & 0x3ff;
  1777. ib1_wptr = (csq2_stat >> 0) & 0x3ff;
  1778. ib2_rptr = (csq2_stat >> 10) & 0x3ff;
  1779. ib2_wptr = (csq2_stat >> 20) & 0x3ff;
  1780. seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
  1781. seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
  1782. seq_printf(m, "Ring rptr %u\n", r_rptr);
  1783. seq_printf(m, "Ring wptr %u\n", r_wptr);
  1784. seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
  1785. seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
  1786. seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
  1787. seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
  1788. /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
  1789. * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
  1790. seq_printf(m, "Ring fifo:\n");
  1791. for (i = 0; i < 256; i++) {
  1792. WREG32(RADEON_CP_CSQ_ADDR, i << 2);
  1793. tmp = RREG32(RADEON_CP_CSQ_DATA);
  1794. seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
  1795. }
  1796. seq_printf(m, "Indirect1 fifo:\n");
  1797. for (i = 256; i <= 512; i++) {
  1798. WREG32(RADEON_CP_CSQ_ADDR, i << 2);
  1799. tmp = RREG32(RADEON_CP_CSQ_DATA);
  1800. seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
  1801. }
  1802. seq_printf(m, "Indirect2 fifo:\n");
  1803. for (i = 640; i < ib1_wptr; i++) {
  1804. WREG32(RADEON_CP_CSQ_ADDR, i << 2);
  1805. tmp = RREG32(RADEON_CP_CSQ_DATA);
  1806. seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
  1807. }
  1808. return 0;
  1809. }
  1810. static int r100_debugfs_mc_info(struct seq_file *m, void *data)
  1811. {
  1812. struct drm_info_node *node = (struct drm_info_node *) m->private;
  1813. struct drm_device *dev = node->minor->dev;
  1814. struct radeon_device *rdev = dev->dev_private;
  1815. uint32_t tmp;
  1816. tmp = RREG32(RADEON_CONFIG_MEMSIZE);
  1817. seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
  1818. tmp = RREG32(RADEON_MC_FB_LOCATION);
  1819. seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
  1820. tmp = RREG32(RADEON_BUS_CNTL);
  1821. seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
  1822. tmp = RREG32(RADEON_MC_AGP_LOCATION);
  1823. seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
  1824. tmp = RREG32(RADEON_AGP_BASE);
  1825. seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
  1826. tmp = RREG32(RADEON_HOST_PATH_CNTL);
  1827. seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
  1828. tmp = RREG32(0x01D0);
  1829. seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
  1830. tmp = RREG32(RADEON_AIC_LO_ADDR);
  1831. seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
  1832. tmp = RREG32(RADEON_AIC_HI_ADDR);
  1833. seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
  1834. tmp = RREG32(0x01E4);
  1835. seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
  1836. return 0;
  1837. }
  1838. static struct drm_info_list r100_debugfs_rbbm_list[] = {
  1839. {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
  1840. };
  1841. static struct drm_info_list r100_debugfs_cp_list[] = {
  1842. {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
  1843. {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
  1844. };
  1845. static struct drm_info_list r100_debugfs_mc_info_list[] = {
  1846. {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
  1847. };
  1848. #endif
  1849. int r100_debugfs_rbbm_init(struct radeon_device *rdev)
  1850. {
  1851. #if defined(CONFIG_DEBUG_FS)
  1852. return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
  1853. #else
  1854. return 0;
  1855. #endif
  1856. }
  1857. int r100_debugfs_cp_init(struct radeon_device *rdev)
  1858. {
  1859. #if defined(CONFIG_DEBUG_FS)
  1860. return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
  1861. #else
  1862. return 0;
  1863. #endif
  1864. }
  1865. int r100_debugfs_mc_info_init(struct radeon_device *rdev)
  1866. {
  1867. #if defined(CONFIG_DEBUG_FS)
  1868. return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
  1869. #else
  1870. return 0;
  1871. #endif
  1872. }
  1873. int r100_set_surface_reg(struct radeon_device *rdev, int reg,
  1874. uint32_t tiling_flags, uint32_t pitch,
  1875. uint32_t offset, uint32_t obj_size)
  1876. {
  1877. int surf_index = reg * 16;
  1878. int flags = 0;
  1879. /* r100/r200 divide by 16 */
  1880. if (rdev->family < CHIP_R300)
  1881. flags = pitch / 16;
  1882. else
  1883. flags = pitch / 8;
  1884. if (rdev->family <= CHIP_RS200) {
  1885. if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
  1886. == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
  1887. flags |= RADEON_SURF_TILE_COLOR_BOTH;
  1888. if (tiling_flags & RADEON_TILING_MACRO)
  1889. flags |= RADEON_SURF_TILE_COLOR_MACRO;
  1890. } else if (rdev->family <= CHIP_RV280) {
  1891. if (tiling_flags & (RADEON_TILING_MACRO))
  1892. flags |= R200_SURF_TILE_COLOR_MACRO;
  1893. if (tiling_flags & RADEON_TILING_MICRO)
  1894. flags |= R200_SURF_TILE_COLOR_MICRO;
  1895. } else {
  1896. if (tiling_flags & RADEON_TILING_MACRO)
  1897. flags |= R300_SURF_TILE_MACRO;
  1898. if (tiling_flags & RADEON_TILING_MICRO)
  1899. flags |= R300_SURF_TILE_MICRO;
  1900. }
  1901. if (tiling_flags & RADEON_TILING_SWAP_16BIT)
  1902. flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
  1903. if (tiling_flags & RADEON_TILING_SWAP_32BIT)
  1904. flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
  1905. DRM_DEBUG("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
  1906. WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
  1907. WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
  1908. WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
  1909. return 0;
  1910. }
  1911. void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
  1912. {
  1913. int surf_index = reg * 16;
  1914. WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
  1915. }
  1916. void r100_bandwidth_update(struct radeon_device *rdev)
  1917. {
  1918. fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
  1919. fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
  1920. fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
  1921. uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
  1922. fixed20_12 memtcas_ff[8] = {
  1923. fixed_init(1),
  1924. fixed_init(2),
  1925. fixed_init(3),
  1926. fixed_init(0),
  1927. fixed_init_half(1),
  1928. fixed_init_half(2),
  1929. fixed_init(0),
  1930. };
  1931. fixed20_12 memtcas_rs480_ff[8] = {
  1932. fixed_init(0),
  1933. fixed_init(1),
  1934. fixed_init(2),
  1935. fixed_init(3),
  1936. fixed_init(0),
  1937. fixed_init_half(1),
  1938. fixed_init_half(2),
  1939. fixed_init_half(3),
  1940. };
  1941. fixed20_12 memtcas2_ff[8] = {
  1942. fixed_init(0),
  1943. fixed_init(1),
  1944. fixed_init(2),
  1945. fixed_init(3),
  1946. fixed_init(4),
  1947. fixed_init(5),
  1948. fixed_init(6),
  1949. fixed_init(7),
  1950. };
  1951. fixed20_12 memtrbs[8] = {
  1952. fixed_init(1),
  1953. fixed_init_half(1),
  1954. fixed_init(2),
  1955. fixed_init_half(2),
  1956. fixed_init(3),
  1957. fixed_init_half(3),
  1958. fixed_init(4),
  1959. fixed_init_half(4)
  1960. };
  1961. fixed20_12 memtrbs_r4xx[8] = {
  1962. fixed_init(4),
  1963. fixed_init(5),
  1964. fixed_init(6),
  1965. fixed_init(7),
  1966. fixed_init(8),
  1967. fixed_init(9),
  1968. fixed_init(10),
  1969. fixed_init(11)
  1970. };
  1971. fixed20_12 min_mem_eff;
  1972. fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
  1973. fixed20_12 cur_latency_mclk, cur_latency_sclk;
  1974. fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
  1975. disp_drain_rate2, read_return_rate;
  1976. fixed20_12 time_disp1_drop_priority;
  1977. int c;
  1978. int cur_size = 16; /* in octawords */
  1979. int critical_point = 0, critical_point2;
  1980. /* uint32_t read_return_rate, time_disp1_drop_priority; */
  1981. int stop_req, max_stop_req;
  1982. struct drm_display_mode *mode1 = NULL;
  1983. struct drm_display_mode *mode2 = NULL;
  1984. uint32_t pixel_bytes1 = 0;
  1985. uint32_t pixel_bytes2 = 0;
  1986. if (rdev->mode_info.crtcs[0]->base.enabled) {
  1987. mode1 = &rdev->mode_info.crtcs[0]->base.mode;
  1988. pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
  1989. }
  1990. if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
  1991. if (rdev->mode_info.crtcs[1]->base.enabled) {
  1992. mode2 = &rdev->mode_info.crtcs[1]->base.mode;
  1993. pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
  1994. }
  1995. }
  1996. min_mem_eff.full = rfixed_const_8(0);
  1997. /* get modes */
  1998. if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
  1999. uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
  2000. mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
  2001. mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
  2002. /* check crtc enables */
  2003. if (mode2)
  2004. mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
  2005. if (mode1)
  2006. mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
  2007. WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
  2008. }
  2009. /*
  2010. * determine is there is enough bw for current mode
  2011. */
  2012. mclk_ff.full = rfixed_const(rdev->clock.default_mclk);
  2013. temp_ff.full = rfixed_const(100);
  2014. mclk_ff.full = rfixed_div(mclk_ff, temp_ff);
  2015. sclk_ff.full = rfixed_const(rdev->clock.default_sclk);
  2016. sclk_ff.full = rfixed_div(sclk_ff, temp_ff);
  2017. temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
  2018. temp_ff.full = rfixed_const(temp);
  2019. mem_bw.full = rfixed_mul(mclk_ff, temp_ff);
  2020. pix_clk.full = 0;
  2021. pix_clk2.full = 0;
  2022. peak_disp_bw.full = 0;
  2023. if (mode1) {
  2024. temp_ff.full = rfixed_const(1000);
  2025. pix_clk.full = rfixed_const(mode1->clock); /* convert to fixed point */
  2026. pix_clk.full = rfixed_div(pix_clk, temp_ff);
  2027. temp_ff.full = rfixed_const(pixel_bytes1);
  2028. peak_disp_bw.full += rfixed_mul(pix_clk, temp_ff);
  2029. }
  2030. if (mode2) {
  2031. temp_ff.full = rfixed_const(1000);
  2032. pix_clk2.full = rfixed_const(mode2->clock); /* convert to fixed point */
  2033. pix_clk2.full = rfixed_div(pix_clk2, temp_ff);
  2034. temp_ff.full = rfixed_const(pixel_bytes2);
  2035. peak_disp_bw.full += rfixed_mul(pix_clk2, temp_ff);
  2036. }
  2037. mem_bw.full = rfixed_mul(mem_bw, min_mem_eff);
  2038. if (peak_disp_bw.full >= mem_bw.full) {
  2039. DRM_ERROR("You may not have enough display bandwidth for current mode\n"
  2040. "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
  2041. }
  2042. /* Get values from the EXT_MEM_CNTL register...converting its contents. */
  2043. temp = RREG32(RADEON_MEM_TIMING_CNTL);
  2044. if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
  2045. mem_trcd = ((temp >> 2) & 0x3) + 1;
  2046. mem_trp = ((temp & 0x3)) + 1;
  2047. mem_tras = ((temp & 0x70) >> 4) + 1;
  2048. } else if (rdev->family == CHIP_R300 ||
  2049. rdev->family == CHIP_R350) { /* r300, r350 */
  2050. mem_trcd = (temp & 0x7) + 1;
  2051. mem_trp = ((temp >> 8) & 0x7) + 1;
  2052. mem_tras = ((temp >> 11) & 0xf) + 4;
  2053. } else if (rdev->family == CHIP_RV350 ||
  2054. rdev->family <= CHIP_RV380) {
  2055. /* rv3x0 */
  2056. mem_trcd = (temp & 0x7) + 3;
  2057. mem_trp = ((temp >> 8) & 0x7) + 3;
  2058. mem_tras = ((temp >> 11) & 0xf) + 6;
  2059. } else if (rdev->family == CHIP_R420 ||
  2060. rdev->family == CHIP_R423 ||
  2061. rdev->family == CHIP_RV410) {
  2062. /* r4xx */
  2063. mem_trcd = (temp & 0xf) + 3;
  2064. if (mem_trcd > 15)
  2065. mem_trcd = 15;
  2066. mem_trp = ((temp >> 8) & 0xf) + 3;
  2067. if (mem_trp > 15)
  2068. mem_trp = 15;
  2069. mem_tras = ((temp >> 12) & 0x1f) + 6;
  2070. if (mem_tras > 31)
  2071. mem_tras = 31;
  2072. } else { /* RV200, R200 */
  2073. mem_trcd = (temp & 0x7) + 1;
  2074. mem_trp = ((temp >> 8) & 0x7) + 1;
  2075. mem_tras = ((temp >> 12) & 0xf) + 4;
  2076. }
  2077. /* convert to FF */
  2078. trcd_ff.full = rfixed_const(mem_trcd);
  2079. trp_ff.full = rfixed_const(mem_trp);
  2080. tras_ff.full = rfixed_const(mem_tras);
  2081. /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
  2082. temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
  2083. data = (temp & (7 << 20)) >> 20;
  2084. if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
  2085. if (rdev->family == CHIP_RS480) /* don't think rs400 */
  2086. tcas_ff = memtcas_rs480_ff[data];
  2087. else
  2088. tcas_ff = memtcas_ff[data];
  2089. } else
  2090. tcas_ff = memtcas2_ff[data];
  2091. if (rdev->family == CHIP_RS400 ||
  2092. rdev->family == CHIP_RS480) {
  2093. /* extra cas latency stored in bits 23-25 0-4 clocks */
  2094. data = (temp >> 23) & 0x7;
  2095. if (data < 5)
  2096. tcas_ff.full += rfixed_const(data);
  2097. }
  2098. if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
  2099. /* on the R300, Tcas is included in Trbs.
  2100. */
  2101. temp = RREG32(RADEON_MEM_CNTL);
  2102. data = (R300_MEM_NUM_CHANNELS_MASK & temp);
  2103. if (data == 1) {
  2104. if (R300_MEM_USE_CD_CH_ONLY & temp) {
  2105. temp = RREG32(R300_MC_IND_INDEX);
  2106. temp &= ~R300_MC_IND_ADDR_MASK;
  2107. temp |= R300_MC_READ_CNTL_CD_mcind;
  2108. WREG32(R300_MC_IND_INDEX, temp);
  2109. temp = RREG32(R300_MC_IND_DATA);
  2110. data = (R300_MEM_RBS_POSITION_C_MASK & temp);
  2111. } else {
  2112. temp = RREG32(R300_MC_READ_CNTL_AB);
  2113. data = (R300_MEM_RBS_POSITION_A_MASK & temp);
  2114. }
  2115. } else {
  2116. temp = RREG32(R300_MC_READ_CNTL_AB);
  2117. data = (R300_MEM_RBS_POSITION_A_MASK & temp);
  2118. }
  2119. if (rdev->family == CHIP_RV410 ||
  2120. rdev->family == CHIP_R420 ||
  2121. rdev->family == CHIP_R423)
  2122. trbs_ff = memtrbs_r4xx[data];
  2123. else
  2124. trbs_ff = memtrbs[data];
  2125. tcas_ff.full += trbs_ff.full;
  2126. }
  2127. sclk_eff_ff.full = sclk_ff.full;
  2128. if (rdev->flags & RADEON_IS_AGP) {
  2129. fixed20_12 agpmode_ff;
  2130. agpmode_ff.full = rfixed_const(radeon_agpmode);
  2131. temp_ff.full = rfixed_const_666(16);
  2132. sclk_eff_ff.full -= rfixed_mul(agpmode_ff, temp_ff);
  2133. }
  2134. /* TODO PCIE lanes may affect this - agpmode == 16?? */
  2135. if (ASIC_IS_R300(rdev)) {
  2136. sclk_delay_ff.full = rfixed_const(250);
  2137. } else {
  2138. if ((rdev->family == CHIP_RV100) ||
  2139. rdev->flags & RADEON_IS_IGP) {
  2140. if (rdev->mc.vram_is_ddr)
  2141. sclk_delay_ff.full = rfixed_const(41);
  2142. else
  2143. sclk_delay_ff.full = rfixed_const(33);
  2144. } else {
  2145. if (rdev->mc.vram_width == 128)
  2146. sclk_delay_ff.full = rfixed_const(57);
  2147. else
  2148. sclk_delay_ff.full = rfixed_const(41);
  2149. }
  2150. }
  2151. mc_latency_sclk.full = rfixed_div(sclk_delay_ff, sclk_eff_ff);
  2152. if (rdev->mc.vram_is_ddr) {
  2153. if (rdev->mc.vram_width == 32) {
  2154. k1.full = rfixed_const(40);
  2155. c = 3;
  2156. } else {
  2157. k1.full = rfixed_const(20);
  2158. c = 1;
  2159. }
  2160. } else {
  2161. k1.full = rfixed_const(40);
  2162. c = 3;
  2163. }
  2164. temp_ff.full = rfixed_const(2);
  2165. mc_latency_mclk.full = rfixed_mul(trcd_ff, temp_ff);
  2166. temp_ff.full = rfixed_const(c);
  2167. mc_latency_mclk.full += rfixed_mul(tcas_ff, temp_ff);
  2168. temp_ff.full = rfixed_const(4);
  2169. mc_latency_mclk.full += rfixed_mul(tras_ff, temp_ff);
  2170. mc_latency_mclk.full += rfixed_mul(trp_ff, temp_ff);
  2171. mc_latency_mclk.full += k1.full;
  2172. mc_latency_mclk.full = rfixed_div(mc_latency_mclk, mclk_ff);
  2173. mc_latency_mclk.full += rfixed_div(temp_ff, sclk_eff_ff);
  2174. /*
  2175. HW cursor time assuming worst case of full size colour cursor.
  2176. */
  2177. temp_ff.full = rfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
  2178. temp_ff.full += trcd_ff.full;
  2179. if (temp_ff.full < tras_ff.full)
  2180. temp_ff.full = tras_ff.full;
  2181. cur_latency_mclk.full = rfixed_div(temp_ff, mclk_ff);
  2182. temp_ff.full = rfixed_const(cur_size);
  2183. cur_latency_sclk.full = rfixed_div(temp_ff, sclk_eff_ff);
  2184. /*
  2185. Find the total latency for the display data.
  2186. */
  2187. disp_latency_overhead.full = rfixed_const(80);
  2188. disp_latency_overhead.full = rfixed_div(disp_latency_overhead, sclk_ff);
  2189. mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
  2190. mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
  2191. if (mc_latency_mclk.full > mc_latency_sclk.full)
  2192. disp_latency.full = mc_latency_mclk.full;
  2193. else
  2194. disp_latency.full = mc_latency_sclk.full;
  2195. /* setup Max GRPH_STOP_REQ default value */
  2196. if (ASIC_IS_RV100(rdev))
  2197. max_stop_req = 0x5c;
  2198. else
  2199. max_stop_req = 0x7c;
  2200. if (mode1) {
  2201. /* CRTC1
  2202. Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
  2203. GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
  2204. */
  2205. stop_req = mode1->hdisplay * pixel_bytes1 / 16;
  2206. if (stop_req > max_stop_req)
  2207. stop_req = max_stop_req;
  2208. /*
  2209. Find the drain rate of the display buffer.
  2210. */
  2211. temp_ff.full = rfixed_const((16/pixel_bytes1));
  2212. disp_drain_rate.full = rfixed_div(pix_clk, temp_ff);
  2213. /*
  2214. Find the critical point of the display buffer.
  2215. */
  2216. crit_point_ff.full = rfixed_mul(disp_drain_rate, disp_latency);
  2217. crit_point_ff.full += rfixed_const_half(0);
  2218. critical_point = rfixed_trunc(crit_point_ff);
  2219. if (rdev->disp_priority == 2) {
  2220. critical_point = 0;
  2221. }
  2222. /*
  2223. The critical point should never be above max_stop_req-4. Setting
  2224. GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
  2225. */
  2226. if (max_stop_req - critical_point < 4)
  2227. critical_point = 0;
  2228. if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
  2229. /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
  2230. critical_point = 0x10;
  2231. }
  2232. temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
  2233. temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
  2234. temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
  2235. temp &= ~(RADEON_GRPH_START_REQ_MASK);
  2236. if ((rdev->family == CHIP_R350) &&
  2237. (stop_req > 0x15)) {
  2238. stop_req -= 0x10;
  2239. }
  2240. temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
  2241. temp |= RADEON_GRPH_BUFFER_SIZE;
  2242. temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
  2243. RADEON_GRPH_CRITICAL_AT_SOF |
  2244. RADEON_GRPH_STOP_CNTL);
  2245. /*
  2246. Write the result into the register.
  2247. */
  2248. WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
  2249. (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
  2250. #if 0
  2251. if ((rdev->family == CHIP_RS400) ||
  2252. (rdev->family == CHIP_RS480)) {
  2253. /* attempt to program RS400 disp regs correctly ??? */
  2254. temp = RREG32(RS400_DISP1_REG_CNTL);
  2255. temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
  2256. RS400_DISP1_STOP_REQ_LEVEL_MASK);
  2257. WREG32(RS400_DISP1_REQ_CNTL1, (temp |
  2258. (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
  2259. (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
  2260. temp = RREG32(RS400_DMIF_MEM_CNTL1);
  2261. temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
  2262. RS400_DISP1_CRITICAL_POINT_STOP_MASK);
  2263. WREG32(RS400_DMIF_MEM_CNTL1, (temp |
  2264. (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
  2265. (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
  2266. }
  2267. #endif
  2268. DRM_DEBUG("GRPH_BUFFER_CNTL from to %x\n",
  2269. /* (unsigned int)info->SavedReg->grph_buffer_cntl, */
  2270. (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
  2271. }
  2272. if (mode2) {
  2273. u32 grph2_cntl;
  2274. stop_req = mode2->hdisplay * pixel_bytes2 / 16;
  2275. if (stop_req > max_stop_req)
  2276. stop_req = max_stop_req;
  2277. /*
  2278. Find the drain rate of the display buffer.
  2279. */
  2280. temp_ff.full = rfixed_const((16/pixel_bytes2));
  2281. disp_drain_rate2.full = rfixed_div(pix_clk2, temp_ff);
  2282. grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
  2283. grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
  2284. grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
  2285. grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
  2286. if ((rdev->family == CHIP_R350) &&
  2287. (stop_req > 0x15)) {
  2288. stop_req -= 0x10;
  2289. }
  2290. grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
  2291. grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
  2292. grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL |
  2293. RADEON_GRPH_CRITICAL_AT_SOF |
  2294. RADEON_GRPH_STOP_CNTL);
  2295. if ((rdev->family == CHIP_RS100) ||
  2296. (rdev->family == CHIP_RS200))
  2297. critical_point2 = 0;
  2298. else {
  2299. temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
  2300. temp_ff.full = rfixed_const(temp);
  2301. temp_ff.full = rfixed_mul(mclk_ff, temp_ff);
  2302. if (sclk_ff.full < temp_ff.full)
  2303. temp_ff.full = sclk_ff.full;
  2304. read_return_rate.full = temp_ff.full;
  2305. if (mode1) {
  2306. temp_ff.full = read_return_rate.full - disp_drain_rate.full;
  2307. time_disp1_drop_priority.full = rfixed_div(crit_point_ff, temp_ff);
  2308. } else {
  2309. time_disp1_drop_priority.full = 0;
  2310. }
  2311. crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
  2312. crit_point_ff.full = rfixed_mul(crit_point_ff, disp_drain_rate2);
  2313. crit_point_ff.full += rfixed_const_half(0);
  2314. critical_point2 = rfixed_trunc(crit_point_ff);
  2315. if (rdev->disp_priority == 2) {
  2316. critical_point2 = 0;
  2317. }
  2318. if (max_stop_req - critical_point2 < 4)
  2319. critical_point2 = 0;
  2320. }
  2321. if (critical_point2 == 0 && rdev->family == CHIP_R300) {
  2322. /* some R300 cards have problem with this set to 0 */
  2323. critical_point2 = 0x10;
  2324. }
  2325. WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
  2326. (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
  2327. if ((rdev->family == CHIP_RS400) ||
  2328. (rdev->family == CHIP_RS480)) {
  2329. #if 0
  2330. /* attempt to program RS400 disp2 regs correctly ??? */
  2331. temp = RREG32(RS400_DISP2_REQ_CNTL1);
  2332. temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
  2333. RS400_DISP2_STOP_REQ_LEVEL_MASK);
  2334. WREG32(RS400_DISP2_REQ_CNTL1, (temp |
  2335. (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
  2336. (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
  2337. temp = RREG32(RS400_DISP2_REQ_CNTL2);
  2338. temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
  2339. RS400_DISP2_CRITICAL_POINT_STOP_MASK);
  2340. WREG32(RS400_DISP2_REQ_CNTL2, (temp |
  2341. (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
  2342. (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
  2343. #endif
  2344. WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
  2345. WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
  2346. WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
  2347. WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
  2348. }
  2349. DRM_DEBUG("GRPH2_BUFFER_CNTL from to %x\n",
  2350. (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
  2351. }
  2352. }
  2353. static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
  2354. {
  2355. DRM_ERROR("pitch %d\n", t->pitch);
  2356. DRM_ERROR("width %d\n", t->width);
  2357. DRM_ERROR("height %d\n", t->height);
  2358. DRM_ERROR("num levels %d\n", t->num_levels);
  2359. DRM_ERROR("depth %d\n", t->txdepth);
  2360. DRM_ERROR("bpp %d\n", t->cpp);
  2361. DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
  2362. DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
  2363. DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
  2364. }
  2365. static int r100_cs_track_cube(struct radeon_device *rdev,
  2366. struct r100_cs_track *track, unsigned idx)
  2367. {
  2368. unsigned face, w, h;
  2369. struct radeon_object *cube_robj;
  2370. unsigned long size;
  2371. for (face = 0; face < 5; face++) {
  2372. cube_robj = track->textures[idx].cube_info[face].robj;
  2373. w = track->textures[idx].cube_info[face].width;
  2374. h = track->textures[idx].cube_info[face].height;
  2375. size = w * h;
  2376. size *= track->textures[idx].cpp;
  2377. size += track->textures[idx].cube_info[face].offset;
  2378. if (size > radeon_object_size(cube_robj)) {
  2379. DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
  2380. size, radeon_object_size(cube_robj));
  2381. r100_cs_track_texture_print(&track->textures[idx]);
  2382. return -1;
  2383. }
  2384. }
  2385. return 0;
  2386. }
  2387. static int r100_cs_track_texture_check(struct radeon_device *rdev,
  2388. struct r100_cs_track *track)
  2389. {
  2390. struct radeon_object *robj;
  2391. unsigned long size;
  2392. unsigned u, i, w, h;
  2393. int ret;
  2394. for (u = 0; u < track->num_texture; u++) {
  2395. if (!track->textures[u].enabled)
  2396. continue;
  2397. robj = track->textures[u].robj;
  2398. if (robj == NULL) {
  2399. DRM_ERROR("No texture bound to unit %u\n", u);
  2400. return -EINVAL;
  2401. }
  2402. size = 0;
  2403. for (i = 0; i <= track->textures[u].num_levels; i++) {
  2404. if (track->textures[u].use_pitch) {
  2405. if (rdev->family < CHIP_R300)
  2406. w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
  2407. else
  2408. w = track->textures[u].pitch / (1 << i);
  2409. } else {
  2410. w = track->textures[u].width / (1 << i);
  2411. if (rdev->family >= CHIP_RV515)
  2412. w |= track->textures[u].width_11;
  2413. if (track->textures[u].roundup_w)
  2414. w = roundup_pow_of_two(w);
  2415. }
  2416. h = track->textures[u].height / (1 << i);
  2417. if (rdev->family >= CHIP_RV515)
  2418. h |= track->textures[u].height_11;
  2419. if (track->textures[u].roundup_h)
  2420. h = roundup_pow_of_two(h);
  2421. size += w * h;
  2422. }
  2423. size *= track->textures[u].cpp;
  2424. switch (track->textures[u].tex_coord_type) {
  2425. case 0:
  2426. break;
  2427. case 1:
  2428. size *= (1 << track->textures[u].txdepth);
  2429. break;
  2430. case 2:
  2431. if (track->separate_cube) {
  2432. ret = r100_cs_track_cube(rdev, track, u);
  2433. if (ret)
  2434. return ret;
  2435. } else
  2436. size *= 6;
  2437. break;
  2438. default:
  2439. DRM_ERROR("Invalid texture coordinate type %u for unit "
  2440. "%u\n", track->textures[u].tex_coord_type, u);
  2441. return -EINVAL;
  2442. }
  2443. if (size > radeon_object_size(robj)) {
  2444. DRM_ERROR("Texture of unit %u needs %lu bytes but is "
  2445. "%lu\n", u, size, radeon_object_size(robj));
  2446. r100_cs_track_texture_print(&track->textures[u]);
  2447. return -EINVAL;
  2448. }
  2449. }
  2450. return 0;
  2451. }
  2452. int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
  2453. {
  2454. unsigned i;
  2455. unsigned long size;
  2456. unsigned prim_walk;
  2457. unsigned nverts;
  2458. for (i = 0; i < track->num_cb; i++) {
  2459. if (track->cb[i].robj == NULL) {
  2460. DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
  2461. return -EINVAL;
  2462. }
  2463. size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
  2464. size += track->cb[i].offset;
  2465. if (size > radeon_object_size(track->cb[i].robj)) {
  2466. DRM_ERROR("[drm] Buffer too small for color buffer %d "
  2467. "(need %lu have %lu) !\n", i, size,
  2468. radeon_object_size(track->cb[i].robj));
  2469. DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
  2470. i, track->cb[i].pitch, track->cb[i].cpp,
  2471. track->cb[i].offset, track->maxy);
  2472. return -EINVAL;
  2473. }
  2474. }
  2475. if (track->z_enabled) {
  2476. if (track->zb.robj == NULL) {
  2477. DRM_ERROR("[drm] No buffer for z buffer !\n");
  2478. return -EINVAL;
  2479. }
  2480. size = track->zb.pitch * track->zb.cpp * track->maxy;
  2481. size += track->zb.offset;
  2482. if (size > radeon_object_size(track->zb.robj)) {
  2483. DRM_ERROR("[drm] Buffer too small for z buffer "
  2484. "(need %lu have %lu) !\n", size,
  2485. radeon_object_size(track->zb.robj));
  2486. DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
  2487. track->zb.pitch, track->zb.cpp,
  2488. track->zb.offset, track->maxy);
  2489. return -EINVAL;
  2490. }
  2491. }
  2492. prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
  2493. nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
  2494. switch (prim_walk) {
  2495. case 1:
  2496. for (i = 0; i < track->num_arrays; i++) {
  2497. size = track->arrays[i].esize * track->max_indx * 4;
  2498. if (track->arrays[i].robj == NULL) {
  2499. DRM_ERROR("(PW %u) Vertex array %u no buffer "
  2500. "bound\n", prim_walk, i);
  2501. return -EINVAL;
  2502. }
  2503. if (size > radeon_object_size(track->arrays[i].robj)) {
  2504. DRM_ERROR("(PW %u) Vertex array %u need %lu dwords "
  2505. "have %lu dwords\n", prim_walk, i,
  2506. size >> 2,
  2507. radeon_object_size(track->arrays[i].robj) >> 2);
  2508. DRM_ERROR("Max indices %u\n", track->max_indx);
  2509. return -EINVAL;
  2510. }
  2511. }
  2512. break;
  2513. case 2:
  2514. for (i = 0; i < track->num_arrays; i++) {
  2515. size = track->arrays[i].esize * (nverts - 1) * 4;
  2516. if (track->arrays[i].robj == NULL) {
  2517. DRM_ERROR("(PW %u) Vertex array %u no buffer "
  2518. "bound\n", prim_walk, i);
  2519. return -EINVAL;
  2520. }
  2521. if (size > radeon_object_size(track->arrays[i].robj)) {
  2522. DRM_ERROR("(PW %u) Vertex array %u need %lu dwords "
  2523. "have %lu dwords\n", prim_walk, i, size >> 2,
  2524. radeon_object_size(track->arrays[i].robj) >> 2);
  2525. return -EINVAL;
  2526. }
  2527. }
  2528. break;
  2529. case 3:
  2530. size = track->vtx_size * nverts;
  2531. if (size != track->immd_dwords) {
  2532. DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
  2533. track->immd_dwords, size);
  2534. DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
  2535. nverts, track->vtx_size);
  2536. return -EINVAL;
  2537. }
  2538. break;
  2539. default:
  2540. DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
  2541. prim_walk);
  2542. return -EINVAL;
  2543. }
  2544. return r100_cs_track_texture_check(rdev, track);
  2545. }
  2546. void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
  2547. {
  2548. unsigned i, face;
  2549. if (rdev->family < CHIP_R300) {
  2550. track->num_cb = 1;
  2551. if (rdev->family <= CHIP_RS200)
  2552. track->num_texture = 3;
  2553. else
  2554. track->num_texture = 6;
  2555. track->maxy = 2048;
  2556. track->separate_cube = 1;
  2557. } else {
  2558. track->num_cb = 4;
  2559. track->num_texture = 16;
  2560. track->maxy = 4096;
  2561. track->separate_cube = 0;
  2562. }
  2563. for (i = 0; i < track->num_cb; i++) {
  2564. track->cb[i].robj = NULL;
  2565. track->cb[i].pitch = 8192;
  2566. track->cb[i].cpp = 16;
  2567. track->cb[i].offset = 0;
  2568. }
  2569. track->z_enabled = true;
  2570. track->zb.robj = NULL;
  2571. track->zb.pitch = 8192;
  2572. track->zb.cpp = 4;
  2573. track->zb.offset = 0;
  2574. track->vtx_size = 0x7F;
  2575. track->immd_dwords = 0xFFFFFFFFUL;
  2576. track->num_arrays = 11;
  2577. track->max_indx = 0x00FFFFFFUL;
  2578. for (i = 0; i < track->num_arrays; i++) {
  2579. track->arrays[i].robj = NULL;
  2580. track->arrays[i].esize = 0x7F;
  2581. }
  2582. for (i = 0; i < track->num_texture; i++) {
  2583. track->textures[i].pitch = 16536;
  2584. track->textures[i].width = 16536;
  2585. track->textures[i].height = 16536;
  2586. track->textures[i].width_11 = 1 << 11;
  2587. track->textures[i].height_11 = 1 << 11;
  2588. track->textures[i].num_levels = 12;
  2589. if (rdev->family <= CHIP_RS200) {
  2590. track->textures[i].tex_coord_type = 0;
  2591. track->textures[i].txdepth = 0;
  2592. } else {
  2593. track->textures[i].txdepth = 16;
  2594. track->textures[i].tex_coord_type = 1;
  2595. }
  2596. track->textures[i].cpp = 64;
  2597. track->textures[i].robj = NULL;
  2598. /* CS IB emission code makes sure texture unit are disabled */
  2599. track->textures[i].enabled = false;
  2600. track->textures[i].roundup_w = true;
  2601. track->textures[i].roundup_h = true;
  2602. if (track->separate_cube)
  2603. for (face = 0; face < 5; face++) {
  2604. track->textures[i].cube_info[face].robj = NULL;
  2605. track->textures[i].cube_info[face].width = 16536;
  2606. track->textures[i].cube_info[face].height = 16536;
  2607. track->textures[i].cube_info[face].offset = 0;
  2608. }
  2609. }
  2610. }
  2611. int r100_ring_test(struct radeon_device *rdev)
  2612. {
  2613. uint32_t scratch;
  2614. uint32_t tmp = 0;
  2615. unsigned i;
  2616. int r;
  2617. r = radeon_scratch_get(rdev, &scratch);
  2618. if (r) {
  2619. DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
  2620. return r;
  2621. }
  2622. WREG32(scratch, 0xCAFEDEAD);
  2623. r = radeon_ring_lock(rdev, 2);
  2624. if (r) {
  2625. DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
  2626. radeon_scratch_free(rdev, scratch);
  2627. return r;
  2628. }
  2629. radeon_ring_write(rdev, PACKET0(scratch, 0));
  2630. radeon_ring_write(rdev, 0xDEADBEEF);
  2631. radeon_ring_unlock_commit(rdev);
  2632. for (i = 0; i < rdev->usec_timeout; i++) {
  2633. tmp = RREG32(scratch);
  2634. if (tmp == 0xDEADBEEF) {
  2635. break;
  2636. }
  2637. DRM_UDELAY(1);
  2638. }
  2639. if (i < rdev->usec_timeout) {
  2640. DRM_INFO("ring test succeeded in %d usecs\n", i);
  2641. } else {
  2642. DRM_ERROR("radeon: ring test failed (sracth(0x%04X)=0x%08X)\n",
  2643. scratch, tmp);
  2644. r = -EINVAL;
  2645. }
  2646. radeon_scratch_free(rdev, scratch);
  2647. return r;
  2648. }
  2649. void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
  2650. {
  2651. radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1));
  2652. radeon_ring_write(rdev, ib->gpu_addr);
  2653. radeon_ring_write(rdev, ib->length_dw);
  2654. }
  2655. int r100_ib_test(struct radeon_device *rdev)
  2656. {
  2657. struct radeon_ib *ib;
  2658. uint32_t scratch;
  2659. uint32_t tmp = 0;
  2660. unsigned i;
  2661. int r;
  2662. r = radeon_scratch_get(rdev, &scratch);
  2663. if (r) {
  2664. DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
  2665. return r;
  2666. }
  2667. WREG32(scratch, 0xCAFEDEAD);
  2668. r = radeon_ib_get(rdev, &ib);
  2669. if (r) {
  2670. return r;
  2671. }
  2672. ib->ptr[0] = PACKET0(scratch, 0);
  2673. ib->ptr[1] = 0xDEADBEEF;
  2674. ib->ptr[2] = PACKET2(0);
  2675. ib->ptr[3] = PACKET2(0);
  2676. ib->ptr[4] = PACKET2(0);
  2677. ib->ptr[5] = PACKET2(0);
  2678. ib->ptr[6] = PACKET2(0);
  2679. ib->ptr[7] = PACKET2(0);
  2680. ib->length_dw = 8;
  2681. r = radeon_ib_schedule(rdev, ib);
  2682. if (r) {
  2683. radeon_scratch_free(rdev, scratch);
  2684. radeon_ib_free(rdev, &ib);
  2685. return r;
  2686. }
  2687. r = radeon_fence_wait(ib->fence, false);
  2688. if (r) {
  2689. return r;
  2690. }
  2691. for (i = 0; i < rdev->usec_timeout; i++) {
  2692. tmp = RREG32(scratch);
  2693. if (tmp == 0xDEADBEEF) {
  2694. break;
  2695. }
  2696. DRM_UDELAY(1);
  2697. }
  2698. if (i < rdev->usec_timeout) {
  2699. DRM_INFO("ib test succeeded in %u usecs\n", i);
  2700. } else {
  2701. DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
  2702. scratch, tmp);
  2703. r = -EINVAL;
  2704. }
  2705. radeon_scratch_free(rdev, scratch);
  2706. radeon_ib_free(rdev, &ib);
  2707. return r;
  2708. }
  2709. void r100_ib_fini(struct radeon_device *rdev)
  2710. {
  2711. radeon_ib_pool_fini(rdev);
  2712. }
  2713. int r100_ib_init(struct radeon_device *rdev)
  2714. {
  2715. int r;
  2716. r = radeon_ib_pool_init(rdev);
  2717. if (r) {
  2718. dev_err(rdev->dev, "failled initializing IB pool (%d).\n", r);
  2719. r100_ib_fini(rdev);
  2720. return r;
  2721. }
  2722. r = r100_ib_test(rdev);
  2723. if (r) {
  2724. dev_err(rdev->dev, "failled testing IB (%d).\n", r);
  2725. r100_ib_fini(rdev);
  2726. return r;
  2727. }
  2728. return 0;
  2729. }
  2730. void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
  2731. {
  2732. /* Shutdown CP we shouldn't need to do that but better be safe than
  2733. * sorry
  2734. */
  2735. rdev->cp.ready = false;
  2736. WREG32(R_000740_CP_CSQ_CNTL, 0);
  2737. /* Save few CRTC registers */
  2738. save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
  2739. save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
  2740. save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
  2741. save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
  2742. if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
  2743. save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
  2744. save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
  2745. }
  2746. /* Disable VGA aperture access */
  2747. WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
  2748. /* Disable cursor, overlay, crtc */
  2749. WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
  2750. WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
  2751. S_000054_CRTC_DISPLAY_DIS(1));
  2752. WREG32(R_000050_CRTC_GEN_CNTL,
  2753. (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
  2754. S_000050_CRTC_DISP_REQ_EN_B(1));
  2755. WREG32(R_000420_OV0_SCALE_CNTL,
  2756. C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
  2757. WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
  2758. if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
  2759. WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
  2760. S_000360_CUR2_LOCK(1));
  2761. WREG32(R_0003F8_CRTC2_GEN_CNTL,
  2762. (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
  2763. S_0003F8_CRTC2_DISPLAY_DIS(1) |
  2764. S_0003F8_CRTC2_DISP_REQ_EN_B(1));
  2765. WREG32(R_000360_CUR2_OFFSET,
  2766. C_000360_CUR2_LOCK & save->CUR2_OFFSET);
  2767. }
  2768. }
  2769. void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
  2770. {
  2771. /* Update base address for crtc */
  2772. WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_location);
  2773. if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
  2774. WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR,
  2775. rdev->mc.vram_location);
  2776. }
  2777. /* Restore CRTC registers */
  2778. WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
  2779. WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
  2780. WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
  2781. if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
  2782. WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
  2783. }
  2784. }
  2785. void r100_vga_render_disable(struct radeon_device *rdev)
  2786. {
  2787. u32 tmp;
  2788. tmp = RREG8(R_0003C2_GENMO_WT);
  2789. WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
  2790. }
  2791. static void r100_debugfs(struct radeon_device *rdev)
  2792. {
  2793. int r;
  2794. r = r100_debugfs_mc_info_init(rdev);
  2795. if (r)
  2796. dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
  2797. }
  2798. static void r100_mc_program(struct radeon_device *rdev)
  2799. {
  2800. struct r100_mc_save save;
  2801. /* Stops all mc clients */
  2802. r100_mc_stop(rdev, &save);
  2803. if (rdev->flags & RADEON_IS_AGP) {
  2804. WREG32(R_00014C_MC_AGP_LOCATION,
  2805. S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
  2806. S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
  2807. WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
  2808. if (rdev->family > CHIP_RV200)
  2809. WREG32(R_00015C_AGP_BASE_2,
  2810. upper_32_bits(rdev->mc.agp_base) & 0xff);
  2811. } else {
  2812. WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
  2813. WREG32(R_000170_AGP_BASE, 0);
  2814. if (rdev->family > CHIP_RV200)
  2815. WREG32(R_00015C_AGP_BASE_2, 0);
  2816. }
  2817. /* Wait for mc idle */
  2818. if (r100_mc_wait_for_idle(rdev))
  2819. dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
  2820. /* Program MC, should be a 32bits limited address space */
  2821. WREG32(R_000148_MC_FB_LOCATION,
  2822. S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
  2823. S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
  2824. r100_mc_resume(rdev, &save);
  2825. }
  2826. void r100_clock_startup(struct radeon_device *rdev)
  2827. {
  2828. u32 tmp;
  2829. if (radeon_dynclks != -1 && radeon_dynclks)
  2830. radeon_legacy_set_clock_gating(rdev, 1);
  2831. /* We need to force on some of the block */
  2832. tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
  2833. tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
  2834. if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
  2835. tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
  2836. WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
  2837. }
  2838. static int r100_startup(struct radeon_device *rdev)
  2839. {
  2840. int r;
  2841. r100_mc_program(rdev);
  2842. /* Resume clock */
  2843. r100_clock_startup(rdev);
  2844. /* Initialize GPU configuration (# pipes, ...) */
  2845. r100_gpu_init(rdev);
  2846. /* Initialize GART (initialize after TTM so we can allocate
  2847. * memory through TTM but finalize after TTM) */
  2848. if (rdev->flags & RADEON_IS_PCI) {
  2849. r = r100_pci_gart_enable(rdev);
  2850. if (r)
  2851. return r;
  2852. }
  2853. /* Enable IRQ */
  2854. rdev->irq.sw_int = true;
  2855. r100_irq_set(rdev);
  2856. /* 1M ring buffer */
  2857. r = r100_cp_init(rdev, 1024 * 1024);
  2858. if (r) {
  2859. dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
  2860. return r;
  2861. }
  2862. r = r100_wb_init(rdev);
  2863. if (r)
  2864. dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
  2865. r = r100_ib_init(rdev);
  2866. if (r) {
  2867. dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
  2868. return r;
  2869. }
  2870. return 0;
  2871. }
  2872. int r100_resume(struct radeon_device *rdev)
  2873. {
  2874. /* Make sur GART are not working */
  2875. if (rdev->flags & RADEON_IS_PCI)
  2876. r100_pci_gart_disable(rdev);
  2877. /* Resume clock before doing reset */
  2878. r100_clock_startup(rdev);
  2879. /* Reset gpu before posting otherwise ATOM will enter infinite loop */
  2880. if (radeon_gpu_reset(rdev)) {
  2881. dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
  2882. RREG32(R_000E40_RBBM_STATUS),
  2883. RREG32(R_0007C0_CP_STAT));
  2884. }
  2885. /* post */
  2886. radeon_combios_asic_init(rdev->ddev);
  2887. /* Resume clock after posting */
  2888. r100_clock_startup(rdev);
  2889. return r100_startup(rdev);
  2890. }
  2891. int r100_suspend(struct radeon_device *rdev)
  2892. {
  2893. r100_cp_disable(rdev);
  2894. r100_wb_disable(rdev);
  2895. r100_irq_disable(rdev);
  2896. if (rdev->flags & RADEON_IS_PCI)
  2897. r100_pci_gart_disable(rdev);
  2898. return 0;
  2899. }
  2900. void r100_fini(struct radeon_device *rdev)
  2901. {
  2902. r100_suspend(rdev);
  2903. r100_cp_fini(rdev);
  2904. r100_wb_fini(rdev);
  2905. r100_ib_fini(rdev);
  2906. radeon_gem_fini(rdev);
  2907. if (rdev->flags & RADEON_IS_PCI)
  2908. r100_pci_gart_fini(rdev);
  2909. radeon_irq_kms_fini(rdev);
  2910. radeon_fence_driver_fini(rdev);
  2911. radeon_object_fini(rdev);
  2912. radeon_atombios_fini(rdev);
  2913. kfree(rdev->bios);
  2914. rdev->bios = NULL;
  2915. }
  2916. int r100_mc_init(struct radeon_device *rdev)
  2917. {
  2918. int r;
  2919. u32 tmp;
  2920. /* Setup GPU memory space */
  2921. rdev->mc.vram_location = 0xFFFFFFFFUL;
  2922. rdev->mc.gtt_location = 0xFFFFFFFFUL;
  2923. if (rdev->flags & RADEON_IS_IGP) {
  2924. tmp = G_00015C_MC_FB_START(RREG32(R_00015C_NB_TOM));
  2925. rdev->mc.vram_location = tmp << 16;
  2926. }
  2927. if (rdev->flags & RADEON_IS_AGP) {
  2928. r = radeon_agp_init(rdev);
  2929. if (r) {
  2930. printk(KERN_WARNING "[drm] Disabling AGP\n");
  2931. rdev->flags &= ~RADEON_IS_AGP;
  2932. rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
  2933. } else {
  2934. rdev->mc.gtt_location = rdev->mc.agp_base;
  2935. }
  2936. }
  2937. r = radeon_mc_setup(rdev);
  2938. if (r)
  2939. return r;
  2940. return 0;
  2941. }
  2942. int r100_init(struct radeon_device *rdev)
  2943. {
  2944. int r;
  2945. /* Register debugfs file specific to this group of asics */
  2946. r100_debugfs(rdev);
  2947. /* Disable VGA */
  2948. r100_vga_render_disable(rdev);
  2949. /* Initialize scratch registers */
  2950. radeon_scratch_init(rdev);
  2951. /* Initialize surface registers */
  2952. radeon_surface_init(rdev);
  2953. /* TODO: disable VGA need to use VGA request */
  2954. /* BIOS*/
  2955. if (!radeon_get_bios(rdev)) {
  2956. if (ASIC_IS_AVIVO(rdev))
  2957. return -EINVAL;
  2958. }
  2959. if (rdev->is_atom_bios) {
  2960. dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
  2961. return -EINVAL;
  2962. } else {
  2963. r = radeon_combios_init(rdev);
  2964. if (r)
  2965. return r;
  2966. }
  2967. /* Reset gpu before posting otherwise ATOM will enter infinite loop */
  2968. if (radeon_gpu_reset(rdev)) {
  2969. dev_warn(rdev->dev,
  2970. "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
  2971. RREG32(R_000E40_RBBM_STATUS),
  2972. RREG32(R_0007C0_CP_STAT));
  2973. }
  2974. /* check if cards are posted or not */
  2975. if (!radeon_card_posted(rdev) && rdev->bios) {
  2976. DRM_INFO("GPU not posted. posting now...\n");
  2977. radeon_combios_asic_init(rdev->ddev);
  2978. }
  2979. /* Set asic errata */
  2980. r100_errata(rdev);
  2981. /* Initialize clocks */
  2982. radeon_get_clock_info(rdev->ddev);
  2983. /* Get vram informations */
  2984. r100_vram_info(rdev);
  2985. /* Initialize memory controller (also test AGP) */
  2986. r = r100_mc_init(rdev);
  2987. if (r)
  2988. return r;
  2989. /* Fence driver */
  2990. r = radeon_fence_driver_init(rdev);
  2991. if (r)
  2992. return r;
  2993. r = radeon_irq_kms_init(rdev);
  2994. if (r)
  2995. return r;
  2996. /* Memory manager */
  2997. r = radeon_object_init(rdev);
  2998. if (r)
  2999. return r;
  3000. if (rdev->flags & RADEON_IS_PCI) {
  3001. r = r100_pci_gart_init(rdev);
  3002. if (r)
  3003. return r;
  3004. }
  3005. r100_set_safe_registers(rdev);
  3006. rdev->accel_working = true;
  3007. r = r100_startup(rdev);
  3008. if (r) {
  3009. /* Somethings want wront with the accel init stop accel */
  3010. dev_err(rdev->dev, "Disabling GPU acceleration\n");
  3011. r100_suspend(rdev);
  3012. r100_cp_fini(rdev);
  3013. r100_wb_fini(rdev);
  3014. r100_ib_fini(rdev);
  3015. if (rdev->flags & RADEON_IS_PCI)
  3016. r100_pci_gart_fini(rdev);
  3017. radeon_irq_kms_fini(rdev);
  3018. rdev->accel_working = false;
  3019. }
  3020. return 0;
  3021. }