gdth.c 198 KB

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  1. /************************************************************************
  2. * Linux driver for *
  3. * ICP vortex GmbH: GDT ISA/EISA/PCI Disk Array Controllers *
  4. * Intel Corporation: Storage RAID Controllers *
  5. * *
  6. * gdth.c *
  7. * Copyright (C) 1995-06 ICP vortex GmbH, Achim Leubner *
  8. * Copyright (C) 2002-04 Intel Corporation *
  9. * Copyright (C) 2003-06 Adaptec Inc. *
  10. * <achim_leubner@adaptec.com> *
  11. * *
  12. * Additions/Fixes: *
  13. * Boji Tony Kannanthanam <boji.t.kannanthanam@intel.com> *
  14. * Johannes Dinner <johannes_dinner@adaptec.com> *
  15. * *
  16. * This program is free software; you can redistribute it and/or modify *
  17. * it under the terms of the GNU General Public License as published *
  18. * by the Free Software Foundation; either version 2 of the License, *
  19. * or (at your option) any later version. *
  20. * *
  21. * This program is distributed in the hope that it will be useful, *
  22. * but WITHOUT ANY WARRANTY; without even the implied warranty of *
  23. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
  24. * GNU General Public License for more details. *
  25. * *
  26. * You should have received a copy of the GNU General Public License *
  27. * along with this kernel; if not, write to the Free Software *
  28. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. *
  29. * *
  30. * Linux kernel 2.4.x, 2.6.x supported *
  31. * *
  32. * $Log: gdth.c,v $
  33. * Revision 1.74 2006/04/10 13:44:47 achim
  34. * Community changes for 2.6.x
  35. * Kernel 2.2.x no longer supported
  36. * scsi_request interface removed, thanks to Christoph Hellwig
  37. *
  38. * Revision 1.73 2004/03/31 13:33:03 achim
  39. * Special command 0xfd implemented to detect 64-bit DMA support
  40. *
  41. * Revision 1.72 2004/03/17 08:56:04 achim
  42. * 64-bit DMA only enabled if FW >= x.43
  43. *
  44. * Revision 1.71 2004/03/05 15:51:29 achim
  45. * Screen service: separate message buffer, bugfixes
  46. *
  47. * Revision 1.70 2004/02/27 12:19:07 achim
  48. * Bugfix: Reset bit in config (0xfe) call removed
  49. *
  50. * Revision 1.69 2004/02/20 09:50:24 achim
  51. * Compatibility changes for kernels < 2.4.20
  52. * Bugfix screen service command size
  53. * pci_set_dma_mask() error handling added
  54. *
  55. * Revision 1.68 2004/02/19 15:46:54 achim
  56. * 64-bit DMA bugfixes
  57. * Drive size bugfix for drives > 1TB
  58. *
  59. * Revision 1.67 2004/01/14 13:11:57 achim
  60. * Tool access over /proc no longer supported
  61. * Bugfixes IOCTLs
  62. *
  63. * Revision 1.66 2003/12/19 15:04:06 achim
  64. * Bugfixes support for drives > 2TB
  65. *
  66. * Revision 1.65 2003/12/15 11:21:56 achim
  67. * 64-bit DMA support added
  68. * Support for drives > 2 TB implemented
  69. * Kernels 2.2.x, 2.4.x, 2.6.x supported
  70. *
  71. * Revision 1.64 2003/09/17 08:30:26 achim
  72. * EISA/ISA controller scan disabled
  73. * Command line switch probe_eisa_isa added
  74. *
  75. * Revision 1.63 2003/07/12 14:01:00 Daniele Bellucci <bellucda@tiscali.it>
  76. * Minor cleanups in gdth_ioctl.
  77. *
  78. * Revision 1.62 2003/02/27 15:01:59 achim
  79. * Dynamic DMA mapping implemented
  80. * New (character device) IOCTL interface added
  81. * Other controller related changes made
  82. *
  83. * Revision 1.61 2002/11/08 13:09:52 boji
  84. * Added support for XSCALE based RAID Controllers
  85. * Fixed SCREENSERVICE initialization in SMP cases
  86. * Added checks for gdth_polling before GDTH_HA_LOCK
  87. *
  88. * Revision 1.60 2002/02/05 09:35:22 achim
  89. * MODULE_LICENSE only if kernel >= 2.4.11
  90. *
  91. * Revision 1.59 2002/01/30 09:46:33 achim
  92. * Small changes
  93. *
  94. * Revision 1.58 2002/01/29 15:30:02 achim
  95. * Set default value of shared_access to Y
  96. * New status S_CACHE_RESERV for clustering added
  97. *
  98. * Revision 1.57 2001/08/21 11:16:35 achim
  99. * Bugfix free_irq()
  100. *
  101. * Revision 1.56 2001/08/09 11:19:39 achim
  102. * Scsi_Host_Template changes
  103. *
  104. * Revision 1.55 2001/08/09 10:11:28 achim
  105. * Command HOST_UNFREEZE_IO before cache service init.
  106. *
  107. * Revision 1.54 2001/07/20 13:48:12 achim
  108. * Expand: gdth_analyse_hdrive() removed
  109. *
  110. * Revision 1.53 2001/07/17 09:52:49 achim
  111. * Small OEM related change
  112. *
  113. * Revision 1.52 2001/06/19 15:06:20 achim
  114. * New host command GDT_UNFREEZE_IO added
  115. *
  116. * Revision 1.51 2001/05/22 06:42:37 achim
  117. * PCI: Subdevice ID added
  118. *
  119. * Revision 1.50 2001/05/17 13:42:16 achim
  120. * Support for Intel Storage RAID Controllers added
  121. *
  122. * Revision 1.50 2001/05/17 12:12:34 achim
  123. * Support for Intel Storage RAID Controllers added
  124. *
  125. * Revision 1.49 2001/03/15 15:07:17 achim
  126. * New __setup interface for boot command line options added
  127. *
  128. * Revision 1.48 2001/02/06 12:36:28 achim
  129. * Bugfix Cluster protocol
  130. *
  131. * Revision 1.47 2001/01/10 14:42:06 achim
  132. * New switch shared_access added
  133. *
  134. * Revision 1.46 2001/01/09 08:11:35 achim
  135. * gdth_command() removed
  136. * meaning of Scsi_Pointer members changed
  137. *
  138. * Revision 1.45 2000/11/16 12:02:24 achim
  139. * Changes for kernel 2.4
  140. *
  141. * Revision 1.44 2000/10/11 08:44:10 achim
  142. * Clustering changes: New flag media_changed added
  143. *
  144. * Revision 1.43 2000/09/20 12:59:01 achim
  145. * DPMEM remap functions for all PCI controller types implemented
  146. * Small changes for ia64 platform
  147. *
  148. * Revision 1.42 2000/07/20 09:04:50 achim
  149. * Small changes for kernel 2.4
  150. *
  151. * Revision 1.41 2000/07/04 14:11:11 achim
  152. * gdth_analyse_hdrive() added to rescan drives after online expansion
  153. *
  154. * Revision 1.40 2000/06/27 11:24:16 achim
  155. * Changes Clustering, Screenservice
  156. *
  157. * Revision 1.39 2000/06/15 13:09:04 achim
  158. * Changes for gdth_do_cmd()
  159. *
  160. * Revision 1.38 2000/06/15 12:08:43 achim
  161. * Bugfix gdth_sync_event(), service SCREENSERVICE
  162. * Data direction for command 0xc2 changed to DOU
  163. *
  164. * Revision 1.37 2000/05/25 13:50:10 achim
  165. * New driver parameter virt_ctr added
  166. *
  167. * Revision 1.36 2000/05/04 08:50:46 achim
  168. * Event buffer now in gdth_ha_str
  169. *
  170. * Revision 1.35 2000/03/03 10:44:08 achim
  171. * New event_string only valid for the RP controller family
  172. *
  173. * Revision 1.34 2000/03/02 14:55:29 achim
  174. * New mechanism for async. event handling implemented
  175. *
  176. * Revision 1.33 2000/02/21 15:37:37 achim
  177. * Bugfix Alpha platform + DPMEM above 4GB
  178. *
  179. * Revision 1.32 2000/02/14 16:17:37 achim
  180. * Bugfix sense_buffer[] + raw devices
  181. *
  182. * Revision 1.31 2000/02/10 10:29:00 achim
  183. * Delete sense_buffer[0], if command OK
  184. *
  185. * Revision 1.30 1999/11/02 13:42:39 achim
  186. * ARRAY_DRV_LIST2 implemented
  187. * Now 255 log. and 100 host drives supported
  188. *
  189. * Revision 1.29 1999/10/05 13:28:47 achim
  190. * GDT_CLUST_RESET added
  191. *
  192. * Revision 1.28 1999/08/12 13:44:54 achim
  193. * MOUNTALL removed
  194. * Cluster drives -> removeable drives
  195. *
  196. * Revision 1.27 1999/06/22 07:22:38 achim
  197. * Small changes
  198. *
  199. * Revision 1.26 1999/06/10 16:09:12 achim
  200. * Cluster Host Drive support: Bugfixes
  201. *
  202. * Revision 1.25 1999/06/01 16:03:56 achim
  203. * gdth_init_pci(): Manipulate config. space to start RP controller
  204. *
  205. * Revision 1.24 1999/05/26 11:53:06 achim
  206. * Cluster Host Drive support added
  207. *
  208. * Revision 1.23 1999/03/26 09:12:31 achim
  209. * Default value for hdr_channel set to 0
  210. *
  211. * Revision 1.22 1999/03/22 16:27:16 achim
  212. * Bugfix: gdth_store_event() must not be locked with GDTH_LOCK_HA()
  213. *
  214. * Revision 1.21 1999/03/16 13:40:34 achim
  215. * Problems with reserved drives solved
  216. * gdth_eh_bus_reset() implemented
  217. *
  218. * Revision 1.20 1999/03/10 09:08:13 achim
  219. * Bugfix: Corrections in gdth_direction_tab[] made
  220. * Bugfix: Increase command timeout (gdth_update_timeout()) NOT in gdth_putq()
  221. *
  222. * Revision 1.19 1999/03/05 14:38:16 achim
  223. * Bugfix: Heads/Sectors mapping for reserved devices possibly wrong
  224. * -> gdth_eval_mapping() implemented, changes in gdth_bios_param()
  225. * INIT_RETRIES set to 100s to avoid DEINIT-Timeout for controllers
  226. * with BIOS disabled and memory test set to Intensive
  227. * Enhanced /proc support
  228. *
  229. * Revision 1.18 1999/02/24 09:54:33 achim
  230. * Command line parameter hdr_channel implemented
  231. * Bugfix for EISA controllers + Linux 2.2.x
  232. *
  233. * Revision 1.17 1998/12/17 15:58:11 achim
  234. * Command line parameters implemented
  235. * Changes for Alpha platforms
  236. * PCI controller scan changed
  237. * SMP support improved (spin_lock_irqsave(),...)
  238. * New async. events, new scan/reserve commands included
  239. *
  240. * Revision 1.16 1998/09/28 16:08:46 achim
  241. * GDT_PCIMPR: DPMEM remapping, if required
  242. * mdelay() added
  243. *
  244. * Revision 1.15 1998/06/03 14:54:06 achim
  245. * gdth_delay(), gdth_flush() implemented
  246. * Bugfix: gdth_release() changed
  247. *
  248. * Revision 1.14 1998/05/22 10:01:17 achim
  249. * mj: pcibios_strerror() removed
  250. * Improved SMP support (if version >= 2.1.95)
  251. * gdth_halt(): halt_called flag added (if version < 2.1)
  252. *
  253. * Revision 1.13 1998/04/16 09:14:57 achim
  254. * Reserve drives (for raw service) implemented
  255. * New error handling code enabled
  256. * Get controller name from board_info() IOCTL
  257. * Final round of PCI device driver patches by Martin Mares
  258. *
  259. * Revision 1.12 1998/03/03 09:32:37 achim
  260. * Fibre channel controller support added
  261. *
  262. * Revision 1.11 1998/01/27 16:19:14 achim
  263. * SA_SHIRQ added
  264. * add_timer()/del_timer() instead of GDTH_TIMER
  265. * scsi_add_timer()/scsi_del_timer() instead of SCSI_TIMER
  266. * New error handling included
  267. *
  268. * Revision 1.10 1997/10/31 12:29:57 achim
  269. * Read heads/sectors from host drive
  270. *
  271. * Revision 1.9 1997/09/04 10:07:25 achim
  272. * IO-mapping with virt_to_bus(), gdth_readb(), gdth_writeb(), ...
  273. * register_reboot_notifier() to get a notify on shutown used
  274. *
  275. * Revision 1.8 1997/04/02 12:14:30 achim
  276. * Version 1.00 (see gdth.h), tested with kernel 2.0.29
  277. *
  278. * Revision 1.7 1997/03/12 13:33:37 achim
  279. * gdth_reset() changed, new async. events
  280. *
  281. * Revision 1.6 1997/03/04 14:01:11 achim
  282. * Shutdown routine gdth_halt() implemented
  283. *
  284. * Revision 1.5 1997/02/21 09:08:36 achim
  285. * New controller included (RP, RP1, RP2 series)
  286. * IOCTL interface implemented
  287. *
  288. * Revision 1.4 1996/07/05 12:48:55 achim
  289. * Function gdth_bios_param() implemented
  290. * New constant GDTH_MAXC_P_L inserted
  291. * GDT_WRITE_THR, GDT_EXT_INFO implemented
  292. * Function gdth_reset() changed
  293. *
  294. * Revision 1.3 1996/05/10 09:04:41 achim
  295. * Small changes for Linux 1.2.13
  296. *
  297. * Revision 1.2 1996/05/09 12:45:27 achim
  298. * Loadable module support implemented
  299. * /proc support corrections made
  300. *
  301. * Revision 1.1 1996/04/11 07:35:57 achim
  302. * Initial revision
  303. *
  304. ************************************************************************/
  305. /* All GDT Disk Array Controllers are fully supported by this driver.
  306. * This includes the PCI/EISA/ISA SCSI Disk Array Controllers and the
  307. * PCI Fibre Channel Disk Array Controllers. See gdth.h for a complete
  308. * list of all controller types.
  309. *
  310. * If you have one or more GDT3000/3020 EISA controllers with
  311. * controller BIOS disabled, you have to set the IRQ values with the
  312. * command line option "gdth=irq1,irq2,...", where the irq1,irq2,... are
  313. * the IRQ values for the EISA controllers.
  314. *
  315. * After the optional list of IRQ values, other possible
  316. * command line options are:
  317. * disable:Y disable driver
  318. * disable:N enable driver
  319. * reserve_mode:0 reserve no drives for the raw service
  320. * reserve_mode:1 reserve all not init., removable drives
  321. * reserve_mode:2 reserve all not init. drives
  322. * reserve_list:h,b,t,l,h,b,t,l,... reserve particular drive(s) with
  323. * h- controller no., b- channel no.,
  324. * t- target ID, l- LUN
  325. * reverse_scan:Y reverse scan order for PCI controllers
  326. * reverse_scan:N scan PCI controllers like BIOS
  327. * max_ids:x x - target ID count per channel (1..MAXID)
  328. * rescan:Y rescan all channels/IDs
  329. * rescan:N use all devices found until now
  330. * virt_ctr:Y map every channel to a virtual controller
  331. * virt_ctr:N use multi channel support
  332. * hdr_channel:x x - number of virtual bus for host drives
  333. * shared_access:Y disable driver reserve/release protocol to
  334. * access a shared resource from several nodes,
  335. * appropriate controller firmware required
  336. * shared_access:N enable driver reserve/release protocol
  337. * probe_eisa_isa:Y scan for EISA/ISA controllers
  338. * probe_eisa_isa:N do not scan for EISA/ISA controllers
  339. * force_dma32:Y use only 32 bit DMA mode
  340. * force_dma32:N use 64 bit DMA mode, if supported
  341. *
  342. * The default values are: "gdth=disable:N,reserve_mode:1,reverse_scan:N,
  343. * max_ids:127,rescan:N,virt_ctr:N,hdr_channel:0,
  344. * shared_access:Y,probe_eisa_isa:N,force_dma32:N".
  345. * Here is another example: "gdth=reserve_list:0,1,2,0,0,1,3,0,rescan:Y".
  346. *
  347. * When loading the gdth driver as a module, the same options are available.
  348. * You can set the IRQs with "IRQ=...". However, the syntax to specify the
  349. * options changes slightly. You must replace all ',' between options
  350. * with ' ' and all ':' with '=' and you must use
  351. * '1' in place of 'Y' and '0' in place of 'N'.
  352. *
  353. * Default: "modprobe gdth disable=0 reserve_mode=1 reverse_scan=0
  354. * max_ids=127 rescan=0 virt_ctr=0 hdr_channel=0 shared_access=0
  355. * probe_eisa_isa=0 force_dma32=0"
  356. * The other example: "modprobe gdth reserve_list=0,1,2,0,0,1,3,0 rescan=1".
  357. */
  358. /* The meaning of the Scsi_Pointer members in this driver is as follows:
  359. * ptr: Chaining
  360. * this_residual: Command priority
  361. * buffer: phys. DMA sense buffer
  362. * dma_handle: phys. DMA buffer (kernel >= 2.4.0)
  363. * buffers_residual: Timeout value
  364. * Status: Command status (gdth_do_cmd()), DMA mem. mappings
  365. * Message: Additional info (gdth_do_cmd()), DMA direction
  366. * have_data_in: Flag for gdth_wait_completion()
  367. * sent_command: Opcode special command
  368. * phase: Service/parameter/return code special command
  369. */
  370. /* interrupt coalescing */
  371. /* #define INT_COAL */
  372. /* statistics */
  373. #define GDTH_STATISTICS
  374. #include <linux/module.h>
  375. #include <linux/version.h>
  376. #include <linux/kernel.h>
  377. #include <linux/types.h>
  378. #include <linux/pci.h>
  379. #include <linux/string.h>
  380. #include <linux/ctype.h>
  381. #include <linux/ioport.h>
  382. #include <linux/delay.h>
  383. #include <linux/interrupt.h>
  384. #include <linux/in.h>
  385. #include <linux/proc_fs.h>
  386. #include <linux/time.h>
  387. #include <linux/timer.h>
  388. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,6)
  389. #include <linux/dma-mapping.h>
  390. #else
  391. #define DMA_32BIT_MASK 0x00000000ffffffffULL
  392. #define DMA_64BIT_MASK 0xffffffffffffffffULL
  393. #endif
  394. #ifdef GDTH_RTC
  395. #include <linux/mc146818rtc.h>
  396. #endif
  397. #include <linux/reboot.h>
  398. #include <asm/dma.h>
  399. #include <asm/system.h>
  400. #include <asm/io.h>
  401. #include <asm/uaccess.h>
  402. #include <linux/spinlock.h>
  403. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  404. #include <linux/blkdev.h>
  405. #else
  406. #include <linux/blk.h>
  407. #include "sd.h"
  408. #endif
  409. #include "scsi.h"
  410. #include <scsi/scsi_host.h>
  411. #include "gdth_kcompat.h"
  412. #include "gdth.h"
  413. static void gdth_delay(int milliseconds);
  414. static void gdth_eval_mapping(ulong32 size, ulong32 *cyls, int *heads, int *secs);
  415. static irqreturn_t gdth_interrupt(int irq, void *dev_id);
  416. static int gdth_sync_event(int hanum,int service,unchar index,Scsi_Cmnd *scp);
  417. static int gdth_async_event(int hanum);
  418. static void gdth_log_event(gdth_evt_data *dvr, char *buffer);
  419. static void gdth_putq(int hanum,Scsi_Cmnd *scp,unchar priority);
  420. static void gdth_next(int hanum);
  421. static int gdth_fill_raw_cmd(int hanum,Scsi_Cmnd *scp,unchar b);
  422. static int gdth_special_cmd(int hanum,Scsi_Cmnd *scp);
  423. static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, ushort source,
  424. ushort idx, gdth_evt_data *evt);
  425. static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr);
  426. static void gdth_readapp_event(gdth_ha_str *ha, unchar application,
  427. gdth_evt_str *estr);
  428. static void gdth_clear_events(void);
  429. static void gdth_copy_internal_data(int hanum,Scsi_Cmnd *scp,
  430. char *buffer,ushort count);
  431. static int gdth_internal_cache_cmd(int hanum,Scsi_Cmnd *scp);
  432. static int gdth_fill_cache_cmd(int hanum,Scsi_Cmnd *scp,ushort hdrive);
  433. static int gdth_search_pci(gdth_pci_str *pcistr);
  434. static void gdth_search_dev(gdth_pci_str *pcistr, ushort *cnt,
  435. ushort vendor, ushort dev);
  436. static void gdth_sort_pci(gdth_pci_str *pcistr, int cnt);
  437. static int gdth_init_pci(gdth_pci_str *pcistr,gdth_ha_str *ha);
  438. static void gdth_enable_int(int hanum);
  439. static int gdth_get_status(unchar *pIStatus,int irq);
  440. static int gdth_test_busy(int hanum);
  441. static int gdth_get_cmd_index(int hanum);
  442. static void gdth_release_event(int hanum);
  443. static int gdth_wait(int hanum,int index,ulong32 time);
  444. static int gdth_internal_cmd(int hanum,unchar service,ushort opcode,ulong32 p1,
  445. ulong64 p2,ulong64 p3);
  446. static int gdth_search_drives(int hanum);
  447. static int gdth_analyse_hdrive(int hanum, ushort hdrive);
  448. static const char *gdth_ctr_name(int hanum);
  449. static int gdth_open(struct inode *inode, struct file *filep);
  450. static int gdth_close(struct inode *inode, struct file *filep);
  451. static int gdth_ioctl(struct inode *inode, struct file *filep,
  452. unsigned int cmd, unsigned long arg);
  453. static void gdth_flush(int hanum);
  454. static int gdth_halt(struct notifier_block *nb, ulong event, void *buf);
  455. static int gdth_queuecommand(Scsi_Cmnd *scp,void (*done)(Scsi_Cmnd *));
  456. static void gdth_scsi_done(struct scsi_cmnd *scp);
  457. #ifdef CONFIG_ISA
  458. static int gdth_isa_probe_one(struct scsi_host_template *, ulong32);
  459. #endif
  460. #ifdef CONFIG_EISA
  461. static int gdth_eisa_probe_one(struct scsi_host_template *, ushort);
  462. #endif
  463. #ifdef DEBUG_GDTH
  464. static unchar DebugState = DEBUG_GDTH;
  465. #ifdef __SERIAL__
  466. #define MAX_SERBUF 160
  467. static void ser_init(void);
  468. static void ser_puts(char *str);
  469. static void ser_putc(char c);
  470. static int ser_printk(const char *fmt, ...);
  471. static char strbuf[MAX_SERBUF+1];
  472. #ifdef __COM2__
  473. #define COM_BASE 0x2f8
  474. #else
  475. #define COM_BASE 0x3f8
  476. #endif
  477. static void ser_init()
  478. {
  479. unsigned port=COM_BASE;
  480. outb(0x80,port+3);
  481. outb(0,port+1);
  482. /* 19200 Baud, if 9600: outb(12,port) */
  483. outb(6, port);
  484. outb(3,port+3);
  485. outb(0,port+1);
  486. /*
  487. ser_putc('I');
  488. ser_putc(' ');
  489. */
  490. }
  491. static void ser_puts(char *str)
  492. {
  493. char *ptr;
  494. ser_init();
  495. for (ptr=str;*ptr;++ptr)
  496. ser_putc(*ptr);
  497. }
  498. static void ser_putc(char c)
  499. {
  500. unsigned port=COM_BASE;
  501. while ((inb(port+5) & 0x20)==0);
  502. outb(c,port);
  503. if (c==0x0a)
  504. {
  505. while ((inb(port+5) & 0x20)==0);
  506. outb(0x0d,port);
  507. }
  508. }
  509. static int ser_printk(const char *fmt, ...)
  510. {
  511. va_list args;
  512. int i;
  513. va_start(args,fmt);
  514. i = vsprintf(strbuf,fmt,args);
  515. ser_puts(strbuf);
  516. va_end(args);
  517. return i;
  518. }
  519. #define TRACE(a) {if (DebugState==1) {ser_printk a;}}
  520. #define TRACE2(a) {if (DebugState==1 || DebugState==2) {ser_printk a;}}
  521. #define TRACE3(a) {if (DebugState!=0) {ser_printk a;}}
  522. #else /* !__SERIAL__ */
  523. #define TRACE(a) {if (DebugState==1) {printk a;}}
  524. #define TRACE2(a) {if (DebugState==1 || DebugState==2) {printk a;}}
  525. #define TRACE3(a) {if (DebugState!=0) {printk a;}}
  526. #endif
  527. #else /* !DEBUG */
  528. #define TRACE(a)
  529. #define TRACE2(a)
  530. #define TRACE3(a)
  531. #endif
  532. #ifdef GDTH_STATISTICS
  533. static ulong32 max_rq=0, max_index=0, max_sg=0;
  534. #ifdef INT_COAL
  535. static ulong32 max_int_coal=0;
  536. #endif
  537. static ulong32 act_ints=0, act_ios=0, act_stats=0, act_rq=0;
  538. static struct timer_list gdth_timer;
  539. #endif
  540. #define PTR2USHORT(a) (ushort)(ulong)(a)
  541. #define GDTOFFSOF(a,b) (size_t)&(((a*)0)->b)
  542. #define INDEX_OK(i,t) ((i)<ARRAY_SIZE(t))
  543. #define NUMDATA(a) ( (gdth_num_str *)((a)->hostdata))
  544. #define HADATA(a) (&((gdth_ext_str *)((a)->hostdata))->haext)
  545. #define CMDDATA(a) (&((gdth_ext_str *)((a)->hostdata))->cmdext)
  546. #define BUS_L2P(a,b) ((b)>(a)->virt_bus ? (b-1):(b))
  547. #define gdth_readb(addr) readb(addr)
  548. #define gdth_readw(addr) readw(addr)
  549. #define gdth_readl(addr) readl(addr)
  550. #define gdth_writeb(b,addr) writeb((b),(addr))
  551. #define gdth_writew(b,addr) writew((b),(addr))
  552. #define gdth_writel(b,addr) writel((b),(addr))
  553. #ifdef CONFIG_ISA
  554. static unchar gdth_drq_tab[4] = {5,6,7,7}; /* DRQ table */
  555. #endif
  556. #ifdef CONFIG_EISA
  557. static unchar gdth_irq_tab[6] = {0,10,11,12,14,0}; /* IRQ table */
  558. #endif
  559. static unchar gdth_polling; /* polling if TRUE */
  560. static unchar gdth_from_wait = FALSE; /* gdth_wait() */
  561. static int wait_index,wait_hanum; /* gdth_wait() */
  562. static int gdth_ctr_count = 0; /* controller count */
  563. static int gdth_ctr_vcount = 0; /* virt. ctr. count */
  564. static int gdth_ctr_released = 0; /* gdth_release() */
  565. static struct Scsi_Host *gdth_ctr_tab[MAXHA]; /* controller table */
  566. static struct Scsi_Host *gdth_ctr_vtab[MAXHA*MAXBUS]; /* virt. ctr. table */
  567. static unchar gdth_write_through = FALSE; /* write through */
  568. static gdth_evt_str ebuffer[MAX_EVENTS]; /* event buffer */
  569. static int elastidx;
  570. static int eoldidx;
  571. static int major;
  572. #define DIN 1 /* IN data direction */
  573. #define DOU 2 /* OUT data direction */
  574. #define DNO DIN /* no data transfer */
  575. #define DUN DIN /* unknown data direction */
  576. static unchar gdth_direction_tab[0x100] = {
  577. DNO,DNO,DIN,DIN,DOU,DIN,DIN,DOU,DIN,DUN,DOU,DOU,DUN,DUN,DUN,DIN,
  578. DNO,DIN,DIN,DOU,DIN,DOU,DNO,DNO,DOU,DNO,DIN,DNO,DIN,DOU,DNO,DUN,
  579. DIN,DUN,DIN,DUN,DOU,DIN,DUN,DUN,DIN,DIN,DOU,DNO,DUN,DIN,DOU,DOU,
  580. DOU,DOU,DOU,DNO,DIN,DNO,DNO,DIN,DOU,DOU,DOU,DOU,DIN,DOU,DIN,DOU,
  581. DOU,DOU,DIN,DIN,DIN,DNO,DUN,DNO,DNO,DNO,DUN,DNO,DOU,DIN,DUN,DUN,
  582. DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DIN,DUN,DUN,DUN,DUN,DUN,
  583. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  584. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  585. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
  586. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DIN,DUN,
  587. DUN,DUN,DUN,DUN,DUN,DNO,DNO,DUN,DIN,DNO,DOU,DUN,DNO,DUN,DOU,DOU,
  588. DOU,DOU,DOU,DNO,DUN,DIN,DOU,DIN,DIN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  589. DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  590. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,
  591. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DOU,DUN,DUN,DUN,DUN,DUN,
  592. DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN,DUN
  593. };
  594. /* LILO and modprobe/insmod parameters */
  595. /* IRQ list for GDT3000/3020 EISA controllers */
  596. static int irq[MAXHA] __initdata =
  597. {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  598. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
  599. /* disable driver flag */
  600. static int disable __initdata = 0;
  601. /* reserve flag */
  602. static int reserve_mode = 1;
  603. /* reserve list */
  604. static int reserve_list[MAX_RES_ARGS] =
  605. {0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  606. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,
  607. 0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff};
  608. /* scan order for PCI controllers */
  609. static int reverse_scan = 0;
  610. /* virtual channel for the host drives */
  611. static int hdr_channel = 0;
  612. /* max. IDs per channel */
  613. static int max_ids = MAXID;
  614. /* rescan all IDs */
  615. static int rescan = 0;
  616. /* map channels to virtual controllers */
  617. static int virt_ctr = 0;
  618. /* shared access */
  619. static int shared_access = 1;
  620. /* enable support for EISA and ISA controllers */
  621. static int probe_eisa_isa = 0;
  622. /* 64 bit DMA mode, support for drives > 2 TB, if force_dma32 = 0 */
  623. static int force_dma32 = 0;
  624. /* parameters for modprobe/insmod */
  625. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,11)
  626. module_param_array(irq, int, NULL, 0);
  627. module_param(disable, int, 0);
  628. module_param(reserve_mode, int, 0);
  629. module_param_array(reserve_list, int, NULL, 0);
  630. module_param(reverse_scan, int, 0);
  631. module_param(hdr_channel, int, 0);
  632. module_param(max_ids, int, 0);
  633. module_param(rescan, int, 0);
  634. module_param(virt_ctr, int, 0);
  635. module_param(shared_access, int, 0);
  636. module_param(probe_eisa_isa, int, 0);
  637. module_param(force_dma32, int, 0);
  638. #else
  639. MODULE_PARM(irq, "i");
  640. MODULE_PARM(disable, "i");
  641. MODULE_PARM(reserve_mode, "i");
  642. MODULE_PARM(reserve_list, "4-" __MODULE_STRING(MAX_RES_ARGS) "i");
  643. MODULE_PARM(reverse_scan, "i");
  644. MODULE_PARM(hdr_channel, "i");
  645. MODULE_PARM(max_ids, "i");
  646. MODULE_PARM(rescan, "i");
  647. MODULE_PARM(virt_ctr, "i");
  648. MODULE_PARM(shared_access, "i");
  649. MODULE_PARM(probe_eisa_isa, "i");
  650. MODULE_PARM(force_dma32, "i");
  651. #endif
  652. MODULE_AUTHOR("Achim Leubner");
  653. MODULE_LICENSE("GPL");
  654. /* ioctl interface */
  655. static const struct file_operations gdth_fops = {
  656. .ioctl = gdth_ioctl,
  657. .open = gdth_open,
  658. .release = gdth_close,
  659. };
  660. #define GDTH_MAGIC 0xc2e7c389 /* I got it from /dev/urandom */
  661. #define IS_GDTH_INTERNAL_CMD(scp) (scp->underflow == GDTH_MAGIC)
  662. #include "gdth_proc.h"
  663. #include "gdth_proc.c"
  664. /* notifier block to get a notify on system shutdown/halt/reboot */
  665. static struct notifier_block gdth_notifier = {
  666. gdth_halt, NULL, 0
  667. };
  668. static int notifier_disabled = 0;
  669. static void gdth_delay(int milliseconds)
  670. {
  671. if (milliseconds == 0) {
  672. udelay(1);
  673. } else {
  674. mdelay(milliseconds);
  675. }
  676. }
  677. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  678. static void gdth_scsi_done(struct scsi_cmnd *scp)
  679. {
  680. TRACE2(("gdth_scsi_done()\n"));
  681. if (IS_GDTH_INTERNAL_CMD(scp))
  682. complete((struct completion *)scp->request);
  683. else
  684. scp->scsi_done(scp);
  685. }
  686. int __gdth_execute(struct scsi_device *sdev, gdth_cmd_str *gdtcmd, char *cmnd,
  687. int timeout, u32 *info)
  688. {
  689. Scsi_Cmnd *scp;
  690. DECLARE_COMPLETION_ONSTACK(wait);
  691. int rval;
  692. scp = kzalloc(sizeof(*scp), GFP_KERNEL);
  693. if (!scp)
  694. return -ENOMEM;
  695. scp->device = sdev;
  696. /* use request field to save the ptr. to completion struct. */
  697. scp->request = (struct request *)&wait;
  698. scp->timeout_per_command = timeout*HZ;
  699. scp->request_buffer = gdtcmd;
  700. scp->cmd_len = 12;
  701. memcpy(scp->cmnd, cmnd, 12);
  702. scp->SCp.this_residual = IOCTL_PRI; /* priority */
  703. scp->underflow = GDTH_MAGIC;
  704. gdth_queuecommand(scp, NULL);
  705. wait_for_completion(&wait);
  706. rval = scp->SCp.Status;
  707. if (info)
  708. *info = scp->SCp.Message;
  709. kfree(scp);
  710. return rval;
  711. }
  712. #else
  713. static void gdth_scsi_done(Scsi_Cmnd *scp)
  714. {
  715. TRACE2(("gdth_scsi_done()\n"));
  716. scp->request.rq_status = RQ_SCSI_DONE;
  717. if (scp->request.waiting)
  718. complete(scp->request.waiting);
  719. }
  720. int __gdth_execute(struct scsi_device *sdev, gdth_cmd_str *gdtcmd, char *cmnd,
  721. int timeout, u32 *info)
  722. {
  723. Scsi_Cmnd *scp = scsi_allocate_device(sdev, 1, FALSE);
  724. unsigned bufflen = gdtcmd ? sizeof(gdth_cmd_str) : 0;
  725. DECLARE_COMPLETION_ONSTACK(wait);
  726. int rval;
  727. if (!scp)
  728. return -ENOMEM;
  729. scp->cmd_len = 12;
  730. scp->use_sg = 0;
  731. scp->SCp.this_residual = IOCTL_PRI; /* priority */
  732. scp->request.rq_status = RQ_SCSI_BUSY;
  733. scp->request.waiting = &wait;
  734. scsi_do_cmd(scp, cmnd, gdtcmd, bufflen, gdth_scsi_done, timeout*HZ, 1);
  735. wait_for_completion(&wait);
  736. rval = scp->SCp.Status;
  737. if (info)
  738. *info = scp->SCp.Message;
  739. scsi_release_command(scp);
  740. return rval;
  741. }
  742. #endif
  743. int gdth_execute(struct Scsi_Host *shost, gdth_cmd_str *gdtcmd, char *cmnd,
  744. int timeout, u32 *info)
  745. {
  746. struct scsi_device *sdev = scsi_get_host_dev(shost);
  747. int rval = __gdth_execute(sdev, gdtcmd, cmnd, timeout, info);
  748. scsi_free_host_dev(sdev);
  749. return rval;
  750. }
  751. static void gdth_eval_mapping(ulong32 size, ulong32 *cyls, int *heads, int *secs)
  752. {
  753. *cyls = size /HEADS/SECS;
  754. if (*cyls <= MAXCYLS) {
  755. *heads = HEADS;
  756. *secs = SECS;
  757. } else { /* too high for 64*32 */
  758. *cyls = size /MEDHEADS/MEDSECS;
  759. if (*cyls <= MAXCYLS) {
  760. *heads = MEDHEADS;
  761. *secs = MEDSECS;
  762. } else { /* too high for 127*63 */
  763. *cyls = size /BIGHEADS/BIGSECS;
  764. *heads = BIGHEADS;
  765. *secs = BIGSECS;
  766. }
  767. }
  768. }
  769. /* controller search and initialization functions */
  770. #ifdef CONFIG_EISA
  771. static int __init gdth_search_eisa(ushort eisa_adr)
  772. {
  773. ulong32 id;
  774. TRACE(("gdth_search_eisa() adr. %x\n",eisa_adr));
  775. id = inl(eisa_adr+ID0REG);
  776. if (id == GDT3A_ID || id == GDT3B_ID) { /* GDT3000A or GDT3000B */
  777. if ((inb(eisa_adr+EISAREG) & 8) == 0)
  778. return 0; /* not EISA configured */
  779. return 1;
  780. }
  781. if (id == GDT3_ID) /* GDT3000 */
  782. return 1;
  783. return 0;
  784. }
  785. #endif /* CONFIG_EISA */
  786. #ifdef CONFIG_ISA
  787. static int __init gdth_search_isa(ulong32 bios_adr)
  788. {
  789. void __iomem *addr;
  790. ulong32 id;
  791. TRACE(("gdth_search_isa() bios adr. %x\n",bios_adr));
  792. if ((addr = ioremap(bios_adr+BIOS_ID_OFFS, sizeof(ulong32))) != NULL) {
  793. id = gdth_readl(addr);
  794. iounmap(addr);
  795. if (id == GDT2_ID) /* GDT2000 */
  796. return 1;
  797. }
  798. return 0;
  799. }
  800. #endif /* CONFIG_ISA */
  801. static int __init gdth_search_pci(gdth_pci_str *pcistr)
  802. {
  803. ushort device, cnt;
  804. TRACE(("gdth_search_pci()\n"));
  805. cnt = 0;
  806. for (device = 0; device <= PCI_DEVICE_ID_VORTEX_GDT6555; ++device)
  807. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX, device);
  808. for (device = PCI_DEVICE_ID_VORTEX_GDT6x17RP;
  809. device <= PCI_DEVICE_ID_VORTEX_GDTMAXRP; ++device)
  810. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX, device);
  811. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX,
  812. PCI_DEVICE_ID_VORTEX_GDTNEWRX);
  813. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_VORTEX,
  814. PCI_DEVICE_ID_VORTEX_GDTNEWRX2);
  815. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_INTEL,
  816. PCI_DEVICE_ID_INTEL_SRC);
  817. gdth_search_dev(pcistr, &cnt, PCI_VENDOR_ID_INTEL,
  818. PCI_DEVICE_ID_INTEL_SRC_XSCALE);
  819. return cnt;
  820. }
  821. /* Vortex only makes RAID controllers.
  822. * We do not really want to specify all 550 ids here, so wildcard match.
  823. */
  824. static struct pci_device_id gdthtable[] __maybe_unused = {
  825. {PCI_VENDOR_ID_VORTEX,PCI_ANY_ID,PCI_ANY_ID, PCI_ANY_ID},
  826. {PCI_VENDOR_ID_INTEL,PCI_DEVICE_ID_INTEL_SRC,PCI_ANY_ID,PCI_ANY_ID},
  827. {PCI_VENDOR_ID_INTEL,PCI_DEVICE_ID_INTEL_SRC_XSCALE,PCI_ANY_ID,PCI_ANY_ID},
  828. {0}
  829. };
  830. MODULE_DEVICE_TABLE(pci,gdthtable);
  831. static void __init gdth_search_dev(gdth_pci_str *pcistr, ushort *cnt,
  832. ushort vendor, ushort device)
  833. {
  834. ulong base0, base1, base2;
  835. struct pci_dev *pdev;
  836. TRACE(("gdth_search_dev() cnt %d vendor %x device %x\n",
  837. *cnt, vendor, device));
  838. pdev = NULL;
  839. while ((pdev = pci_find_device(vendor, device, pdev))
  840. != NULL) {
  841. if (pci_enable_device(pdev))
  842. continue;
  843. if (*cnt >= MAXHA)
  844. return;
  845. /* GDT PCI controller found, resources are already in pdev */
  846. pcistr[*cnt].pdev = pdev;
  847. pcistr[*cnt].irq = pdev->irq;
  848. base0 = pci_resource_flags(pdev, 0);
  849. base1 = pci_resource_flags(pdev, 1);
  850. base2 = pci_resource_flags(pdev, 2);
  851. if (device <= PCI_DEVICE_ID_VORTEX_GDT6000B || /* GDT6000/B */
  852. device >= PCI_DEVICE_ID_VORTEX_GDT6x17RP) { /* MPR */
  853. if (!(base0 & IORESOURCE_MEM))
  854. continue;
  855. pcistr[*cnt].dpmem = pci_resource_start(pdev, 0);
  856. } else { /* GDT6110, GDT6120, .. */
  857. if (!(base0 & IORESOURCE_MEM) ||
  858. !(base2 & IORESOURCE_MEM) ||
  859. !(base1 & IORESOURCE_IO))
  860. continue;
  861. pcistr[*cnt].dpmem = pci_resource_start(pdev, 2);
  862. pcistr[*cnt].io_mm = pci_resource_start(pdev, 0);
  863. pcistr[*cnt].io = pci_resource_start(pdev, 1);
  864. }
  865. TRACE2(("Controller found at %d/%d, irq %d, dpmem 0x%lx\n",
  866. pcistr[*cnt].pdev->bus->number,
  867. PCI_SLOT(pcistr[*cnt].pdev->devfn),
  868. pcistr[*cnt].irq, pcistr[*cnt].dpmem));
  869. (*cnt)++;
  870. }
  871. }
  872. static void __init gdth_sort_pci(gdth_pci_str *pcistr, int cnt)
  873. {
  874. gdth_pci_str temp;
  875. int i, changed;
  876. TRACE(("gdth_sort_pci() cnt %d\n",cnt));
  877. if (cnt == 0)
  878. return;
  879. do {
  880. changed = FALSE;
  881. for (i = 0; i < cnt-1; ++i) {
  882. if (!reverse_scan) {
  883. if ((pcistr[i].pdev->bus->number > pcistr[i+1].pdev->bus->number) ||
  884. (pcistr[i].pdev->bus->number == pcistr[i+1].pdev->bus->number &&
  885. PCI_SLOT(pcistr[i].pdev->devfn) >
  886. PCI_SLOT(pcistr[i+1].pdev->devfn))) {
  887. temp = pcistr[i];
  888. pcistr[i] = pcistr[i+1];
  889. pcistr[i+1] = temp;
  890. changed = TRUE;
  891. }
  892. } else {
  893. if ((pcistr[i].pdev->bus->number < pcistr[i+1].pdev->bus->number) ||
  894. (pcistr[i].pdev->bus->number == pcistr[i+1].pdev->bus->number &&
  895. PCI_SLOT(pcistr[i].pdev->devfn) <
  896. PCI_SLOT(pcistr[i+1].pdev->devfn))) {
  897. temp = pcistr[i];
  898. pcistr[i] = pcistr[i+1];
  899. pcistr[i+1] = temp;
  900. changed = TRUE;
  901. }
  902. }
  903. }
  904. } while (changed);
  905. }
  906. #ifdef CONFIG_EISA
  907. static int __init gdth_init_eisa(ushort eisa_adr,gdth_ha_str *ha)
  908. {
  909. ulong32 retries,id;
  910. unchar prot_ver,eisacf,i,irq_found;
  911. TRACE(("gdth_init_eisa() adr. %x\n",eisa_adr));
  912. /* disable board interrupts, deinitialize services */
  913. outb(0xff,eisa_adr+EDOORREG);
  914. outb(0x00,eisa_adr+EDENABREG);
  915. outb(0x00,eisa_adr+EINTENABREG);
  916. outb(0xff,eisa_adr+LDOORREG);
  917. retries = INIT_RETRIES;
  918. gdth_delay(20);
  919. while (inb(eisa_adr+EDOORREG) != 0xff) {
  920. if (--retries == 0) {
  921. printk("GDT-EISA: Initialization error (DEINIT failed)\n");
  922. return 0;
  923. }
  924. gdth_delay(1);
  925. TRACE2(("wait for DEINIT: retries=%d\n",retries));
  926. }
  927. prot_ver = inb(eisa_adr+MAILBOXREG);
  928. outb(0xff,eisa_adr+EDOORREG);
  929. if (prot_ver != PROTOCOL_VERSION) {
  930. printk("GDT-EISA: Illegal protocol version\n");
  931. return 0;
  932. }
  933. ha->bmic = eisa_adr;
  934. ha->brd_phys = (ulong32)eisa_adr >> 12;
  935. outl(0,eisa_adr+MAILBOXREG);
  936. outl(0,eisa_adr+MAILBOXREG+4);
  937. outl(0,eisa_adr+MAILBOXREG+8);
  938. outl(0,eisa_adr+MAILBOXREG+12);
  939. /* detect IRQ */
  940. if ((id = inl(eisa_adr+ID0REG)) == GDT3_ID) {
  941. ha->oem_id = OEM_ID_ICP;
  942. ha->type = GDT_EISA;
  943. ha->stype = id;
  944. outl(1,eisa_adr+MAILBOXREG+8);
  945. outb(0xfe,eisa_adr+LDOORREG);
  946. retries = INIT_RETRIES;
  947. gdth_delay(20);
  948. while (inb(eisa_adr+EDOORREG) != 0xfe) {
  949. if (--retries == 0) {
  950. printk("GDT-EISA: Initialization error (get IRQ failed)\n");
  951. return 0;
  952. }
  953. gdth_delay(1);
  954. }
  955. ha->irq = inb(eisa_adr+MAILBOXREG);
  956. outb(0xff,eisa_adr+EDOORREG);
  957. TRACE2(("GDT3000/3020: IRQ=%d\n",ha->irq));
  958. /* check the result */
  959. if (ha->irq == 0) {
  960. TRACE2(("Unknown IRQ, use IRQ table from cmd line !\n"));
  961. for (i = 0, irq_found = FALSE;
  962. i < MAXHA && irq[i] != 0xff; ++i) {
  963. if (irq[i]==10 || irq[i]==11 || irq[i]==12 || irq[i]==14) {
  964. irq_found = TRUE;
  965. break;
  966. }
  967. }
  968. if (irq_found) {
  969. ha->irq = irq[i];
  970. irq[i] = 0;
  971. printk("GDT-EISA: Can not detect controller IRQ,\n");
  972. printk("Use IRQ setting from command line (IRQ = %d)\n",
  973. ha->irq);
  974. } else {
  975. printk("GDT-EISA: Initialization error (unknown IRQ), Enable\n");
  976. printk("the controller BIOS or use command line parameters\n");
  977. return 0;
  978. }
  979. }
  980. } else {
  981. eisacf = inb(eisa_adr+EISAREG) & 7;
  982. if (eisacf > 4) /* level triggered */
  983. eisacf -= 4;
  984. ha->irq = gdth_irq_tab[eisacf];
  985. ha->oem_id = OEM_ID_ICP;
  986. ha->type = GDT_EISA;
  987. ha->stype = id;
  988. }
  989. ha->dma64_support = 0;
  990. return 1;
  991. }
  992. #endif /* CONFIG_EISA */
  993. #ifdef CONFIG_ISA
  994. static int __init gdth_init_isa(ulong32 bios_adr,gdth_ha_str *ha)
  995. {
  996. register gdt2_dpram_str __iomem *dp2_ptr;
  997. int i;
  998. unchar irq_drq,prot_ver;
  999. ulong32 retries;
  1000. TRACE(("gdth_init_isa() bios adr. %x\n",bios_adr));
  1001. ha->brd = ioremap(bios_adr, sizeof(gdt2_dpram_str));
  1002. if (ha->brd == NULL) {
  1003. printk("GDT-ISA: Initialization error (DPMEM remap error)\n");
  1004. return 0;
  1005. }
  1006. dp2_ptr = ha->brd;
  1007. gdth_writeb(1, &dp2_ptr->io.memlock); /* switch off write protection */
  1008. /* reset interface area */
  1009. memset_io(&dp2_ptr->u, 0, sizeof(dp2_ptr->u));
  1010. if (gdth_readl(&dp2_ptr->u) != 0) {
  1011. printk("GDT-ISA: Initialization error (DPMEM write error)\n");
  1012. iounmap(ha->brd);
  1013. return 0;
  1014. }
  1015. /* disable board interrupts, read DRQ and IRQ */
  1016. gdth_writeb(0xff, &dp2_ptr->io.irqdel);
  1017. gdth_writeb(0x00, &dp2_ptr->io.irqen);
  1018. gdth_writeb(0x00, &dp2_ptr->u.ic.S_Status);
  1019. gdth_writeb(0x00, &dp2_ptr->u.ic.Cmd_Index);
  1020. irq_drq = gdth_readb(&dp2_ptr->io.rq);
  1021. for (i=0; i<3; ++i) {
  1022. if ((irq_drq & 1)==0)
  1023. break;
  1024. irq_drq >>= 1;
  1025. }
  1026. ha->drq = gdth_drq_tab[i];
  1027. irq_drq = gdth_readb(&dp2_ptr->io.rq) >> 3;
  1028. for (i=1; i<5; ++i) {
  1029. if ((irq_drq & 1)==0)
  1030. break;
  1031. irq_drq >>= 1;
  1032. }
  1033. ha->irq = gdth_irq_tab[i];
  1034. /* deinitialize services */
  1035. gdth_writel(bios_adr, &dp2_ptr->u.ic.S_Info[0]);
  1036. gdth_writeb(0xff, &dp2_ptr->u.ic.S_Cmd_Indx);
  1037. gdth_writeb(0, &dp2_ptr->io.event);
  1038. retries = INIT_RETRIES;
  1039. gdth_delay(20);
  1040. while (gdth_readb(&dp2_ptr->u.ic.S_Status) != 0xff) {
  1041. if (--retries == 0) {
  1042. printk("GDT-ISA: Initialization error (DEINIT failed)\n");
  1043. iounmap(ha->brd);
  1044. return 0;
  1045. }
  1046. gdth_delay(1);
  1047. }
  1048. prot_ver = (unchar)gdth_readl(&dp2_ptr->u.ic.S_Info[0]);
  1049. gdth_writeb(0, &dp2_ptr->u.ic.Status);
  1050. gdth_writeb(0xff, &dp2_ptr->io.irqdel);
  1051. if (prot_ver != PROTOCOL_VERSION) {
  1052. printk("GDT-ISA: Illegal protocol version\n");
  1053. iounmap(ha->brd);
  1054. return 0;
  1055. }
  1056. ha->oem_id = OEM_ID_ICP;
  1057. ha->type = GDT_ISA;
  1058. ha->ic_all_size = sizeof(dp2_ptr->u);
  1059. ha->stype= GDT2_ID;
  1060. ha->brd_phys = bios_adr >> 4;
  1061. /* special request to controller BIOS */
  1062. gdth_writel(0x00, &dp2_ptr->u.ic.S_Info[0]);
  1063. gdth_writel(0x00, &dp2_ptr->u.ic.S_Info[1]);
  1064. gdth_writel(0x01, &dp2_ptr->u.ic.S_Info[2]);
  1065. gdth_writel(0x00, &dp2_ptr->u.ic.S_Info[3]);
  1066. gdth_writeb(0xfe, &dp2_ptr->u.ic.S_Cmd_Indx);
  1067. gdth_writeb(0, &dp2_ptr->io.event);
  1068. retries = INIT_RETRIES;
  1069. gdth_delay(20);
  1070. while (gdth_readb(&dp2_ptr->u.ic.S_Status) != 0xfe) {
  1071. if (--retries == 0) {
  1072. printk("GDT-ISA: Initialization error\n");
  1073. iounmap(ha->brd);
  1074. return 0;
  1075. }
  1076. gdth_delay(1);
  1077. }
  1078. gdth_writeb(0, &dp2_ptr->u.ic.Status);
  1079. gdth_writeb(0xff, &dp2_ptr->io.irqdel);
  1080. ha->dma64_support = 0;
  1081. return 1;
  1082. }
  1083. #endif /* CONFIG_ISA */
  1084. static int __init gdth_init_pci(gdth_pci_str *pcistr,gdth_ha_str *ha)
  1085. {
  1086. register gdt6_dpram_str __iomem *dp6_ptr;
  1087. register gdt6c_dpram_str __iomem *dp6c_ptr;
  1088. register gdt6m_dpram_str __iomem *dp6m_ptr;
  1089. ulong32 retries;
  1090. unchar prot_ver;
  1091. ushort command;
  1092. int i, found = FALSE;
  1093. TRACE(("gdth_init_pci()\n"));
  1094. if (pcistr->pdev->vendor == PCI_VENDOR_ID_INTEL)
  1095. ha->oem_id = OEM_ID_INTEL;
  1096. else
  1097. ha->oem_id = OEM_ID_ICP;
  1098. ha->brd_phys = (pcistr->pdev->bus->number << 8) | (pcistr->pdev->devfn & 0xf8);
  1099. ha->stype = (ulong32)pcistr->pdev->device;
  1100. ha->irq = pcistr->irq;
  1101. ha->pdev = pcistr->pdev;
  1102. if (ha->pdev->device <= PCI_DEVICE_ID_VORTEX_GDT6000B) { /* GDT6000/B */
  1103. TRACE2(("init_pci() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
  1104. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6_dpram_str));
  1105. if (ha->brd == NULL) {
  1106. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1107. return 0;
  1108. }
  1109. /* check and reset interface area */
  1110. dp6_ptr = ha->brd;
  1111. gdth_writel(DPMEM_MAGIC, &dp6_ptr->u);
  1112. if (gdth_readl(&dp6_ptr->u) != DPMEM_MAGIC) {
  1113. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  1114. pcistr->dpmem);
  1115. found = FALSE;
  1116. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  1117. iounmap(ha->brd);
  1118. ha->brd = ioremap(i, sizeof(ushort));
  1119. if (ha->brd == NULL) {
  1120. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1121. return 0;
  1122. }
  1123. if (gdth_readw(ha->brd) != 0xffff) {
  1124. TRACE2(("init_pci_old() address 0x%x busy\n", i));
  1125. continue;
  1126. }
  1127. iounmap(ha->brd);
  1128. pci_write_config_dword(pcistr->pdev,
  1129. PCI_BASE_ADDRESS_0, i);
  1130. ha->brd = ioremap(i, sizeof(gdt6_dpram_str));
  1131. if (ha->brd == NULL) {
  1132. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1133. return 0;
  1134. }
  1135. dp6_ptr = ha->brd;
  1136. gdth_writel(DPMEM_MAGIC, &dp6_ptr->u);
  1137. if (gdth_readl(&dp6_ptr->u) == DPMEM_MAGIC) {
  1138. printk("GDT-PCI: Use free address at 0x%x\n", i);
  1139. found = TRUE;
  1140. break;
  1141. }
  1142. }
  1143. if (!found) {
  1144. printk("GDT-PCI: No free address found!\n");
  1145. iounmap(ha->brd);
  1146. return 0;
  1147. }
  1148. }
  1149. memset_io(&dp6_ptr->u, 0, sizeof(dp6_ptr->u));
  1150. if (gdth_readl(&dp6_ptr->u) != 0) {
  1151. printk("GDT-PCI: Initialization error (DPMEM write error)\n");
  1152. iounmap(ha->brd);
  1153. return 0;
  1154. }
  1155. /* disable board interrupts, deinit services */
  1156. gdth_writeb(0xff, &dp6_ptr->io.irqdel);
  1157. gdth_writeb(0x00, &dp6_ptr->io.irqen);
  1158. gdth_writeb(0x00, &dp6_ptr->u.ic.S_Status);
  1159. gdth_writeb(0x00, &dp6_ptr->u.ic.Cmd_Index);
  1160. gdth_writel(pcistr->dpmem, &dp6_ptr->u.ic.S_Info[0]);
  1161. gdth_writeb(0xff, &dp6_ptr->u.ic.S_Cmd_Indx);
  1162. gdth_writeb(0, &dp6_ptr->io.event);
  1163. retries = INIT_RETRIES;
  1164. gdth_delay(20);
  1165. while (gdth_readb(&dp6_ptr->u.ic.S_Status) != 0xff) {
  1166. if (--retries == 0) {
  1167. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  1168. iounmap(ha->brd);
  1169. return 0;
  1170. }
  1171. gdth_delay(1);
  1172. }
  1173. prot_ver = (unchar)gdth_readl(&dp6_ptr->u.ic.S_Info[0]);
  1174. gdth_writeb(0, &dp6_ptr->u.ic.S_Status);
  1175. gdth_writeb(0xff, &dp6_ptr->io.irqdel);
  1176. if (prot_ver != PROTOCOL_VERSION) {
  1177. printk("GDT-PCI: Illegal protocol version\n");
  1178. iounmap(ha->brd);
  1179. return 0;
  1180. }
  1181. ha->type = GDT_PCI;
  1182. ha->ic_all_size = sizeof(dp6_ptr->u);
  1183. /* special command to controller BIOS */
  1184. gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[0]);
  1185. gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[1]);
  1186. gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[2]);
  1187. gdth_writel(0x00, &dp6_ptr->u.ic.S_Info[3]);
  1188. gdth_writeb(0xfe, &dp6_ptr->u.ic.S_Cmd_Indx);
  1189. gdth_writeb(0, &dp6_ptr->io.event);
  1190. retries = INIT_RETRIES;
  1191. gdth_delay(20);
  1192. while (gdth_readb(&dp6_ptr->u.ic.S_Status) != 0xfe) {
  1193. if (--retries == 0) {
  1194. printk("GDT-PCI: Initialization error\n");
  1195. iounmap(ha->brd);
  1196. return 0;
  1197. }
  1198. gdth_delay(1);
  1199. }
  1200. gdth_writeb(0, &dp6_ptr->u.ic.S_Status);
  1201. gdth_writeb(0xff, &dp6_ptr->io.irqdel);
  1202. ha->dma64_support = 0;
  1203. } else if (ha->pdev->device <= PCI_DEVICE_ID_VORTEX_GDT6555) { /* GDT6110, ... */
  1204. ha->plx = (gdt6c_plx_regs *)pcistr->io;
  1205. TRACE2(("init_pci_new() dpmem %lx irq %d\n",
  1206. pcistr->dpmem,ha->irq));
  1207. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6c_dpram_str));
  1208. if (ha->brd == NULL) {
  1209. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1210. iounmap(ha->brd);
  1211. return 0;
  1212. }
  1213. /* check and reset interface area */
  1214. dp6c_ptr = ha->brd;
  1215. gdth_writel(DPMEM_MAGIC, &dp6c_ptr->u);
  1216. if (gdth_readl(&dp6c_ptr->u) != DPMEM_MAGIC) {
  1217. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  1218. pcistr->dpmem);
  1219. found = FALSE;
  1220. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  1221. iounmap(ha->brd);
  1222. ha->brd = ioremap(i, sizeof(ushort));
  1223. if (ha->brd == NULL) {
  1224. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1225. return 0;
  1226. }
  1227. if (gdth_readw(ha->brd) != 0xffff) {
  1228. TRACE2(("init_pci_plx() address 0x%x busy\n", i));
  1229. continue;
  1230. }
  1231. iounmap(ha->brd);
  1232. pci_write_config_dword(pcistr->pdev,
  1233. PCI_BASE_ADDRESS_2, i);
  1234. ha->brd = ioremap(i, sizeof(gdt6c_dpram_str));
  1235. if (ha->brd == NULL) {
  1236. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1237. return 0;
  1238. }
  1239. dp6c_ptr = ha->brd;
  1240. gdth_writel(DPMEM_MAGIC, &dp6c_ptr->u);
  1241. if (gdth_readl(&dp6c_ptr->u) == DPMEM_MAGIC) {
  1242. printk("GDT-PCI: Use free address at 0x%x\n", i);
  1243. found = TRUE;
  1244. break;
  1245. }
  1246. }
  1247. if (!found) {
  1248. printk("GDT-PCI: No free address found!\n");
  1249. iounmap(ha->brd);
  1250. return 0;
  1251. }
  1252. }
  1253. memset_io(&dp6c_ptr->u, 0, sizeof(dp6c_ptr->u));
  1254. if (gdth_readl(&dp6c_ptr->u) != 0) {
  1255. printk("GDT-PCI: Initialization error (DPMEM write error)\n");
  1256. iounmap(ha->brd);
  1257. return 0;
  1258. }
  1259. /* disable board interrupts, deinit services */
  1260. outb(0x00,PTR2USHORT(&ha->plx->control1));
  1261. outb(0xff,PTR2USHORT(&ha->plx->edoor_reg));
  1262. gdth_writeb(0x00, &dp6c_ptr->u.ic.S_Status);
  1263. gdth_writeb(0x00, &dp6c_ptr->u.ic.Cmd_Index);
  1264. gdth_writel(pcistr->dpmem, &dp6c_ptr->u.ic.S_Info[0]);
  1265. gdth_writeb(0xff, &dp6c_ptr->u.ic.S_Cmd_Indx);
  1266. outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
  1267. retries = INIT_RETRIES;
  1268. gdth_delay(20);
  1269. while (gdth_readb(&dp6c_ptr->u.ic.S_Status) != 0xff) {
  1270. if (--retries == 0) {
  1271. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  1272. iounmap(ha->brd);
  1273. return 0;
  1274. }
  1275. gdth_delay(1);
  1276. }
  1277. prot_ver = (unchar)gdth_readl(&dp6c_ptr->u.ic.S_Info[0]);
  1278. gdth_writeb(0, &dp6c_ptr->u.ic.Status);
  1279. if (prot_ver != PROTOCOL_VERSION) {
  1280. printk("GDT-PCI: Illegal protocol version\n");
  1281. iounmap(ha->brd);
  1282. return 0;
  1283. }
  1284. ha->type = GDT_PCINEW;
  1285. ha->ic_all_size = sizeof(dp6c_ptr->u);
  1286. /* special command to controller BIOS */
  1287. gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[0]);
  1288. gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[1]);
  1289. gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[2]);
  1290. gdth_writel(0x00, &dp6c_ptr->u.ic.S_Info[3]);
  1291. gdth_writeb(0xfe, &dp6c_ptr->u.ic.S_Cmd_Indx);
  1292. outb(1,PTR2USHORT(&ha->plx->ldoor_reg));
  1293. retries = INIT_RETRIES;
  1294. gdth_delay(20);
  1295. while (gdth_readb(&dp6c_ptr->u.ic.S_Status) != 0xfe) {
  1296. if (--retries == 0) {
  1297. printk("GDT-PCI: Initialization error\n");
  1298. iounmap(ha->brd);
  1299. return 0;
  1300. }
  1301. gdth_delay(1);
  1302. }
  1303. gdth_writeb(0, &dp6c_ptr->u.ic.S_Status);
  1304. ha->dma64_support = 0;
  1305. } else { /* MPR */
  1306. TRACE2(("init_pci_mpr() dpmem %lx irq %d\n",pcistr->dpmem,ha->irq));
  1307. ha->brd = ioremap(pcistr->dpmem, sizeof(gdt6m_dpram_str));
  1308. if (ha->brd == NULL) {
  1309. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1310. return 0;
  1311. }
  1312. /* manipulate config. space to enable DPMEM, start RP controller */
  1313. pci_read_config_word(pcistr->pdev, PCI_COMMAND, &command);
  1314. command |= 6;
  1315. pci_write_config_word(pcistr->pdev, PCI_COMMAND, command);
  1316. if (pci_resource_start(pcistr->pdev, 8) == 1UL)
  1317. pci_resource_start(pcistr->pdev, 8) = 0UL;
  1318. i = 0xFEFF0001UL;
  1319. pci_write_config_dword(pcistr->pdev, PCI_ROM_ADDRESS, i);
  1320. gdth_delay(1);
  1321. pci_write_config_dword(pcistr->pdev, PCI_ROM_ADDRESS,
  1322. pci_resource_start(pcistr->pdev, 8));
  1323. dp6m_ptr = ha->brd;
  1324. /* Ensure that it is safe to access the non HW portions of DPMEM.
  1325. * Aditional check needed for Xscale based RAID controllers */
  1326. while( ((int)gdth_readb(&dp6m_ptr->i960r.sema0_reg) ) & 3 )
  1327. gdth_delay(1);
  1328. /* check and reset interface area */
  1329. gdth_writel(DPMEM_MAGIC, &dp6m_ptr->u);
  1330. if (gdth_readl(&dp6m_ptr->u) != DPMEM_MAGIC) {
  1331. printk("GDT-PCI: Cannot access DPMEM at 0x%lx (shadowed?)\n",
  1332. pcistr->dpmem);
  1333. found = FALSE;
  1334. for (i = 0xC8000; i < 0xE8000; i += 0x4000) {
  1335. iounmap(ha->brd);
  1336. ha->brd = ioremap(i, sizeof(ushort));
  1337. if (ha->brd == NULL) {
  1338. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1339. return 0;
  1340. }
  1341. if (gdth_readw(ha->brd) != 0xffff) {
  1342. TRACE2(("init_pci_mpr() address 0x%x busy\n", i));
  1343. continue;
  1344. }
  1345. iounmap(ha->brd);
  1346. pci_write_config_dword(pcistr->pdev,
  1347. PCI_BASE_ADDRESS_0, i);
  1348. ha->brd = ioremap(i, sizeof(gdt6m_dpram_str));
  1349. if (ha->brd == NULL) {
  1350. printk("GDT-PCI: Initialization error (DPMEM remap error)\n");
  1351. return 0;
  1352. }
  1353. dp6m_ptr = ha->brd;
  1354. gdth_writel(DPMEM_MAGIC, &dp6m_ptr->u);
  1355. if (gdth_readl(&dp6m_ptr->u) == DPMEM_MAGIC) {
  1356. printk("GDT-PCI: Use free address at 0x%x\n", i);
  1357. found = TRUE;
  1358. break;
  1359. }
  1360. }
  1361. if (!found) {
  1362. printk("GDT-PCI: No free address found!\n");
  1363. iounmap(ha->brd);
  1364. return 0;
  1365. }
  1366. }
  1367. memset_io(&dp6m_ptr->u, 0, sizeof(dp6m_ptr->u));
  1368. /* disable board interrupts, deinit services */
  1369. gdth_writeb(gdth_readb(&dp6m_ptr->i960r.edoor_en_reg) | 4,
  1370. &dp6m_ptr->i960r.edoor_en_reg);
  1371. gdth_writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  1372. gdth_writeb(0x00, &dp6m_ptr->u.ic.S_Status);
  1373. gdth_writeb(0x00, &dp6m_ptr->u.ic.Cmd_Index);
  1374. gdth_writel(pcistr->dpmem, &dp6m_ptr->u.ic.S_Info[0]);
  1375. gdth_writeb(0xff, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1376. gdth_writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1377. retries = INIT_RETRIES;
  1378. gdth_delay(20);
  1379. while (gdth_readb(&dp6m_ptr->u.ic.S_Status) != 0xff) {
  1380. if (--retries == 0) {
  1381. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  1382. iounmap(ha->brd);
  1383. return 0;
  1384. }
  1385. gdth_delay(1);
  1386. }
  1387. prot_ver = (unchar)gdth_readl(&dp6m_ptr->u.ic.S_Info[0]);
  1388. gdth_writeb(0, &dp6m_ptr->u.ic.S_Status);
  1389. if (prot_ver != PROTOCOL_VERSION) {
  1390. printk("GDT-PCI: Illegal protocol version\n");
  1391. iounmap(ha->brd);
  1392. return 0;
  1393. }
  1394. ha->type = GDT_PCIMPR;
  1395. ha->ic_all_size = sizeof(dp6m_ptr->u);
  1396. /* special command to controller BIOS */
  1397. gdth_writel(0x00, &dp6m_ptr->u.ic.S_Info[0]);
  1398. gdth_writel(0x00, &dp6m_ptr->u.ic.S_Info[1]);
  1399. gdth_writel(0x00, &dp6m_ptr->u.ic.S_Info[2]);
  1400. gdth_writel(0x00, &dp6m_ptr->u.ic.S_Info[3]);
  1401. gdth_writeb(0xfe, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1402. gdth_writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1403. retries = INIT_RETRIES;
  1404. gdth_delay(20);
  1405. while (gdth_readb(&dp6m_ptr->u.ic.S_Status) != 0xfe) {
  1406. if (--retries == 0) {
  1407. printk("GDT-PCI: Initialization error\n");
  1408. iounmap(ha->brd);
  1409. return 0;
  1410. }
  1411. gdth_delay(1);
  1412. }
  1413. gdth_writeb(0, &dp6m_ptr->u.ic.S_Status);
  1414. /* read FW version to detect 64-bit DMA support */
  1415. gdth_writeb(0xfd, &dp6m_ptr->u.ic.S_Cmd_Indx);
  1416. gdth_writeb(1, &dp6m_ptr->i960r.ldoor_reg);
  1417. retries = INIT_RETRIES;
  1418. gdth_delay(20);
  1419. while (gdth_readb(&dp6m_ptr->u.ic.S_Status) != 0xfd) {
  1420. if (--retries == 0) {
  1421. printk("GDT-PCI: Initialization error (DEINIT failed)\n");
  1422. iounmap(ha->brd);
  1423. return 0;
  1424. }
  1425. gdth_delay(1);
  1426. }
  1427. prot_ver = (unchar)(gdth_readl(&dp6m_ptr->u.ic.S_Info[0]) >> 16);
  1428. gdth_writeb(0, &dp6m_ptr->u.ic.S_Status);
  1429. if (prot_ver < 0x2b) /* FW < x.43: no 64-bit DMA support */
  1430. ha->dma64_support = 0;
  1431. else
  1432. ha->dma64_support = 1;
  1433. }
  1434. return 1;
  1435. }
  1436. /* controller protocol functions */
  1437. static void __init gdth_enable_int(int hanum)
  1438. {
  1439. gdth_ha_str *ha;
  1440. ulong flags;
  1441. gdt2_dpram_str __iomem *dp2_ptr;
  1442. gdt6_dpram_str __iomem *dp6_ptr;
  1443. gdt6m_dpram_str __iomem *dp6m_ptr;
  1444. TRACE(("gdth_enable_int() hanum %d\n",hanum));
  1445. ha = HADATA(gdth_ctr_tab[hanum]);
  1446. spin_lock_irqsave(&ha->smp_lock, flags);
  1447. if (ha->type == GDT_EISA) {
  1448. outb(0xff, ha->bmic + EDOORREG);
  1449. outb(0xff, ha->bmic + EDENABREG);
  1450. outb(0x01, ha->bmic + EINTENABREG);
  1451. } else if (ha->type == GDT_ISA) {
  1452. dp2_ptr = ha->brd;
  1453. gdth_writeb(1, &dp2_ptr->io.irqdel);
  1454. gdth_writeb(0, &dp2_ptr->u.ic.Cmd_Index);
  1455. gdth_writeb(1, &dp2_ptr->io.irqen);
  1456. } else if (ha->type == GDT_PCI) {
  1457. dp6_ptr = ha->brd;
  1458. gdth_writeb(1, &dp6_ptr->io.irqdel);
  1459. gdth_writeb(0, &dp6_ptr->u.ic.Cmd_Index);
  1460. gdth_writeb(1, &dp6_ptr->io.irqen);
  1461. } else if (ha->type == GDT_PCINEW) {
  1462. outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
  1463. outb(0x03, PTR2USHORT(&ha->plx->control1));
  1464. } else if (ha->type == GDT_PCIMPR) {
  1465. dp6m_ptr = ha->brd;
  1466. gdth_writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  1467. gdth_writeb(gdth_readb(&dp6m_ptr->i960r.edoor_en_reg) & ~4,
  1468. &dp6m_ptr->i960r.edoor_en_reg);
  1469. }
  1470. spin_unlock_irqrestore(&ha->smp_lock, flags);
  1471. }
  1472. static int gdth_get_status(unchar *pIStatus,int irq)
  1473. {
  1474. register gdth_ha_str *ha;
  1475. int i;
  1476. TRACE(("gdth_get_status() irq %d ctr_count %d\n",
  1477. irq,gdth_ctr_count));
  1478. *pIStatus = 0;
  1479. for (i=0; i<gdth_ctr_count; ++i) {
  1480. ha = HADATA(gdth_ctr_tab[i]);
  1481. if (ha->irq != (unchar)irq) /* check IRQ */
  1482. continue;
  1483. if (ha->type == GDT_EISA)
  1484. *pIStatus = inb((ushort)ha->bmic + EDOORREG);
  1485. else if (ha->type == GDT_ISA)
  1486. *pIStatus =
  1487. gdth_readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
  1488. else if (ha->type == GDT_PCI)
  1489. *pIStatus =
  1490. gdth_readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Cmd_Index);
  1491. else if (ha->type == GDT_PCINEW)
  1492. *pIStatus = inb(PTR2USHORT(&ha->plx->edoor_reg));
  1493. else if (ha->type == GDT_PCIMPR)
  1494. *pIStatus =
  1495. gdth_readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.edoor_reg);
  1496. if (*pIStatus)
  1497. return i; /* board found */
  1498. }
  1499. return -1;
  1500. }
  1501. static int gdth_test_busy(int hanum)
  1502. {
  1503. register gdth_ha_str *ha;
  1504. register int gdtsema0 = 0;
  1505. TRACE(("gdth_test_busy() hanum %d\n",hanum));
  1506. ha = HADATA(gdth_ctr_tab[hanum]);
  1507. if (ha->type == GDT_EISA)
  1508. gdtsema0 = (int)inb(ha->bmic + SEMA0REG);
  1509. else if (ha->type == GDT_ISA)
  1510. gdtsema0 = (int)gdth_readb(&((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1511. else if (ha->type == GDT_PCI)
  1512. gdtsema0 = (int)gdth_readb(&((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1513. else if (ha->type == GDT_PCINEW)
  1514. gdtsema0 = (int)inb(PTR2USHORT(&ha->plx->sema0_reg));
  1515. else if (ha->type == GDT_PCIMPR)
  1516. gdtsema0 =
  1517. (int)gdth_readb(&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
  1518. return (gdtsema0 & 1);
  1519. }
  1520. static int gdth_get_cmd_index(int hanum)
  1521. {
  1522. register gdth_ha_str *ha;
  1523. int i;
  1524. TRACE(("gdth_get_cmd_index() hanum %d\n",hanum));
  1525. ha = HADATA(gdth_ctr_tab[hanum]);
  1526. for (i=0; i<GDTH_MAXCMDS; ++i) {
  1527. if (ha->cmd_tab[i].cmnd == UNUSED_CMND) {
  1528. ha->cmd_tab[i].cmnd = ha->pccb->RequestBuffer;
  1529. ha->cmd_tab[i].service = ha->pccb->Service;
  1530. ha->pccb->CommandIndex = (ulong32)i+2;
  1531. return (i+2);
  1532. }
  1533. }
  1534. return 0;
  1535. }
  1536. static void gdth_set_sema0(int hanum)
  1537. {
  1538. register gdth_ha_str *ha;
  1539. TRACE(("gdth_set_sema0() hanum %d\n",hanum));
  1540. ha = HADATA(gdth_ctr_tab[hanum]);
  1541. if (ha->type == GDT_EISA) {
  1542. outb(1, ha->bmic + SEMA0REG);
  1543. } else if (ha->type == GDT_ISA) {
  1544. gdth_writeb(1, &((gdt2_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1545. } else if (ha->type == GDT_PCI) {
  1546. gdth_writeb(1, &((gdt6_dpram_str __iomem *)ha->brd)->u.ic.Sema0);
  1547. } else if (ha->type == GDT_PCINEW) {
  1548. outb(1, PTR2USHORT(&ha->plx->sema0_reg));
  1549. } else if (ha->type == GDT_PCIMPR) {
  1550. gdth_writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.sema0_reg);
  1551. }
  1552. }
  1553. static void gdth_copy_command(int hanum)
  1554. {
  1555. register gdth_ha_str *ha;
  1556. register gdth_cmd_str *cmd_ptr;
  1557. register gdt6m_dpram_str __iomem *dp6m_ptr;
  1558. register gdt6c_dpram_str __iomem *dp6c_ptr;
  1559. gdt6_dpram_str __iomem *dp6_ptr;
  1560. gdt2_dpram_str __iomem *dp2_ptr;
  1561. ushort cp_count,dp_offset,cmd_no;
  1562. TRACE(("gdth_copy_command() hanum %d\n",hanum));
  1563. ha = HADATA(gdth_ctr_tab[hanum]);
  1564. cp_count = ha->cmd_len;
  1565. dp_offset= ha->cmd_offs_dpmem;
  1566. cmd_no = ha->cmd_cnt;
  1567. cmd_ptr = ha->pccb;
  1568. ++ha->cmd_cnt;
  1569. if (ha->type == GDT_EISA)
  1570. return; /* no DPMEM, no copy */
  1571. /* set cpcount dword aligned */
  1572. if (cp_count & 3)
  1573. cp_count += (4 - (cp_count & 3));
  1574. ha->cmd_offs_dpmem += cp_count;
  1575. /* set offset and service, copy command to DPMEM */
  1576. if (ha->type == GDT_ISA) {
  1577. dp2_ptr = ha->brd;
  1578. gdth_writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1579. &dp2_ptr->u.ic.comm_queue[cmd_no].offset);
  1580. gdth_writew((ushort)cmd_ptr->Service,
  1581. &dp2_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1582. memcpy_toio(&dp2_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1583. } else if (ha->type == GDT_PCI) {
  1584. dp6_ptr = ha->brd;
  1585. gdth_writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1586. &dp6_ptr->u.ic.comm_queue[cmd_no].offset);
  1587. gdth_writew((ushort)cmd_ptr->Service,
  1588. &dp6_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1589. memcpy_toio(&dp6_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1590. } else if (ha->type == GDT_PCINEW) {
  1591. dp6c_ptr = ha->brd;
  1592. gdth_writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1593. &dp6c_ptr->u.ic.comm_queue[cmd_no].offset);
  1594. gdth_writew((ushort)cmd_ptr->Service,
  1595. &dp6c_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1596. memcpy_toio(&dp6c_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1597. } else if (ha->type == GDT_PCIMPR) {
  1598. dp6m_ptr = ha->brd;
  1599. gdth_writew(dp_offset + DPMEM_COMMAND_OFFSET,
  1600. &dp6m_ptr->u.ic.comm_queue[cmd_no].offset);
  1601. gdth_writew((ushort)cmd_ptr->Service,
  1602. &dp6m_ptr->u.ic.comm_queue[cmd_no].serv_id);
  1603. memcpy_toio(&dp6m_ptr->u.ic.gdt_dpr_cmd[dp_offset],cmd_ptr,cp_count);
  1604. }
  1605. }
  1606. static void gdth_release_event(int hanum)
  1607. {
  1608. register gdth_ha_str *ha;
  1609. TRACE(("gdth_release_event() hanum %d\n",hanum));
  1610. ha = HADATA(gdth_ctr_tab[hanum]);
  1611. #ifdef GDTH_STATISTICS
  1612. {
  1613. ulong32 i,j;
  1614. for (i=0,j=0; j<GDTH_MAXCMDS; ++j) {
  1615. if (ha->cmd_tab[j].cmnd != UNUSED_CMND)
  1616. ++i;
  1617. }
  1618. if (max_index < i) {
  1619. max_index = i;
  1620. TRACE3(("GDT: max_index = %d\n",(ushort)i));
  1621. }
  1622. }
  1623. #endif
  1624. if (ha->pccb->OpCode == GDT_INIT)
  1625. ha->pccb->Service |= 0x80;
  1626. if (ha->type == GDT_EISA) {
  1627. if (ha->pccb->OpCode == GDT_INIT) /* store DMA buffer */
  1628. outl(ha->ccb_phys, ha->bmic + MAILBOXREG);
  1629. outb(ha->pccb->Service, ha->bmic + LDOORREG);
  1630. } else if (ha->type == GDT_ISA) {
  1631. gdth_writeb(0, &((gdt2_dpram_str __iomem *)ha->brd)->io.event);
  1632. } else if (ha->type == GDT_PCI) {
  1633. gdth_writeb(0, &((gdt6_dpram_str __iomem *)ha->brd)->io.event);
  1634. } else if (ha->type == GDT_PCINEW) {
  1635. outb(1, PTR2USHORT(&ha->plx->ldoor_reg));
  1636. } else if (ha->type == GDT_PCIMPR) {
  1637. gdth_writeb(1, &((gdt6m_dpram_str __iomem *)ha->brd)->i960r.ldoor_reg);
  1638. }
  1639. }
  1640. static int gdth_wait(int hanum,int index,ulong32 time)
  1641. {
  1642. gdth_ha_str *ha;
  1643. int answer_found = FALSE;
  1644. TRACE(("gdth_wait() hanum %d index %d time %d\n",hanum,index,time));
  1645. ha = HADATA(gdth_ctr_tab[hanum]);
  1646. if (index == 0)
  1647. return 1; /* no wait required */
  1648. gdth_from_wait = TRUE;
  1649. do {
  1650. gdth_interrupt((int)ha->irq,ha);
  1651. if (wait_hanum==hanum && wait_index==index) {
  1652. answer_found = TRUE;
  1653. break;
  1654. }
  1655. gdth_delay(1);
  1656. } while (--time);
  1657. gdth_from_wait = FALSE;
  1658. while (gdth_test_busy(hanum))
  1659. gdth_delay(0);
  1660. return (answer_found);
  1661. }
  1662. static int gdth_internal_cmd(int hanum,unchar service,ushort opcode,ulong32 p1,
  1663. ulong64 p2,ulong64 p3)
  1664. {
  1665. register gdth_ha_str *ha;
  1666. register gdth_cmd_str *cmd_ptr;
  1667. int retries,index;
  1668. TRACE2(("gdth_internal_cmd() service %d opcode %d\n",service,opcode));
  1669. ha = HADATA(gdth_ctr_tab[hanum]);
  1670. cmd_ptr = ha->pccb;
  1671. memset((char*)cmd_ptr,0,sizeof(gdth_cmd_str));
  1672. /* make command */
  1673. for (retries = INIT_RETRIES;;) {
  1674. cmd_ptr->Service = service;
  1675. cmd_ptr->RequestBuffer = INTERNAL_CMND;
  1676. if (!(index=gdth_get_cmd_index(hanum))) {
  1677. TRACE(("GDT: No free command index found\n"));
  1678. return 0;
  1679. }
  1680. gdth_set_sema0(hanum);
  1681. cmd_ptr->OpCode = opcode;
  1682. cmd_ptr->BoardNode = LOCALBOARD;
  1683. if (service == CACHESERVICE) {
  1684. if (opcode == GDT_IOCTL) {
  1685. cmd_ptr->u.ioctl.subfunc = p1;
  1686. cmd_ptr->u.ioctl.channel = (ulong32)p2;
  1687. cmd_ptr->u.ioctl.param_size = (ushort)p3;
  1688. cmd_ptr->u.ioctl.p_param = ha->scratch_phys;
  1689. } else {
  1690. if (ha->cache_feat & GDT_64BIT) {
  1691. cmd_ptr->u.cache64.DeviceNo = (ushort)p1;
  1692. cmd_ptr->u.cache64.BlockNo = p2;
  1693. } else {
  1694. cmd_ptr->u.cache.DeviceNo = (ushort)p1;
  1695. cmd_ptr->u.cache.BlockNo = (ulong32)p2;
  1696. }
  1697. }
  1698. } else if (service == SCSIRAWSERVICE) {
  1699. if (ha->raw_feat & GDT_64BIT) {
  1700. cmd_ptr->u.raw64.direction = p1;
  1701. cmd_ptr->u.raw64.bus = (unchar)p2;
  1702. cmd_ptr->u.raw64.target = (unchar)p3;
  1703. cmd_ptr->u.raw64.lun = (unchar)(p3 >> 8);
  1704. } else {
  1705. cmd_ptr->u.raw.direction = p1;
  1706. cmd_ptr->u.raw.bus = (unchar)p2;
  1707. cmd_ptr->u.raw.target = (unchar)p3;
  1708. cmd_ptr->u.raw.lun = (unchar)(p3 >> 8);
  1709. }
  1710. } else if (service == SCREENSERVICE) {
  1711. if (opcode == GDT_REALTIME) {
  1712. *(ulong32 *)&cmd_ptr->u.screen.su.data[0] = p1;
  1713. *(ulong32 *)&cmd_ptr->u.screen.su.data[4] = (ulong32)p2;
  1714. *(ulong32 *)&cmd_ptr->u.screen.su.data[8] = (ulong32)p3;
  1715. }
  1716. }
  1717. ha->cmd_len = sizeof(gdth_cmd_str);
  1718. ha->cmd_offs_dpmem = 0;
  1719. ha->cmd_cnt = 0;
  1720. gdth_copy_command(hanum);
  1721. gdth_release_event(hanum);
  1722. gdth_delay(20);
  1723. if (!gdth_wait(hanum,index,INIT_TIMEOUT)) {
  1724. printk("GDT: Initialization error (timeout service %d)\n",service);
  1725. return 0;
  1726. }
  1727. if (ha->status != S_BSY || --retries == 0)
  1728. break;
  1729. gdth_delay(1);
  1730. }
  1731. return (ha->status != S_OK ? 0:1);
  1732. }
  1733. /* search for devices */
  1734. static int __init gdth_search_drives(int hanum)
  1735. {
  1736. register gdth_ha_str *ha;
  1737. ushort cdev_cnt, i;
  1738. int ok;
  1739. ulong32 bus_no, drv_cnt, drv_no, j;
  1740. gdth_getch_str *chn;
  1741. gdth_drlist_str *drl;
  1742. gdth_iochan_str *ioc;
  1743. gdth_raw_iochan_str *iocr;
  1744. gdth_arcdl_str *alst;
  1745. gdth_alist_str *alst2;
  1746. gdth_oem_str_ioctl *oemstr;
  1747. #ifdef INT_COAL
  1748. gdth_perf_modes *pmod;
  1749. #endif
  1750. #ifdef GDTH_RTC
  1751. unchar rtc[12];
  1752. ulong flags;
  1753. #endif
  1754. TRACE(("gdth_search_drives() hanum %d\n",hanum));
  1755. ha = HADATA(gdth_ctr_tab[hanum]);
  1756. ok = 0;
  1757. /* initialize controller services, at first: screen service */
  1758. ha->screen_feat = 0;
  1759. if (!force_dma32) {
  1760. ok = gdth_internal_cmd(hanum,SCREENSERVICE,GDT_X_INIT_SCR,0,0,0);
  1761. if (ok)
  1762. ha->screen_feat = GDT_64BIT;
  1763. }
  1764. if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
  1765. ok = gdth_internal_cmd(hanum,SCREENSERVICE,GDT_INIT,0,0,0);
  1766. if (!ok) {
  1767. printk("GDT-HA %d: Initialization error screen service (code %d)\n",
  1768. hanum, ha->status);
  1769. return 0;
  1770. }
  1771. TRACE2(("gdth_search_drives(): SCREENSERVICE initialized\n"));
  1772. #ifdef GDTH_RTC
  1773. /* read realtime clock info, send to controller */
  1774. /* 1. wait for the falling edge of update flag */
  1775. spin_lock_irqsave(&rtc_lock, flags);
  1776. for (j = 0; j < 1000000; ++j)
  1777. if (CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP)
  1778. break;
  1779. for (j = 0; j < 1000000; ++j)
  1780. if (!(CMOS_READ(RTC_FREQ_SELECT) & RTC_UIP))
  1781. break;
  1782. /* 2. read info */
  1783. do {
  1784. for (j = 0; j < 12; ++j)
  1785. rtc[j] = CMOS_READ(j);
  1786. } while (rtc[0] != CMOS_READ(0));
  1787. spin_unlock_irqrestore(&rtc_lock, flags);
  1788. TRACE2(("gdth_search_drives(): RTC: %x/%x/%x\n",*(ulong32 *)&rtc[0],
  1789. *(ulong32 *)&rtc[4], *(ulong32 *)&rtc[8]));
  1790. /* 3. send to controller firmware */
  1791. gdth_internal_cmd(hanum,SCREENSERVICE,GDT_REALTIME, *(ulong32 *)&rtc[0],
  1792. *(ulong32 *)&rtc[4], *(ulong32 *)&rtc[8]);
  1793. #endif
  1794. /* unfreeze all IOs */
  1795. gdth_internal_cmd(hanum,CACHESERVICE,GDT_UNFREEZE_IO,0,0,0);
  1796. /* initialize cache service */
  1797. ha->cache_feat = 0;
  1798. if (!force_dma32) {
  1799. ok = gdth_internal_cmd(hanum,CACHESERVICE,GDT_X_INIT_HOST,LINUX_OS,0,0);
  1800. if (ok)
  1801. ha->cache_feat = GDT_64BIT;
  1802. }
  1803. if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
  1804. ok = gdth_internal_cmd(hanum,CACHESERVICE,GDT_INIT,LINUX_OS,0,0);
  1805. if (!ok) {
  1806. printk("GDT-HA %d: Initialization error cache service (code %d)\n",
  1807. hanum, ha->status);
  1808. return 0;
  1809. }
  1810. TRACE2(("gdth_search_drives(): CACHESERVICE initialized\n"));
  1811. cdev_cnt = (ushort)ha->info;
  1812. ha->fw_vers = ha->service;
  1813. #ifdef INT_COAL
  1814. if (ha->type == GDT_PCIMPR) {
  1815. /* set perf. modes */
  1816. pmod = (gdth_perf_modes *)ha->pscratch;
  1817. pmod->version = 1;
  1818. pmod->st_mode = 1; /* enable one status buffer */
  1819. *((ulong64 *)&pmod->st_buff_addr1) = ha->coal_stat_phys;
  1820. pmod->st_buff_indx1 = COALINDEX;
  1821. pmod->st_buff_addr2 = 0;
  1822. pmod->st_buff_u_addr2 = 0;
  1823. pmod->st_buff_indx2 = 0;
  1824. pmod->st_buff_size = sizeof(gdth_coal_status) * MAXOFFSETS;
  1825. pmod->cmd_mode = 0; // disable all cmd buffers
  1826. pmod->cmd_buff_addr1 = 0;
  1827. pmod->cmd_buff_u_addr1 = 0;
  1828. pmod->cmd_buff_indx1 = 0;
  1829. pmod->cmd_buff_addr2 = 0;
  1830. pmod->cmd_buff_u_addr2 = 0;
  1831. pmod->cmd_buff_indx2 = 0;
  1832. pmod->cmd_buff_size = 0;
  1833. pmod->reserved1 = 0;
  1834. pmod->reserved2 = 0;
  1835. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,SET_PERF_MODES,
  1836. INVALID_CHANNEL,sizeof(gdth_perf_modes))) {
  1837. printk("GDT-HA %d: Interrupt coalescing activated\n", hanum);
  1838. }
  1839. }
  1840. #endif
  1841. /* detect number of buses - try new IOCTL */
  1842. iocr = (gdth_raw_iochan_str *)ha->pscratch;
  1843. iocr->hdr.version = 0xffffffff;
  1844. iocr->hdr.list_entries = MAXBUS;
  1845. iocr->hdr.first_chan = 0;
  1846. iocr->hdr.last_chan = MAXBUS-1;
  1847. iocr->hdr.list_offset = GDTOFFSOF(gdth_raw_iochan_str, list[0]);
  1848. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,IOCHAN_RAW_DESC,
  1849. INVALID_CHANNEL,sizeof(gdth_raw_iochan_str))) {
  1850. TRACE2(("IOCHAN_RAW_DESC supported!\n"));
  1851. ha->bus_cnt = iocr->hdr.chan_count;
  1852. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1853. if (iocr->list[bus_no].proc_id < MAXID)
  1854. ha->bus_id[bus_no] = iocr->list[bus_no].proc_id;
  1855. else
  1856. ha->bus_id[bus_no] = 0xff;
  1857. }
  1858. } else {
  1859. /* old method */
  1860. chn = (gdth_getch_str *)ha->pscratch;
  1861. for (bus_no = 0; bus_no < MAXBUS; ++bus_no) {
  1862. chn->channel_no = bus_no;
  1863. if (!gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
  1864. SCSI_CHAN_CNT | L_CTRL_PATTERN,
  1865. IO_CHANNEL | INVALID_CHANNEL,
  1866. sizeof(gdth_getch_str))) {
  1867. if (bus_no == 0) {
  1868. printk("GDT-HA %d: Error detecting channel count (0x%x)\n",
  1869. hanum, ha->status);
  1870. return 0;
  1871. }
  1872. break;
  1873. }
  1874. if (chn->siop_id < MAXID)
  1875. ha->bus_id[bus_no] = chn->siop_id;
  1876. else
  1877. ha->bus_id[bus_no] = 0xff;
  1878. }
  1879. ha->bus_cnt = (unchar)bus_no;
  1880. }
  1881. TRACE2(("gdth_search_drives() %d channels\n",ha->bus_cnt));
  1882. /* read cache configuration */
  1883. if (!gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,CACHE_INFO,
  1884. INVALID_CHANNEL,sizeof(gdth_cinfo_str))) {
  1885. printk("GDT-HA %d: Initialization error cache service (code %d)\n",
  1886. hanum, ha->status);
  1887. return 0;
  1888. }
  1889. ha->cpar = ((gdth_cinfo_str *)ha->pscratch)->cpar;
  1890. TRACE2(("gdth_search_drives() cinfo: vs %x sta %d str %d dw %d b %d\n",
  1891. ha->cpar.version,ha->cpar.state,ha->cpar.strategy,
  1892. ha->cpar.write_back,ha->cpar.block_size));
  1893. /* read board info and features */
  1894. ha->more_proc = FALSE;
  1895. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,BOARD_INFO,
  1896. INVALID_CHANNEL,sizeof(gdth_binfo_str))) {
  1897. memcpy(&ha->binfo, (gdth_binfo_str *)ha->pscratch,
  1898. sizeof(gdth_binfo_str));
  1899. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,BOARD_FEATURES,
  1900. INVALID_CHANNEL,sizeof(gdth_bfeat_str))) {
  1901. TRACE2(("BOARD_INFO/BOARD_FEATURES supported\n"));
  1902. ha->bfeat = *(gdth_bfeat_str *)ha->pscratch;
  1903. ha->more_proc = TRUE;
  1904. }
  1905. } else {
  1906. TRACE2(("BOARD_INFO requires firmware >= 1.10/2.08\n"));
  1907. strcpy(ha->binfo.type_string, gdth_ctr_name(hanum));
  1908. }
  1909. TRACE2(("Controller name: %s\n",ha->binfo.type_string));
  1910. /* read more informations */
  1911. if (ha->more_proc) {
  1912. /* physical drives, channel addresses */
  1913. ioc = (gdth_iochan_str *)ha->pscratch;
  1914. ioc->hdr.version = 0xffffffff;
  1915. ioc->hdr.list_entries = MAXBUS;
  1916. ioc->hdr.first_chan = 0;
  1917. ioc->hdr.last_chan = MAXBUS-1;
  1918. ioc->hdr.list_offset = GDTOFFSOF(gdth_iochan_str, list[0]);
  1919. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,IOCHAN_DESC,
  1920. INVALID_CHANNEL,sizeof(gdth_iochan_str))) {
  1921. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1922. ha->raw[bus_no].address = ioc->list[bus_no].address;
  1923. ha->raw[bus_no].local_no = ioc->list[bus_no].local_no;
  1924. }
  1925. } else {
  1926. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1927. ha->raw[bus_no].address = IO_CHANNEL;
  1928. ha->raw[bus_no].local_no = bus_no;
  1929. }
  1930. }
  1931. for (bus_no = 0; bus_no < ha->bus_cnt; ++bus_no) {
  1932. chn = (gdth_getch_str *)ha->pscratch;
  1933. chn->channel_no = ha->raw[bus_no].local_no;
  1934. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
  1935. SCSI_CHAN_CNT | L_CTRL_PATTERN,
  1936. ha->raw[bus_no].address | INVALID_CHANNEL,
  1937. sizeof(gdth_getch_str))) {
  1938. ha->raw[bus_no].pdev_cnt = chn->drive_cnt;
  1939. TRACE2(("Channel %d: %d phys. drives\n",
  1940. bus_no,chn->drive_cnt));
  1941. }
  1942. if (ha->raw[bus_no].pdev_cnt > 0) {
  1943. drl = (gdth_drlist_str *)ha->pscratch;
  1944. drl->sc_no = ha->raw[bus_no].local_no;
  1945. drl->sc_cnt = ha->raw[bus_no].pdev_cnt;
  1946. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
  1947. SCSI_DR_LIST | L_CTRL_PATTERN,
  1948. ha->raw[bus_no].address | INVALID_CHANNEL,
  1949. sizeof(gdth_drlist_str))) {
  1950. for (j = 0; j < ha->raw[bus_no].pdev_cnt; ++j)
  1951. ha->raw[bus_no].id_list[j] = drl->sc_list[j];
  1952. } else {
  1953. ha->raw[bus_no].pdev_cnt = 0;
  1954. }
  1955. }
  1956. }
  1957. /* logical drives */
  1958. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,CACHE_DRV_CNT,
  1959. INVALID_CHANNEL,sizeof(ulong32))) {
  1960. drv_cnt = *(ulong32 *)ha->pscratch;
  1961. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,CACHE_DRV_LIST,
  1962. INVALID_CHANNEL,drv_cnt * sizeof(ulong32))) {
  1963. for (j = 0; j < drv_cnt; ++j) {
  1964. drv_no = ((ulong32 *)ha->pscratch)[j];
  1965. if (drv_no < MAX_LDRIVES) {
  1966. ha->hdr[drv_no].is_logdrv = TRUE;
  1967. TRACE2(("Drive %d is log. drive\n",drv_no));
  1968. }
  1969. }
  1970. }
  1971. alst = (gdth_arcdl_str *)ha->pscratch;
  1972. alst->entries_avail = MAX_LDRIVES;
  1973. alst->first_entry = 0;
  1974. alst->list_offset = GDTOFFSOF(gdth_arcdl_str, list[0]);
  1975. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
  1976. ARRAY_DRV_LIST2 | LA_CTRL_PATTERN,
  1977. INVALID_CHANNEL, sizeof(gdth_arcdl_str) +
  1978. (alst->entries_avail-1) * sizeof(gdth_alist_str))) {
  1979. for (j = 0; j < alst->entries_init; ++j) {
  1980. ha->hdr[j].is_arraydrv = alst->list[j].is_arrayd;
  1981. ha->hdr[j].is_master = alst->list[j].is_master;
  1982. ha->hdr[j].is_parity = alst->list[j].is_parity;
  1983. ha->hdr[j].is_hotfix = alst->list[j].is_hotfix;
  1984. ha->hdr[j].master_no = alst->list[j].cd_handle;
  1985. }
  1986. } else if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
  1987. ARRAY_DRV_LIST | LA_CTRL_PATTERN,
  1988. 0, 35 * sizeof(gdth_alist_str))) {
  1989. for (j = 0; j < 35; ++j) {
  1990. alst2 = &((gdth_alist_str *)ha->pscratch)[j];
  1991. ha->hdr[j].is_arraydrv = alst2->is_arrayd;
  1992. ha->hdr[j].is_master = alst2->is_master;
  1993. ha->hdr[j].is_parity = alst2->is_parity;
  1994. ha->hdr[j].is_hotfix = alst2->is_hotfix;
  1995. ha->hdr[j].master_no = alst2->cd_handle;
  1996. }
  1997. }
  1998. }
  1999. }
  2000. /* initialize raw service */
  2001. ha->raw_feat = 0;
  2002. if (!force_dma32) {
  2003. ok = gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_X_INIT_RAW,0,0,0);
  2004. if (ok)
  2005. ha->raw_feat = GDT_64BIT;
  2006. }
  2007. if (force_dma32 || (!ok && ha->status == (ushort)S_NOFUNC))
  2008. ok = gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_INIT,0,0,0);
  2009. if (!ok) {
  2010. printk("GDT-HA %d: Initialization error raw service (code %d)\n",
  2011. hanum, ha->status);
  2012. return 0;
  2013. }
  2014. TRACE2(("gdth_search_drives(): RAWSERVICE initialized\n"));
  2015. /* set/get features raw service (scatter/gather) */
  2016. if (gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_SET_FEAT,SCATTER_GATHER,
  2017. 0,0)) {
  2018. TRACE2(("gdth_search_drives(): set features RAWSERVICE OK\n"));
  2019. if (gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_GET_FEAT,0,0,0)) {
  2020. TRACE2(("gdth_search_dr(): get feat RAWSERVICE %d\n",
  2021. ha->info));
  2022. ha->raw_feat |= (ushort)ha->info;
  2023. }
  2024. }
  2025. /* set/get features cache service (equal to raw service) */
  2026. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_SET_FEAT,0,
  2027. SCATTER_GATHER,0)) {
  2028. TRACE2(("gdth_search_drives(): set features CACHESERVICE OK\n"));
  2029. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_GET_FEAT,0,0,0)) {
  2030. TRACE2(("gdth_search_dr(): get feat CACHESERV. %d\n",
  2031. ha->info));
  2032. ha->cache_feat |= (ushort)ha->info;
  2033. }
  2034. }
  2035. /* reserve drives for raw service */
  2036. if (reserve_mode != 0) {
  2037. gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_RESERVE_ALL,
  2038. reserve_mode == 1 ? 1 : 3, 0, 0);
  2039. TRACE2(("gdth_search_drives(): RESERVE_ALL code %d\n",
  2040. ha->status));
  2041. }
  2042. for (i = 0; i < MAX_RES_ARGS; i += 4) {
  2043. if (reserve_list[i] == hanum && reserve_list[i+1] < ha->bus_cnt &&
  2044. reserve_list[i+2] < ha->tid_cnt && reserve_list[i+3] < MAXLUN) {
  2045. TRACE2(("gdth_search_drives(): reserve ha %d bus %d id %d lun %d\n",
  2046. reserve_list[i], reserve_list[i+1],
  2047. reserve_list[i+2], reserve_list[i+3]));
  2048. if (!gdth_internal_cmd(hanum,SCSIRAWSERVICE,GDT_RESERVE,0,
  2049. reserve_list[i+1], reserve_list[i+2] |
  2050. (reserve_list[i+3] << 8))) {
  2051. printk("GDT-HA %d: Error raw service (RESERVE, code %d)\n",
  2052. hanum, ha->status);
  2053. }
  2054. }
  2055. }
  2056. /* Determine OEM string using IOCTL */
  2057. oemstr = (gdth_oem_str_ioctl *)ha->pscratch;
  2058. oemstr->params.ctl_version = 0x01;
  2059. oemstr->params.buffer_size = sizeof(oemstr->text);
  2060. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_IOCTL,
  2061. CACHE_READ_OEM_STRING_RECORD,INVALID_CHANNEL,
  2062. sizeof(gdth_oem_str_ioctl))) {
  2063. TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD OK\n"));
  2064. printk("GDT-HA %d: Vendor: %s Name: %s\n",
  2065. hanum,oemstr->text.oem_company_name,ha->binfo.type_string);
  2066. /* Save the Host Drive inquiry data */
  2067. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  2068. strlcpy(ha->oem_name,oemstr->text.scsi_host_drive_inquiry_vendor_id,
  2069. sizeof(ha->oem_name));
  2070. #else
  2071. strncpy(ha->oem_name,oemstr->text.scsi_host_drive_inquiry_vendor_id,7);
  2072. ha->oem_name[7] = '\0';
  2073. #endif
  2074. } else {
  2075. /* Old method, based on PCI ID */
  2076. TRACE2(("gdth_search_drives(): CACHE_READ_OEM_STRING_RECORD failed\n"));
  2077. printk("GDT-HA %d: Name: %s\n",
  2078. hanum,ha->binfo.type_string);
  2079. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  2080. if (ha->oem_id == OEM_ID_INTEL)
  2081. strlcpy(ha->oem_name,"Intel ", sizeof(ha->oem_name));
  2082. else
  2083. strlcpy(ha->oem_name,"ICP ", sizeof(ha->oem_name));
  2084. #else
  2085. if (ha->oem_id == OEM_ID_INTEL)
  2086. strcpy(ha->oem_name,"Intel ");
  2087. else
  2088. strcpy(ha->oem_name,"ICP ");
  2089. #endif
  2090. }
  2091. /* scanning for host drives */
  2092. for (i = 0; i < cdev_cnt; ++i)
  2093. gdth_analyse_hdrive(hanum,i);
  2094. TRACE(("gdth_search_drives() OK\n"));
  2095. return 1;
  2096. }
  2097. static int gdth_analyse_hdrive(int hanum,ushort hdrive)
  2098. {
  2099. register gdth_ha_str *ha;
  2100. ulong32 drv_cyls;
  2101. int drv_hds, drv_secs;
  2102. TRACE(("gdth_analyse_hdrive() hanum %d drive %d\n",hanum,hdrive));
  2103. if (hdrive >= MAX_HDRIVES)
  2104. return 0;
  2105. ha = HADATA(gdth_ctr_tab[hanum]);
  2106. if (!gdth_internal_cmd(hanum,CACHESERVICE,GDT_INFO,hdrive,0,0))
  2107. return 0;
  2108. ha->hdr[hdrive].present = TRUE;
  2109. ha->hdr[hdrive].size = ha->info;
  2110. /* evaluate mapping (sectors per head, heads per cylinder) */
  2111. ha->hdr[hdrive].size &= ~SECS32;
  2112. if (ha->info2 == 0) {
  2113. gdth_eval_mapping(ha->hdr[hdrive].size,&drv_cyls,&drv_hds,&drv_secs);
  2114. } else {
  2115. drv_hds = ha->info2 & 0xff;
  2116. drv_secs = (ha->info2 >> 8) & 0xff;
  2117. drv_cyls = (ulong32)ha->hdr[hdrive].size / drv_hds / drv_secs;
  2118. }
  2119. ha->hdr[hdrive].heads = (unchar)drv_hds;
  2120. ha->hdr[hdrive].secs = (unchar)drv_secs;
  2121. /* round size */
  2122. ha->hdr[hdrive].size = drv_cyls * drv_hds * drv_secs;
  2123. if (ha->cache_feat & GDT_64BIT) {
  2124. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_X_INFO,hdrive,0,0)
  2125. && ha->info2 != 0) {
  2126. ha->hdr[hdrive].size = ((ulong64)ha->info2 << 32) | ha->info;
  2127. }
  2128. }
  2129. TRACE2(("gdth_search_dr() cdr. %d size %d hds %d scs %d\n",
  2130. hdrive,ha->hdr[hdrive].size,drv_hds,drv_secs));
  2131. /* get informations about device */
  2132. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_DEVTYPE,hdrive,0,0)) {
  2133. TRACE2(("gdth_search_dr() cache drive %d devtype %d\n",
  2134. hdrive,ha->info));
  2135. ha->hdr[hdrive].devtype = (ushort)ha->info;
  2136. }
  2137. /* cluster info */
  2138. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_CLUST_INFO,hdrive,0,0)) {
  2139. TRACE2(("gdth_search_dr() cache drive %d cluster info %d\n",
  2140. hdrive,ha->info));
  2141. if (!shared_access)
  2142. ha->hdr[hdrive].cluster_type = (unchar)ha->info;
  2143. }
  2144. /* R/W attributes */
  2145. if (gdth_internal_cmd(hanum,CACHESERVICE,GDT_RW_ATTRIBS,hdrive,0,0)) {
  2146. TRACE2(("gdth_search_dr() cache drive %d r/w attrib. %d\n",
  2147. hdrive,ha->info));
  2148. ha->hdr[hdrive].rw_attribs = (unchar)ha->info;
  2149. }
  2150. return 1;
  2151. }
  2152. /* command queueing/sending functions */
  2153. static void gdth_putq(int hanum,Scsi_Cmnd *scp,unchar priority)
  2154. {
  2155. register gdth_ha_str *ha;
  2156. register Scsi_Cmnd *pscp;
  2157. register Scsi_Cmnd *nscp;
  2158. ulong flags;
  2159. unchar b, t;
  2160. TRACE(("gdth_putq() priority %d\n",priority));
  2161. ha = HADATA(gdth_ctr_tab[hanum]);
  2162. spin_lock_irqsave(&ha->smp_lock, flags);
  2163. if (!IS_GDTH_INTERNAL_CMD(scp)) {
  2164. scp->SCp.this_residual = (int)priority;
  2165. b = virt_ctr ? NUMDATA(scp->device->host)->busnum:scp->device->channel;
  2166. t = scp->device->id;
  2167. if (priority >= DEFAULT_PRI) {
  2168. if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha,b)].lock) ||
  2169. (b==ha->virt_bus && t<MAX_HDRIVES && ha->hdr[t].lock)) {
  2170. TRACE2(("gdth_putq(): locked IO ->update_timeout()\n"));
  2171. scp->SCp.buffers_residual = gdth_update_timeout(hanum, scp, 0);
  2172. }
  2173. }
  2174. }
  2175. if (ha->req_first==NULL) {
  2176. ha->req_first = scp; /* queue was empty */
  2177. scp->SCp.ptr = NULL;
  2178. } else { /* queue not empty */
  2179. pscp = ha->req_first;
  2180. nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
  2181. /* priority: 0-highest,..,0xff-lowest */
  2182. while (nscp && (unchar)nscp->SCp.this_residual <= priority) {
  2183. pscp = nscp;
  2184. nscp = (Scsi_Cmnd *)pscp->SCp.ptr;
  2185. }
  2186. pscp->SCp.ptr = (char *)scp;
  2187. scp->SCp.ptr = (char *)nscp;
  2188. }
  2189. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2190. #ifdef GDTH_STATISTICS
  2191. flags = 0;
  2192. for (nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
  2193. ++flags;
  2194. if (max_rq < flags) {
  2195. max_rq = flags;
  2196. TRACE3(("GDT: max_rq = %d\n",(ushort)max_rq));
  2197. }
  2198. #endif
  2199. }
  2200. static void gdth_next(int hanum)
  2201. {
  2202. register gdth_ha_str *ha;
  2203. register Scsi_Cmnd *pscp;
  2204. register Scsi_Cmnd *nscp;
  2205. unchar b, t, l, firsttime;
  2206. unchar this_cmd, next_cmd;
  2207. ulong flags = 0;
  2208. int cmd_index;
  2209. TRACE(("gdth_next() hanum %d\n",hanum));
  2210. ha = HADATA(gdth_ctr_tab[hanum]);
  2211. if (!gdth_polling)
  2212. spin_lock_irqsave(&ha->smp_lock, flags);
  2213. ha->cmd_cnt = ha->cmd_offs_dpmem = 0;
  2214. this_cmd = firsttime = TRUE;
  2215. next_cmd = gdth_polling ? FALSE:TRUE;
  2216. cmd_index = 0;
  2217. for (nscp = pscp = ha->req_first; nscp; nscp = (Scsi_Cmnd *)nscp->SCp.ptr) {
  2218. if (nscp != pscp && nscp != (Scsi_Cmnd *)pscp->SCp.ptr)
  2219. pscp = (Scsi_Cmnd *)pscp->SCp.ptr;
  2220. if (!IS_GDTH_INTERNAL_CMD(nscp)) {
  2221. b = virt_ctr ?
  2222. NUMDATA(nscp->device->host)->busnum : nscp->device->channel;
  2223. t = nscp->device->id;
  2224. l = nscp->device->lun;
  2225. if (nscp->SCp.this_residual >= DEFAULT_PRI) {
  2226. if ((b != ha->virt_bus && ha->raw[BUS_L2P(ha,b)].lock) ||
  2227. (b == ha->virt_bus && t < MAX_HDRIVES && ha->hdr[t].lock))
  2228. continue;
  2229. }
  2230. } else
  2231. b = t = l = 0;
  2232. if (firsttime) {
  2233. if (gdth_test_busy(hanum)) { /* controller busy ? */
  2234. TRACE(("gdth_next() controller %d busy !\n",hanum));
  2235. if (!gdth_polling) {
  2236. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2237. return;
  2238. }
  2239. while (gdth_test_busy(hanum))
  2240. gdth_delay(1);
  2241. }
  2242. firsttime = FALSE;
  2243. }
  2244. if (!IS_GDTH_INTERNAL_CMD(nscp)) {
  2245. if (nscp->SCp.phase == -1) {
  2246. nscp->SCp.phase = CACHESERVICE; /* default: cache svc. */
  2247. if (nscp->cmnd[0] == TEST_UNIT_READY) {
  2248. TRACE2(("TEST_UNIT_READY Bus %d Id %d LUN %d\n",
  2249. b, t, l));
  2250. /* TEST_UNIT_READY -> set scan mode */
  2251. if ((ha->scan_mode & 0x0f) == 0) {
  2252. if (b == 0 && t == 0 && l == 0) {
  2253. ha->scan_mode |= 1;
  2254. TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
  2255. }
  2256. } else if ((ha->scan_mode & 0x0f) == 1) {
  2257. if (b == 0 && ((t == 0 && l == 1) ||
  2258. (t == 1 && l == 0))) {
  2259. nscp->SCp.sent_command = GDT_SCAN_START;
  2260. nscp->SCp.phase = ((ha->scan_mode & 0x10 ? 1:0) << 8)
  2261. | SCSIRAWSERVICE;
  2262. ha->scan_mode = 0x12;
  2263. TRACE2(("Scan mode: 0x%x (SCAN_START)\n",
  2264. ha->scan_mode));
  2265. } else {
  2266. ha->scan_mode &= 0x10;
  2267. TRACE2(("Scan mode: 0x%x\n", ha->scan_mode));
  2268. }
  2269. } else if (ha->scan_mode == 0x12) {
  2270. if (b == ha->bus_cnt && t == ha->tid_cnt-1) {
  2271. nscp->SCp.phase = SCSIRAWSERVICE;
  2272. nscp->SCp.sent_command = GDT_SCAN_END;
  2273. ha->scan_mode &= 0x10;
  2274. TRACE2(("Scan mode: 0x%x (SCAN_END)\n",
  2275. ha->scan_mode));
  2276. }
  2277. }
  2278. }
  2279. if (b == ha->virt_bus && nscp->cmnd[0] != INQUIRY &&
  2280. nscp->cmnd[0] != READ_CAPACITY && nscp->cmnd[0] != MODE_SENSE &&
  2281. (ha->hdr[t].cluster_type & CLUSTER_DRIVE)) {
  2282. /* always GDT_CLUST_INFO! */
  2283. nscp->SCp.sent_command = GDT_CLUST_INFO;
  2284. }
  2285. }
  2286. }
  2287. if (nscp->SCp.sent_command != -1) {
  2288. if ((nscp->SCp.phase & 0xff) == CACHESERVICE) {
  2289. if (!(cmd_index=gdth_fill_cache_cmd(hanum,nscp,t)))
  2290. this_cmd = FALSE;
  2291. next_cmd = FALSE;
  2292. } else if ((nscp->SCp.phase & 0xff) == SCSIRAWSERVICE) {
  2293. if (!(cmd_index=gdth_fill_raw_cmd(hanum,nscp,BUS_L2P(ha,b))))
  2294. this_cmd = FALSE;
  2295. next_cmd = FALSE;
  2296. } else {
  2297. memset((char*)nscp->sense_buffer,0,16);
  2298. nscp->sense_buffer[0] = 0x70;
  2299. nscp->sense_buffer[2] = NOT_READY;
  2300. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  2301. if (!nscp->SCp.have_data_in)
  2302. nscp->SCp.have_data_in++;
  2303. else
  2304. gdth_scsi_done(nscp);
  2305. }
  2306. } else if (IS_GDTH_INTERNAL_CMD(nscp)) {
  2307. if (!(cmd_index=gdth_special_cmd(hanum,nscp)))
  2308. this_cmd = FALSE;
  2309. next_cmd = FALSE;
  2310. } else if (b != ha->virt_bus) {
  2311. if (ha->raw[BUS_L2P(ha,b)].io_cnt[t] >= GDTH_MAX_RAW ||
  2312. !(cmd_index=gdth_fill_raw_cmd(hanum,nscp,BUS_L2P(ha,b))))
  2313. this_cmd = FALSE;
  2314. else
  2315. ha->raw[BUS_L2P(ha,b)].io_cnt[t]++;
  2316. } else if (t >= MAX_HDRIVES || !ha->hdr[t].present || l != 0) {
  2317. TRACE2(("Command 0x%x to bus %d id %d lun %d -> IGNORE\n",
  2318. nscp->cmnd[0], b, t, l));
  2319. nscp->result = DID_BAD_TARGET << 16;
  2320. if (!nscp->SCp.have_data_in)
  2321. nscp->SCp.have_data_in++;
  2322. else
  2323. gdth_scsi_done(nscp);
  2324. } else {
  2325. switch (nscp->cmnd[0]) {
  2326. case TEST_UNIT_READY:
  2327. case INQUIRY:
  2328. case REQUEST_SENSE:
  2329. case READ_CAPACITY:
  2330. case VERIFY:
  2331. case START_STOP:
  2332. case MODE_SENSE:
  2333. case SERVICE_ACTION_IN:
  2334. TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
  2335. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  2336. nscp->cmnd[4],nscp->cmnd[5]));
  2337. if (ha->hdr[t].media_changed && nscp->cmnd[0] != INQUIRY) {
  2338. /* return UNIT_ATTENTION */
  2339. TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
  2340. nscp->cmnd[0], t));
  2341. ha->hdr[t].media_changed = FALSE;
  2342. memset((char*)nscp->sense_buffer,0,16);
  2343. nscp->sense_buffer[0] = 0x70;
  2344. nscp->sense_buffer[2] = UNIT_ATTENTION;
  2345. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  2346. if (!nscp->SCp.have_data_in)
  2347. nscp->SCp.have_data_in++;
  2348. else
  2349. gdth_scsi_done(nscp);
  2350. } else if (gdth_internal_cache_cmd(hanum, nscp))
  2351. gdth_scsi_done(nscp);
  2352. break;
  2353. case ALLOW_MEDIUM_REMOVAL:
  2354. TRACE(("cache cmd %x/%x/%x/%x/%x/%x\n",nscp->cmnd[0],
  2355. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  2356. nscp->cmnd[4],nscp->cmnd[5]));
  2357. if ( (nscp->cmnd[4]&1) && !(ha->hdr[t].devtype&1) ) {
  2358. TRACE(("Prevent r. nonremov. drive->do nothing\n"));
  2359. nscp->result = DID_OK << 16;
  2360. nscp->sense_buffer[0] = 0;
  2361. if (!nscp->SCp.have_data_in)
  2362. nscp->SCp.have_data_in++;
  2363. else
  2364. gdth_scsi_done(nscp);
  2365. } else {
  2366. nscp->cmnd[3] = (ha->hdr[t].devtype&1) ? 1:0;
  2367. TRACE(("Prevent/allow r. %d rem. drive %d\n",
  2368. nscp->cmnd[4],nscp->cmnd[3]));
  2369. if (!(cmd_index=gdth_fill_cache_cmd(hanum,nscp,t)))
  2370. this_cmd = FALSE;
  2371. }
  2372. break;
  2373. case RESERVE:
  2374. case RELEASE:
  2375. TRACE2(("cache cmd %s\n",nscp->cmnd[0] == RESERVE ?
  2376. "RESERVE" : "RELEASE"));
  2377. if (!(cmd_index=gdth_fill_cache_cmd(hanum,nscp,t)))
  2378. this_cmd = FALSE;
  2379. break;
  2380. case READ_6:
  2381. case WRITE_6:
  2382. case READ_10:
  2383. case WRITE_10:
  2384. case READ_16:
  2385. case WRITE_16:
  2386. if (ha->hdr[t].media_changed) {
  2387. /* return UNIT_ATTENTION */
  2388. TRACE2(("cmd 0x%x target %d: UNIT_ATTENTION\n",
  2389. nscp->cmnd[0], t));
  2390. ha->hdr[t].media_changed = FALSE;
  2391. memset((char*)nscp->sense_buffer,0,16);
  2392. nscp->sense_buffer[0] = 0x70;
  2393. nscp->sense_buffer[2] = UNIT_ATTENTION;
  2394. nscp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  2395. if (!nscp->SCp.have_data_in)
  2396. nscp->SCp.have_data_in++;
  2397. else
  2398. gdth_scsi_done(nscp);
  2399. } else if (!(cmd_index=gdth_fill_cache_cmd(hanum, nscp, t)))
  2400. this_cmd = FALSE;
  2401. break;
  2402. default:
  2403. TRACE2(("cache cmd %x/%x/%x/%x/%x/%x unknown\n",nscp->cmnd[0],
  2404. nscp->cmnd[1],nscp->cmnd[2],nscp->cmnd[3],
  2405. nscp->cmnd[4],nscp->cmnd[5]));
  2406. printk("GDT-HA %d: Unknown SCSI command 0x%x to cache service !\n",
  2407. hanum, nscp->cmnd[0]);
  2408. nscp->result = DID_ABORT << 16;
  2409. if (!nscp->SCp.have_data_in)
  2410. nscp->SCp.have_data_in++;
  2411. else
  2412. gdth_scsi_done(nscp);
  2413. break;
  2414. }
  2415. }
  2416. if (!this_cmd)
  2417. break;
  2418. if (nscp == ha->req_first)
  2419. ha->req_first = pscp = (Scsi_Cmnd *)nscp->SCp.ptr;
  2420. else
  2421. pscp->SCp.ptr = nscp->SCp.ptr;
  2422. if (!next_cmd)
  2423. break;
  2424. }
  2425. if (ha->cmd_cnt > 0) {
  2426. gdth_release_event(hanum);
  2427. }
  2428. if (!gdth_polling)
  2429. spin_unlock_irqrestore(&ha->smp_lock, flags);
  2430. if (gdth_polling && ha->cmd_cnt > 0) {
  2431. if (!gdth_wait(hanum,cmd_index,POLL_TIMEOUT))
  2432. printk("GDT-HA %d: Command %d timed out !\n",
  2433. hanum,cmd_index);
  2434. }
  2435. }
  2436. static void gdth_copy_internal_data(int hanum,Scsi_Cmnd *scp,
  2437. char *buffer,ushort count)
  2438. {
  2439. ushort cpcount,i;
  2440. ushort cpsum,cpnow;
  2441. struct scatterlist *sl;
  2442. gdth_ha_str *ha;
  2443. char *address;
  2444. cpcount = count<=(ushort)scp->request_bufflen ? count:(ushort)scp->request_bufflen;
  2445. ha = HADATA(gdth_ctr_tab[hanum]);
  2446. if (scp->use_sg) {
  2447. sl = (struct scatterlist *)scp->request_buffer;
  2448. for (i=0,cpsum=0; i<scp->use_sg; ++i,++sl) {
  2449. unsigned long flags;
  2450. cpnow = (ushort)sl->length;
  2451. TRACE(("copy_internal() now %d sum %d count %d %d\n",
  2452. cpnow,cpsum,cpcount,(ushort)scp->bufflen));
  2453. if (cpsum+cpnow > cpcount)
  2454. cpnow = cpcount - cpsum;
  2455. cpsum += cpnow;
  2456. if (!sl->page) {
  2457. printk("GDT-HA %d: invalid sc/gt element in gdth_copy_internal_data()\n",
  2458. hanum);
  2459. return;
  2460. }
  2461. local_irq_save(flags);
  2462. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  2463. address = kmap_atomic(sl->page, KM_BIO_SRC_IRQ) + sl->offset;
  2464. memcpy(address,buffer,cpnow);
  2465. flush_dcache_page(sl->page);
  2466. kunmap_atomic(address, KM_BIO_SRC_IRQ);
  2467. #else
  2468. address = kmap_atomic(sl->page, KM_BH_IRQ) + sl->offset;
  2469. memcpy(address,buffer,cpnow);
  2470. flush_dcache_page(sl->page);
  2471. kunmap_atomic(address, KM_BH_IRQ);
  2472. #endif
  2473. local_irq_restore(flags);
  2474. if (cpsum == cpcount)
  2475. break;
  2476. buffer += cpnow;
  2477. }
  2478. } else {
  2479. TRACE(("copy_internal() count %d\n",cpcount));
  2480. memcpy((char*)scp->request_buffer,buffer,cpcount);
  2481. }
  2482. }
  2483. static int gdth_internal_cache_cmd(int hanum,Scsi_Cmnd *scp)
  2484. {
  2485. register gdth_ha_str *ha;
  2486. unchar t;
  2487. gdth_inq_data inq;
  2488. gdth_rdcap_data rdc;
  2489. gdth_sense_data sd;
  2490. gdth_modep_data mpd;
  2491. ha = HADATA(gdth_ctr_tab[hanum]);
  2492. t = scp->device->id;
  2493. TRACE(("gdth_internal_cache_cmd() cmd 0x%x hdrive %d\n",
  2494. scp->cmnd[0],t));
  2495. scp->result = DID_OK << 16;
  2496. scp->sense_buffer[0] = 0;
  2497. switch (scp->cmnd[0]) {
  2498. case TEST_UNIT_READY:
  2499. case VERIFY:
  2500. case START_STOP:
  2501. TRACE2(("Test/Verify/Start hdrive %d\n",t));
  2502. break;
  2503. case INQUIRY:
  2504. TRACE2(("Inquiry hdrive %d devtype %d\n",
  2505. t,ha->hdr[t].devtype));
  2506. inq.type_qual = (ha->hdr[t].devtype&4) ? TYPE_ROM:TYPE_DISK;
  2507. /* you can here set all disks to removable, if you want to do
  2508. a flush using the ALLOW_MEDIUM_REMOVAL command */
  2509. inq.modif_rmb = 0x00;
  2510. if ((ha->hdr[t].devtype & 1) ||
  2511. (ha->hdr[t].cluster_type & CLUSTER_DRIVE))
  2512. inq.modif_rmb = 0x80;
  2513. inq.version = 2;
  2514. inq.resp_aenc = 2;
  2515. inq.add_length= 32;
  2516. strcpy(inq.vendor,ha->oem_name);
  2517. sprintf(inq.product,"Host Drive #%02d",t);
  2518. strcpy(inq.revision," ");
  2519. gdth_copy_internal_data(hanum,scp,(char*)&inq,sizeof(gdth_inq_data));
  2520. break;
  2521. case REQUEST_SENSE:
  2522. TRACE2(("Request sense hdrive %d\n",t));
  2523. sd.errorcode = 0x70;
  2524. sd.segno = 0x00;
  2525. sd.key = NO_SENSE;
  2526. sd.info = 0;
  2527. sd.add_length= 0;
  2528. gdth_copy_internal_data(hanum,scp,(char*)&sd,sizeof(gdth_sense_data));
  2529. break;
  2530. case MODE_SENSE:
  2531. TRACE2(("Mode sense hdrive %d\n",t));
  2532. memset((char*)&mpd,0,sizeof(gdth_modep_data));
  2533. mpd.hd.data_length = sizeof(gdth_modep_data);
  2534. mpd.hd.dev_par = (ha->hdr[t].devtype&2) ? 0x80:0;
  2535. mpd.hd.bd_length = sizeof(mpd.bd);
  2536. mpd.bd.block_length[0] = (SECTOR_SIZE & 0x00ff0000) >> 16;
  2537. mpd.bd.block_length[1] = (SECTOR_SIZE & 0x0000ff00) >> 8;
  2538. mpd.bd.block_length[2] = (SECTOR_SIZE & 0x000000ff);
  2539. gdth_copy_internal_data(hanum,scp,(char*)&mpd,sizeof(gdth_modep_data));
  2540. break;
  2541. case READ_CAPACITY:
  2542. TRACE2(("Read capacity hdrive %d\n",t));
  2543. if (ha->hdr[t].size > (ulong64)0xffffffff)
  2544. rdc.last_block_no = 0xffffffff;
  2545. else
  2546. rdc.last_block_no = cpu_to_be32(ha->hdr[t].size-1);
  2547. rdc.block_length = cpu_to_be32(SECTOR_SIZE);
  2548. gdth_copy_internal_data(hanum,scp,(char*)&rdc,sizeof(gdth_rdcap_data));
  2549. break;
  2550. case SERVICE_ACTION_IN:
  2551. if ((scp->cmnd[1] & 0x1f) == SAI_READ_CAPACITY_16 &&
  2552. (ha->cache_feat & GDT_64BIT)) {
  2553. gdth_rdcap16_data rdc16;
  2554. TRACE2(("Read capacity (16) hdrive %d\n",t));
  2555. rdc16.last_block_no = cpu_to_be64(ha->hdr[t].size-1);
  2556. rdc16.block_length = cpu_to_be32(SECTOR_SIZE);
  2557. gdth_copy_internal_data(hanum,scp,(char*)&rdc16,sizeof(gdth_rdcap16_data));
  2558. } else {
  2559. scp->result = DID_ABORT << 16;
  2560. }
  2561. break;
  2562. default:
  2563. TRACE2(("Internal cache cmd 0x%x unknown\n",scp->cmnd[0]));
  2564. break;
  2565. }
  2566. if (!scp->SCp.have_data_in)
  2567. scp->SCp.have_data_in++;
  2568. else
  2569. return 1;
  2570. return 0;
  2571. }
  2572. static int gdth_fill_cache_cmd(int hanum,Scsi_Cmnd *scp,ushort hdrive)
  2573. {
  2574. register gdth_ha_str *ha;
  2575. register gdth_cmd_str *cmdp;
  2576. struct scatterlist *sl;
  2577. ulong32 cnt, blockcnt;
  2578. ulong64 no, blockno;
  2579. dma_addr_t phys_addr;
  2580. int i, cmd_index, read_write, sgcnt, mode64;
  2581. struct page *page;
  2582. ulong offset;
  2583. ha = HADATA(gdth_ctr_tab[hanum]);
  2584. cmdp = ha->pccb;
  2585. TRACE(("gdth_fill_cache_cmd() cmd 0x%x cmdsize %d hdrive %d\n",
  2586. scp->cmnd[0],scp->cmd_len,hdrive));
  2587. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2588. return 0;
  2589. mode64 = (ha->cache_feat & GDT_64BIT) ? TRUE : FALSE;
  2590. /* test for READ_16, WRITE_16 if !mode64 ? ---
  2591. not required, should not occur due to error return on
  2592. READ_CAPACITY_16 */
  2593. cmdp->Service = CACHESERVICE;
  2594. cmdp->RequestBuffer = scp;
  2595. /* search free command index */
  2596. if (!(cmd_index=gdth_get_cmd_index(hanum))) {
  2597. TRACE(("GDT: No free command index found\n"));
  2598. return 0;
  2599. }
  2600. /* if it's the first command, set command semaphore */
  2601. if (ha->cmd_cnt == 0)
  2602. gdth_set_sema0(hanum);
  2603. /* fill command */
  2604. read_write = 0;
  2605. if (scp->SCp.sent_command != -1)
  2606. cmdp->OpCode = scp->SCp.sent_command; /* special cache cmd. */
  2607. else if (scp->cmnd[0] == RESERVE)
  2608. cmdp->OpCode = GDT_RESERVE_DRV;
  2609. else if (scp->cmnd[0] == RELEASE)
  2610. cmdp->OpCode = GDT_RELEASE_DRV;
  2611. else if (scp->cmnd[0] == ALLOW_MEDIUM_REMOVAL) {
  2612. if (scp->cmnd[4] & 1) /* prevent ? */
  2613. cmdp->OpCode = GDT_MOUNT;
  2614. else if (scp->cmnd[3] & 1) /* removable drive ? */
  2615. cmdp->OpCode = GDT_UNMOUNT;
  2616. else
  2617. cmdp->OpCode = GDT_FLUSH;
  2618. } else if (scp->cmnd[0] == WRITE_6 || scp->cmnd[0] == WRITE_10 ||
  2619. scp->cmnd[0] == WRITE_12 || scp->cmnd[0] == WRITE_16
  2620. ) {
  2621. read_write = 1;
  2622. if (gdth_write_through || ((ha->hdr[hdrive].rw_attribs & 1) &&
  2623. (ha->cache_feat & GDT_WR_THROUGH)))
  2624. cmdp->OpCode = GDT_WRITE_THR;
  2625. else
  2626. cmdp->OpCode = GDT_WRITE;
  2627. } else {
  2628. read_write = 2;
  2629. cmdp->OpCode = GDT_READ;
  2630. }
  2631. cmdp->BoardNode = LOCALBOARD;
  2632. if (mode64) {
  2633. cmdp->u.cache64.DeviceNo = hdrive;
  2634. cmdp->u.cache64.BlockNo = 1;
  2635. cmdp->u.cache64.sg_canz = 0;
  2636. } else {
  2637. cmdp->u.cache.DeviceNo = hdrive;
  2638. cmdp->u.cache.BlockNo = 1;
  2639. cmdp->u.cache.sg_canz = 0;
  2640. }
  2641. if (read_write) {
  2642. if (scp->cmd_len == 16) {
  2643. memcpy(&no, &scp->cmnd[2], sizeof(ulong64));
  2644. blockno = be64_to_cpu(no);
  2645. memcpy(&cnt, &scp->cmnd[10], sizeof(ulong32));
  2646. blockcnt = be32_to_cpu(cnt);
  2647. } else if (scp->cmd_len == 10) {
  2648. memcpy(&no, &scp->cmnd[2], sizeof(ulong32));
  2649. blockno = be32_to_cpu(no);
  2650. memcpy(&cnt, &scp->cmnd[7], sizeof(ushort));
  2651. blockcnt = be16_to_cpu(cnt);
  2652. } else {
  2653. memcpy(&no, &scp->cmnd[0], sizeof(ulong32));
  2654. blockno = be32_to_cpu(no) & 0x001fffffUL;
  2655. blockcnt= scp->cmnd[4]==0 ? 0x100 : scp->cmnd[4];
  2656. }
  2657. if (mode64) {
  2658. cmdp->u.cache64.BlockNo = blockno;
  2659. cmdp->u.cache64.BlockCnt = blockcnt;
  2660. } else {
  2661. cmdp->u.cache.BlockNo = (ulong32)blockno;
  2662. cmdp->u.cache.BlockCnt = blockcnt;
  2663. }
  2664. if (scp->use_sg) {
  2665. sl = (struct scatterlist *)scp->request_buffer;
  2666. sgcnt = scp->use_sg;
  2667. scp->SCp.Status = GDTH_MAP_SG;
  2668. scp->SCp.Message = (read_write == 1 ?
  2669. PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  2670. sgcnt = pci_map_sg(ha->pdev,sl,scp->use_sg,scp->SCp.Message);
  2671. if (mode64) {
  2672. cmdp->u.cache64.DestAddr= (ulong64)-1;
  2673. cmdp->u.cache64.sg_canz = sgcnt;
  2674. for (i=0; i<sgcnt; ++i,++sl) {
  2675. cmdp->u.cache64.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2676. #ifdef GDTH_DMA_STATISTICS
  2677. if (cmdp->u.cache64.sg_lst[i].sg_ptr > (ulong64)0xffffffff)
  2678. ha->dma64_cnt++;
  2679. else
  2680. ha->dma32_cnt++;
  2681. #endif
  2682. cmdp->u.cache64.sg_lst[i].sg_len = sg_dma_len(sl);
  2683. }
  2684. } else {
  2685. cmdp->u.cache.DestAddr= 0xffffffff;
  2686. cmdp->u.cache.sg_canz = sgcnt;
  2687. for (i=0; i<sgcnt; ++i,++sl) {
  2688. cmdp->u.cache.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2689. #ifdef GDTH_DMA_STATISTICS
  2690. ha->dma32_cnt++;
  2691. #endif
  2692. cmdp->u.cache.sg_lst[i].sg_len = sg_dma_len(sl);
  2693. }
  2694. }
  2695. #ifdef GDTH_STATISTICS
  2696. if (max_sg < (ulong32)sgcnt) {
  2697. max_sg = (ulong32)sgcnt;
  2698. TRACE3(("GDT: max_sg = %d\n",max_sg));
  2699. }
  2700. #endif
  2701. } else if (scp->request_bufflen) {
  2702. scp->SCp.Status = GDTH_MAP_SINGLE;
  2703. scp->SCp.Message = (read_write == 1 ?
  2704. PCI_DMA_TODEVICE : PCI_DMA_FROMDEVICE);
  2705. page = virt_to_page(scp->request_buffer);
  2706. offset = (ulong)scp->request_buffer & ~PAGE_MASK;
  2707. phys_addr = pci_map_page(ha->pdev,page,offset,
  2708. scp->request_bufflen,scp->SCp.Message);
  2709. scp->SCp.dma_handle = phys_addr;
  2710. if (mode64) {
  2711. if (ha->cache_feat & SCATTER_GATHER) {
  2712. cmdp->u.cache64.DestAddr = (ulong64)-1;
  2713. cmdp->u.cache64.sg_canz = 1;
  2714. cmdp->u.cache64.sg_lst[0].sg_ptr = phys_addr;
  2715. cmdp->u.cache64.sg_lst[0].sg_len = scp->request_bufflen;
  2716. cmdp->u.cache64.sg_lst[1].sg_len = 0;
  2717. } else {
  2718. cmdp->u.cache64.DestAddr = phys_addr;
  2719. cmdp->u.cache64.sg_canz= 0;
  2720. }
  2721. } else {
  2722. if (ha->cache_feat & SCATTER_GATHER) {
  2723. cmdp->u.cache.DestAddr = 0xffffffff;
  2724. cmdp->u.cache.sg_canz = 1;
  2725. cmdp->u.cache.sg_lst[0].sg_ptr = phys_addr;
  2726. cmdp->u.cache.sg_lst[0].sg_len = scp->request_bufflen;
  2727. cmdp->u.cache.sg_lst[1].sg_len = 0;
  2728. } else {
  2729. cmdp->u.cache.DestAddr = phys_addr;
  2730. cmdp->u.cache.sg_canz= 0;
  2731. }
  2732. }
  2733. }
  2734. }
  2735. /* evaluate command size, check space */
  2736. if (mode64) {
  2737. TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2738. cmdp->u.cache64.DestAddr,cmdp->u.cache64.sg_canz,
  2739. cmdp->u.cache64.sg_lst[0].sg_ptr,
  2740. cmdp->u.cache64.sg_lst[0].sg_len));
  2741. TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
  2742. cmdp->OpCode,cmdp->u.cache64.BlockNo,cmdp->u.cache64.BlockCnt));
  2743. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) +
  2744. (ushort)cmdp->u.cache64.sg_canz * sizeof(gdth_sg64_str);
  2745. } else {
  2746. TRACE(("cache cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2747. cmdp->u.cache.DestAddr,cmdp->u.cache.sg_canz,
  2748. cmdp->u.cache.sg_lst[0].sg_ptr,
  2749. cmdp->u.cache.sg_lst[0].sg_len));
  2750. TRACE(("cache cmd: cmd %d blockno. %d, blockcnt %d\n",
  2751. cmdp->OpCode,cmdp->u.cache.BlockNo,cmdp->u.cache.BlockCnt));
  2752. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) +
  2753. (ushort)cmdp->u.cache.sg_canz * sizeof(gdth_sg_str);
  2754. }
  2755. if (ha->cmd_len & 3)
  2756. ha->cmd_len += (4 - (ha->cmd_len & 3));
  2757. if (ha->cmd_cnt > 0) {
  2758. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  2759. ha->ic_all_size) {
  2760. TRACE2(("gdth_fill_cache() DPMEM overflow\n"));
  2761. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  2762. return 0;
  2763. }
  2764. }
  2765. /* copy command */
  2766. gdth_copy_command(hanum);
  2767. return cmd_index;
  2768. }
  2769. static int gdth_fill_raw_cmd(int hanum,Scsi_Cmnd *scp,unchar b)
  2770. {
  2771. register gdth_ha_str *ha;
  2772. register gdth_cmd_str *cmdp;
  2773. struct scatterlist *sl;
  2774. ushort i;
  2775. dma_addr_t phys_addr, sense_paddr;
  2776. int cmd_index, sgcnt, mode64;
  2777. unchar t,l;
  2778. struct page *page;
  2779. ulong offset;
  2780. ha = HADATA(gdth_ctr_tab[hanum]);
  2781. t = scp->device->id;
  2782. l = scp->device->lun;
  2783. cmdp = ha->pccb;
  2784. TRACE(("gdth_fill_raw_cmd() cmd 0x%x bus %d ID %d LUN %d\n",
  2785. scp->cmnd[0],b,t,l));
  2786. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2787. return 0;
  2788. mode64 = (ha->raw_feat & GDT_64BIT) ? TRUE : FALSE;
  2789. cmdp->Service = SCSIRAWSERVICE;
  2790. cmdp->RequestBuffer = scp;
  2791. /* search free command index */
  2792. if (!(cmd_index=gdth_get_cmd_index(hanum))) {
  2793. TRACE(("GDT: No free command index found\n"));
  2794. return 0;
  2795. }
  2796. /* if it's the first command, set command semaphore */
  2797. if (ha->cmd_cnt == 0)
  2798. gdth_set_sema0(hanum);
  2799. /* fill command */
  2800. if (scp->SCp.sent_command != -1) {
  2801. cmdp->OpCode = scp->SCp.sent_command; /* special raw cmd. */
  2802. cmdp->BoardNode = LOCALBOARD;
  2803. if (mode64) {
  2804. cmdp->u.raw64.direction = (scp->SCp.phase >> 8);
  2805. TRACE2(("special raw cmd 0x%x param 0x%x\n",
  2806. cmdp->OpCode, cmdp->u.raw64.direction));
  2807. /* evaluate command size */
  2808. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst);
  2809. } else {
  2810. cmdp->u.raw.direction = (scp->SCp.phase >> 8);
  2811. TRACE2(("special raw cmd 0x%x param 0x%x\n",
  2812. cmdp->OpCode, cmdp->u.raw.direction));
  2813. /* evaluate command size */
  2814. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst);
  2815. }
  2816. } else {
  2817. page = virt_to_page(scp->sense_buffer);
  2818. offset = (ulong)scp->sense_buffer & ~PAGE_MASK;
  2819. sense_paddr = pci_map_page(ha->pdev,page,offset,
  2820. 16,PCI_DMA_FROMDEVICE);
  2821. *(ulong32 *)&scp->SCp.buffer = (ulong32)sense_paddr;
  2822. /* high part, if 64bit */
  2823. *(ulong32 *)&scp->host_scribble = (ulong32)((ulong64)sense_paddr >> 32);
  2824. cmdp->OpCode = GDT_WRITE; /* always */
  2825. cmdp->BoardNode = LOCALBOARD;
  2826. if (mode64) {
  2827. cmdp->u.raw64.reserved = 0;
  2828. cmdp->u.raw64.mdisc_time = 0;
  2829. cmdp->u.raw64.mcon_time = 0;
  2830. cmdp->u.raw64.clen = scp->cmd_len;
  2831. cmdp->u.raw64.target = t;
  2832. cmdp->u.raw64.lun = l;
  2833. cmdp->u.raw64.bus = b;
  2834. cmdp->u.raw64.priority = 0;
  2835. cmdp->u.raw64.sdlen = scp->request_bufflen;
  2836. cmdp->u.raw64.sense_len = 16;
  2837. cmdp->u.raw64.sense_data = sense_paddr;
  2838. cmdp->u.raw64.direction =
  2839. gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
  2840. memcpy(cmdp->u.raw64.cmd,scp->cmnd,16);
  2841. cmdp->u.raw64.sg_ranz = 0;
  2842. } else {
  2843. cmdp->u.raw.reserved = 0;
  2844. cmdp->u.raw.mdisc_time = 0;
  2845. cmdp->u.raw.mcon_time = 0;
  2846. cmdp->u.raw.clen = scp->cmd_len;
  2847. cmdp->u.raw.target = t;
  2848. cmdp->u.raw.lun = l;
  2849. cmdp->u.raw.bus = b;
  2850. cmdp->u.raw.priority = 0;
  2851. cmdp->u.raw.link_p = 0;
  2852. cmdp->u.raw.sdlen = scp->request_bufflen;
  2853. cmdp->u.raw.sense_len = 16;
  2854. cmdp->u.raw.sense_data = sense_paddr;
  2855. cmdp->u.raw.direction =
  2856. gdth_direction_tab[scp->cmnd[0]]==DOU ? GDTH_DATA_OUT:GDTH_DATA_IN;
  2857. memcpy(cmdp->u.raw.cmd,scp->cmnd,12);
  2858. cmdp->u.raw.sg_ranz = 0;
  2859. }
  2860. if (scp->use_sg) {
  2861. sl = (struct scatterlist *)scp->request_buffer;
  2862. sgcnt = scp->use_sg;
  2863. scp->SCp.Status = GDTH_MAP_SG;
  2864. scp->SCp.Message = PCI_DMA_BIDIRECTIONAL;
  2865. sgcnt = pci_map_sg(ha->pdev,sl,scp->use_sg,scp->SCp.Message);
  2866. if (mode64) {
  2867. cmdp->u.raw64.sdata = (ulong64)-1;
  2868. cmdp->u.raw64.sg_ranz = sgcnt;
  2869. for (i=0; i<sgcnt; ++i,++sl) {
  2870. cmdp->u.raw64.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2871. #ifdef GDTH_DMA_STATISTICS
  2872. if (cmdp->u.raw64.sg_lst[i].sg_ptr > (ulong64)0xffffffff)
  2873. ha->dma64_cnt++;
  2874. else
  2875. ha->dma32_cnt++;
  2876. #endif
  2877. cmdp->u.raw64.sg_lst[i].sg_len = sg_dma_len(sl);
  2878. }
  2879. } else {
  2880. cmdp->u.raw.sdata = 0xffffffff;
  2881. cmdp->u.raw.sg_ranz = sgcnt;
  2882. for (i=0; i<sgcnt; ++i,++sl) {
  2883. cmdp->u.raw.sg_lst[i].sg_ptr = sg_dma_address(sl);
  2884. #ifdef GDTH_DMA_STATISTICS
  2885. ha->dma32_cnt++;
  2886. #endif
  2887. cmdp->u.raw.sg_lst[i].sg_len = sg_dma_len(sl);
  2888. }
  2889. }
  2890. #ifdef GDTH_STATISTICS
  2891. if (max_sg < sgcnt) {
  2892. max_sg = sgcnt;
  2893. TRACE3(("GDT: max_sg = %d\n",sgcnt));
  2894. }
  2895. #endif
  2896. } else if (scp->request_bufflen) {
  2897. scp->SCp.Status = GDTH_MAP_SINGLE;
  2898. scp->SCp.Message = PCI_DMA_BIDIRECTIONAL;
  2899. page = virt_to_page(scp->request_buffer);
  2900. offset = (ulong)scp->request_buffer & ~PAGE_MASK;
  2901. phys_addr = pci_map_page(ha->pdev,page,offset,
  2902. scp->request_bufflen,scp->SCp.Message);
  2903. scp->SCp.dma_handle = phys_addr;
  2904. if (mode64) {
  2905. if (ha->raw_feat & SCATTER_GATHER) {
  2906. cmdp->u.raw64.sdata = (ulong64)-1;
  2907. cmdp->u.raw64.sg_ranz= 1;
  2908. cmdp->u.raw64.sg_lst[0].sg_ptr = phys_addr;
  2909. cmdp->u.raw64.sg_lst[0].sg_len = scp->request_bufflen;
  2910. cmdp->u.raw64.sg_lst[1].sg_len = 0;
  2911. } else {
  2912. cmdp->u.raw64.sdata = phys_addr;
  2913. cmdp->u.raw64.sg_ranz= 0;
  2914. }
  2915. } else {
  2916. if (ha->raw_feat & SCATTER_GATHER) {
  2917. cmdp->u.raw.sdata = 0xffffffff;
  2918. cmdp->u.raw.sg_ranz= 1;
  2919. cmdp->u.raw.sg_lst[0].sg_ptr = phys_addr;
  2920. cmdp->u.raw.sg_lst[0].sg_len = scp->request_bufflen;
  2921. cmdp->u.raw.sg_lst[1].sg_len = 0;
  2922. } else {
  2923. cmdp->u.raw.sdata = phys_addr;
  2924. cmdp->u.raw.sg_ranz= 0;
  2925. }
  2926. }
  2927. }
  2928. if (mode64) {
  2929. TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2930. cmdp->u.raw64.sdata,cmdp->u.raw64.sg_ranz,
  2931. cmdp->u.raw64.sg_lst[0].sg_ptr,
  2932. cmdp->u.raw64.sg_lst[0].sg_len));
  2933. /* evaluate command size */
  2934. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) +
  2935. (ushort)cmdp->u.raw64.sg_ranz * sizeof(gdth_sg64_str);
  2936. } else {
  2937. TRACE(("raw cmd: addr. %x sganz %x sgptr0 %x sglen0 %x\n",
  2938. cmdp->u.raw.sdata,cmdp->u.raw.sg_ranz,
  2939. cmdp->u.raw.sg_lst[0].sg_ptr,
  2940. cmdp->u.raw.sg_lst[0].sg_len));
  2941. /* evaluate command size */
  2942. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) +
  2943. (ushort)cmdp->u.raw.sg_ranz * sizeof(gdth_sg_str);
  2944. }
  2945. }
  2946. /* check space */
  2947. if (ha->cmd_len & 3)
  2948. ha->cmd_len += (4 - (ha->cmd_len & 3));
  2949. if (ha->cmd_cnt > 0) {
  2950. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  2951. ha->ic_all_size) {
  2952. TRACE2(("gdth_fill_raw() DPMEM overflow\n"));
  2953. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  2954. return 0;
  2955. }
  2956. }
  2957. /* copy command */
  2958. gdth_copy_command(hanum);
  2959. return cmd_index;
  2960. }
  2961. static int gdth_special_cmd(int hanum,Scsi_Cmnd *scp)
  2962. {
  2963. register gdth_ha_str *ha;
  2964. register gdth_cmd_str *cmdp;
  2965. int cmd_index;
  2966. ha = HADATA(gdth_ctr_tab[hanum]);
  2967. cmdp= ha->pccb;
  2968. TRACE2(("gdth_special_cmd(): "));
  2969. if (ha->type==GDT_EISA && ha->cmd_cnt>0)
  2970. return 0;
  2971. memcpy( cmdp, scp->request_buffer, sizeof(gdth_cmd_str));
  2972. cmdp->RequestBuffer = scp;
  2973. /* search free command index */
  2974. if (!(cmd_index=gdth_get_cmd_index(hanum))) {
  2975. TRACE(("GDT: No free command index found\n"));
  2976. return 0;
  2977. }
  2978. /* if it's the first command, set command semaphore */
  2979. if (ha->cmd_cnt == 0)
  2980. gdth_set_sema0(hanum);
  2981. /* evaluate command size, check space */
  2982. if (cmdp->OpCode == GDT_IOCTL) {
  2983. TRACE2(("IOCTL\n"));
  2984. ha->cmd_len =
  2985. GDTOFFSOF(gdth_cmd_str,u.ioctl.p_param) + sizeof(ulong64);
  2986. } else if (cmdp->Service == CACHESERVICE) {
  2987. TRACE2(("cache command %d\n",cmdp->OpCode));
  2988. if (ha->cache_feat & GDT_64BIT)
  2989. ha->cmd_len =
  2990. GDTOFFSOF(gdth_cmd_str,u.cache64.sg_lst) + sizeof(gdth_sg64_str);
  2991. else
  2992. ha->cmd_len =
  2993. GDTOFFSOF(gdth_cmd_str,u.cache.sg_lst) + sizeof(gdth_sg_str);
  2994. } else if (cmdp->Service == SCSIRAWSERVICE) {
  2995. TRACE2(("raw command %d\n",cmdp->OpCode));
  2996. if (ha->raw_feat & GDT_64BIT)
  2997. ha->cmd_len =
  2998. GDTOFFSOF(gdth_cmd_str,u.raw64.sg_lst) + sizeof(gdth_sg64_str);
  2999. else
  3000. ha->cmd_len =
  3001. GDTOFFSOF(gdth_cmd_str,u.raw.sg_lst) + sizeof(gdth_sg_str);
  3002. }
  3003. if (ha->cmd_len & 3)
  3004. ha->cmd_len += (4 - (ha->cmd_len & 3));
  3005. if (ha->cmd_cnt > 0) {
  3006. if ((ha->cmd_offs_dpmem + ha->cmd_len + DPMEM_COMMAND_OFFSET) >
  3007. ha->ic_all_size) {
  3008. TRACE2(("gdth_special_cmd() DPMEM overflow\n"));
  3009. ha->cmd_tab[cmd_index-2].cmnd = UNUSED_CMND;
  3010. return 0;
  3011. }
  3012. }
  3013. /* copy command */
  3014. gdth_copy_command(hanum);
  3015. return cmd_index;
  3016. }
  3017. /* Controller event handling functions */
  3018. static gdth_evt_str *gdth_store_event(gdth_ha_str *ha, ushort source,
  3019. ushort idx, gdth_evt_data *evt)
  3020. {
  3021. gdth_evt_str *e;
  3022. struct timeval tv;
  3023. /* no GDTH_LOCK_HA() ! */
  3024. TRACE2(("gdth_store_event() source %d idx %d\n", source, idx));
  3025. if (source == 0) /* no source -> no event */
  3026. return NULL;
  3027. if (ebuffer[elastidx].event_source == source &&
  3028. ebuffer[elastidx].event_idx == idx &&
  3029. ((evt->size != 0 && ebuffer[elastidx].event_data.size != 0 &&
  3030. !memcmp((char *)&ebuffer[elastidx].event_data.eu,
  3031. (char *)&evt->eu, evt->size)) ||
  3032. (evt->size == 0 && ebuffer[elastidx].event_data.size == 0 &&
  3033. !strcmp((char *)&ebuffer[elastidx].event_data.event_string,
  3034. (char *)&evt->event_string)))) {
  3035. e = &ebuffer[elastidx];
  3036. do_gettimeofday(&tv);
  3037. e->last_stamp = tv.tv_sec;
  3038. ++e->same_count;
  3039. } else {
  3040. if (ebuffer[elastidx].event_source != 0) { /* entry not free ? */
  3041. ++elastidx;
  3042. if (elastidx == MAX_EVENTS)
  3043. elastidx = 0;
  3044. if (elastidx == eoldidx) { /* reached mark ? */
  3045. ++eoldidx;
  3046. if (eoldidx == MAX_EVENTS)
  3047. eoldidx = 0;
  3048. }
  3049. }
  3050. e = &ebuffer[elastidx];
  3051. e->event_source = source;
  3052. e->event_idx = idx;
  3053. do_gettimeofday(&tv);
  3054. e->first_stamp = e->last_stamp = tv.tv_sec;
  3055. e->same_count = 1;
  3056. e->event_data = *evt;
  3057. e->application = 0;
  3058. }
  3059. return e;
  3060. }
  3061. static int gdth_read_event(gdth_ha_str *ha, int handle, gdth_evt_str *estr)
  3062. {
  3063. gdth_evt_str *e;
  3064. int eindex;
  3065. ulong flags;
  3066. TRACE2(("gdth_read_event() handle %d\n", handle));
  3067. spin_lock_irqsave(&ha->smp_lock, flags);
  3068. if (handle == -1)
  3069. eindex = eoldidx;
  3070. else
  3071. eindex = handle;
  3072. estr->event_source = 0;
  3073. if (eindex >= MAX_EVENTS) {
  3074. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3075. return eindex;
  3076. }
  3077. e = &ebuffer[eindex];
  3078. if (e->event_source != 0) {
  3079. if (eindex != elastidx) {
  3080. if (++eindex == MAX_EVENTS)
  3081. eindex = 0;
  3082. } else {
  3083. eindex = -1;
  3084. }
  3085. memcpy(estr, e, sizeof(gdth_evt_str));
  3086. }
  3087. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3088. return eindex;
  3089. }
  3090. static void gdth_readapp_event(gdth_ha_str *ha,
  3091. unchar application, gdth_evt_str *estr)
  3092. {
  3093. gdth_evt_str *e;
  3094. int eindex;
  3095. ulong flags;
  3096. unchar found = FALSE;
  3097. TRACE2(("gdth_readapp_event() app. %d\n", application));
  3098. spin_lock_irqsave(&ha->smp_lock, flags);
  3099. eindex = eoldidx;
  3100. for (;;) {
  3101. e = &ebuffer[eindex];
  3102. if (e->event_source == 0)
  3103. break;
  3104. if ((e->application & application) == 0) {
  3105. e->application |= application;
  3106. found = TRUE;
  3107. break;
  3108. }
  3109. if (eindex == elastidx)
  3110. break;
  3111. if (++eindex == MAX_EVENTS)
  3112. eindex = 0;
  3113. }
  3114. if (found)
  3115. memcpy(estr, e, sizeof(gdth_evt_str));
  3116. else
  3117. estr->event_source = 0;
  3118. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3119. }
  3120. static void gdth_clear_events(void)
  3121. {
  3122. TRACE(("gdth_clear_events()"));
  3123. eoldidx = elastidx = 0;
  3124. ebuffer[0].event_source = 0;
  3125. }
  3126. /* SCSI interface functions */
  3127. static irqreturn_t gdth_interrupt(int irq,void *dev_id)
  3128. {
  3129. gdth_ha_str *ha2 = (gdth_ha_str *)dev_id;
  3130. register gdth_ha_str *ha;
  3131. gdt6m_dpram_str __iomem *dp6m_ptr = NULL;
  3132. gdt6_dpram_str __iomem *dp6_ptr;
  3133. gdt2_dpram_str __iomem *dp2_ptr;
  3134. Scsi_Cmnd *scp;
  3135. int hanum, rval, i;
  3136. unchar IStatus;
  3137. ushort Service;
  3138. ulong flags = 0;
  3139. #ifdef INT_COAL
  3140. int coalesced = FALSE;
  3141. int next = FALSE;
  3142. gdth_coal_status *pcs = NULL;
  3143. int act_int_coal = 0;
  3144. #endif
  3145. TRACE(("gdth_interrupt() IRQ %d\n",irq));
  3146. /* if polling and not from gdth_wait() -> return */
  3147. if (gdth_polling) {
  3148. if (!gdth_from_wait) {
  3149. return IRQ_HANDLED;
  3150. }
  3151. }
  3152. if (!gdth_polling)
  3153. spin_lock_irqsave(&ha2->smp_lock, flags);
  3154. wait_index = 0;
  3155. /* search controller */
  3156. if ((hanum = gdth_get_status(&IStatus,irq)) == -1) {
  3157. /* spurious interrupt */
  3158. if (!gdth_polling)
  3159. spin_unlock_irqrestore(&ha2->smp_lock, flags);
  3160. return IRQ_HANDLED;
  3161. }
  3162. ha = HADATA(gdth_ctr_tab[hanum]);
  3163. #ifdef GDTH_STATISTICS
  3164. ++act_ints;
  3165. #endif
  3166. #ifdef INT_COAL
  3167. /* See if the fw is returning coalesced status */
  3168. if (IStatus == COALINDEX) {
  3169. /* Coalesced status. Setup the initial status
  3170. buffer pointer and flags */
  3171. pcs = ha->coal_stat;
  3172. coalesced = TRUE;
  3173. next = TRUE;
  3174. }
  3175. do {
  3176. if (coalesced) {
  3177. /* For coalesced requests all status
  3178. information is found in the status buffer */
  3179. IStatus = (unchar)(pcs->status & 0xff);
  3180. }
  3181. #endif
  3182. if (ha->type == GDT_EISA) {
  3183. if (IStatus & 0x80) { /* error flag */
  3184. IStatus &= ~0x80;
  3185. ha->status = inw(ha->bmic + MAILBOXREG+8);
  3186. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  3187. } else /* no error */
  3188. ha->status = S_OK;
  3189. ha->info = inl(ha->bmic + MAILBOXREG+12);
  3190. ha->service = inw(ha->bmic + MAILBOXREG+10);
  3191. ha->info2 = inl(ha->bmic + MAILBOXREG+4);
  3192. outb(0xff, ha->bmic + EDOORREG); /* acknowledge interrupt */
  3193. outb(0x00, ha->bmic + SEMA1REG); /* reset status semaphore */
  3194. } else if (ha->type == GDT_ISA) {
  3195. dp2_ptr = ha->brd;
  3196. if (IStatus & 0x80) { /* error flag */
  3197. IStatus &= ~0x80;
  3198. ha->status = gdth_readw(&dp2_ptr->u.ic.Status);
  3199. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  3200. } else /* no error */
  3201. ha->status = S_OK;
  3202. ha->info = gdth_readl(&dp2_ptr->u.ic.Info[0]);
  3203. ha->service = gdth_readw(&dp2_ptr->u.ic.Service);
  3204. ha->info2 = gdth_readl(&dp2_ptr->u.ic.Info[1]);
  3205. gdth_writeb(0xff, &dp2_ptr->io.irqdel); /* acknowledge interrupt */
  3206. gdth_writeb(0, &dp2_ptr->u.ic.Cmd_Index);/* reset command index */
  3207. gdth_writeb(0, &dp2_ptr->io.Sema1); /* reset status semaphore */
  3208. } else if (ha->type == GDT_PCI) {
  3209. dp6_ptr = ha->brd;
  3210. if (IStatus & 0x80) { /* error flag */
  3211. IStatus &= ~0x80;
  3212. ha->status = gdth_readw(&dp6_ptr->u.ic.Status);
  3213. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  3214. } else /* no error */
  3215. ha->status = S_OK;
  3216. ha->info = gdth_readl(&dp6_ptr->u.ic.Info[0]);
  3217. ha->service = gdth_readw(&dp6_ptr->u.ic.Service);
  3218. ha->info2 = gdth_readl(&dp6_ptr->u.ic.Info[1]);
  3219. gdth_writeb(0xff, &dp6_ptr->io.irqdel); /* acknowledge interrupt */
  3220. gdth_writeb(0, &dp6_ptr->u.ic.Cmd_Index);/* reset command index */
  3221. gdth_writeb(0, &dp6_ptr->io.Sema1); /* reset status semaphore */
  3222. } else if (ha->type == GDT_PCINEW) {
  3223. if (IStatus & 0x80) { /* error flag */
  3224. IStatus &= ~0x80;
  3225. ha->status = inw(PTR2USHORT(&ha->plx->status));
  3226. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  3227. } else
  3228. ha->status = S_OK;
  3229. ha->info = inl(PTR2USHORT(&ha->plx->info[0]));
  3230. ha->service = inw(PTR2USHORT(&ha->plx->service));
  3231. ha->info2 = inl(PTR2USHORT(&ha->plx->info[1]));
  3232. outb(0xff, PTR2USHORT(&ha->plx->edoor_reg));
  3233. outb(0x00, PTR2USHORT(&ha->plx->sema1_reg));
  3234. } else if (ha->type == GDT_PCIMPR) {
  3235. dp6m_ptr = ha->brd;
  3236. if (IStatus & 0x80) { /* error flag */
  3237. IStatus &= ~0x80;
  3238. #ifdef INT_COAL
  3239. if (coalesced)
  3240. ha->status = pcs->ext_status & 0xffff;
  3241. else
  3242. #endif
  3243. ha->status = gdth_readw(&dp6m_ptr->i960r.status);
  3244. TRACE2(("gdth_interrupt() error %d/%d\n",IStatus,ha->status));
  3245. } else /* no error */
  3246. ha->status = S_OK;
  3247. #ifdef INT_COAL
  3248. /* get information */
  3249. if (coalesced) {
  3250. ha->info = pcs->info0;
  3251. ha->info2 = pcs->info1;
  3252. ha->service = (pcs->ext_status >> 16) & 0xffff;
  3253. } else
  3254. #endif
  3255. {
  3256. ha->info = gdth_readl(&dp6m_ptr->i960r.info[0]);
  3257. ha->service = gdth_readw(&dp6m_ptr->i960r.service);
  3258. ha->info2 = gdth_readl(&dp6m_ptr->i960r.info[1]);
  3259. }
  3260. /* event string */
  3261. if (IStatus == ASYNCINDEX) {
  3262. if (ha->service != SCREENSERVICE &&
  3263. (ha->fw_vers & 0xff) >= 0x1a) {
  3264. ha->dvr.severity = gdth_readb
  3265. (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.severity);
  3266. for (i = 0; i < 256; ++i) {
  3267. ha->dvr.event_string[i] = gdth_readb
  3268. (&((gdt6m_dpram_str __iomem *)ha->brd)->i960r.evt_str[i]);
  3269. if (ha->dvr.event_string[i] == 0)
  3270. break;
  3271. }
  3272. }
  3273. }
  3274. #ifdef INT_COAL
  3275. /* Make sure that non coalesced interrupts get cleared
  3276. before being handled by gdth_async_event/gdth_sync_event */
  3277. if (!coalesced)
  3278. #endif
  3279. {
  3280. gdth_writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  3281. gdth_writeb(0, &dp6m_ptr->i960r.sema1_reg);
  3282. }
  3283. } else {
  3284. TRACE2(("gdth_interrupt() unknown controller type\n"));
  3285. if (!gdth_polling)
  3286. spin_unlock_irqrestore(&ha2->smp_lock, flags);
  3287. return IRQ_HANDLED;
  3288. }
  3289. TRACE(("gdth_interrupt() index %d stat %d info %d\n",
  3290. IStatus,ha->status,ha->info));
  3291. if (gdth_from_wait) {
  3292. wait_hanum = hanum;
  3293. wait_index = (int)IStatus;
  3294. }
  3295. if (IStatus == ASYNCINDEX) {
  3296. TRACE2(("gdth_interrupt() async. event\n"));
  3297. gdth_async_event(hanum);
  3298. if (!gdth_polling)
  3299. spin_unlock_irqrestore(&ha2->smp_lock, flags);
  3300. gdth_next(hanum);
  3301. return IRQ_HANDLED;
  3302. }
  3303. if (IStatus == SPEZINDEX) {
  3304. TRACE2(("Service unknown or not initialized !\n"));
  3305. ha->dvr.size = sizeof(ha->dvr.eu.driver);
  3306. ha->dvr.eu.driver.ionode = hanum;
  3307. gdth_store_event(ha, ES_DRIVER, 4, &ha->dvr);
  3308. if (!gdth_polling)
  3309. spin_unlock_irqrestore(&ha2->smp_lock, flags);
  3310. return IRQ_HANDLED;
  3311. }
  3312. scp = ha->cmd_tab[IStatus-2].cmnd;
  3313. Service = ha->cmd_tab[IStatus-2].service;
  3314. ha->cmd_tab[IStatus-2].cmnd = UNUSED_CMND;
  3315. if (scp == UNUSED_CMND) {
  3316. TRACE2(("gdth_interrupt() index to unused command (%d)\n",IStatus));
  3317. ha->dvr.size = sizeof(ha->dvr.eu.driver);
  3318. ha->dvr.eu.driver.ionode = hanum;
  3319. ha->dvr.eu.driver.index = IStatus;
  3320. gdth_store_event(ha, ES_DRIVER, 1, &ha->dvr);
  3321. if (!gdth_polling)
  3322. spin_unlock_irqrestore(&ha2->smp_lock, flags);
  3323. return IRQ_HANDLED;
  3324. }
  3325. if (scp == INTERNAL_CMND) {
  3326. TRACE(("gdth_interrupt() answer to internal command\n"));
  3327. if (!gdth_polling)
  3328. spin_unlock_irqrestore(&ha2->smp_lock, flags);
  3329. return IRQ_HANDLED;
  3330. }
  3331. TRACE(("gdth_interrupt() sync. status\n"));
  3332. rval = gdth_sync_event(hanum,Service,IStatus,scp);
  3333. if (!gdth_polling)
  3334. spin_unlock_irqrestore(&ha2->smp_lock, flags);
  3335. if (rval == 2) {
  3336. gdth_putq(hanum,scp,scp->SCp.this_residual);
  3337. } else if (rval == 1) {
  3338. gdth_scsi_done(scp);
  3339. }
  3340. #ifdef INT_COAL
  3341. if (coalesced) {
  3342. /* go to the next status in the status buffer */
  3343. ++pcs;
  3344. #ifdef GDTH_STATISTICS
  3345. ++act_int_coal;
  3346. if (act_int_coal > max_int_coal) {
  3347. max_int_coal = act_int_coal;
  3348. printk("GDT: max_int_coal = %d\n",(ushort)max_int_coal);
  3349. }
  3350. #endif
  3351. /* see if there is another status */
  3352. if (pcs->status == 0)
  3353. /* Stop the coalesce loop */
  3354. next = FALSE;
  3355. }
  3356. } while (next);
  3357. /* coalescing only for new GDT_PCIMPR controllers available */
  3358. if (ha->type == GDT_PCIMPR && coalesced) {
  3359. gdth_writeb(0xff, &dp6m_ptr->i960r.edoor_reg);
  3360. gdth_writeb(0, &dp6m_ptr->i960r.sema1_reg);
  3361. }
  3362. #endif
  3363. gdth_next(hanum);
  3364. return IRQ_HANDLED;
  3365. }
  3366. static int gdth_sync_event(int hanum,int service,unchar index,Scsi_Cmnd *scp)
  3367. {
  3368. register gdth_ha_str *ha;
  3369. gdth_msg_str *msg;
  3370. gdth_cmd_str *cmdp;
  3371. unchar b, t;
  3372. ha = HADATA(gdth_ctr_tab[hanum]);
  3373. cmdp = ha->pccb;
  3374. TRACE(("gdth_sync_event() serv %d status %d\n",
  3375. service,ha->status));
  3376. if (service == SCREENSERVICE) {
  3377. msg = ha->pmsg;
  3378. TRACE(("len: %d, answer: %d, ext: %d, alen: %d\n",
  3379. msg->msg_len,msg->msg_answer,msg->msg_ext,msg->msg_alen));
  3380. if (msg->msg_len > MSGLEN+1)
  3381. msg->msg_len = MSGLEN+1;
  3382. if (msg->msg_len)
  3383. if (!(msg->msg_answer && msg->msg_ext)) {
  3384. msg->msg_text[msg->msg_len] = '\0';
  3385. printk("%s",msg->msg_text);
  3386. }
  3387. if (msg->msg_ext && !msg->msg_answer) {
  3388. while (gdth_test_busy(hanum))
  3389. gdth_delay(0);
  3390. cmdp->Service = SCREENSERVICE;
  3391. cmdp->RequestBuffer = SCREEN_CMND;
  3392. gdth_get_cmd_index(hanum);
  3393. gdth_set_sema0(hanum);
  3394. cmdp->OpCode = GDT_READ;
  3395. cmdp->BoardNode = LOCALBOARD;
  3396. cmdp->u.screen.reserved = 0;
  3397. cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
  3398. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  3399. ha->cmd_offs_dpmem = 0;
  3400. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  3401. + sizeof(ulong64);
  3402. ha->cmd_cnt = 0;
  3403. gdth_copy_command(hanum);
  3404. gdth_release_event(hanum);
  3405. return 0;
  3406. }
  3407. if (msg->msg_answer && msg->msg_alen) {
  3408. /* default answers (getchar() not possible) */
  3409. if (msg->msg_alen == 1) {
  3410. msg->msg_alen = 0;
  3411. msg->msg_len = 1;
  3412. msg->msg_text[0] = 0;
  3413. } else {
  3414. msg->msg_alen -= 2;
  3415. msg->msg_len = 2;
  3416. msg->msg_text[0] = 1;
  3417. msg->msg_text[1] = 0;
  3418. }
  3419. msg->msg_ext = 0;
  3420. msg->msg_answer = 0;
  3421. while (gdth_test_busy(hanum))
  3422. gdth_delay(0);
  3423. cmdp->Service = SCREENSERVICE;
  3424. cmdp->RequestBuffer = SCREEN_CMND;
  3425. gdth_get_cmd_index(hanum);
  3426. gdth_set_sema0(hanum);
  3427. cmdp->OpCode = GDT_WRITE;
  3428. cmdp->BoardNode = LOCALBOARD;
  3429. cmdp->u.screen.reserved = 0;
  3430. cmdp->u.screen.su.msg.msg_handle= msg->msg_handle;
  3431. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  3432. ha->cmd_offs_dpmem = 0;
  3433. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  3434. + sizeof(ulong64);
  3435. ha->cmd_cnt = 0;
  3436. gdth_copy_command(hanum);
  3437. gdth_release_event(hanum);
  3438. return 0;
  3439. }
  3440. printk("\n");
  3441. } else {
  3442. b = virt_ctr ? NUMDATA(scp->device->host)->busnum : scp->device->channel;
  3443. t = scp->device->id;
  3444. if (scp->SCp.sent_command == -1 && b != ha->virt_bus) {
  3445. ha->raw[BUS_L2P(ha,b)].io_cnt[t]--;
  3446. }
  3447. /* cache or raw service */
  3448. if (ha->status == S_BSY) {
  3449. TRACE2(("Controller busy -> retry !\n"));
  3450. if (scp->SCp.sent_command == GDT_MOUNT)
  3451. scp->SCp.sent_command = GDT_CLUST_INFO;
  3452. /* retry */
  3453. return 2;
  3454. }
  3455. if (scp->SCp.Status == GDTH_MAP_SG)
  3456. pci_unmap_sg(ha->pdev,scp->request_buffer,
  3457. scp->use_sg,scp->SCp.Message);
  3458. else if (scp->SCp.Status == GDTH_MAP_SINGLE)
  3459. pci_unmap_page(ha->pdev,scp->SCp.dma_handle,
  3460. scp->request_bufflen,scp->SCp.Message);
  3461. if (scp->SCp.buffer) {
  3462. dma_addr_t addr;
  3463. addr = (dma_addr_t)*(ulong32 *)&scp->SCp.buffer;
  3464. if (scp->host_scribble)
  3465. addr += (dma_addr_t)
  3466. ((ulong64)(*(ulong32 *)&scp->host_scribble) << 32);
  3467. pci_unmap_page(ha->pdev,addr,16,PCI_DMA_FROMDEVICE);
  3468. }
  3469. if (ha->status == S_OK) {
  3470. scp->SCp.Status = S_OK;
  3471. scp->SCp.Message = ha->info;
  3472. if (scp->SCp.sent_command != -1) {
  3473. TRACE2(("gdth_sync_event(): special cmd 0x%x OK\n",
  3474. scp->SCp.sent_command));
  3475. /* special commands GDT_CLUST_INFO/GDT_MOUNT ? */
  3476. if (scp->SCp.sent_command == GDT_CLUST_INFO) {
  3477. ha->hdr[t].cluster_type = (unchar)ha->info;
  3478. if (!(ha->hdr[t].cluster_type &
  3479. CLUSTER_MOUNTED)) {
  3480. /* NOT MOUNTED -> MOUNT */
  3481. scp->SCp.sent_command = GDT_MOUNT;
  3482. if (ha->hdr[t].cluster_type &
  3483. CLUSTER_RESERVED) {
  3484. /* cluster drive RESERVED (on the other node) */
  3485. scp->SCp.phase = -2; /* reservation conflict */
  3486. }
  3487. } else {
  3488. scp->SCp.sent_command = -1;
  3489. }
  3490. } else {
  3491. if (scp->SCp.sent_command == GDT_MOUNT) {
  3492. ha->hdr[t].cluster_type |= CLUSTER_MOUNTED;
  3493. ha->hdr[t].media_changed = TRUE;
  3494. } else if (scp->SCp.sent_command == GDT_UNMOUNT) {
  3495. ha->hdr[t].cluster_type &= ~CLUSTER_MOUNTED;
  3496. ha->hdr[t].media_changed = TRUE;
  3497. }
  3498. scp->SCp.sent_command = -1;
  3499. }
  3500. /* retry */
  3501. scp->SCp.this_residual = HIGH_PRI;
  3502. return 2;
  3503. } else {
  3504. /* RESERVE/RELEASE ? */
  3505. if (scp->cmnd[0] == RESERVE) {
  3506. ha->hdr[t].cluster_type |= CLUSTER_RESERVED;
  3507. } else if (scp->cmnd[0] == RELEASE) {
  3508. ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
  3509. }
  3510. scp->result = DID_OK << 16;
  3511. scp->sense_buffer[0] = 0;
  3512. }
  3513. } else {
  3514. scp->SCp.Status = ha->status;
  3515. scp->SCp.Message = ha->info;
  3516. if (scp->SCp.sent_command != -1) {
  3517. TRACE2(("gdth_sync_event(): special cmd 0x%x error 0x%x\n",
  3518. scp->SCp.sent_command, ha->status));
  3519. if (scp->SCp.sent_command == GDT_SCAN_START ||
  3520. scp->SCp.sent_command == GDT_SCAN_END) {
  3521. scp->SCp.sent_command = -1;
  3522. /* retry */
  3523. scp->SCp.this_residual = HIGH_PRI;
  3524. return 2;
  3525. }
  3526. memset((char*)scp->sense_buffer,0,16);
  3527. scp->sense_buffer[0] = 0x70;
  3528. scp->sense_buffer[2] = NOT_READY;
  3529. scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  3530. } else if (service == CACHESERVICE) {
  3531. if (ha->status == S_CACHE_UNKNOWN &&
  3532. (ha->hdr[t].cluster_type &
  3533. CLUSTER_RESERVE_STATE) == CLUSTER_RESERVE_STATE) {
  3534. /* bus reset -> force GDT_CLUST_INFO */
  3535. ha->hdr[t].cluster_type &= ~CLUSTER_RESERVED;
  3536. }
  3537. memset((char*)scp->sense_buffer,0,16);
  3538. if (ha->status == (ushort)S_CACHE_RESERV) {
  3539. scp->result = (DID_OK << 16) | (RESERVATION_CONFLICT << 1);
  3540. } else {
  3541. scp->sense_buffer[0] = 0x70;
  3542. scp->sense_buffer[2] = NOT_READY;
  3543. scp->result = (DID_OK << 16) | (CHECK_CONDITION << 1);
  3544. }
  3545. if (!IS_GDTH_INTERNAL_CMD(scp)) {
  3546. ha->dvr.size = sizeof(ha->dvr.eu.sync);
  3547. ha->dvr.eu.sync.ionode = hanum;
  3548. ha->dvr.eu.sync.service = service;
  3549. ha->dvr.eu.sync.status = ha->status;
  3550. ha->dvr.eu.sync.info = ha->info;
  3551. ha->dvr.eu.sync.hostdrive = t;
  3552. if (ha->status >= 0x8000)
  3553. gdth_store_event(ha, ES_SYNC, 0, &ha->dvr);
  3554. else
  3555. gdth_store_event(ha, ES_SYNC, service, &ha->dvr);
  3556. }
  3557. } else {
  3558. /* sense buffer filled from controller firmware (DMA) */
  3559. if (ha->status != S_RAW_SCSI || ha->info >= 0x100) {
  3560. scp->result = DID_BAD_TARGET << 16;
  3561. } else {
  3562. scp->result = (DID_OK << 16) | ha->info;
  3563. }
  3564. }
  3565. }
  3566. if (!scp->SCp.have_data_in)
  3567. scp->SCp.have_data_in++;
  3568. else
  3569. return 1;
  3570. }
  3571. return 0;
  3572. }
  3573. static char *async_cache_tab[] = {
  3574. /* 0*/ "\011\000\002\002\002\004\002\006\004"
  3575. "GDT HA %u, service %u, async. status %u/%lu unknown",
  3576. /* 1*/ "\011\000\002\002\002\004\002\006\004"
  3577. "GDT HA %u, service %u, async. status %u/%lu unknown",
  3578. /* 2*/ "\005\000\002\006\004"
  3579. "GDT HA %u, Host Drive %lu not ready",
  3580. /* 3*/ "\005\000\002\006\004"
  3581. "GDT HA %u, Host Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
  3582. /* 4*/ "\005\000\002\006\004"
  3583. "GDT HA %u, mirror update on Host Drive %lu failed",
  3584. /* 5*/ "\005\000\002\006\004"
  3585. "GDT HA %u, Mirror Drive %lu failed",
  3586. /* 6*/ "\005\000\002\006\004"
  3587. "GDT HA %u, Mirror Drive %lu: REASSIGN not successful and/or data error on reassigned blocks. Drive may crash in the future and should be replaced",
  3588. /* 7*/ "\005\000\002\006\004"
  3589. "GDT HA %u, Host Drive %lu write protected",
  3590. /* 8*/ "\005\000\002\006\004"
  3591. "GDT HA %u, media changed in Host Drive %lu",
  3592. /* 9*/ "\005\000\002\006\004"
  3593. "GDT HA %u, Host Drive %lu is offline",
  3594. /*10*/ "\005\000\002\006\004"
  3595. "GDT HA %u, media change of Mirror Drive %lu",
  3596. /*11*/ "\005\000\002\006\004"
  3597. "GDT HA %u, Mirror Drive %lu is write protected",
  3598. /*12*/ "\005\000\002\006\004"
  3599. "GDT HA %u, general error on Host Drive %lu. Please check the devices of this drive!",
  3600. /*13*/ "\007\000\002\006\002\010\002"
  3601. "GDT HA %u, Array Drive %u: Cache Drive %u failed",
  3602. /*14*/ "\005\000\002\006\002"
  3603. "GDT HA %u, Array Drive %u: FAIL state entered",
  3604. /*15*/ "\005\000\002\006\002"
  3605. "GDT HA %u, Array Drive %u: error",
  3606. /*16*/ "\007\000\002\006\002\010\002"
  3607. "GDT HA %u, Array Drive %u: failed drive replaced by Cache Drive %u",
  3608. /*17*/ "\005\000\002\006\002"
  3609. "GDT HA %u, Array Drive %u: parity build failed",
  3610. /*18*/ "\005\000\002\006\002"
  3611. "GDT HA %u, Array Drive %u: drive rebuild failed",
  3612. /*19*/ "\005\000\002\010\002"
  3613. "GDT HA %u, Test of Hot Fix %u failed",
  3614. /*20*/ "\005\000\002\006\002"
  3615. "GDT HA %u, Array Drive %u: drive build finished successfully",
  3616. /*21*/ "\005\000\002\006\002"
  3617. "GDT HA %u, Array Drive %u: drive rebuild finished successfully",
  3618. /*22*/ "\007\000\002\006\002\010\002"
  3619. "GDT HA %u, Array Drive %u: Hot Fix %u activated",
  3620. /*23*/ "\005\000\002\006\002"
  3621. "GDT HA %u, Host Drive %u: processing of i/o aborted due to serious drive error",
  3622. /*24*/ "\005\000\002\010\002"
  3623. "GDT HA %u, mirror update on Cache Drive %u completed",
  3624. /*25*/ "\005\000\002\010\002"
  3625. "GDT HA %u, mirror update on Cache Drive %lu failed",
  3626. /*26*/ "\005\000\002\006\002"
  3627. "GDT HA %u, Array Drive %u: drive rebuild started",
  3628. /*27*/ "\005\000\002\012\001"
  3629. "GDT HA %u, Fault bus %u: SHELF OK detected",
  3630. /*28*/ "\005\000\002\012\001"
  3631. "GDT HA %u, Fault bus %u: SHELF not OK detected",
  3632. /*29*/ "\007\000\002\012\001\013\001"
  3633. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug started",
  3634. /*30*/ "\007\000\002\012\001\013\001"
  3635. "GDT HA %u, Fault bus %u, ID %u: new disk detected",
  3636. /*31*/ "\007\000\002\012\001\013\001"
  3637. "GDT HA %u, Fault bus %u, ID %u: old disk detected",
  3638. /*32*/ "\007\000\002\012\001\013\001"
  3639. "GDT HA %u, Fault bus %u, ID %u: plugging an active disk is invalid",
  3640. /*33*/ "\007\000\002\012\001\013\001"
  3641. "GDT HA %u, Fault bus %u, ID %u: invalid device detected",
  3642. /*34*/ "\011\000\002\012\001\013\001\006\004"
  3643. "GDT HA %u, Fault bus %u, ID %u: insufficient disk capacity (%lu MB required)",
  3644. /*35*/ "\007\000\002\012\001\013\001"
  3645. "GDT HA %u, Fault bus %u, ID %u: disk write protected",
  3646. /*36*/ "\007\000\002\012\001\013\001"
  3647. "GDT HA %u, Fault bus %u, ID %u: disk not available",
  3648. /*37*/ "\007\000\002\012\001\006\004"
  3649. "GDT HA %u, Fault bus %u: swap detected (%lu)",
  3650. /*38*/ "\007\000\002\012\001\013\001"
  3651. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug finished successfully",
  3652. /*39*/ "\007\000\002\012\001\013\001"
  3653. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted due to user Hot Plug",
  3654. /*40*/ "\007\000\002\012\001\013\001"
  3655. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug aborted",
  3656. /*41*/ "\007\000\002\012\001\013\001"
  3657. "GDT HA %u, Fault bus %u, ID %u: Auto Hot Plug for Hot Fix started",
  3658. /*42*/ "\005\000\002\006\002"
  3659. "GDT HA %u, Array Drive %u: drive build started",
  3660. /*43*/ "\003\000\002"
  3661. "GDT HA %u, DRAM parity error detected",
  3662. /*44*/ "\005\000\002\006\002"
  3663. "GDT HA %u, Mirror Drive %u: update started",
  3664. /*45*/ "\007\000\002\006\002\010\002"
  3665. "GDT HA %u, Mirror Drive %u: Hot Fix %u activated",
  3666. /*46*/ "\005\000\002\006\002"
  3667. "GDT HA %u, Array Drive %u: no matching Pool Hot Fix Drive available",
  3668. /*47*/ "\005\000\002\006\002"
  3669. "GDT HA %u, Array Drive %u: Pool Hot Fix Drive available",
  3670. /*48*/ "\005\000\002\006\002"
  3671. "GDT HA %u, Mirror Drive %u: no matching Pool Hot Fix Drive available",
  3672. /*49*/ "\005\000\002\006\002"
  3673. "GDT HA %u, Mirror Drive %u: Pool Hot Fix Drive available",
  3674. /*50*/ "\007\000\002\012\001\013\001"
  3675. "GDT HA %u, SCSI bus %u, ID %u: IGNORE_WIDE_RESIDUE message received",
  3676. /*51*/ "\005\000\002\006\002"
  3677. "GDT HA %u, Array Drive %u: expand started",
  3678. /*52*/ "\005\000\002\006\002"
  3679. "GDT HA %u, Array Drive %u: expand finished successfully",
  3680. /*53*/ "\005\000\002\006\002"
  3681. "GDT HA %u, Array Drive %u: expand failed",
  3682. /*54*/ "\003\000\002"
  3683. "GDT HA %u, CPU temperature critical",
  3684. /*55*/ "\003\000\002"
  3685. "GDT HA %u, CPU temperature OK",
  3686. /*56*/ "\005\000\002\006\004"
  3687. "GDT HA %u, Host drive %lu created",
  3688. /*57*/ "\005\000\002\006\002"
  3689. "GDT HA %u, Array Drive %u: expand restarted",
  3690. /*58*/ "\005\000\002\006\002"
  3691. "GDT HA %u, Array Drive %u: expand stopped",
  3692. /*59*/ "\005\000\002\010\002"
  3693. "GDT HA %u, Mirror Drive %u: drive build quited",
  3694. /*60*/ "\005\000\002\006\002"
  3695. "GDT HA %u, Array Drive %u: parity build quited",
  3696. /*61*/ "\005\000\002\006\002"
  3697. "GDT HA %u, Array Drive %u: drive rebuild quited",
  3698. /*62*/ "\005\000\002\006\002"
  3699. "GDT HA %u, Array Drive %u: parity verify started",
  3700. /*63*/ "\005\000\002\006\002"
  3701. "GDT HA %u, Array Drive %u: parity verify done",
  3702. /*64*/ "\005\000\002\006\002"
  3703. "GDT HA %u, Array Drive %u: parity verify failed",
  3704. /*65*/ "\005\000\002\006\002"
  3705. "GDT HA %u, Array Drive %u: parity error detected",
  3706. /*66*/ "\005\000\002\006\002"
  3707. "GDT HA %u, Array Drive %u: parity verify quited",
  3708. /*67*/ "\005\000\002\006\002"
  3709. "GDT HA %u, Host Drive %u reserved",
  3710. /*68*/ "\005\000\002\006\002"
  3711. "GDT HA %u, Host Drive %u mounted and released",
  3712. /*69*/ "\005\000\002\006\002"
  3713. "GDT HA %u, Host Drive %u released",
  3714. /*70*/ "\003\000\002"
  3715. "GDT HA %u, DRAM error detected and corrected with ECC",
  3716. /*71*/ "\003\000\002"
  3717. "GDT HA %u, Uncorrectable DRAM error detected with ECC",
  3718. /*72*/ "\011\000\002\012\001\013\001\014\001"
  3719. "GDT HA %u, SCSI bus %u, ID %u, LUN %u: reassigning block",
  3720. /*73*/ "\005\000\002\006\002"
  3721. "GDT HA %u, Host drive %u resetted locally",
  3722. /*74*/ "\005\000\002\006\002"
  3723. "GDT HA %u, Host drive %u resetted remotely",
  3724. /*75*/ "\003\000\002"
  3725. "GDT HA %u, async. status 75 unknown",
  3726. };
  3727. static int gdth_async_event(int hanum)
  3728. {
  3729. gdth_ha_str *ha;
  3730. gdth_cmd_str *cmdp;
  3731. int cmd_index;
  3732. ha = HADATA(gdth_ctr_tab[hanum]);
  3733. cmdp= ha->pccb;
  3734. TRACE2(("gdth_async_event() ha %d serv %d\n",
  3735. hanum,ha->service));
  3736. if (ha->service == SCREENSERVICE) {
  3737. if (ha->status == MSG_REQUEST) {
  3738. while (gdth_test_busy(hanum))
  3739. gdth_delay(0);
  3740. cmdp->Service = SCREENSERVICE;
  3741. cmdp->RequestBuffer = SCREEN_CMND;
  3742. cmd_index = gdth_get_cmd_index(hanum);
  3743. gdth_set_sema0(hanum);
  3744. cmdp->OpCode = GDT_READ;
  3745. cmdp->BoardNode = LOCALBOARD;
  3746. cmdp->u.screen.reserved = 0;
  3747. cmdp->u.screen.su.msg.msg_handle= MSG_INV_HANDLE;
  3748. cmdp->u.screen.su.msg.msg_addr = ha->msg_phys;
  3749. ha->cmd_offs_dpmem = 0;
  3750. ha->cmd_len = GDTOFFSOF(gdth_cmd_str,u.screen.su.msg.msg_addr)
  3751. + sizeof(ulong64);
  3752. ha->cmd_cnt = 0;
  3753. gdth_copy_command(hanum);
  3754. if (ha->type == GDT_EISA)
  3755. printk("[EISA slot %d] ",(ushort)ha->brd_phys);
  3756. else if (ha->type == GDT_ISA)
  3757. printk("[DPMEM 0x%4X] ",(ushort)ha->brd_phys);
  3758. else
  3759. printk("[PCI %d/%d] ",(ushort)(ha->brd_phys>>8),
  3760. (ushort)((ha->brd_phys>>3)&0x1f));
  3761. gdth_release_event(hanum);
  3762. }
  3763. } else {
  3764. if (ha->type == GDT_PCIMPR &&
  3765. (ha->fw_vers & 0xff) >= 0x1a) {
  3766. ha->dvr.size = 0;
  3767. ha->dvr.eu.async.ionode = hanum;
  3768. ha->dvr.eu.async.status = ha->status;
  3769. /* severity and event_string already set! */
  3770. } else {
  3771. ha->dvr.size = sizeof(ha->dvr.eu.async);
  3772. ha->dvr.eu.async.ionode = hanum;
  3773. ha->dvr.eu.async.service = ha->service;
  3774. ha->dvr.eu.async.status = ha->status;
  3775. ha->dvr.eu.async.info = ha->info;
  3776. *(ulong32 *)ha->dvr.eu.async.scsi_coord = ha->info2;
  3777. }
  3778. gdth_store_event( ha, ES_ASYNC, ha->service, &ha->dvr );
  3779. gdth_log_event( &ha->dvr, NULL );
  3780. /* new host drive from expand? */
  3781. if (ha->service == CACHESERVICE && ha->status == 56) {
  3782. TRACE2(("gdth_async_event(): new host drive %d created\n",
  3783. (ushort)ha->info));
  3784. /* gdth_analyse_hdrive(hanum, (ushort)ha->info); */
  3785. }
  3786. }
  3787. return 1;
  3788. }
  3789. static void gdth_log_event(gdth_evt_data *dvr, char *buffer)
  3790. {
  3791. gdth_stackframe stack;
  3792. char *f = NULL;
  3793. int i,j;
  3794. TRACE2(("gdth_log_event()\n"));
  3795. if (dvr->size == 0) {
  3796. if (buffer == NULL) {
  3797. printk("Adapter %d: %s\n",dvr->eu.async.ionode,dvr->event_string);
  3798. } else {
  3799. sprintf(buffer,"Adapter %d: %s\n",
  3800. dvr->eu.async.ionode,dvr->event_string);
  3801. }
  3802. } else if (dvr->eu.async.service == CACHESERVICE &&
  3803. INDEX_OK(dvr->eu.async.status, async_cache_tab)) {
  3804. TRACE2(("GDT: Async. event cache service, event no.: %d\n",
  3805. dvr->eu.async.status));
  3806. f = async_cache_tab[dvr->eu.async.status];
  3807. /* i: parameter to push, j: stack element to fill */
  3808. for (j=0,i=1; i < f[0]; i+=2) {
  3809. switch (f[i+1]) {
  3810. case 4:
  3811. stack.b[j++] = *(ulong32*)&dvr->eu.stream[(int)f[i]];
  3812. break;
  3813. case 2:
  3814. stack.b[j++] = *(ushort*)&dvr->eu.stream[(int)f[i]];
  3815. break;
  3816. case 1:
  3817. stack.b[j++] = *(unchar*)&dvr->eu.stream[(int)f[i]];
  3818. break;
  3819. default:
  3820. break;
  3821. }
  3822. }
  3823. if (buffer == NULL) {
  3824. printk(&f[(int)f[0]],stack);
  3825. printk("\n");
  3826. } else {
  3827. sprintf(buffer,&f[(int)f[0]],stack);
  3828. }
  3829. } else {
  3830. if (buffer == NULL) {
  3831. printk("GDT HA %u, Unknown async. event service %d event no. %d\n",
  3832. dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
  3833. } else {
  3834. sprintf(buffer,"GDT HA %u, Unknown async. event service %d event no. %d",
  3835. dvr->eu.async.ionode,dvr->eu.async.service,dvr->eu.async.status);
  3836. }
  3837. }
  3838. }
  3839. #ifdef GDTH_STATISTICS
  3840. static void gdth_timeout(ulong data)
  3841. {
  3842. ulong32 i;
  3843. Scsi_Cmnd *nscp;
  3844. gdth_ha_str *ha;
  3845. ulong flags;
  3846. int hanum = 0;
  3847. ha = HADATA(gdth_ctr_tab[hanum]);
  3848. spin_lock_irqsave(&ha->smp_lock, flags);
  3849. for (act_stats=0,i=0; i<GDTH_MAXCMDS; ++i)
  3850. if (ha->cmd_tab[i].cmnd != UNUSED_CMND)
  3851. ++act_stats;
  3852. for (act_rq=0,nscp=ha->req_first; nscp; nscp=(Scsi_Cmnd*)nscp->SCp.ptr)
  3853. ++act_rq;
  3854. TRACE2(("gdth_to(): ints %d, ios %d, act_stats %d, act_rq %d\n",
  3855. act_ints, act_ios, act_stats, act_rq));
  3856. act_ints = act_ios = 0;
  3857. gdth_timer.expires = jiffies + 30 * HZ;
  3858. add_timer(&gdth_timer);
  3859. spin_unlock_irqrestore(&ha->smp_lock, flags);
  3860. }
  3861. #endif
  3862. static void __init internal_setup(char *str,int *ints)
  3863. {
  3864. int i, argc;
  3865. char *cur_str, *argv;
  3866. TRACE2(("internal_setup() str %s ints[0] %d\n",
  3867. str ? str:"NULL", ints ? ints[0]:0));
  3868. /* read irq[] from ints[] */
  3869. if (ints) {
  3870. argc = ints[0];
  3871. if (argc > 0) {
  3872. if (argc > MAXHA)
  3873. argc = MAXHA;
  3874. for (i = 0; i < argc; ++i)
  3875. irq[i] = ints[i+1];
  3876. }
  3877. }
  3878. /* analyse string */
  3879. argv = str;
  3880. while (argv && (cur_str = strchr(argv, ':'))) {
  3881. int val = 0, c = *++cur_str;
  3882. if (c == 'n' || c == 'N')
  3883. val = 0;
  3884. else if (c == 'y' || c == 'Y')
  3885. val = 1;
  3886. else
  3887. val = (int)simple_strtoul(cur_str, NULL, 0);
  3888. if (!strncmp(argv, "disable:", 8))
  3889. disable = val;
  3890. else if (!strncmp(argv, "reserve_mode:", 13))
  3891. reserve_mode = val;
  3892. else if (!strncmp(argv, "reverse_scan:", 13))
  3893. reverse_scan = val;
  3894. else if (!strncmp(argv, "hdr_channel:", 12))
  3895. hdr_channel = val;
  3896. else if (!strncmp(argv, "max_ids:", 8))
  3897. max_ids = val;
  3898. else if (!strncmp(argv, "rescan:", 7))
  3899. rescan = val;
  3900. else if (!strncmp(argv, "virt_ctr:", 9))
  3901. virt_ctr = val;
  3902. else if (!strncmp(argv, "shared_access:", 14))
  3903. shared_access = val;
  3904. else if (!strncmp(argv, "probe_eisa_isa:", 15))
  3905. probe_eisa_isa = val;
  3906. else if (!strncmp(argv, "reserve_list:", 13)) {
  3907. reserve_list[0] = val;
  3908. for (i = 1; i < MAX_RES_ARGS; i++) {
  3909. cur_str = strchr(cur_str, ',');
  3910. if (!cur_str)
  3911. break;
  3912. if (!isdigit((int)*++cur_str)) {
  3913. --cur_str;
  3914. break;
  3915. }
  3916. reserve_list[i] =
  3917. (int)simple_strtoul(cur_str, NULL, 0);
  3918. }
  3919. if (!cur_str)
  3920. break;
  3921. argv = ++cur_str;
  3922. continue;
  3923. }
  3924. if ((argv = strchr(argv, ',')))
  3925. ++argv;
  3926. }
  3927. }
  3928. int __init option_setup(char *str)
  3929. {
  3930. int ints[MAXHA];
  3931. char *cur = str;
  3932. int i = 1;
  3933. TRACE2(("option_setup() str %s\n", str ? str:"NULL"));
  3934. while (cur && isdigit(*cur) && i <= MAXHA) {
  3935. ints[i++] = simple_strtoul(cur, NULL, 0);
  3936. if ((cur = strchr(cur, ',')) != NULL) cur++;
  3937. }
  3938. ints[0] = i - 1;
  3939. internal_setup(cur, ints);
  3940. return 1;
  3941. }
  3942. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  3943. static int __init gdth_detect(struct scsi_host_template *shtp)
  3944. #else
  3945. static int __init gdth_detect(Scsi_Host_Template *shtp)
  3946. #endif
  3947. {
  3948. struct Scsi_Host *shp;
  3949. gdth_pci_str pcistr[MAXHA];
  3950. gdth_ha_str *ha;
  3951. int i,hanum,cnt,ctr,err;
  3952. unchar b;
  3953. #ifdef DEBUG_GDTH
  3954. printk("GDT: This driver contains debugging information !! Trace level = %d\n",
  3955. DebugState);
  3956. printk(" Destination of debugging information: ");
  3957. #ifdef __SERIAL__
  3958. #ifdef __COM2__
  3959. printk("Serial port COM2\n");
  3960. #else
  3961. printk("Serial port COM1\n");
  3962. #endif
  3963. #else
  3964. printk("Console\n");
  3965. #endif
  3966. gdth_delay(3000);
  3967. #endif
  3968. TRACE(("gdth_detect()\n"));
  3969. if (disable) {
  3970. printk("GDT-HA: Controller driver disabled from command line !\n");
  3971. return 0;
  3972. }
  3973. printk("GDT-HA: Storage RAID Controller Driver. Version: %s\n",GDTH_VERSION_STR);
  3974. /* initializations */
  3975. gdth_polling = TRUE; b = 0;
  3976. gdth_clear_events();
  3977. /* As default we do not probe for EISA or ISA controllers */
  3978. if (probe_eisa_isa) {
  3979. /* scanning for controllers, at first: ISA controller */
  3980. #ifdef CONFIG_ISA
  3981. ulong32 isa_bios;
  3982. for (isa_bios = 0xc8000UL; isa_bios <= 0xd8000UL;
  3983. isa_bios += 0x8000UL) {
  3984. if (gdth_ctr_count >= MAXHA)
  3985. break;
  3986. gdth_isa_probe_one(shtp, isa_bios);
  3987. }
  3988. #endif
  3989. #ifdef CONFIG_EISA
  3990. {
  3991. ushort eisa_slot;
  3992. for (eisa_slot = 0x1000; eisa_slot <= 0x8000; eisa_slot += 0x1000) {
  3993. if (gdth_ctr_count >= MAXHA)
  3994. break;
  3995. gdth_eisa_probe_one(shtp, eisa_slot);
  3996. }
  3997. }
  3998. #endif
  3999. }
  4000. /* scanning for PCI controllers */
  4001. cnt = gdth_search_pci(pcistr);
  4002. printk("GDT-HA: Found %d PCI Storage RAID Controllers\n",cnt);
  4003. gdth_sort_pci(pcistr,cnt);
  4004. for (ctr = 0; ctr < cnt; ++ctr) {
  4005. dma_addr_t scratch_dma_handle;
  4006. scratch_dma_handle = 0;
  4007. if (gdth_ctr_count >= MAXHA)
  4008. break;
  4009. shp = scsi_register(shtp,sizeof(gdth_ext_str));
  4010. if (shp == NULL)
  4011. continue;
  4012. ha = HADATA(shp);
  4013. if (!gdth_init_pci(&pcistr[ctr],ha)) {
  4014. scsi_unregister(shp);
  4015. continue;
  4016. }
  4017. /* controller found and initialized */
  4018. printk("Configuring GDT-PCI HA at %d/%d IRQ %u\n",
  4019. pcistr[ctr].pdev->bus->number,
  4020. PCI_SLOT(pcistr[ctr].pdev->devfn), ha->irq);
  4021. if (request_irq(ha->irq, gdth_interrupt,
  4022. IRQF_DISABLED|IRQF_SHARED, "gdth", ha))
  4023. {
  4024. printk("GDT-PCI: Unable to allocate IRQ\n");
  4025. scsi_unregister(shp);
  4026. continue;
  4027. }
  4028. shp->unchecked_isa_dma = 0;
  4029. shp->irq = ha->irq;
  4030. shp->dma_channel = 0xff;
  4031. hanum = gdth_ctr_count;
  4032. gdth_ctr_tab[gdth_ctr_count++] = shp;
  4033. gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
  4034. NUMDATA(shp)->hanum = (ushort)hanum;
  4035. NUMDATA(shp)->busnum= 0;
  4036. ha->pccb = CMDDATA(shp);
  4037. ha->ccb_phys = 0L;
  4038. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  4039. &scratch_dma_handle);
  4040. ha->scratch_phys = scratch_dma_handle;
  4041. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  4042. &scratch_dma_handle);
  4043. ha->msg_phys = scratch_dma_handle;
  4044. #ifdef INT_COAL
  4045. ha->coal_stat = (gdth_coal_status *)
  4046. pci_alloc_consistent(ha->pdev, sizeof(gdth_coal_status) *
  4047. MAXOFFSETS, &scratch_dma_handle);
  4048. ha->coal_stat_phys = scratch_dma_handle;
  4049. #endif
  4050. ha->scratch_busy = FALSE;
  4051. ha->req_first = NULL;
  4052. ha->tid_cnt = pcistr[ctr].pdev->device >= 0x200 ? MAXID : MAX_HDRIVES;
  4053. if (max_ids > 0 && max_ids < ha->tid_cnt)
  4054. ha->tid_cnt = max_ids;
  4055. for (i=0; i<GDTH_MAXCMDS; ++i)
  4056. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4057. ha->scan_mode = rescan ? 0x10 : 0;
  4058. err = FALSE;
  4059. if (ha->pscratch == NULL || ha->pmsg == NULL ||
  4060. !gdth_search_drives(hanum)) {
  4061. err = TRUE;
  4062. } else {
  4063. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  4064. hdr_channel = ha->bus_cnt;
  4065. ha->virt_bus = hdr_channel;
  4066. #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
  4067. scsi_set_pci_device(shp, pcistr[ctr].pdev);
  4068. #endif
  4069. if (!(ha->cache_feat & ha->raw_feat & ha->screen_feat &GDT_64BIT)||
  4070. /* 64-bit DMA only supported from FW >= x.43 */
  4071. (!ha->dma64_support)) {
  4072. if (pci_set_dma_mask(pcistr[ctr].pdev, DMA_32BIT_MASK)) {
  4073. printk(KERN_WARNING "GDT-PCI %d: Unable to set 32-bit DMA\n", hanum);
  4074. err = TRUE;
  4075. }
  4076. } else {
  4077. shp->max_cmd_len = 16;
  4078. if (!pci_set_dma_mask(pcistr[ctr].pdev, DMA_64BIT_MASK)) {
  4079. printk("GDT-PCI %d: 64-bit DMA enabled\n", hanum);
  4080. } else if (pci_set_dma_mask(pcistr[ctr].pdev, DMA_32BIT_MASK)) {
  4081. printk(KERN_WARNING "GDT-PCI %d: Unable to set 64/32-bit DMA\n", hanum);
  4082. err = TRUE;
  4083. }
  4084. }
  4085. }
  4086. if (err) {
  4087. printk("GDT-PCI %d: Error during device scan\n", hanum);
  4088. --gdth_ctr_count;
  4089. --gdth_ctr_vcount;
  4090. #ifdef INT_COAL
  4091. if (ha->coal_stat)
  4092. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
  4093. MAXOFFSETS, ha->coal_stat,
  4094. ha->coal_stat_phys);
  4095. #endif
  4096. if (ha->pscratch)
  4097. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4098. ha->pscratch, ha->scratch_phys);
  4099. if (ha->pmsg)
  4100. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4101. ha->pmsg, ha->msg_phys);
  4102. free_irq(ha->irq,ha);
  4103. scsi_unregister(shp);
  4104. continue;
  4105. }
  4106. shp->max_id = ha->tid_cnt;
  4107. shp->max_lun = MAXLUN;
  4108. shp->max_channel = virt_ctr ? 0 : ha->bus_cnt;
  4109. if (virt_ctr) {
  4110. virt_ctr = 1;
  4111. /* register addit. SCSI channels as virtual controllers */
  4112. for (b = 1; b < ha->bus_cnt + 1; ++b) {
  4113. shp = scsi_register(shtp,sizeof(gdth_num_str));
  4114. shp->unchecked_isa_dma = 0;
  4115. shp->irq = ha->irq;
  4116. shp->dma_channel = 0xff;
  4117. gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
  4118. NUMDATA(shp)->hanum = (ushort)hanum;
  4119. NUMDATA(shp)->busnum = b;
  4120. }
  4121. }
  4122. spin_lock_init(&ha->smp_lock);
  4123. gdth_enable_int(hanum);
  4124. }
  4125. TRACE2(("gdth_detect() %d controller detected\n",gdth_ctr_count));
  4126. if (gdth_ctr_count > 0) {
  4127. #ifdef GDTH_STATISTICS
  4128. TRACE2(("gdth_detect(): Initializing timer !\n"));
  4129. init_timer(&gdth_timer);
  4130. gdth_timer.expires = jiffies + HZ;
  4131. gdth_timer.data = 0L;
  4132. gdth_timer.function = gdth_timeout;
  4133. add_timer(&gdth_timer);
  4134. #endif
  4135. major = register_chrdev(0,"gdth",&gdth_fops);
  4136. notifier_disabled = 0;
  4137. register_reboot_notifier(&gdth_notifier);
  4138. }
  4139. gdth_polling = FALSE;
  4140. return gdth_ctr_vcount;
  4141. }
  4142. static int gdth_release(struct Scsi_Host *shp)
  4143. {
  4144. int hanum;
  4145. gdth_ha_str *ha;
  4146. TRACE2(("gdth_release()\n"));
  4147. if (NUMDATA(shp)->busnum == 0) {
  4148. hanum = NUMDATA(shp)->hanum;
  4149. ha = HADATA(gdth_ctr_tab[hanum]);
  4150. if (ha->sdev) {
  4151. scsi_free_host_dev(ha->sdev);
  4152. ha->sdev = NULL;
  4153. }
  4154. gdth_flush(hanum);
  4155. if (shp->irq) {
  4156. free_irq(shp->irq,ha);
  4157. }
  4158. #ifdef CONFIG_ISA
  4159. if (shp->dma_channel != 0xff) {
  4160. free_dma(shp->dma_channel);
  4161. }
  4162. #endif
  4163. #ifdef INT_COAL
  4164. if (ha->coal_stat)
  4165. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) *
  4166. MAXOFFSETS, ha->coal_stat, ha->coal_stat_phys);
  4167. #endif
  4168. if (ha->pscratch)
  4169. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  4170. ha->pscratch, ha->scratch_phys);
  4171. if (ha->pmsg)
  4172. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  4173. ha->pmsg, ha->msg_phys);
  4174. if (ha->ccb_phys)
  4175. pci_unmap_single(ha->pdev,ha->ccb_phys,
  4176. sizeof(gdth_cmd_str),PCI_DMA_BIDIRECTIONAL);
  4177. gdth_ctr_released++;
  4178. TRACE2(("gdth_release(): HA %d of %d\n",
  4179. gdth_ctr_released, gdth_ctr_count));
  4180. if (gdth_ctr_released == gdth_ctr_count) {
  4181. #ifdef GDTH_STATISTICS
  4182. del_timer(&gdth_timer);
  4183. #endif
  4184. unregister_chrdev(major,"gdth");
  4185. unregister_reboot_notifier(&gdth_notifier);
  4186. }
  4187. }
  4188. scsi_unregister(shp);
  4189. return 0;
  4190. }
  4191. static const char *gdth_ctr_name(int hanum)
  4192. {
  4193. gdth_ha_str *ha;
  4194. TRACE2(("gdth_ctr_name()\n"));
  4195. ha = HADATA(gdth_ctr_tab[hanum]);
  4196. if (ha->type == GDT_EISA) {
  4197. switch (ha->stype) {
  4198. case GDT3_ID:
  4199. return("GDT3000/3020");
  4200. case GDT3A_ID:
  4201. return("GDT3000A/3020A/3050A");
  4202. case GDT3B_ID:
  4203. return("GDT3000B/3010A");
  4204. }
  4205. } else if (ha->type == GDT_ISA) {
  4206. return("GDT2000/2020");
  4207. } else if (ha->type == GDT_PCI) {
  4208. switch (ha->pdev->device) {
  4209. case PCI_DEVICE_ID_VORTEX_GDT60x0:
  4210. return("GDT6000/6020/6050");
  4211. case PCI_DEVICE_ID_VORTEX_GDT6000B:
  4212. return("GDT6000B/6010");
  4213. }
  4214. }
  4215. /* new controllers (GDT_PCINEW, GDT_PCIMPR, ..) use board_info IOCTL! */
  4216. return("");
  4217. }
  4218. static const char *gdth_info(struct Scsi_Host *shp)
  4219. {
  4220. int hanum;
  4221. gdth_ha_str *ha;
  4222. TRACE2(("gdth_info()\n"));
  4223. hanum = NUMDATA(shp)->hanum;
  4224. ha = HADATA(gdth_ctr_tab[hanum]);
  4225. return ((const char *)ha->binfo.type_string);
  4226. }
  4227. static int gdth_eh_bus_reset(Scsi_Cmnd *scp)
  4228. {
  4229. int i, hanum;
  4230. gdth_ha_str *ha;
  4231. ulong flags;
  4232. Scsi_Cmnd *cmnd;
  4233. unchar b;
  4234. TRACE2(("gdth_eh_bus_reset()\n"));
  4235. hanum = NUMDATA(scp->device->host)->hanum;
  4236. b = virt_ctr ? NUMDATA(scp->device->host)->busnum : scp->device->channel;
  4237. ha = HADATA(gdth_ctr_tab[hanum]);
  4238. /* clear command tab */
  4239. spin_lock_irqsave(&ha->smp_lock, flags);
  4240. for (i = 0; i < GDTH_MAXCMDS; ++i) {
  4241. cmnd = ha->cmd_tab[i].cmnd;
  4242. if (!SPECIAL_SCP(cmnd) && cmnd->device->channel == b)
  4243. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  4244. }
  4245. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4246. if (b == ha->virt_bus) {
  4247. /* host drives */
  4248. for (i = 0; i < MAX_HDRIVES; ++i) {
  4249. if (ha->hdr[i].present) {
  4250. spin_lock_irqsave(&ha->smp_lock, flags);
  4251. gdth_polling = TRUE;
  4252. while (gdth_test_busy(hanum))
  4253. gdth_delay(0);
  4254. if (gdth_internal_cmd(hanum, CACHESERVICE,
  4255. GDT_CLUST_RESET, i, 0, 0))
  4256. ha->hdr[i].cluster_type &= ~CLUSTER_RESERVED;
  4257. gdth_polling = FALSE;
  4258. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4259. }
  4260. }
  4261. } else {
  4262. /* raw devices */
  4263. spin_lock_irqsave(&ha->smp_lock, flags);
  4264. for (i = 0; i < MAXID; ++i)
  4265. ha->raw[BUS_L2P(ha,b)].io_cnt[i] = 0;
  4266. gdth_polling = TRUE;
  4267. while (gdth_test_busy(hanum))
  4268. gdth_delay(0);
  4269. gdth_internal_cmd(hanum, SCSIRAWSERVICE, GDT_RESET_BUS,
  4270. BUS_L2P(ha,b), 0, 0);
  4271. gdth_polling = FALSE;
  4272. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4273. }
  4274. return SUCCESS;
  4275. }
  4276. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4277. static int gdth_bios_param(struct scsi_device *sdev,struct block_device *bdev,sector_t cap,int *ip)
  4278. #else
  4279. static int gdth_bios_param(Disk *disk,kdev_t dev,int *ip)
  4280. #endif
  4281. {
  4282. unchar b, t;
  4283. int hanum;
  4284. gdth_ha_str *ha;
  4285. struct scsi_device *sd;
  4286. unsigned capacity;
  4287. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4288. sd = sdev;
  4289. capacity = cap;
  4290. #else
  4291. sd = disk->device;
  4292. capacity = disk->capacity;
  4293. #endif
  4294. hanum = NUMDATA(sd->host)->hanum;
  4295. b = virt_ctr ? NUMDATA(sd->host)->busnum : sd->channel;
  4296. t = sd->id;
  4297. TRACE2(("gdth_bios_param() ha %d bus %d target %d\n", hanum, b, t));
  4298. ha = HADATA(gdth_ctr_tab[hanum]);
  4299. if (b != ha->virt_bus || ha->hdr[t].heads == 0) {
  4300. /* raw device or host drive without mapping information */
  4301. TRACE2(("Evaluate mapping\n"));
  4302. gdth_eval_mapping(capacity,&ip[2],&ip[0],&ip[1]);
  4303. } else {
  4304. ip[0] = ha->hdr[t].heads;
  4305. ip[1] = ha->hdr[t].secs;
  4306. ip[2] = capacity / ip[0] / ip[1];
  4307. }
  4308. TRACE2(("gdth_bios_param(): %d heads, %d secs, %d cyls\n",
  4309. ip[0],ip[1],ip[2]));
  4310. return 0;
  4311. }
  4312. static int gdth_queuecommand(struct scsi_cmnd *scp,
  4313. void (*done)(struct scsi_cmnd *))
  4314. {
  4315. int hanum;
  4316. int priority;
  4317. TRACE(("gdth_queuecommand() cmd 0x%x\n", scp->cmnd[0]));
  4318. scp->scsi_done = done;
  4319. scp->SCp.have_data_in = 1;
  4320. scp->SCp.phase = -1;
  4321. scp->SCp.sent_command = -1;
  4322. scp->SCp.Status = GDTH_MAP_NONE;
  4323. scp->SCp.buffer = (struct scatterlist *)NULL;
  4324. hanum = NUMDATA(scp->device->host)->hanum;
  4325. #ifdef GDTH_STATISTICS
  4326. ++act_ios;
  4327. #endif
  4328. priority = DEFAULT_PRI;
  4329. if (IS_GDTH_INTERNAL_CMD(scp))
  4330. priority = scp->SCp.this_residual;
  4331. else
  4332. gdth_update_timeout(hanum, scp, scp->timeout_per_command * 6);
  4333. gdth_putq( hanum, scp, priority );
  4334. gdth_next( hanum );
  4335. return 0;
  4336. }
  4337. static int gdth_open(struct inode *inode, struct file *filep)
  4338. {
  4339. gdth_ha_str *ha;
  4340. int i;
  4341. for (i = 0; i < gdth_ctr_count; i++) {
  4342. ha = HADATA(gdth_ctr_tab[i]);
  4343. if (!ha->sdev)
  4344. ha->sdev = scsi_get_host_dev(gdth_ctr_tab[i]);
  4345. }
  4346. TRACE(("gdth_open()\n"));
  4347. return 0;
  4348. }
  4349. static int gdth_close(struct inode *inode, struct file *filep)
  4350. {
  4351. TRACE(("gdth_close()\n"));
  4352. return 0;
  4353. }
  4354. static int ioc_event(void __user *arg)
  4355. {
  4356. gdth_ioctl_event evt;
  4357. gdth_ha_str *ha;
  4358. ulong flags;
  4359. if (copy_from_user(&evt, arg, sizeof(gdth_ioctl_event)) ||
  4360. evt.ionode >= gdth_ctr_count)
  4361. return -EFAULT;
  4362. ha = HADATA(gdth_ctr_tab[evt.ionode]);
  4363. if (evt.erase == 0xff) {
  4364. if (evt.event.event_source == ES_TEST)
  4365. evt.event.event_data.size=sizeof(evt.event.event_data.eu.test);
  4366. else if (evt.event.event_source == ES_DRIVER)
  4367. evt.event.event_data.size=sizeof(evt.event.event_data.eu.driver);
  4368. else if (evt.event.event_source == ES_SYNC)
  4369. evt.event.event_data.size=sizeof(evt.event.event_data.eu.sync);
  4370. else
  4371. evt.event.event_data.size=sizeof(evt.event.event_data.eu.async);
  4372. spin_lock_irqsave(&ha->smp_lock, flags);
  4373. gdth_store_event(ha, evt.event.event_source, evt.event.event_idx,
  4374. &evt.event.event_data);
  4375. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4376. } else if (evt.erase == 0xfe) {
  4377. gdth_clear_events();
  4378. } else if (evt.erase == 0) {
  4379. evt.handle = gdth_read_event(ha, evt.handle, &evt.event);
  4380. } else {
  4381. gdth_readapp_event(ha, evt.erase, &evt.event);
  4382. }
  4383. if (copy_to_user(arg, &evt, sizeof(gdth_ioctl_event)))
  4384. return -EFAULT;
  4385. return 0;
  4386. }
  4387. static int ioc_lockdrv(void __user *arg)
  4388. {
  4389. gdth_ioctl_lockdrv ldrv;
  4390. unchar i, j;
  4391. ulong flags;
  4392. gdth_ha_str *ha;
  4393. if (copy_from_user(&ldrv, arg, sizeof(gdth_ioctl_lockdrv)) ||
  4394. ldrv.ionode >= gdth_ctr_count)
  4395. return -EFAULT;
  4396. ha = HADATA(gdth_ctr_tab[ldrv.ionode]);
  4397. for (i = 0; i < ldrv.drive_cnt && i < MAX_HDRIVES; ++i) {
  4398. j = ldrv.drives[i];
  4399. if (j >= MAX_HDRIVES || !ha->hdr[j].present)
  4400. continue;
  4401. if (ldrv.lock) {
  4402. spin_lock_irqsave(&ha->smp_lock, flags);
  4403. ha->hdr[j].lock = 1;
  4404. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4405. gdth_wait_completion(ldrv.ionode, ha->bus_cnt, j);
  4406. gdth_stop_timeout(ldrv.ionode, ha->bus_cnt, j);
  4407. } else {
  4408. spin_lock_irqsave(&ha->smp_lock, flags);
  4409. ha->hdr[j].lock = 0;
  4410. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4411. gdth_start_timeout(ldrv.ionode, ha->bus_cnt, j);
  4412. gdth_next(ldrv.ionode);
  4413. }
  4414. }
  4415. return 0;
  4416. }
  4417. static int ioc_resetdrv(void __user *arg, char *cmnd)
  4418. {
  4419. gdth_ioctl_reset res;
  4420. gdth_cmd_str cmd;
  4421. int hanum;
  4422. gdth_ha_str *ha;
  4423. int rval;
  4424. if (copy_from_user(&res, arg, sizeof(gdth_ioctl_reset)) ||
  4425. res.ionode >= gdth_ctr_count || res.number >= MAX_HDRIVES)
  4426. return -EFAULT;
  4427. hanum = res.ionode;
  4428. ha = HADATA(gdth_ctr_tab[hanum]);
  4429. if (!ha->hdr[res.number].present)
  4430. return 0;
  4431. memset(&cmd, 0, sizeof(gdth_cmd_str));
  4432. cmd.Service = CACHESERVICE;
  4433. cmd.OpCode = GDT_CLUST_RESET;
  4434. if (ha->cache_feat & GDT_64BIT)
  4435. cmd.u.cache64.DeviceNo = res.number;
  4436. else
  4437. cmd.u.cache.DeviceNo = res.number;
  4438. rval = __gdth_execute(ha->sdev, &cmd, cmnd, 30, NULL);
  4439. if (rval < 0)
  4440. return rval;
  4441. res.status = rval;
  4442. if (copy_to_user(arg, &res, sizeof(gdth_ioctl_reset)))
  4443. return -EFAULT;
  4444. return 0;
  4445. }
  4446. static int ioc_general(void __user *arg, char *cmnd)
  4447. {
  4448. gdth_ioctl_general gen;
  4449. char *buf = NULL;
  4450. ulong64 paddr;
  4451. int hanum;
  4452. gdth_ha_str *ha;
  4453. int rval;
  4454. if (copy_from_user(&gen, arg, sizeof(gdth_ioctl_general)) ||
  4455. gen.ionode >= gdth_ctr_count)
  4456. return -EFAULT;
  4457. hanum = gen.ionode;
  4458. ha = HADATA(gdth_ctr_tab[hanum]);
  4459. if (gen.data_len + gen.sense_len != 0) {
  4460. if (!(buf = gdth_ioctl_alloc(hanum, gen.data_len + gen.sense_len,
  4461. FALSE, &paddr)))
  4462. return -EFAULT;
  4463. if (copy_from_user(buf, arg + sizeof(gdth_ioctl_general),
  4464. gen.data_len + gen.sense_len)) {
  4465. gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
  4466. return -EFAULT;
  4467. }
  4468. if (gen.command.OpCode == GDT_IOCTL) {
  4469. gen.command.u.ioctl.p_param = paddr;
  4470. } else if (gen.command.Service == CACHESERVICE) {
  4471. if (ha->cache_feat & GDT_64BIT) {
  4472. /* copy elements from 32-bit IOCTL structure */
  4473. gen.command.u.cache64.BlockCnt = gen.command.u.cache.BlockCnt;
  4474. gen.command.u.cache64.BlockNo = gen.command.u.cache.BlockNo;
  4475. gen.command.u.cache64.DeviceNo = gen.command.u.cache.DeviceNo;
  4476. /* addresses */
  4477. if (ha->cache_feat & SCATTER_GATHER) {
  4478. gen.command.u.cache64.DestAddr = (ulong64)-1;
  4479. gen.command.u.cache64.sg_canz = 1;
  4480. gen.command.u.cache64.sg_lst[0].sg_ptr = paddr;
  4481. gen.command.u.cache64.sg_lst[0].sg_len = gen.data_len;
  4482. gen.command.u.cache64.sg_lst[1].sg_len = 0;
  4483. } else {
  4484. gen.command.u.cache64.DestAddr = paddr;
  4485. gen.command.u.cache64.sg_canz = 0;
  4486. }
  4487. } else {
  4488. if (ha->cache_feat & SCATTER_GATHER) {
  4489. gen.command.u.cache.DestAddr = 0xffffffff;
  4490. gen.command.u.cache.sg_canz = 1;
  4491. gen.command.u.cache.sg_lst[0].sg_ptr = (ulong32)paddr;
  4492. gen.command.u.cache.sg_lst[0].sg_len = gen.data_len;
  4493. gen.command.u.cache.sg_lst[1].sg_len = 0;
  4494. } else {
  4495. gen.command.u.cache.DestAddr = paddr;
  4496. gen.command.u.cache.sg_canz = 0;
  4497. }
  4498. }
  4499. } else if (gen.command.Service == SCSIRAWSERVICE) {
  4500. if (ha->raw_feat & GDT_64BIT) {
  4501. /* copy elements from 32-bit IOCTL structure */
  4502. char cmd[16];
  4503. gen.command.u.raw64.sense_len = gen.command.u.raw.sense_len;
  4504. gen.command.u.raw64.bus = gen.command.u.raw.bus;
  4505. gen.command.u.raw64.lun = gen.command.u.raw.lun;
  4506. gen.command.u.raw64.target = gen.command.u.raw.target;
  4507. memcpy(cmd, gen.command.u.raw.cmd, 16);
  4508. memcpy(gen.command.u.raw64.cmd, cmd, 16);
  4509. gen.command.u.raw64.clen = gen.command.u.raw.clen;
  4510. gen.command.u.raw64.sdlen = gen.command.u.raw.sdlen;
  4511. gen.command.u.raw64.direction = gen.command.u.raw.direction;
  4512. /* addresses */
  4513. if (ha->raw_feat & SCATTER_GATHER) {
  4514. gen.command.u.raw64.sdata = (ulong64)-1;
  4515. gen.command.u.raw64.sg_ranz = 1;
  4516. gen.command.u.raw64.sg_lst[0].sg_ptr = paddr;
  4517. gen.command.u.raw64.sg_lst[0].sg_len = gen.data_len;
  4518. gen.command.u.raw64.sg_lst[1].sg_len = 0;
  4519. } else {
  4520. gen.command.u.raw64.sdata = paddr;
  4521. gen.command.u.raw64.sg_ranz = 0;
  4522. }
  4523. gen.command.u.raw64.sense_data = paddr + gen.data_len;
  4524. } else {
  4525. if (ha->raw_feat & SCATTER_GATHER) {
  4526. gen.command.u.raw.sdata = 0xffffffff;
  4527. gen.command.u.raw.sg_ranz = 1;
  4528. gen.command.u.raw.sg_lst[0].sg_ptr = (ulong32)paddr;
  4529. gen.command.u.raw.sg_lst[0].sg_len = gen.data_len;
  4530. gen.command.u.raw.sg_lst[1].sg_len = 0;
  4531. } else {
  4532. gen.command.u.raw.sdata = paddr;
  4533. gen.command.u.raw.sg_ranz = 0;
  4534. }
  4535. gen.command.u.raw.sense_data = (ulong32)paddr + gen.data_len;
  4536. }
  4537. } else {
  4538. gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
  4539. return -EFAULT;
  4540. }
  4541. }
  4542. rval = __gdth_execute(ha->sdev, &gen.command, cmnd, gen.timeout, &gen.info);
  4543. if (rval < 0)
  4544. return rval;
  4545. gen.status = rval;
  4546. if (copy_to_user(arg + sizeof(gdth_ioctl_general), buf,
  4547. gen.data_len + gen.sense_len)) {
  4548. gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
  4549. return -EFAULT;
  4550. }
  4551. if (copy_to_user(arg, &gen,
  4552. sizeof(gdth_ioctl_general) - sizeof(gdth_cmd_str))) {
  4553. gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
  4554. return -EFAULT;
  4555. }
  4556. gdth_ioctl_free(hanum, gen.data_len+gen.sense_len, buf, paddr);
  4557. return 0;
  4558. }
  4559. static int ioc_hdrlist(void __user *arg, char *cmnd)
  4560. {
  4561. gdth_ioctl_rescan *rsc;
  4562. gdth_cmd_str *cmd;
  4563. gdth_ha_str *ha;
  4564. unchar i;
  4565. int hanum, rc = -ENOMEM;
  4566. u32 cluster_type = 0;
  4567. rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
  4568. cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
  4569. if (!rsc || !cmd)
  4570. goto free_fail;
  4571. if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
  4572. rsc->ionode >= gdth_ctr_count) {
  4573. rc = -EFAULT;
  4574. goto free_fail;
  4575. }
  4576. hanum = rsc->ionode;
  4577. ha = HADATA(gdth_ctr_tab[hanum]);
  4578. memset(cmd, 0, sizeof(gdth_cmd_str));
  4579. for (i = 0; i < MAX_HDRIVES; ++i) {
  4580. if (!ha->hdr[i].present) {
  4581. rsc->hdr_list[i].bus = 0xff;
  4582. continue;
  4583. }
  4584. rsc->hdr_list[i].bus = ha->virt_bus;
  4585. rsc->hdr_list[i].target = i;
  4586. rsc->hdr_list[i].lun = 0;
  4587. rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
  4588. if (ha->hdr[i].cluster_type & CLUSTER_DRIVE) {
  4589. cmd->Service = CACHESERVICE;
  4590. cmd->OpCode = GDT_CLUST_INFO;
  4591. if (ha->cache_feat & GDT_64BIT)
  4592. cmd->u.cache64.DeviceNo = i;
  4593. else
  4594. cmd->u.cache.DeviceNo = i;
  4595. if (__gdth_execute(ha->sdev, cmd, cmnd, 30, &cluster_type) == S_OK)
  4596. rsc->hdr_list[i].cluster_type = cluster_type;
  4597. }
  4598. }
  4599. if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
  4600. rc = -EFAULT;
  4601. else
  4602. rc = 0;
  4603. free_fail:
  4604. kfree(rsc);
  4605. kfree(cmd);
  4606. return rc;
  4607. }
  4608. static int ioc_rescan(void __user *arg, char *cmnd)
  4609. {
  4610. gdth_ioctl_rescan *rsc;
  4611. gdth_cmd_str *cmd;
  4612. ushort i, status, hdr_cnt;
  4613. ulong32 info;
  4614. int hanum, cyls, hds, secs;
  4615. int rc = -ENOMEM;
  4616. ulong flags;
  4617. gdth_ha_str *ha;
  4618. rsc = kmalloc(sizeof(*rsc), GFP_KERNEL);
  4619. cmd = kmalloc(sizeof(*cmd), GFP_KERNEL);
  4620. if (!cmd || !rsc)
  4621. goto free_fail;
  4622. if (copy_from_user(rsc, arg, sizeof(gdth_ioctl_rescan)) ||
  4623. rsc->ionode >= gdth_ctr_count) {
  4624. rc = -EFAULT;
  4625. goto free_fail;
  4626. }
  4627. hanum = rsc->ionode;
  4628. ha = HADATA(gdth_ctr_tab[hanum]);
  4629. memset(cmd, 0, sizeof(gdth_cmd_str));
  4630. if (rsc->flag == 0) {
  4631. /* old method: re-init. cache service */
  4632. cmd->Service = CACHESERVICE;
  4633. if (ha->cache_feat & GDT_64BIT) {
  4634. cmd->OpCode = GDT_X_INIT_HOST;
  4635. cmd->u.cache64.DeviceNo = LINUX_OS;
  4636. } else {
  4637. cmd->OpCode = GDT_INIT;
  4638. cmd->u.cache.DeviceNo = LINUX_OS;
  4639. }
  4640. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  4641. i = 0;
  4642. hdr_cnt = (status == S_OK ? (ushort)info : 0);
  4643. } else {
  4644. i = rsc->hdr_no;
  4645. hdr_cnt = i + 1;
  4646. }
  4647. for (; i < hdr_cnt && i < MAX_HDRIVES; ++i) {
  4648. cmd->Service = CACHESERVICE;
  4649. cmd->OpCode = GDT_INFO;
  4650. if (ha->cache_feat & GDT_64BIT)
  4651. cmd->u.cache64.DeviceNo = i;
  4652. else
  4653. cmd->u.cache.DeviceNo = i;
  4654. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  4655. spin_lock_irqsave(&ha->smp_lock, flags);
  4656. rsc->hdr_list[i].bus = ha->virt_bus;
  4657. rsc->hdr_list[i].target = i;
  4658. rsc->hdr_list[i].lun = 0;
  4659. if (status != S_OK) {
  4660. ha->hdr[i].present = FALSE;
  4661. } else {
  4662. ha->hdr[i].present = TRUE;
  4663. ha->hdr[i].size = info;
  4664. /* evaluate mapping */
  4665. ha->hdr[i].size &= ~SECS32;
  4666. gdth_eval_mapping(ha->hdr[i].size,&cyls,&hds,&secs);
  4667. ha->hdr[i].heads = hds;
  4668. ha->hdr[i].secs = secs;
  4669. /* round size */
  4670. ha->hdr[i].size = cyls * hds * secs;
  4671. }
  4672. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4673. if (status != S_OK)
  4674. continue;
  4675. /* extended info, if GDT_64BIT, for drives > 2 TB */
  4676. /* but we need ha->info2, not yet stored in scp->SCp */
  4677. /* devtype, cluster info, R/W attribs */
  4678. cmd->Service = CACHESERVICE;
  4679. cmd->OpCode = GDT_DEVTYPE;
  4680. if (ha->cache_feat & GDT_64BIT)
  4681. cmd->u.cache64.DeviceNo = i;
  4682. else
  4683. cmd->u.cache.DeviceNo = i;
  4684. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  4685. spin_lock_irqsave(&ha->smp_lock, flags);
  4686. ha->hdr[i].devtype = (status == S_OK ? (ushort)info : 0);
  4687. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4688. cmd->Service = CACHESERVICE;
  4689. cmd->OpCode = GDT_CLUST_INFO;
  4690. if (ha->cache_feat & GDT_64BIT)
  4691. cmd->u.cache64.DeviceNo = i;
  4692. else
  4693. cmd->u.cache.DeviceNo = i;
  4694. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  4695. spin_lock_irqsave(&ha->smp_lock, flags);
  4696. ha->hdr[i].cluster_type =
  4697. ((status == S_OK && !shared_access) ? (ushort)info : 0);
  4698. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4699. rsc->hdr_list[i].cluster_type = ha->hdr[i].cluster_type;
  4700. cmd->Service = CACHESERVICE;
  4701. cmd->OpCode = GDT_RW_ATTRIBS;
  4702. if (ha->cache_feat & GDT_64BIT)
  4703. cmd->u.cache64.DeviceNo = i;
  4704. else
  4705. cmd->u.cache.DeviceNo = i;
  4706. status = __gdth_execute(ha->sdev, cmd, cmnd, 30, &info);
  4707. spin_lock_irqsave(&ha->smp_lock, flags);
  4708. ha->hdr[i].rw_attribs = (status == S_OK ? (ushort)info : 0);
  4709. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4710. }
  4711. if (copy_to_user(arg, rsc, sizeof(gdth_ioctl_rescan)))
  4712. rc = -EFAULT;
  4713. else
  4714. rc = 0;
  4715. free_fail:
  4716. kfree(rsc);
  4717. kfree(cmd);
  4718. return rc;
  4719. }
  4720. static int gdth_ioctl(struct inode *inode, struct file *filep,
  4721. unsigned int cmd, unsigned long arg)
  4722. {
  4723. gdth_ha_str *ha;
  4724. Scsi_Cmnd *scp;
  4725. ulong flags;
  4726. char cmnd[MAX_COMMAND_SIZE];
  4727. void __user *argp = (void __user *)arg;
  4728. memset(cmnd, 0xff, 12);
  4729. TRACE(("gdth_ioctl() cmd 0x%x\n", cmd));
  4730. switch (cmd) {
  4731. case GDTIOCTL_CTRCNT:
  4732. {
  4733. int cnt = gdth_ctr_count;
  4734. if (put_user(cnt, (int __user *)argp))
  4735. return -EFAULT;
  4736. break;
  4737. }
  4738. case GDTIOCTL_DRVERS:
  4739. {
  4740. int ver = (GDTH_VERSION<<8) | GDTH_SUBVERSION;
  4741. if (put_user(ver, (int __user *)argp))
  4742. return -EFAULT;
  4743. break;
  4744. }
  4745. case GDTIOCTL_OSVERS:
  4746. {
  4747. gdth_ioctl_osvers osv;
  4748. osv.version = (unchar)(LINUX_VERSION_CODE >> 16);
  4749. osv.subversion = (unchar)(LINUX_VERSION_CODE >> 8);
  4750. osv.revision = (ushort)(LINUX_VERSION_CODE & 0xff);
  4751. if (copy_to_user(argp, &osv, sizeof(gdth_ioctl_osvers)))
  4752. return -EFAULT;
  4753. break;
  4754. }
  4755. case GDTIOCTL_CTRTYPE:
  4756. {
  4757. gdth_ioctl_ctrtype ctrt;
  4758. if (copy_from_user(&ctrt, argp, sizeof(gdth_ioctl_ctrtype)) ||
  4759. ctrt.ionode >= gdth_ctr_count)
  4760. return -EFAULT;
  4761. ha = HADATA(gdth_ctr_tab[ctrt.ionode]);
  4762. if (ha->type == GDT_ISA || ha->type == GDT_EISA) {
  4763. ctrt.type = (unchar)((ha->stype>>20) - 0x10);
  4764. } else {
  4765. if (ha->type != GDT_PCIMPR) {
  4766. ctrt.type = (unchar)((ha->stype<<4) + 6);
  4767. } else {
  4768. ctrt.type =
  4769. (ha->oem_id == OEM_ID_INTEL ? 0xfd : 0xfe);
  4770. if (ha->stype >= 0x300)
  4771. ctrt.ext_type = 0x6000 | ha->pdev->subsystem_device;
  4772. else
  4773. ctrt.ext_type = 0x6000 | ha->stype;
  4774. }
  4775. ctrt.device_id = ha->pdev->device;
  4776. ctrt.sub_device_id = ha->pdev->subsystem_device;
  4777. }
  4778. ctrt.info = ha->brd_phys;
  4779. ctrt.oem_id = ha->oem_id;
  4780. if (copy_to_user(argp, &ctrt, sizeof(gdth_ioctl_ctrtype)))
  4781. return -EFAULT;
  4782. break;
  4783. }
  4784. case GDTIOCTL_GENERAL:
  4785. return ioc_general(argp, cmnd);
  4786. case GDTIOCTL_EVENT:
  4787. return ioc_event(argp);
  4788. case GDTIOCTL_LOCKDRV:
  4789. return ioc_lockdrv(argp);
  4790. case GDTIOCTL_LOCKCHN:
  4791. {
  4792. gdth_ioctl_lockchn lchn;
  4793. unchar i, j;
  4794. if (copy_from_user(&lchn, argp, sizeof(gdth_ioctl_lockchn)) ||
  4795. lchn.ionode >= gdth_ctr_count)
  4796. return -EFAULT;
  4797. ha = HADATA(gdth_ctr_tab[lchn.ionode]);
  4798. i = lchn.channel;
  4799. if (i < ha->bus_cnt) {
  4800. if (lchn.lock) {
  4801. spin_lock_irqsave(&ha->smp_lock, flags);
  4802. ha->raw[i].lock = 1;
  4803. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4804. for (j = 0; j < ha->tid_cnt; ++j) {
  4805. gdth_wait_completion(lchn.ionode, i, j);
  4806. gdth_stop_timeout(lchn.ionode, i, j);
  4807. }
  4808. } else {
  4809. spin_lock_irqsave(&ha->smp_lock, flags);
  4810. ha->raw[i].lock = 0;
  4811. spin_unlock_irqrestore(&ha->smp_lock, flags);
  4812. for (j = 0; j < ha->tid_cnt; ++j) {
  4813. gdth_start_timeout(lchn.ionode, i, j);
  4814. gdth_next(lchn.ionode);
  4815. }
  4816. }
  4817. }
  4818. break;
  4819. }
  4820. case GDTIOCTL_RESCAN:
  4821. return ioc_rescan(argp, cmnd);
  4822. case GDTIOCTL_HDRLIST:
  4823. return ioc_hdrlist(argp, cmnd);
  4824. case GDTIOCTL_RESET_BUS:
  4825. {
  4826. gdth_ioctl_reset res;
  4827. int hanum, rval;
  4828. if (copy_from_user(&res, argp, sizeof(gdth_ioctl_reset)) ||
  4829. res.ionode >= gdth_ctr_count)
  4830. return -EFAULT;
  4831. hanum = res.ionode;
  4832. ha = HADATA(gdth_ctr_tab[hanum]);
  4833. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4834. scp = kzalloc(sizeof(*scp), GFP_KERNEL);
  4835. if (!scp)
  4836. return -ENOMEM;
  4837. scp->device = ha->sdev;
  4838. scp->cmd_len = 12;
  4839. scp->use_sg = 0;
  4840. scp->device->channel = virt_ctr ? 0 : res.number;
  4841. rval = gdth_eh_bus_reset(scp);
  4842. res.status = (rval == SUCCESS ? S_OK : S_GENERR);
  4843. kfree(scp);
  4844. #else
  4845. scp = scsi_allocate_device(ha->sdev, 1, FALSE);
  4846. if (!scp)
  4847. return -ENOMEM;
  4848. scp->cmd_len = 12;
  4849. scp->use_sg = 0;
  4850. scp->channel = virt_ctr ? 0 : res.number;
  4851. rval = gdth_eh_bus_reset(scp);
  4852. res.status = (rval == SUCCESS ? S_OK : S_GENERR);
  4853. scsi_release_command(scp);
  4854. #endif
  4855. if (copy_to_user(argp, &res, sizeof(gdth_ioctl_reset)))
  4856. return -EFAULT;
  4857. break;
  4858. }
  4859. case GDTIOCTL_RESET_DRV:
  4860. return ioc_resetdrv(argp, cmnd);
  4861. default:
  4862. break;
  4863. }
  4864. return 0;
  4865. }
  4866. /* flush routine */
  4867. static void gdth_flush(int hanum)
  4868. {
  4869. int i;
  4870. gdth_ha_str *ha;
  4871. gdth_cmd_str gdtcmd;
  4872. char cmnd[MAX_COMMAND_SIZE];
  4873. memset(cmnd, 0xff, MAX_COMMAND_SIZE);
  4874. TRACE2(("gdth_flush() hanum %d\n",hanum));
  4875. ha = HADATA(gdth_ctr_tab[hanum]);
  4876. for (i = 0; i < MAX_HDRIVES; ++i) {
  4877. if (ha->hdr[i].present) {
  4878. gdtcmd.BoardNode = LOCALBOARD;
  4879. gdtcmd.Service = CACHESERVICE;
  4880. gdtcmd.OpCode = GDT_FLUSH;
  4881. if (ha->cache_feat & GDT_64BIT) {
  4882. gdtcmd.u.cache64.DeviceNo = i;
  4883. gdtcmd.u.cache64.BlockNo = 1;
  4884. gdtcmd.u.cache64.sg_canz = 0;
  4885. } else {
  4886. gdtcmd.u.cache.DeviceNo = i;
  4887. gdtcmd.u.cache.BlockNo = 1;
  4888. gdtcmd.u.cache.sg_canz = 0;
  4889. }
  4890. TRACE2(("gdth_flush(): flush ha %d drive %d\n", hanum, i));
  4891. gdth_execute(gdth_ctr_tab[hanum], &gdtcmd, cmnd, 30, NULL);
  4892. }
  4893. }
  4894. }
  4895. /* shutdown routine */
  4896. static int gdth_halt(struct notifier_block *nb, ulong event, void *buf)
  4897. {
  4898. int hanum;
  4899. #ifndef __alpha__
  4900. gdth_cmd_str gdtcmd;
  4901. char cmnd[MAX_COMMAND_SIZE];
  4902. #endif
  4903. if (notifier_disabled)
  4904. return NOTIFY_OK;
  4905. TRACE2(("gdth_halt() event %d\n",(int)event));
  4906. if (event != SYS_RESTART && event != SYS_HALT && event != SYS_POWER_OFF)
  4907. return NOTIFY_DONE;
  4908. notifier_disabled = 1;
  4909. printk("GDT-HA: Flushing all host drives .. ");
  4910. for (hanum = 0; hanum < gdth_ctr_count; ++hanum) {
  4911. gdth_flush(hanum);
  4912. #ifndef __alpha__
  4913. /* controller reset */
  4914. memset(cmnd, 0xff, MAX_COMMAND_SIZE);
  4915. gdtcmd.BoardNode = LOCALBOARD;
  4916. gdtcmd.Service = CACHESERVICE;
  4917. gdtcmd.OpCode = GDT_RESET;
  4918. TRACE2(("gdth_halt(): reset controller %d\n", hanum));
  4919. gdth_execute(gdth_ctr_tab[hanum], &gdtcmd, cmnd, 10, NULL);
  4920. #endif
  4921. }
  4922. printk("Done.\n");
  4923. #ifdef GDTH_STATISTICS
  4924. del_timer(&gdth_timer);
  4925. #endif
  4926. return NOTIFY_OK;
  4927. }
  4928. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4929. /* configure lun */
  4930. static int gdth_slave_configure(struct scsi_device *sdev)
  4931. {
  4932. scsi_adjust_queue_depth(sdev, 0, sdev->host->cmd_per_lun);
  4933. sdev->skip_ms_page_3f = 1;
  4934. sdev->skip_ms_page_8 = 1;
  4935. return 0;
  4936. }
  4937. #endif
  4938. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4939. static struct scsi_host_template driver_template = {
  4940. #else
  4941. static Scsi_Host_Template driver_template = {
  4942. #endif
  4943. .proc_name = "gdth",
  4944. .proc_info = gdth_proc_info,
  4945. .name = "GDT SCSI Disk Array Controller",
  4946. .detect = gdth_detect,
  4947. .release = gdth_release,
  4948. .info = gdth_info,
  4949. .queuecommand = gdth_queuecommand,
  4950. .eh_bus_reset_handler = gdth_eh_bus_reset,
  4951. .bios_param = gdth_bios_param,
  4952. .can_queue = GDTH_MAXCMDS,
  4953. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,6,0)
  4954. .slave_configure = gdth_slave_configure,
  4955. #endif
  4956. .this_id = -1,
  4957. .sg_tablesize = GDTH_MAXSG,
  4958. .cmd_per_lun = GDTH_MAXC_P_L,
  4959. .unchecked_isa_dma = 1,
  4960. .use_clustering = ENABLE_CLUSTERING,
  4961. #if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,0)
  4962. .use_new_eh_code = 1,
  4963. #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,20)
  4964. .highmem_io = 1,
  4965. #endif
  4966. #endif
  4967. };
  4968. #ifdef CONFIG_ISA
  4969. static int gdth_isa_probe_one(struct scsi_host_template *shtp, ulong32 isa_bios)
  4970. {
  4971. struct Scsi_Host *shp;
  4972. gdth_ha_str *ha;
  4973. dma_addr_t scratch_dma_handle = 0;
  4974. int error, hanum, i;
  4975. u8 b;
  4976. if (!gdth_search_isa(isa_bios))
  4977. return -ENXIO;
  4978. shp = scsi_register(shtp, sizeof(gdth_ext_str));
  4979. if (!shp)
  4980. return -ENOMEM;
  4981. ha = HADATA(shp);
  4982. error = -ENODEV;
  4983. if (!gdth_init_isa(isa_bios,ha))
  4984. goto out_host_put;
  4985. /* controller found and initialized */
  4986. printk("Configuring GDT-ISA HA at BIOS 0x%05X IRQ %u DRQ %u\n",
  4987. isa_bios, ha->irq, ha->drq);
  4988. error = request_irq(ha->irq, gdth_interrupt, IRQF_DISABLED, "gdth", ha);
  4989. if (error) {
  4990. printk("GDT-ISA: Unable to allocate IRQ\n");
  4991. goto out_host_put;
  4992. }
  4993. error = request_dma(ha->drq, "gdth");
  4994. if (error) {
  4995. printk("GDT-ISA: Unable to allocate DMA channel\n");
  4996. goto out_free_irq;
  4997. }
  4998. set_dma_mode(ha->drq,DMA_MODE_CASCADE);
  4999. enable_dma(ha->drq);
  5000. shp->unchecked_isa_dma = 1;
  5001. shp->irq = ha->irq;
  5002. shp->dma_channel = ha->drq;
  5003. hanum = gdth_ctr_count;
  5004. gdth_ctr_tab[gdth_ctr_count++] = shp;
  5005. gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
  5006. NUMDATA(shp)->hanum = (ushort)hanum;
  5007. NUMDATA(shp)->busnum= 0;
  5008. ha->pccb = CMDDATA(shp);
  5009. ha->ccb_phys = 0L;
  5010. ha->pdev = NULL;
  5011. error = -ENOMEM;
  5012. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  5013. &scratch_dma_handle);
  5014. if (!ha->pscratch)
  5015. goto out_dec_counters;
  5016. ha->scratch_phys = scratch_dma_handle;
  5017. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  5018. &scratch_dma_handle);
  5019. if (!ha->pmsg)
  5020. goto out_free_pscratch;
  5021. ha->msg_phys = scratch_dma_handle;
  5022. #ifdef INT_COAL
  5023. ha->coal_stat = pci_alloc_consistent(ha->pdev,
  5024. sizeof(gdth_coal_status) * MAXOFFSETS,
  5025. &scratch_dma_handle);
  5026. if (!ha->coal_stat)
  5027. goto out_free_pmsg;
  5028. ha->coal_stat_phys = scratch_dma_handle;
  5029. #endif
  5030. ha->scratch_busy = FALSE;
  5031. ha->req_first = NULL;
  5032. ha->tid_cnt = MAX_HDRIVES;
  5033. if (max_ids > 0 && max_ids < ha->tid_cnt)
  5034. ha->tid_cnt = max_ids;
  5035. for (i = 0; i < GDTH_MAXCMDS; ++i)
  5036. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  5037. ha->scan_mode = rescan ? 0x10 : 0;
  5038. error = -ENODEV;
  5039. if (!gdth_search_drives(hanum)) {
  5040. printk("GDT-ISA: Error during device scan\n");
  5041. goto out_free_coal_stat;
  5042. }
  5043. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  5044. hdr_channel = ha->bus_cnt;
  5045. ha->virt_bus = hdr_channel;
  5046. if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
  5047. shp->max_cmd_len = 16;
  5048. shp->max_id = ha->tid_cnt;
  5049. shp->max_lun = MAXLUN;
  5050. shp->max_channel = virt_ctr ? 0 : ha->bus_cnt;
  5051. if (virt_ctr) {
  5052. virt_ctr = 1;
  5053. /* register addit. SCSI channels as virtual controllers */
  5054. for (b = 1; b < ha->bus_cnt + 1; ++b) {
  5055. shp = scsi_register(shtp,sizeof(gdth_num_str));
  5056. shp->unchecked_isa_dma = 1;
  5057. shp->irq = ha->irq;
  5058. shp->dma_channel = ha->drq;
  5059. gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
  5060. NUMDATA(shp)->hanum = (ushort)hanum;
  5061. NUMDATA(shp)->busnum = b;
  5062. }
  5063. }
  5064. spin_lock_init(&ha->smp_lock);
  5065. gdth_enable_int(hanum);
  5066. return 0;
  5067. out_free_coal_stat:
  5068. #ifdef INT_COAL
  5069. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
  5070. ha->coal_stat, ha->coal_stat_phys);
  5071. out_free_pmsg:
  5072. #endif
  5073. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  5074. ha->pmsg, ha->msg_phys);
  5075. out_free_pscratch:
  5076. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  5077. ha->pscratch, ha->scratch_phys);
  5078. out_dec_counters:
  5079. gdth_ctr_count--;
  5080. gdth_ctr_vcount--;
  5081. out_free_irq:
  5082. free_irq(ha->irq, ha);
  5083. out_host_put:
  5084. scsi_unregister(shp);
  5085. return error;
  5086. }
  5087. #endif /* CONFIG_ISA */
  5088. #ifdef CONFIG_EISA
  5089. static int gdth_eisa_probe_one(struct scsi_host_template *shtp,
  5090. ushort eisa_slot)
  5091. {
  5092. struct Scsi_Host *shp;
  5093. gdth_ha_str *ha;
  5094. dma_addr_t scratch_dma_handle = 0;
  5095. int error, hanum, i;
  5096. u8 b;
  5097. if (!gdth_search_eisa(eisa_slot))
  5098. return -ENXIO;
  5099. shp = scsi_register(shtp,sizeof(gdth_ext_str));
  5100. if (!shp)
  5101. return -ENOMEM;
  5102. ha = HADATA(shp);
  5103. error = -ENODEV;
  5104. if (!gdth_init_eisa(eisa_slot,ha))
  5105. goto out_host_put;
  5106. /* controller found and initialized */
  5107. printk("Configuring GDT-EISA HA at Slot %d IRQ %u\n",
  5108. eisa_slot >> 12, ha->irq);
  5109. error = request_irq(ha->irq, gdth_interrupt, IRQF_DISABLED, "gdth", ha);
  5110. if (error) {
  5111. printk("GDT-EISA: Unable to allocate IRQ\n");
  5112. goto out_host_put;
  5113. }
  5114. shp->unchecked_isa_dma = 0;
  5115. shp->irq = ha->irq;
  5116. shp->dma_channel = 0xff;
  5117. hanum = gdth_ctr_count;
  5118. gdth_ctr_tab[gdth_ctr_count++] = shp;
  5119. gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
  5120. NUMDATA(shp)->hanum = (ushort)hanum;
  5121. NUMDATA(shp)->busnum= 0;
  5122. TRACE2(("EISA detect Bus 0: hanum %d\n",
  5123. NUMDATA(shp)->hanum));
  5124. ha->pccb = CMDDATA(shp);
  5125. ha->ccb_phys = 0L;
  5126. error = -ENOMEM;
  5127. ha->pdev = NULL;
  5128. ha->pscratch = pci_alloc_consistent(ha->pdev, GDTH_SCRATCH,
  5129. &scratch_dma_handle);
  5130. if (!ha->pscratch)
  5131. goto out_free_irq;
  5132. ha->scratch_phys = scratch_dma_handle;
  5133. ha->pmsg = pci_alloc_consistent(ha->pdev, sizeof(gdth_msg_str),
  5134. &scratch_dma_handle);
  5135. if (!ha->pmsg)
  5136. goto out_free_pscratch;
  5137. ha->msg_phys = scratch_dma_handle;
  5138. #ifdef INT_COAL
  5139. ha->coal_stat = pci_alloc_consistent(ha->pdev,
  5140. sizeof(gdth_coal_status) * MAXOFFSETS,
  5141. &scratch_dma_handle);
  5142. if (!ha->coal_stat)
  5143. goto out_free_pmsg;
  5144. ha->coal_stat_phys = scratch_dma_handle;
  5145. #endif
  5146. ha->ccb_phys = pci_map_single(ha->pdev,ha->pccb,
  5147. sizeof(gdth_cmd_str), PCI_DMA_BIDIRECTIONAL);
  5148. if (!ha->ccb_phys)
  5149. goto out_free_coal_stat;
  5150. ha->scratch_busy = FALSE;
  5151. ha->req_first = NULL;
  5152. ha->tid_cnt = MAX_HDRIVES;
  5153. if (max_ids > 0 && max_ids < ha->tid_cnt)
  5154. ha->tid_cnt = max_ids;
  5155. for (i = 0; i < GDTH_MAXCMDS; ++i)
  5156. ha->cmd_tab[i].cmnd = UNUSED_CMND;
  5157. ha->scan_mode = rescan ? 0x10 : 0;
  5158. if (!gdth_search_drives(hanum)) {
  5159. printk("GDT-EISA: Error during device scan\n");
  5160. error = -ENODEV;
  5161. goto out_free_ccb_phys;
  5162. }
  5163. if (hdr_channel < 0 || hdr_channel > ha->bus_cnt)
  5164. hdr_channel = ha->bus_cnt;
  5165. ha->virt_bus = hdr_channel;
  5166. if (ha->cache_feat & ha->raw_feat & ha->screen_feat & GDT_64BIT)
  5167. shp->max_cmd_len = 16;
  5168. shp->max_id = ha->tid_cnt;
  5169. shp->max_lun = MAXLUN;
  5170. shp->max_channel = virt_ctr ? 0 : ha->bus_cnt;
  5171. if (virt_ctr) {
  5172. virt_ctr = 1;
  5173. /* register addit. SCSI channels as virtual controllers */
  5174. for (b = 1; b < ha->bus_cnt + 1; ++b) {
  5175. shp = scsi_register(shtp,sizeof(gdth_num_str));
  5176. shp->unchecked_isa_dma = 0;
  5177. shp->irq = ha->irq;
  5178. shp->dma_channel = 0xff;
  5179. gdth_ctr_vtab[gdth_ctr_vcount++] = shp;
  5180. NUMDATA(shp)->hanum = (ushort)hanum;
  5181. NUMDATA(shp)->busnum = b;
  5182. }
  5183. }
  5184. spin_lock_init(&ha->smp_lock);
  5185. gdth_enable_int(hanum);
  5186. return 0;
  5187. out_free_ccb_phys:
  5188. pci_unmap_single(ha->pdev,ha->ccb_phys, sizeof(gdth_cmd_str),
  5189. PCI_DMA_BIDIRECTIONAL);
  5190. out_free_coal_stat:
  5191. #ifdef INT_COAL
  5192. pci_free_consistent(ha->pdev, sizeof(gdth_coal_status) * MAXOFFSETS,
  5193. ha->coal_stat, ha->coal_stat_phys);
  5194. out_free_pmsg:
  5195. #endif
  5196. pci_free_consistent(ha->pdev, sizeof(gdth_msg_str),
  5197. ha->pmsg, ha->msg_phys);
  5198. out_free_pscratch:
  5199. pci_free_consistent(ha->pdev, GDTH_SCRATCH,
  5200. ha->pscratch, ha->scratch_phys);
  5201. out_free_irq:
  5202. free_irq(ha->irq, ha);
  5203. gdth_ctr_count--;
  5204. gdth_ctr_vcount--;
  5205. out_host_put:
  5206. scsi_unregister(shp);
  5207. return error;
  5208. }
  5209. #endif /* CONFIG_EISA */
  5210. #include "scsi_module.c"
  5211. #ifndef MODULE
  5212. __setup("gdth=", option_setup);
  5213. #endif