iwl-agn-lib.c 44 KB

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  1. /******************************************************************************
  2. *
  3. * GPL LICENSE SUMMARY
  4. *
  5. * Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved.
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of version 2 of the GNU General Public License as
  9. * published by the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful, but
  12. * WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  14. * General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
  19. * USA
  20. *
  21. * The full GNU General Public License is included in this distribution
  22. * in the file called LICENSE.GPL.
  23. *
  24. * Contact Information:
  25. * Intel Linux Wireless <ilw@linux.intel.com>
  26. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  27. *
  28. *****************************************************************************/
  29. #include <linux/etherdevice.h>
  30. #include <linux/kernel.h>
  31. #include <linux/module.h>
  32. #include <linux/init.h>
  33. #include <linux/sched.h>
  34. #include "iwl-dev.h"
  35. #include "iwl-core.h"
  36. #include "iwl-io.h"
  37. #include "iwl-helpers.h"
  38. #include "iwl-agn-hw.h"
  39. #include "iwl-agn.h"
  40. #include "iwl-sta.h"
  41. static inline u32 iwlagn_get_scd_ssn(struct iwl5000_tx_resp *tx_resp)
  42. {
  43. return le32_to_cpup((__le32 *)&tx_resp->status +
  44. tx_resp->frame_count) & MAX_SN;
  45. }
  46. static int iwlagn_tx_status_reply_tx(struct iwl_priv *priv,
  47. struct iwl_ht_agg *agg,
  48. struct iwl5000_tx_resp *tx_resp,
  49. int txq_id, u16 start_idx)
  50. {
  51. u16 status;
  52. struct agg_tx_status *frame_status = &tx_resp->status;
  53. struct ieee80211_tx_info *info = NULL;
  54. struct ieee80211_hdr *hdr = NULL;
  55. u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
  56. int i, sh, idx;
  57. u16 seq;
  58. if (agg->wait_for_ba)
  59. IWL_DEBUG_TX_REPLY(priv, "got tx response w/o block-ack\n");
  60. agg->frame_count = tx_resp->frame_count;
  61. agg->start_idx = start_idx;
  62. agg->rate_n_flags = rate_n_flags;
  63. agg->bitmap = 0;
  64. /* # frames attempted by Tx command */
  65. if (agg->frame_count == 1) {
  66. /* Only one frame was attempted; no block-ack will arrive */
  67. status = le16_to_cpu(frame_status[0].status);
  68. idx = start_idx;
  69. /* FIXME: code repetition */
  70. IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, StartIdx=%d idx=%d\n",
  71. agg->frame_count, agg->start_idx, idx);
  72. info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]);
  73. info->status.rates[0].count = tx_resp->failure_frame + 1;
  74. info->flags &= ~IEEE80211_TX_CTL_AMPDU;
  75. info->flags |= iwl_tx_status_to_mac80211(status);
  76. iwlagn_hwrate_to_tx_control(priv, rate_n_flags, info);
  77. /* FIXME: code repetition end */
  78. IWL_DEBUG_TX_REPLY(priv, "1 Frame 0x%x failure :%d\n",
  79. status & 0xff, tx_resp->failure_frame);
  80. IWL_DEBUG_TX_REPLY(priv, "Rate Info rate_n_flags=%x\n", rate_n_flags);
  81. agg->wait_for_ba = 0;
  82. } else {
  83. /* Two or more frames were attempted; expect block-ack */
  84. u64 bitmap = 0;
  85. int start = agg->start_idx;
  86. /* Construct bit-map of pending frames within Tx window */
  87. for (i = 0; i < agg->frame_count; i++) {
  88. u16 sc;
  89. status = le16_to_cpu(frame_status[i].status);
  90. seq = le16_to_cpu(frame_status[i].sequence);
  91. idx = SEQ_TO_INDEX(seq);
  92. txq_id = SEQ_TO_QUEUE(seq);
  93. if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
  94. AGG_TX_STATE_ABORT_MSK))
  95. continue;
  96. IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n",
  97. agg->frame_count, txq_id, idx);
  98. hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
  99. if (!hdr) {
  100. IWL_ERR(priv,
  101. "BUG_ON idx doesn't point to valid skb"
  102. " idx=%d, txq_id=%d\n", idx, txq_id);
  103. return -1;
  104. }
  105. sc = le16_to_cpu(hdr->seq_ctrl);
  106. if (idx != (SEQ_TO_SN(sc) & 0xff)) {
  107. IWL_ERR(priv,
  108. "BUG_ON idx doesn't match seq control"
  109. " idx=%d, seq_idx=%d, seq=%d\n",
  110. idx, SEQ_TO_SN(sc),
  111. hdr->seq_ctrl);
  112. return -1;
  113. }
  114. IWL_DEBUG_TX_REPLY(priv, "AGG Frame i=%d idx %d seq=%d\n",
  115. i, idx, SEQ_TO_SN(sc));
  116. sh = idx - start;
  117. if (sh > 64) {
  118. sh = (start - idx) + 0xff;
  119. bitmap = bitmap << sh;
  120. sh = 0;
  121. start = idx;
  122. } else if (sh < -64)
  123. sh = 0xff - (start - idx);
  124. else if (sh < 0) {
  125. sh = start - idx;
  126. start = idx;
  127. bitmap = bitmap << sh;
  128. sh = 0;
  129. }
  130. bitmap |= 1ULL << sh;
  131. IWL_DEBUG_TX_REPLY(priv, "start=%d bitmap=0x%llx\n",
  132. start, (unsigned long long)bitmap);
  133. }
  134. agg->bitmap = bitmap;
  135. agg->start_idx = start;
  136. IWL_DEBUG_TX_REPLY(priv, "Frames %d start_idx=%d bitmap=0x%llx\n",
  137. agg->frame_count, agg->start_idx,
  138. (unsigned long long)agg->bitmap);
  139. if (bitmap)
  140. agg->wait_for_ba = 1;
  141. }
  142. return 0;
  143. }
  144. void iwl_check_abort_status(struct iwl_priv *priv,
  145. u8 frame_count, u32 status)
  146. {
  147. if (frame_count == 1 && status == TX_STATUS_FAIL_RFKILL_FLUSH) {
  148. IWL_ERR(priv, "TODO: Implement Tx flush command!!!\n");
  149. }
  150. }
  151. static void iwlagn_rx_reply_tx(struct iwl_priv *priv,
  152. struct iwl_rx_mem_buffer *rxb)
  153. {
  154. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  155. u16 sequence = le16_to_cpu(pkt->hdr.sequence);
  156. int txq_id = SEQ_TO_QUEUE(sequence);
  157. int index = SEQ_TO_INDEX(sequence);
  158. struct iwl_tx_queue *txq = &priv->txq[txq_id];
  159. struct ieee80211_tx_info *info;
  160. struct iwl5000_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
  161. u32 status = le16_to_cpu(tx_resp->status.status);
  162. int tid;
  163. int sta_id;
  164. int freed;
  165. if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
  166. IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
  167. "is out of range [0-%d] %d %d\n", txq_id,
  168. index, txq->q.n_bd, txq->q.write_ptr,
  169. txq->q.read_ptr);
  170. return;
  171. }
  172. info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
  173. memset(&info->status, 0, sizeof(info->status));
  174. tid = (tx_resp->ra_tid & IWL50_TX_RES_TID_MSK) >> IWL50_TX_RES_TID_POS;
  175. sta_id = (tx_resp->ra_tid & IWL50_TX_RES_RA_MSK) >> IWL50_TX_RES_RA_POS;
  176. if (txq->sched_retry) {
  177. const u32 scd_ssn = iwlagn_get_scd_ssn(tx_resp);
  178. struct iwl_ht_agg *agg = NULL;
  179. agg = &priv->stations[sta_id].tid[tid].agg;
  180. iwlagn_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
  181. /* check if BAR is needed */
  182. if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
  183. info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
  184. if (txq->q.read_ptr != (scd_ssn & 0xff)) {
  185. index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
  186. IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim "
  187. "scd_ssn=%d idx=%d txq=%d swq=%d\n",
  188. scd_ssn , index, txq_id, txq->swq_id);
  189. freed = iwlagn_tx_queue_reclaim(priv, txq_id, index);
  190. iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
  191. if (priv->mac80211_registered &&
  192. (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
  193. (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) {
  194. if (agg->state == IWL_AGG_OFF)
  195. iwl_wake_queue(priv, txq_id);
  196. else
  197. iwl_wake_queue(priv, txq->swq_id);
  198. }
  199. }
  200. } else {
  201. BUG_ON(txq_id != txq->swq_id);
  202. info->status.rates[0].count = tx_resp->failure_frame + 1;
  203. info->flags |= iwl_tx_status_to_mac80211(status);
  204. iwlagn_hwrate_to_tx_control(priv,
  205. le32_to_cpu(tx_resp->rate_n_flags),
  206. info);
  207. IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x) rate_n_flags "
  208. "0x%x retries %d\n",
  209. txq_id,
  210. iwl_get_tx_fail_reason(status), status,
  211. le32_to_cpu(tx_resp->rate_n_flags),
  212. tx_resp->failure_frame);
  213. freed = iwlagn_tx_queue_reclaim(priv, txq_id, index);
  214. iwl_free_tfds_in_queue(priv, sta_id, tid, freed);
  215. if (priv->mac80211_registered &&
  216. (iwl_queue_space(&txq->q) > txq->q.low_mark))
  217. iwl_wake_queue(priv, txq_id);
  218. }
  219. iwlagn_txq_check_empty(priv, sta_id, tid, txq_id);
  220. iwl_check_abort_status(priv, tx_resp->frame_count, status);
  221. }
  222. void iwlagn_rx_handler_setup(struct iwl_priv *priv)
  223. {
  224. /* init calibration handlers */
  225. priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
  226. iwlagn_rx_calib_result;
  227. priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] =
  228. iwlagn_rx_calib_complete;
  229. priv->rx_handlers[REPLY_TX] = iwlagn_rx_reply_tx;
  230. }
  231. void iwlagn_setup_deferred_work(struct iwl_priv *priv)
  232. {
  233. /* in agn, the tx power calibration is done in uCode */
  234. priv->disable_tx_power_cal = 1;
  235. }
  236. int iwlagn_hw_valid_rtc_data_addr(u32 addr)
  237. {
  238. return (addr >= IWLAGN_RTC_DATA_LOWER_BOUND) &&
  239. (addr < IWLAGN_RTC_DATA_UPPER_BOUND);
  240. }
  241. int iwlagn_send_tx_power(struct iwl_priv *priv)
  242. {
  243. struct iwl5000_tx_power_dbm_cmd tx_power_cmd;
  244. u8 tx_ant_cfg_cmd;
  245. /* half dBm need to multiply */
  246. tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt);
  247. if (priv->tx_power_lmt_in_half_dbm &&
  248. priv->tx_power_lmt_in_half_dbm < tx_power_cmd.global_lmt) {
  249. /*
  250. * For the newer devices which using enhanced/extend tx power
  251. * table in EEPROM, the format is in half dBm. driver need to
  252. * convert to dBm format before report to mac80211.
  253. * By doing so, there is a possibility of 1/2 dBm resolution
  254. * lost. driver will perform "round-up" operation before
  255. * reporting, but it will cause 1/2 dBm tx power over the
  256. * regulatory limit. Perform the checking here, if the
  257. * "tx_power_user_lmt" is higher than EEPROM value (in
  258. * half-dBm format), lower the tx power based on EEPROM
  259. */
  260. tx_power_cmd.global_lmt = priv->tx_power_lmt_in_half_dbm;
  261. }
  262. tx_power_cmd.flags = IWL50_TX_POWER_NO_CLOSED;
  263. tx_power_cmd.srv_chan_lmt = IWL50_TX_POWER_AUTO;
  264. if (IWL_UCODE_API(priv->ucode_ver) == 1)
  265. tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD_V1;
  266. else
  267. tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD;
  268. return iwl_send_cmd_pdu_async(priv, tx_ant_cfg_cmd,
  269. sizeof(tx_power_cmd), &tx_power_cmd,
  270. NULL);
  271. }
  272. void iwlagn_temperature(struct iwl_priv *priv)
  273. {
  274. /* store temperature from statistics (in Celsius) */
  275. priv->temperature = le32_to_cpu(priv->statistics.general.temperature);
  276. iwl_tt_handler(priv);
  277. }
  278. u16 iwlagn_eeprom_calib_version(struct iwl_priv *priv)
  279. {
  280. struct iwl_eeprom_calib_hdr {
  281. u8 version;
  282. u8 pa_type;
  283. u16 voltage;
  284. } *hdr;
  285. hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
  286. EEPROM_CALIB_ALL);
  287. return hdr->version;
  288. }
  289. /*
  290. * EEPROM
  291. */
  292. static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
  293. {
  294. u16 offset = 0;
  295. if ((address & INDIRECT_ADDRESS) == 0)
  296. return address;
  297. switch (address & INDIRECT_TYPE_MSK) {
  298. case INDIRECT_HOST:
  299. offset = iwl_eeprom_query16(priv, EEPROM_LINK_HOST);
  300. break;
  301. case INDIRECT_GENERAL:
  302. offset = iwl_eeprom_query16(priv, EEPROM_LINK_GENERAL);
  303. break;
  304. case INDIRECT_REGULATORY:
  305. offset = iwl_eeprom_query16(priv, EEPROM_LINK_REGULATORY);
  306. break;
  307. case INDIRECT_CALIBRATION:
  308. offset = iwl_eeprom_query16(priv, EEPROM_LINK_CALIBRATION);
  309. break;
  310. case INDIRECT_PROCESS_ADJST:
  311. offset = iwl_eeprom_query16(priv, EEPROM_LINK_PROCESS_ADJST);
  312. break;
  313. case INDIRECT_OTHERS:
  314. offset = iwl_eeprom_query16(priv, EEPROM_LINK_OTHERS);
  315. break;
  316. default:
  317. IWL_ERR(priv, "illegal indirect type: 0x%X\n",
  318. address & INDIRECT_TYPE_MSK);
  319. break;
  320. }
  321. /* translate the offset from words to byte */
  322. return (address & ADDRESS_MSK) + (offset << 1);
  323. }
  324. const u8 *iwlagn_eeprom_query_addr(const struct iwl_priv *priv,
  325. size_t offset)
  326. {
  327. u32 address = eeprom_indirect_address(priv, offset);
  328. BUG_ON(address >= priv->cfg->eeprom_size);
  329. return &priv->eeprom[address];
  330. }
  331. struct iwl_mod_params iwlagn_mod_params = {
  332. .amsdu_size_8K = 1,
  333. .restart_fw = 1,
  334. /* the rest are 0 by default */
  335. };
  336. void iwlagn_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
  337. {
  338. unsigned long flags;
  339. int i;
  340. spin_lock_irqsave(&rxq->lock, flags);
  341. INIT_LIST_HEAD(&rxq->rx_free);
  342. INIT_LIST_HEAD(&rxq->rx_used);
  343. /* Fill the rx_used queue with _all_ of the Rx buffers */
  344. for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) {
  345. /* In the reset function, these buffers may have been allocated
  346. * to an SKB, so we need to unmap and free potential storage */
  347. if (rxq->pool[i].page != NULL) {
  348. pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
  349. PAGE_SIZE << priv->hw_params.rx_page_order,
  350. PCI_DMA_FROMDEVICE);
  351. __iwl_free_pages(priv, rxq->pool[i].page);
  352. rxq->pool[i].page = NULL;
  353. }
  354. list_add_tail(&rxq->pool[i].list, &rxq->rx_used);
  355. }
  356. for (i = 0; i < RX_QUEUE_SIZE; i++)
  357. rxq->queue[i] = NULL;
  358. /* Set us so that we have processed and used all buffers, but have
  359. * not restocked the Rx queue with fresh buffers */
  360. rxq->read = rxq->write = 0;
  361. rxq->write_actual = 0;
  362. rxq->free_count = 0;
  363. spin_unlock_irqrestore(&rxq->lock, flags);
  364. }
  365. int iwlagn_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
  366. {
  367. u32 rb_size;
  368. const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */
  369. u32 rb_timeout = 0; /* FIXME: RX_RB_TIMEOUT for all devices? */
  370. if (!priv->cfg->use_isr_legacy)
  371. rb_timeout = RX_RB_TIMEOUT;
  372. if (priv->cfg->mod_params->amsdu_size_8K)
  373. rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
  374. else
  375. rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
  376. /* Stop Rx DMA */
  377. iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
  378. /* Reset driver's Rx queue write index */
  379. iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
  380. /* Tell device where to find RBD circular buffer in DRAM */
  381. iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
  382. (u32)(rxq->dma_addr >> 8));
  383. /* Tell device where in DRAM to update its Rx status */
  384. iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
  385. rxq->rb_stts_dma >> 4);
  386. /* Enable Rx DMA
  387. * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in
  388. * the credit mechanism in 5000 HW RX FIFO
  389. * Direct rx interrupts to hosts
  390. * Rx buffer size 4 or 8k
  391. * RB timeout 0x10
  392. * 256 RBDs
  393. */
  394. iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
  395. FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
  396. FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY |
  397. FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
  398. FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK |
  399. rb_size|
  400. (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)|
  401. (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS));
  402. /* Set interrupt coalescing timer to default (2048 usecs) */
  403. iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF);
  404. return 0;
  405. }
  406. int iwlagn_hw_nic_init(struct iwl_priv *priv)
  407. {
  408. unsigned long flags;
  409. struct iwl_rx_queue *rxq = &priv->rxq;
  410. int ret;
  411. /* nic_init */
  412. spin_lock_irqsave(&priv->lock, flags);
  413. priv->cfg->ops->lib->apm_ops.init(priv);
  414. /* Set interrupt coalescing calibration timer to default (512 usecs) */
  415. iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_CALIB_TIMEOUT_DEF);
  416. spin_unlock_irqrestore(&priv->lock, flags);
  417. ret = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN);
  418. priv->cfg->ops->lib->apm_ops.config(priv);
  419. /* Allocate the RX queue, or reset if it is already allocated */
  420. if (!rxq->bd) {
  421. ret = iwl_rx_queue_alloc(priv);
  422. if (ret) {
  423. IWL_ERR(priv, "Unable to initialize Rx queue\n");
  424. return -ENOMEM;
  425. }
  426. } else
  427. iwlagn_rx_queue_reset(priv, rxq);
  428. iwlagn_rx_replenish(priv);
  429. iwlagn_rx_init(priv, rxq);
  430. spin_lock_irqsave(&priv->lock, flags);
  431. rxq->need_update = 1;
  432. iwl_rx_queue_update_write_ptr(priv, rxq);
  433. spin_unlock_irqrestore(&priv->lock, flags);
  434. /* Allocate or reset and init all Tx and Command queues */
  435. if (!priv->txq) {
  436. ret = iwlagn_txq_ctx_alloc(priv);
  437. if (ret)
  438. return ret;
  439. } else
  440. iwlagn_txq_ctx_reset(priv);
  441. set_bit(STATUS_INIT, &priv->status);
  442. return 0;
  443. }
  444. /**
  445. * iwlagn_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr
  446. */
  447. static inline __le32 iwlagn_dma_addr2rbd_ptr(struct iwl_priv *priv,
  448. dma_addr_t dma_addr)
  449. {
  450. return cpu_to_le32((u32)(dma_addr >> 8));
  451. }
  452. /**
  453. * iwlagn_rx_queue_restock - refill RX queue from pre-allocated pool
  454. *
  455. * If there are slots in the RX queue that need to be restocked,
  456. * and we have free pre-allocated buffers, fill the ranks as much
  457. * as we can, pulling from rx_free.
  458. *
  459. * This moves the 'write' index forward to catch up with 'processed', and
  460. * also updates the memory address in the firmware to reference the new
  461. * target buffer.
  462. */
  463. void iwlagn_rx_queue_restock(struct iwl_priv *priv)
  464. {
  465. struct iwl_rx_queue *rxq = &priv->rxq;
  466. struct list_head *element;
  467. struct iwl_rx_mem_buffer *rxb;
  468. unsigned long flags;
  469. spin_lock_irqsave(&rxq->lock, flags);
  470. while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) {
  471. /* The overwritten rxb must be a used one */
  472. rxb = rxq->queue[rxq->write];
  473. BUG_ON(rxb && rxb->page);
  474. /* Get next free Rx buffer, remove from free list */
  475. element = rxq->rx_free.next;
  476. rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
  477. list_del(element);
  478. /* Point to Rx buffer via next RBD in circular buffer */
  479. rxq->bd[rxq->write] = iwlagn_dma_addr2rbd_ptr(priv,
  480. rxb->page_dma);
  481. rxq->queue[rxq->write] = rxb;
  482. rxq->write = (rxq->write + 1) & RX_QUEUE_MASK;
  483. rxq->free_count--;
  484. }
  485. spin_unlock_irqrestore(&rxq->lock, flags);
  486. /* If the pre-allocated buffer pool is dropping low, schedule to
  487. * refill it */
  488. if (rxq->free_count <= RX_LOW_WATERMARK)
  489. queue_work(priv->workqueue, &priv->rx_replenish);
  490. /* If we've added more space for the firmware to place data, tell it.
  491. * Increment device's write pointer in multiples of 8. */
  492. if (rxq->write_actual != (rxq->write & ~0x7)) {
  493. spin_lock_irqsave(&rxq->lock, flags);
  494. rxq->need_update = 1;
  495. spin_unlock_irqrestore(&rxq->lock, flags);
  496. iwl_rx_queue_update_write_ptr(priv, rxq);
  497. }
  498. }
  499. /**
  500. * iwlagn_rx_replenish - Move all used packet from rx_used to rx_free
  501. *
  502. * When moving to rx_free an SKB is allocated for the slot.
  503. *
  504. * Also restock the Rx queue via iwl_rx_queue_restock.
  505. * This is called as a scheduled work item (except for during initialization)
  506. */
  507. void iwlagn_rx_allocate(struct iwl_priv *priv, gfp_t priority)
  508. {
  509. struct iwl_rx_queue *rxq = &priv->rxq;
  510. struct list_head *element;
  511. struct iwl_rx_mem_buffer *rxb;
  512. struct page *page;
  513. unsigned long flags;
  514. gfp_t gfp_mask = priority;
  515. while (1) {
  516. spin_lock_irqsave(&rxq->lock, flags);
  517. if (list_empty(&rxq->rx_used)) {
  518. spin_unlock_irqrestore(&rxq->lock, flags);
  519. return;
  520. }
  521. spin_unlock_irqrestore(&rxq->lock, flags);
  522. if (rxq->free_count > RX_LOW_WATERMARK)
  523. gfp_mask |= __GFP_NOWARN;
  524. if (priv->hw_params.rx_page_order > 0)
  525. gfp_mask |= __GFP_COMP;
  526. /* Alloc a new receive buffer */
  527. page = alloc_pages(gfp_mask, priv->hw_params.rx_page_order);
  528. if (!page) {
  529. if (net_ratelimit())
  530. IWL_DEBUG_INFO(priv, "alloc_pages failed, "
  531. "order: %d\n",
  532. priv->hw_params.rx_page_order);
  533. if ((rxq->free_count <= RX_LOW_WATERMARK) &&
  534. net_ratelimit())
  535. IWL_CRIT(priv, "Failed to alloc_pages with %s. Only %u free buffers remaining.\n",
  536. priority == GFP_ATOMIC ? "GFP_ATOMIC" : "GFP_KERNEL",
  537. rxq->free_count);
  538. /* We don't reschedule replenish work here -- we will
  539. * call the restock method and if it still needs
  540. * more buffers it will schedule replenish */
  541. return;
  542. }
  543. spin_lock_irqsave(&rxq->lock, flags);
  544. if (list_empty(&rxq->rx_used)) {
  545. spin_unlock_irqrestore(&rxq->lock, flags);
  546. __free_pages(page, priv->hw_params.rx_page_order);
  547. return;
  548. }
  549. element = rxq->rx_used.next;
  550. rxb = list_entry(element, struct iwl_rx_mem_buffer, list);
  551. list_del(element);
  552. spin_unlock_irqrestore(&rxq->lock, flags);
  553. BUG_ON(rxb->page);
  554. rxb->page = page;
  555. /* Get physical address of the RB */
  556. rxb->page_dma = pci_map_page(priv->pci_dev, page, 0,
  557. PAGE_SIZE << priv->hw_params.rx_page_order,
  558. PCI_DMA_FROMDEVICE);
  559. /* dma address must be no more than 36 bits */
  560. BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36));
  561. /* and also 256 byte aligned! */
  562. BUG_ON(rxb->page_dma & DMA_BIT_MASK(8));
  563. spin_lock_irqsave(&rxq->lock, flags);
  564. list_add_tail(&rxb->list, &rxq->rx_free);
  565. rxq->free_count++;
  566. priv->alloc_rxb_page++;
  567. spin_unlock_irqrestore(&rxq->lock, flags);
  568. }
  569. }
  570. void iwlagn_rx_replenish(struct iwl_priv *priv)
  571. {
  572. unsigned long flags;
  573. iwlagn_rx_allocate(priv, GFP_KERNEL);
  574. spin_lock_irqsave(&priv->lock, flags);
  575. iwlagn_rx_queue_restock(priv);
  576. spin_unlock_irqrestore(&priv->lock, flags);
  577. }
  578. void iwlagn_rx_replenish_now(struct iwl_priv *priv)
  579. {
  580. iwlagn_rx_allocate(priv, GFP_ATOMIC);
  581. iwlagn_rx_queue_restock(priv);
  582. }
  583. /* Assumes that the skb field of the buffers in 'pool' is kept accurate.
  584. * If an SKB has been detached, the POOL needs to have its SKB set to NULL
  585. * This free routine walks the list of POOL entries and if SKB is set to
  586. * non NULL it is unmapped and freed
  587. */
  588. void iwlagn_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq)
  589. {
  590. int i;
  591. for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) {
  592. if (rxq->pool[i].page != NULL) {
  593. pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma,
  594. PAGE_SIZE << priv->hw_params.rx_page_order,
  595. PCI_DMA_FROMDEVICE);
  596. __iwl_free_pages(priv, rxq->pool[i].page);
  597. rxq->pool[i].page = NULL;
  598. }
  599. }
  600. dma_free_coherent(&priv->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd,
  601. rxq->dma_addr);
  602. dma_free_coherent(&priv->pci_dev->dev, sizeof(struct iwl_rb_status),
  603. rxq->rb_stts, rxq->rb_stts_dma);
  604. rxq->bd = NULL;
  605. rxq->rb_stts = NULL;
  606. }
  607. int iwlagn_rxq_stop(struct iwl_priv *priv)
  608. {
  609. /* stop Rx DMA */
  610. iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
  611. iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
  612. FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000);
  613. return 0;
  614. }
  615. int iwlagn_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band)
  616. {
  617. int idx = 0;
  618. int band_offset = 0;
  619. /* HT rate format: mac80211 wants an MCS number, which is just LSB */
  620. if (rate_n_flags & RATE_MCS_HT_MSK) {
  621. idx = (rate_n_flags & 0xff);
  622. return idx;
  623. /* Legacy rate format, search for match in table */
  624. } else {
  625. if (band == IEEE80211_BAND_5GHZ)
  626. band_offset = IWL_FIRST_OFDM_RATE;
  627. for (idx = band_offset; idx < IWL_RATE_COUNT_LEGACY; idx++)
  628. if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF))
  629. return idx - band_offset;
  630. }
  631. return -1;
  632. }
  633. /* Calc max signal level (dBm) among 3 possible receivers */
  634. static inline int iwlagn_calc_rssi(struct iwl_priv *priv,
  635. struct iwl_rx_phy_res *rx_resp)
  636. {
  637. return priv->cfg->ops->utils->calc_rssi(priv, rx_resp);
  638. }
  639. #ifdef CONFIG_IWLWIFI_DEBUG
  640. /**
  641. * iwlagn_dbg_report_frame - dump frame to syslog during debug sessions
  642. *
  643. * You may hack this function to show different aspects of received frames,
  644. * including selective frame dumps.
  645. * group100 parameter selects whether to show 1 out of 100 good data frames.
  646. * All beacon and probe response frames are printed.
  647. */
  648. static void iwlagn_dbg_report_frame(struct iwl_priv *priv,
  649. struct iwl_rx_phy_res *phy_res, u16 length,
  650. struct ieee80211_hdr *header, int group100)
  651. {
  652. u32 to_us;
  653. u32 print_summary = 0;
  654. u32 print_dump = 0; /* set to 1 to dump all frames' contents */
  655. u32 hundred = 0;
  656. u32 dataframe = 0;
  657. __le16 fc;
  658. u16 seq_ctl;
  659. u16 channel;
  660. u16 phy_flags;
  661. u32 rate_n_flags;
  662. u32 tsf_low;
  663. int rssi;
  664. if (likely(!(iwl_get_debug_level(priv) & IWL_DL_RX)))
  665. return;
  666. /* MAC header */
  667. fc = header->frame_control;
  668. seq_ctl = le16_to_cpu(header->seq_ctrl);
  669. /* metadata */
  670. channel = le16_to_cpu(phy_res->channel);
  671. phy_flags = le16_to_cpu(phy_res->phy_flags);
  672. rate_n_flags = le32_to_cpu(phy_res->rate_n_flags);
  673. /* signal statistics */
  674. rssi = iwlagn_calc_rssi(priv, phy_res);
  675. tsf_low = le64_to_cpu(phy_res->timestamp) & 0x0ffffffff;
  676. to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
  677. /* if data frame is to us and all is good,
  678. * (optionally) print summary for only 1 out of every 100 */
  679. if (to_us && (fc & ~cpu_to_le16(IEEE80211_FCTL_PROTECTED)) ==
  680. cpu_to_le16(IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
  681. dataframe = 1;
  682. if (!group100)
  683. print_summary = 1; /* print each frame */
  684. else if (priv->framecnt_to_us < 100) {
  685. priv->framecnt_to_us++;
  686. print_summary = 0;
  687. } else {
  688. priv->framecnt_to_us = 0;
  689. print_summary = 1;
  690. hundred = 1;
  691. }
  692. } else {
  693. /* print summary for all other frames */
  694. print_summary = 1;
  695. }
  696. if (print_summary) {
  697. char *title;
  698. int rate_idx;
  699. u32 bitrate;
  700. if (hundred)
  701. title = "100Frames";
  702. else if (ieee80211_has_retry(fc))
  703. title = "Retry";
  704. else if (ieee80211_is_assoc_resp(fc))
  705. title = "AscRsp";
  706. else if (ieee80211_is_reassoc_resp(fc))
  707. title = "RasRsp";
  708. else if (ieee80211_is_probe_resp(fc)) {
  709. title = "PrbRsp";
  710. print_dump = 1; /* dump frame contents */
  711. } else if (ieee80211_is_beacon(fc)) {
  712. title = "Beacon";
  713. print_dump = 1; /* dump frame contents */
  714. } else if (ieee80211_is_atim(fc))
  715. title = "ATIM";
  716. else if (ieee80211_is_auth(fc))
  717. title = "Auth";
  718. else if (ieee80211_is_deauth(fc))
  719. title = "DeAuth";
  720. else if (ieee80211_is_disassoc(fc))
  721. title = "DisAssoc";
  722. else
  723. title = "Frame";
  724. rate_idx = iwl_hwrate_to_plcp_idx(rate_n_flags);
  725. if (unlikely((rate_idx < 0) || (rate_idx >= IWL_RATE_COUNT))) {
  726. bitrate = 0;
  727. WARN_ON_ONCE(1);
  728. } else {
  729. bitrate = iwl_rates[rate_idx].ieee / 2;
  730. }
  731. /* print frame summary.
  732. * MAC addresses show just the last byte (for brevity),
  733. * but you can hack it to show more, if you'd like to. */
  734. if (dataframe)
  735. IWL_DEBUG_RX(priv, "%s: mhd=0x%04x, dst=0x%02x, "
  736. "len=%u, rssi=%d, chnl=%d, rate=%u,\n",
  737. title, le16_to_cpu(fc), header->addr1[5],
  738. length, rssi, channel, bitrate);
  739. else {
  740. /* src/dst addresses assume managed mode */
  741. IWL_DEBUG_RX(priv, "%s: 0x%04x, dst=0x%02x, src=0x%02x, "
  742. "len=%u, rssi=%d, tim=%lu usec, "
  743. "phy=0x%02x, chnl=%d\n",
  744. title, le16_to_cpu(fc), header->addr1[5],
  745. header->addr3[5], length, rssi,
  746. tsf_low - priv->scan_start_tsf,
  747. phy_flags, channel);
  748. }
  749. }
  750. if (print_dump)
  751. iwl_print_hex_dump(priv, IWL_DL_RX, header, length);
  752. }
  753. #endif
  754. static u32 iwlagn_translate_rx_status(struct iwl_priv *priv, u32 decrypt_in)
  755. {
  756. u32 decrypt_out = 0;
  757. if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) ==
  758. RX_RES_STATUS_STATION_FOUND)
  759. decrypt_out |= (RX_RES_STATUS_STATION_FOUND |
  760. RX_RES_STATUS_NO_STATION_INFO_MISMATCH);
  761. decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK);
  762. /* packet was not encrypted */
  763. if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
  764. RX_RES_STATUS_SEC_TYPE_NONE)
  765. return decrypt_out;
  766. /* packet was encrypted with unknown alg */
  767. if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) ==
  768. RX_RES_STATUS_SEC_TYPE_ERR)
  769. return decrypt_out;
  770. /* decryption was not done in HW */
  771. if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) !=
  772. RX_MPDU_RES_STATUS_DEC_DONE_MSK)
  773. return decrypt_out;
  774. switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) {
  775. case RX_RES_STATUS_SEC_TYPE_CCMP:
  776. /* alg is CCM: check MIC only */
  777. if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK))
  778. /* Bad MIC */
  779. decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
  780. else
  781. decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
  782. break;
  783. case RX_RES_STATUS_SEC_TYPE_TKIP:
  784. if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) {
  785. /* Bad TTAK */
  786. decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK;
  787. break;
  788. }
  789. /* fall through if TTAK OK */
  790. default:
  791. if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK))
  792. decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC;
  793. else
  794. decrypt_out |= RX_RES_STATUS_DECRYPT_OK;
  795. break;
  796. };
  797. IWL_DEBUG_RX(priv, "decrypt_in:0x%x decrypt_out = 0x%x\n",
  798. decrypt_in, decrypt_out);
  799. return decrypt_out;
  800. }
  801. static void iwlagn_pass_packet_to_mac80211(struct iwl_priv *priv,
  802. struct ieee80211_hdr *hdr,
  803. u16 len,
  804. u32 ampdu_status,
  805. struct iwl_rx_mem_buffer *rxb,
  806. struct ieee80211_rx_status *stats)
  807. {
  808. struct sk_buff *skb;
  809. __le16 fc = hdr->frame_control;
  810. /* We only process data packets if the interface is open */
  811. if (unlikely(!priv->is_open)) {
  812. IWL_DEBUG_DROP_LIMIT(priv,
  813. "Dropping packet while interface is not open.\n");
  814. return;
  815. }
  816. /* In case of HW accelerated crypto and bad decryption, drop */
  817. if (!priv->cfg->mod_params->sw_crypto &&
  818. iwl_set_decrypted_flag(priv, hdr, ampdu_status, stats))
  819. return;
  820. skb = dev_alloc_skb(128);
  821. if (!skb) {
  822. IWL_ERR(priv, "dev_alloc_skb failed\n");
  823. return;
  824. }
  825. skb_add_rx_frag(skb, 0, rxb->page, (void *)hdr - rxb_addr(rxb), len);
  826. iwl_update_stats(priv, false, fc, len);
  827. memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats));
  828. ieee80211_rx(priv->hw, skb);
  829. priv->alloc_rxb_page--;
  830. rxb->page = NULL;
  831. }
  832. /* Called for REPLY_RX (legacy ABG frames), or
  833. * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */
  834. void iwlagn_rx_reply_rx(struct iwl_priv *priv,
  835. struct iwl_rx_mem_buffer *rxb)
  836. {
  837. struct ieee80211_hdr *header;
  838. struct ieee80211_rx_status rx_status;
  839. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  840. struct iwl_rx_phy_res *phy_res;
  841. __le32 rx_pkt_status;
  842. struct iwl4965_rx_mpdu_res_start *amsdu;
  843. u32 len;
  844. u32 ampdu_status;
  845. u32 rate_n_flags;
  846. /**
  847. * REPLY_RX and REPLY_RX_MPDU_CMD are handled differently.
  848. * REPLY_RX: physical layer info is in this buffer
  849. * REPLY_RX_MPDU_CMD: physical layer info was sent in separate
  850. * command and cached in priv->last_phy_res
  851. *
  852. * Here we set up local variables depending on which command is
  853. * received.
  854. */
  855. if (pkt->hdr.cmd == REPLY_RX) {
  856. phy_res = (struct iwl_rx_phy_res *)pkt->u.raw;
  857. header = (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*phy_res)
  858. + phy_res->cfg_phy_cnt);
  859. len = le16_to_cpu(phy_res->byte_count);
  860. rx_pkt_status = *(__le32 *)(pkt->u.raw + sizeof(*phy_res) +
  861. phy_res->cfg_phy_cnt + len);
  862. ampdu_status = le32_to_cpu(rx_pkt_status);
  863. } else {
  864. if (!priv->_agn.last_phy_res_valid) {
  865. IWL_ERR(priv, "MPDU frame without cached PHY data\n");
  866. return;
  867. }
  868. phy_res = &priv->_agn.last_phy_res;
  869. amsdu = (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
  870. header = (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*amsdu));
  871. len = le16_to_cpu(amsdu->byte_count);
  872. rx_pkt_status = *(__le32 *)(pkt->u.raw + sizeof(*amsdu) + len);
  873. ampdu_status = iwlagn_translate_rx_status(priv,
  874. le32_to_cpu(rx_pkt_status));
  875. }
  876. if ((unlikely(phy_res->cfg_phy_cnt > 20))) {
  877. IWL_DEBUG_DROP(priv, "dsp size out of range [0,20]: %d/n",
  878. phy_res->cfg_phy_cnt);
  879. return;
  880. }
  881. if (!(rx_pkt_status & RX_RES_STATUS_NO_CRC32_ERROR) ||
  882. !(rx_pkt_status & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
  883. IWL_DEBUG_RX(priv, "Bad CRC or FIFO: 0x%08X.\n",
  884. le32_to_cpu(rx_pkt_status));
  885. return;
  886. }
  887. /* This will be used in several places later */
  888. rate_n_flags = le32_to_cpu(phy_res->rate_n_flags);
  889. /* rx_status carries information about the packet to mac80211 */
  890. rx_status.mactime = le64_to_cpu(phy_res->timestamp);
  891. rx_status.freq =
  892. ieee80211_channel_to_frequency(le16_to_cpu(phy_res->channel));
  893. rx_status.band = (phy_res->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
  894. IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
  895. rx_status.rate_idx =
  896. iwlagn_hwrate_to_mac80211_idx(rate_n_flags, rx_status.band);
  897. rx_status.flag = 0;
  898. /* TSF isn't reliable. In order to allow smooth user experience,
  899. * this W/A doesn't propagate it to the mac80211 */
  900. /*rx_status.flag |= RX_FLAG_TSFT;*/
  901. priv->ucode_beacon_time = le32_to_cpu(phy_res->beacon_time_stamp);
  902. /* Find max signal strength (dBm) among 3 antenna/receiver chains */
  903. rx_status.signal = iwlagn_calc_rssi(priv, phy_res);
  904. #ifdef CONFIG_IWLWIFI_DEBUG
  905. /* Set "1" to report good data frames in groups of 100 */
  906. if (unlikely(iwl_get_debug_level(priv) & IWL_DL_RX))
  907. iwlagn_dbg_report_frame(priv, phy_res, len, header, 1);
  908. #endif
  909. iwl_dbg_log_rx_data_frame(priv, len, header);
  910. IWL_DEBUG_STATS_LIMIT(priv, "Rssi %d, TSF %llu\n",
  911. rx_status.signal, (unsigned long long)rx_status.mactime);
  912. /*
  913. * "antenna number"
  914. *
  915. * It seems that the antenna field in the phy flags value
  916. * is actually a bit field. This is undefined by radiotap,
  917. * it wants an actual antenna number but I always get "7"
  918. * for most legacy frames I receive indicating that the
  919. * same frame was received on all three RX chains.
  920. *
  921. * I think this field should be removed in favor of a
  922. * new 802.11n radiotap field "RX chains" that is defined
  923. * as a bitmask.
  924. */
  925. rx_status.antenna =
  926. (le16_to_cpu(phy_res->phy_flags) & RX_RES_PHY_FLAGS_ANTENNA_MSK)
  927. >> RX_RES_PHY_FLAGS_ANTENNA_POS;
  928. /* set the preamble flag if appropriate */
  929. if (phy_res->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
  930. rx_status.flag |= RX_FLAG_SHORTPRE;
  931. /* Set up the HT phy flags */
  932. if (rate_n_flags & RATE_MCS_HT_MSK)
  933. rx_status.flag |= RX_FLAG_HT;
  934. if (rate_n_flags & RATE_MCS_HT40_MSK)
  935. rx_status.flag |= RX_FLAG_40MHZ;
  936. if (rate_n_flags & RATE_MCS_SGI_MSK)
  937. rx_status.flag |= RX_FLAG_SHORT_GI;
  938. iwlagn_pass_packet_to_mac80211(priv, header, len, ampdu_status,
  939. rxb, &rx_status);
  940. }
  941. /* Cache phy data (Rx signal strength, etc) for HT frame (REPLY_RX_PHY_CMD).
  942. * This will be used later in iwl_rx_reply_rx() for REPLY_RX_MPDU_CMD. */
  943. void iwlagn_rx_reply_rx_phy(struct iwl_priv *priv,
  944. struct iwl_rx_mem_buffer *rxb)
  945. {
  946. struct iwl_rx_packet *pkt = rxb_addr(rxb);
  947. priv->_agn.last_phy_res_valid = true;
  948. memcpy(&priv->_agn.last_phy_res, pkt->u.raw,
  949. sizeof(struct iwl_rx_phy_res));
  950. }
  951. static int iwl_get_single_channel_for_scan(struct iwl_priv *priv,
  952. struct ieee80211_vif *vif,
  953. enum ieee80211_band band,
  954. struct iwl_scan_channel *scan_ch)
  955. {
  956. const struct ieee80211_supported_band *sband;
  957. const struct iwl_channel_info *ch_info;
  958. u16 passive_dwell = 0;
  959. u16 active_dwell = 0;
  960. int i, added = 0;
  961. u16 channel = 0;
  962. sband = iwl_get_hw_mode(priv, band);
  963. if (!sband) {
  964. IWL_ERR(priv, "invalid band\n");
  965. return added;
  966. }
  967. active_dwell = iwl_get_active_dwell_time(priv, band, 0);
  968. passive_dwell = iwl_get_passive_dwell_time(priv, band, vif);
  969. if (passive_dwell <= active_dwell)
  970. passive_dwell = active_dwell + 1;
  971. /* only scan single channel, good enough to reset the RF */
  972. /* pick the first valid not in-use channel */
  973. if (band == IEEE80211_BAND_5GHZ) {
  974. for (i = 14; i < priv->channel_count; i++) {
  975. if (priv->channel_info[i].channel !=
  976. le16_to_cpu(priv->staging_rxon.channel)) {
  977. channel = priv->channel_info[i].channel;
  978. ch_info = iwl_get_channel_info(priv,
  979. band, channel);
  980. if (is_channel_valid(ch_info))
  981. break;
  982. }
  983. }
  984. } else {
  985. for (i = 0; i < 14; i++) {
  986. if (priv->channel_info[i].channel !=
  987. le16_to_cpu(priv->staging_rxon.channel)) {
  988. channel =
  989. priv->channel_info[i].channel;
  990. ch_info = iwl_get_channel_info(priv,
  991. band, channel);
  992. if (is_channel_valid(ch_info))
  993. break;
  994. }
  995. }
  996. }
  997. if (channel) {
  998. scan_ch->channel = cpu_to_le16(channel);
  999. scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
  1000. scan_ch->active_dwell = cpu_to_le16(active_dwell);
  1001. scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
  1002. /* Set txpower levels to defaults */
  1003. scan_ch->dsp_atten = 110;
  1004. if (band == IEEE80211_BAND_5GHZ)
  1005. scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
  1006. else
  1007. scan_ch->tx_gain = ((1 << 5) | (5 << 3));
  1008. added++;
  1009. } else
  1010. IWL_ERR(priv, "no valid channel found\n");
  1011. return added;
  1012. }
  1013. static int iwl_get_channels_for_scan(struct iwl_priv *priv,
  1014. struct ieee80211_vif *vif,
  1015. enum ieee80211_band band,
  1016. u8 is_active, u8 n_probes,
  1017. struct iwl_scan_channel *scan_ch)
  1018. {
  1019. struct ieee80211_channel *chan;
  1020. const struct ieee80211_supported_band *sband;
  1021. const struct iwl_channel_info *ch_info;
  1022. u16 passive_dwell = 0;
  1023. u16 active_dwell = 0;
  1024. int added, i;
  1025. u16 channel;
  1026. sband = iwl_get_hw_mode(priv, band);
  1027. if (!sband)
  1028. return 0;
  1029. active_dwell = iwl_get_active_dwell_time(priv, band, n_probes);
  1030. passive_dwell = iwl_get_passive_dwell_time(priv, band, vif);
  1031. if (passive_dwell <= active_dwell)
  1032. passive_dwell = active_dwell + 1;
  1033. for (i = 0, added = 0; i < priv->scan_request->n_channels; i++) {
  1034. chan = priv->scan_request->channels[i];
  1035. if (chan->band != band)
  1036. continue;
  1037. channel = ieee80211_frequency_to_channel(chan->center_freq);
  1038. scan_ch->channel = cpu_to_le16(channel);
  1039. ch_info = iwl_get_channel_info(priv, band, channel);
  1040. if (!is_channel_valid(ch_info)) {
  1041. IWL_DEBUG_SCAN(priv, "Channel %d is INVALID for this band.\n",
  1042. channel);
  1043. continue;
  1044. }
  1045. if (!is_active || is_channel_passive(ch_info) ||
  1046. (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN))
  1047. scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE;
  1048. else
  1049. scan_ch->type = SCAN_CHANNEL_TYPE_ACTIVE;
  1050. if (n_probes)
  1051. scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes);
  1052. scan_ch->active_dwell = cpu_to_le16(active_dwell);
  1053. scan_ch->passive_dwell = cpu_to_le16(passive_dwell);
  1054. /* Set txpower levels to defaults */
  1055. scan_ch->dsp_atten = 110;
  1056. /* NOTE: if we were doing 6Mb OFDM for scans we'd use
  1057. * power level:
  1058. * scan_ch->tx_gain = ((1 << 5) | (2 << 3)) | 3;
  1059. */
  1060. if (band == IEEE80211_BAND_5GHZ)
  1061. scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3;
  1062. else
  1063. scan_ch->tx_gain = ((1 << 5) | (5 << 3));
  1064. IWL_DEBUG_SCAN(priv, "Scanning ch=%d prob=0x%X [%s %d]\n",
  1065. channel, le32_to_cpu(scan_ch->type),
  1066. (scan_ch->type & SCAN_CHANNEL_TYPE_ACTIVE) ?
  1067. "ACTIVE" : "PASSIVE",
  1068. (scan_ch->type & SCAN_CHANNEL_TYPE_ACTIVE) ?
  1069. active_dwell : passive_dwell);
  1070. scan_ch++;
  1071. added++;
  1072. }
  1073. IWL_DEBUG_SCAN(priv, "total channels to scan %d\n", added);
  1074. return added;
  1075. }
  1076. void iwlagn_request_scan(struct iwl_priv *priv, struct ieee80211_vif *vif)
  1077. {
  1078. struct iwl_host_cmd cmd = {
  1079. .id = REPLY_SCAN_CMD,
  1080. .len = sizeof(struct iwl_scan_cmd),
  1081. .flags = CMD_SIZE_HUGE,
  1082. };
  1083. struct iwl_scan_cmd *scan;
  1084. struct ieee80211_conf *conf = NULL;
  1085. u32 rate_flags = 0;
  1086. u16 cmd_len;
  1087. u16 rx_chain = 0;
  1088. enum ieee80211_band band;
  1089. u8 n_probes = 0;
  1090. u8 rx_ant = priv->hw_params.valid_rx_ant;
  1091. u8 rate;
  1092. bool is_active = false;
  1093. int chan_mod;
  1094. u8 active_chains;
  1095. conf = ieee80211_get_hw_conf(priv->hw);
  1096. cancel_delayed_work(&priv->scan_check);
  1097. if (!iwl_is_ready(priv)) {
  1098. IWL_WARN(priv, "request scan called when driver not ready.\n");
  1099. goto done;
  1100. }
  1101. /* Make sure the scan wasn't canceled before this queued work
  1102. * was given the chance to run... */
  1103. if (!test_bit(STATUS_SCANNING, &priv->status))
  1104. goto done;
  1105. /* This should never be called or scheduled if there is currently
  1106. * a scan active in the hardware. */
  1107. if (test_bit(STATUS_SCAN_HW, &priv->status)) {
  1108. IWL_DEBUG_INFO(priv, "Multiple concurrent scan requests in parallel. "
  1109. "Ignoring second request.\n");
  1110. goto done;
  1111. }
  1112. if (test_bit(STATUS_EXIT_PENDING, &priv->status)) {
  1113. IWL_DEBUG_SCAN(priv, "Aborting scan due to device shutdown\n");
  1114. goto done;
  1115. }
  1116. if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) {
  1117. IWL_DEBUG_HC(priv, "Scan request while abort pending. Queuing.\n");
  1118. goto done;
  1119. }
  1120. if (iwl_is_rfkill(priv)) {
  1121. IWL_DEBUG_HC(priv, "Aborting scan due to RF Kill activation\n");
  1122. goto done;
  1123. }
  1124. if (!test_bit(STATUS_READY, &priv->status)) {
  1125. IWL_DEBUG_HC(priv, "Scan request while uninitialized. Queuing.\n");
  1126. goto done;
  1127. }
  1128. if (!priv->scan_cmd) {
  1129. priv->scan_cmd = kmalloc(sizeof(struct iwl_scan_cmd) +
  1130. IWL_MAX_SCAN_SIZE, GFP_KERNEL);
  1131. if (!priv->scan_cmd) {
  1132. IWL_DEBUG_SCAN(priv,
  1133. "fail to allocate memory for scan\n");
  1134. goto done;
  1135. }
  1136. }
  1137. scan = priv->scan_cmd;
  1138. memset(scan, 0, sizeof(struct iwl_scan_cmd) + IWL_MAX_SCAN_SIZE);
  1139. scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH;
  1140. scan->quiet_time = IWL_ACTIVE_QUIET_TIME;
  1141. if (iwl_is_associated(priv)) {
  1142. u16 interval = 0;
  1143. u32 extra;
  1144. u32 suspend_time = 100;
  1145. u32 scan_suspend_time = 100;
  1146. unsigned long flags;
  1147. IWL_DEBUG_INFO(priv, "Scanning while associated...\n");
  1148. spin_lock_irqsave(&priv->lock, flags);
  1149. interval = vif ? vif->bss_conf.beacon_int : 0;
  1150. spin_unlock_irqrestore(&priv->lock, flags);
  1151. scan->suspend_time = 0;
  1152. scan->max_out_time = cpu_to_le32(200 * 1024);
  1153. if (!interval)
  1154. interval = suspend_time;
  1155. extra = (suspend_time / interval) << 22;
  1156. scan_suspend_time = (extra |
  1157. ((suspend_time % interval) * 1024));
  1158. scan->suspend_time = cpu_to_le32(scan_suspend_time);
  1159. IWL_DEBUG_SCAN(priv, "suspend_time 0x%X beacon interval %d\n",
  1160. scan_suspend_time, interval);
  1161. }
  1162. if (priv->is_internal_short_scan) {
  1163. IWL_DEBUG_SCAN(priv, "Start internal passive scan.\n");
  1164. } else if (priv->scan_request->n_ssids) {
  1165. int i, p = 0;
  1166. IWL_DEBUG_SCAN(priv, "Kicking off active scan\n");
  1167. for (i = 0; i < priv->scan_request->n_ssids; i++) {
  1168. /* always does wildcard anyway */
  1169. if (!priv->scan_request->ssids[i].ssid_len)
  1170. continue;
  1171. scan->direct_scan[p].id = WLAN_EID_SSID;
  1172. scan->direct_scan[p].len =
  1173. priv->scan_request->ssids[i].ssid_len;
  1174. memcpy(scan->direct_scan[p].ssid,
  1175. priv->scan_request->ssids[i].ssid,
  1176. priv->scan_request->ssids[i].ssid_len);
  1177. n_probes++;
  1178. p++;
  1179. }
  1180. is_active = true;
  1181. } else
  1182. IWL_DEBUG_SCAN(priv, "Start passive scan.\n");
  1183. scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK;
  1184. scan->tx_cmd.sta_id = priv->hw_params.bcast_sta_id;
  1185. scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  1186. switch (priv->scan_band) {
  1187. case IEEE80211_BAND_2GHZ:
  1188. scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK;
  1189. chan_mod = le32_to_cpu(priv->active_rxon.flags & RXON_FLG_CHANNEL_MODE_MSK)
  1190. >> RXON_FLG_CHANNEL_MODE_POS;
  1191. if (chan_mod == CHANNEL_MODE_PURE_40) {
  1192. rate = IWL_RATE_6M_PLCP;
  1193. } else {
  1194. rate = IWL_RATE_1M_PLCP;
  1195. rate_flags = RATE_MCS_CCK_MSK;
  1196. }
  1197. scan->good_CRC_th = IWL_GOOD_CRC_TH_DISABLED;
  1198. break;
  1199. case IEEE80211_BAND_5GHZ:
  1200. rate = IWL_RATE_6M_PLCP;
  1201. /*
  1202. * If active scanning is requested but a certain channel is
  1203. * marked passive, we can do active scanning if we detect
  1204. * transmissions.
  1205. *
  1206. * There is an issue with some firmware versions that triggers
  1207. * a sysassert on a "good CRC threshold" of zero (== disabled),
  1208. * on a radar channel even though this means that we should NOT
  1209. * send probes.
  1210. *
  1211. * The "good CRC threshold" is the number of frames that we
  1212. * need to receive during our dwell time on a channel before
  1213. * sending out probes -- setting this to a huge value will
  1214. * mean we never reach it, but at the same time work around
  1215. * the aforementioned issue. Thus use IWL_GOOD_CRC_TH_NEVER
  1216. * here instead of IWL_GOOD_CRC_TH_DISABLED.
  1217. */
  1218. scan->good_CRC_th = is_active ? IWL_GOOD_CRC_TH_DEFAULT :
  1219. IWL_GOOD_CRC_TH_NEVER;
  1220. break;
  1221. default:
  1222. IWL_WARN(priv, "Invalid scan band count\n");
  1223. goto done;
  1224. }
  1225. band = priv->scan_band;
  1226. if (priv->cfg->scan_antennas[band])
  1227. rx_ant = priv->cfg->scan_antennas[band];
  1228. priv->scan_tx_ant[band] =
  1229. iwl_toggle_tx_ant(priv, priv->scan_tx_ant[band]);
  1230. rate_flags |= iwl_ant_idx_to_flags(priv->scan_tx_ant[band]);
  1231. scan->tx_cmd.rate_n_flags = iwl_hw_set_rate_n_flags(rate, rate_flags);
  1232. /* In power save mode use one chain, otherwise use all chains */
  1233. if (test_bit(STATUS_POWER_PMI, &priv->status)) {
  1234. /* rx_ant has been set to all valid chains previously */
  1235. active_chains = rx_ant &
  1236. ((u8)(priv->chain_noise_data.active_chains));
  1237. if (!active_chains)
  1238. active_chains = rx_ant;
  1239. IWL_DEBUG_SCAN(priv, "chain_noise_data.active_chains: %u\n",
  1240. priv->chain_noise_data.active_chains);
  1241. rx_ant = first_antenna(active_chains);
  1242. }
  1243. /* MIMO is not used here, but value is required */
  1244. rx_chain |= priv->hw_params.valid_rx_ant << RXON_RX_CHAIN_VALID_POS;
  1245. rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS;
  1246. rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_SEL_POS;
  1247. rx_chain |= 0x1 << RXON_RX_CHAIN_DRIVER_FORCE_POS;
  1248. scan->rx_chain = cpu_to_le16(rx_chain);
  1249. if (!priv->is_internal_short_scan) {
  1250. cmd_len = iwl_fill_probe_req(priv,
  1251. (struct ieee80211_mgmt *)scan->data,
  1252. priv->scan_request->ie,
  1253. priv->scan_request->ie_len,
  1254. IWL_MAX_SCAN_SIZE - sizeof(*scan));
  1255. } else {
  1256. cmd_len = iwl_fill_probe_req(priv,
  1257. (struct ieee80211_mgmt *)scan->data,
  1258. NULL, 0,
  1259. IWL_MAX_SCAN_SIZE - sizeof(*scan));
  1260. }
  1261. scan->tx_cmd.len = cpu_to_le16(cmd_len);
  1262. scan->filter_flags |= (RXON_FILTER_ACCEPT_GRP_MSK |
  1263. RXON_FILTER_BCON_AWARE_MSK);
  1264. if (priv->is_internal_short_scan) {
  1265. scan->channel_count =
  1266. iwl_get_single_channel_for_scan(priv, vif, band,
  1267. (void *)&scan->data[le16_to_cpu(
  1268. scan->tx_cmd.len)]);
  1269. } else {
  1270. scan->channel_count =
  1271. iwl_get_channels_for_scan(priv, vif, band,
  1272. is_active, n_probes,
  1273. (void *)&scan->data[le16_to_cpu(
  1274. scan->tx_cmd.len)]);
  1275. }
  1276. if (scan->channel_count == 0) {
  1277. IWL_DEBUG_SCAN(priv, "channel count %d\n", scan->channel_count);
  1278. goto done;
  1279. }
  1280. cmd.len += le16_to_cpu(scan->tx_cmd.len) +
  1281. scan->channel_count * sizeof(struct iwl_scan_channel);
  1282. cmd.data = scan;
  1283. scan->len = cpu_to_le16(cmd.len);
  1284. set_bit(STATUS_SCAN_HW, &priv->status);
  1285. if (iwl_send_cmd_sync(priv, &cmd))
  1286. goto done;
  1287. queue_delayed_work(priv->workqueue, &priv->scan_check,
  1288. IWL_SCAN_CHECK_WATCHDOG);
  1289. return;
  1290. done:
  1291. /* Cannot perform scan. Make sure we clear scanning
  1292. * bits from status so next scan request can be performed.
  1293. * If we don't clear scanning status bit here all next scan
  1294. * will fail
  1295. */
  1296. clear_bit(STATUS_SCAN_HW, &priv->status);
  1297. clear_bit(STATUS_SCANNING, &priv->status);
  1298. /* inform mac80211 scan aborted */
  1299. queue_work(priv->workqueue, &priv->scan_completed);
  1300. }
  1301. int iwlagn_manage_ibss_station(struct iwl_priv *priv,
  1302. struct ieee80211_vif *vif, bool add)
  1303. {
  1304. struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv;
  1305. if (add)
  1306. return iwl_add_bssid_station(priv, vif->bss_conf.bssid, true,
  1307. &vif_priv->ibss_bssid_sta_id);
  1308. return iwl_remove_station(priv, vif_priv->ibss_bssid_sta_id,
  1309. vif->bss_conf.bssid);
  1310. }