mm-imx5.c 4.2 KB

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  1. /*
  2. * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
  3. *
  4. * The code contained herein is licensed under the GNU General Public
  5. * License. You may obtain a copy of the GNU General Public License
  6. * Version 2 or later at the following locations:
  7. *
  8. * http://www.opensource.org/licenses/gpl-license.html
  9. * http://www.gnu.org/copyleft/gpl.html
  10. *
  11. * Create static mapping between physical to virtual memory.
  12. */
  13. #include <linux/mm.h>
  14. #include <linux/init.h>
  15. #include <linux/clk.h>
  16. #include <linux/pinctrl/machine.h>
  17. #include <linux/of_address.h>
  18. #include <asm/mach/map.h>
  19. #include "common.h"
  20. #include "devices/devices-common.h"
  21. #include "hardware.h"
  22. #include "iomux-v3.h"
  23. /*
  24. * Define the MX51 memory map.
  25. */
  26. static struct map_desc mx51_io_desc[] __initdata = {
  27. imx_map_entry(MX51, TZIC, MT_DEVICE),
  28. imx_map_entry(MX51, IRAM, MT_DEVICE),
  29. imx_map_entry(MX51, AIPS1, MT_DEVICE),
  30. imx_map_entry(MX51, SPBA0, MT_DEVICE),
  31. imx_map_entry(MX51, AIPS2, MT_DEVICE),
  32. };
  33. /*
  34. * Define the MX53 memory map.
  35. */
  36. static struct map_desc mx53_io_desc[] __initdata = {
  37. imx_map_entry(MX53, TZIC, MT_DEVICE),
  38. imx_map_entry(MX53, AIPS1, MT_DEVICE),
  39. imx_map_entry(MX53, SPBA0, MT_DEVICE),
  40. imx_map_entry(MX53, AIPS2, MT_DEVICE),
  41. };
  42. /*
  43. * This function initializes the memory map. It is called during the
  44. * system startup to create static physical to virtual memory mappings
  45. * for the IO modules.
  46. */
  47. void __init mx51_map_io(void)
  48. {
  49. iotable_init(mx51_io_desc, ARRAY_SIZE(mx51_io_desc));
  50. }
  51. void __init mx53_map_io(void)
  52. {
  53. iotable_init(mx53_io_desc, ARRAY_SIZE(mx53_io_desc));
  54. }
  55. /*
  56. * The MIPI HSC unit has been removed from the i.MX51 Reference Manual by
  57. * the Freescale marketing division. However this did not remove the
  58. * hardware from the chip which still needs to be configured for proper
  59. * IPU support.
  60. */
  61. static void __init imx51_ipu_mipi_setup(void)
  62. {
  63. void __iomem *hsc_addr;
  64. hsc_addr = MX51_IO_ADDRESS(MX51_MIPI_HSC_BASE_ADDR);
  65. /* setup MIPI module to legacy mode */
  66. __raw_writel(0xf00, hsc_addr);
  67. /* CSI mode: reserved; DI control mode: legacy (from Freescale BSP) */
  68. __raw_writel(__raw_readl(hsc_addr + 0x800) | 0x30ff,
  69. hsc_addr + 0x800);
  70. }
  71. void __init imx51_init_early(void)
  72. {
  73. imx51_ipu_mipi_setup();
  74. mxc_set_cpu_type(MXC_CPU_MX51);
  75. mxc_iomux_v3_init(MX51_IO_ADDRESS(MX51_IOMUXC_BASE_ADDR));
  76. imx_src_init();
  77. }
  78. void __init imx53_init_early(void)
  79. {
  80. struct device_node *np;
  81. void __iomem *base;
  82. mxc_set_cpu_type(MXC_CPU_MX53);
  83. np = of_find_compatible_node(NULL, NULL, "fsl,imx53-iomuxc");
  84. base = of_iomap(np, 0);
  85. WARN_ON(!base);
  86. mxc_iomux_v3_init(base);
  87. imx_src_init();
  88. }
  89. void __init mx51_init_irq(void)
  90. {
  91. tzic_init_irq(MX51_IO_ADDRESS(MX51_TZIC_BASE_ADDR));
  92. }
  93. void __init mx53_init_irq(void)
  94. {
  95. struct device_node *np;
  96. void __iomem *base;
  97. np = of_find_compatible_node(NULL, NULL, "fsl,imx53-tzic");
  98. base = of_iomap(np, 0);
  99. WARN_ON(!base);
  100. tzic_init_irq(base);
  101. }
  102. static struct sdma_platform_data imx51_sdma_pdata __initdata = {
  103. .fw_name = "sdma-imx51.bin",
  104. };
  105. static const struct resource imx51_audmux_res[] __initconst = {
  106. DEFINE_RES_MEM(MX51_AUDMUX_BASE_ADDR, SZ_16K),
  107. };
  108. void __init imx51_soc_init(void)
  109. {
  110. mxc_arch_reset_init(MX51_IO_ADDRESS(MX51_WDOG1_BASE_ADDR));
  111. mxc_device_init();
  112. /* i.mx51 has the i.mx35 type gpio */
  113. mxc_register_gpio("imx35-gpio", 0, MX51_GPIO1_BASE_ADDR, SZ_16K, MX51_INT_GPIO1_LOW, MX51_INT_GPIO1_HIGH);
  114. mxc_register_gpio("imx35-gpio", 1, MX51_GPIO2_BASE_ADDR, SZ_16K, MX51_INT_GPIO2_LOW, MX51_INT_GPIO2_HIGH);
  115. mxc_register_gpio("imx35-gpio", 2, MX51_GPIO3_BASE_ADDR, SZ_16K, MX51_INT_GPIO3_LOW, MX51_INT_GPIO3_HIGH);
  116. mxc_register_gpio("imx35-gpio", 3, MX51_GPIO4_BASE_ADDR, SZ_16K, MX51_INT_GPIO4_LOW, MX51_INT_GPIO4_HIGH);
  117. pinctrl_provide_dummies();
  118. /* i.mx51 has the i.mx35 type sdma */
  119. imx_add_imx_sdma("imx35-sdma", MX51_SDMA_BASE_ADDR, MX51_INT_SDMA, &imx51_sdma_pdata);
  120. /* Setup AIPS registers */
  121. imx_set_aips(MX51_IO_ADDRESS(MX51_AIPS1_BASE_ADDR));
  122. imx_set_aips(MX51_IO_ADDRESS(MX51_AIPS2_BASE_ADDR));
  123. /* i.mx51 has the i.mx31 type audmux */
  124. platform_device_register_simple("imx31-audmux", 0, imx51_audmux_res,
  125. ARRAY_SIZE(imx51_audmux_res));
  126. }
  127. void __init imx51_init_late(void)
  128. {
  129. mx51_neon_fixup();
  130. imx5_pm_init();
  131. }
  132. void __init imx53_init_late(void)
  133. {
  134. imx5_pm_init();
  135. }