iwl-4965.c 138 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2003 - 2007 Intel Corporation. All rights reserved.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc.,
  16. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17. *
  18. * The full GNU General Public License is included in this distribution in the
  19. * file called LICENSE.
  20. *
  21. * Contact Information:
  22. * James P. Ketrenos <ipw2100-admin@linux.intel.com>
  23. * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  24. *
  25. *****************************************************************************/
  26. #include <linux/kernel.h>
  27. #include <linux/module.h>
  28. #include <linux/version.h>
  29. #include <linux/init.h>
  30. #include <linux/pci.h>
  31. #include <linux/dma-mapping.h>
  32. #include <linux/delay.h>
  33. #include <linux/skbuff.h>
  34. #include <linux/netdevice.h>
  35. #include <linux/wireless.h>
  36. #include <net/mac80211.h>
  37. #include <linux/etherdevice.h>
  38. #include <asm/unaligned.h>
  39. #include "iwl-4965.h"
  40. #include "iwl-helpers.h"
  41. static void iwl4965_hw_card_show_info(struct iwl4965_priv *priv);
  42. #define IWL_DECLARE_RATE_INFO(r, s, ip, in, rp, rn, pp, np) \
  43. [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \
  44. IWL_RATE_SISO_##s##M_PLCP, \
  45. IWL_RATE_MIMO_##s##M_PLCP, \
  46. IWL_RATE_##r##M_IEEE, \
  47. IWL_RATE_##ip##M_INDEX, \
  48. IWL_RATE_##in##M_INDEX, \
  49. IWL_RATE_##rp##M_INDEX, \
  50. IWL_RATE_##rn##M_INDEX, \
  51. IWL_RATE_##pp##M_INDEX, \
  52. IWL_RATE_##np##M_INDEX }
  53. /*
  54. * Parameter order:
  55. * rate, ht rate, prev rate, next rate, prev tgg rate, next tgg rate
  56. *
  57. * If there isn't a valid next or previous rate then INV is used which
  58. * maps to IWL_RATE_INVALID
  59. *
  60. */
  61. const struct iwl4965_rate_info iwl4965_rates[IWL_RATE_COUNT] = {
  62. IWL_DECLARE_RATE_INFO(1, INV, INV, 2, INV, 2, INV, 2), /* 1mbps */
  63. IWL_DECLARE_RATE_INFO(2, INV, 1, 5, 1, 5, 1, 5), /* 2mbps */
  64. IWL_DECLARE_RATE_INFO(5, INV, 2, 6, 2, 11, 2, 11), /*5.5mbps */
  65. IWL_DECLARE_RATE_INFO(11, INV, 9, 12, 9, 12, 5, 18), /* 11mbps */
  66. IWL_DECLARE_RATE_INFO(6, 6, 5, 9, 5, 11, 5, 11), /* 6mbps */
  67. IWL_DECLARE_RATE_INFO(9, 6, 6, 11, 6, 11, 5, 11), /* 9mbps */
  68. IWL_DECLARE_RATE_INFO(12, 12, 11, 18, 11, 18, 11, 18), /* 12mbps */
  69. IWL_DECLARE_RATE_INFO(18, 18, 12, 24, 12, 24, 11, 24), /* 18mbps */
  70. IWL_DECLARE_RATE_INFO(24, 24, 18, 36, 18, 36, 18, 36), /* 24mbps */
  71. IWL_DECLARE_RATE_INFO(36, 36, 24, 48, 24, 48, 24, 48), /* 36mbps */
  72. IWL_DECLARE_RATE_INFO(48, 48, 36, 54, 36, 54, 36, 54), /* 48mbps */
  73. IWL_DECLARE_RATE_INFO(54, 54, 48, INV, 48, INV, 48, INV),/* 54mbps */
  74. IWL_DECLARE_RATE_INFO(60, 60, 48, INV, 48, INV, 48, INV),/* 60mbps */
  75. };
  76. #ifdef CONFIG_IWL4965_HT
  77. static const u16 default_tid_to_tx_fifo[] = {
  78. IWL_TX_FIFO_AC1,
  79. IWL_TX_FIFO_AC0,
  80. IWL_TX_FIFO_AC0,
  81. IWL_TX_FIFO_AC1,
  82. IWL_TX_FIFO_AC2,
  83. IWL_TX_FIFO_AC2,
  84. IWL_TX_FIFO_AC3,
  85. IWL_TX_FIFO_AC3,
  86. IWL_TX_FIFO_NONE,
  87. IWL_TX_FIFO_NONE,
  88. IWL_TX_FIFO_NONE,
  89. IWL_TX_FIFO_NONE,
  90. IWL_TX_FIFO_NONE,
  91. IWL_TX_FIFO_NONE,
  92. IWL_TX_FIFO_NONE,
  93. IWL_TX_FIFO_NONE,
  94. IWL_TX_FIFO_AC3
  95. };
  96. #endif /*CONFIG_IWL4965_HT */
  97. static int is_fat_channel(__le32 rxon_flags)
  98. {
  99. return (rxon_flags & RXON_FLG_CHANNEL_MODE_PURE_40_MSK) ||
  100. (rxon_flags & RXON_FLG_CHANNEL_MODE_MIXED_MSK);
  101. }
  102. static u8 is_single_stream(struct iwl4965_priv *priv)
  103. {
  104. #ifdef CONFIG_IWL4965_HT
  105. if (!priv->current_ht_config.is_ht ||
  106. (priv->current_ht_config.supp_mcs_set[1] == 0) ||
  107. (priv->ps_mode == IWL_MIMO_PS_STATIC))
  108. return 1;
  109. #else
  110. return 1;
  111. #endif /*CONFIG_IWL4965_HT */
  112. return 0;
  113. }
  114. int iwl4965_hwrate_to_plcp_idx(u32 rate_n_flags)
  115. {
  116. int idx = 0;
  117. /* 4965 HT rate format */
  118. if (rate_n_flags & RATE_MCS_HT_MSK) {
  119. idx = (rate_n_flags & 0xff);
  120. if (idx >= IWL_RATE_MIMO_6M_PLCP)
  121. idx = idx - IWL_RATE_MIMO_6M_PLCP;
  122. idx += IWL_FIRST_OFDM_RATE;
  123. /* skip 9M not supported in ht*/
  124. if (idx >= IWL_RATE_9M_INDEX)
  125. idx += 1;
  126. if ((idx >= IWL_FIRST_OFDM_RATE) && (idx <= IWL_LAST_OFDM_RATE))
  127. return idx;
  128. /* 4965 legacy rate format, search for match in table */
  129. } else {
  130. for (idx = 0; idx < ARRAY_SIZE(iwl4965_rates); idx++)
  131. if (iwl4965_rates[idx].plcp == (rate_n_flags & 0xFF))
  132. return idx;
  133. }
  134. return -1;
  135. }
  136. /**
  137. * translate ucode response to mac80211 tx status control values
  138. */
  139. void iwl4965_hwrate_to_tx_control(struct iwl4965_priv *priv, u32 rate_n_flags,
  140. struct ieee80211_tx_control *control)
  141. {
  142. int rate_index;
  143. control->antenna_sel_tx =
  144. ((rate_n_flags & RATE_MCS_ANT_AB_MSK) >> RATE_MCS_ANT_A_POS);
  145. if (rate_n_flags & RATE_MCS_HT_MSK)
  146. control->flags |= IEEE80211_TXCTL_OFDM_HT;
  147. if (rate_n_flags & RATE_MCS_GF_MSK)
  148. control->flags |= IEEE80211_TXCTL_GREEN_FIELD;
  149. if (rate_n_flags & RATE_MCS_FAT_MSK)
  150. control->flags |= IEEE80211_TXCTL_40_MHZ_WIDTH;
  151. if (rate_n_flags & RATE_MCS_DUP_MSK)
  152. control->flags |= IEEE80211_TXCTL_DUP_DATA;
  153. if (rate_n_flags & RATE_MCS_SGI_MSK)
  154. control->flags |= IEEE80211_TXCTL_SHORT_GI;
  155. /* since iwl4965_hwrate_to_plcp_idx is band indifferent, we always use
  156. * IEEE80211_BAND_2GHZ band as it contains all the rates */
  157. rate_index = iwl4965_hwrate_to_plcp_idx(rate_n_flags);
  158. if (rate_index == -1)
  159. control->tx_rate = NULL;
  160. else
  161. control->tx_rate =
  162. &priv->bands[IEEE80211_BAND_2GHZ].bitrates[rate_index];
  163. }
  164. /*
  165. * Determine how many receiver/antenna chains to use.
  166. * More provides better reception via diversity. Fewer saves power.
  167. * MIMO (dual stream) requires at least 2, but works better with 3.
  168. * This does not determine *which* chains to use, just how many.
  169. */
  170. static int iwl4965_get_rx_chain_counter(struct iwl4965_priv *priv,
  171. u8 *idle_state, u8 *rx_state)
  172. {
  173. u8 is_single = is_single_stream(priv);
  174. u8 is_cam = test_bit(STATUS_POWER_PMI, &priv->status) ? 0 : 1;
  175. /* # of Rx chains to use when expecting MIMO. */
  176. if (is_single || (!is_cam && (priv->ps_mode == IWL_MIMO_PS_STATIC)))
  177. *rx_state = 2;
  178. else
  179. *rx_state = 3;
  180. /* # Rx chains when idling and maybe trying to save power */
  181. switch (priv->ps_mode) {
  182. case IWL_MIMO_PS_STATIC:
  183. case IWL_MIMO_PS_DYNAMIC:
  184. *idle_state = (is_cam) ? 2 : 1;
  185. break;
  186. case IWL_MIMO_PS_NONE:
  187. *idle_state = (is_cam) ? *rx_state : 1;
  188. break;
  189. default:
  190. *idle_state = 1;
  191. break;
  192. }
  193. return 0;
  194. }
  195. int iwl4965_hw_rxq_stop(struct iwl4965_priv *priv)
  196. {
  197. int rc;
  198. unsigned long flags;
  199. spin_lock_irqsave(&priv->lock, flags);
  200. rc = iwl4965_grab_nic_access(priv);
  201. if (rc) {
  202. spin_unlock_irqrestore(&priv->lock, flags);
  203. return rc;
  204. }
  205. /* stop Rx DMA */
  206. iwl4965_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
  207. rc = iwl4965_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG,
  208. (1 << 24), 1000);
  209. if (rc < 0)
  210. IWL_ERROR("Can't stop Rx DMA.\n");
  211. iwl4965_release_nic_access(priv);
  212. spin_unlock_irqrestore(&priv->lock, flags);
  213. return 0;
  214. }
  215. u8 iwl4965_hw_find_station(struct iwl4965_priv *priv, const u8 *addr)
  216. {
  217. int i;
  218. int start = 0;
  219. int ret = IWL_INVALID_STATION;
  220. unsigned long flags;
  221. DECLARE_MAC_BUF(mac);
  222. if ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS) ||
  223. (priv->iw_mode == IEEE80211_IF_TYPE_AP))
  224. start = IWL_STA_ID;
  225. if (is_broadcast_ether_addr(addr))
  226. return IWL4965_BROADCAST_ID;
  227. spin_lock_irqsave(&priv->sta_lock, flags);
  228. for (i = start; i < priv->hw_setting.max_stations; i++)
  229. if ((priv->stations[i].used) &&
  230. (!compare_ether_addr
  231. (priv->stations[i].sta.sta.addr, addr))) {
  232. ret = i;
  233. goto out;
  234. }
  235. IWL_DEBUG_ASSOC_LIMIT("can not find STA %s total %d\n",
  236. print_mac(mac, addr), priv->num_stations);
  237. out:
  238. spin_unlock_irqrestore(&priv->sta_lock, flags);
  239. return ret;
  240. }
  241. static int iwl4965_nic_set_pwr_src(struct iwl4965_priv *priv, int pwr_max)
  242. {
  243. int ret;
  244. unsigned long flags;
  245. spin_lock_irqsave(&priv->lock, flags);
  246. ret = iwl4965_grab_nic_access(priv);
  247. if (ret) {
  248. spin_unlock_irqrestore(&priv->lock, flags);
  249. return ret;
  250. }
  251. if (!pwr_max) {
  252. u32 val;
  253. ret = pci_read_config_dword(priv->pci_dev, PCI_POWER_SOURCE,
  254. &val);
  255. if (val & PCI_CFG_PMC_PME_FROM_D3COLD_SUPPORT)
  256. iwl4965_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  257. APMG_PS_CTRL_VAL_PWR_SRC_VAUX,
  258. ~APMG_PS_CTRL_MSK_PWR_SRC);
  259. } else
  260. iwl4965_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
  261. APMG_PS_CTRL_VAL_PWR_SRC_VMAIN,
  262. ~APMG_PS_CTRL_MSK_PWR_SRC);
  263. iwl4965_release_nic_access(priv);
  264. spin_unlock_irqrestore(&priv->lock, flags);
  265. return ret;
  266. }
  267. static int iwl4965_rx_init(struct iwl4965_priv *priv, struct iwl4965_rx_queue *rxq)
  268. {
  269. int rc;
  270. unsigned long flags;
  271. unsigned int rb_size;
  272. spin_lock_irqsave(&priv->lock, flags);
  273. rc = iwl4965_grab_nic_access(priv);
  274. if (rc) {
  275. spin_unlock_irqrestore(&priv->lock, flags);
  276. return rc;
  277. }
  278. if (iwl4965_param_amsdu_size_8K)
  279. rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K;
  280. else
  281. rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K;
  282. /* Stop Rx DMA */
  283. iwl4965_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
  284. /* Reset driver's Rx queue write index */
  285. iwl4965_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0);
  286. /* Tell device where to find RBD circular buffer in DRAM */
  287. iwl4965_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG,
  288. rxq->dma_addr >> 8);
  289. /* Tell device where in DRAM to update its Rx status */
  290. iwl4965_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG,
  291. (priv->hw_setting.shared_phys +
  292. offsetof(struct iwl4965_shared, val0)) >> 4);
  293. /* Enable Rx DMA, enable host interrupt, Rx buffer size 4k, 256 RBDs */
  294. iwl4965_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG,
  295. FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL |
  296. FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL |
  297. rb_size |
  298. /*0x10 << 4 | */
  299. (RX_QUEUE_SIZE_LOG <<
  300. FH_RCSR_RX_CONFIG_RBDCB_SIZE_BITSHIFT));
  301. /*
  302. * iwl4965_write32(priv,CSR_INT_COAL_REG,0);
  303. */
  304. iwl4965_release_nic_access(priv);
  305. spin_unlock_irqrestore(&priv->lock, flags);
  306. return 0;
  307. }
  308. /* Tell 4965 where to find the "keep warm" buffer */
  309. static int iwl4965_kw_init(struct iwl4965_priv *priv)
  310. {
  311. unsigned long flags;
  312. int rc;
  313. spin_lock_irqsave(&priv->lock, flags);
  314. rc = iwl4965_grab_nic_access(priv);
  315. if (rc)
  316. goto out;
  317. iwl4965_write_direct32(priv, IWL_FH_KW_MEM_ADDR_REG,
  318. priv->kw.dma_addr >> 4);
  319. iwl4965_release_nic_access(priv);
  320. out:
  321. spin_unlock_irqrestore(&priv->lock, flags);
  322. return rc;
  323. }
  324. static int iwl4965_kw_alloc(struct iwl4965_priv *priv)
  325. {
  326. struct pci_dev *dev = priv->pci_dev;
  327. struct iwl4965_kw *kw = &priv->kw;
  328. kw->size = IWL4965_KW_SIZE; /* TBW need set somewhere else */
  329. kw->v_addr = pci_alloc_consistent(dev, kw->size, &kw->dma_addr);
  330. if (!kw->v_addr)
  331. return -ENOMEM;
  332. return 0;
  333. }
  334. #define CHECK_AND_PRINT(x) ((eeprom_ch->flags & EEPROM_CHANNEL_##x) \
  335. ? # x " " : "")
  336. /**
  337. * iwl4965_set_fat_chan_info - Copy fat channel info into driver's priv.
  338. *
  339. * Does not set up a command, or touch hardware.
  340. */
  341. int iwl4965_set_fat_chan_info(struct iwl4965_priv *priv,
  342. enum ieee80211_band band, u16 channel,
  343. const struct iwl4965_eeprom_channel *eeprom_ch,
  344. u8 fat_extension_channel)
  345. {
  346. struct iwl4965_channel_info *ch_info;
  347. ch_info = (struct iwl4965_channel_info *)
  348. iwl4965_get_channel_info(priv, band, channel);
  349. if (!is_channel_valid(ch_info))
  350. return -1;
  351. IWL_DEBUG_INFO("FAT Ch. %d [%sGHz] %s%s%s%s%s%s(0x%02x"
  352. " %ddBm): Ad-Hoc %ssupported\n",
  353. ch_info->channel,
  354. is_channel_a_band(ch_info) ?
  355. "5.2" : "2.4",
  356. CHECK_AND_PRINT(IBSS),
  357. CHECK_AND_PRINT(ACTIVE),
  358. CHECK_AND_PRINT(RADAR),
  359. CHECK_AND_PRINT(WIDE),
  360. CHECK_AND_PRINT(NARROW),
  361. CHECK_AND_PRINT(DFS),
  362. eeprom_ch->flags,
  363. eeprom_ch->max_power_avg,
  364. ((eeprom_ch->flags & EEPROM_CHANNEL_IBSS)
  365. && !(eeprom_ch->flags & EEPROM_CHANNEL_RADAR)) ?
  366. "" : "not ");
  367. ch_info->fat_eeprom = *eeprom_ch;
  368. ch_info->fat_max_power_avg = eeprom_ch->max_power_avg;
  369. ch_info->fat_curr_txpow = eeprom_ch->max_power_avg;
  370. ch_info->fat_min_power = 0;
  371. ch_info->fat_scan_power = eeprom_ch->max_power_avg;
  372. ch_info->fat_flags = eeprom_ch->flags;
  373. ch_info->fat_extension_channel = fat_extension_channel;
  374. return 0;
  375. }
  376. /**
  377. * iwl4965_kw_free - Free the "keep warm" buffer
  378. */
  379. static void iwl4965_kw_free(struct iwl4965_priv *priv)
  380. {
  381. struct pci_dev *dev = priv->pci_dev;
  382. struct iwl4965_kw *kw = &priv->kw;
  383. if (kw->v_addr) {
  384. pci_free_consistent(dev, kw->size, kw->v_addr, kw->dma_addr);
  385. memset(kw, 0, sizeof(*kw));
  386. }
  387. }
  388. /**
  389. * iwl4965_txq_ctx_reset - Reset TX queue context
  390. * Destroys all DMA structures and initialise them again
  391. *
  392. * @param priv
  393. * @return error code
  394. */
  395. static int iwl4965_txq_ctx_reset(struct iwl4965_priv *priv)
  396. {
  397. int rc = 0;
  398. int txq_id, slots_num;
  399. unsigned long flags;
  400. iwl4965_kw_free(priv);
  401. /* Free all tx/cmd queues and keep-warm buffer */
  402. iwl4965_hw_txq_ctx_free(priv);
  403. /* Alloc keep-warm buffer */
  404. rc = iwl4965_kw_alloc(priv);
  405. if (rc) {
  406. IWL_ERROR("Keep Warm allocation failed");
  407. goto error_kw;
  408. }
  409. spin_lock_irqsave(&priv->lock, flags);
  410. rc = iwl4965_grab_nic_access(priv);
  411. if (unlikely(rc)) {
  412. IWL_ERROR("TX reset failed");
  413. spin_unlock_irqrestore(&priv->lock, flags);
  414. goto error_reset;
  415. }
  416. /* Turn off all Tx DMA channels */
  417. iwl4965_write_prph(priv, KDR_SCD_TXFACT, 0);
  418. iwl4965_release_nic_access(priv);
  419. spin_unlock_irqrestore(&priv->lock, flags);
  420. /* Tell 4965 where to find the keep-warm buffer */
  421. rc = iwl4965_kw_init(priv);
  422. if (rc) {
  423. IWL_ERROR("kw_init failed\n");
  424. goto error_reset;
  425. }
  426. /* Alloc and init all (default 16) Tx queues,
  427. * including the command queue (#4) */
  428. for (txq_id = 0; txq_id < priv->hw_setting.max_txq_num; txq_id++) {
  429. slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ?
  430. TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS;
  431. rc = iwl4965_tx_queue_init(priv, &priv->txq[txq_id], slots_num,
  432. txq_id);
  433. if (rc) {
  434. IWL_ERROR("Tx %d queue init failed\n", txq_id);
  435. goto error;
  436. }
  437. }
  438. return rc;
  439. error:
  440. iwl4965_hw_txq_ctx_free(priv);
  441. error_reset:
  442. iwl4965_kw_free(priv);
  443. error_kw:
  444. return rc;
  445. }
  446. int iwl4965_hw_nic_init(struct iwl4965_priv *priv)
  447. {
  448. int rc;
  449. unsigned long flags;
  450. struct iwl4965_rx_queue *rxq = &priv->rxq;
  451. u8 rev_id;
  452. u32 val;
  453. u8 val_link;
  454. iwl4965_power_init_handle(priv);
  455. /* nic_init */
  456. spin_lock_irqsave(&priv->lock, flags);
  457. iwl4965_set_bit(priv, CSR_GIO_CHICKEN_BITS,
  458. CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
  459. iwl4965_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  460. rc = iwl4965_poll_bit(priv, CSR_GP_CNTRL,
  461. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
  462. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
  463. if (rc < 0) {
  464. spin_unlock_irqrestore(&priv->lock, flags);
  465. IWL_DEBUG_INFO("Failed to init the card\n");
  466. return rc;
  467. }
  468. rc = iwl4965_grab_nic_access(priv);
  469. if (rc) {
  470. spin_unlock_irqrestore(&priv->lock, flags);
  471. return rc;
  472. }
  473. iwl4965_read_prph(priv, APMG_CLK_CTRL_REG);
  474. iwl4965_write_prph(priv, APMG_CLK_CTRL_REG,
  475. APMG_CLK_VAL_DMA_CLK_RQT |
  476. APMG_CLK_VAL_BSM_CLK_RQT);
  477. iwl4965_read_prph(priv, APMG_CLK_CTRL_REG);
  478. udelay(20);
  479. iwl4965_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
  480. APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
  481. iwl4965_release_nic_access(priv);
  482. iwl4965_write32(priv, CSR_INT_COALESCING, 512 / 32);
  483. spin_unlock_irqrestore(&priv->lock, flags);
  484. /* Determine HW type */
  485. rc = pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id);
  486. if (rc)
  487. return rc;
  488. IWL_DEBUG_INFO("HW Revision ID = 0x%X\n", rev_id);
  489. iwl4965_nic_set_pwr_src(priv, 1);
  490. spin_lock_irqsave(&priv->lock, flags);
  491. if ((rev_id & 0x80) == 0x80 && (rev_id & 0x7f) < 8) {
  492. pci_read_config_dword(priv->pci_dev, PCI_REG_WUM8, &val);
  493. /* Enable No Snoop field */
  494. pci_write_config_dword(priv->pci_dev, PCI_REG_WUM8,
  495. val & ~(1 << 11));
  496. }
  497. spin_unlock_irqrestore(&priv->lock, flags);
  498. if (priv->eeprom.calib_version < EEPROM_TX_POWER_VERSION_NEW) {
  499. IWL_ERROR("Older EEPROM detected! Aborting.\n");
  500. return -EINVAL;
  501. }
  502. pci_read_config_byte(priv->pci_dev, PCI_LINK_CTRL, &val_link);
  503. /* disable L1 entry -- workaround for pre-B1 */
  504. pci_write_config_byte(priv->pci_dev, PCI_LINK_CTRL, val_link & ~0x02);
  505. spin_lock_irqsave(&priv->lock, flags);
  506. /* set CSR_HW_CONFIG_REG for uCode use */
  507. iwl4965_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  508. CSR49_HW_IF_CONFIG_REG_BIT_4965_R |
  509. CSR49_HW_IF_CONFIG_REG_BIT_RADIO_SI |
  510. CSR49_HW_IF_CONFIG_REG_BIT_MAC_SI);
  511. rc = iwl4965_grab_nic_access(priv);
  512. if (rc < 0) {
  513. spin_unlock_irqrestore(&priv->lock, flags);
  514. IWL_DEBUG_INFO("Failed to init the card\n");
  515. return rc;
  516. }
  517. iwl4965_read_prph(priv, APMG_PS_CTRL_REG);
  518. iwl4965_set_bits_prph(priv, APMG_PS_CTRL_REG,
  519. APMG_PS_CTRL_VAL_RESET_REQ);
  520. udelay(5);
  521. iwl4965_clear_bits_prph(priv, APMG_PS_CTRL_REG,
  522. APMG_PS_CTRL_VAL_RESET_REQ);
  523. iwl4965_release_nic_access(priv);
  524. spin_unlock_irqrestore(&priv->lock, flags);
  525. iwl4965_hw_card_show_info(priv);
  526. /* end nic_init */
  527. /* Allocate the RX queue, or reset if it is already allocated */
  528. if (!rxq->bd) {
  529. rc = iwl4965_rx_queue_alloc(priv);
  530. if (rc) {
  531. IWL_ERROR("Unable to initialize Rx queue\n");
  532. return -ENOMEM;
  533. }
  534. } else
  535. iwl4965_rx_queue_reset(priv, rxq);
  536. iwl4965_rx_replenish(priv);
  537. iwl4965_rx_init(priv, rxq);
  538. spin_lock_irqsave(&priv->lock, flags);
  539. rxq->need_update = 1;
  540. iwl4965_rx_queue_update_write_ptr(priv, rxq);
  541. spin_unlock_irqrestore(&priv->lock, flags);
  542. /* Allocate and init all Tx and Command queues */
  543. rc = iwl4965_txq_ctx_reset(priv);
  544. if (rc)
  545. return rc;
  546. if (priv->eeprom.sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE)
  547. IWL_DEBUG_RF_KILL("SW RF KILL supported in EEPROM.\n");
  548. if (priv->eeprom.sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE)
  549. IWL_DEBUG_RF_KILL("HW RF KILL supported in EEPROM.\n");
  550. set_bit(STATUS_INIT, &priv->status);
  551. return 0;
  552. }
  553. int iwl4965_hw_nic_stop_master(struct iwl4965_priv *priv)
  554. {
  555. int rc = 0;
  556. u32 reg_val;
  557. unsigned long flags;
  558. spin_lock_irqsave(&priv->lock, flags);
  559. /* set stop master bit */
  560. iwl4965_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
  561. reg_val = iwl4965_read32(priv, CSR_GP_CNTRL);
  562. if (CSR_GP_CNTRL_REG_FLAG_MAC_POWER_SAVE ==
  563. (reg_val & CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE))
  564. IWL_DEBUG_INFO("Card in power save, master is already "
  565. "stopped\n");
  566. else {
  567. rc = iwl4965_poll_bit(priv, CSR_RESET,
  568. CSR_RESET_REG_FLAG_MASTER_DISABLED,
  569. CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
  570. if (rc < 0) {
  571. spin_unlock_irqrestore(&priv->lock, flags);
  572. return rc;
  573. }
  574. }
  575. spin_unlock_irqrestore(&priv->lock, flags);
  576. IWL_DEBUG_INFO("stop master\n");
  577. return rc;
  578. }
  579. /**
  580. * iwl4965_hw_txq_ctx_stop - Stop all Tx DMA channels, free Tx queue memory
  581. */
  582. void iwl4965_hw_txq_ctx_stop(struct iwl4965_priv *priv)
  583. {
  584. int txq_id;
  585. unsigned long flags;
  586. /* Stop each Tx DMA channel, and wait for it to be idle */
  587. for (txq_id = 0; txq_id < priv->hw_setting.max_txq_num; txq_id++) {
  588. spin_lock_irqsave(&priv->lock, flags);
  589. if (iwl4965_grab_nic_access(priv)) {
  590. spin_unlock_irqrestore(&priv->lock, flags);
  591. continue;
  592. }
  593. iwl4965_write_direct32(priv,
  594. IWL_FH_TCSR_CHNL_TX_CONFIG_REG(txq_id),
  595. 0x0);
  596. iwl4965_poll_direct_bit(priv, IWL_FH_TSSR_TX_STATUS_REG,
  597. IWL_FH_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE
  598. (txq_id), 200);
  599. iwl4965_release_nic_access(priv);
  600. spin_unlock_irqrestore(&priv->lock, flags);
  601. }
  602. /* Deallocate memory for all Tx queues */
  603. iwl4965_hw_txq_ctx_free(priv);
  604. }
  605. int iwl4965_hw_nic_reset(struct iwl4965_priv *priv)
  606. {
  607. int rc = 0;
  608. unsigned long flags;
  609. iwl4965_hw_nic_stop_master(priv);
  610. spin_lock_irqsave(&priv->lock, flags);
  611. iwl4965_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
  612. udelay(10);
  613. iwl4965_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
  614. rc = iwl4965_poll_bit(priv, CSR_RESET,
  615. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
  616. CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25);
  617. udelay(10);
  618. rc = iwl4965_grab_nic_access(priv);
  619. if (!rc) {
  620. iwl4965_write_prph(priv, APMG_CLK_EN_REG,
  621. APMG_CLK_VAL_DMA_CLK_RQT |
  622. APMG_CLK_VAL_BSM_CLK_RQT);
  623. udelay(10);
  624. iwl4965_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
  625. APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
  626. iwl4965_release_nic_access(priv);
  627. }
  628. clear_bit(STATUS_HCMD_ACTIVE, &priv->status);
  629. wake_up_interruptible(&priv->wait_command_queue);
  630. spin_unlock_irqrestore(&priv->lock, flags);
  631. return rc;
  632. }
  633. #define REG_RECALIB_PERIOD (60)
  634. /**
  635. * iwl4965_bg_statistics_periodic - Timer callback to queue statistics
  636. *
  637. * This callback is provided in order to queue the statistics_work
  638. * in work_queue context (v. softirq)
  639. *
  640. * This timer function is continually reset to execute within
  641. * REG_RECALIB_PERIOD seconds since the last STATISTICS_NOTIFICATION
  642. * was received. We need to ensure we receive the statistics in order
  643. * to update the temperature used for calibrating the TXPOWER. However,
  644. * we can't send the statistics command from softirq context (which
  645. * is the context which timers run at) so we have to queue off the
  646. * statistics_work to actually send the command to the hardware.
  647. */
  648. static void iwl4965_bg_statistics_periodic(unsigned long data)
  649. {
  650. struct iwl4965_priv *priv = (struct iwl4965_priv *)data;
  651. queue_work(priv->workqueue, &priv->statistics_work);
  652. }
  653. /**
  654. * iwl4965_bg_statistics_work - Send the statistics request to the hardware.
  655. *
  656. * This is queued by iwl4965_bg_statistics_periodic.
  657. */
  658. static void iwl4965_bg_statistics_work(struct work_struct *work)
  659. {
  660. struct iwl4965_priv *priv = container_of(work, struct iwl4965_priv,
  661. statistics_work);
  662. if (test_bit(STATUS_EXIT_PENDING, &priv->status))
  663. return;
  664. mutex_lock(&priv->mutex);
  665. iwl4965_send_statistics_request(priv);
  666. mutex_unlock(&priv->mutex);
  667. }
  668. #define CT_LIMIT_CONST 259
  669. #define TM_CT_KILL_THRESHOLD 110
  670. void iwl4965_rf_kill_ct_config(struct iwl4965_priv *priv)
  671. {
  672. struct iwl4965_ct_kill_config cmd;
  673. u32 R1, R2, R3;
  674. u32 temp_th;
  675. u32 crit_temperature;
  676. unsigned long flags;
  677. int rc = 0;
  678. spin_lock_irqsave(&priv->lock, flags);
  679. iwl4965_write32(priv, CSR_UCODE_DRV_GP1_CLR,
  680. CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT);
  681. spin_unlock_irqrestore(&priv->lock, flags);
  682. if (priv->statistics.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK) {
  683. R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[1]);
  684. R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[1]);
  685. R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[1]);
  686. } else {
  687. R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[0]);
  688. R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[0]);
  689. R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[0]);
  690. }
  691. temp_th = CELSIUS_TO_KELVIN(TM_CT_KILL_THRESHOLD);
  692. crit_temperature = ((temp_th * (R3-R1))/CT_LIMIT_CONST) + R2;
  693. cmd.critical_temperature_R = cpu_to_le32(crit_temperature);
  694. rc = iwl4965_send_cmd_pdu(priv,
  695. REPLY_CT_KILL_CONFIG_CMD, sizeof(cmd), &cmd);
  696. if (rc)
  697. IWL_ERROR("REPLY_CT_KILL_CONFIG_CMD failed\n");
  698. else
  699. IWL_DEBUG_INFO("REPLY_CT_KILL_CONFIG_CMD succeeded\n");
  700. }
  701. #ifdef CONFIG_IWL4965_SENSITIVITY
  702. /* "false alarms" are signals that our DSP tries to lock onto,
  703. * but then determines that they are either noise, or transmissions
  704. * from a distant wireless network (also "noise", really) that get
  705. * "stepped on" by stronger transmissions within our own network.
  706. * This algorithm attempts to set a sensitivity level that is high
  707. * enough to receive all of our own network traffic, but not so
  708. * high that our DSP gets too busy trying to lock onto non-network
  709. * activity/noise. */
  710. static int iwl4965_sens_energy_cck(struct iwl4965_priv *priv,
  711. u32 norm_fa,
  712. u32 rx_enable_time,
  713. struct statistics_general_data *rx_info)
  714. {
  715. u32 max_nrg_cck = 0;
  716. int i = 0;
  717. u8 max_silence_rssi = 0;
  718. u32 silence_ref = 0;
  719. u8 silence_rssi_a = 0;
  720. u8 silence_rssi_b = 0;
  721. u8 silence_rssi_c = 0;
  722. u32 val;
  723. /* "false_alarms" values below are cross-multiplications to assess the
  724. * numbers of false alarms within the measured period of actual Rx
  725. * (Rx is off when we're txing), vs the min/max expected false alarms
  726. * (some should be expected if rx is sensitive enough) in a
  727. * hypothetical listening period of 200 time units (TU), 204.8 msec:
  728. *
  729. * MIN_FA/fixed-time < false_alarms/actual-rx-time < MAX_FA/beacon-time
  730. *
  731. * */
  732. u32 false_alarms = norm_fa * 200 * 1024;
  733. u32 max_false_alarms = MAX_FA_CCK * rx_enable_time;
  734. u32 min_false_alarms = MIN_FA_CCK * rx_enable_time;
  735. struct iwl4965_sensitivity_data *data = NULL;
  736. data = &(priv->sensitivity_data);
  737. data->nrg_auto_corr_silence_diff = 0;
  738. /* Find max silence rssi among all 3 receivers.
  739. * This is background noise, which may include transmissions from other
  740. * networks, measured during silence before our network's beacon */
  741. silence_rssi_a = (u8)((rx_info->beacon_silence_rssi_a &
  742. ALL_BAND_FILTER) >> 8);
  743. silence_rssi_b = (u8)((rx_info->beacon_silence_rssi_b &
  744. ALL_BAND_FILTER) >> 8);
  745. silence_rssi_c = (u8)((rx_info->beacon_silence_rssi_c &
  746. ALL_BAND_FILTER) >> 8);
  747. val = max(silence_rssi_b, silence_rssi_c);
  748. max_silence_rssi = max(silence_rssi_a, (u8) val);
  749. /* Store silence rssi in 20-beacon history table */
  750. data->nrg_silence_rssi[data->nrg_silence_idx] = max_silence_rssi;
  751. data->nrg_silence_idx++;
  752. if (data->nrg_silence_idx >= NRG_NUM_PREV_STAT_L)
  753. data->nrg_silence_idx = 0;
  754. /* Find max silence rssi across 20 beacon history */
  755. for (i = 0; i < NRG_NUM_PREV_STAT_L; i++) {
  756. val = data->nrg_silence_rssi[i];
  757. silence_ref = max(silence_ref, val);
  758. }
  759. IWL_DEBUG_CALIB("silence a %u, b %u, c %u, 20-bcn max %u\n",
  760. silence_rssi_a, silence_rssi_b, silence_rssi_c,
  761. silence_ref);
  762. /* Find max rx energy (min value!) among all 3 receivers,
  763. * measured during beacon frame.
  764. * Save it in 10-beacon history table. */
  765. i = data->nrg_energy_idx;
  766. val = min(rx_info->beacon_energy_b, rx_info->beacon_energy_c);
  767. data->nrg_value[i] = min(rx_info->beacon_energy_a, val);
  768. data->nrg_energy_idx++;
  769. if (data->nrg_energy_idx >= 10)
  770. data->nrg_energy_idx = 0;
  771. /* Find min rx energy (max value) across 10 beacon history.
  772. * This is the minimum signal level that we want to receive well.
  773. * Add backoff (margin so we don't miss slightly lower energy frames).
  774. * This establishes an upper bound (min value) for energy threshold. */
  775. max_nrg_cck = data->nrg_value[0];
  776. for (i = 1; i < 10; i++)
  777. max_nrg_cck = (u32) max(max_nrg_cck, (data->nrg_value[i]));
  778. max_nrg_cck += 6;
  779. IWL_DEBUG_CALIB("rx energy a %u, b %u, c %u, 10-bcn max/min %u\n",
  780. rx_info->beacon_energy_a, rx_info->beacon_energy_b,
  781. rx_info->beacon_energy_c, max_nrg_cck - 6);
  782. /* Count number of consecutive beacons with fewer-than-desired
  783. * false alarms. */
  784. if (false_alarms < min_false_alarms)
  785. data->num_in_cck_no_fa++;
  786. else
  787. data->num_in_cck_no_fa = 0;
  788. IWL_DEBUG_CALIB("consecutive bcns with few false alarms = %u\n",
  789. data->num_in_cck_no_fa);
  790. /* If we got too many false alarms this time, reduce sensitivity */
  791. if (false_alarms > max_false_alarms) {
  792. IWL_DEBUG_CALIB("norm FA %u > max FA %u\n",
  793. false_alarms, max_false_alarms);
  794. IWL_DEBUG_CALIB("... reducing sensitivity\n");
  795. data->nrg_curr_state = IWL_FA_TOO_MANY;
  796. if (data->auto_corr_cck > AUTO_CORR_MAX_TH_CCK) {
  797. /* Store for "fewer than desired" on later beacon */
  798. data->nrg_silence_ref = silence_ref;
  799. /* increase energy threshold (reduce nrg value)
  800. * to decrease sensitivity */
  801. if (data->nrg_th_cck > (NRG_MAX_CCK + NRG_STEP_CCK))
  802. data->nrg_th_cck = data->nrg_th_cck
  803. - NRG_STEP_CCK;
  804. }
  805. /* increase auto_corr values to decrease sensitivity */
  806. if (data->auto_corr_cck < AUTO_CORR_MAX_TH_CCK)
  807. data->auto_corr_cck = AUTO_CORR_MAX_TH_CCK + 1;
  808. else {
  809. val = data->auto_corr_cck + AUTO_CORR_STEP_CCK;
  810. data->auto_corr_cck = min((u32)AUTO_CORR_MAX_CCK, val);
  811. }
  812. val = data->auto_corr_cck_mrc + AUTO_CORR_STEP_CCK;
  813. data->auto_corr_cck_mrc = min((u32)AUTO_CORR_MAX_CCK_MRC, val);
  814. /* Else if we got fewer than desired, increase sensitivity */
  815. } else if (false_alarms < min_false_alarms) {
  816. data->nrg_curr_state = IWL_FA_TOO_FEW;
  817. /* Compare silence level with silence level for most recent
  818. * healthy number or too many false alarms */
  819. data->nrg_auto_corr_silence_diff = (s32)data->nrg_silence_ref -
  820. (s32)silence_ref;
  821. IWL_DEBUG_CALIB("norm FA %u < min FA %u, silence diff %d\n",
  822. false_alarms, min_false_alarms,
  823. data->nrg_auto_corr_silence_diff);
  824. /* Increase value to increase sensitivity, but only if:
  825. * 1a) previous beacon did *not* have *too many* false alarms
  826. * 1b) AND there's a significant difference in Rx levels
  827. * from a previous beacon with too many, or healthy # FAs
  828. * OR 2) We've seen a lot of beacons (100) with too few
  829. * false alarms */
  830. if ((data->nrg_prev_state != IWL_FA_TOO_MANY) &&
  831. ((data->nrg_auto_corr_silence_diff > NRG_DIFF) ||
  832. (data->num_in_cck_no_fa > MAX_NUMBER_CCK_NO_FA))) {
  833. IWL_DEBUG_CALIB("... increasing sensitivity\n");
  834. /* Increase nrg value to increase sensitivity */
  835. val = data->nrg_th_cck + NRG_STEP_CCK;
  836. data->nrg_th_cck = min((u32)NRG_MIN_CCK, val);
  837. /* Decrease auto_corr values to increase sensitivity */
  838. val = data->auto_corr_cck - AUTO_CORR_STEP_CCK;
  839. data->auto_corr_cck = max((u32)AUTO_CORR_MIN_CCK, val);
  840. val = data->auto_corr_cck_mrc - AUTO_CORR_STEP_CCK;
  841. data->auto_corr_cck_mrc =
  842. max((u32)AUTO_CORR_MIN_CCK_MRC, val);
  843. } else
  844. IWL_DEBUG_CALIB("... but not changing sensitivity\n");
  845. /* Else we got a healthy number of false alarms, keep status quo */
  846. } else {
  847. IWL_DEBUG_CALIB(" FA in safe zone\n");
  848. data->nrg_curr_state = IWL_FA_GOOD_RANGE;
  849. /* Store for use in "fewer than desired" with later beacon */
  850. data->nrg_silence_ref = silence_ref;
  851. /* If previous beacon had too many false alarms,
  852. * give it some extra margin by reducing sensitivity again
  853. * (but don't go below measured energy of desired Rx) */
  854. if (IWL_FA_TOO_MANY == data->nrg_prev_state) {
  855. IWL_DEBUG_CALIB("... increasing margin\n");
  856. data->nrg_th_cck -= NRG_MARGIN;
  857. }
  858. }
  859. /* Make sure the energy threshold does not go above the measured
  860. * energy of the desired Rx signals (reduced by backoff margin),
  861. * or else we might start missing Rx frames.
  862. * Lower value is higher energy, so we use max()!
  863. */
  864. data->nrg_th_cck = max(max_nrg_cck, data->nrg_th_cck);
  865. IWL_DEBUG_CALIB("new nrg_th_cck %u\n", data->nrg_th_cck);
  866. data->nrg_prev_state = data->nrg_curr_state;
  867. return 0;
  868. }
  869. static int iwl4965_sens_auto_corr_ofdm(struct iwl4965_priv *priv,
  870. u32 norm_fa,
  871. u32 rx_enable_time)
  872. {
  873. u32 val;
  874. u32 false_alarms = norm_fa * 200 * 1024;
  875. u32 max_false_alarms = MAX_FA_OFDM * rx_enable_time;
  876. u32 min_false_alarms = MIN_FA_OFDM * rx_enable_time;
  877. struct iwl4965_sensitivity_data *data = NULL;
  878. data = &(priv->sensitivity_data);
  879. /* If we got too many false alarms this time, reduce sensitivity */
  880. if (false_alarms > max_false_alarms) {
  881. IWL_DEBUG_CALIB("norm FA %u > max FA %u)\n",
  882. false_alarms, max_false_alarms);
  883. val = data->auto_corr_ofdm + AUTO_CORR_STEP_OFDM;
  884. data->auto_corr_ofdm =
  885. min((u32)AUTO_CORR_MAX_OFDM, val);
  886. val = data->auto_corr_ofdm_mrc + AUTO_CORR_STEP_OFDM;
  887. data->auto_corr_ofdm_mrc =
  888. min((u32)AUTO_CORR_MAX_OFDM_MRC, val);
  889. val = data->auto_corr_ofdm_x1 + AUTO_CORR_STEP_OFDM;
  890. data->auto_corr_ofdm_x1 =
  891. min((u32)AUTO_CORR_MAX_OFDM_X1, val);
  892. val = data->auto_corr_ofdm_mrc_x1 + AUTO_CORR_STEP_OFDM;
  893. data->auto_corr_ofdm_mrc_x1 =
  894. min((u32)AUTO_CORR_MAX_OFDM_MRC_X1, val);
  895. }
  896. /* Else if we got fewer than desired, increase sensitivity */
  897. else if (false_alarms < min_false_alarms) {
  898. IWL_DEBUG_CALIB("norm FA %u < min FA %u\n",
  899. false_alarms, min_false_alarms);
  900. val = data->auto_corr_ofdm - AUTO_CORR_STEP_OFDM;
  901. data->auto_corr_ofdm =
  902. max((u32)AUTO_CORR_MIN_OFDM, val);
  903. val = data->auto_corr_ofdm_mrc - AUTO_CORR_STEP_OFDM;
  904. data->auto_corr_ofdm_mrc =
  905. max((u32)AUTO_CORR_MIN_OFDM_MRC, val);
  906. val = data->auto_corr_ofdm_x1 - AUTO_CORR_STEP_OFDM;
  907. data->auto_corr_ofdm_x1 =
  908. max((u32)AUTO_CORR_MIN_OFDM_X1, val);
  909. val = data->auto_corr_ofdm_mrc_x1 - AUTO_CORR_STEP_OFDM;
  910. data->auto_corr_ofdm_mrc_x1 =
  911. max((u32)AUTO_CORR_MIN_OFDM_MRC_X1, val);
  912. }
  913. else
  914. IWL_DEBUG_CALIB("min FA %u < norm FA %u < max FA %u OK\n",
  915. min_false_alarms, false_alarms, max_false_alarms);
  916. return 0;
  917. }
  918. static int iwl4965_sensitivity_callback(struct iwl4965_priv *priv,
  919. struct iwl4965_cmd *cmd, struct sk_buff *skb)
  920. {
  921. /* We didn't cache the SKB; let the caller free it */
  922. return 1;
  923. }
  924. /* Prepare a SENSITIVITY_CMD, send to uCode if values have changed */
  925. static int iwl4965_sensitivity_write(struct iwl4965_priv *priv, u8 flags)
  926. {
  927. int rc = 0;
  928. struct iwl4965_sensitivity_cmd cmd ;
  929. struct iwl4965_sensitivity_data *data = NULL;
  930. struct iwl4965_host_cmd cmd_out = {
  931. .id = SENSITIVITY_CMD,
  932. .len = sizeof(struct iwl4965_sensitivity_cmd),
  933. .meta.flags = flags,
  934. .data = &cmd,
  935. };
  936. data = &(priv->sensitivity_data);
  937. memset(&cmd, 0, sizeof(cmd));
  938. cmd.table[HD_AUTO_CORR32_X4_TH_ADD_MIN_INDEX] =
  939. cpu_to_le16((u16)data->auto_corr_ofdm);
  940. cmd.table[HD_AUTO_CORR32_X4_TH_ADD_MIN_MRC_INDEX] =
  941. cpu_to_le16((u16)data->auto_corr_ofdm_mrc);
  942. cmd.table[HD_AUTO_CORR32_X1_TH_ADD_MIN_INDEX] =
  943. cpu_to_le16((u16)data->auto_corr_ofdm_x1);
  944. cmd.table[HD_AUTO_CORR32_X1_TH_ADD_MIN_MRC_INDEX] =
  945. cpu_to_le16((u16)data->auto_corr_ofdm_mrc_x1);
  946. cmd.table[HD_AUTO_CORR40_X4_TH_ADD_MIN_INDEX] =
  947. cpu_to_le16((u16)data->auto_corr_cck);
  948. cmd.table[HD_AUTO_CORR40_X4_TH_ADD_MIN_MRC_INDEX] =
  949. cpu_to_le16((u16)data->auto_corr_cck_mrc);
  950. cmd.table[HD_MIN_ENERGY_CCK_DET_INDEX] =
  951. cpu_to_le16((u16)data->nrg_th_cck);
  952. cmd.table[HD_MIN_ENERGY_OFDM_DET_INDEX] =
  953. cpu_to_le16((u16)data->nrg_th_ofdm);
  954. cmd.table[HD_BARKER_CORR_TH_ADD_MIN_INDEX] =
  955. __constant_cpu_to_le16(190);
  956. cmd.table[HD_BARKER_CORR_TH_ADD_MIN_MRC_INDEX] =
  957. __constant_cpu_to_le16(390);
  958. cmd.table[HD_OFDM_ENERGY_TH_IN_INDEX] =
  959. __constant_cpu_to_le16(62);
  960. IWL_DEBUG_CALIB("ofdm: ac %u mrc %u x1 %u mrc_x1 %u thresh %u\n",
  961. data->auto_corr_ofdm, data->auto_corr_ofdm_mrc,
  962. data->auto_corr_ofdm_x1, data->auto_corr_ofdm_mrc_x1,
  963. data->nrg_th_ofdm);
  964. IWL_DEBUG_CALIB("cck: ac %u mrc %u thresh %u\n",
  965. data->auto_corr_cck, data->auto_corr_cck_mrc,
  966. data->nrg_th_cck);
  967. /* Update uCode's "work" table, and copy it to DSP */
  968. cmd.control = SENSITIVITY_CMD_CONTROL_WORK_TABLE;
  969. if (flags & CMD_ASYNC)
  970. cmd_out.meta.u.callback = iwl4965_sensitivity_callback;
  971. /* Don't send command to uCode if nothing has changed */
  972. if (!memcmp(&cmd.table[0], &(priv->sensitivity_tbl[0]),
  973. sizeof(u16)*HD_TABLE_SIZE)) {
  974. IWL_DEBUG_CALIB("No change in SENSITIVITY_CMD\n");
  975. return 0;
  976. }
  977. /* Copy table for comparison next time */
  978. memcpy(&(priv->sensitivity_tbl[0]), &(cmd.table[0]),
  979. sizeof(u16)*HD_TABLE_SIZE);
  980. rc = iwl4965_send_cmd(priv, &cmd_out);
  981. if (!rc) {
  982. IWL_DEBUG_CALIB("SENSITIVITY_CMD succeeded\n");
  983. return rc;
  984. }
  985. return 0;
  986. }
  987. void iwl4965_init_sensitivity(struct iwl4965_priv *priv, u8 flags, u8 force)
  988. {
  989. int rc = 0;
  990. int i;
  991. struct iwl4965_sensitivity_data *data = NULL;
  992. IWL_DEBUG_CALIB("Start iwl4965_init_sensitivity\n");
  993. if (force)
  994. memset(&(priv->sensitivity_tbl[0]), 0,
  995. sizeof(u16)*HD_TABLE_SIZE);
  996. /* Clear driver's sensitivity algo data */
  997. data = &(priv->sensitivity_data);
  998. memset(data, 0, sizeof(struct iwl4965_sensitivity_data));
  999. data->num_in_cck_no_fa = 0;
  1000. data->nrg_curr_state = IWL_FA_TOO_MANY;
  1001. data->nrg_prev_state = IWL_FA_TOO_MANY;
  1002. data->nrg_silence_ref = 0;
  1003. data->nrg_silence_idx = 0;
  1004. data->nrg_energy_idx = 0;
  1005. for (i = 0; i < 10; i++)
  1006. data->nrg_value[i] = 0;
  1007. for (i = 0; i < NRG_NUM_PREV_STAT_L; i++)
  1008. data->nrg_silence_rssi[i] = 0;
  1009. data->auto_corr_ofdm = 90;
  1010. data->auto_corr_ofdm_mrc = 170;
  1011. data->auto_corr_ofdm_x1 = 105;
  1012. data->auto_corr_ofdm_mrc_x1 = 220;
  1013. data->auto_corr_cck = AUTO_CORR_CCK_MIN_VAL_DEF;
  1014. data->auto_corr_cck_mrc = 200;
  1015. data->nrg_th_cck = 100;
  1016. data->nrg_th_ofdm = 100;
  1017. data->last_bad_plcp_cnt_ofdm = 0;
  1018. data->last_fa_cnt_ofdm = 0;
  1019. data->last_bad_plcp_cnt_cck = 0;
  1020. data->last_fa_cnt_cck = 0;
  1021. /* Clear prior Sensitivity command data to force send to uCode */
  1022. if (force)
  1023. memset(&(priv->sensitivity_tbl[0]), 0,
  1024. sizeof(u16)*HD_TABLE_SIZE);
  1025. rc |= iwl4965_sensitivity_write(priv, flags);
  1026. IWL_DEBUG_CALIB("<<return 0x%X\n", rc);
  1027. return;
  1028. }
  1029. /* Reset differential Rx gains in NIC to prepare for chain noise calibration.
  1030. * Called after every association, but this runs only once!
  1031. * ... once chain noise is calibrated the first time, it's good forever. */
  1032. void iwl4965_chain_noise_reset(struct iwl4965_priv *priv)
  1033. {
  1034. struct iwl4965_chain_noise_data *data = NULL;
  1035. int rc = 0;
  1036. data = &(priv->chain_noise_data);
  1037. if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl4965_is_associated(priv)) {
  1038. struct iwl4965_calibration_cmd cmd;
  1039. memset(&cmd, 0, sizeof(cmd));
  1040. cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
  1041. cmd.diff_gain_a = 0;
  1042. cmd.diff_gain_b = 0;
  1043. cmd.diff_gain_c = 0;
  1044. rc = iwl4965_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
  1045. sizeof(cmd), &cmd);
  1046. msleep(4);
  1047. data->state = IWL_CHAIN_NOISE_ACCUMULATE;
  1048. IWL_DEBUG_CALIB("Run chain_noise_calibrate\n");
  1049. }
  1050. return;
  1051. }
  1052. /*
  1053. * Accumulate 20 beacons of signal and noise statistics for each of
  1054. * 3 receivers/antennas/rx-chains, then figure out:
  1055. * 1) Which antennas are connected.
  1056. * 2) Differential rx gain settings to balance the 3 receivers.
  1057. */
  1058. static void iwl4965_noise_calibration(struct iwl4965_priv *priv,
  1059. struct iwl4965_notif_statistics *stat_resp)
  1060. {
  1061. struct iwl4965_chain_noise_data *data = NULL;
  1062. int rc = 0;
  1063. u32 chain_noise_a;
  1064. u32 chain_noise_b;
  1065. u32 chain_noise_c;
  1066. u32 chain_sig_a;
  1067. u32 chain_sig_b;
  1068. u32 chain_sig_c;
  1069. u32 average_sig[NUM_RX_CHAINS] = {INITIALIZATION_VALUE};
  1070. u32 average_noise[NUM_RX_CHAINS] = {INITIALIZATION_VALUE};
  1071. u32 max_average_sig;
  1072. u16 max_average_sig_antenna_i;
  1073. u32 min_average_noise = MIN_AVERAGE_NOISE_MAX_VALUE;
  1074. u16 min_average_noise_antenna_i = INITIALIZATION_VALUE;
  1075. u16 i = 0;
  1076. u16 chan_num = INITIALIZATION_VALUE;
  1077. u32 band = INITIALIZATION_VALUE;
  1078. u32 active_chains = 0;
  1079. unsigned long flags;
  1080. struct statistics_rx_non_phy *rx_info = &(stat_resp->rx.general);
  1081. data = &(priv->chain_noise_data);
  1082. /* Accumulate just the first 20 beacons after the first association,
  1083. * then we're done forever. */
  1084. if (data->state != IWL_CHAIN_NOISE_ACCUMULATE) {
  1085. if (data->state == IWL_CHAIN_NOISE_ALIVE)
  1086. IWL_DEBUG_CALIB("Wait for noise calib reset\n");
  1087. return;
  1088. }
  1089. spin_lock_irqsave(&priv->lock, flags);
  1090. if (rx_info->interference_data_flag != INTERFERENCE_DATA_AVAILABLE) {
  1091. IWL_DEBUG_CALIB(" << Interference data unavailable\n");
  1092. spin_unlock_irqrestore(&priv->lock, flags);
  1093. return;
  1094. }
  1095. band = (priv->staging_rxon.flags & RXON_FLG_BAND_24G_MSK) ? 0 : 1;
  1096. chan_num = le16_to_cpu(priv->staging_rxon.channel);
  1097. /* Make sure we accumulate data for just the associated channel
  1098. * (even if scanning). */
  1099. if ((chan_num != (le32_to_cpu(stat_resp->flag) >> 16)) ||
  1100. ((STATISTICS_REPLY_FLG_BAND_24G_MSK ==
  1101. (stat_resp->flag & STATISTICS_REPLY_FLG_BAND_24G_MSK)) && band)) {
  1102. IWL_DEBUG_CALIB("Stats not from chan=%d, band=%d\n",
  1103. chan_num, band);
  1104. spin_unlock_irqrestore(&priv->lock, flags);
  1105. return;
  1106. }
  1107. /* Accumulate beacon statistics values across 20 beacons */
  1108. chain_noise_a = le32_to_cpu(rx_info->beacon_silence_rssi_a) &
  1109. IN_BAND_FILTER;
  1110. chain_noise_b = le32_to_cpu(rx_info->beacon_silence_rssi_b) &
  1111. IN_BAND_FILTER;
  1112. chain_noise_c = le32_to_cpu(rx_info->beacon_silence_rssi_c) &
  1113. IN_BAND_FILTER;
  1114. chain_sig_a = le32_to_cpu(rx_info->beacon_rssi_a) & IN_BAND_FILTER;
  1115. chain_sig_b = le32_to_cpu(rx_info->beacon_rssi_b) & IN_BAND_FILTER;
  1116. chain_sig_c = le32_to_cpu(rx_info->beacon_rssi_c) & IN_BAND_FILTER;
  1117. spin_unlock_irqrestore(&priv->lock, flags);
  1118. data->beacon_count++;
  1119. data->chain_noise_a = (chain_noise_a + data->chain_noise_a);
  1120. data->chain_noise_b = (chain_noise_b + data->chain_noise_b);
  1121. data->chain_noise_c = (chain_noise_c + data->chain_noise_c);
  1122. data->chain_signal_a = (chain_sig_a + data->chain_signal_a);
  1123. data->chain_signal_b = (chain_sig_b + data->chain_signal_b);
  1124. data->chain_signal_c = (chain_sig_c + data->chain_signal_c);
  1125. IWL_DEBUG_CALIB("chan=%d, band=%d, beacon=%d\n", chan_num, band,
  1126. data->beacon_count);
  1127. IWL_DEBUG_CALIB("chain_sig: a %d b %d c %d\n",
  1128. chain_sig_a, chain_sig_b, chain_sig_c);
  1129. IWL_DEBUG_CALIB("chain_noise: a %d b %d c %d\n",
  1130. chain_noise_a, chain_noise_b, chain_noise_c);
  1131. /* If this is the 20th beacon, determine:
  1132. * 1) Disconnected antennas (using signal strengths)
  1133. * 2) Differential gain (using silence noise) to balance receivers */
  1134. if (data->beacon_count == CAL_NUM_OF_BEACONS) {
  1135. /* Analyze signal for disconnected antenna */
  1136. average_sig[0] = (data->chain_signal_a) / CAL_NUM_OF_BEACONS;
  1137. average_sig[1] = (data->chain_signal_b) / CAL_NUM_OF_BEACONS;
  1138. average_sig[2] = (data->chain_signal_c) / CAL_NUM_OF_BEACONS;
  1139. if (average_sig[0] >= average_sig[1]) {
  1140. max_average_sig = average_sig[0];
  1141. max_average_sig_antenna_i = 0;
  1142. active_chains = (1 << max_average_sig_antenna_i);
  1143. } else {
  1144. max_average_sig = average_sig[1];
  1145. max_average_sig_antenna_i = 1;
  1146. active_chains = (1 << max_average_sig_antenna_i);
  1147. }
  1148. if (average_sig[2] >= max_average_sig) {
  1149. max_average_sig = average_sig[2];
  1150. max_average_sig_antenna_i = 2;
  1151. active_chains = (1 << max_average_sig_antenna_i);
  1152. }
  1153. IWL_DEBUG_CALIB("average_sig: a %d b %d c %d\n",
  1154. average_sig[0], average_sig[1], average_sig[2]);
  1155. IWL_DEBUG_CALIB("max_average_sig = %d, antenna %d\n",
  1156. max_average_sig, max_average_sig_antenna_i);
  1157. /* Compare signal strengths for all 3 receivers. */
  1158. for (i = 0; i < NUM_RX_CHAINS; i++) {
  1159. if (i != max_average_sig_antenna_i) {
  1160. s32 rssi_delta = (max_average_sig -
  1161. average_sig[i]);
  1162. /* If signal is very weak, compared with
  1163. * strongest, mark it as disconnected. */
  1164. if (rssi_delta > MAXIMUM_ALLOWED_PATHLOSS)
  1165. data->disconn_array[i] = 1;
  1166. else
  1167. active_chains |= (1 << i);
  1168. IWL_DEBUG_CALIB("i = %d rssiDelta = %d "
  1169. "disconn_array[i] = %d\n",
  1170. i, rssi_delta, data->disconn_array[i]);
  1171. }
  1172. }
  1173. /*If both chains A & B are disconnected -
  1174. * connect B and leave A as is */
  1175. if (data->disconn_array[CHAIN_A] &&
  1176. data->disconn_array[CHAIN_B]) {
  1177. data->disconn_array[CHAIN_B] = 0;
  1178. active_chains |= (1 << CHAIN_B);
  1179. IWL_DEBUG_CALIB("both A & B chains are disconnected! "
  1180. "W/A - declare B as connected\n");
  1181. }
  1182. IWL_DEBUG_CALIB("active_chains (bitwise) = 0x%x\n",
  1183. active_chains);
  1184. /* Save for use within RXON, TX, SCAN commands, etc. */
  1185. priv->valid_antenna = active_chains;
  1186. /* Analyze noise for rx balance */
  1187. average_noise[0] = ((data->chain_noise_a)/CAL_NUM_OF_BEACONS);
  1188. average_noise[1] = ((data->chain_noise_b)/CAL_NUM_OF_BEACONS);
  1189. average_noise[2] = ((data->chain_noise_c)/CAL_NUM_OF_BEACONS);
  1190. for (i = 0; i < NUM_RX_CHAINS; i++) {
  1191. if (!(data->disconn_array[i]) &&
  1192. (average_noise[i] <= min_average_noise)) {
  1193. /* This means that chain i is active and has
  1194. * lower noise values so far: */
  1195. min_average_noise = average_noise[i];
  1196. min_average_noise_antenna_i = i;
  1197. }
  1198. }
  1199. data->delta_gain_code[min_average_noise_antenna_i] = 0;
  1200. IWL_DEBUG_CALIB("average_noise: a %d b %d c %d\n",
  1201. average_noise[0], average_noise[1],
  1202. average_noise[2]);
  1203. IWL_DEBUG_CALIB("min_average_noise = %d, antenna %d\n",
  1204. min_average_noise, min_average_noise_antenna_i);
  1205. for (i = 0; i < NUM_RX_CHAINS; i++) {
  1206. s32 delta_g = 0;
  1207. if (!(data->disconn_array[i]) &&
  1208. (data->delta_gain_code[i] ==
  1209. CHAIN_NOISE_DELTA_GAIN_INIT_VAL)) {
  1210. delta_g = average_noise[i] - min_average_noise;
  1211. data->delta_gain_code[i] = (u8)((delta_g *
  1212. 10) / 15);
  1213. if (CHAIN_NOISE_MAX_DELTA_GAIN_CODE <
  1214. data->delta_gain_code[i])
  1215. data->delta_gain_code[i] =
  1216. CHAIN_NOISE_MAX_DELTA_GAIN_CODE;
  1217. data->delta_gain_code[i] =
  1218. (data->delta_gain_code[i] | (1 << 2));
  1219. } else
  1220. data->delta_gain_code[i] = 0;
  1221. }
  1222. IWL_DEBUG_CALIB("delta_gain_codes: a %d b %d c %d\n",
  1223. data->delta_gain_code[0],
  1224. data->delta_gain_code[1],
  1225. data->delta_gain_code[2]);
  1226. /* Differential gain gets sent to uCode only once */
  1227. if (!data->radio_write) {
  1228. struct iwl4965_calibration_cmd cmd;
  1229. data->radio_write = 1;
  1230. memset(&cmd, 0, sizeof(cmd));
  1231. cmd.opCode = PHY_CALIBRATE_DIFF_GAIN_CMD;
  1232. cmd.diff_gain_a = data->delta_gain_code[0];
  1233. cmd.diff_gain_b = data->delta_gain_code[1];
  1234. cmd.diff_gain_c = data->delta_gain_code[2];
  1235. rc = iwl4965_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
  1236. sizeof(cmd), &cmd);
  1237. if (rc)
  1238. IWL_DEBUG_CALIB("fail sending cmd "
  1239. "REPLY_PHY_CALIBRATION_CMD \n");
  1240. /* TODO we might want recalculate
  1241. * rx_chain in rxon cmd */
  1242. /* Mark so we run this algo only once! */
  1243. data->state = IWL_CHAIN_NOISE_CALIBRATED;
  1244. }
  1245. data->chain_noise_a = 0;
  1246. data->chain_noise_b = 0;
  1247. data->chain_noise_c = 0;
  1248. data->chain_signal_a = 0;
  1249. data->chain_signal_b = 0;
  1250. data->chain_signal_c = 0;
  1251. data->beacon_count = 0;
  1252. }
  1253. return;
  1254. }
  1255. static void iwl4965_sensitivity_calibration(struct iwl4965_priv *priv,
  1256. struct iwl4965_notif_statistics *resp)
  1257. {
  1258. int rc = 0;
  1259. u32 rx_enable_time;
  1260. u32 fa_cck;
  1261. u32 fa_ofdm;
  1262. u32 bad_plcp_cck;
  1263. u32 bad_plcp_ofdm;
  1264. u32 norm_fa_ofdm;
  1265. u32 norm_fa_cck;
  1266. struct iwl4965_sensitivity_data *data = NULL;
  1267. struct statistics_rx_non_phy *rx_info = &(resp->rx.general);
  1268. struct statistics_rx *statistics = &(resp->rx);
  1269. unsigned long flags;
  1270. struct statistics_general_data statis;
  1271. data = &(priv->sensitivity_data);
  1272. if (!iwl4965_is_associated(priv)) {
  1273. IWL_DEBUG_CALIB("<< - not associated\n");
  1274. return;
  1275. }
  1276. spin_lock_irqsave(&priv->lock, flags);
  1277. if (rx_info->interference_data_flag != INTERFERENCE_DATA_AVAILABLE) {
  1278. IWL_DEBUG_CALIB("<< invalid data.\n");
  1279. spin_unlock_irqrestore(&priv->lock, flags);
  1280. return;
  1281. }
  1282. /* Extract Statistics: */
  1283. rx_enable_time = le32_to_cpu(rx_info->channel_load);
  1284. fa_cck = le32_to_cpu(statistics->cck.false_alarm_cnt);
  1285. fa_ofdm = le32_to_cpu(statistics->ofdm.false_alarm_cnt);
  1286. bad_plcp_cck = le32_to_cpu(statistics->cck.plcp_err);
  1287. bad_plcp_ofdm = le32_to_cpu(statistics->ofdm.plcp_err);
  1288. statis.beacon_silence_rssi_a =
  1289. le32_to_cpu(statistics->general.beacon_silence_rssi_a);
  1290. statis.beacon_silence_rssi_b =
  1291. le32_to_cpu(statistics->general.beacon_silence_rssi_b);
  1292. statis.beacon_silence_rssi_c =
  1293. le32_to_cpu(statistics->general.beacon_silence_rssi_c);
  1294. statis.beacon_energy_a =
  1295. le32_to_cpu(statistics->general.beacon_energy_a);
  1296. statis.beacon_energy_b =
  1297. le32_to_cpu(statistics->general.beacon_energy_b);
  1298. statis.beacon_energy_c =
  1299. le32_to_cpu(statistics->general.beacon_energy_c);
  1300. spin_unlock_irqrestore(&priv->lock, flags);
  1301. IWL_DEBUG_CALIB("rx_enable_time = %u usecs\n", rx_enable_time);
  1302. if (!rx_enable_time) {
  1303. IWL_DEBUG_CALIB("<< RX Enable Time == 0! \n");
  1304. return;
  1305. }
  1306. /* These statistics increase monotonically, and do not reset
  1307. * at each beacon. Calculate difference from last value, or just
  1308. * use the new statistics value if it has reset or wrapped around. */
  1309. if (data->last_bad_plcp_cnt_cck > bad_plcp_cck)
  1310. data->last_bad_plcp_cnt_cck = bad_plcp_cck;
  1311. else {
  1312. bad_plcp_cck -= data->last_bad_plcp_cnt_cck;
  1313. data->last_bad_plcp_cnt_cck += bad_plcp_cck;
  1314. }
  1315. if (data->last_bad_plcp_cnt_ofdm > bad_plcp_ofdm)
  1316. data->last_bad_plcp_cnt_ofdm = bad_plcp_ofdm;
  1317. else {
  1318. bad_plcp_ofdm -= data->last_bad_plcp_cnt_ofdm;
  1319. data->last_bad_plcp_cnt_ofdm += bad_plcp_ofdm;
  1320. }
  1321. if (data->last_fa_cnt_ofdm > fa_ofdm)
  1322. data->last_fa_cnt_ofdm = fa_ofdm;
  1323. else {
  1324. fa_ofdm -= data->last_fa_cnt_ofdm;
  1325. data->last_fa_cnt_ofdm += fa_ofdm;
  1326. }
  1327. if (data->last_fa_cnt_cck > fa_cck)
  1328. data->last_fa_cnt_cck = fa_cck;
  1329. else {
  1330. fa_cck -= data->last_fa_cnt_cck;
  1331. data->last_fa_cnt_cck += fa_cck;
  1332. }
  1333. /* Total aborted signal locks */
  1334. norm_fa_ofdm = fa_ofdm + bad_plcp_ofdm;
  1335. norm_fa_cck = fa_cck + bad_plcp_cck;
  1336. IWL_DEBUG_CALIB("cck: fa %u badp %u ofdm: fa %u badp %u\n", fa_cck,
  1337. bad_plcp_cck, fa_ofdm, bad_plcp_ofdm);
  1338. iwl4965_sens_auto_corr_ofdm(priv, norm_fa_ofdm, rx_enable_time);
  1339. iwl4965_sens_energy_cck(priv, norm_fa_cck, rx_enable_time, &statis);
  1340. rc |= iwl4965_sensitivity_write(priv, CMD_ASYNC);
  1341. return;
  1342. }
  1343. static void iwl4965_bg_sensitivity_work(struct work_struct *work)
  1344. {
  1345. struct iwl4965_priv *priv = container_of(work, struct iwl4965_priv,
  1346. sensitivity_work);
  1347. mutex_lock(&priv->mutex);
  1348. if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
  1349. test_bit(STATUS_SCANNING, &priv->status)) {
  1350. mutex_unlock(&priv->mutex);
  1351. return;
  1352. }
  1353. if (priv->start_calib) {
  1354. iwl4965_noise_calibration(priv, &priv->statistics);
  1355. if (priv->sensitivity_data.state ==
  1356. IWL_SENS_CALIB_NEED_REINIT) {
  1357. iwl4965_init_sensitivity(priv, CMD_ASYNC, 0);
  1358. priv->sensitivity_data.state = IWL_SENS_CALIB_ALLOWED;
  1359. } else
  1360. iwl4965_sensitivity_calibration(priv,
  1361. &priv->statistics);
  1362. }
  1363. mutex_unlock(&priv->mutex);
  1364. return;
  1365. }
  1366. #endif /*CONFIG_IWL4965_SENSITIVITY*/
  1367. static void iwl4965_bg_txpower_work(struct work_struct *work)
  1368. {
  1369. struct iwl4965_priv *priv = container_of(work, struct iwl4965_priv,
  1370. txpower_work);
  1371. /* If a scan happened to start before we got here
  1372. * then just return; the statistics notification will
  1373. * kick off another scheduled work to compensate for
  1374. * any temperature delta we missed here. */
  1375. if (test_bit(STATUS_EXIT_PENDING, &priv->status) ||
  1376. test_bit(STATUS_SCANNING, &priv->status))
  1377. return;
  1378. mutex_lock(&priv->mutex);
  1379. /* Regardless of if we are assocaited, we must reconfigure the
  1380. * TX power since frames can be sent on non-radar channels while
  1381. * not associated */
  1382. iwl4965_hw_reg_send_txpower(priv);
  1383. /* Update last_temperature to keep is_calib_needed from running
  1384. * when it isn't needed... */
  1385. priv->last_temperature = priv->temperature;
  1386. mutex_unlock(&priv->mutex);
  1387. }
  1388. /*
  1389. * Acquire priv->lock before calling this function !
  1390. */
  1391. static void iwl4965_set_wr_ptrs(struct iwl4965_priv *priv, int txq_id, u32 index)
  1392. {
  1393. iwl4965_write_direct32(priv, HBUS_TARG_WRPTR,
  1394. (index & 0xff) | (txq_id << 8));
  1395. iwl4965_write_prph(priv, KDR_SCD_QUEUE_RDPTR(txq_id), index);
  1396. }
  1397. /**
  1398. * iwl4965_tx_queue_set_status - (optionally) start Tx/Cmd queue
  1399. * @tx_fifo_id: Tx DMA/FIFO channel (range 0-7) that the queue will feed
  1400. * @scd_retry: (1) Indicates queue will be used in aggregation mode
  1401. *
  1402. * NOTE: Acquire priv->lock before calling this function !
  1403. */
  1404. static void iwl4965_tx_queue_set_status(struct iwl4965_priv *priv,
  1405. struct iwl4965_tx_queue *txq,
  1406. int tx_fifo_id, int scd_retry)
  1407. {
  1408. int txq_id = txq->q.id;
  1409. /* Find out whether to activate Tx queue */
  1410. int active = test_bit(txq_id, &priv->txq_ctx_active_msk)?1:0;
  1411. /* Set up and activate */
  1412. iwl4965_write_prph(priv, KDR_SCD_QUEUE_STATUS_BITS(txq_id),
  1413. (active << SCD_QUEUE_STTS_REG_POS_ACTIVE) |
  1414. (tx_fifo_id << SCD_QUEUE_STTS_REG_POS_TXF) |
  1415. (scd_retry << SCD_QUEUE_STTS_REG_POS_WSL) |
  1416. (scd_retry << SCD_QUEUE_STTS_REG_POS_SCD_ACK) |
  1417. SCD_QUEUE_STTS_REG_MSK);
  1418. txq->sched_retry = scd_retry;
  1419. IWL_DEBUG_INFO("%s %s Queue %d on AC %d\n",
  1420. active ? "Activate" : "Deactivate",
  1421. scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
  1422. }
  1423. static const u16 default_queue_to_tx_fifo[] = {
  1424. IWL_TX_FIFO_AC3,
  1425. IWL_TX_FIFO_AC2,
  1426. IWL_TX_FIFO_AC1,
  1427. IWL_TX_FIFO_AC0,
  1428. IWL_CMD_FIFO_NUM,
  1429. IWL_TX_FIFO_HCCA_1,
  1430. IWL_TX_FIFO_HCCA_2
  1431. };
  1432. static inline void iwl4965_txq_ctx_activate(struct iwl4965_priv *priv, int txq_id)
  1433. {
  1434. set_bit(txq_id, &priv->txq_ctx_active_msk);
  1435. }
  1436. static inline void iwl4965_txq_ctx_deactivate(struct iwl4965_priv *priv, int txq_id)
  1437. {
  1438. clear_bit(txq_id, &priv->txq_ctx_active_msk);
  1439. }
  1440. int iwl4965_alive_notify(struct iwl4965_priv *priv)
  1441. {
  1442. u32 a;
  1443. int i = 0;
  1444. unsigned long flags;
  1445. int rc;
  1446. spin_lock_irqsave(&priv->lock, flags);
  1447. #ifdef CONFIG_IWL4965_SENSITIVITY
  1448. memset(&(priv->sensitivity_data), 0,
  1449. sizeof(struct iwl4965_sensitivity_data));
  1450. memset(&(priv->chain_noise_data), 0,
  1451. sizeof(struct iwl4965_chain_noise_data));
  1452. for (i = 0; i < NUM_RX_CHAINS; i++)
  1453. priv->chain_noise_data.delta_gain_code[i] =
  1454. CHAIN_NOISE_DELTA_GAIN_INIT_VAL;
  1455. #endif /* CONFIG_IWL4965_SENSITIVITY*/
  1456. rc = iwl4965_grab_nic_access(priv);
  1457. if (rc) {
  1458. spin_unlock_irqrestore(&priv->lock, flags);
  1459. return rc;
  1460. }
  1461. /* Clear 4965's internal Tx Scheduler data base */
  1462. priv->scd_base_addr = iwl4965_read_prph(priv, KDR_SCD_SRAM_BASE_ADDR);
  1463. a = priv->scd_base_addr + SCD_CONTEXT_DATA_OFFSET;
  1464. for (; a < priv->scd_base_addr + SCD_TX_STTS_BITMAP_OFFSET; a += 4)
  1465. iwl4965_write_targ_mem(priv, a, 0);
  1466. for (; a < priv->scd_base_addr + SCD_TRANSLATE_TBL_OFFSET; a += 4)
  1467. iwl4965_write_targ_mem(priv, a, 0);
  1468. for (; a < sizeof(u16) * priv->hw_setting.max_txq_num; a += 4)
  1469. iwl4965_write_targ_mem(priv, a, 0);
  1470. /* Tel 4965 where to find Tx byte count tables */
  1471. iwl4965_write_prph(priv, KDR_SCD_DRAM_BASE_ADDR,
  1472. (priv->hw_setting.shared_phys +
  1473. offsetof(struct iwl4965_shared, queues_byte_cnt_tbls)) >> 10);
  1474. /* Disable chain mode for all queues */
  1475. iwl4965_write_prph(priv, KDR_SCD_QUEUECHAIN_SEL, 0);
  1476. /* Initialize each Tx queue (including the command queue) */
  1477. for (i = 0; i < priv->hw_setting.max_txq_num; i++) {
  1478. /* TFD circular buffer read/write indexes */
  1479. iwl4965_write_prph(priv, KDR_SCD_QUEUE_RDPTR(i), 0);
  1480. iwl4965_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
  1481. /* Max Tx Window size for Scheduler-ACK mode */
  1482. iwl4965_write_targ_mem(priv, priv->scd_base_addr +
  1483. SCD_CONTEXT_QUEUE_OFFSET(i),
  1484. (SCD_WIN_SIZE <<
  1485. SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
  1486. SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
  1487. /* Frame limit */
  1488. iwl4965_write_targ_mem(priv, priv->scd_base_addr +
  1489. SCD_CONTEXT_QUEUE_OFFSET(i) +
  1490. sizeof(u32),
  1491. (SCD_FRAME_LIMIT <<
  1492. SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
  1493. SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
  1494. }
  1495. iwl4965_write_prph(priv, KDR_SCD_INTERRUPT_MASK,
  1496. (1 << priv->hw_setting.max_txq_num) - 1);
  1497. /* Activate all Tx DMA/FIFO channels */
  1498. iwl4965_write_prph(priv, KDR_SCD_TXFACT,
  1499. SCD_TXFACT_REG_TXFIFO_MASK(0, 7));
  1500. iwl4965_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
  1501. /* Map each Tx/cmd queue to its corresponding fifo */
  1502. for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) {
  1503. int ac = default_queue_to_tx_fifo[i];
  1504. iwl4965_txq_ctx_activate(priv, i);
  1505. iwl4965_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
  1506. }
  1507. iwl4965_release_nic_access(priv);
  1508. spin_unlock_irqrestore(&priv->lock, flags);
  1509. return 0;
  1510. }
  1511. /**
  1512. * iwl4965_hw_set_hw_setting
  1513. *
  1514. * Called when initializing driver
  1515. */
  1516. int iwl4965_hw_set_hw_setting(struct iwl4965_priv *priv)
  1517. {
  1518. /* Allocate area for Tx byte count tables and Rx queue status */
  1519. priv->hw_setting.shared_virt =
  1520. pci_alloc_consistent(priv->pci_dev,
  1521. sizeof(struct iwl4965_shared),
  1522. &priv->hw_setting.shared_phys);
  1523. if (!priv->hw_setting.shared_virt)
  1524. return -1;
  1525. memset(priv->hw_setting.shared_virt, 0, sizeof(struct iwl4965_shared));
  1526. priv->hw_setting.max_txq_num = iwl4965_param_queues_num;
  1527. priv->hw_setting.tx_cmd_len = sizeof(struct iwl4965_tx_cmd);
  1528. priv->hw_setting.max_rxq_size = RX_QUEUE_SIZE;
  1529. priv->hw_setting.max_rxq_log = RX_QUEUE_SIZE_LOG;
  1530. if (iwl4965_param_amsdu_size_8K)
  1531. priv->hw_setting.rx_buf_size = IWL_RX_BUF_SIZE_8K;
  1532. else
  1533. priv->hw_setting.rx_buf_size = IWL_RX_BUF_SIZE_4K;
  1534. priv->hw_setting.max_pkt_size = priv->hw_setting.rx_buf_size - 256;
  1535. priv->hw_setting.max_stations = IWL4965_STATION_COUNT;
  1536. priv->hw_setting.bcast_sta_id = IWL4965_BROADCAST_ID;
  1537. priv->hw_setting.tx_ant_num = 2;
  1538. return 0;
  1539. }
  1540. /**
  1541. * iwl4965_hw_txq_ctx_free - Free TXQ Context
  1542. *
  1543. * Destroy all TX DMA queues and structures
  1544. */
  1545. void iwl4965_hw_txq_ctx_free(struct iwl4965_priv *priv)
  1546. {
  1547. int txq_id;
  1548. /* Tx queues */
  1549. for (txq_id = 0; txq_id < priv->hw_setting.max_txq_num; txq_id++)
  1550. iwl4965_tx_queue_free(priv, &priv->txq[txq_id]);
  1551. /* Keep-warm buffer */
  1552. iwl4965_kw_free(priv);
  1553. }
  1554. /**
  1555. * iwl4965_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr]
  1556. *
  1557. * Does NOT advance any TFD circular buffer read/write indexes
  1558. * Does NOT free the TFD itself (which is within circular buffer)
  1559. */
  1560. int iwl4965_hw_txq_free_tfd(struct iwl4965_priv *priv, struct iwl4965_tx_queue *txq)
  1561. {
  1562. struct iwl4965_tfd_frame *bd_tmp = (struct iwl4965_tfd_frame *)&txq->bd[0];
  1563. struct iwl4965_tfd_frame *bd = &bd_tmp[txq->q.read_ptr];
  1564. struct pci_dev *dev = priv->pci_dev;
  1565. int i;
  1566. int counter = 0;
  1567. int index, is_odd;
  1568. /* Host command buffers stay mapped in memory, nothing to clean */
  1569. if (txq->q.id == IWL_CMD_QUEUE_NUM)
  1570. return 0;
  1571. /* Sanity check on number of chunks */
  1572. counter = IWL_GET_BITS(*bd, num_tbs);
  1573. if (counter > MAX_NUM_OF_TBS) {
  1574. IWL_ERROR("Too many chunks: %i\n", counter);
  1575. /* @todo issue fatal error, it is quite serious situation */
  1576. return 0;
  1577. }
  1578. /* Unmap chunks, if any.
  1579. * TFD info for odd chunks is different format than for even chunks. */
  1580. for (i = 0; i < counter; i++) {
  1581. index = i / 2;
  1582. is_odd = i & 0x1;
  1583. if (is_odd)
  1584. pci_unmap_single(
  1585. dev,
  1586. IWL_GET_BITS(bd->pa[index], tb2_addr_lo16) |
  1587. (IWL_GET_BITS(bd->pa[index],
  1588. tb2_addr_hi20) << 16),
  1589. IWL_GET_BITS(bd->pa[index], tb2_len),
  1590. PCI_DMA_TODEVICE);
  1591. else if (i > 0)
  1592. pci_unmap_single(dev,
  1593. le32_to_cpu(bd->pa[index].tb1_addr),
  1594. IWL_GET_BITS(bd->pa[index], tb1_len),
  1595. PCI_DMA_TODEVICE);
  1596. /* Free SKB, if any, for this chunk */
  1597. if (txq->txb[txq->q.read_ptr].skb[i]) {
  1598. struct sk_buff *skb = txq->txb[txq->q.read_ptr].skb[i];
  1599. dev_kfree_skb(skb);
  1600. txq->txb[txq->q.read_ptr].skb[i] = NULL;
  1601. }
  1602. }
  1603. return 0;
  1604. }
  1605. int iwl4965_hw_reg_set_txpower(struct iwl4965_priv *priv, s8 power)
  1606. {
  1607. IWL_ERROR("TODO: Implement iwl4965_hw_reg_set_txpower!\n");
  1608. return -EINVAL;
  1609. }
  1610. static s32 iwl4965_math_div_round(s32 num, s32 denom, s32 *res)
  1611. {
  1612. s32 sign = 1;
  1613. if (num < 0) {
  1614. sign = -sign;
  1615. num = -num;
  1616. }
  1617. if (denom < 0) {
  1618. sign = -sign;
  1619. denom = -denom;
  1620. }
  1621. *res = 1;
  1622. *res = ((num * 2 + denom) / (denom * 2)) * sign;
  1623. return 1;
  1624. }
  1625. /**
  1626. * iwl4965_get_voltage_compensation - Power supply voltage comp for txpower
  1627. *
  1628. * Determines power supply voltage compensation for txpower calculations.
  1629. * Returns number of 1/2-dB steps to subtract from gain table index,
  1630. * to compensate for difference between power supply voltage during
  1631. * factory measurements, vs. current power supply voltage.
  1632. *
  1633. * Voltage indication is higher for lower voltage.
  1634. * Lower voltage requires more gain (lower gain table index).
  1635. */
  1636. static s32 iwl4965_get_voltage_compensation(s32 eeprom_voltage,
  1637. s32 current_voltage)
  1638. {
  1639. s32 comp = 0;
  1640. if ((TX_POWER_IWL_ILLEGAL_VOLTAGE == eeprom_voltage) ||
  1641. (TX_POWER_IWL_ILLEGAL_VOLTAGE == current_voltage))
  1642. return 0;
  1643. iwl4965_math_div_round(current_voltage - eeprom_voltage,
  1644. TX_POWER_IWL_VOLTAGE_CODES_PER_03V, &comp);
  1645. if (current_voltage > eeprom_voltage)
  1646. comp *= 2;
  1647. if ((comp < -2) || (comp > 2))
  1648. comp = 0;
  1649. return comp;
  1650. }
  1651. static const struct iwl4965_channel_info *
  1652. iwl4965_get_channel_txpower_info(struct iwl4965_priv *priv,
  1653. enum ieee80211_band band, u16 channel)
  1654. {
  1655. const struct iwl4965_channel_info *ch_info;
  1656. ch_info = iwl4965_get_channel_info(priv, band, channel);
  1657. if (!is_channel_valid(ch_info))
  1658. return NULL;
  1659. return ch_info;
  1660. }
  1661. static s32 iwl4965_get_tx_atten_grp(u16 channel)
  1662. {
  1663. if (channel >= CALIB_IWL_TX_ATTEN_GR5_FCH &&
  1664. channel <= CALIB_IWL_TX_ATTEN_GR5_LCH)
  1665. return CALIB_CH_GROUP_5;
  1666. if (channel >= CALIB_IWL_TX_ATTEN_GR1_FCH &&
  1667. channel <= CALIB_IWL_TX_ATTEN_GR1_LCH)
  1668. return CALIB_CH_GROUP_1;
  1669. if (channel >= CALIB_IWL_TX_ATTEN_GR2_FCH &&
  1670. channel <= CALIB_IWL_TX_ATTEN_GR2_LCH)
  1671. return CALIB_CH_GROUP_2;
  1672. if (channel >= CALIB_IWL_TX_ATTEN_GR3_FCH &&
  1673. channel <= CALIB_IWL_TX_ATTEN_GR3_LCH)
  1674. return CALIB_CH_GROUP_3;
  1675. if (channel >= CALIB_IWL_TX_ATTEN_GR4_FCH &&
  1676. channel <= CALIB_IWL_TX_ATTEN_GR4_LCH)
  1677. return CALIB_CH_GROUP_4;
  1678. IWL_ERROR("Can't find txatten group for channel %d.\n", channel);
  1679. return -1;
  1680. }
  1681. static u32 iwl4965_get_sub_band(const struct iwl4965_priv *priv, u32 channel)
  1682. {
  1683. s32 b = -1;
  1684. for (b = 0; b < EEPROM_TX_POWER_BANDS; b++) {
  1685. if (priv->eeprom.calib_info.band_info[b].ch_from == 0)
  1686. continue;
  1687. if ((channel >= priv->eeprom.calib_info.band_info[b].ch_from)
  1688. && (channel <= priv->eeprom.calib_info.band_info[b].ch_to))
  1689. break;
  1690. }
  1691. return b;
  1692. }
  1693. static s32 iwl4965_interpolate_value(s32 x, s32 x1, s32 y1, s32 x2, s32 y2)
  1694. {
  1695. s32 val;
  1696. if (x2 == x1)
  1697. return y1;
  1698. else {
  1699. iwl4965_math_div_round((x2 - x) * (y1 - y2), (x2 - x1), &val);
  1700. return val + y2;
  1701. }
  1702. }
  1703. /**
  1704. * iwl4965_interpolate_chan - Interpolate factory measurements for one channel
  1705. *
  1706. * Interpolates factory measurements from the two sample channels within a
  1707. * sub-band, to apply to channel of interest. Interpolation is proportional to
  1708. * differences in channel frequencies, which is proportional to differences
  1709. * in channel number.
  1710. */
  1711. static int iwl4965_interpolate_chan(struct iwl4965_priv *priv, u32 channel,
  1712. struct iwl4965_eeprom_calib_ch_info *chan_info)
  1713. {
  1714. s32 s = -1;
  1715. u32 c;
  1716. u32 m;
  1717. const struct iwl4965_eeprom_calib_measure *m1;
  1718. const struct iwl4965_eeprom_calib_measure *m2;
  1719. struct iwl4965_eeprom_calib_measure *omeas;
  1720. u32 ch_i1;
  1721. u32 ch_i2;
  1722. s = iwl4965_get_sub_band(priv, channel);
  1723. if (s >= EEPROM_TX_POWER_BANDS) {
  1724. IWL_ERROR("Tx Power can not find channel %d ", channel);
  1725. return -1;
  1726. }
  1727. ch_i1 = priv->eeprom.calib_info.band_info[s].ch1.ch_num;
  1728. ch_i2 = priv->eeprom.calib_info.band_info[s].ch2.ch_num;
  1729. chan_info->ch_num = (u8) channel;
  1730. IWL_DEBUG_TXPOWER("channel %d subband %d factory cal ch %d & %d\n",
  1731. channel, s, ch_i1, ch_i2);
  1732. for (c = 0; c < EEPROM_TX_POWER_TX_CHAINS; c++) {
  1733. for (m = 0; m < EEPROM_TX_POWER_MEASUREMENTS; m++) {
  1734. m1 = &(priv->eeprom.calib_info.band_info[s].ch1.
  1735. measurements[c][m]);
  1736. m2 = &(priv->eeprom.calib_info.band_info[s].ch2.
  1737. measurements[c][m]);
  1738. omeas = &(chan_info->measurements[c][m]);
  1739. omeas->actual_pow =
  1740. (u8) iwl4965_interpolate_value(channel, ch_i1,
  1741. m1->actual_pow,
  1742. ch_i2,
  1743. m2->actual_pow);
  1744. omeas->gain_idx =
  1745. (u8) iwl4965_interpolate_value(channel, ch_i1,
  1746. m1->gain_idx, ch_i2,
  1747. m2->gain_idx);
  1748. omeas->temperature =
  1749. (u8) iwl4965_interpolate_value(channel, ch_i1,
  1750. m1->temperature,
  1751. ch_i2,
  1752. m2->temperature);
  1753. omeas->pa_det =
  1754. (s8) iwl4965_interpolate_value(channel, ch_i1,
  1755. m1->pa_det, ch_i2,
  1756. m2->pa_det);
  1757. IWL_DEBUG_TXPOWER
  1758. ("chain %d meas %d AP1=%d AP2=%d AP=%d\n", c, m,
  1759. m1->actual_pow, m2->actual_pow, omeas->actual_pow);
  1760. IWL_DEBUG_TXPOWER
  1761. ("chain %d meas %d NI1=%d NI2=%d NI=%d\n", c, m,
  1762. m1->gain_idx, m2->gain_idx, omeas->gain_idx);
  1763. IWL_DEBUG_TXPOWER
  1764. ("chain %d meas %d PA1=%d PA2=%d PA=%d\n", c, m,
  1765. m1->pa_det, m2->pa_det, omeas->pa_det);
  1766. IWL_DEBUG_TXPOWER
  1767. ("chain %d meas %d T1=%d T2=%d T=%d\n", c, m,
  1768. m1->temperature, m2->temperature,
  1769. omeas->temperature);
  1770. }
  1771. }
  1772. return 0;
  1773. }
  1774. /* bit-rate-dependent table to prevent Tx distortion, in half-dB units,
  1775. * for OFDM 6, 12, 18, 24, 36, 48, 54, 60 MBit, and CCK all rates. */
  1776. static s32 back_off_table[] = {
  1777. 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 20 MHz */
  1778. 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 20 MHz */
  1779. 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM SISO 40 MHz */
  1780. 10, 10, 10, 10, 10, 15, 17, 20, /* OFDM MIMO 40 MHz */
  1781. 10 /* CCK */
  1782. };
  1783. /* Thermal compensation values for txpower for various frequency ranges ...
  1784. * ratios from 3:1 to 4.5:1 of degrees (Celsius) per half-dB gain adjust */
  1785. static struct iwl4965_txpower_comp_entry {
  1786. s32 degrees_per_05db_a;
  1787. s32 degrees_per_05db_a_denom;
  1788. } tx_power_cmp_tble[CALIB_CH_GROUP_MAX] = {
  1789. {9, 2}, /* group 0 5.2, ch 34-43 */
  1790. {4, 1}, /* group 1 5.2, ch 44-70 */
  1791. {4, 1}, /* group 2 5.2, ch 71-124 */
  1792. {4, 1}, /* group 3 5.2, ch 125-200 */
  1793. {3, 1} /* group 4 2.4, ch all */
  1794. };
  1795. static s32 get_min_power_index(s32 rate_power_index, u32 band)
  1796. {
  1797. if (!band) {
  1798. if ((rate_power_index & 7) <= 4)
  1799. return MIN_TX_GAIN_INDEX_52GHZ_EXT;
  1800. }
  1801. return MIN_TX_GAIN_INDEX;
  1802. }
  1803. struct gain_entry {
  1804. u8 dsp;
  1805. u8 radio;
  1806. };
  1807. static const struct gain_entry gain_table[2][108] = {
  1808. /* 5.2GHz power gain index table */
  1809. {
  1810. {123, 0x3F}, /* highest txpower */
  1811. {117, 0x3F},
  1812. {110, 0x3F},
  1813. {104, 0x3F},
  1814. {98, 0x3F},
  1815. {110, 0x3E},
  1816. {104, 0x3E},
  1817. {98, 0x3E},
  1818. {110, 0x3D},
  1819. {104, 0x3D},
  1820. {98, 0x3D},
  1821. {110, 0x3C},
  1822. {104, 0x3C},
  1823. {98, 0x3C},
  1824. {110, 0x3B},
  1825. {104, 0x3B},
  1826. {98, 0x3B},
  1827. {110, 0x3A},
  1828. {104, 0x3A},
  1829. {98, 0x3A},
  1830. {110, 0x39},
  1831. {104, 0x39},
  1832. {98, 0x39},
  1833. {110, 0x38},
  1834. {104, 0x38},
  1835. {98, 0x38},
  1836. {110, 0x37},
  1837. {104, 0x37},
  1838. {98, 0x37},
  1839. {110, 0x36},
  1840. {104, 0x36},
  1841. {98, 0x36},
  1842. {110, 0x35},
  1843. {104, 0x35},
  1844. {98, 0x35},
  1845. {110, 0x34},
  1846. {104, 0x34},
  1847. {98, 0x34},
  1848. {110, 0x33},
  1849. {104, 0x33},
  1850. {98, 0x33},
  1851. {110, 0x32},
  1852. {104, 0x32},
  1853. {98, 0x32},
  1854. {110, 0x31},
  1855. {104, 0x31},
  1856. {98, 0x31},
  1857. {110, 0x30},
  1858. {104, 0x30},
  1859. {98, 0x30},
  1860. {110, 0x25},
  1861. {104, 0x25},
  1862. {98, 0x25},
  1863. {110, 0x24},
  1864. {104, 0x24},
  1865. {98, 0x24},
  1866. {110, 0x23},
  1867. {104, 0x23},
  1868. {98, 0x23},
  1869. {110, 0x22},
  1870. {104, 0x18},
  1871. {98, 0x18},
  1872. {110, 0x17},
  1873. {104, 0x17},
  1874. {98, 0x17},
  1875. {110, 0x16},
  1876. {104, 0x16},
  1877. {98, 0x16},
  1878. {110, 0x15},
  1879. {104, 0x15},
  1880. {98, 0x15},
  1881. {110, 0x14},
  1882. {104, 0x14},
  1883. {98, 0x14},
  1884. {110, 0x13},
  1885. {104, 0x13},
  1886. {98, 0x13},
  1887. {110, 0x12},
  1888. {104, 0x08},
  1889. {98, 0x08},
  1890. {110, 0x07},
  1891. {104, 0x07},
  1892. {98, 0x07},
  1893. {110, 0x06},
  1894. {104, 0x06},
  1895. {98, 0x06},
  1896. {110, 0x05},
  1897. {104, 0x05},
  1898. {98, 0x05},
  1899. {110, 0x04},
  1900. {104, 0x04},
  1901. {98, 0x04},
  1902. {110, 0x03},
  1903. {104, 0x03},
  1904. {98, 0x03},
  1905. {110, 0x02},
  1906. {104, 0x02},
  1907. {98, 0x02},
  1908. {110, 0x01},
  1909. {104, 0x01},
  1910. {98, 0x01},
  1911. {110, 0x00},
  1912. {104, 0x00},
  1913. {98, 0x00},
  1914. {93, 0x00},
  1915. {88, 0x00},
  1916. {83, 0x00},
  1917. {78, 0x00},
  1918. },
  1919. /* 2.4GHz power gain index table */
  1920. {
  1921. {110, 0x3f}, /* highest txpower */
  1922. {104, 0x3f},
  1923. {98, 0x3f},
  1924. {110, 0x3e},
  1925. {104, 0x3e},
  1926. {98, 0x3e},
  1927. {110, 0x3d},
  1928. {104, 0x3d},
  1929. {98, 0x3d},
  1930. {110, 0x3c},
  1931. {104, 0x3c},
  1932. {98, 0x3c},
  1933. {110, 0x3b},
  1934. {104, 0x3b},
  1935. {98, 0x3b},
  1936. {110, 0x3a},
  1937. {104, 0x3a},
  1938. {98, 0x3a},
  1939. {110, 0x39},
  1940. {104, 0x39},
  1941. {98, 0x39},
  1942. {110, 0x38},
  1943. {104, 0x38},
  1944. {98, 0x38},
  1945. {110, 0x37},
  1946. {104, 0x37},
  1947. {98, 0x37},
  1948. {110, 0x36},
  1949. {104, 0x36},
  1950. {98, 0x36},
  1951. {110, 0x35},
  1952. {104, 0x35},
  1953. {98, 0x35},
  1954. {110, 0x34},
  1955. {104, 0x34},
  1956. {98, 0x34},
  1957. {110, 0x33},
  1958. {104, 0x33},
  1959. {98, 0x33},
  1960. {110, 0x32},
  1961. {104, 0x32},
  1962. {98, 0x32},
  1963. {110, 0x31},
  1964. {104, 0x31},
  1965. {98, 0x31},
  1966. {110, 0x30},
  1967. {104, 0x30},
  1968. {98, 0x30},
  1969. {110, 0x6},
  1970. {104, 0x6},
  1971. {98, 0x6},
  1972. {110, 0x5},
  1973. {104, 0x5},
  1974. {98, 0x5},
  1975. {110, 0x4},
  1976. {104, 0x4},
  1977. {98, 0x4},
  1978. {110, 0x3},
  1979. {104, 0x3},
  1980. {98, 0x3},
  1981. {110, 0x2},
  1982. {104, 0x2},
  1983. {98, 0x2},
  1984. {110, 0x1},
  1985. {104, 0x1},
  1986. {98, 0x1},
  1987. {110, 0x0},
  1988. {104, 0x0},
  1989. {98, 0x0},
  1990. {97, 0},
  1991. {96, 0},
  1992. {95, 0},
  1993. {94, 0},
  1994. {93, 0},
  1995. {92, 0},
  1996. {91, 0},
  1997. {90, 0},
  1998. {89, 0},
  1999. {88, 0},
  2000. {87, 0},
  2001. {86, 0},
  2002. {85, 0},
  2003. {84, 0},
  2004. {83, 0},
  2005. {82, 0},
  2006. {81, 0},
  2007. {80, 0},
  2008. {79, 0},
  2009. {78, 0},
  2010. {77, 0},
  2011. {76, 0},
  2012. {75, 0},
  2013. {74, 0},
  2014. {73, 0},
  2015. {72, 0},
  2016. {71, 0},
  2017. {70, 0},
  2018. {69, 0},
  2019. {68, 0},
  2020. {67, 0},
  2021. {66, 0},
  2022. {65, 0},
  2023. {64, 0},
  2024. {63, 0},
  2025. {62, 0},
  2026. {61, 0},
  2027. {60, 0},
  2028. {59, 0},
  2029. }
  2030. };
  2031. static int iwl4965_fill_txpower_tbl(struct iwl4965_priv *priv, u8 band, u16 channel,
  2032. u8 is_fat, u8 ctrl_chan_high,
  2033. struct iwl4965_tx_power_db *tx_power_tbl)
  2034. {
  2035. u8 saturation_power;
  2036. s32 target_power;
  2037. s32 user_target_power;
  2038. s32 power_limit;
  2039. s32 current_temp;
  2040. s32 reg_limit;
  2041. s32 current_regulatory;
  2042. s32 txatten_grp = CALIB_CH_GROUP_MAX;
  2043. int i;
  2044. int c;
  2045. const struct iwl4965_channel_info *ch_info = NULL;
  2046. struct iwl4965_eeprom_calib_ch_info ch_eeprom_info;
  2047. const struct iwl4965_eeprom_calib_measure *measurement;
  2048. s16 voltage;
  2049. s32 init_voltage;
  2050. s32 voltage_compensation;
  2051. s32 degrees_per_05db_num;
  2052. s32 degrees_per_05db_denom;
  2053. s32 factory_temp;
  2054. s32 temperature_comp[2];
  2055. s32 factory_gain_index[2];
  2056. s32 factory_actual_pwr[2];
  2057. s32 power_index;
  2058. /* Sanity check requested level (dBm) */
  2059. if (priv->user_txpower_limit < IWL_TX_POWER_TARGET_POWER_MIN) {
  2060. IWL_WARNING("Requested user TXPOWER %d below limit.\n",
  2061. priv->user_txpower_limit);
  2062. return -EINVAL;
  2063. }
  2064. if (priv->user_txpower_limit > IWL_TX_POWER_TARGET_POWER_MAX) {
  2065. IWL_WARNING("Requested user TXPOWER %d above limit.\n",
  2066. priv->user_txpower_limit);
  2067. return -EINVAL;
  2068. }
  2069. /* user_txpower_limit is in dBm, convert to half-dBm (half-dB units
  2070. * are used for indexing into txpower table) */
  2071. user_target_power = 2 * priv->user_txpower_limit;
  2072. /* Get current (RXON) channel, band, width */
  2073. ch_info =
  2074. iwl4965_get_channel_txpower_info(priv, priv->band, channel);
  2075. IWL_DEBUG_TXPOWER("chan %d band %d is_fat %d\n", channel, band,
  2076. is_fat);
  2077. if (!ch_info)
  2078. return -EINVAL;
  2079. /* get txatten group, used to select 1) thermal txpower adjustment
  2080. * and 2) mimo txpower balance between Tx chains. */
  2081. txatten_grp = iwl4965_get_tx_atten_grp(channel);
  2082. if (txatten_grp < 0)
  2083. return -EINVAL;
  2084. IWL_DEBUG_TXPOWER("channel %d belongs to txatten group %d\n",
  2085. channel, txatten_grp);
  2086. if (is_fat) {
  2087. if (ctrl_chan_high)
  2088. channel -= 2;
  2089. else
  2090. channel += 2;
  2091. }
  2092. /* hardware txpower limits ...
  2093. * saturation (clipping distortion) txpowers are in half-dBm */
  2094. if (band)
  2095. saturation_power = priv->eeprom.calib_info.saturation_power24;
  2096. else
  2097. saturation_power = priv->eeprom.calib_info.saturation_power52;
  2098. if (saturation_power < IWL_TX_POWER_SATURATION_MIN ||
  2099. saturation_power > IWL_TX_POWER_SATURATION_MAX) {
  2100. if (band)
  2101. saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_24;
  2102. else
  2103. saturation_power = IWL_TX_POWER_DEFAULT_SATURATION_52;
  2104. }
  2105. /* regulatory txpower limits ... reg_limit values are in half-dBm,
  2106. * max_power_avg values are in dBm, convert * 2 */
  2107. if (is_fat)
  2108. reg_limit = ch_info->fat_max_power_avg * 2;
  2109. else
  2110. reg_limit = ch_info->max_power_avg * 2;
  2111. if ((reg_limit < IWL_TX_POWER_REGULATORY_MIN) ||
  2112. (reg_limit > IWL_TX_POWER_REGULATORY_MAX)) {
  2113. if (band)
  2114. reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_24;
  2115. else
  2116. reg_limit = IWL_TX_POWER_DEFAULT_REGULATORY_52;
  2117. }
  2118. /* Interpolate txpower calibration values for this channel,
  2119. * based on factory calibration tests on spaced channels. */
  2120. iwl4965_interpolate_chan(priv, channel, &ch_eeprom_info);
  2121. /* calculate tx gain adjustment based on power supply voltage */
  2122. voltage = priv->eeprom.calib_info.voltage;
  2123. init_voltage = (s32)le32_to_cpu(priv->card_alive_init.voltage);
  2124. voltage_compensation =
  2125. iwl4965_get_voltage_compensation(voltage, init_voltage);
  2126. IWL_DEBUG_TXPOWER("curr volt %d eeprom volt %d volt comp %d\n",
  2127. init_voltage,
  2128. voltage, voltage_compensation);
  2129. /* get current temperature (Celsius) */
  2130. current_temp = max(priv->temperature, IWL_TX_POWER_TEMPERATURE_MIN);
  2131. current_temp = min(priv->temperature, IWL_TX_POWER_TEMPERATURE_MAX);
  2132. current_temp = KELVIN_TO_CELSIUS(current_temp);
  2133. /* select thermal txpower adjustment params, based on channel group
  2134. * (same frequency group used for mimo txatten adjustment) */
  2135. degrees_per_05db_num =
  2136. tx_power_cmp_tble[txatten_grp].degrees_per_05db_a;
  2137. degrees_per_05db_denom =
  2138. tx_power_cmp_tble[txatten_grp].degrees_per_05db_a_denom;
  2139. /* get per-chain txpower values from factory measurements */
  2140. for (c = 0; c < 2; c++) {
  2141. measurement = &ch_eeprom_info.measurements[c][1];
  2142. /* txgain adjustment (in half-dB steps) based on difference
  2143. * between factory and current temperature */
  2144. factory_temp = measurement->temperature;
  2145. iwl4965_math_div_round((current_temp - factory_temp) *
  2146. degrees_per_05db_denom,
  2147. degrees_per_05db_num,
  2148. &temperature_comp[c]);
  2149. factory_gain_index[c] = measurement->gain_idx;
  2150. factory_actual_pwr[c] = measurement->actual_pow;
  2151. IWL_DEBUG_TXPOWER("chain = %d\n", c);
  2152. IWL_DEBUG_TXPOWER("fctry tmp %d, "
  2153. "curr tmp %d, comp %d steps\n",
  2154. factory_temp, current_temp,
  2155. temperature_comp[c]);
  2156. IWL_DEBUG_TXPOWER("fctry idx %d, fctry pwr %d\n",
  2157. factory_gain_index[c],
  2158. factory_actual_pwr[c]);
  2159. }
  2160. /* for each of 33 bit-rates (including 1 for CCK) */
  2161. for (i = 0; i < POWER_TABLE_NUM_ENTRIES; i++) {
  2162. u8 is_mimo_rate;
  2163. union iwl4965_tx_power_dual_stream tx_power;
  2164. /* for mimo, reduce each chain's txpower by half
  2165. * (3dB, 6 steps), so total output power is regulatory
  2166. * compliant. */
  2167. if (i & 0x8) {
  2168. current_regulatory = reg_limit -
  2169. IWL_TX_POWER_MIMO_REGULATORY_COMPENSATION;
  2170. is_mimo_rate = 1;
  2171. } else {
  2172. current_regulatory = reg_limit;
  2173. is_mimo_rate = 0;
  2174. }
  2175. /* find txpower limit, either hardware or regulatory */
  2176. power_limit = saturation_power - back_off_table[i];
  2177. if (power_limit > current_regulatory)
  2178. power_limit = current_regulatory;
  2179. /* reduce user's txpower request if necessary
  2180. * for this rate on this channel */
  2181. target_power = user_target_power;
  2182. if (target_power > power_limit)
  2183. target_power = power_limit;
  2184. IWL_DEBUG_TXPOWER("rate %d sat %d reg %d usr %d tgt %d\n",
  2185. i, saturation_power - back_off_table[i],
  2186. current_regulatory, user_target_power,
  2187. target_power);
  2188. /* for each of 2 Tx chains (radio transmitters) */
  2189. for (c = 0; c < 2; c++) {
  2190. s32 atten_value;
  2191. if (is_mimo_rate)
  2192. atten_value =
  2193. (s32)le32_to_cpu(priv->card_alive_init.
  2194. tx_atten[txatten_grp][c]);
  2195. else
  2196. atten_value = 0;
  2197. /* calculate index; higher index means lower txpower */
  2198. power_index = (u8) (factory_gain_index[c] -
  2199. (target_power -
  2200. factory_actual_pwr[c]) -
  2201. temperature_comp[c] -
  2202. voltage_compensation +
  2203. atten_value);
  2204. /* IWL_DEBUG_TXPOWER("calculated txpower index %d\n",
  2205. power_index); */
  2206. if (power_index < get_min_power_index(i, band))
  2207. power_index = get_min_power_index(i, band);
  2208. /* adjust 5 GHz index to support negative indexes */
  2209. if (!band)
  2210. power_index += 9;
  2211. /* CCK, rate 32, reduce txpower for CCK */
  2212. if (i == POWER_TABLE_CCK_ENTRY)
  2213. power_index +=
  2214. IWL_TX_POWER_CCK_COMPENSATION_C_STEP;
  2215. /* stay within the table! */
  2216. if (power_index > 107) {
  2217. IWL_WARNING("txpower index %d > 107\n",
  2218. power_index);
  2219. power_index = 107;
  2220. }
  2221. if (power_index < 0) {
  2222. IWL_WARNING("txpower index %d < 0\n",
  2223. power_index);
  2224. power_index = 0;
  2225. }
  2226. /* fill txpower command for this rate/chain */
  2227. tx_power.s.radio_tx_gain[c] =
  2228. gain_table[band][power_index].radio;
  2229. tx_power.s.dsp_predis_atten[c] =
  2230. gain_table[band][power_index].dsp;
  2231. IWL_DEBUG_TXPOWER("chain %d mimo %d index %d "
  2232. "gain 0x%02x dsp %d\n",
  2233. c, atten_value, power_index,
  2234. tx_power.s.radio_tx_gain[c],
  2235. tx_power.s.dsp_predis_atten[c]);
  2236. }/* for each chain */
  2237. tx_power_tbl->power_tbl[i].dw = cpu_to_le32(tx_power.dw);
  2238. }/* for each rate */
  2239. return 0;
  2240. }
  2241. /**
  2242. * iwl4965_hw_reg_send_txpower - Configure the TXPOWER level user limit
  2243. *
  2244. * Uses the active RXON for channel, band, and characteristics (fat, high)
  2245. * The power limit is taken from priv->user_txpower_limit.
  2246. */
  2247. int iwl4965_hw_reg_send_txpower(struct iwl4965_priv *priv)
  2248. {
  2249. struct iwl4965_txpowertable_cmd cmd = { 0 };
  2250. int rc = 0;
  2251. u8 band = 0;
  2252. u8 is_fat = 0;
  2253. u8 ctrl_chan_high = 0;
  2254. if (test_bit(STATUS_SCANNING, &priv->status)) {
  2255. /* If this gets hit a lot, switch it to a BUG() and catch
  2256. * the stack trace to find out who is calling this during
  2257. * a scan. */
  2258. IWL_WARNING("TX Power requested while scanning!\n");
  2259. return -EAGAIN;
  2260. }
  2261. band = priv->band == IEEE80211_BAND_2GHZ;
  2262. is_fat = is_fat_channel(priv->active_rxon.flags);
  2263. if (is_fat &&
  2264. (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
  2265. ctrl_chan_high = 1;
  2266. cmd.band = band;
  2267. cmd.channel = priv->active_rxon.channel;
  2268. rc = iwl4965_fill_txpower_tbl(priv, band,
  2269. le16_to_cpu(priv->active_rxon.channel),
  2270. is_fat, ctrl_chan_high, &cmd.tx_power);
  2271. if (rc)
  2272. return rc;
  2273. rc = iwl4965_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD, sizeof(cmd), &cmd);
  2274. return rc;
  2275. }
  2276. int iwl4965_hw_channel_switch(struct iwl4965_priv *priv, u16 channel)
  2277. {
  2278. int rc;
  2279. u8 band = 0;
  2280. u8 is_fat = 0;
  2281. u8 ctrl_chan_high = 0;
  2282. struct iwl4965_channel_switch_cmd cmd = { 0 };
  2283. const struct iwl4965_channel_info *ch_info;
  2284. band = priv->band == IEEE80211_BAND_2GHZ;
  2285. ch_info = iwl4965_get_channel_info(priv, priv->band, channel);
  2286. is_fat = is_fat_channel(priv->staging_rxon.flags);
  2287. if (is_fat &&
  2288. (priv->active_rxon.flags & RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK))
  2289. ctrl_chan_high = 1;
  2290. cmd.band = band;
  2291. cmd.expect_beacon = 0;
  2292. cmd.channel = cpu_to_le16(channel);
  2293. cmd.rxon_flags = priv->active_rxon.flags;
  2294. cmd.rxon_filter_flags = priv->active_rxon.filter_flags;
  2295. cmd.switch_time = cpu_to_le32(priv->ucode_beacon_time);
  2296. if (ch_info)
  2297. cmd.expect_beacon = is_channel_radar(ch_info);
  2298. else
  2299. cmd.expect_beacon = 1;
  2300. rc = iwl4965_fill_txpower_tbl(priv, band, channel, is_fat,
  2301. ctrl_chan_high, &cmd.tx_power);
  2302. if (rc) {
  2303. IWL_DEBUG_11H("error:%d fill txpower_tbl\n", rc);
  2304. return rc;
  2305. }
  2306. rc = iwl4965_send_cmd_pdu(priv, REPLY_CHANNEL_SWITCH, sizeof(cmd), &cmd);
  2307. return rc;
  2308. }
  2309. #define RTS_HCCA_RETRY_LIMIT 3
  2310. #define RTS_DFAULT_RETRY_LIMIT 60
  2311. void iwl4965_hw_build_tx_cmd_rate(struct iwl4965_priv *priv,
  2312. struct iwl4965_cmd *cmd,
  2313. struct ieee80211_tx_control *ctrl,
  2314. struct ieee80211_hdr *hdr, int sta_id,
  2315. int is_hcca)
  2316. {
  2317. struct iwl4965_tx_cmd *tx = &cmd->cmd.tx;
  2318. u8 rts_retry_limit = 0;
  2319. u8 data_retry_limit = 0;
  2320. u16 fc = le16_to_cpu(hdr->frame_control);
  2321. u8 rate_plcp;
  2322. u16 rate_flags = 0;
  2323. int rate_idx = min(ctrl->tx_rate->hw_value & 0xffff, IWL_RATE_COUNT - 1);
  2324. rate_plcp = iwl4965_rates[rate_idx].plcp;
  2325. rts_retry_limit = (is_hcca) ?
  2326. RTS_HCCA_RETRY_LIMIT : RTS_DFAULT_RETRY_LIMIT;
  2327. if ((rate_idx >= IWL_FIRST_CCK_RATE) && (rate_idx <= IWL_LAST_CCK_RATE))
  2328. rate_flags |= RATE_MCS_CCK_MSK;
  2329. if (ieee80211_is_probe_response(fc)) {
  2330. data_retry_limit = 3;
  2331. if (data_retry_limit < rts_retry_limit)
  2332. rts_retry_limit = data_retry_limit;
  2333. } else
  2334. data_retry_limit = IWL_DEFAULT_TX_RETRY;
  2335. if (priv->data_retry_limit != -1)
  2336. data_retry_limit = priv->data_retry_limit;
  2337. if (ieee80211_is_data(fc)) {
  2338. tx->initial_rate_index = 0;
  2339. tx->tx_flags |= TX_CMD_FLG_STA_RATE_MSK;
  2340. } else {
  2341. switch (fc & IEEE80211_FCTL_STYPE) {
  2342. case IEEE80211_STYPE_AUTH:
  2343. case IEEE80211_STYPE_DEAUTH:
  2344. case IEEE80211_STYPE_ASSOC_REQ:
  2345. case IEEE80211_STYPE_REASSOC_REQ:
  2346. if (tx->tx_flags & TX_CMD_FLG_RTS_MSK) {
  2347. tx->tx_flags &= ~TX_CMD_FLG_RTS_MSK;
  2348. tx->tx_flags |= TX_CMD_FLG_CTS_MSK;
  2349. }
  2350. break;
  2351. default:
  2352. break;
  2353. }
  2354. /* Alternate between antenna A and B for successive frames */
  2355. if (priv->use_ant_b_for_management_frame) {
  2356. priv->use_ant_b_for_management_frame = 0;
  2357. rate_flags |= RATE_MCS_ANT_B_MSK;
  2358. } else {
  2359. priv->use_ant_b_for_management_frame = 1;
  2360. rate_flags |= RATE_MCS_ANT_A_MSK;
  2361. }
  2362. }
  2363. tx->rts_retry_limit = rts_retry_limit;
  2364. tx->data_retry_limit = data_retry_limit;
  2365. tx->rate_n_flags = iwl4965_hw_set_rate_n_flags(rate_plcp, rate_flags);
  2366. }
  2367. int iwl4965_hw_get_rx_read(struct iwl4965_priv *priv)
  2368. {
  2369. struct iwl4965_shared *shared_data = priv->hw_setting.shared_virt;
  2370. return IWL_GET_BITS(*shared_data, rb_closed_stts_rb_num);
  2371. }
  2372. int iwl4965_hw_get_temperature(struct iwl4965_priv *priv)
  2373. {
  2374. return priv->temperature;
  2375. }
  2376. unsigned int iwl4965_hw_get_beacon_cmd(struct iwl4965_priv *priv,
  2377. struct iwl4965_frame *frame, u8 rate)
  2378. {
  2379. struct iwl4965_tx_beacon_cmd *tx_beacon_cmd;
  2380. unsigned int frame_size;
  2381. tx_beacon_cmd = &frame->u.beacon;
  2382. memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd));
  2383. tx_beacon_cmd->tx.sta_id = IWL4965_BROADCAST_ID;
  2384. tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE;
  2385. frame_size = iwl4965_fill_beacon_frame(priv,
  2386. tx_beacon_cmd->frame,
  2387. iwl4965_broadcast_addr,
  2388. sizeof(frame->u) - sizeof(*tx_beacon_cmd));
  2389. BUG_ON(frame_size > MAX_MPDU_SIZE);
  2390. tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size);
  2391. if ((rate == IWL_RATE_1M_PLCP) || (rate >= IWL_RATE_2M_PLCP))
  2392. tx_beacon_cmd->tx.rate_n_flags =
  2393. iwl4965_hw_set_rate_n_flags(rate, RATE_MCS_CCK_MSK);
  2394. else
  2395. tx_beacon_cmd->tx.rate_n_flags =
  2396. iwl4965_hw_set_rate_n_flags(rate, 0);
  2397. tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK |
  2398. TX_CMD_FLG_TSF_MSK | TX_CMD_FLG_STA_RATE_MSK);
  2399. return (sizeof(*tx_beacon_cmd) + frame_size);
  2400. }
  2401. /*
  2402. * Tell 4965 where to find circular buffer of Tx Frame Descriptors for
  2403. * given Tx queue, and enable the DMA channel used for that queue.
  2404. *
  2405. * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA
  2406. * channels supported in hardware.
  2407. */
  2408. int iwl4965_hw_tx_queue_init(struct iwl4965_priv *priv, struct iwl4965_tx_queue *txq)
  2409. {
  2410. int rc;
  2411. unsigned long flags;
  2412. int txq_id = txq->q.id;
  2413. spin_lock_irqsave(&priv->lock, flags);
  2414. rc = iwl4965_grab_nic_access(priv);
  2415. if (rc) {
  2416. spin_unlock_irqrestore(&priv->lock, flags);
  2417. return rc;
  2418. }
  2419. /* Circular buffer (TFD queue in DRAM) physical base address */
  2420. iwl4965_write_direct32(priv, FH_MEM_CBBC_QUEUE(txq_id),
  2421. txq->q.dma_addr >> 8);
  2422. /* Enable DMA channel, using same id as for TFD queue */
  2423. iwl4965_write_direct32(
  2424. priv, IWL_FH_TCSR_CHNL_TX_CONFIG_REG(txq_id),
  2425. IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
  2426. IWL_FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL);
  2427. iwl4965_release_nic_access(priv);
  2428. spin_unlock_irqrestore(&priv->lock, flags);
  2429. return 0;
  2430. }
  2431. int iwl4965_hw_txq_attach_buf_to_tfd(struct iwl4965_priv *priv, void *ptr,
  2432. dma_addr_t addr, u16 len)
  2433. {
  2434. int index, is_odd;
  2435. struct iwl4965_tfd_frame *tfd = ptr;
  2436. u32 num_tbs = IWL_GET_BITS(*tfd, num_tbs);
  2437. /* Each TFD can point to a maximum 20 Tx buffers */
  2438. if ((num_tbs >= MAX_NUM_OF_TBS) || (num_tbs < 0)) {
  2439. IWL_ERROR("Error can not send more than %d chunks\n",
  2440. MAX_NUM_OF_TBS);
  2441. return -EINVAL;
  2442. }
  2443. index = num_tbs / 2;
  2444. is_odd = num_tbs & 0x1;
  2445. if (!is_odd) {
  2446. tfd->pa[index].tb1_addr = cpu_to_le32(addr);
  2447. IWL_SET_BITS(tfd->pa[index], tb1_addr_hi,
  2448. iwl_get_dma_hi_address(addr));
  2449. IWL_SET_BITS(tfd->pa[index], tb1_len, len);
  2450. } else {
  2451. IWL_SET_BITS(tfd->pa[index], tb2_addr_lo16,
  2452. (u32) (addr & 0xffff));
  2453. IWL_SET_BITS(tfd->pa[index], tb2_addr_hi20, addr >> 16);
  2454. IWL_SET_BITS(tfd->pa[index], tb2_len, len);
  2455. }
  2456. IWL_SET_BITS(*tfd, num_tbs, num_tbs + 1);
  2457. return 0;
  2458. }
  2459. static void iwl4965_hw_card_show_info(struct iwl4965_priv *priv)
  2460. {
  2461. u16 hw_version = priv->eeprom.board_revision_4965;
  2462. IWL_DEBUG_INFO("4965ABGN HW Version %u.%u.%u\n",
  2463. ((hw_version >> 8) & 0x0F),
  2464. ((hw_version >> 8) >> 4), (hw_version & 0x00FF));
  2465. IWL_DEBUG_INFO("4965ABGN PBA Number %.16s\n",
  2466. priv->eeprom.board_pba_number_4965);
  2467. }
  2468. #define IWL_TX_CRC_SIZE 4
  2469. #define IWL_TX_DELIMITER_SIZE 4
  2470. /**
  2471. * iwl4965_tx_queue_update_wr_ptr - Set up entry in Tx byte-count array
  2472. */
  2473. int iwl4965_tx_queue_update_wr_ptr(struct iwl4965_priv *priv,
  2474. struct iwl4965_tx_queue *txq, u16 byte_cnt)
  2475. {
  2476. int len;
  2477. int txq_id = txq->q.id;
  2478. struct iwl4965_shared *shared_data = priv->hw_setting.shared_virt;
  2479. if (txq->need_update == 0)
  2480. return 0;
  2481. len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
  2482. /* Set up byte count within first 256 entries */
  2483. IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
  2484. tfd_offset[txq->q.write_ptr], byte_cnt, len);
  2485. /* If within first 64 entries, duplicate at end */
  2486. if (txq->q.write_ptr < IWL4965_MAX_WIN_SIZE)
  2487. IWL_SET_BITS16(shared_data->queues_byte_cnt_tbls[txq_id].
  2488. tfd_offset[IWL4965_QUEUE_SIZE + txq->q.write_ptr],
  2489. byte_cnt, len);
  2490. return 0;
  2491. }
  2492. /**
  2493. * iwl4965_set_rxon_chain - Set up Rx chain usage in "staging" RXON image
  2494. *
  2495. * Selects how many and which Rx receivers/antennas/chains to use.
  2496. * This should not be used for scan command ... it puts data in wrong place.
  2497. */
  2498. void iwl4965_set_rxon_chain(struct iwl4965_priv *priv)
  2499. {
  2500. u8 is_single = is_single_stream(priv);
  2501. u8 idle_state, rx_state;
  2502. priv->staging_rxon.rx_chain = 0;
  2503. rx_state = idle_state = 3;
  2504. /* Tell uCode which antennas are actually connected.
  2505. * Before first association, we assume all antennas are connected.
  2506. * Just after first association, iwl4965_noise_calibration()
  2507. * checks which antennas actually *are* connected. */
  2508. priv->staging_rxon.rx_chain |=
  2509. cpu_to_le16(priv->valid_antenna << RXON_RX_CHAIN_VALID_POS);
  2510. /* How many receivers should we use? */
  2511. iwl4965_get_rx_chain_counter(priv, &idle_state, &rx_state);
  2512. priv->staging_rxon.rx_chain |=
  2513. cpu_to_le16(rx_state << RXON_RX_CHAIN_MIMO_CNT_POS);
  2514. priv->staging_rxon.rx_chain |=
  2515. cpu_to_le16(idle_state << RXON_RX_CHAIN_CNT_POS);
  2516. if (!is_single && (rx_state >= 2) &&
  2517. !test_bit(STATUS_POWER_PMI, &priv->status))
  2518. priv->staging_rxon.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK;
  2519. else
  2520. priv->staging_rxon.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK;
  2521. IWL_DEBUG_ASSOC("rx chain %X\n", priv->staging_rxon.rx_chain);
  2522. }
  2523. /**
  2524. * sign_extend - Sign extend a value using specified bit as sign-bit
  2525. *
  2526. * Example: sign_extend(9, 3) would return -7 as bit3 of 1001b is 1
  2527. * and bit0..2 is 001b which when sign extended to 1111111111111001b is -7.
  2528. *
  2529. * @param oper value to sign extend
  2530. * @param index 0 based bit index (0<=index<32) to sign bit
  2531. */
  2532. static s32 sign_extend(u32 oper, int index)
  2533. {
  2534. u8 shift = 31 - index;
  2535. return (s32)(oper << shift) >> shift;
  2536. }
  2537. /**
  2538. * iwl4965_get_temperature - return the calibrated temperature (in Kelvin)
  2539. * @statistics: Provides the temperature reading from the uCode
  2540. *
  2541. * A return of <0 indicates bogus data in the statistics
  2542. */
  2543. int iwl4965_get_temperature(const struct iwl4965_priv *priv)
  2544. {
  2545. s32 temperature;
  2546. s32 vt;
  2547. s32 R1, R2, R3;
  2548. u32 R4;
  2549. if (test_bit(STATUS_TEMPERATURE, &priv->status) &&
  2550. (priv->statistics.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)) {
  2551. IWL_DEBUG_TEMP("Running FAT temperature calibration\n");
  2552. R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[1]);
  2553. R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[1]);
  2554. R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[1]);
  2555. R4 = le32_to_cpu(priv->card_alive_init.therm_r4[1]);
  2556. } else {
  2557. IWL_DEBUG_TEMP("Running temperature calibration\n");
  2558. R1 = (s32)le32_to_cpu(priv->card_alive_init.therm_r1[0]);
  2559. R2 = (s32)le32_to_cpu(priv->card_alive_init.therm_r2[0]);
  2560. R3 = (s32)le32_to_cpu(priv->card_alive_init.therm_r3[0]);
  2561. R4 = le32_to_cpu(priv->card_alive_init.therm_r4[0]);
  2562. }
  2563. /*
  2564. * Temperature is only 23 bits, so sign extend out to 32.
  2565. *
  2566. * NOTE If we haven't received a statistics notification yet
  2567. * with an updated temperature, use R4 provided to us in the
  2568. * "initialize" ALIVE response.
  2569. */
  2570. if (!test_bit(STATUS_TEMPERATURE, &priv->status))
  2571. vt = sign_extend(R4, 23);
  2572. else
  2573. vt = sign_extend(
  2574. le32_to_cpu(priv->statistics.general.temperature), 23);
  2575. IWL_DEBUG_TEMP("Calib values R[1-3]: %d %d %d R4: %d\n",
  2576. R1, R2, R3, vt);
  2577. if (R3 == R1) {
  2578. IWL_ERROR("Calibration conflict R1 == R3\n");
  2579. return -1;
  2580. }
  2581. /* Calculate temperature in degrees Kelvin, adjust by 97%.
  2582. * Add offset to center the adjustment around 0 degrees Centigrade. */
  2583. temperature = TEMPERATURE_CALIB_A_VAL * (vt - R2);
  2584. temperature /= (R3 - R1);
  2585. temperature = (temperature * 97) / 100 +
  2586. TEMPERATURE_CALIB_KELVIN_OFFSET;
  2587. IWL_DEBUG_TEMP("Calibrated temperature: %dK, %dC\n", temperature,
  2588. KELVIN_TO_CELSIUS(temperature));
  2589. return temperature;
  2590. }
  2591. /* Adjust Txpower only if temperature variance is greater than threshold. */
  2592. #define IWL_TEMPERATURE_THRESHOLD 3
  2593. /**
  2594. * iwl4965_is_temp_calib_needed - determines if new calibration is needed
  2595. *
  2596. * If the temperature changed has changed sufficiently, then a recalibration
  2597. * is needed.
  2598. *
  2599. * Assumes caller will replace priv->last_temperature once calibration
  2600. * executed.
  2601. */
  2602. static int iwl4965_is_temp_calib_needed(struct iwl4965_priv *priv)
  2603. {
  2604. int temp_diff;
  2605. if (!test_bit(STATUS_STATISTICS, &priv->status)) {
  2606. IWL_DEBUG_TEMP("Temperature not updated -- no statistics.\n");
  2607. return 0;
  2608. }
  2609. temp_diff = priv->temperature - priv->last_temperature;
  2610. /* get absolute value */
  2611. if (temp_diff < 0) {
  2612. IWL_DEBUG_POWER("Getting cooler, delta %d, \n", temp_diff);
  2613. temp_diff = -temp_diff;
  2614. } else if (temp_diff == 0)
  2615. IWL_DEBUG_POWER("Same temp, \n");
  2616. else
  2617. IWL_DEBUG_POWER("Getting warmer, delta %d, \n", temp_diff);
  2618. if (temp_diff < IWL_TEMPERATURE_THRESHOLD) {
  2619. IWL_DEBUG_POWER("Thermal txpower calib not needed\n");
  2620. return 0;
  2621. }
  2622. IWL_DEBUG_POWER("Thermal txpower calib needed\n");
  2623. return 1;
  2624. }
  2625. /* Calculate noise level, based on measurements during network silence just
  2626. * before arriving beacon. This measurement can be done only if we know
  2627. * exactly when to expect beacons, therefore only when we're associated. */
  2628. static void iwl4965_rx_calc_noise(struct iwl4965_priv *priv)
  2629. {
  2630. struct statistics_rx_non_phy *rx_info
  2631. = &(priv->statistics.rx.general);
  2632. int num_active_rx = 0;
  2633. int total_silence = 0;
  2634. int bcn_silence_a =
  2635. le32_to_cpu(rx_info->beacon_silence_rssi_a) & IN_BAND_FILTER;
  2636. int bcn_silence_b =
  2637. le32_to_cpu(rx_info->beacon_silence_rssi_b) & IN_BAND_FILTER;
  2638. int bcn_silence_c =
  2639. le32_to_cpu(rx_info->beacon_silence_rssi_c) & IN_BAND_FILTER;
  2640. if (bcn_silence_a) {
  2641. total_silence += bcn_silence_a;
  2642. num_active_rx++;
  2643. }
  2644. if (bcn_silence_b) {
  2645. total_silence += bcn_silence_b;
  2646. num_active_rx++;
  2647. }
  2648. if (bcn_silence_c) {
  2649. total_silence += bcn_silence_c;
  2650. num_active_rx++;
  2651. }
  2652. /* Average among active antennas */
  2653. if (num_active_rx)
  2654. priv->last_rx_noise = (total_silence / num_active_rx) - 107;
  2655. else
  2656. priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
  2657. IWL_DEBUG_CALIB("inband silence a %u, b %u, c %u, dBm %d\n",
  2658. bcn_silence_a, bcn_silence_b, bcn_silence_c,
  2659. priv->last_rx_noise);
  2660. }
  2661. void iwl4965_hw_rx_statistics(struct iwl4965_priv *priv, struct iwl4965_rx_mem_buffer *rxb)
  2662. {
  2663. struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
  2664. int change;
  2665. s32 temp;
  2666. IWL_DEBUG_RX("Statistics notification received (%d vs %d).\n",
  2667. (int)sizeof(priv->statistics), pkt->len);
  2668. change = ((priv->statistics.general.temperature !=
  2669. pkt->u.stats.general.temperature) ||
  2670. ((priv->statistics.flag &
  2671. STATISTICS_REPLY_FLG_FAT_MODE_MSK) !=
  2672. (pkt->u.stats.flag & STATISTICS_REPLY_FLG_FAT_MODE_MSK)));
  2673. memcpy(&priv->statistics, &pkt->u.stats, sizeof(priv->statistics));
  2674. set_bit(STATUS_STATISTICS, &priv->status);
  2675. /* Reschedule the statistics timer to occur in
  2676. * REG_RECALIB_PERIOD seconds to ensure we get a
  2677. * thermal update even if the uCode doesn't give
  2678. * us one */
  2679. mod_timer(&priv->statistics_periodic, jiffies +
  2680. msecs_to_jiffies(REG_RECALIB_PERIOD * 1000));
  2681. if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
  2682. (pkt->hdr.cmd == STATISTICS_NOTIFICATION)) {
  2683. iwl4965_rx_calc_noise(priv);
  2684. #ifdef CONFIG_IWL4965_SENSITIVITY
  2685. queue_work(priv->workqueue, &priv->sensitivity_work);
  2686. #endif
  2687. }
  2688. /* If the hardware hasn't reported a change in
  2689. * temperature then don't bother computing a
  2690. * calibrated temperature value */
  2691. if (!change)
  2692. return;
  2693. temp = iwl4965_get_temperature(priv);
  2694. if (temp < 0)
  2695. return;
  2696. if (priv->temperature != temp) {
  2697. if (priv->temperature)
  2698. IWL_DEBUG_TEMP("Temperature changed "
  2699. "from %dC to %dC\n",
  2700. KELVIN_TO_CELSIUS(priv->temperature),
  2701. KELVIN_TO_CELSIUS(temp));
  2702. else
  2703. IWL_DEBUG_TEMP("Temperature "
  2704. "initialized to %dC\n",
  2705. KELVIN_TO_CELSIUS(temp));
  2706. }
  2707. priv->temperature = temp;
  2708. set_bit(STATUS_TEMPERATURE, &priv->status);
  2709. if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)) &&
  2710. iwl4965_is_temp_calib_needed(priv))
  2711. queue_work(priv->workqueue, &priv->txpower_work);
  2712. }
  2713. static void iwl4965_add_radiotap(struct iwl4965_priv *priv,
  2714. struct sk_buff *skb,
  2715. struct iwl4965_rx_phy_res *rx_start,
  2716. struct ieee80211_rx_status *stats,
  2717. u32 ampdu_status)
  2718. {
  2719. s8 signal = stats->ssi;
  2720. s8 noise = 0;
  2721. int rate = stats->rate_idx;
  2722. u64 tsf = stats->mactime;
  2723. __le16 phy_flags_hw = rx_start->phy_flags;
  2724. struct iwl4965_rt_rx_hdr {
  2725. struct ieee80211_radiotap_header rt_hdr;
  2726. __le64 rt_tsf; /* TSF */
  2727. u8 rt_flags; /* radiotap packet flags */
  2728. u8 rt_rate; /* rate in 500kb/s */
  2729. __le16 rt_channelMHz; /* channel in MHz */
  2730. __le16 rt_chbitmask; /* channel bitfield */
  2731. s8 rt_dbmsignal; /* signal in dBm, kluged to signed */
  2732. s8 rt_dbmnoise;
  2733. u8 rt_antenna; /* antenna number */
  2734. } __attribute__ ((packed)) *iwl4965_rt;
  2735. /* TODO: We won't have enough headroom for HT frames. Fix it later. */
  2736. if (skb_headroom(skb) < sizeof(*iwl4965_rt)) {
  2737. if (net_ratelimit())
  2738. printk(KERN_ERR "not enough headroom [%d] for "
  2739. "radiotap head [%zd]\n",
  2740. skb_headroom(skb), sizeof(*iwl4965_rt));
  2741. return;
  2742. }
  2743. /* put radiotap header in front of 802.11 header and data */
  2744. iwl4965_rt = (void *)skb_push(skb, sizeof(*iwl4965_rt));
  2745. /* initialise radiotap header */
  2746. iwl4965_rt->rt_hdr.it_version = PKTHDR_RADIOTAP_VERSION;
  2747. iwl4965_rt->rt_hdr.it_pad = 0;
  2748. /* total header + data */
  2749. put_unaligned(cpu_to_le16(sizeof(*iwl4965_rt)),
  2750. &iwl4965_rt->rt_hdr.it_len);
  2751. /* Indicate all the fields we add to the radiotap header */
  2752. put_unaligned(cpu_to_le32((1 << IEEE80211_RADIOTAP_TSFT) |
  2753. (1 << IEEE80211_RADIOTAP_FLAGS) |
  2754. (1 << IEEE80211_RADIOTAP_RATE) |
  2755. (1 << IEEE80211_RADIOTAP_CHANNEL) |
  2756. (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) |
  2757. (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE) |
  2758. (1 << IEEE80211_RADIOTAP_ANTENNA)),
  2759. &iwl4965_rt->rt_hdr.it_present);
  2760. /* Zero the flags, we'll add to them as we go */
  2761. iwl4965_rt->rt_flags = 0;
  2762. put_unaligned(cpu_to_le64(tsf), &iwl4965_rt->rt_tsf);
  2763. iwl4965_rt->rt_dbmsignal = signal;
  2764. iwl4965_rt->rt_dbmnoise = noise;
  2765. /* Convert the channel frequency and set the flags */
  2766. put_unaligned(cpu_to_le16(stats->freq), &iwl4965_rt->rt_channelMHz);
  2767. if (!(phy_flags_hw & RX_RES_PHY_FLAGS_BAND_24_MSK))
  2768. put_unaligned(cpu_to_le16(IEEE80211_CHAN_OFDM |
  2769. IEEE80211_CHAN_5GHZ),
  2770. &iwl4965_rt->rt_chbitmask);
  2771. else if (phy_flags_hw & RX_RES_PHY_FLAGS_MOD_CCK_MSK)
  2772. put_unaligned(cpu_to_le16(IEEE80211_CHAN_CCK |
  2773. IEEE80211_CHAN_2GHZ),
  2774. &iwl4965_rt->rt_chbitmask);
  2775. else /* 802.11g */
  2776. put_unaligned(cpu_to_le16(IEEE80211_CHAN_OFDM |
  2777. IEEE80211_CHAN_2GHZ),
  2778. &iwl4965_rt->rt_chbitmask);
  2779. if (rate == -1)
  2780. iwl4965_rt->rt_rate = 0;
  2781. else
  2782. iwl4965_rt->rt_rate = iwl4965_rates[rate].ieee;
  2783. /*
  2784. * "antenna number"
  2785. *
  2786. * It seems that the antenna field in the phy flags value
  2787. * is actually a bitfield. This is undefined by radiotap,
  2788. * it wants an actual antenna number but I always get "7"
  2789. * for most legacy frames I receive indicating that the
  2790. * same frame was received on all three RX chains.
  2791. *
  2792. * I think this field should be removed in favour of a
  2793. * new 802.11n radiotap field "RX chains" that is defined
  2794. * as a bitmask.
  2795. */
  2796. iwl4965_rt->rt_antenna =
  2797. le16_to_cpu(phy_flags_hw & RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4;
  2798. /* set the preamble flag if appropriate */
  2799. if (phy_flags_hw & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK)
  2800. iwl4965_rt->rt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
  2801. stats->flag |= RX_FLAG_RADIOTAP;
  2802. }
  2803. static void iwl4965_handle_data_packet(struct iwl4965_priv *priv, int is_data,
  2804. int include_phy,
  2805. struct iwl4965_rx_mem_buffer *rxb,
  2806. struct ieee80211_rx_status *stats)
  2807. {
  2808. struct iwl4965_rx_packet *pkt = (struct iwl4965_rx_packet *)rxb->skb->data;
  2809. struct iwl4965_rx_phy_res *rx_start = (include_phy) ?
  2810. (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) : NULL;
  2811. struct ieee80211_hdr *hdr;
  2812. u16 len;
  2813. __le32 *rx_end;
  2814. unsigned int skblen;
  2815. u32 ampdu_status;
  2816. if (!include_phy && priv->last_phy_res[0])
  2817. rx_start = (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1];
  2818. if (!rx_start) {
  2819. IWL_ERROR("MPDU frame without a PHY data\n");
  2820. return;
  2821. }
  2822. if (include_phy) {
  2823. hdr = (struct ieee80211_hdr *)((u8 *) & rx_start[1] +
  2824. rx_start->cfg_phy_cnt);
  2825. len = le16_to_cpu(rx_start->byte_count);
  2826. rx_end = (__le32 *) ((u8 *) & pkt->u.raw[0] +
  2827. sizeof(struct iwl4965_rx_phy_res) +
  2828. rx_start->cfg_phy_cnt + len);
  2829. } else {
  2830. struct iwl4965_rx_mpdu_res_start *amsdu =
  2831. (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
  2832. hdr = (struct ieee80211_hdr *)(pkt->u.raw +
  2833. sizeof(struct iwl4965_rx_mpdu_res_start));
  2834. len = le16_to_cpu(amsdu->byte_count);
  2835. rx_start->byte_count = amsdu->byte_count;
  2836. rx_end = (__le32 *) (((u8 *) hdr) + len);
  2837. }
  2838. if (len > priv->hw_setting.max_pkt_size || len < 16) {
  2839. IWL_WARNING("byte count out of range [16,4K] : %d\n", len);
  2840. return;
  2841. }
  2842. ampdu_status = le32_to_cpu(*rx_end);
  2843. skblen = ((u8 *) rx_end - (u8 *) & pkt->u.raw[0]) + sizeof(u32);
  2844. /* start from MAC */
  2845. skb_reserve(rxb->skb, (void *)hdr - (void *)pkt);
  2846. skb_put(rxb->skb, len); /* end where data ends */
  2847. /* We only process data packets if the interface is open */
  2848. if (unlikely(!priv->is_open)) {
  2849. IWL_DEBUG_DROP_LIMIT
  2850. ("Dropping packet while interface is not open.\n");
  2851. return;
  2852. }
  2853. stats->flag = 0;
  2854. hdr = (struct ieee80211_hdr *)rxb->skb->data;
  2855. if (iwl4965_param_hwcrypto)
  2856. iwl4965_set_decrypted_flag(priv, rxb->skb, ampdu_status, stats);
  2857. if (priv->add_radiotap)
  2858. iwl4965_add_radiotap(priv, rxb->skb, rx_start, stats, ampdu_status);
  2859. ieee80211_rx_irqsafe(priv->hw, rxb->skb, stats);
  2860. priv->alloc_rxb_skb--;
  2861. rxb->skb = NULL;
  2862. #ifdef LED
  2863. priv->led_packets += len;
  2864. iwl4965_setup_activity_timer(priv);
  2865. #endif
  2866. }
  2867. /* Calc max signal level (dBm) among 3 possible receivers */
  2868. static int iwl4965_calc_rssi(struct iwl4965_rx_phy_res *rx_resp)
  2869. {
  2870. /* data from PHY/DSP regarding signal strength, etc.,
  2871. * contents are always there, not configurable by host. */
  2872. struct iwl4965_rx_non_cfg_phy *ncphy =
  2873. (struct iwl4965_rx_non_cfg_phy *)rx_resp->non_cfg_phy;
  2874. u32 agc = (le16_to_cpu(ncphy->agc_info) & IWL_AGC_DB_MASK)
  2875. >> IWL_AGC_DB_POS;
  2876. u32 valid_antennae =
  2877. (le16_to_cpu(rx_resp->phy_flags) & RX_PHY_FLAGS_ANTENNAE_MASK)
  2878. >> RX_PHY_FLAGS_ANTENNAE_OFFSET;
  2879. u8 max_rssi = 0;
  2880. u32 i;
  2881. /* Find max rssi among 3 possible receivers.
  2882. * These values are measured by the digital signal processor (DSP).
  2883. * They should stay fairly constant even as the signal strength varies,
  2884. * if the radio's automatic gain control (AGC) is working right.
  2885. * AGC value (see below) will provide the "interesting" info. */
  2886. for (i = 0; i < 3; i++)
  2887. if (valid_antennae & (1 << i))
  2888. max_rssi = max(ncphy->rssi_info[i << 1], max_rssi);
  2889. IWL_DEBUG_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n",
  2890. ncphy->rssi_info[0], ncphy->rssi_info[2], ncphy->rssi_info[4],
  2891. max_rssi, agc);
  2892. /* dBm = max_rssi dB - agc dB - constant.
  2893. * Higher AGC (higher radio gain) means lower signal. */
  2894. return (max_rssi - agc - IWL_RSSI_OFFSET);
  2895. }
  2896. #ifdef CONFIG_IWL4965_HT
  2897. /* Parsed Information Elements */
  2898. struct ieee802_11_elems {
  2899. u8 *ds_params;
  2900. u8 ds_params_len;
  2901. u8 *tim;
  2902. u8 tim_len;
  2903. u8 *ibss_params;
  2904. u8 ibss_params_len;
  2905. u8 *erp_info;
  2906. u8 erp_info_len;
  2907. u8 *ht_cap_param;
  2908. u8 ht_cap_param_len;
  2909. u8 *ht_extra_param;
  2910. u8 ht_extra_param_len;
  2911. };
  2912. static int parse_elems(u8 *start, size_t len, struct ieee802_11_elems *elems)
  2913. {
  2914. size_t left = len;
  2915. u8 *pos = start;
  2916. int unknown = 0;
  2917. memset(elems, 0, sizeof(*elems));
  2918. while (left >= 2) {
  2919. u8 id, elen;
  2920. id = *pos++;
  2921. elen = *pos++;
  2922. left -= 2;
  2923. if (elen > left)
  2924. return -1;
  2925. switch (id) {
  2926. case WLAN_EID_DS_PARAMS:
  2927. elems->ds_params = pos;
  2928. elems->ds_params_len = elen;
  2929. break;
  2930. case WLAN_EID_TIM:
  2931. elems->tim = pos;
  2932. elems->tim_len = elen;
  2933. break;
  2934. case WLAN_EID_IBSS_PARAMS:
  2935. elems->ibss_params = pos;
  2936. elems->ibss_params_len = elen;
  2937. break;
  2938. case WLAN_EID_ERP_INFO:
  2939. elems->erp_info = pos;
  2940. elems->erp_info_len = elen;
  2941. break;
  2942. case WLAN_EID_HT_CAPABILITY:
  2943. elems->ht_cap_param = pos;
  2944. elems->ht_cap_param_len = elen;
  2945. break;
  2946. case WLAN_EID_HT_EXTRA_INFO:
  2947. elems->ht_extra_param = pos;
  2948. elems->ht_extra_param_len = elen;
  2949. break;
  2950. default:
  2951. unknown++;
  2952. break;
  2953. }
  2954. left -= elen;
  2955. pos += elen;
  2956. }
  2957. return 0;
  2958. }
  2959. void iwl4965_init_ht_hw_capab(struct ieee80211_ht_info *ht_info,
  2960. enum ieee80211_band band)
  2961. {
  2962. ht_info->cap = 0;
  2963. memset(ht_info->supp_mcs_set, 0, 16);
  2964. ht_info->ht_supported = 1;
  2965. if (band == IEEE80211_BAND_5GHZ) {
  2966. ht_info->cap |= (u16)IEEE80211_HT_CAP_SUP_WIDTH;
  2967. ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_40;
  2968. ht_info->supp_mcs_set[4] = 0x01;
  2969. }
  2970. ht_info->cap |= (u16)IEEE80211_HT_CAP_GRN_FLD;
  2971. ht_info->cap |= (u16)IEEE80211_HT_CAP_SGI_20;
  2972. ht_info->cap |= (u16)(IEEE80211_HT_CAP_MIMO_PS &
  2973. (IWL_MIMO_PS_NONE << 2));
  2974. if (iwl4965_param_amsdu_size_8K) {
  2975. printk(KERN_DEBUG "iwl4965 in A-MSDU 8K support mode\n");
  2976. ht_info->cap |= (u16)IEEE80211_HT_CAP_MAX_AMSDU;
  2977. }
  2978. ht_info->ampdu_factor = CFG_HT_RX_AMPDU_FACTOR_DEF;
  2979. ht_info->ampdu_density = CFG_HT_MPDU_DENSITY_DEF;
  2980. ht_info->supp_mcs_set[0] = 0xFF;
  2981. ht_info->supp_mcs_set[1] = 0xFF;
  2982. }
  2983. #endif /* CONFIG_IWL4965_HT */
  2984. static void iwl4965_sta_modify_ps_wake(struct iwl4965_priv *priv, int sta_id)
  2985. {
  2986. unsigned long flags;
  2987. spin_lock_irqsave(&priv->sta_lock, flags);
  2988. priv->stations[sta_id].sta.station_flags &= ~STA_FLG_PWR_SAVE_MSK;
  2989. priv->stations[sta_id].sta.station_flags_msk = STA_FLG_PWR_SAVE_MSK;
  2990. priv->stations[sta_id].sta.sta.modify_mask = 0;
  2991. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  2992. spin_unlock_irqrestore(&priv->sta_lock, flags);
  2993. iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
  2994. }
  2995. static void iwl4965_update_ps_mode(struct iwl4965_priv *priv, u16 ps_bit, u8 *addr)
  2996. {
  2997. /* FIXME: need locking over ps_status ??? */
  2998. u8 sta_id = iwl4965_hw_find_station(priv, addr);
  2999. if (sta_id != IWL_INVALID_STATION) {
  3000. u8 sta_awake = priv->stations[sta_id].
  3001. ps_status == STA_PS_STATUS_WAKE;
  3002. if (sta_awake && ps_bit)
  3003. priv->stations[sta_id].ps_status = STA_PS_STATUS_SLEEP;
  3004. else if (!sta_awake && !ps_bit) {
  3005. iwl4965_sta_modify_ps_wake(priv, sta_id);
  3006. priv->stations[sta_id].ps_status = STA_PS_STATUS_WAKE;
  3007. }
  3008. }
  3009. }
  3010. #ifdef CONFIG_IWL4965_DEBUG
  3011. /**
  3012. * iwl4965_dbg_report_frame - dump frame to syslog during debug sessions
  3013. *
  3014. * You may hack this function to show different aspects of received frames,
  3015. * including selective frame dumps.
  3016. * group100 parameter selects whether to show 1 out of 100 good frames.
  3017. *
  3018. * TODO: This was originally written for 3945, need to audit for
  3019. * proper operation with 4965.
  3020. */
  3021. static void iwl4965_dbg_report_frame(struct iwl4965_priv *priv,
  3022. struct iwl4965_rx_packet *pkt,
  3023. struct ieee80211_hdr *header, int group100)
  3024. {
  3025. u32 to_us;
  3026. u32 print_summary = 0;
  3027. u32 print_dump = 0; /* set to 1 to dump all frames' contents */
  3028. u32 hundred = 0;
  3029. u32 dataframe = 0;
  3030. u16 fc;
  3031. u16 seq_ctl;
  3032. u16 channel;
  3033. u16 phy_flags;
  3034. int rate_sym;
  3035. u16 length;
  3036. u16 status;
  3037. u16 bcn_tmr;
  3038. u32 tsf_low;
  3039. u64 tsf;
  3040. u8 rssi;
  3041. u8 agc;
  3042. u16 sig_avg;
  3043. u16 noise_diff;
  3044. struct iwl4965_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt);
  3045. struct iwl4965_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt);
  3046. struct iwl4965_rx_frame_end *rx_end = IWL_RX_END(pkt);
  3047. u8 *data = IWL_RX_DATA(pkt);
  3048. if (likely(!(iwl4965_debug_level & IWL_DL_RX)))
  3049. return;
  3050. /* MAC header */
  3051. fc = le16_to_cpu(header->frame_control);
  3052. seq_ctl = le16_to_cpu(header->seq_ctrl);
  3053. /* metadata */
  3054. channel = le16_to_cpu(rx_hdr->channel);
  3055. phy_flags = le16_to_cpu(rx_hdr->phy_flags);
  3056. rate_sym = rx_hdr->rate;
  3057. length = le16_to_cpu(rx_hdr->len);
  3058. /* end-of-frame status and timestamp */
  3059. status = le32_to_cpu(rx_end->status);
  3060. bcn_tmr = le32_to_cpu(rx_end->beacon_timestamp);
  3061. tsf_low = le64_to_cpu(rx_end->timestamp) & 0x0ffffffff;
  3062. tsf = le64_to_cpu(rx_end->timestamp);
  3063. /* signal statistics */
  3064. rssi = rx_stats->rssi;
  3065. agc = rx_stats->agc;
  3066. sig_avg = le16_to_cpu(rx_stats->sig_avg);
  3067. noise_diff = le16_to_cpu(rx_stats->noise_diff);
  3068. to_us = !compare_ether_addr(header->addr1, priv->mac_addr);
  3069. /* if data frame is to us and all is good,
  3070. * (optionally) print summary for only 1 out of every 100 */
  3071. if (to_us && (fc & ~IEEE80211_FCTL_PROTECTED) ==
  3072. (IEEE80211_FCTL_FROMDS | IEEE80211_FTYPE_DATA)) {
  3073. dataframe = 1;
  3074. if (!group100)
  3075. print_summary = 1; /* print each frame */
  3076. else if (priv->framecnt_to_us < 100) {
  3077. priv->framecnt_to_us++;
  3078. print_summary = 0;
  3079. } else {
  3080. priv->framecnt_to_us = 0;
  3081. print_summary = 1;
  3082. hundred = 1;
  3083. }
  3084. } else {
  3085. /* print summary for all other frames */
  3086. print_summary = 1;
  3087. }
  3088. if (print_summary) {
  3089. char *title;
  3090. int rate_idx;
  3091. u32 bitrate;
  3092. if (hundred)
  3093. title = "100Frames";
  3094. else if (fc & IEEE80211_FCTL_RETRY)
  3095. title = "Retry";
  3096. else if (ieee80211_is_assoc_response(fc))
  3097. title = "AscRsp";
  3098. else if (ieee80211_is_reassoc_response(fc))
  3099. title = "RasRsp";
  3100. else if (ieee80211_is_probe_response(fc)) {
  3101. title = "PrbRsp";
  3102. print_dump = 1; /* dump frame contents */
  3103. } else if (ieee80211_is_beacon(fc)) {
  3104. title = "Beacon";
  3105. print_dump = 1; /* dump frame contents */
  3106. } else if (ieee80211_is_atim(fc))
  3107. title = "ATIM";
  3108. else if (ieee80211_is_auth(fc))
  3109. title = "Auth";
  3110. else if (ieee80211_is_deauth(fc))
  3111. title = "DeAuth";
  3112. else if (ieee80211_is_disassoc(fc))
  3113. title = "DisAssoc";
  3114. else
  3115. title = "Frame";
  3116. rate_idx = iwl4965_hwrate_to_plcp_idx(rate_sym);
  3117. if (unlikely(rate_idx == -1))
  3118. bitrate = 0;
  3119. else
  3120. bitrate = iwl4965_rates[rate_idx].ieee / 2;
  3121. /* print frame summary.
  3122. * MAC addresses show just the last byte (for brevity),
  3123. * but you can hack it to show more, if you'd like to. */
  3124. if (dataframe)
  3125. IWL_DEBUG_RX("%s: mhd=0x%04x, dst=0x%02x, "
  3126. "len=%u, rssi=%d, chnl=%d, rate=%u, \n",
  3127. title, fc, header->addr1[5],
  3128. length, rssi, channel, bitrate);
  3129. else {
  3130. /* src/dst addresses assume managed mode */
  3131. IWL_DEBUG_RX("%s: 0x%04x, dst=0x%02x, "
  3132. "src=0x%02x, rssi=%u, tim=%lu usec, "
  3133. "phy=0x%02x, chnl=%d\n",
  3134. title, fc, header->addr1[5],
  3135. header->addr3[5], rssi,
  3136. tsf_low - priv->scan_start_tsf,
  3137. phy_flags, channel);
  3138. }
  3139. }
  3140. if (print_dump)
  3141. iwl4965_print_hex_dump(IWL_DL_RX, data, length);
  3142. }
  3143. #else
  3144. static inline void iwl4965_dbg_report_frame(struct iwl4965_priv *priv,
  3145. struct iwl4965_rx_packet *pkt,
  3146. struct ieee80211_hdr *header,
  3147. int group100)
  3148. {
  3149. }
  3150. #endif
  3151. #define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6)
  3152. /* Called for REPLY_4965_RX (legacy ABG frames), or
  3153. * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */
  3154. static void iwl4965_rx_reply_rx(struct iwl4965_priv *priv,
  3155. struct iwl4965_rx_mem_buffer *rxb)
  3156. {
  3157. struct ieee80211_hdr *header;
  3158. struct ieee80211_rx_status rx_status;
  3159. struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
  3160. /* Use phy data (Rx signal strength, etc.) contained within
  3161. * this rx packet for legacy frames,
  3162. * or phy data cached from REPLY_RX_PHY_CMD for HT frames. */
  3163. int include_phy = (pkt->hdr.cmd == REPLY_4965_RX);
  3164. struct iwl4965_rx_phy_res *rx_start = (include_phy) ?
  3165. (struct iwl4965_rx_phy_res *)&(pkt->u.raw[0]) :
  3166. (struct iwl4965_rx_phy_res *)&priv->last_phy_res[1];
  3167. __le32 *rx_end;
  3168. unsigned int len = 0;
  3169. u16 fc;
  3170. u8 network_packet;
  3171. rx_status.mactime = le64_to_cpu(rx_start->timestamp);
  3172. rx_status.freq = ieee80211chan2mhz(le16_to_cpu(rx_start->channel));
  3173. rx_status.band = (rx_start->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ?
  3174. IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ;
  3175. rx_status.rate_idx = iwl4965_hwrate_to_plcp_idx(
  3176. le32_to_cpu(rx_start->rate_n_flags));
  3177. if (rx_status.band == IEEE80211_BAND_5GHZ)
  3178. rx_status.rate_idx -= IWL_FIRST_OFDM_RATE;
  3179. rx_status.antenna = 0;
  3180. rx_status.flag = 0;
  3181. if ((unlikely(rx_start->cfg_phy_cnt > 20))) {
  3182. IWL_DEBUG_DROP
  3183. ("dsp size out of range [0,20]: "
  3184. "%d/n", rx_start->cfg_phy_cnt);
  3185. return;
  3186. }
  3187. if (!include_phy) {
  3188. if (priv->last_phy_res[0])
  3189. rx_start = (struct iwl4965_rx_phy_res *)
  3190. &priv->last_phy_res[1];
  3191. else
  3192. rx_start = NULL;
  3193. }
  3194. if (!rx_start) {
  3195. IWL_ERROR("MPDU frame without a PHY data\n");
  3196. return;
  3197. }
  3198. if (include_phy) {
  3199. header = (struct ieee80211_hdr *)((u8 *) & rx_start[1]
  3200. + rx_start->cfg_phy_cnt);
  3201. len = le16_to_cpu(rx_start->byte_count);
  3202. rx_end = (__le32 *)(pkt->u.raw + rx_start->cfg_phy_cnt +
  3203. sizeof(struct iwl4965_rx_phy_res) + len);
  3204. } else {
  3205. struct iwl4965_rx_mpdu_res_start *amsdu =
  3206. (struct iwl4965_rx_mpdu_res_start *)pkt->u.raw;
  3207. header = (void *)(pkt->u.raw +
  3208. sizeof(struct iwl4965_rx_mpdu_res_start));
  3209. len = le16_to_cpu(amsdu->byte_count);
  3210. rx_end = (__le32 *) (pkt->u.raw +
  3211. sizeof(struct iwl4965_rx_mpdu_res_start) + len);
  3212. }
  3213. if (!(*rx_end & RX_RES_STATUS_NO_CRC32_ERROR) ||
  3214. !(*rx_end & RX_RES_STATUS_NO_RXE_OVERFLOW)) {
  3215. IWL_DEBUG_RX("Bad CRC or FIFO: 0x%08X.\n",
  3216. le32_to_cpu(*rx_end));
  3217. return;
  3218. }
  3219. priv->ucode_beacon_time = le32_to_cpu(rx_start->beacon_time_stamp);
  3220. /* Find max signal strength (dBm) among 3 antenna/receiver chains */
  3221. rx_status.ssi = iwl4965_calc_rssi(rx_start);
  3222. /* Meaningful noise values are available only from beacon statistics,
  3223. * which are gathered only when associated, and indicate noise
  3224. * only for the associated network channel ...
  3225. * Ignore these noise values while scanning (other channels) */
  3226. if (iwl4965_is_associated(priv) &&
  3227. !test_bit(STATUS_SCANNING, &priv->status)) {
  3228. rx_status.noise = priv->last_rx_noise;
  3229. rx_status.signal = iwl4965_calc_sig_qual(rx_status.ssi,
  3230. rx_status.noise);
  3231. } else {
  3232. rx_status.noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
  3233. rx_status.signal = iwl4965_calc_sig_qual(rx_status.ssi, 0);
  3234. }
  3235. /* Reset beacon noise level if not associated. */
  3236. if (!iwl4965_is_associated(priv))
  3237. priv->last_rx_noise = IWL_NOISE_MEAS_NOT_AVAILABLE;
  3238. /* Set "1" to report good data frames in groups of 100 */
  3239. /* FIXME: need to optimze the call: */
  3240. iwl4965_dbg_report_frame(priv, pkt, header, 1);
  3241. IWL_DEBUG_STATS_LIMIT("Rssi %d, noise %d, qual %d, TSF %llu\n",
  3242. rx_status.ssi, rx_status.noise, rx_status.signal,
  3243. rx_status.mactime);
  3244. network_packet = iwl4965_is_network_packet(priv, header);
  3245. if (network_packet) {
  3246. priv->last_rx_rssi = rx_status.ssi;
  3247. priv->last_beacon_time = priv->ucode_beacon_time;
  3248. priv->last_tsf = le64_to_cpu(rx_start->timestamp);
  3249. }
  3250. fc = le16_to_cpu(header->frame_control);
  3251. switch (fc & IEEE80211_FCTL_FTYPE) {
  3252. case IEEE80211_FTYPE_MGMT:
  3253. if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
  3254. iwl4965_update_ps_mode(priv, fc & IEEE80211_FCTL_PM,
  3255. header->addr2);
  3256. switch (fc & IEEE80211_FCTL_STYPE) {
  3257. case IEEE80211_STYPE_PROBE_RESP:
  3258. case IEEE80211_STYPE_BEACON:
  3259. if ((priv->iw_mode == IEEE80211_IF_TYPE_STA &&
  3260. !compare_ether_addr(header->addr2, priv->bssid)) ||
  3261. (priv->iw_mode == IEEE80211_IF_TYPE_IBSS &&
  3262. !compare_ether_addr(header->addr3, priv->bssid))) {
  3263. struct ieee80211_mgmt *mgmt =
  3264. (struct ieee80211_mgmt *)header;
  3265. u64 timestamp =
  3266. le64_to_cpu(mgmt->u.beacon.timestamp);
  3267. priv->timestamp0 = timestamp & 0xFFFFFFFF;
  3268. priv->timestamp1 =
  3269. (timestamp >> 32) & 0xFFFFFFFF;
  3270. priv->beacon_int = le16_to_cpu(
  3271. mgmt->u.beacon.beacon_int);
  3272. if (priv->call_post_assoc_from_beacon &&
  3273. (priv->iw_mode == IEEE80211_IF_TYPE_STA)) {
  3274. priv->call_post_assoc_from_beacon = 0;
  3275. queue_work(priv->workqueue,
  3276. &priv->post_associate.work);
  3277. }
  3278. }
  3279. break;
  3280. case IEEE80211_STYPE_ACTION:
  3281. break;
  3282. /*
  3283. * TODO: Use the new callback function from
  3284. * mac80211 instead of sniffing these packets.
  3285. */
  3286. case IEEE80211_STYPE_ASSOC_RESP:
  3287. case IEEE80211_STYPE_REASSOC_RESP:
  3288. if (network_packet) {
  3289. #ifdef CONFIG_IWL4965_HT
  3290. u8 *pos = NULL;
  3291. struct ieee802_11_elems elems;
  3292. #endif /*CONFIG_IWL4965_HT */
  3293. struct ieee80211_mgmt *mgnt =
  3294. (struct ieee80211_mgmt *)header;
  3295. /* We have just associated, give some
  3296. * time for the 4-way handshake if
  3297. * any. Don't start scan too early. */
  3298. priv->next_scan_jiffies = jiffies +
  3299. IWL_DELAY_NEXT_SCAN_AFTER_ASSOC;
  3300. priv->assoc_id = (~((1 << 15) | (1 << 14))
  3301. & le16_to_cpu(mgnt->u.assoc_resp.aid));
  3302. priv->assoc_capability =
  3303. le16_to_cpu(
  3304. mgnt->u.assoc_resp.capab_info);
  3305. #ifdef CONFIG_IWL4965_HT
  3306. pos = mgnt->u.assoc_resp.variable;
  3307. if (!parse_elems(pos,
  3308. len - (pos - (u8 *) mgnt),
  3309. &elems)) {
  3310. if (elems.ht_extra_param &&
  3311. elems.ht_cap_param)
  3312. break;
  3313. }
  3314. #endif /*CONFIG_IWL4965_HT */
  3315. /* assoc_id is 0 no association */
  3316. if (!priv->assoc_id)
  3317. break;
  3318. if (priv->beacon_int)
  3319. queue_work(priv->workqueue,
  3320. &priv->post_associate.work);
  3321. else
  3322. priv->call_post_assoc_from_beacon = 1;
  3323. }
  3324. break;
  3325. case IEEE80211_STYPE_PROBE_REQ:
  3326. if ((priv->iw_mode == IEEE80211_IF_TYPE_IBSS) &&
  3327. !iwl4965_is_associated(priv)) {
  3328. DECLARE_MAC_BUF(mac1);
  3329. DECLARE_MAC_BUF(mac2);
  3330. DECLARE_MAC_BUF(mac3);
  3331. IWL_DEBUG_DROP("Dropping (non network): "
  3332. "%s, %s, %s\n",
  3333. print_mac(mac1, header->addr1),
  3334. print_mac(mac2, header->addr2),
  3335. print_mac(mac3, header->addr3));
  3336. return;
  3337. }
  3338. }
  3339. iwl4965_handle_data_packet(priv, 0, include_phy, rxb, &rx_status);
  3340. break;
  3341. case IEEE80211_FTYPE_CTL:
  3342. #ifdef CONFIG_IWL4965_HT
  3343. switch (fc & IEEE80211_FCTL_STYPE) {
  3344. case IEEE80211_STYPE_BACK_REQ:
  3345. IWL_DEBUG_HT("IEEE80211_STYPE_BACK_REQ arrived\n");
  3346. iwl4965_handle_data_packet(priv, 0, include_phy,
  3347. rxb, &rx_status);
  3348. break;
  3349. default:
  3350. break;
  3351. }
  3352. #endif
  3353. break;
  3354. case IEEE80211_FTYPE_DATA: {
  3355. DECLARE_MAC_BUF(mac1);
  3356. DECLARE_MAC_BUF(mac2);
  3357. DECLARE_MAC_BUF(mac3);
  3358. if (priv->iw_mode == IEEE80211_IF_TYPE_AP)
  3359. iwl4965_update_ps_mode(priv, fc & IEEE80211_FCTL_PM,
  3360. header->addr2);
  3361. if (unlikely(!network_packet))
  3362. IWL_DEBUG_DROP("Dropping (non network): "
  3363. "%s, %s, %s\n",
  3364. print_mac(mac1, header->addr1),
  3365. print_mac(mac2, header->addr2),
  3366. print_mac(mac3, header->addr3));
  3367. else if (unlikely(iwl4965_is_duplicate_packet(priv, header)))
  3368. IWL_DEBUG_DROP("Dropping (dup): %s, %s, %s\n",
  3369. print_mac(mac1, header->addr1),
  3370. print_mac(mac2, header->addr2),
  3371. print_mac(mac3, header->addr3));
  3372. else
  3373. iwl4965_handle_data_packet(priv, 1, include_phy, rxb,
  3374. &rx_status);
  3375. break;
  3376. }
  3377. default:
  3378. break;
  3379. }
  3380. }
  3381. /* Cache phy data (Rx signal strength, etc) for HT frame (REPLY_RX_PHY_CMD).
  3382. * This will be used later in iwl4965_rx_reply_rx() for REPLY_RX_MPDU_CMD. */
  3383. static void iwl4965_rx_reply_rx_phy(struct iwl4965_priv *priv,
  3384. struct iwl4965_rx_mem_buffer *rxb)
  3385. {
  3386. struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
  3387. priv->last_phy_res[0] = 1;
  3388. memcpy(&priv->last_phy_res[1], &(pkt->u.raw[0]),
  3389. sizeof(struct iwl4965_rx_phy_res));
  3390. }
  3391. static void iwl4965_rx_missed_beacon_notif(struct iwl4965_priv *priv,
  3392. struct iwl4965_rx_mem_buffer *rxb)
  3393. {
  3394. #ifdef CONFIG_IWL4965_SENSITIVITY
  3395. struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
  3396. struct iwl4965_missed_beacon_notif *missed_beacon;
  3397. missed_beacon = &pkt->u.missed_beacon;
  3398. if (le32_to_cpu(missed_beacon->consequtive_missed_beacons) > 5) {
  3399. IWL_DEBUG_CALIB("missed bcn cnsq %d totl %d rcd %d expctd %d\n",
  3400. le32_to_cpu(missed_beacon->consequtive_missed_beacons),
  3401. le32_to_cpu(missed_beacon->total_missed_becons),
  3402. le32_to_cpu(missed_beacon->num_recvd_beacons),
  3403. le32_to_cpu(missed_beacon->num_expected_beacons));
  3404. priv->sensitivity_data.state = IWL_SENS_CALIB_NEED_REINIT;
  3405. if (unlikely(!test_bit(STATUS_SCANNING, &priv->status)))
  3406. queue_work(priv->workqueue, &priv->sensitivity_work);
  3407. }
  3408. #endif /*CONFIG_IWL4965_SENSITIVITY*/
  3409. }
  3410. #ifdef CONFIG_IWL4965_HT
  3411. /**
  3412. * iwl4965_sta_modify_enable_tid_tx - Enable Tx for this TID in station table
  3413. */
  3414. static void iwl4965_sta_modify_enable_tid_tx(struct iwl4965_priv *priv,
  3415. int sta_id, int tid)
  3416. {
  3417. unsigned long flags;
  3418. /* Remove "disable" flag, to enable Tx for this TID */
  3419. spin_lock_irqsave(&priv->sta_lock, flags);
  3420. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_TID_DISABLE_TX;
  3421. priv->stations[sta_id].sta.tid_disable_tx &= cpu_to_le16(~(1 << tid));
  3422. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  3423. spin_unlock_irqrestore(&priv->sta_lock, flags);
  3424. iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
  3425. }
  3426. /**
  3427. * iwl4965_tx_status_reply_compressed_ba - Update tx status from block-ack
  3428. *
  3429. * Go through block-ack's bitmap of ACK'd frames, update driver's record of
  3430. * ACK vs. not. This gets sent to mac80211, then to rate scaling algo.
  3431. */
  3432. static int iwl4965_tx_status_reply_compressed_ba(struct iwl4965_priv *priv,
  3433. struct iwl4965_ht_agg *agg,
  3434. struct iwl4965_compressed_ba_resp*
  3435. ba_resp)
  3436. {
  3437. int i, sh, ack;
  3438. u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl);
  3439. u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
  3440. u64 bitmap;
  3441. int successes = 0;
  3442. struct ieee80211_tx_status *tx_status;
  3443. if (unlikely(!agg->wait_for_ba)) {
  3444. IWL_ERROR("Received BA when not expected\n");
  3445. return -EINVAL;
  3446. }
  3447. /* Mark that the expected block-ack response arrived */
  3448. agg->wait_for_ba = 0;
  3449. IWL_DEBUG_TX_REPLY("BA %d %d\n", agg->start_idx, ba_resp->seq_ctl);
  3450. /* Calculate shift to align block-ack bits with our Tx window bits */
  3451. sh = agg->start_idx - SEQ_TO_INDEX(seq_ctl>>4);
  3452. if (sh < 0) /* tbw something is wrong with indices */
  3453. sh += 0x100;
  3454. /* don't use 64-bit values for now */
  3455. bitmap = le64_to_cpu(ba_resp->bitmap) >> sh;
  3456. if (agg->frame_count > (64 - sh)) {
  3457. IWL_DEBUG_TX_REPLY("more frames than bitmap size");
  3458. return -1;
  3459. }
  3460. /* check for success or failure according to the
  3461. * transmitted bitmap and block-ack bitmap */
  3462. bitmap &= agg->bitmap;
  3463. /* For each frame attempted in aggregation,
  3464. * update driver's record of tx frame's status. */
  3465. for (i = 0; i < agg->frame_count ; i++) {
  3466. ack = bitmap & (1 << i);
  3467. successes += !!ack;
  3468. IWL_DEBUG_TX_REPLY("%s ON i=%d idx=%d raw=%d\n",
  3469. ack? "ACK":"NACK", i, (agg->start_idx + i) & 0xff,
  3470. agg->start_idx + i);
  3471. }
  3472. tx_status = &priv->txq[scd_flow].txb[agg->start_idx].status;
  3473. tx_status->flags = IEEE80211_TX_STATUS_ACK;
  3474. tx_status->flags |= IEEE80211_TX_STATUS_AMPDU;
  3475. tx_status->ampdu_ack_map = successes;
  3476. tx_status->ampdu_ack_len = agg->frame_count;
  3477. iwl4965_hwrate_to_tx_control(priv, agg->rate_n_flags,
  3478. &tx_status->control);
  3479. IWL_DEBUG_TX_REPLY("Bitmap %llx\n", bitmap);
  3480. return 0;
  3481. }
  3482. /**
  3483. * iwl4965_tx_queue_stop_scheduler - Stop queue, but keep configuration
  3484. */
  3485. static void iwl4965_tx_queue_stop_scheduler(struct iwl4965_priv *priv,
  3486. u16 txq_id)
  3487. {
  3488. /* Simply stop the queue, but don't change any configuration;
  3489. * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
  3490. iwl4965_write_prph(priv,
  3491. KDR_SCD_QUEUE_STATUS_BITS(txq_id),
  3492. (0 << SCD_QUEUE_STTS_REG_POS_ACTIVE)|
  3493. (1 << SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
  3494. }
  3495. /**
  3496. * txq_id must be greater than IWL_BACK_QUEUE_FIRST_ID
  3497. */
  3498. static int iwl4965_tx_queue_agg_disable(struct iwl4965_priv *priv, u16 txq_id,
  3499. u16 ssn_idx, u8 tx_fifo)
  3500. {
  3501. if (IWL_BACK_QUEUE_FIRST_ID > txq_id) {
  3502. IWL_WARNING("queue number too small: %d, must be > %d\n",
  3503. txq_id, IWL_BACK_QUEUE_FIRST_ID);
  3504. return -EINVAL;
  3505. }
  3506. iwl4965_tx_queue_stop_scheduler(priv, txq_id);
  3507. iwl4965_clear_bits_prph(priv, KDR_SCD_QUEUECHAIN_SEL, (1 << txq_id));
  3508. priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
  3509. priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
  3510. /* supposes that ssn_idx is valid (!= 0xFFF) */
  3511. iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
  3512. iwl4965_clear_bits_prph(priv, KDR_SCD_INTERRUPT_MASK, (1 << txq_id));
  3513. iwl4965_txq_ctx_deactivate(priv, txq_id);
  3514. iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
  3515. return 0;
  3516. }
  3517. int iwl4965_check_empty_hw_queue(struct iwl4965_priv *priv, int sta_id,
  3518. u8 tid, int txq_id)
  3519. {
  3520. struct iwl4965_queue *q = &priv->txq[txq_id].q;
  3521. u8 *addr = priv->stations[sta_id].sta.sta.addr;
  3522. struct iwl4965_tid_data *tid_data = &priv->stations[sta_id].tid[tid];
  3523. switch (priv->stations[sta_id].tid[tid].agg.state) {
  3524. case IWL_EMPTYING_HW_QUEUE_DELBA:
  3525. /* We are reclaiming the last packet of the */
  3526. /* aggregated HW queue */
  3527. if (txq_id == tid_data->agg.txq_id &&
  3528. q->read_ptr == q->write_ptr) {
  3529. u16 ssn = SEQ_TO_SN(tid_data->seq_number);
  3530. int tx_fifo = default_tid_to_tx_fifo[tid];
  3531. IWL_DEBUG_HT("HW queue empty: continue DELBA flow\n");
  3532. iwl4965_tx_queue_agg_disable(priv, txq_id,
  3533. ssn, tx_fifo);
  3534. tid_data->agg.state = IWL_AGG_OFF;
  3535. ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, addr, tid);
  3536. }
  3537. break;
  3538. case IWL_EMPTYING_HW_QUEUE_ADDBA:
  3539. /* We are reclaiming the last packet of the queue */
  3540. if (tid_data->tfds_in_queue == 0) {
  3541. IWL_DEBUG_HT("HW queue empty: continue ADDBA flow\n");
  3542. tid_data->agg.state = IWL_AGG_ON;
  3543. ieee80211_start_tx_ba_cb_irqsafe(priv->hw, addr, tid);
  3544. }
  3545. break;
  3546. }
  3547. return 0;
  3548. }
  3549. /**
  3550. * iwl4965_queue_dec_wrap - Decrement queue index, wrap back to end if needed
  3551. * @index -- current index
  3552. * @n_bd -- total number of entries in queue (s/b power of 2)
  3553. */
  3554. static inline int iwl4965_queue_dec_wrap(int index, int n_bd)
  3555. {
  3556. return (index == 0) ? n_bd - 1 : index - 1;
  3557. }
  3558. /**
  3559. * iwl4965_rx_reply_compressed_ba - Handler for REPLY_COMPRESSED_BA
  3560. *
  3561. * Handles block-acknowledge notification from device, which reports success
  3562. * of frames sent via aggregation.
  3563. */
  3564. static void iwl4965_rx_reply_compressed_ba(struct iwl4965_priv *priv,
  3565. struct iwl4965_rx_mem_buffer *rxb)
  3566. {
  3567. struct iwl4965_rx_packet *pkt = (void *)rxb->skb->data;
  3568. struct iwl4965_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba;
  3569. int index;
  3570. struct iwl4965_tx_queue *txq = NULL;
  3571. struct iwl4965_ht_agg *agg;
  3572. DECLARE_MAC_BUF(mac);
  3573. /* "flow" corresponds to Tx queue */
  3574. u16 scd_flow = le16_to_cpu(ba_resp->scd_flow);
  3575. /* "ssn" is start of block-ack Tx window, corresponds to index
  3576. * (in Tx queue's circular buffer) of first TFD/frame in window */
  3577. u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn);
  3578. if (scd_flow >= ARRAY_SIZE(priv->txq)) {
  3579. IWL_ERROR("BUG_ON scd_flow is bigger than number of queues");
  3580. return;
  3581. }
  3582. txq = &priv->txq[scd_flow];
  3583. agg = &priv->stations[ba_resp->sta_id].tid[ba_resp->tid].agg;
  3584. /* Find index just before block-ack window */
  3585. index = iwl4965_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd);
  3586. /* TODO: Need to get this copy more safely - now good for debug */
  3587. IWL_DEBUG_TX_REPLY("REPLY_COMPRESSED_BA [%d]Received from %s, "
  3588. "sta_id = %d\n",
  3589. agg->wait_for_ba,
  3590. print_mac(mac, (u8*) &ba_resp->sta_addr_lo32),
  3591. ba_resp->sta_id);
  3592. IWL_DEBUG_TX_REPLY("TID = %d, SeqCtl = %d, bitmap = 0x%llx, scd_flow = "
  3593. "%d, scd_ssn = %d\n",
  3594. ba_resp->tid,
  3595. ba_resp->seq_ctl,
  3596. ba_resp->bitmap,
  3597. ba_resp->scd_flow,
  3598. ba_resp->scd_ssn);
  3599. IWL_DEBUG_TX_REPLY("DAT start_idx = %d, bitmap = 0x%llx \n",
  3600. agg->start_idx,
  3601. agg->bitmap);
  3602. /* Update driver's record of ACK vs. not for each frame in window */
  3603. iwl4965_tx_status_reply_compressed_ba(priv, agg, ba_resp);
  3604. /* Release all TFDs before the SSN, i.e. all TFDs in front of
  3605. * block-ack window (we assume that they've been successfully
  3606. * transmitted ... if not, it's too late anyway). */
  3607. if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) {
  3608. int freed = iwl4965_tx_queue_reclaim(priv, scd_flow, index);
  3609. priv->stations[ba_resp->sta_id].
  3610. tid[ba_resp->tid].tfds_in_queue -= freed;
  3611. if (iwl4965_queue_space(&txq->q) > txq->q.low_mark &&
  3612. priv->mac80211_registered &&
  3613. agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)
  3614. ieee80211_wake_queue(priv->hw, scd_flow);
  3615. iwl4965_check_empty_hw_queue(priv, ba_resp->sta_id,
  3616. ba_resp->tid, scd_flow);
  3617. }
  3618. }
  3619. /**
  3620. * iwl4965_tx_queue_set_q2ratid - Map unique receiver/tid combination to a queue
  3621. */
  3622. static int iwl4965_tx_queue_set_q2ratid(struct iwl4965_priv *priv, u16 ra_tid,
  3623. u16 txq_id)
  3624. {
  3625. u32 tbl_dw_addr;
  3626. u32 tbl_dw;
  3627. u16 scd_q2ratid;
  3628. scd_q2ratid = ra_tid & SCD_QUEUE_RA_TID_MAP_RATID_MSK;
  3629. tbl_dw_addr = priv->scd_base_addr +
  3630. SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
  3631. tbl_dw = iwl4965_read_targ_mem(priv, tbl_dw_addr);
  3632. if (txq_id & 0x1)
  3633. tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
  3634. else
  3635. tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
  3636. iwl4965_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
  3637. return 0;
  3638. }
  3639. /**
  3640. * iwl4965_tx_queue_agg_enable - Set up & enable aggregation for selected queue
  3641. *
  3642. * NOTE: txq_id must be greater than IWL_BACK_QUEUE_FIRST_ID,
  3643. * i.e. it must be one of the higher queues used for aggregation
  3644. */
  3645. static int iwl4965_tx_queue_agg_enable(struct iwl4965_priv *priv, int txq_id,
  3646. int tx_fifo, int sta_id, int tid,
  3647. u16 ssn_idx)
  3648. {
  3649. unsigned long flags;
  3650. int rc;
  3651. u16 ra_tid;
  3652. if (IWL_BACK_QUEUE_FIRST_ID > txq_id)
  3653. IWL_WARNING("queue number too small: %d, must be > %d\n",
  3654. txq_id, IWL_BACK_QUEUE_FIRST_ID);
  3655. ra_tid = BUILD_RAxTID(sta_id, tid);
  3656. /* Modify device's station table to Tx this TID */
  3657. iwl4965_sta_modify_enable_tid_tx(priv, sta_id, tid);
  3658. spin_lock_irqsave(&priv->lock, flags);
  3659. rc = iwl4965_grab_nic_access(priv);
  3660. if (rc) {
  3661. spin_unlock_irqrestore(&priv->lock, flags);
  3662. return rc;
  3663. }
  3664. /* Stop this Tx queue before configuring it */
  3665. iwl4965_tx_queue_stop_scheduler(priv, txq_id);
  3666. /* Map receiver-address / traffic-ID to this queue */
  3667. iwl4965_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
  3668. /* Set this queue as a chain-building queue */
  3669. iwl4965_set_bits_prph(priv, KDR_SCD_QUEUECHAIN_SEL, (1 << txq_id));
  3670. /* Place first TFD at index corresponding to start sequence number.
  3671. * Assumes that ssn_idx is valid (!= 0xFFF) */
  3672. priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
  3673. priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
  3674. iwl4965_set_wr_ptrs(priv, txq_id, ssn_idx);
  3675. /* Set up Tx window size and frame limit for this queue */
  3676. iwl4965_write_targ_mem(priv,
  3677. priv->scd_base_addr + SCD_CONTEXT_QUEUE_OFFSET(txq_id),
  3678. (SCD_WIN_SIZE << SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) &
  3679. SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK);
  3680. iwl4965_write_targ_mem(priv, priv->scd_base_addr +
  3681. SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32),
  3682. (SCD_FRAME_LIMIT << SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS)
  3683. & SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK);
  3684. iwl4965_set_bits_prph(priv, KDR_SCD_INTERRUPT_MASK, (1 << txq_id));
  3685. /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
  3686. iwl4965_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
  3687. iwl4965_release_nic_access(priv);
  3688. spin_unlock_irqrestore(&priv->lock, flags);
  3689. return 0;
  3690. }
  3691. #endif /* CONFIG_IWL4965_HT */
  3692. /**
  3693. * iwl4965_add_station - Initialize a station's hardware rate table
  3694. *
  3695. * The uCode's station table contains a table of fallback rates
  3696. * for automatic fallback during transmission.
  3697. *
  3698. * NOTE: This sets up a default set of values. These will be replaced later
  3699. * if the driver's iwl-4965-rs rate scaling algorithm is used, instead of
  3700. * rc80211_simple.
  3701. *
  3702. * NOTE: Run REPLY_ADD_STA command to set up station table entry, before
  3703. * calling this function (which runs REPLY_TX_LINK_QUALITY_CMD,
  3704. * which requires station table entry to exist).
  3705. */
  3706. void iwl4965_add_station(struct iwl4965_priv *priv, const u8 *addr, int is_ap)
  3707. {
  3708. int i, r;
  3709. struct iwl4965_link_quality_cmd link_cmd = {
  3710. .reserved1 = 0,
  3711. };
  3712. u16 rate_flags;
  3713. /* Set up the rate scaling to start at selected rate, fall back
  3714. * all the way down to 1M in IEEE order, and then spin on 1M */
  3715. if (is_ap)
  3716. r = IWL_RATE_54M_INDEX;
  3717. else if (priv->band == IEEE80211_BAND_5GHZ)
  3718. r = IWL_RATE_6M_INDEX;
  3719. else
  3720. r = IWL_RATE_1M_INDEX;
  3721. for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++) {
  3722. rate_flags = 0;
  3723. if (r >= IWL_FIRST_CCK_RATE && r <= IWL_LAST_CCK_RATE)
  3724. rate_flags |= RATE_MCS_CCK_MSK;
  3725. /* Use Tx antenna B only */
  3726. rate_flags |= RATE_MCS_ANT_B_MSK;
  3727. rate_flags &= ~RATE_MCS_ANT_A_MSK;
  3728. link_cmd.rs_table[i].rate_n_flags =
  3729. iwl4965_hw_set_rate_n_flags(iwl4965_rates[r].plcp, rate_flags);
  3730. r = iwl4965_get_prev_ieee_rate(r);
  3731. }
  3732. link_cmd.general_params.single_stream_ant_msk = 2;
  3733. link_cmd.general_params.dual_stream_ant_msk = 3;
  3734. link_cmd.agg_params.agg_dis_start_th = 3;
  3735. link_cmd.agg_params.agg_time_limit = cpu_to_le16(4000);
  3736. /* Update the rate scaling for control frame Tx to AP */
  3737. link_cmd.sta_id = is_ap ? IWL_AP_ID : IWL4965_BROADCAST_ID;
  3738. iwl4965_send_cmd_pdu(priv, REPLY_TX_LINK_QUALITY_CMD, sizeof(link_cmd),
  3739. &link_cmd);
  3740. }
  3741. #ifdef CONFIG_IWL4965_HT
  3742. static u8 iwl4965_is_channel_extension(struct iwl4965_priv *priv,
  3743. enum ieee80211_band band,
  3744. u16 channel, u8 extension_chan_offset)
  3745. {
  3746. const struct iwl4965_channel_info *ch_info;
  3747. ch_info = iwl4965_get_channel_info(priv, band, channel);
  3748. if (!is_channel_valid(ch_info))
  3749. return 0;
  3750. if (extension_chan_offset == IWL_EXT_CHANNEL_OFFSET_NONE)
  3751. return 0;
  3752. if ((ch_info->fat_extension_channel == extension_chan_offset) ||
  3753. (ch_info->fat_extension_channel == HT_IE_EXT_CHANNEL_MAX))
  3754. return 1;
  3755. return 0;
  3756. }
  3757. static u8 iwl4965_is_fat_tx_allowed(struct iwl4965_priv *priv,
  3758. struct ieee80211_ht_info *sta_ht_inf)
  3759. {
  3760. struct iwl_ht_info *iwl_ht_conf = &priv->current_ht_config;
  3761. if ((!iwl_ht_conf->is_ht) ||
  3762. (iwl_ht_conf->supported_chan_width != IWL_CHANNEL_WIDTH_40MHZ) ||
  3763. (iwl_ht_conf->extension_chan_offset == IWL_EXT_CHANNEL_OFFSET_NONE))
  3764. return 0;
  3765. if (sta_ht_inf) {
  3766. if ((!sta_ht_inf->ht_supported) ||
  3767. (!(sta_ht_inf->cap & IEEE80211_HT_CAP_SUP_WIDTH)))
  3768. return 0;
  3769. }
  3770. return (iwl4965_is_channel_extension(priv, priv->band,
  3771. iwl_ht_conf->control_channel,
  3772. iwl_ht_conf->extension_chan_offset));
  3773. }
  3774. void iwl4965_set_rxon_ht(struct iwl4965_priv *priv, struct iwl_ht_info *ht_info)
  3775. {
  3776. struct iwl4965_rxon_cmd *rxon = &priv->staging_rxon;
  3777. u32 val;
  3778. if (!ht_info->is_ht)
  3779. return;
  3780. /* Set up channel bandwidth: 20 MHz only, or 20/40 mixed if fat ok */
  3781. if (iwl4965_is_fat_tx_allowed(priv, NULL))
  3782. rxon->flags |= RXON_FLG_CHANNEL_MODE_MIXED_MSK;
  3783. else
  3784. rxon->flags &= ~(RXON_FLG_CHANNEL_MODE_MIXED_MSK |
  3785. RXON_FLG_CHANNEL_MODE_PURE_40_MSK);
  3786. if (le16_to_cpu(rxon->channel) != ht_info->control_channel) {
  3787. IWL_DEBUG_ASSOC("control diff than current %d %d\n",
  3788. le16_to_cpu(rxon->channel),
  3789. ht_info->control_channel);
  3790. rxon->channel = cpu_to_le16(ht_info->control_channel);
  3791. return;
  3792. }
  3793. /* Note: control channel is opposite of extension channel */
  3794. switch (ht_info->extension_chan_offset) {
  3795. case IWL_EXT_CHANNEL_OFFSET_ABOVE:
  3796. rxon->flags &= ~(RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK);
  3797. break;
  3798. case IWL_EXT_CHANNEL_OFFSET_BELOW:
  3799. rxon->flags |= RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK;
  3800. break;
  3801. case IWL_EXT_CHANNEL_OFFSET_NONE:
  3802. default:
  3803. rxon->flags &= ~RXON_FLG_CHANNEL_MODE_MIXED_MSK;
  3804. break;
  3805. }
  3806. val = ht_info->ht_protection;
  3807. rxon->flags |= cpu_to_le32(val << RXON_FLG_HT_OPERATING_MODE_POS);
  3808. iwl4965_set_rxon_chain(priv);
  3809. IWL_DEBUG_ASSOC("supported HT rate 0x%X %X "
  3810. "rxon flags 0x%X operation mode :0x%X "
  3811. "extension channel offset 0x%x "
  3812. "control chan %d\n",
  3813. ht_info->supp_mcs_set[0], ht_info->supp_mcs_set[1],
  3814. le32_to_cpu(rxon->flags), ht_info->ht_protection,
  3815. ht_info->extension_chan_offset,
  3816. ht_info->control_channel);
  3817. return;
  3818. }
  3819. void iwl4965_set_ht_add_station(struct iwl4965_priv *priv, u8 index,
  3820. struct ieee80211_ht_info *sta_ht_inf)
  3821. {
  3822. __le32 sta_flags;
  3823. u8 mimo_ps_mode;
  3824. if (!sta_ht_inf || !sta_ht_inf->ht_supported)
  3825. goto done;
  3826. mimo_ps_mode = (sta_ht_inf->cap & IEEE80211_HT_CAP_MIMO_PS) >> 2;
  3827. sta_flags = priv->stations[index].sta.station_flags;
  3828. sta_flags &= ~(STA_FLG_RTS_MIMO_PROT_MSK | STA_FLG_MIMO_DIS_MSK);
  3829. switch (mimo_ps_mode) {
  3830. case WLAN_HT_CAP_MIMO_PS_STATIC:
  3831. sta_flags |= STA_FLG_MIMO_DIS_MSK;
  3832. break;
  3833. case WLAN_HT_CAP_MIMO_PS_DYNAMIC:
  3834. sta_flags |= STA_FLG_RTS_MIMO_PROT_MSK;
  3835. break;
  3836. case WLAN_HT_CAP_MIMO_PS_DISABLED:
  3837. break;
  3838. default:
  3839. IWL_WARNING("Invalid MIMO PS mode %d", mimo_ps_mode);
  3840. break;
  3841. }
  3842. sta_flags |= cpu_to_le32(
  3843. (u32)sta_ht_inf->ampdu_factor << STA_FLG_MAX_AGG_SIZE_POS);
  3844. sta_flags |= cpu_to_le32(
  3845. (u32)sta_ht_inf->ampdu_density << STA_FLG_AGG_MPDU_DENSITY_POS);
  3846. if (iwl4965_is_fat_tx_allowed(priv, sta_ht_inf))
  3847. sta_flags |= STA_FLG_FAT_EN_MSK;
  3848. else
  3849. sta_flags &= ~STA_FLG_FAT_EN_MSK;
  3850. priv->stations[index].sta.station_flags = sta_flags;
  3851. done:
  3852. return;
  3853. }
  3854. static void iwl4965_sta_modify_add_ba_tid(struct iwl4965_priv *priv,
  3855. int sta_id, int tid, u16 ssn)
  3856. {
  3857. unsigned long flags;
  3858. spin_lock_irqsave(&priv->sta_lock, flags);
  3859. priv->stations[sta_id].sta.station_flags_msk = 0;
  3860. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_ADDBA_TID_MSK;
  3861. priv->stations[sta_id].sta.add_immediate_ba_tid = (u8)tid;
  3862. priv->stations[sta_id].sta.add_immediate_ba_ssn = cpu_to_le16(ssn);
  3863. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  3864. spin_unlock_irqrestore(&priv->sta_lock, flags);
  3865. iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
  3866. }
  3867. static void iwl4965_sta_modify_del_ba_tid(struct iwl4965_priv *priv,
  3868. int sta_id, int tid)
  3869. {
  3870. unsigned long flags;
  3871. spin_lock_irqsave(&priv->sta_lock, flags);
  3872. priv->stations[sta_id].sta.station_flags_msk = 0;
  3873. priv->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_DELBA_TID_MSK;
  3874. priv->stations[sta_id].sta.remove_immediate_ba_tid = (u8)tid;
  3875. priv->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK;
  3876. spin_unlock_irqrestore(&priv->sta_lock, flags);
  3877. iwl4965_send_add_station(priv, &priv->stations[sta_id].sta, CMD_ASYNC);
  3878. }
  3879. /*
  3880. * Find first available (lowest unused) Tx Queue, mark it "active".
  3881. * Called only when finding queue for aggregation.
  3882. * Should never return anything < 7, because they should already
  3883. * be in use as EDCA AC (0-3), Command (4), HCCA (5, 6).
  3884. */
  3885. static int iwl4965_txq_ctx_activate_free(struct iwl4965_priv *priv)
  3886. {
  3887. int txq_id;
  3888. for (txq_id = 0; txq_id < priv->hw_setting.max_txq_num; txq_id++)
  3889. if (!test_and_set_bit(txq_id, &priv->txq_ctx_active_msk))
  3890. return txq_id;
  3891. return -1;
  3892. }
  3893. static int iwl4965_mac_ht_tx_agg_start(struct ieee80211_hw *hw, const u8 *da,
  3894. u16 tid, u16 *start_seq_num)
  3895. {
  3896. struct iwl4965_priv *priv = hw->priv;
  3897. int sta_id;
  3898. int tx_fifo;
  3899. int txq_id;
  3900. int ssn = -1;
  3901. int rc = 0;
  3902. unsigned long flags;
  3903. struct iwl4965_tid_data *tid_data;
  3904. DECLARE_MAC_BUF(mac);
  3905. if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
  3906. tx_fifo = default_tid_to_tx_fifo[tid];
  3907. else
  3908. return -EINVAL;
  3909. IWL_WARNING("%s on da = %s tid = %d\n",
  3910. __func__, print_mac(mac, da), tid);
  3911. sta_id = iwl4965_hw_find_station(priv, da);
  3912. if (sta_id == IWL_INVALID_STATION)
  3913. return -ENXIO;
  3914. if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_OFF) {
  3915. IWL_ERROR("Start AGG when state is not IWL_AGG_OFF !\n");
  3916. return -ENXIO;
  3917. }
  3918. txq_id = iwl4965_txq_ctx_activate_free(priv);
  3919. if (txq_id == -1)
  3920. return -ENXIO;
  3921. spin_lock_irqsave(&priv->sta_lock, flags);
  3922. tid_data = &priv->stations[sta_id].tid[tid];
  3923. ssn = SEQ_TO_SN(tid_data->seq_number);
  3924. tid_data->agg.txq_id = txq_id;
  3925. spin_unlock_irqrestore(&priv->sta_lock, flags);
  3926. *start_seq_num = ssn;
  3927. rc = iwl4965_tx_queue_agg_enable(priv, txq_id, tx_fifo,
  3928. sta_id, tid, ssn);
  3929. if (rc)
  3930. return rc;
  3931. rc = 0;
  3932. if (tid_data->tfds_in_queue == 0) {
  3933. printk(KERN_ERR "HW queue is empty\n");
  3934. tid_data->agg.state = IWL_AGG_ON;
  3935. ieee80211_start_tx_ba_cb_irqsafe(hw, da, tid);
  3936. } else {
  3937. IWL_DEBUG_HT("HW queue is NOT empty: %d packets in HW queue\n",
  3938. tid_data->tfds_in_queue);
  3939. tid_data->agg.state = IWL_EMPTYING_HW_QUEUE_ADDBA;
  3940. }
  3941. return rc;
  3942. }
  3943. static int iwl4965_mac_ht_tx_agg_stop(struct ieee80211_hw *hw, const u8 *da,
  3944. u16 tid)
  3945. {
  3946. struct iwl4965_priv *priv = hw->priv;
  3947. int tx_fifo_id, txq_id, sta_id, ssn = -1;
  3948. struct iwl4965_tid_data *tid_data;
  3949. int rc, write_ptr, read_ptr;
  3950. unsigned long flags;
  3951. DECLARE_MAC_BUF(mac);
  3952. if (!da) {
  3953. IWL_ERROR("da = NULL\n");
  3954. return -EINVAL;
  3955. }
  3956. if (likely(tid < ARRAY_SIZE(default_tid_to_tx_fifo)))
  3957. tx_fifo_id = default_tid_to_tx_fifo[tid];
  3958. else
  3959. return -EINVAL;
  3960. sta_id = iwl4965_hw_find_station(priv, da);
  3961. if (sta_id == IWL_INVALID_STATION)
  3962. return -ENXIO;
  3963. if (priv->stations[sta_id].tid[tid].agg.state != IWL_AGG_ON)
  3964. IWL_WARNING("Stopping AGG while state not IWL_AGG_ON\n");
  3965. tid_data = &priv->stations[sta_id].tid[tid];
  3966. ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4;
  3967. txq_id = tid_data->agg.txq_id;
  3968. write_ptr = priv->txq[txq_id].q.write_ptr;
  3969. read_ptr = priv->txq[txq_id].q.read_ptr;
  3970. /* The queue is not empty */
  3971. if (write_ptr != read_ptr) {
  3972. IWL_DEBUG_HT("Stopping a non empty AGG HW QUEUE\n");
  3973. priv->stations[sta_id].tid[tid].agg.state =
  3974. IWL_EMPTYING_HW_QUEUE_DELBA;
  3975. return 0;
  3976. }
  3977. IWL_DEBUG_HT("HW queue empty\n");;
  3978. priv->stations[sta_id].tid[tid].agg.state = IWL_AGG_OFF;
  3979. spin_lock_irqsave(&priv->lock, flags);
  3980. rc = iwl4965_grab_nic_access(priv);
  3981. if (rc) {
  3982. spin_unlock_irqrestore(&priv->lock, flags);
  3983. return rc;
  3984. }
  3985. rc = iwl4965_tx_queue_agg_disable(priv, txq_id, ssn, tx_fifo_id);
  3986. iwl4965_release_nic_access(priv);
  3987. spin_unlock_irqrestore(&priv->lock, flags);
  3988. if (rc)
  3989. return rc;
  3990. ieee80211_stop_tx_ba_cb_irqsafe(priv->hw, da, tid);
  3991. IWL_DEBUG_INFO("iwl4965_mac_ht_tx_agg_stop on da=%s tid=%d\n",
  3992. print_mac(mac, da), tid);
  3993. return 0;
  3994. }
  3995. int iwl4965_mac_ampdu_action(struct ieee80211_hw *hw,
  3996. enum ieee80211_ampdu_mlme_action action,
  3997. const u8 *addr, u16 tid, u16 *ssn)
  3998. {
  3999. struct iwl4965_priv *priv = hw->priv;
  4000. int sta_id;
  4001. DECLARE_MAC_BUF(mac);
  4002. IWL_DEBUG_HT("A-MPDU action on da=%s tid=%d ",
  4003. print_mac(mac, addr), tid);
  4004. sta_id = iwl4965_hw_find_station(priv, addr);
  4005. switch (action) {
  4006. case IEEE80211_AMPDU_RX_START:
  4007. IWL_DEBUG_HT("start Rx\n");
  4008. iwl4965_sta_modify_add_ba_tid(priv, sta_id, tid, *ssn);
  4009. break;
  4010. case IEEE80211_AMPDU_RX_STOP:
  4011. IWL_DEBUG_HT("stop Rx\n");
  4012. iwl4965_sta_modify_del_ba_tid(priv, sta_id, tid);
  4013. break;
  4014. case IEEE80211_AMPDU_TX_START:
  4015. IWL_DEBUG_HT("start Tx\n");
  4016. return iwl4965_mac_ht_tx_agg_start(hw, addr, tid, ssn);
  4017. case IEEE80211_AMPDU_TX_STOP:
  4018. IWL_DEBUG_HT("stop Tx\n");
  4019. return iwl4965_mac_ht_tx_agg_stop(hw, addr, tid);
  4020. default:
  4021. IWL_DEBUG_HT("unknown\n");
  4022. return -EINVAL;
  4023. break;
  4024. }
  4025. return 0;
  4026. }
  4027. #endif /* CONFIG_IWL4965_HT */
  4028. /* Set up 4965-specific Rx frame reply handlers */
  4029. void iwl4965_hw_rx_handler_setup(struct iwl4965_priv *priv)
  4030. {
  4031. /* Legacy Rx frames */
  4032. priv->rx_handlers[REPLY_4965_RX] = iwl4965_rx_reply_rx;
  4033. /* High-throughput (HT) Rx frames */
  4034. priv->rx_handlers[REPLY_RX_PHY_CMD] = iwl4965_rx_reply_rx_phy;
  4035. priv->rx_handlers[REPLY_RX_MPDU_CMD] = iwl4965_rx_reply_rx;
  4036. priv->rx_handlers[MISSED_BEACONS_NOTIFICATION] =
  4037. iwl4965_rx_missed_beacon_notif;
  4038. #ifdef CONFIG_IWL4965_HT
  4039. priv->rx_handlers[REPLY_COMPRESSED_BA] = iwl4965_rx_reply_compressed_ba;
  4040. #endif /* CONFIG_IWL4965_HT */
  4041. }
  4042. void iwl4965_hw_setup_deferred_work(struct iwl4965_priv *priv)
  4043. {
  4044. INIT_WORK(&priv->txpower_work, iwl4965_bg_txpower_work);
  4045. INIT_WORK(&priv->statistics_work, iwl4965_bg_statistics_work);
  4046. #ifdef CONFIG_IWL4965_SENSITIVITY
  4047. INIT_WORK(&priv->sensitivity_work, iwl4965_bg_sensitivity_work);
  4048. #endif
  4049. init_timer(&priv->statistics_periodic);
  4050. priv->statistics_periodic.data = (unsigned long)priv;
  4051. priv->statistics_periodic.function = iwl4965_bg_statistics_periodic;
  4052. }
  4053. void iwl4965_hw_cancel_deferred_work(struct iwl4965_priv *priv)
  4054. {
  4055. del_timer_sync(&priv->statistics_periodic);
  4056. cancel_delayed_work(&priv->init_alive_start);
  4057. }
  4058. struct pci_device_id iwl4965_hw_card_ids[] = {
  4059. {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x4229)},
  4060. {PCI_DEVICE(PCI_VENDOR_ID_INTEL, 0x4230)},
  4061. {0}
  4062. };
  4063. /*
  4064. * The device's EEPROM semaphore prevents conflicts between driver and uCode
  4065. * when accessing the EEPROM; each access is a series of pulses to/from the
  4066. * EEPROM chip, not a single event, so even reads could conflict if they
  4067. * weren't arbitrated by the semaphore.
  4068. */
  4069. int iwl4965_eeprom_acquire_semaphore(struct iwl4965_priv *priv)
  4070. {
  4071. u16 count;
  4072. int rc;
  4073. for (count = 0; count < EEPROM_SEM_RETRY_LIMIT; count++) {
  4074. /* Request semaphore */
  4075. iwl4965_set_bit(priv, CSR_HW_IF_CONFIG_REG,
  4076. CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM);
  4077. /* See if we got it */
  4078. rc = iwl4965_poll_bit(priv, CSR_HW_IF_CONFIG_REG,
  4079. CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM,
  4080. CSR_HW_IF_CONFIG_REG_BIT_EEPROM_OWN_SEM,
  4081. EEPROM_SEM_TIMEOUT);
  4082. if (rc >= 0) {
  4083. IWL_DEBUG_IO("Acquired semaphore after %d tries.\n",
  4084. count+1);
  4085. return rc;
  4086. }
  4087. }
  4088. return rc;
  4089. }
  4090. MODULE_DEVICE_TABLE(pci, iwl4965_hw_card_ids);