mc13783-private.h 14 KB

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  1. /*
  2. * Copyright 2009 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
  3. *
  4. * Initial development of this code was funded by
  5. * Phytec Messtechnik GmbH, http://www.phytec.de
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20. */
  21. #ifndef __LINUX_MFD_MC13783_PRIV_H
  22. #define __LINUX_MFD_MC13783_PRIV_H
  23. #include <linux/platform_device.h>
  24. #include <linux/mfd/mc13783.h>
  25. #include <linux/workqueue.h>
  26. #include <linux/mutex.h>
  27. struct mc13783_irq {
  28. void (*handler)(int, void *);
  29. void *data;
  30. };
  31. #define MC13783_NUM_IRQ 2
  32. #define MC13783_IRQ_TS 0
  33. #define MC13783_IRQ_REGULATOR 1
  34. #define MC13783_ADC_MODE_TS 1
  35. #define MC13783_ADC_MODE_SINGLE_CHAN 2
  36. #define MC13783_ADC_MODE_MULT_CHAN 3
  37. struct mc13783 {
  38. int revision;
  39. struct device *dev;
  40. struct spi_device *spi_device;
  41. int (*read_dev)(void *data, char reg, int count, u32 *dst);
  42. int (*write_dev)(void *data, char reg, int count, const u32 *src);
  43. struct mutex io_lock;
  44. void *io_data;
  45. int irq;
  46. unsigned int flags;
  47. struct mc13783_irq irq_handler[MC13783_NUM_IRQ];
  48. struct work_struct work;
  49. struct completion adc_done;
  50. unsigned int ts_active;
  51. struct mutex adc_conv_lock;
  52. struct mc13783_regulator_init_data *regulators;
  53. int num_regulators;
  54. };
  55. int mc13783_reg_read(struct mc13783 *, int reg_num, u32 *);
  56. int mc13783_reg_write(struct mc13783 *, int, u32);
  57. int mc13783_set_bits(struct mc13783 *, int, u32, u32);
  58. int mc13783_free_irq(struct mc13783 *mc13783, int irq);
  59. int mc13783_register_irq(struct mc13783 *mc13783, int irq,
  60. void (*handler) (int, void *), void *data);
  61. #define MC13783_REG_INTERRUPT_STATUS_0 0
  62. #define MC13783_REG_INTERRUPT_MASK_0 1
  63. #define MC13783_REG_INTERRUPT_SENSE_0 2
  64. #define MC13783_REG_INTERRUPT_STATUS_1 3
  65. #define MC13783_REG_INTERRUPT_MASK_1 4
  66. #define MC13783_REG_INTERRUPT_SENSE_1 5
  67. #define MC13783_REG_POWER_UP_MODE_SENSE 6
  68. #define MC13783_REG_REVISION 7
  69. #define MC13783_REG_SEMAPHORE 8
  70. #define MC13783_REG_ARBITRATION_PERIPHERAL_AUDIO 9
  71. #define MC13783_REG_ARBITRATION_SWITCHERS 10
  72. #define MC13783_REG_ARBITRATION_REGULATORS_0 11
  73. #define MC13783_REG_ARBITRATION_REGULATORS_1 12
  74. #define MC13783_REG_POWER_CONTROL_0 13
  75. #define MC13783_REG_POWER_CONTROL_1 14
  76. #define MC13783_REG_POWER_CONTROL_2 15
  77. #define MC13783_REG_REGEN_ASSIGNMENT 16
  78. #define MC13783_REG_CONTROL_SPARE 17
  79. #define MC13783_REG_MEMORY_A 18
  80. #define MC13783_REG_MEMORY_B 19
  81. #define MC13783_REG_RTC_TIME 20
  82. #define MC13783_REG_RTC_ALARM 21
  83. #define MC13783_REG_RTC_DAY 22
  84. #define MC13783_REG_RTC_DAY_ALARM 23
  85. #define MC13783_REG_SWITCHERS_0 24
  86. #define MC13783_REG_SWITCHERS_1 25
  87. #define MC13783_REG_SWITCHERS_2 26
  88. #define MC13783_REG_SWITCHERS_3 27
  89. #define MC13783_REG_SWITCHERS_4 28
  90. #define MC13783_REG_SWITCHERS_5 29
  91. #define MC13783_REG_REGULATOR_SETTING_0 30
  92. #define MC13783_REG_REGULATOR_SETTING_1 31
  93. #define MC13783_REG_REGULATOR_MODE_0 32
  94. #define MC13783_REG_REGULATOR_MODE_1 33
  95. #define MC13783_REG_POWER_MISCELLANEOUS 34
  96. #define MC13783_REG_POWER_SPARE 35
  97. #define MC13783_REG_AUDIO_RX_0 36
  98. #define MC13783_REG_AUDIO_RX_1 37
  99. #define MC13783_REG_AUDIO_TX 38
  100. #define MC13783_REG_AUDIO_SSI_NETWORK 39
  101. #define MC13783_REG_AUDIO_CODEC 40
  102. #define MC13783_REG_AUDIO_STEREO_DAC 41
  103. #define MC13783_REG_AUDIO_SPARE 42
  104. #define MC13783_REG_ADC_0 43
  105. #define MC13783_REG_ADC_1 44
  106. #define MC13783_REG_ADC_2 45
  107. #define MC13783_REG_ADC_3 46
  108. #define MC13783_REG_ADC_4 47
  109. #define MC13783_REG_CHARGER 48
  110. #define MC13783_REG_USB 49
  111. #define MC13783_REG_CHARGE_USB_SPARE 50
  112. #define MC13783_REG_LED_CONTROL_0 51
  113. #define MC13783_REG_LED_CONTROL_1 52
  114. #define MC13783_REG_LED_CONTROL_2 53
  115. #define MC13783_REG_LED_CONTROL_3 54
  116. #define MC13783_REG_LED_CONTROL_4 55
  117. #define MC13783_REG_LED_CONTROL_5 56
  118. #define MC13783_REG_SPARE 57
  119. #define MC13783_REG_TRIM_0 58
  120. #define MC13783_REG_TRIM_1 59
  121. #define MC13783_REG_TEST_0 60
  122. #define MC13783_REG_TEST_1 61
  123. #define MC13783_REG_TEST_2 62
  124. #define MC13783_REG_TEST_3 63
  125. #define MC13783_REG_NB 64
  126. /*
  127. * Interrupt Status
  128. */
  129. #define MC13783_INT_STAT_ADCDONEI (1 << 0)
  130. #define MC13783_INT_STAT_ADCBISDONEI (1 << 1)
  131. #define MC13783_INT_STAT_TSI (1 << 2)
  132. #define MC13783_INT_STAT_WHIGHI (1 << 3)
  133. #define MC13783_INT_STAT_WLOWI (1 << 4)
  134. #define MC13783_INT_STAT_CHGDETI (1 << 6)
  135. #define MC13783_INT_STAT_CHGOVI (1 << 7)
  136. #define MC13783_INT_STAT_CHGREVI (1 << 8)
  137. #define MC13783_INT_STAT_CHGSHORTI (1 << 9)
  138. #define MC13783_INT_STAT_CCCVI (1 << 10)
  139. #define MC13783_INT_STAT_CHGCURRI (1 << 11)
  140. #define MC13783_INT_STAT_BPONI (1 << 12)
  141. #define MC13783_INT_STAT_LOBATLI (1 << 13)
  142. #define MC13783_INT_STAT_LOBATHI (1 << 14)
  143. #define MC13783_INT_STAT_UDPI (1 << 15)
  144. #define MC13783_INT_STAT_USBI (1 << 16)
  145. #define MC13783_INT_STAT_IDI (1 << 19)
  146. #define MC13783_INT_STAT_Unused (1 << 20)
  147. #define MC13783_INT_STAT_SE1I (1 << 21)
  148. #define MC13783_INT_STAT_CKDETI (1 << 22)
  149. #define MC13783_INT_STAT_UDMI (1 << 23)
  150. /*
  151. * Interrupt Mask
  152. */
  153. #define MC13783_INT_MASK_ADCDONEM (1 << 0)
  154. #define MC13783_INT_MASK_ADCBISDONEM (1 << 1)
  155. #define MC13783_INT_MASK_TSM (1 << 2)
  156. #define MC13783_INT_MASK_WHIGHM (1 << 3)
  157. #define MC13783_INT_MASK_WLOWM (1 << 4)
  158. #define MC13783_INT_MASK_CHGDETM (1 << 6)
  159. #define MC13783_INT_MASK_CHGOVM (1 << 7)
  160. #define MC13783_INT_MASK_CHGREVM (1 << 8)
  161. #define MC13783_INT_MASK_CHGSHORTM (1 << 9)
  162. #define MC13783_INT_MASK_CCCVM (1 << 10)
  163. #define MC13783_INT_MASK_CHGCURRM (1 << 11)
  164. #define MC13783_INT_MASK_BPONM (1 << 12)
  165. #define MC13783_INT_MASK_LOBATLM (1 << 13)
  166. #define MC13783_INT_MASK_LOBATHM (1 << 14)
  167. #define MC13783_INT_MASK_UDPM (1 << 15)
  168. #define MC13783_INT_MASK_USBM (1 << 16)
  169. #define MC13783_INT_MASK_IDM (1 << 19)
  170. #define MC13783_INT_MASK_SE1M (1 << 21)
  171. #define MC13783_INT_MASK_CKDETM (1 << 22)
  172. /*
  173. * Reg Regulator Mode 0
  174. */
  175. #define MC13783_REGCTRL_VAUDIO_EN (1 << 0)
  176. #define MC13783_REGCTRL_VAUDIO_STBY (1 << 1)
  177. #define MC13783_REGCTRL_VAUDIO_MODE (1 << 2)
  178. #define MC13783_REGCTRL_VIOHI_EN (1 << 3)
  179. #define MC13783_REGCTRL_VIOHI_STBY (1 << 4)
  180. #define MC13783_REGCTRL_VIOHI_MODE (1 << 5)
  181. #define MC13783_REGCTRL_VIOLO_EN (1 << 6)
  182. #define MC13783_REGCTRL_VIOLO_STBY (1 << 7)
  183. #define MC13783_REGCTRL_VIOLO_MODE (1 << 8)
  184. #define MC13783_REGCTRL_VDIG_EN (1 << 9)
  185. #define MC13783_REGCTRL_VDIG_STBY (1 << 10)
  186. #define MC13783_REGCTRL_VDIG_MODE (1 << 11)
  187. #define MC13783_REGCTRL_VGEN_EN (1 << 12)
  188. #define MC13783_REGCTRL_VGEN_STBY (1 << 13)
  189. #define MC13783_REGCTRL_VGEN_MODE (1 << 14)
  190. #define MC13783_REGCTRL_VRFDIG_EN (1 << 15)
  191. #define MC13783_REGCTRL_VRFDIG_STBY (1 << 16)
  192. #define MC13783_REGCTRL_VRFDIG_MODE (1 << 17)
  193. #define MC13783_REGCTRL_VRFREF_EN (1 << 18)
  194. #define MC13783_REGCTRL_VRFREF_STBY (1 << 19)
  195. #define MC13783_REGCTRL_VRFREF_MODE (1 << 20)
  196. #define MC13783_REGCTRL_VRFCP_EN (1 << 21)
  197. #define MC13783_REGCTRL_VRFCP_STBY (1 << 22)
  198. #define MC13783_REGCTRL_VRFCP_MODE (1 << 23)
  199. /*
  200. * Reg Regulator Mode 1
  201. */
  202. #define MC13783_REGCTRL_VSIM_EN (1 << 0)
  203. #define MC13783_REGCTRL_VSIM_STBY (1 << 1)
  204. #define MC13783_REGCTRL_VSIM_MODE (1 << 2)
  205. #define MC13783_REGCTRL_VESIM_EN (1 << 3)
  206. #define MC13783_REGCTRL_VESIM_STBY (1 << 4)
  207. #define MC13783_REGCTRL_VESIM_MODE (1 << 5)
  208. #define MC13783_REGCTRL_VCAM_EN (1 << 6)
  209. #define MC13783_REGCTRL_VCAM_STBY (1 << 7)
  210. #define MC13783_REGCTRL_VCAM_MODE (1 << 8)
  211. #define MC13783_REGCTRL_VRFBG_EN (1 << 9)
  212. #define MC13783_REGCTRL_VRFBG_STBY (1 << 10)
  213. #define MC13783_REGCTRL_VVIB_EN (1 << 11)
  214. #define MC13783_REGCTRL_VRF1_EN (1 << 12)
  215. #define MC13783_REGCTRL_VRF1_STBY (1 << 13)
  216. #define MC13783_REGCTRL_VRF1_MODE (1 << 14)
  217. #define MC13783_REGCTRL_VRF2_EN (1 << 15)
  218. #define MC13783_REGCTRL_VRF2_STBY (1 << 16)
  219. #define MC13783_REGCTRL_VRF2_MODE (1 << 17)
  220. #define MC13783_REGCTRL_VMMC1_EN (1 << 18)
  221. #define MC13783_REGCTRL_VMMC1_STBY (1 << 19)
  222. #define MC13783_REGCTRL_VMMC1_MODE (1 << 20)
  223. #define MC13783_REGCTRL_VMMC2_EN (1 << 21)
  224. #define MC13783_REGCTRL_VMMC2_STBY (1 << 22)
  225. #define MC13783_REGCTRL_VMMC2_MODE (1 << 23)
  226. /*
  227. * Reg Regulator Misc.
  228. */
  229. #define MC13783_REGCTRL_GPO1_EN (1 << 6)
  230. #define MC13783_REGCTRL_GPO2_EN (1 << 8)
  231. #define MC13783_REGCTRL_GPO3_EN (1 << 10)
  232. #define MC13783_REGCTRL_GPO4_EN (1 << 12)
  233. #define MC13783_REGCTRL_VIBPINCTRL (1 << 14)
  234. /*
  235. * Reg Switcher 4
  236. */
  237. #define MC13783_SWCTRL_SW1A_MODE (1 << 0)
  238. #define MC13783_SWCTRL_SW1A_STBY_MODE (1 << 2)
  239. #define MC13783_SWCTRL_SW1A_DVS_SPEED (1 << 6)
  240. #define MC13783_SWCTRL_SW1A_PANIC_MODE (1 << 8)
  241. #define MC13783_SWCTRL_SW1A_SOFTSTART (1 << 9)
  242. #define MC13783_SWCTRL_SW1B_MODE (1 << 10)
  243. #define MC13783_SWCTRL_SW1B_STBY_MODE (1 << 12)
  244. #define MC13783_SWCTRL_SW1B_DVS_SPEED (1 << 14)
  245. #define MC13783_SWCTRL_SW1B_PANIC_MODE (1 << 16)
  246. #define MC13783_SWCTRL_SW1B_SOFTSTART (1 << 17)
  247. #define MC13783_SWCTRL_PLL_EN (1 << 18)
  248. #define MC13783_SWCTRL_PLL_FACTOR (1 << 19)
  249. /*
  250. * Reg Switcher 5
  251. */
  252. #define MC13783_SWCTRL_SW2A_MODE (1 << 0)
  253. #define MC13783_SWCTRL_SW2A_STBY_MODE (1 << 2)
  254. #define MC13783_SWCTRL_SW2A_DVS_SPEED (1 << 6)
  255. #define MC13783_SWCTRL_SW2A_PANIC_MODE (1 << 8)
  256. #define MC13783_SWCTRL_SW2A_SOFTSTART (1 << 9)
  257. #define MC13783_SWCTRL_SW2B_MODE (1 << 10)
  258. #define MC13783_SWCTRL_SW2B_STBY_MODE (1 << 12)
  259. #define MC13783_SWCTRL_SW2B_DVS_SPEED (1 << 14)
  260. #define MC13783_SWCTRL_SW2B_PANIC_MODE (1 << 16)
  261. #define MC13783_SWCTRL_SW2B_SOFTSTART (1 << 17)
  262. #define MC13783_SWSET_SW3 (1 << 18)
  263. #define MC13783_SWCTRL_SW3_EN (1 << 20)
  264. #define MC13783_SWCTRL_SW3_STBY (1 << 21)
  265. #define MC13783_SWCTRL_SW3_MODE (1 << 22)
  266. /*
  267. * ADC/Touch
  268. */
  269. #define MC13783_ADC0_LICELLCON (1 << 0)
  270. #define MC13783_ADC0_CHRGICON (1 << 1)
  271. #define MC13783_ADC0_BATICON (1 << 2)
  272. #define MC13783_ADC0_RTHEN (1 << 3)
  273. #define MC13783_ADC0_DTHEN (1 << 4)
  274. #define MC13783_ADC0_UIDEN (1 << 5)
  275. #define MC13783_ADC0_ADOUTEN (1 << 6)
  276. #define MC13783_ADC0_ADOUTPER (1 << 7)
  277. #define MC13783_ADC0_ADREFEN (1 << 10)
  278. #define MC13783_ADC0_ADREFMODE (1 << 11)
  279. #define MC13783_ADC0_TSMOD0 (1 << 12)
  280. #define MC13783_ADC0_TSMOD1 (1 << 13)
  281. #define MC13783_ADC0_TSMOD2 (1 << 14)
  282. #define MC13783_ADC0_CHRGRAWDIV (1 << 15)
  283. #define MC13783_ADC0_ADINC1 (1 << 16)
  284. #define MC13783_ADC0_ADINC2 (1 << 17)
  285. #define MC13783_ADC0_WCOMP (1 << 18)
  286. #define MC13783_ADC0_ADCBIS0 (1 << 23)
  287. #define MC13783_ADC1_ADEN (1 << 0)
  288. #define MC13783_ADC1_RAND (1 << 1)
  289. #define MC13783_ADC1_ADSEL (1 << 3)
  290. #define MC13783_ADC1_TRIGMASK (1 << 4)
  291. #define MC13783_ADC1_ADA10 (1 << 5)
  292. #define MC13783_ADC1_ADA11 (1 << 6)
  293. #define MC13783_ADC1_ADA12 (1 << 7)
  294. #define MC13783_ADC1_ADA20 (1 << 8)
  295. #define MC13783_ADC1_ADA21 (1 << 9)
  296. #define MC13783_ADC1_ADA22 (1 << 10)
  297. #define MC13783_ADC1_ATO0 (1 << 11)
  298. #define MC13783_ADC1_ATO1 (1 << 12)
  299. #define MC13783_ADC1_ATO2 (1 << 13)
  300. #define MC13783_ADC1_ATO3 (1 << 14)
  301. #define MC13783_ADC1_ATO4 (1 << 15)
  302. #define MC13783_ADC1_ATO5 (1 << 16)
  303. #define MC13783_ADC1_ATO6 (1 << 17)
  304. #define MC13783_ADC1_ATO7 (1 << 18)
  305. #define MC13783_ADC1_ATOX (1 << 19)
  306. #define MC13783_ADC1_ASC (1 << 20)
  307. #define MC13783_ADC1_ADTRIGIGN (1 << 21)
  308. #define MC13783_ADC1_ADONESHOT (1 << 22)
  309. #define MC13783_ADC1_ADCBIS1 (1 << 23)
  310. #define MC13783_ADC1_CHAN0_SHIFT 5
  311. #define MC13783_ADC1_CHAN1_SHIFT 8
  312. #define MC13783_ADC2_ADD10 (1 << 2)
  313. #define MC13783_ADC2_ADD11 (1 << 3)
  314. #define MC13783_ADC2_ADD12 (1 << 4)
  315. #define MC13783_ADC2_ADD13 (1 << 5)
  316. #define MC13783_ADC2_ADD14 (1 << 6)
  317. #define MC13783_ADC2_ADD15 (1 << 7)
  318. #define MC13783_ADC2_ADD16 (1 << 8)
  319. #define MC13783_ADC2_ADD17 (1 << 9)
  320. #define MC13783_ADC2_ADD18 (1 << 10)
  321. #define MC13783_ADC2_ADD19 (1 << 11)
  322. #define MC13783_ADC2_ADD20 (1 << 14)
  323. #define MC13783_ADC2_ADD21 (1 << 15)
  324. #define MC13783_ADC2_ADD22 (1 << 16)
  325. #define MC13783_ADC2_ADD23 (1 << 17)
  326. #define MC13783_ADC2_ADD24 (1 << 18)
  327. #define MC13783_ADC2_ADD25 (1 << 19)
  328. #define MC13783_ADC2_ADD26 (1 << 20)
  329. #define MC13783_ADC2_ADD27 (1 << 21)
  330. #define MC13783_ADC2_ADD28 (1 << 22)
  331. #define MC13783_ADC2_ADD29 (1 << 23)
  332. #define MC13783_ADC3_WHIGH0 (1 << 0)
  333. #define MC13783_ADC3_WHIGH1 (1 << 1)
  334. #define MC13783_ADC3_WHIGH2 (1 << 2)
  335. #define MC13783_ADC3_WHIGH3 (1 << 3)
  336. #define MC13783_ADC3_WHIGH4 (1 << 4)
  337. #define MC13783_ADC3_WHIGH5 (1 << 5)
  338. #define MC13783_ADC3_ICID0 (1 << 6)
  339. #define MC13783_ADC3_ICID1 (1 << 7)
  340. #define MC13783_ADC3_ICID2 (1 << 8)
  341. #define MC13783_ADC3_WLOW0 (1 << 9)
  342. #define MC13783_ADC3_WLOW1 (1 << 10)
  343. #define MC13783_ADC3_WLOW2 (1 << 11)
  344. #define MC13783_ADC3_WLOW3 (1 << 12)
  345. #define MC13783_ADC3_WLOW4 (1 << 13)
  346. #define MC13783_ADC3_WLOW5 (1 << 14)
  347. #define MC13783_ADC3_ADCBIS2 (1 << 23)
  348. #define MC13783_ADC4_ADDBIS10 (1 << 2)
  349. #define MC13783_ADC4_ADDBIS11 (1 << 3)
  350. #define MC13783_ADC4_ADDBIS12 (1 << 4)
  351. #define MC13783_ADC4_ADDBIS13 (1 << 5)
  352. #define MC13783_ADC4_ADDBIS14 (1 << 6)
  353. #define MC13783_ADC4_ADDBIS15 (1 << 7)
  354. #define MC13783_ADC4_ADDBIS16 (1 << 8)
  355. #define MC13783_ADC4_ADDBIS17 (1 << 9)
  356. #define MC13783_ADC4_ADDBIS18 (1 << 10)
  357. #define MC13783_ADC4_ADDBIS19 (1 << 11)
  358. #define MC13783_ADC4_ADDBIS20 (1 << 14)
  359. #define MC13783_ADC4_ADDBIS21 (1 << 15)
  360. #define MC13783_ADC4_ADDBIS22 (1 << 16)
  361. #define MC13783_ADC4_ADDBIS23 (1 << 17)
  362. #define MC13783_ADC4_ADDBIS24 (1 << 18)
  363. #define MC13783_ADC4_ADDBIS25 (1 << 19)
  364. #define MC13783_ADC4_ADDBIS26 (1 << 20)
  365. #define MC13783_ADC4_ADDBIS27 (1 << 21)
  366. #define MC13783_ADC4_ADDBIS28 (1 << 22)
  367. #define MC13783_ADC4_ADDBIS29 (1 << 23)
  368. #endif /* __LINUX_MFD_MC13783_PRIV_H */