cx23885-cards.c 29 KB

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  1. /*
  2. * Driver for the Conexant CX23885 PCIe bridge
  3. *
  4. * Copyright (c) 2006 Steven Toth <stoth@linuxtv.org>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. *
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20. */
  21. #include <linux/init.h>
  22. #include <linux/module.h>
  23. #include <linux/pci.h>
  24. #include <linux/delay.h>
  25. #include <media/cx25840.h>
  26. #include "cx23885.h"
  27. #include "tuner-xc2028.h"
  28. #include "netup-init.h"
  29. #include "cx23888-ir.h"
  30. /* ------------------------------------------------------------------ */
  31. /* board config info */
  32. struct cx23885_board cx23885_boards[] = {
  33. [CX23885_BOARD_UNKNOWN] = {
  34. .name = "UNKNOWN/GENERIC",
  35. /* Ensure safe default for unknown boards */
  36. .clk_freq = 0,
  37. .input = {{
  38. .type = CX23885_VMUX_COMPOSITE1,
  39. .vmux = 0,
  40. }, {
  41. .type = CX23885_VMUX_COMPOSITE2,
  42. .vmux = 1,
  43. }, {
  44. .type = CX23885_VMUX_COMPOSITE3,
  45. .vmux = 2,
  46. }, {
  47. .type = CX23885_VMUX_COMPOSITE4,
  48. .vmux = 3,
  49. } },
  50. },
  51. [CX23885_BOARD_HAUPPAUGE_HVR1800lp] = {
  52. .name = "Hauppauge WinTV-HVR1800lp",
  53. .portc = CX23885_MPEG_DVB,
  54. .input = {{
  55. .type = CX23885_VMUX_TELEVISION,
  56. .vmux = 0,
  57. .gpio0 = 0xff00,
  58. }, {
  59. .type = CX23885_VMUX_DEBUG,
  60. .vmux = 0,
  61. .gpio0 = 0xff01,
  62. }, {
  63. .type = CX23885_VMUX_COMPOSITE1,
  64. .vmux = 1,
  65. .gpio0 = 0xff02,
  66. }, {
  67. .type = CX23885_VMUX_SVIDEO,
  68. .vmux = 2,
  69. .gpio0 = 0xff02,
  70. } },
  71. },
  72. [CX23885_BOARD_HAUPPAUGE_HVR1800] = {
  73. .name = "Hauppauge WinTV-HVR1800",
  74. .porta = CX23885_ANALOG_VIDEO,
  75. .portb = CX23885_MPEG_ENCODER,
  76. .portc = CX23885_MPEG_DVB,
  77. .tuner_type = TUNER_PHILIPS_TDA8290,
  78. .tuner_addr = 0x42, /* 0x84 >> 1 */
  79. .input = {{
  80. .type = CX23885_VMUX_TELEVISION,
  81. .vmux = CX25840_VIN7_CH3 |
  82. CX25840_VIN5_CH2 |
  83. CX25840_VIN2_CH1,
  84. .gpio0 = 0,
  85. }, {
  86. .type = CX23885_VMUX_COMPOSITE1,
  87. .vmux = CX25840_VIN7_CH3 |
  88. CX25840_VIN4_CH2 |
  89. CX25840_VIN6_CH1,
  90. .gpio0 = 0,
  91. }, {
  92. .type = CX23885_VMUX_SVIDEO,
  93. .vmux = CX25840_VIN7_CH3 |
  94. CX25840_VIN4_CH2 |
  95. CX25840_VIN8_CH1 |
  96. CX25840_SVIDEO_ON,
  97. .gpio0 = 0,
  98. } },
  99. },
  100. [CX23885_BOARD_HAUPPAUGE_HVR1250] = {
  101. .name = "Hauppauge WinTV-HVR1250",
  102. .portc = CX23885_MPEG_DVB,
  103. .input = {{
  104. .type = CX23885_VMUX_TELEVISION,
  105. .vmux = 0,
  106. .gpio0 = 0xff00,
  107. }, {
  108. .type = CX23885_VMUX_DEBUG,
  109. .vmux = 0,
  110. .gpio0 = 0xff01,
  111. }, {
  112. .type = CX23885_VMUX_COMPOSITE1,
  113. .vmux = 1,
  114. .gpio0 = 0xff02,
  115. }, {
  116. .type = CX23885_VMUX_SVIDEO,
  117. .vmux = 2,
  118. .gpio0 = 0xff02,
  119. } },
  120. },
  121. [CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP] = {
  122. .name = "DViCO FusionHDTV5 Express",
  123. .portb = CX23885_MPEG_DVB,
  124. },
  125. [CX23885_BOARD_HAUPPAUGE_HVR1500Q] = {
  126. .name = "Hauppauge WinTV-HVR1500Q",
  127. .portc = CX23885_MPEG_DVB,
  128. },
  129. [CX23885_BOARD_HAUPPAUGE_HVR1500] = {
  130. .name = "Hauppauge WinTV-HVR1500",
  131. .portc = CX23885_MPEG_DVB,
  132. },
  133. [CX23885_BOARD_HAUPPAUGE_HVR1200] = {
  134. .name = "Hauppauge WinTV-HVR1200",
  135. .portc = CX23885_MPEG_DVB,
  136. },
  137. [CX23885_BOARD_HAUPPAUGE_HVR1700] = {
  138. .name = "Hauppauge WinTV-HVR1700",
  139. .portc = CX23885_MPEG_DVB,
  140. },
  141. [CX23885_BOARD_HAUPPAUGE_HVR1400] = {
  142. .name = "Hauppauge WinTV-HVR1400",
  143. .portc = CX23885_MPEG_DVB,
  144. },
  145. [CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP] = {
  146. .name = "DViCO FusionHDTV7 Dual Express",
  147. .portb = CX23885_MPEG_DVB,
  148. .portc = CX23885_MPEG_DVB,
  149. },
  150. [CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP] = {
  151. .name = "DViCO FusionHDTV DVB-T Dual Express",
  152. .portb = CX23885_MPEG_DVB,
  153. .portc = CX23885_MPEG_DVB,
  154. },
  155. [CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H] = {
  156. .name = "Leadtek Winfast PxDVR3200 H",
  157. .portc = CX23885_MPEG_DVB,
  158. },
  159. [CX23885_BOARD_COMPRO_VIDEOMATE_E650F] = {
  160. .name = "Compro VideoMate E650F",
  161. .portc = CX23885_MPEG_DVB,
  162. },
  163. [CX23885_BOARD_TBS_6920] = {
  164. .name = "TurboSight TBS 6920",
  165. .portb = CX23885_MPEG_DVB,
  166. },
  167. [CX23885_BOARD_TEVII_S470] = {
  168. .name = "TeVii S470",
  169. .portb = CX23885_MPEG_DVB,
  170. },
  171. [CX23885_BOARD_DVBWORLD_2005] = {
  172. .name = "DVBWorld DVB-S2 2005",
  173. .portb = CX23885_MPEG_DVB,
  174. },
  175. [CX23885_BOARD_NETUP_DUAL_DVBS2_CI] = {
  176. .cimax = 1,
  177. .name = "NetUP Dual DVB-S2 CI",
  178. .portb = CX23885_MPEG_DVB,
  179. .portc = CX23885_MPEG_DVB,
  180. },
  181. [CX23885_BOARD_HAUPPAUGE_HVR1270] = {
  182. .name = "Hauppauge WinTV-HVR1270",
  183. .portc = CX23885_MPEG_DVB,
  184. },
  185. [CX23885_BOARD_HAUPPAUGE_HVR1275] = {
  186. .name = "Hauppauge WinTV-HVR1275",
  187. .portc = CX23885_MPEG_DVB,
  188. },
  189. [CX23885_BOARD_HAUPPAUGE_HVR1255] = {
  190. .name = "Hauppauge WinTV-HVR1255",
  191. .portc = CX23885_MPEG_DVB,
  192. },
  193. [CX23885_BOARD_HAUPPAUGE_HVR1210] = {
  194. .name = "Hauppauge WinTV-HVR1210",
  195. .portc = CX23885_MPEG_DVB,
  196. },
  197. [CX23885_BOARD_MYGICA_X8506] = {
  198. .name = "Mygica X8506 DMB-TH",
  199. .tuner_type = TUNER_XC5000,
  200. .tuner_addr = 0x61,
  201. .porta = CX23885_ANALOG_VIDEO,
  202. .portb = CX23885_MPEG_DVB,
  203. .input = {
  204. {
  205. .type = CX23885_VMUX_TELEVISION,
  206. .vmux = CX25840_COMPOSITE2,
  207. },
  208. {
  209. .type = CX23885_VMUX_COMPOSITE1,
  210. .vmux = CX25840_COMPOSITE8,
  211. },
  212. {
  213. .type = CX23885_VMUX_SVIDEO,
  214. .vmux = CX25840_SVIDEO_LUMA3 |
  215. CX25840_SVIDEO_CHROMA4,
  216. },
  217. {
  218. .type = CX23885_VMUX_COMPONENT,
  219. .vmux = CX25840_COMPONENT_ON |
  220. CX25840_VIN1_CH1 |
  221. CX25840_VIN6_CH2 |
  222. CX25840_VIN7_CH3,
  223. },
  224. },
  225. },
  226. [CX23885_BOARD_MAGICPRO_PROHDTVE2] = {
  227. .name = "Magic-Pro ProHDTV Extreme 2",
  228. .tuner_type = TUNER_XC5000,
  229. .tuner_addr = 0x61,
  230. .porta = CX23885_ANALOG_VIDEO,
  231. .portb = CX23885_MPEG_DVB,
  232. .input = {
  233. {
  234. .type = CX23885_VMUX_TELEVISION,
  235. .vmux = CX25840_COMPOSITE2,
  236. },
  237. {
  238. .type = CX23885_VMUX_COMPOSITE1,
  239. .vmux = CX25840_COMPOSITE8,
  240. },
  241. {
  242. .type = CX23885_VMUX_SVIDEO,
  243. .vmux = CX25840_SVIDEO_LUMA3 |
  244. CX25840_SVIDEO_CHROMA4,
  245. },
  246. {
  247. .type = CX23885_VMUX_COMPONENT,
  248. .vmux = CX25840_COMPONENT_ON |
  249. CX25840_VIN1_CH1 |
  250. CX25840_VIN6_CH2 |
  251. CX25840_VIN7_CH3,
  252. },
  253. },
  254. },
  255. [CX23885_BOARD_HAUPPAUGE_HVR1850] = {
  256. .name = "Hauppauge WinTV-HVR1850",
  257. .portb = CX23885_MPEG_ENCODER,
  258. .portc = CX23885_MPEG_DVB,
  259. },
  260. [CX23885_BOARD_COMPRO_VIDEOMATE_E800] = {
  261. .name = "Compro VideoMate E800",
  262. .portc = CX23885_MPEG_DVB,
  263. },
  264. };
  265. const unsigned int cx23885_bcount = ARRAY_SIZE(cx23885_boards);
  266. /* ------------------------------------------------------------------ */
  267. /* PCI subsystem IDs */
  268. struct cx23885_subid cx23885_subids[] = {
  269. {
  270. .subvendor = 0x0070,
  271. .subdevice = 0x3400,
  272. .card = CX23885_BOARD_UNKNOWN,
  273. }, {
  274. .subvendor = 0x0070,
  275. .subdevice = 0x7600,
  276. .card = CX23885_BOARD_HAUPPAUGE_HVR1800lp,
  277. }, {
  278. .subvendor = 0x0070,
  279. .subdevice = 0x7800,
  280. .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
  281. }, {
  282. .subvendor = 0x0070,
  283. .subdevice = 0x7801,
  284. .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
  285. }, {
  286. .subvendor = 0x0070,
  287. .subdevice = 0x7809,
  288. .card = CX23885_BOARD_HAUPPAUGE_HVR1800,
  289. }, {
  290. .subvendor = 0x0070,
  291. .subdevice = 0x7911,
  292. .card = CX23885_BOARD_HAUPPAUGE_HVR1250,
  293. }, {
  294. .subvendor = 0x18ac,
  295. .subdevice = 0xd500,
  296. .card = CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP,
  297. }, {
  298. .subvendor = 0x0070,
  299. .subdevice = 0x7790,
  300. .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q,
  301. }, {
  302. .subvendor = 0x0070,
  303. .subdevice = 0x7797,
  304. .card = CX23885_BOARD_HAUPPAUGE_HVR1500Q,
  305. }, {
  306. .subvendor = 0x0070,
  307. .subdevice = 0x7710,
  308. .card = CX23885_BOARD_HAUPPAUGE_HVR1500,
  309. }, {
  310. .subvendor = 0x0070,
  311. .subdevice = 0x7717,
  312. .card = CX23885_BOARD_HAUPPAUGE_HVR1500,
  313. }, {
  314. .subvendor = 0x0070,
  315. .subdevice = 0x71d1,
  316. .card = CX23885_BOARD_HAUPPAUGE_HVR1200,
  317. }, {
  318. .subvendor = 0x0070,
  319. .subdevice = 0x71d3,
  320. .card = CX23885_BOARD_HAUPPAUGE_HVR1200,
  321. }, {
  322. .subvendor = 0x0070,
  323. .subdevice = 0x8101,
  324. .card = CX23885_BOARD_HAUPPAUGE_HVR1700,
  325. }, {
  326. .subvendor = 0x0070,
  327. .subdevice = 0x8010,
  328. .card = CX23885_BOARD_HAUPPAUGE_HVR1400,
  329. }, {
  330. .subvendor = 0x18ac,
  331. .subdevice = 0xd618,
  332. .card = CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP,
  333. }, {
  334. .subvendor = 0x18ac,
  335. .subdevice = 0xdb78,
  336. .card = CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP,
  337. }, {
  338. .subvendor = 0x107d,
  339. .subdevice = 0x6681,
  340. .card = CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H,
  341. }, {
  342. .subvendor = 0x185b,
  343. .subdevice = 0xe800,
  344. .card = CX23885_BOARD_COMPRO_VIDEOMATE_E650F,
  345. }, {
  346. .subvendor = 0x6920,
  347. .subdevice = 0x8888,
  348. .card = CX23885_BOARD_TBS_6920,
  349. }, {
  350. .subvendor = 0xd470,
  351. .subdevice = 0x9022,
  352. .card = CX23885_BOARD_TEVII_S470,
  353. }, {
  354. .subvendor = 0x0001,
  355. .subdevice = 0x2005,
  356. .card = CX23885_BOARD_DVBWORLD_2005,
  357. }, {
  358. .subvendor = 0x1b55,
  359. .subdevice = 0x2a2c,
  360. .card = CX23885_BOARD_NETUP_DUAL_DVBS2_CI,
  361. }, {
  362. .subvendor = 0x0070,
  363. .subdevice = 0x2211,
  364. .card = CX23885_BOARD_HAUPPAUGE_HVR1270,
  365. }, {
  366. .subvendor = 0x0070,
  367. .subdevice = 0x2215,
  368. .card = CX23885_BOARD_HAUPPAUGE_HVR1275,
  369. }, {
  370. .subvendor = 0x0070,
  371. .subdevice = 0x2251,
  372. .card = CX23885_BOARD_HAUPPAUGE_HVR1255,
  373. }, {
  374. .subvendor = 0x0070,
  375. .subdevice = 0x2291,
  376. .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
  377. }, {
  378. .subvendor = 0x0070,
  379. .subdevice = 0x2295,
  380. .card = CX23885_BOARD_HAUPPAUGE_HVR1210,
  381. }, {
  382. .subvendor = 0x14f1,
  383. .subdevice = 0x8651,
  384. .card = CX23885_BOARD_MYGICA_X8506,
  385. }, {
  386. .subvendor = 0x14f1,
  387. .subdevice = 0x8657,
  388. .card = CX23885_BOARD_MAGICPRO_PROHDTVE2,
  389. }, {
  390. .subvendor = 0x0070,
  391. .subdevice = 0x8541,
  392. .card = CX23885_BOARD_HAUPPAUGE_HVR1850,
  393. }, {
  394. .subvendor = 0x1858,
  395. .subdevice = 0xe800,
  396. .card = CX23885_BOARD_COMPRO_VIDEOMATE_E800,
  397. },
  398. };
  399. const unsigned int cx23885_idcount = ARRAY_SIZE(cx23885_subids);
  400. void cx23885_card_list(struct cx23885_dev *dev)
  401. {
  402. int i;
  403. if (0 == dev->pci->subsystem_vendor &&
  404. 0 == dev->pci->subsystem_device) {
  405. printk(KERN_INFO
  406. "%s: Board has no valid PCIe Subsystem ID and can't\n"
  407. "%s: be autodetected. Pass card=<n> insmod option\n"
  408. "%s: to workaround that. Redirect complaints to the\n"
  409. "%s: vendor of the TV card. Best regards,\n"
  410. "%s: -- tux\n",
  411. dev->name, dev->name, dev->name, dev->name, dev->name);
  412. } else {
  413. printk(KERN_INFO
  414. "%s: Your board isn't known (yet) to the driver.\n"
  415. "%s: Try to pick one of the existing card configs via\n"
  416. "%s: card=<n> insmod option. Updating to the latest\n"
  417. "%s: version might help as well.\n",
  418. dev->name, dev->name, dev->name, dev->name);
  419. }
  420. printk(KERN_INFO "%s: Here is a list of valid choices for the card=<n> insmod option:\n",
  421. dev->name);
  422. for (i = 0; i < cx23885_bcount; i++)
  423. printk(KERN_INFO "%s: card=%d -> %s\n",
  424. dev->name, i, cx23885_boards[i].name);
  425. }
  426. static void hauppauge_eeprom(struct cx23885_dev *dev, u8 *eeprom_data)
  427. {
  428. struct tveeprom tv;
  429. tveeprom_hauppauge_analog(&dev->i2c_bus[0].i2c_client, &tv,
  430. eeprom_data);
  431. /* Make sure we support the board model */
  432. switch (tv.model) {
  433. case 22001:
  434. /* WinTV-HVR1270 (PCIe, Retail, half height)
  435. * ATSC/QAM and basic analog, IR Blast */
  436. case 22009:
  437. /* WinTV-HVR1210 (PCIe, Retail, half height)
  438. * DVB-T and basic analog, IR Blast */
  439. case 22011:
  440. /* WinTV-HVR1270 (PCIe, Retail, half height)
  441. * ATSC/QAM and basic analog, IR Recv */
  442. case 22019:
  443. /* WinTV-HVR1210 (PCIe, Retail, half height)
  444. * DVB-T and basic analog, IR Recv */
  445. case 22021:
  446. /* WinTV-HVR1275 (PCIe, Retail, half height)
  447. * ATSC/QAM and basic analog, IR Recv */
  448. case 22029:
  449. /* WinTV-HVR1210 (PCIe, Retail, half height)
  450. * DVB-T and basic analog, IR Recv */
  451. case 22101:
  452. /* WinTV-HVR1270 (PCIe, Retail, full height)
  453. * ATSC/QAM and basic analog, IR Blast */
  454. case 22109:
  455. /* WinTV-HVR1210 (PCIe, Retail, full height)
  456. * DVB-T and basic analog, IR Blast */
  457. case 22111:
  458. /* WinTV-HVR1270 (PCIe, Retail, full height)
  459. * ATSC/QAM and basic analog, IR Recv */
  460. case 22119:
  461. /* WinTV-HVR1210 (PCIe, Retail, full height)
  462. * DVB-T and basic analog, IR Recv */
  463. case 22121:
  464. /* WinTV-HVR1275 (PCIe, Retail, full height)
  465. * ATSC/QAM and basic analog, IR Recv */
  466. case 22129:
  467. /* WinTV-HVR1210 (PCIe, Retail, full height)
  468. * DVB-T and basic analog, IR Recv */
  469. case 71009:
  470. /* WinTV-HVR1200 (PCIe, Retail, full height)
  471. * DVB-T and basic analog */
  472. case 71359:
  473. /* WinTV-HVR1200 (PCIe, OEM, half height)
  474. * DVB-T and basic analog */
  475. case 71439:
  476. /* WinTV-HVR1200 (PCIe, OEM, half height)
  477. * DVB-T and basic analog */
  478. case 71449:
  479. /* WinTV-HVR1200 (PCIe, OEM, full height)
  480. * DVB-T and basic analog */
  481. case 71939:
  482. /* WinTV-HVR1200 (PCIe, OEM, half height)
  483. * DVB-T and basic analog */
  484. case 71949:
  485. /* WinTV-HVR1200 (PCIe, OEM, full height)
  486. * DVB-T and basic analog */
  487. case 71959:
  488. /* WinTV-HVR1200 (PCIe, OEM, full height)
  489. * DVB-T and basic analog */
  490. case 71979:
  491. /* WinTV-HVR1200 (PCIe, OEM, half height)
  492. * DVB-T and basic analog */
  493. case 71999:
  494. /* WinTV-HVR1200 (PCIe, OEM, full height)
  495. * DVB-T and basic analog */
  496. case 76601:
  497. /* WinTV-HVR1800lp (PCIe, Retail, No IR, Dual
  498. channel ATSC and MPEG2 HW Encoder */
  499. case 77001:
  500. /* WinTV-HVR1500 (Express Card, OEM, No IR, ATSC
  501. and Basic analog */
  502. case 77011:
  503. /* WinTV-HVR1500 (Express Card, Retail, No IR, ATSC
  504. and Basic analog */
  505. case 77041:
  506. /* WinTV-HVR1500Q (Express Card, OEM, No IR, ATSC/QAM
  507. and Basic analog */
  508. case 77051:
  509. /* WinTV-HVR1500Q (Express Card, Retail, No IR, ATSC/QAM
  510. and Basic analog */
  511. case 78011:
  512. /* WinTV-HVR1800 (PCIe, Retail, 3.5mm in, IR, No FM,
  513. Dual channel ATSC and MPEG2 HW Encoder */
  514. case 78501:
  515. /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM,
  516. Dual channel ATSC and MPEG2 HW Encoder */
  517. case 78521:
  518. /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, FM,
  519. Dual channel ATSC and MPEG2 HW Encoder */
  520. case 78531:
  521. /* WinTV-HVR1800 (PCIe, OEM, RCA in, No IR, No FM,
  522. Dual channel ATSC and MPEG2 HW Encoder */
  523. case 78631:
  524. /* WinTV-HVR1800 (PCIe, OEM, No IR, No FM,
  525. Dual channel ATSC and MPEG2 HW Encoder */
  526. case 79001:
  527. /* WinTV-HVR1250 (PCIe, Retail, IR, full height,
  528. ATSC and Basic analog */
  529. case 79101:
  530. /* WinTV-HVR1250 (PCIe, Retail, IR, half height,
  531. ATSC and Basic analog */
  532. case 79561:
  533. /* WinTV-HVR1250 (PCIe, OEM, No IR, half height,
  534. ATSC and Basic analog */
  535. case 79571:
  536. /* WinTV-HVR1250 (PCIe, OEM, No IR, full height,
  537. ATSC and Basic analog */
  538. case 79671:
  539. /* WinTV-HVR1250 (PCIe, OEM, No IR, half height,
  540. ATSC and Basic analog */
  541. case 80019:
  542. /* WinTV-HVR1400 (Express Card, Retail, IR,
  543. * DVB-T and Basic analog */
  544. case 81509:
  545. /* WinTV-HVR1700 (PCIe, OEM, No IR, half height)
  546. * DVB-T and MPEG2 HW Encoder */
  547. case 81519:
  548. /* WinTV-HVR1700 (PCIe, OEM, No IR, full height)
  549. * DVB-T and MPEG2 HW Encoder */
  550. break;
  551. case 85021:
  552. /* WinTV-HVR1850 (PCIe, OEM, RCA in, IR, FM,
  553. Dual channel ATSC and MPEG2 HW Encoder */
  554. break;
  555. default:
  556. printk(KERN_WARNING "%s: warning: "
  557. "unknown hauppauge model #%d\n",
  558. dev->name, tv.model);
  559. break;
  560. }
  561. printk(KERN_INFO "%s: hauppauge eeprom: model=%d\n",
  562. dev->name, tv.model);
  563. }
  564. int cx23885_tuner_callback(void *priv, int component, int command, int arg)
  565. {
  566. struct cx23885_tsport *port = priv;
  567. struct cx23885_dev *dev = port->dev;
  568. u32 bitmask = 0;
  569. if (command == XC2028_RESET_CLK)
  570. return 0;
  571. if (command != 0) {
  572. printk(KERN_ERR "%s(): Unknown command 0x%x.\n",
  573. __func__, command);
  574. return -EINVAL;
  575. }
  576. switch (dev->board) {
  577. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  578. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  579. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  580. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
  581. case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
  582. case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
  583. /* Tuner Reset Command */
  584. bitmask = 0x04;
  585. break;
  586. case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
  587. case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
  588. /* Two identical tuners on two different i2c buses,
  589. * we need to reset the correct gpio. */
  590. if (port->nr == 1)
  591. bitmask = 0x01;
  592. else if (port->nr == 2)
  593. bitmask = 0x04;
  594. break;
  595. }
  596. if (bitmask) {
  597. /* Drive the tuner into reset and back out */
  598. cx_clear(GP0_IO, bitmask);
  599. mdelay(200);
  600. cx_set(GP0_IO, bitmask);
  601. }
  602. return 0;
  603. }
  604. void cx23885_gpio_setup(struct cx23885_dev *dev)
  605. {
  606. switch (dev->board) {
  607. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  608. /* GPIO-0 cx24227 demodulator reset */
  609. cx_set(GP0_IO, 0x00010001); /* Bring the part out of reset */
  610. break;
  611. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  612. /* GPIO-0 cx24227 demodulator */
  613. /* GPIO-2 xc3028 tuner */
  614. /* Put the parts into reset */
  615. cx_set(GP0_IO, 0x00050000);
  616. cx_clear(GP0_IO, 0x00000005);
  617. msleep(5);
  618. /* Bring the parts out of reset */
  619. cx_set(GP0_IO, 0x00050005);
  620. break;
  621. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  622. /* GPIO-0 cx24227 demodulator reset */
  623. /* GPIO-2 xc5000 tuner reset */
  624. cx_set(GP0_IO, 0x00050005); /* Bring the part out of reset */
  625. break;
  626. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  627. /* GPIO-0 656_CLK */
  628. /* GPIO-1 656_D0 */
  629. /* GPIO-2 8295A Reset */
  630. /* GPIO-3-10 cx23417 data0-7 */
  631. /* GPIO-11-14 cx23417 addr0-3 */
  632. /* GPIO-15-18 cx23417 READY, CS, RD, WR */
  633. /* GPIO-19 IR_RX */
  634. /* CX23417 GPIO's */
  635. /* EIO15 Zilog Reset */
  636. /* EIO14 S5H1409/CX24227 Reset */
  637. mc417_gpio_enable(dev, GPIO_15 | GPIO_14, 1);
  638. /* Put the demod into reset and protect the eeprom */
  639. mc417_gpio_clear(dev, GPIO_15 | GPIO_14);
  640. mdelay(100);
  641. /* Bring the demod and blaster out of reset */
  642. mc417_gpio_set(dev, GPIO_15 | GPIO_14);
  643. mdelay(100);
  644. /* Force the TDA8295A into reset and back */
  645. cx23885_gpio_enable(dev, GPIO_2, 1);
  646. cx23885_gpio_set(dev, GPIO_2);
  647. mdelay(20);
  648. cx23885_gpio_clear(dev, GPIO_2);
  649. mdelay(20);
  650. cx23885_gpio_set(dev, GPIO_2);
  651. mdelay(20);
  652. break;
  653. case CX23885_BOARD_HAUPPAUGE_HVR1200:
  654. /* GPIO-0 tda10048 demodulator reset */
  655. /* GPIO-2 tda18271 tuner reset */
  656. /* Put the parts into reset and back */
  657. cx_set(GP0_IO, 0x00050000);
  658. mdelay(20);
  659. cx_clear(GP0_IO, 0x00000005);
  660. mdelay(20);
  661. cx_set(GP0_IO, 0x00050005);
  662. break;
  663. case CX23885_BOARD_HAUPPAUGE_HVR1700:
  664. /* GPIO-0 TDA10048 demodulator reset */
  665. /* GPIO-2 TDA8295A Reset */
  666. /* GPIO-3-10 cx23417 data0-7 */
  667. /* GPIO-11-14 cx23417 addr0-3 */
  668. /* GPIO-15-18 cx23417 READY, CS, RD, WR */
  669. /* The following GPIO's are on the interna AVCore (cx25840) */
  670. /* GPIO-19 IR_RX */
  671. /* GPIO-20 IR_TX 416/DVBT Select */
  672. /* GPIO-21 IIS DAT */
  673. /* GPIO-22 IIS WCLK */
  674. /* GPIO-23 IIS BCLK */
  675. /* Put the parts into reset and back */
  676. cx_set(GP0_IO, 0x00050000);
  677. mdelay(20);
  678. cx_clear(GP0_IO, 0x00000005);
  679. mdelay(20);
  680. cx_set(GP0_IO, 0x00050005);
  681. break;
  682. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  683. /* GPIO-0 Dibcom7000p demodulator reset */
  684. /* GPIO-2 xc3028L tuner reset */
  685. /* GPIO-13 LED */
  686. /* Put the parts into reset and back */
  687. cx_set(GP0_IO, 0x00050000);
  688. mdelay(20);
  689. cx_clear(GP0_IO, 0x00000005);
  690. mdelay(20);
  691. cx_set(GP0_IO, 0x00050005);
  692. break;
  693. case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
  694. /* GPIO-0 xc5000 tuner reset i2c bus 0 */
  695. /* GPIO-1 s5h1409 demod reset i2c bus 0 */
  696. /* GPIO-2 xc5000 tuner reset i2c bus 1 */
  697. /* GPIO-3 s5h1409 demod reset i2c bus 0 */
  698. /* Put the parts into reset and back */
  699. cx_set(GP0_IO, 0x000f0000);
  700. mdelay(20);
  701. cx_clear(GP0_IO, 0x0000000f);
  702. mdelay(20);
  703. cx_set(GP0_IO, 0x000f000f);
  704. break;
  705. case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
  706. /* GPIO-0 portb xc3028 reset */
  707. /* GPIO-1 portb zl10353 reset */
  708. /* GPIO-2 portc xc3028 reset */
  709. /* GPIO-3 portc zl10353 reset */
  710. /* Put the parts into reset and back */
  711. cx_set(GP0_IO, 0x000f0000);
  712. mdelay(20);
  713. cx_clear(GP0_IO, 0x0000000f);
  714. mdelay(20);
  715. cx_set(GP0_IO, 0x000f000f);
  716. break;
  717. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
  718. case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
  719. case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
  720. /* GPIO-2 xc3028 tuner reset */
  721. /* The following GPIO's are on the internal AVCore (cx25840) */
  722. /* GPIO-? zl10353 demod reset */
  723. /* Put the parts into reset and back */
  724. cx_set(GP0_IO, 0x00040000);
  725. mdelay(20);
  726. cx_clear(GP0_IO, 0x00000004);
  727. mdelay(20);
  728. cx_set(GP0_IO, 0x00040004);
  729. break;
  730. case CX23885_BOARD_TBS_6920:
  731. case CX23885_BOARD_TEVII_S470:
  732. cx_write(MC417_CTL, 0x00000036);
  733. cx_write(MC417_OEN, 0x00001000);
  734. cx_write(MC417_RWD, 0x00001800);
  735. break;
  736. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  737. /* GPIO-0 INTA from CiMax1
  738. GPIO-1 INTB from CiMax2
  739. GPIO-2 reset chips
  740. GPIO-3 to GPIO-10 data/addr for CA
  741. GPIO-11 ~CS0 to CiMax1
  742. GPIO-12 ~CS1 to CiMax2
  743. GPIO-13 ADL0 load LSB addr
  744. GPIO-14 ADL1 load MSB addr
  745. GPIO-15 ~RDY from CiMax
  746. GPIO-17 ~RD to CiMax
  747. GPIO-18 ~WR to CiMax
  748. */
  749. cx_set(GP0_IO, 0x00040000); /* GPIO as out */
  750. /* GPIO1 and GPIO2 as INTA and INTB from CiMaxes, reset low */
  751. cx_clear(GP0_IO, 0x00030004);
  752. mdelay(100);/* reset delay */
  753. cx_set(GP0_IO, 0x00040004); /* GPIO as out, reset high */
  754. cx_write(MC417_CTL, 0x00000037);/* enable GPIO3-18 pins */
  755. /* GPIO-15 IN as ~ACK, rest as OUT */
  756. cx_write(MC417_OEN, 0x00001000);
  757. /* ~RD, ~WR high; ADL0, ADL1 low; ~CS0, ~CS1 high */
  758. cx_write(MC417_RWD, 0x0000c300);
  759. /* enable irq */
  760. cx_write(GPIO_ISM, 0x00000000);/* INTERRUPTS active low*/
  761. break;
  762. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  763. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  764. case CX23885_BOARD_HAUPPAUGE_HVR1255:
  765. case CX23885_BOARD_HAUPPAUGE_HVR1210:
  766. /* GPIO-5 RF Control: 0 = RF1 Terrestrial, 1 = RF2 Cable */
  767. /* GPIO-6 I2C Gate which can isolate the demod from the bus */
  768. /* GPIO-9 Demod reset */
  769. /* Put the parts into reset and back */
  770. cx23885_gpio_enable(dev, GPIO_9 | GPIO_6 | GPIO_5, 1);
  771. cx23885_gpio_set(dev, GPIO_9 | GPIO_6 | GPIO_5);
  772. cx23885_gpio_clear(dev, GPIO_9);
  773. mdelay(20);
  774. cx23885_gpio_set(dev, GPIO_9);
  775. break;
  776. case CX23885_BOARD_MYGICA_X8506:
  777. case CX23885_BOARD_MAGICPRO_PROHDTVE2:
  778. /* GPIO-0 (0)Analog / (1)Digital TV */
  779. /* GPIO-1 reset XC5000 */
  780. /* GPIO-2 reset LGS8GL5 / LGS8G75 */
  781. cx23885_gpio_enable(dev, GPIO_0 | GPIO_1 | GPIO_2, 1);
  782. cx23885_gpio_clear(dev, GPIO_1 | GPIO_2);
  783. mdelay(100);
  784. cx23885_gpio_set(dev, GPIO_0 | GPIO_1 | GPIO_2);
  785. mdelay(100);
  786. break;
  787. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  788. /* GPIO-0 656_CLK */
  789. /* GPIO-1 656_D0 */
  790. /* GPIO-2 Wake# */
  791. /* GPIO-3-10 cx23417 data0-7 */
  792. /* GPIO-11-14 cx23417 addr0-3 */
  793. /* GPIO-15-18 cx23417 READY, CS, RD, WR */
  794. /* GPIO-19 IR_RX */
  795. /* GPIO-20 C_IR_TX */
  796. /* GPIO-21 I2S DAT */
  797. /* GPIO-22 I2S WCLK */
  798. /* GPIO-23 I2S BCLK */
  799. /* ALT GPIO: EXP GPIO LATCH */
  800. /* CX23417 GPIO's */
  801. /* GPIO-14 S5H1411/CX24228 Reset */
  802. /* GPIO-13 EEPROM write protect */
  803. mc417_gpio_enable(dev, GPIO_14 | GPIO_13, 1);
  804. /* Put the demod into reset and protect the eeprom */
  805. mc417_gpio_clear(dev, GPIO_14 | GPIO_13);
  806. mdelay(100);
  807. /* Bring the demod out of reset */
  808. mc417_gpio_set(dev, GPIO_14);
  809. mdelay(100);
  810. /* CX24228 GPIO */
  811. /* Connected to IF / Mux */
  812. break;
  813. }
  814. }
  815. int cx23885_ir_init(struct cx23885_dev *dev)
  816. {
  817. int ret = 0;
  818. switch (dev->board) {
  819. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  820. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  821. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  822. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  823. case CX23885_BOARD_HAUPPAUGE_HVR1200:
  824. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  825. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  826. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  827. case CX23885_BOARD_HAUPPAUGE_HVR1255:
  828. case CX23885_BOARD_HAUPPAUGE_HVR1210:
  829. /* FIXME: Implement me */
  830. break;
  831. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  832. ret = cx23888_ir_probe(dev);
  833. if (ret)
  834. break;
  835. dev->sd_ir = cx23885_find_hw(dev, CX23885_HW_888_IR);
  836. dev->pci_irqmask |= PCI_MSK_IR;
  837. break;
  838. case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
  839. request_module("ir-kbd-i2c");
  840. break;
  841. }
  842. return ret;
  843. }
  844. void cx23885_ir_fini(struct cx23885_dev *dev)
  845. {
  846. switch (dev->board) {
  847. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  848. dev->pci_irqmask &= ~PCI_MSK_IR;
  849. cx_clear(PCI_INT_MSK, PCI_MSK_IR);
  850. cx23888_ir_remove(dev);
  851. dev->sd_ir = NULL;
  852. break;
  853. }
  854. }
  855. void cx23885_ir_pci_int_enable(struct cx23885_dev *dev)
  856. {
  857. switch (dev->board) {
  858. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  859. if (dev->sd_ir && (dev->pci_irqmask & PCI_MSK_IR))
  860. cx_set(PCI_INT_MSK, PCI_MSK_IR);
  861. break;
  862. }
  863. }
  864. void cx23885_card_setup(struct cx23885_dev *dev)
  865. {
  866. struct cx23885_tsport *ts1 = &dev->ts1;
  867. struct cx23885_tsport *ts2 = &dev->ts2;
  868. static u8 eeprom[256];
  869. if (dev->i2c_bus[0].i2c_rc == 0) {
  870. dev->i2c_bus[0].i2c_client.addr = 0xa0 >> 1;
  871. tveeprom_read(&dev->i2c_bus[0].i2c_client,
  872. eeprom, sizeof(eeprom));
  873. }
  874. switch (dev->board) {
  875. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  876. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  877. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  878. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  879. if (dev->i2c_bus[0].i2c_rc == 0)
  880. hauppauge_eeprom(dev, eeprom+0x80);
  881. break;
  882. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  883. case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
  884. case CX23885_BOARD_HAUPPAUGE_HVR1200:
  885. case CX23885_BOARD_HAUPPAUGE_HVR1700:
  886. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  887. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  888. case CX23885_BOARD_HAUPPAUGE_HVR1255:
  889. case CX23885_BOARD_HAUPPAUGE_HVR1210:
  890. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  891. if (dev->i2c_bus[0].i2c_rc == 0)
  892. hauppauge_eeprom(dev, eeprom+0xc0);
  893. break;
  894. }
  895. switch (dev->board) {
  896. case CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP:
  897. case CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP:
  898. ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  899. ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  900. ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  901. /* break omitted intentionally */
  902. case CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP:
  903. ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  904. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  905. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  906. break;
  907. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  908. /* Defaults for VID B - Analog encoder */
  909. /* DREQ_POL, SMODE, PUNC_CLK, MCLK_POL Serial bus + punc clk */
  910. ts1->gen_ctrl_val = 0x10e;
  911. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  912. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  913. /* APB_TSVALERR_POL (active low)*/
  914. ts1->vld_misc_val = 0x2000;
  915. ts1->hw_sop_ctrl_val = (0x47 << 16 | 188 << 4 | 0xc);
  916. /* Defaults for VID C */
  917. ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  918. ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  919. ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  920. break;
  921. case CX23885_BOARD_TEVII_S470:
  922. case CX23885_BOARD_TBS_6920:
  923. case CX23885_BOARD_DVBWORLD_2005:
  924. ts1->gen_ctrl_val = 0x5; /* Parallel */
  925. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  926. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  927. break;
  928. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  929. ts1->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  930. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  931. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  932. ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  933. ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  934. ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  935. break;
  936. case CX23885_BOARD_MYGICA_X8506:
  937. case CX23885_BOARD_MAGICPRO_PROHDTVE2:
  938. ts1->gen_ctrl_val = 0x5; /* Parallel */
  939. ts1->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  940. ts1->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  941. break;
  942. case CX23885_BOARD_HAUPPAUGE_HVR1250:
  943. case CX23885_BOARD_HAUPPAUGE_HVR1500:
  944. case CX23885_BOARD_HAUPPAUGE_HVR1500Q:
  945. case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
  946. case CX23885_BOARD_HAUPPAUGE_HVR1200:
  947. case CX23885_BOARD_HAUPPAUGE_HVR1700:
  948. case CX23885_BOARD_HAUPPAUGE_HVR1400:
  949. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
  950. case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
  951. case CX23885_BOARD_HAUPPAUGE_HVR1270:
  952. case CX23885_BOARD_HAUPPAUGE_HVR1275:
  953. case CX23885_BOARD_HAUPPAUGE_HVR1255:
  954. case CX23885_BOARD_HAUPPAUGE_HVR1210:
  955. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  956. case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
  957. default:
  958. ts2->gen_ctrl_val = 0xc; /* Serial bus + punctured clock */
  959. ts2->ts_clk_en_val = 0x1; /* Enable TS_CLK */
  960. ts2->src_sel_val = CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO;
  961. }
  962. /* Certain boards support analog, or require the avcore to be
  963. * loaded, ensure this happens.
  964. */
  965. switch (dev->board) {
  966. case CX23885_BOARD_HAUPPAUGE_HVR1800:
  967. case CX23885_BOARD_HAUPPAUGE_HVR1800lp:
  968. case CX23885_BOARD_HAUPPAUGE_HVR1700:
  969. case CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H:
  970. case CX23885_BOARD_COMPRO_VIDEOMATE_E650F:
  971. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  972. case CX23885_BOARD_COMPRO_VIDEOMATE_E800:
  973. case CX23885_BOARD_HAUPPAUGE_HVR1850:
  974. case CX23885_BOARD_MYGICA_X8506:
  975. case CX23885_BOARD_MAGICPRO_PROHDTVE2:
  976. dev->sd_cx25840 = v4l2_i2c_new_subdev(&dev->v4l2_dev,
  977. &dev->i2c_bus[2].i2c_adap,
  978. "cx25840", "cx25840", 0x88 >> 1, NULL);
  979. v4l2_subdev_call(dev->sd_cx25840, core, load_fw);
  980. break;
  981. }
  982. /* AUX-PLL 27MHz CLK */
  983. switch (dev->board) {
  984. case CX23885_BOARD_NETUP_DUAL_DVBS2_CI:
  985. netup_initialize(dev);
  986. break;
  987. }
  988. }
  989. /* ------------------------------------------------------------------ */