intel_sdvo.c 87 KB

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  1. /*
  2. * Copyright 2006 Dave Airlie <airlied@linux.ie>
  3. * Copyright © 2006-2007 Intel Corporation
  4. * Jesse Barnes <jesse.barnes@intel.com>
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice (including the next
  14. * paragraph) shall be included in all copies or substantial portions of the
  15. * Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  22. * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  23. * DEALINGS IN THE SOFTWARE.
  24. *
  25. * Authors:
  26. * Eric Anholt <eric@anholt.net>
  27. */
  28. #include <linux/i2c.h>
  29. #include <linux/slab.h>
  30. #include <linux/delay.h>
  31. #include <linux/export.h>
  32. #include <drm/drmP.h>
  33. #include <drm/drm_crtc.h>
  34. #include <drm/drm_edid.h>
  35. #include "intel_drv.h"
  36. #include <drm/i915_drm.h>
  37. #include "i915_drv.h"
  38. #include "intel_sdvo_regs.h"
  39. #define SDVO_TMDS_MASK (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_TMDS1)
  40. #define SDVO_RGB_MASK (SDVO_OUTPUT_RGB0 | SDVO_OUTPUT_RGB1)
  41. #define SDVO_LVDS_MASK (SDVO_OUTPUT_LVDS0 | SDVO_OUTPUT_LVDS1)
  42. #define SDVO_TV_MASK (SDVO_OUTPUT_CVBS0 | SDVO_OUTPUT_SVID0 | SDVO_OUTPUT_YPRPB0)
  43. #define SDVO_OUTPUT_MASK (SDVO_TMDS_MASK | SDVO_RGB_MASK | SDVO_LVDS_MASK |\
  44. SDVO_TV_MASK)
  45. #define IS_TV(c) (c->output_flag & SDVO_TV_MASK)
  46. #define IS_TMDS(c) (c->output_flag & SDVO_TMDS_MASK)
  47. #define IS_LVDS(c) (c->output_flag & SDVO_LVDS_MASK)
  48. #define IS_TV_OR_LVDS(c) (c->output_flag & (SDVO_TV_MASK | SDVO_LVDS_MASK))
  49. #define IS_DIGITAL(c) (c->output_flag & (SDVO_TMDS_MASK | SDVO_LVDS_MASK))
  50. static const char *tv_format_names[] = {
  51. "NTSC_M" , "NTSC_J" , "NTSC_443",
  52. "PAL_B" , "PAL_D" , "PAL_G" ,
  53. "PAL_H" , "PAL_I" , "PAL_M" ,
  54. "PAL_N" , "PAL_NC" , "PAL_60" ,
  55. "SECAM_B" , "SECAM_D" , "SECAM_G" ,
  56. "SECAM_K" , "SECAM_K1", "SECAM_L" ,
  57. "SECAM_60"
  58. };
  59. #define TV_FORMAT_NUM (sizeof(tv_format_names) / sizeof(*tv_format_names))
  60. struct intel_sdvo {
  61. struct intel_encoder base;
  62. struct i2c_adapter *i2c;
  63. u8 slave_addr;
  64. struct i2c_adapter ddc;
  65. /* Register for the SDVO device: SDVOB or SDVOC */
  66. uint32_t sdvo_reg;
  67. /* Active outputs controlled by this SDVO output */
  68. uint16_t controlled_output;
  69. /*
  70. * Capabilities of the SDVO device returned by
  71. * i830_sdvo_get_capabilities()
  72. */
  73. struct intel_sdvo_caps caps;
  74. /* Pixel clock limitations reported by the SDVO device, in kHz */
  75. int pixel_clock_min, pixel_clock_max;
  76. /*
  77. * For multiple function SDVO device,
  78. * this is for current attached outputs.
  79. */
  80. uint16_t attached_output;
  81. /*
  82. * Hotplug activation bits for this device
  83. */
  84. uint16_t hotplug_active;
  85. /**
  86. * This is used to select the color range of RBG outputs in HDMI mode.
  87. * It is only valid when using TMDS encoding and 8 bit per color mode.
  88. */
  89. uint32_t color_range;
  90. bool color_range_auto;
  91. /**
  92. * This is set if we're going to treat the device as TV-out.
  93. *
  94. * While we have these nice friendly flags for output types that ought
  95. * to decide this for us, the S-Video output on our HDMI+S-Video card
  96. * shows up as RGB1 (VGA).
  97. */
  98. bool is_tv;
  99. /* On different gens SDVOB is at different places. */
  100. bool is_sdvob;
  101. /* This is for current tv format name */
  102. int tv_format_index;
  103. /**
  104. * This is set if we treat the device as HDMI, instead of DVI.
  105. */
  106. bool is_hdmi;
  107. bool has_hdmi_monitor;
  108. bool has_hdmi_audio;
  109. bool rgb_quant_range_selectable;
  110. /**
  111. * This is set if we detect output of sdvo device as LVDS and
  112. * have a valid fixed mode to use with the panel.
  113. */
  114. bool is_lvds;
  115. /**
  116. * This is sdvo fixed pannel mode pointer
  117. */
  118. struct drm_display_mode *sdvo_lvds_fixed_mode;
  119. /* DDC bus used by this SDVO encoder */
  120. uint8_t ddc_bus;
  121. /*
  122. * the sdvo flag gets lost in round trip: dtd->adjusted_mode->dtd
  123. */
  124. uint8_t dtd_sdvo_flags;
  125. };
  126. struct intel_sdvo_connector {
  127. struct intel_connector base;
  128. /* Mark the type of connector */
  129. uint16_t output_flag;
  130. enum hdmi_force_audio force_audio;
  131. /* This contains all current supported TV format */
  132. u8 tv_format_supported[TV_FORMAT_NUM];
  133. int format_supported_num;
  134. struct drm_property *tv_format;
  135. /* add the property for the SDVO-TV */
  136. struct drm_property *left;
  137. struct drm_property *right;
  138. struct drm_property *top;
  139. struct drm_property *bottom;
  140. struct drm_property *hpos;
  141. struct drm_property *vpos;
  142. struct drm_property *contrast;
  143. struct drm_property *saturation;
  144. struct drm_property *hue;
  145. struct drm_property *sharpness;
  146. struct drm_property *flicker_filter;
  147. struct drm_property *flicker_filter_adaptive;
  148. struct drm_property *flicker_filter_2d;
  149. struct drm_property *tv_chroma_filter;
  150. struct drm_property *tv_luma_filter;
  151. struct drm_property *dot_crawl;
  152. /* add the property for the SDVO-TV/LVDS */
  153. struct drm_property *brightness;
  154. /* Add variable to record current setting for the above property */
  155. u32 left_margin, right_margin, top_margin, bottom_margin;
  156. /* this is to get the range of margin.*/
  157. u32 max_hscan, max_vscan;
  158. u32 max_hpos, cur_hpos;
  159. u32 max_vpos, cur_vpos;
  160. u32 cur_brightness, max_brightness;
  161. u32 cur_contrast, max_contrast;
  162. u32 cur_saturation, max_saturation;
  163. u32 cur_hue, max_hue;
  164. u32 cur_sharpness, max_sharpness;
  165. u32 cur_flicker_filter, max_flicker_filter;
  166. u32 cur_flicker_filter_adaptive, max_flicker_filter_adaptive;
  167. u32 cur_flicker_filter_2d, max_flicker_filter_2d;
  168. u32 cur_tv_chroma_filter, max_tv_chroma_filter;
  169. u32 cur_tv_luma_filter, max_tv_luma_filter;
  170. u32 cur_dot_crawl, max_dot_crawl;
  171. };
  172. static struct intel_sdvo *to_intel_sdvo(struct drm_encoder *encoder)
  173. {
  174. return container_of(encoder, struct intel_sdvo, base.base);
  175. }
  176. static struct intel_sdvo *intel_attached_sdvo(struct drm_connector *connector)
  177. {
  178. return container_of(intel_attached_encoder(connector),
  179. struct intel_sdvo, base);
  180. }
  181. static struct intel_sdvo_connector *to_intel_sdvo_connector(struct drm_connector *connector)
  182. {
  183. return container_of(to_intel_connector(connector), struct intel_sdvo_connector, base);
  184. }
  185. static bool
  186. intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags);
  187. static bool
  188. intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
  189. struct intel_sdvo_connector *intel_sdvo_connector,
  190. int type);
  191. static bool
  192. intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
  193. struct intel_sdvo_connector *intel_sdvo_connector);
  194. /**
  195. * Writes the SDVOB or SDVOC with the given value, but always writes both
  196. * SDVOB and SDVOC to work around apparent hardware issues (according to
  197. * comments in the BIOS).
  198. */
  199. static void intel_sdvo_write_sdvox(struct intel_sdvo *intel_sdvo, u32 val)
  200. {
  201. struct drm_device *dev = intel_sdvo->base.base.dev;
  202. struct drm_i915_private *dev_priv = dev->dev_private;
  203. u32 bval = val, cval = val;
  204. int i;
  205. if (intel_sdvo->sdvo_reg == PCH_SDVOB) {
  206. I915_WRITE(intel_sdvo->sdvo_reg, val);
  207. I915_READ(intel_sdvo->sdvo_reg);
  208. return;
  209. }
  210. if (intel_sdvo->sdvo_reg == GEN3_SDVOB)
  211. cval = I915_READ(GEN3_SDVOC);
  212. else
  213. bval = I915_READ(GEN3_SDVOB);
  214. /*
  215. * Write the registers twice for luck. Sometimes,
  216. * writing them only once doesn't appear to 'stick'.
  217. * The BIOS does this too. Yay, magic
  218. */
  219. for (i = 0; i < 2; i++)
  220. {
  221. I915_WRITE(GEN3_SDVOB, bval);
  222. I915_READ(GEN3_SDVOB);
  223. I915_WRITE(GEN3_SDVOC, cval);
  224. I915_READ(GEN3_SDVOC);
  225. }
  226. }
  227. static bool intel_sdvo_read_byte(struct intel_sdvo *intel_sdvo, u8 addr, u8 *ch)
  228. {
  229. struct i2c_msg msgs[] = {
  230. {
  231. .addr = intel_sdvo->slave_addr,
  232. .flags = 0,
  233. .len = 1,
  234. .buf = &addr,
  235. },
  236. {
  237. .addr = intel_sdvo->slave_addr,
  238. .flags = I2C_M_RD,
  239. .len = 1,
  240. .buf = ch,
  241. }
  242. };
  243. int ret;
  244. if ((ret = i2c_transfer(intel_sdvo->i2c, msgs, 2)) == 2)
  245. return true;
  246. DRM_DEBUG_KMS("i2c transfer returned %d\n", ret);
  247. return false;
  248. }
  249. #define SDVO_CMD_NAME_ENTRY(cmd) {cmd, #cmd}
  250. /** Mapping of command numbers to names, for debug output */
  251. static const struct _sdvo_cmd_name {
  252. u8 cmd;
  253. const char *name;
  254. } sdvo_cmd_names[] = {
  255. SDVO_CMD_NAME_ENTRY(SDVO_CMD_RESET),
  256. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DEVICE_CAPS),
  257. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FIRMWARE_REV),
  258. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TRAINED_INPUTS),
  259. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_OUTPUTS),
  260. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_OUTPUTS),
  261. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_IN_OUT_MAP),
  262. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_IN_OUT_MAP),
  263. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ATTACHED_DISPLAYS),
  264. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HOT_PLUG_SUPPORT),
  265. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ACTIVE_HOT_PLUG),
  266. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ACTIVE_HOT_PLUG),
  267. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INTERRUPT_EVENT_SOURCE),
  268. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_INPUT),
  269. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TARGET_OUTPUT),
  270. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART1),
  271. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_TIMINGS_PART2),
  272. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
  273. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART2),
  274. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_INPUT_TIMINGS_PART1),
  275. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART1),
  276. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OUTPUT_TIMINGS_PART2),
  277. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART1),
  278. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_TIMINGS_PART2),
  279. SDVO_CMD_NAME_ENTRY(SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING),
  280. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1),
  281. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2),
  282. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE),
  283. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OUTPUT_PIXEL_CLOCK_RANGE),
  284. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_CLOCK_RATE_MULTS),
  285. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CLOCK_RATE_MULT),
  286. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CLOCK_RATE_MULT),
  287. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_TV_FORMATS),
  288. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_FORMAT),
  289. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_FORMAT),
  290. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_POWER_STATES),
  291. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_POWER_STATE),
  292. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODER_POWER_STATE),
  293. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DISPLAY_POWER_STATE),
  294. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTROL_BUS_SWITCH),
  295. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT),
  296. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SCALED_HDTV_RESOLUTION_SUPPORT),
  297. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS),
  298. /* Add the op code for SDVO enhancements */
  299. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HPOS),
  300. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HPOS),
  301. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HPOS),
  302. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_VPOS),
  303. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_VPOS),
  304. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_VPOS),
  305. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SATURATION),
  306. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SATURATION),
  307. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SATURATION),
  308. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_HUE),
  309. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HUE),
  310. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HUE),
  311. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_CONTRAST),
  312. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_CONTRAST),
  313. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_CONTRAST),
  314. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_BRIGHTNESS),
  315. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_BRIGHTNESS),
  316. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_BRIGHTNESS),
  317. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_H),
  318. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_H),
  319. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_H),
  320. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_OVERSCAN_V),
  321. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_OVERSCAN_V),
  322. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_OVERSCAN_V),
  323. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER),
  324. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER),
  325. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER),
  326. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_ADAPTIVE),
  327. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_ADAPTIVE),
  328. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_ADAPTIVE),
  329. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_FLICKER_FILTER_2D),
  330. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_FLICKER_FILTER_2D),
  331. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_FLICKER_FILTER_2D),
  332. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_SHARPNESS),
  333. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SHARPNESS),
  334. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_SHARPNESS),
  335. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_DOT_CRAWL),
  336. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_DOT_CRAWL),
  337. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_CHROMA_FILTER),
  338. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_CHROMA_FILTER),
  339. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_CHROMA_FILTER),
  340. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_MAX_TV_LUMA_FILTER),
  341. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_TV_LUMA_FILTER),
  342. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_TV_LUMA_FILTER),
  343. /* HDMI op code */
  344. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_SUPP_ENCODE),
  345. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_ENCODE),
  346. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_ENCODE),
  347. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_PIXEL_REPLI),
  348. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_PIXEL_REPLI),
  349. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY_CAP),
  350. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_COLORIMETRY),
  351. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_COLORIMETRY),
  352. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_ENCRYPT_PREFER),
  353. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_AUDIO_STAT),
  354. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_AUDIO_STAT),
  355. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INDEX),
  356. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_INDEX),
  357. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_INFO),
  358. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_AV_SPLIT),
  359. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_AV_SPLIT),
  360. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_TXRATE),
  361. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_TXRATE),
  362. SDVO_CMD_NAME_ENTRY(SDVO_CMD_SET_HBUF_DATA),
  363. SDVO_CMD_NAME_ENTRY(SDVO_CMD_GET_HBUF_DATA),
  364. };
  365. #define SDVO_NAME(svdo) ((svdo)->is_sdvob ? "SDVOB" : "SDVOC")
  366. static void intel_sdvo_debug_write(struct intel_sdvo *intel_sdvo, u8 cmd,
  367. const void *args, int args_len)
  368. {
  369. int i;
  370. DRM_DEBUG_KMS("%s: W: %02X ",
  371. SDVO_NAME(intel_sdvo), cmd);
  372. for (i = 0; i < args_len; i++)
  373. DRM_LOG_KMS("%02X ", ((u8 *)args)[i]);
  374. for (; i < 8; i++)
  375. DRM_LOG_KMS(" ");
  376. for (i = 0; i < ARRAY_SIZE(sdvo_cmd_names); i++) {
  377. if (cmd == sdvo_cmd_names[i].cmd) {
  378. DRM_LOG_KMS("(%s)", sdvo_cmd_names[i].name);
  379. break;
  380. }
  381. }
  382. if (i == ARRAY_SIZE(sdvo_cmd_names))
  383. DRM_LOG_KMS("(%02X)", cmd);
  384. DRM_LOG_KMS("\n");
  385. }
  386. static const char *cmd_status_names[] = {
  387. "Power on",
  388. "Success",
  389. "Not supported",
  390. "Invalid arg",
  391. "Pending",
  392. "Target not specified",
  393. "Scaling not supported"
  394. };
  395. static bool intel_sdvo_write_cmd(struct intel_sdvo *intel_sdvo, u8 cmd,
  396. const void *args, int args_len)
  397. {
  398. u8 *buf, status;
  399. struct i2c_msg *msgs;
  400. int i, ret = true;
  401. /* Would be simpler to allocate both in one go ? */
  402. buf = kzalloc(args_len * 2 + 2, GFP_KERNEL);
  403. if (!buf)
  404. return false;
  405. msgs = kcalloc(args_len + 3, sizeof(*msgs), GFP_KERNEL);
  406. if (!msgs) {
  407. kfree(buf);
  408. return false;
  409. }
  410. intel_sdvo_debug_write(intel_sdvo, cmd, args, args_len);
  411. for (i = 0; i < args_len; i++) {
  412. msgs[i].addr = intel_sdvo->slave_addr;
  413. msgs[i].flags = 0;
  414. msgs[i].len = 2;
  415. msgs[i].buf = buf + 2 *i;
  416. buf[2*i + 0] = SDVO_I2C_ARG_0 - i;
  417. buf[2*i + 1] = ((u8*)args)[i];
  418. }
  419. msgs[i].addr = intel_sdvo->slave_addr;
  420. msgs[i].flags = 0;
  421. msgs[i].len = 2;
  422. msgs[i].buf = buf + 2*i;
  423. buf[2*i + 0] = SDVO_I2C_OPCODE;
  424. buf[2*i + 1] = cmd;
  425. /* the following two are to read the response */
  426. status = SDVO_I2C_CMD_STATUS;
  427. msgs[i+1].addr = intel_sdvo->slave_addr;
  428. msgs[i+1].flags = 0;
  429. msgs[i+1].len = 1;
  430. msgs[i+1].buf = &status;
  431. msgs[i+2].addr = intel_sdvo->slave_addr;
  432. msgs[i+2].flags = I2C_M_RD;
  433. msgs[i+2].len = 1;
  434. msgs[i+2].buf = &status;
  435. ret = i2c_transfer(intel_sdvo->i2c, msgs, i+3);
  436. if (ret < 0) {
  437. DRM_DEBUG_KMS("I2c transfer returned %d\n", ret);
  438. ret = false;
  439. goto out;
  440. }
  441. if (ret != i+3) {
  442. /* failure in I2C transfer */
  443. DRM_DEBUG_KMS("I2c transfer returned %d/%d\n", ret, i+3);
  444. ret = false;
  445. }
  446. out:
  447. kfree(msgs);
  448. kfree(buf);
  449. return ret;
  450. }
  451. static bool intel_sdvo_read_response(struct intel_sdvo *intel_sdvo,
  452. void *response, int response_len)
  453. {
  454. u8 retry = 15; /* 5 quick checks, followed by 10 long checks */
  455. u8 status;
  456. int i;
  457. DRM_DEBUG_KMS("%s: R: ", SDVO_NAME(intel_sdvo));
  458. /*
  459. * The documentation states that all commands will be
  460. * processed within 15µs, and that we need only poll
  461. * the status byte a maximum of 3 times in order for the
  462. * command to be complete.
  463. *
  464. * Check 5 times in case the hardware failed to read the docs.
  465. *
  466. * Also beware that the first response by many devices is to
  467. * reply PENDING and stall for time. TVs are notorious for
  468. * requiring longer than specified to complete their replies.
  469. * Originally (in the DDX long ago), the delay was only ever 15ms
  470. * with an additional delay of 30ms applied for TVs added later after
  471. * many experiments. To accommodate both sets of delays, we do a
  472. * sequence of slow checks if the device is falling behind and fails
  473. * to reply within 5*15µs.
  474. */
  475. if (!intel_sdvo_read_byte(intel_sdvo,
  476. SDVO_I2C_CMD_STATUS,
  477. &status))
  478. goto log_fail;
  479. while (status == SDVO_CMD_STATUS_PENDING && --retry) {
  480. if (retry < 10)
  481. msleep(15);
  482. else
  483. udelay(15);
  484. if (!intel_sdvo_read_byte(intel_sdvo,
  485. SDVO_I2C_CMD_STATUS,
  486. &status))
  487. goto log_fail;
  488. }
  489. if (status <= SDVO_CMD_STATUS_SCALING_NOT_SUPP)
  490. DRM_LOG_KMS("(%s)", cmd_status_names[status]);
  491. else
  492. DRM_LOG_KMS("(??? %d)", status);
  493. if (status != SDVO_CMD_STATUS_SUCCESS)
  494. goto log_fail;
  495. /* Read the command response */
  496. for (i = 0; i < response_len; i++) {
  497. if (!intel_sdvo_read_byte(intel_sdvo,
  498. SDVO_I2C_RETURN_0 + i,
  499. &((u8 *)response)[i]))
  500. goto log_fail;
  501. DRM_LOG_KMS(" %02X", ((u8 *)response)[i]);
  502. }
  503. DRM_LOG_KMS("\n");
  504. return true;
  505. log_fail:
  506. DRM_LOG_KMS("... failed\n");
  507. return false;
  508. }
  509. static int intel_sdvo_get_pixel_multiplier(struct drm_display_mode *mode)
  510. {
  511. if (mode->clock >= 100000)
  512. return 1;
  513. else if (mode->clock >= 50000)
  514. return 2;
  515. else
  516. return 4;
  517. }
  518. static bool intel_sdvo_set_control_bus_switch(struct intel_sdvo *intel_sdvo,
  519. u8 ddc_bus)
  520. {
  521. /* This must be the immediately preceding write before the i2c xfer */
  522. return intel_sdvo_write_cmd(intel_sdvo,
  523. SDVO_CMD_SET_CONTROL_BUS_SWITCH,
  524. &ddc_bus, 1);
  525. }
  526. static bool intel_sdvo_set_value(struct intel_sdvo *intel_sdvo, u8 cmd, const void *data, int len)
  527. {
  528. if (!intel_sdvo_write_cmd(intel_sdvo, cmd, data, len))
  529. return false;
  530. return intel_sdvo_read_response(intel_sdvo, NULL, 0);
  531. }
  532. static bool
  533. intel_sdvo_get_value(struct intel_sdvo *intel_sdvo, u8 cmd, void *value, int len)
  534. {
  535. if (!intel_sdvo_write_cmd(intel_sdvo, cmd, NULL, 0))
  536. return false;
  537. return intel_sdvo_read_response(intel_sdvo, value, len);
  538. }
  539. static bool intel_sdvo_set_target_input(struct intel_sdvo *intel_sdvo)
  540. {
  541. struct intel_sdvo_set_target_input_args targets = {0};
  542. return intel_sdvo_set_value(intel_sdvo,
  543. SDVO_CMD_SET_TARGET_INPUT,
  544. &targets, sizeof(targets));
  545. }
  546. /**
  547. * Return whether each input is trained.
  548. *
  549. * This function is making an assumption about the layout of the response,
  550. * which should be checked against the docs.
  551. */
  552. static bool intel_sdvo_get_trained_inputs(struct intel_sdvo *intel_sdvo, bool *input_1, bool *input_2)
  553. {
  554. struct intel_sdvo_get_trained_inputs_response response;
  555. BUILD_BUG_ON(sizeof(response) != 1);
  556. if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_TRAINED_INPUTS,
  557. &response, sizeof(response)))
  558. return false;
  559. *input_1 = response.input0_trained;
  560. *input_2 = response.input1_trained;
  561. return true;
  562. }
  563. static bool intel_sdvo_set_active_outputs(struct intel_sdvo *intel_sdvo,
  564. u16 outputs)
  565. {
  566. return intel_sdvo_set_value(intel_sdvo,
  567. SDVO_CMD_SET_ACTIVE_OUTPUTS,
  568. &outputs, sizeof(outputs));
  569. }
  570. static bool intel_sdvo_get_active_outputs(struct intel_sdvo *intel_sdvo,
  571. u16 *outputs)
  572. {
  573. return intel_sdvo_get_value(intel_sdvo,
  574. SDVO_CMD_GET_ACTIVE_OUTPUTS,
  575. outputs, sizeof(*outputs));
  576. }
  577. static bool intel_sdvo_set_encoder_power_state(struct intel_sdvo *intel_sdvo,
  578. int mode)
  579. {
  580. u8 state = SDVO_ENCODER_STATE_ON;
  581. switch (mode) {
  582. case DRM_MODE_DPMS_ON:
  583. state = SDVO_ENCODER_STATE_ON;
  584. break;
  585. case DRM_MODE_DPMS_STANDBY:
  586. state = SDVO_ENCODER_STATE_STANDBY;
  587. break;
  588. case DRM_MODE_DPMS_SUSPEND:
  589. state = SDVO_ENCODER_STATE_SUSPEND;
  590. break;
  591. case DRM_MODE_DPMS_OFF:
  592. state = SDVO_ENCODER_STATE_OFF;
  593. break;
  594. }
  595. return intel_sdvo_set_value(intel_sdvo,
  596. SDVO_CMD_SET_ENCODER_POWER_STATE, &state, sizeof(state));
  597. }
  598. static bool intel_sdvo_get_input_pixel_clock_range(struct intel_sdvo *intel_sdvo,
  599. int *clock_min,
  600. int *clock_max)
  601. {
  602. struct intel_sdvo_pixel_clock_range clocks;
  603. BUILD_BUG_ON(sizeof(clocks) != 4);
  604. if (!intel_sdvo_get_value(intel_sdvo,
  605. SDVO_CMD_GET_INPUT_PIXEL_CLOCK_RANGE,
  606. &clocks, sizeof(clocks)))
  607. return false;
  608. /* Convert the values from units of 10 kHz to kHz. */
  609. *clock_min = clocks.min * 10;
  610. *clock_max = clocks.max * 10;
  611. return true;
  612. }
  613. static bool intel_sdvo_set_target_output(struct intel_sdvo *intel_sdvo,
  614. u16 outputs)
  615. {
  616. return intel_sdvo_set_value(intel_sdvo,
  617. SDVO_CMD_SET_TARGET_OUTPUT,
  618. &outputs, sizeof(outputs));
  619. }
  620. static bool intel_sdvo_set_timing(struct intel_sdvo *intel_sdvo, u8 cmd,
  621. struct intel_sdvo_dtd *dtd)
  622. {
  623. return intel_sdvo_set_value(intel_sdvo, cmd, &dtd->part1, sizeof(dtd->part1)) &&
  624. intel_sdvo_set_value(intel_sdvo, cmd + 1, &dtd->part2, sizeof(dtd->part2));
  625. }
  626. static bool intel_sdvo_set_input_timing(struct intel_sdvo *intel_sdvo,
  627. struct intel_sdvo_dtd *dtd)
  628. {
  629. return intel_sdvo_set_timing(intel_sdvo,
  630. SDVO_CMD_SET_INPUT_TIMINGS_PART1, dtd);
  631. }
  632. static bool intel_sdvo_set_output_timing(struct intel_sdvo *intel_sdvo,
  633. struct intel_sdvo_dtd *dtd)
  634. {
  635. return intel_sdvo_set_timing(intel_sdvo,
  636. SDVO_CMD_SET_OUTPUT_TIMINGS_PART1, dtd);
  637. }
  638. static bool
  639. intel_sdvo_create_preferred_input_timing(struct intel_sdvo *intel_sdvo,
  640. uint16_t clock,
  641. uint16_t width,
  642. uint16_t height)
  643. {
  644. struct intel_sdvo_preferred_input_timing_args args;
  645. memset(&args, 0, sizeof(args));
  646. args.clock = clock;
  647. args.width = width;
  648. args.height = height;
  649. args.interlace = 0;
  650. if (intel_sdvo->is_lvds &&
  651. (intel_sdvo->sdvo_lvds_fixed_mode->hdisplay != width ||
  652. intel_sdvo->sdvo_lvds_fixed_mode->vdisplay != height))
  653. args.scaled = 1;
  654. return intel_sdvo_set_value(intel_sdvo,
  655. SDVO_CMD_CREATE_PREFERRED_INPUT_TIMING,
  656. &args, sizeof(args));
  657. }
  658. static bool intel_sdvo_get_preferred_input_timing(struct intel_sdvo *intel_sdvo,
  659. struct intel_sdvo_dtd *dtd)
  660. {
  661. BUILD_BUG_ON(sizeof(dtd->part1) != 8);
  662. BUILD_BUG_ON(sizeof(dtd->part2) != 8);
  663. return intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART1,
  664. &dtd->part1, sizeof(dtd->part1)) &&
  665. intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_PREFERRED_INPUT_TIMING_PART2,
  666. &dtd->part2, sizeof(dtd->part2));
  667. }
  668. static bool intel_sdvo_set_clock_rate_mult(struct intel_sdvo *intel_sdvo, u8 val)
  669. {
  670. return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_CLOCK_RATE_MULT, &val, 1);
  671. }
  672. static void intel_sdvo_get_dtd_from_mode(struct intel_sdvo_dtd *dtd,
  673. const struct drm_display_mode *mode)
  674. {
  675. uint16_t width, height;
  676. uint16_t h_blank_len, h_sync_len, v_blank_len, v_sync_len;
  677. uint16_t h_sync_offset, v_sync_offset;
  678. int mode_clock;
  679. width = mode->hdisplay;
  680. height = mode->vdisplay;
  681. /* do some mode translations */
  682. h_blank_len = mode->htotal - mode->hdisplay;
  683. h_sync_len = mode->hsync_end - mode->hsync_start;
  684. v_blank_len = mode->vtotal - mode->vdisplay;
  685. v_sync_len = mode->vsync_end - mode->vsync_start;
  686. h_sync_offset = mode->hsync_start - mode->hdisplay;
  687. v_sync_offset = mode->vsync_start - mode->vdisplay;
  688. mode_clock = mode->clock;
  689. mode_clock /= 10;
  690. dtd->part1.clock = mode_clock;
  691. dtd->part1.h_active = width & 0xff;
  692. dtd->part1.h_blank = h_blank_len & 0xff;
  693. dtd->part1.h_high = (((width >> 8) & 0xf) << 4) |
  694. ((h_blank_len >> 8) & 0xf);
  695. dtd->part1.v_active = height & 0xff;
  696. dtd->part1.v_blank = v_blank_len & 0xff;
  697. dtd->part1.v_high = (((height >> 8) & 0xf) << 4) |
  698. ((v_blank_len >> 8) & 0xf);
  699. dtd->part2.h_sync_off = h_sync_offset & 0xff;
  700. dtd->part2.h_sync_width = h_sync_len & 0xff;
  701. dtd->part2.v_sync_off_width = (v_sync_offset & 0xf) << 4 |
  702. (v_sync_len & 0xf);
  703. dtd->part2.sync_off_width_high = ((h_sync_offset & 0x300) >> 2) |
  704. ((h_sync_len & 0x300) >> 4) | ((v_sync_offset & 0x30) >> 2) |
  705. ((v_sync_len & 0x30) >> 4);
  706. dtd->part2.dtd_flags = 0x18;
  707. if (mode->flags & DRM_MODE_FLAG_INTERLACE)
  708. dtd->part2.dtd_flags |= DTD_FLAG_INTERLACE;
  709. if (mode->flags & DRM_MODE_FLAG_PHSYNC)
  710. dtd->part2.dtd_flags |= DTD_FLAG_HSYNC_POSITIVE;
  711. if (mode->flags & DRM_MODE_FLAG_PVSYNC)
  712. dtd->part2.dtd_flags |= DTD_FLAG_VSYNC_POSITIVE;
  713. dtd->part2.sdvo_flags = 0;
  714. dtd->part2.v_sync_off_high = v_sync_offset & 0xc0;
  715. dtd->part2.reserved = 0;
  716. }
  717. static void intel_sdvo_get_mode_from_dtd(struct drm_display_mode * mode,
  718. const struct intel_sdvo_dtd *dtd)
  719. {
  720. mode->hdisplay = dtd->part1.h_active;
  721. mode->hdisplay += ((dtd->part1.h_high >> 4) & 0x0f) << 8;
  722. mode->hsync_start = mode->hdisplay + dtd->part2.h_sync_off;
  723. mode->hsync_start += (dtd->part2.sync_off_width_high & 0xc0) << 2;
  724. mode->hsync_end = mode->hsync_start + dtd->part2.h_sync_width;
  725. mode->hsync_end += (dtd->part2.sync_off_width_high & 0x30) << 4;
  726. mode->htotal = mode->hdisplay + dtd->part1.h_blank;
  727. mode->htotal += (dtd->part1.h_high & 0xf) << 8;
  728. mode->vdisplay = dtd->part1.v_active;
  729. mode->vdisplay += ((dtd->part1.v_high >> 4) & 0x0f) << 8;
  730. mode->vsync_start = mode->vdisplay;
  731. mode->vsync_start += (dtd->part2.v_sync_off_width >> 4) & 0xf;
  732. mode->vsync_start += (dtd->part2.sync_off_width_high & 0x0c) << 2;
  733. mode->vsync_start += dtd->part2.v_sync_off_high & 0xc0;
  734. mode->vsync_end = mode->vsync_start +
  735. (dtd->part2.v_sync_off_width & 0xf);
  736. mode->vsync_end += (dtd->part2.sync_off_width_high & 0x3) << 4;
  737. mode->vtotal = mode->vdisplay + dtd->part1.v_blank;
  738. mode->vtotal += (dtd->part1.v_high & 0xf) << 8;
  739. mode->clock = dtd->part1.clock * 10;
  740. mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC);
  741. if (dtd->part2.dtd_flags & DTD_FLAG_INTERLACE)
  742. mode->flags |= DRM_MODE_FLAG_INTERLACE;
  743. if (dtd->part2.dtd_flags & DTD_FLAG_HSYNC_POSITIVE)
  744. mode->flags |= DRM_MODE_FLAG_PHSYNC;
  745. if (dtd->part2.dtd_flags & DTD_FLAG_VSYNC_POSITIVE)
  746. mode->flags |= DRM_MODE_FLAG_PVSYNC;
  747. }
  748. static bool intel_sdvo_check_supp_encode(struct intel_sdvo *intel_sdvo)
  749. {
  750. struct intel_sdvo_encode encode;
  751. BUILD_BUG_ON(sizeof(encode) != 2);
  752. return intel_sdvo_get_value(intel_sdvo,
  753. SDVO_CMD_GET_SUPP_ENCODE,
  754. &encode, sizeof(encode));
  755. }
  756. static bool intel_sdvo_set_encode(struct intel_sdvo *intel_sdvo,
  757. uint8_t mode)
  758. {
  759. return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_ENCODE, &mode, 1);
  760. }
  761. static bool intel_sdvo_set_colorimetry(struct intel_sdvo *intel_sdvo,
  762. uint8_t mode)
  763. {
  764. return intel_sdvo_set_value(intel_sdvo, SDVO_CMD_SET_COLORIMETRY, &mode, 1);
  765. }
  766. #if 0
  767. static void intel_sdvo_dump_hdmi_buf(struct intel_sdvo *intel_sdvo)
  768. {
  769. int i, j;
  770. uint8_t set_buf_index[2];
  771. uint8_t av_split;
  772. uint8_t buf_size;
  773. uint8_t buf[48];
  774. uint8_t *pos;
  775. intel_sdvo_get_value(encoder, SDVO_CMD_GET_HBUF_AV_SPLIT, &av_split, 1);
  776. for (i = 0; i <= av_split; i++) {
  777. set_buf_index[0] = i; set_buf_index[1] = 0;
  778. intel_sdvo_write_cmd(encoder, SDVO_CMD_SET_HBUF_INDEX,
  779. set_buf_index, 2);
  780. intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_INFO, NULL, 0);
  781. intel_sdvo_read_response(encoder, &buf_size, 1);
  782. pos = buf;
  783. for (j = 0; j <= buf_size; j += 8) {
  784. intel_sdvo_write_cmd(encoder, SDVO_CMD_GET_HBUF_DATA,
  785. NULL, 0);
  786. intel_sdvo_read_response(encoder, pos, 8);
  787. pos += 8;
  788. }
  789. }
  790. }
  791. #endif
  792. static bool intel_sdvo_write_infoframe(struct intel_sdvo *intel_sdvo,
  793. unsigned if_index, uint8_t tx_rate,
  794. uint8_t *data, unsigned length)
  795. {
  796. uint8_t set_buf_index[2] = { if_index, 0 };
  797. uint8_t hbuf_size, tmp[8];
  798. int i;
  799. if (!intel_sdvo_set_value(intel_sdvo,
  800. SDVO_CMD_SET_HBUF_INDEX,
  801. set_buf_index, 2))
  802. return false;
  803. if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HBUF_INFO,
  804. &hbuf_size, 1))
  805. return false;
  806. /* Buffer size is 0 based, hooray! */
  807. hbuf_size++;
  808. DRM_DEBUG_KMS("writing sdvo hbuf: %i, hbuf_size %i, hbuf_size: %i\n",
  809. if_index, length, hbuf_size);
  810. for (i = 0; i < hbuf_size; i += 8) {
  811. memset(tmp, 0, 8);
  812. if (i < length)
  813. memcpy(tmp, data + i, min_t(unsigned, 8, length - i));
  814. if (!intel_sdvo_set_value(intel_sdvo,
  815. SDVO_CMD_SET_HBUF_DATA,
  816. tmp, 8))
  817. return false;
  818. }
  819. return intel_sdvo_set_value(intel_sdvo,
  820. SDVO_CMD_SET_HBUF_TXRATE,
  821. &tx_rate, 1);
  822. }
  823. static bool intel_sdvo_set_avi_infoframe(struct intel_sdvo *intel_sdvo,
  824. const struct drm_display_mode *adjusted_mode)
  825. {
  826. struct dip_infoframe avi_if = {
  827. .type = DIP_TYPE_AVI,
  828. .ver = DIP_VERSION_AVI,
  829. .len = DIP_LEN_AVI,
  830. };
  831. uint8_t sdvo_data[4 + sizeof(avi_if.body.avi)];
  832. struct intel_crtc *intel_crtc = to_intel_crtc(intel_sdvo->base.base.crtc);
  833. if (intel_sdvo->rgb_quant_range_selectable) {
  834. if (intel_crtc->config.limited_color_range)
  835. avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_LIMITED;
  836. else
  837. avi_if.body.avi.ITC_EC_Q_SC |= DIP_AVI_RGB_QUANT_RANGE_FULL;
  838. }
  839. avi_if.body.avi.VIC = drm_match_cea_mode(adjusted_mode);
  840. intel_dip_infoframe_csum(&avi_if);
  841. /* sdvo spec says that the ecc is handled by the hw, and it looks like
  842. * we must not send the ecc field, either. */
  843. memcpy(sdvo_data, &avi_if, 3);
  844. sdvo_data[3] = avi_if.checksum;
  845. memcpy(&sdvo_data[4], &avi_if.body, sizeof(avi_if.body.avi));
  846. return intel_sdvo_write_infoframe(intel_sdvo, SDVO_HBUF_INDEX_AVI_IF,
  847. SDVO_HBUF_TX_VSYNC,
  848. sdvo_data, sizeof(sdvo_data));
  849. }
  850. static bool intel_sdvo_set_tv_format(struct intel_sdvo *intel_sdvo)
  851. {
  852. struct intel_sdvo_tv_format format;
  853. uint32_t format_map;
  854. format_map = 1 << intel_sdvo->tv_format_index;
  855. memset(&format, 0, sizeof(format));
  856. memcpy(&format, &format_map, min(sizeof(format), sizeof(format_map)));
  857. BUILD_BUG_ON(sizeof(format) != 6);
  858. return intel_sdvo_set_value(intel_sdvo,
  859. SDVO_CMD_SET_TV_FORMAT,
  860. &format, sizeof(format));
  861. }
  862. static bool
  863. intel_sdvo_set_output_timings_from_mode(struct intel_sdvo *intel_sdvo,
  864. const struct drm_display_mode *mode)
  865. {
  866. struct intel_sdvo_dtd output_dtd;
  867. if (!intel_sdvo_set_target_output(intel_sdvo,
  868. intel_sdvo->attached_output))
  869. return false;
  870. intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
  871. if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
  872. return false;
  873. return true;
  874. }
  875. /* Asks the sdvo controller for the preferred input mode given the output mode.
  876. * Unfortunately we have to set up the full output mode to do that. */
  877. static bool
  878. intel_sdvo_get_preferred_input_mode(struct intel_sdvo *intel_sdvo,
  879. const struct drm_display_mode *mode,
  880. struct drm_display_mode *adjusted_mode)
  881. {
  882. struct intel_sdvo_dtd input_dtd;
  883. /* Reset the input timing to the screen. Assume always input 0. */
  884. if (!intel_sdvo_set_target_input(intel_sdvo))
  885. return false;
  886. if (!intel_sdvo_create_preferred_input_timing(intel_sdvo,
  887. mode->clock / 10,
  888. mode->hdisplay,
  889. mode->vdisplay))
  890. return false;
  891. if (!intel_sdvo_get_preferred_input_timing(intel_sdvo,
  892. &input_dtd))
  893. return false;
  894. intel_sdvo_get_mode_from_dtd(adjusted_mode, &input_dtd);
  895. intel_sdvo->dtd_sdvo_flags = input_dtd.part2.sdvo_flags;
  896. return true;
  897. }
  898. static bool intel_sdvo_compute_config(struct intel_encoder *encoder,
  899. struct intel_crtc_config *pipe_config)
  900. {
  901. struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
  902. struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
  903. struct drm_display_mode *mode = &pipe_config->requested_mode;
  904. DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n");
  905. pipe_config->pipe_bpp = 8*3;
  906. if (HAS_PCH_SPLIT(encoder->base.dev))
  907. pipe_config->has_pch_encoder = true;
  908. /* We need to construct preferred input timings based on our
  909. * output timings. To do that, we have to set the output
  910. * timings, even though this isn't really the right place in
  911. * the sequence to do it. Oh well.
  912. */
  913. if (intel_sdvo->is_tv) {
  914. if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo, mode))
  915. return false;
  916. (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
  917. mode,
  918. adjusted_mode);
  919. } else if (intel_sdvo->is_lvds) {
  920. if (!intel_sdvo_set_output_timings_from_mode(intel_sdvo,
  921. intel_sdvo->sdvo_lvds_fixed_mode))
  922. return false;
  923. (void) intel_sdvo_get_preferred_input_mode(intel_sdvo,
  924. mode,
  925. adjusted_mode);
  926. }
  927. /* Make the CRTC code factor in the SDVO pixel multiplier. The
  928. * SDVO device will factor out the multiplier during mode_set.
  929. */
  930. pipe_config->pixel_multiplier =
  931. intel_sdvo_get_pixel_multiplier(adjusted_mode);
  932. adjusted_mode->clock *= pipe_config->pixel_multiplier;
  933. if (intel_sdvo->color_range_auto) {
  934. /* See CEA-861-E - 5.1 Default Encoding Parameters */
  935. /* FIXME: This bit is only valid when using TMDS encoding and 8
  936. * bit per color mode. */
  937. if (intel_sdvo->has_hdmi_monitor &&
  938. drm_match_cea_mode(adjusted_mode) > 1)
  939. intel_sdvo->color_range = HDMI_COLOR_RANGE_16_235;
  940. else
  941. intel_sdvo->color_range = 0;
  942. }
  943. if (intel_sdvo->color_range)
  944. pipe_config->limited_color_range = true;
  945. return true;
  946. }
  947. static void intel_sdvo_mode_set(struct intel_encoder *intel_encoder)
  948. {
  949. struct drm_device *dev = intel_encoder->base.dev;
  950. struct drm_i915_private *dev_priv = dev->dev_private;
  951. struct drm_crtc *crtc = intel_encoder->base.crtc;
  952. struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
  953. struct drm_display_mode *adjusted_mode =
  954. &intel_crtc->config.adjusted_mode;
  955. struct drm_display_mode *mode = &intel_crtc->config.requested_mode;
  956. struct intel_sdvo *intel_sdvo = to_intel_sdvo(&intel_encoder->base);
  957. u32 sdvox;
  958. struct intel_sdvo_in_out_map in_out;
  959. struct intel_sdvo_dtd input_dtd, output_dtd;
  960. int rate;
  961. if (!mode)
  962. return;
  963. /* First, set the input mapping for the first input to our controlled
  964. * output. This is only correct if we're a single-input device, in
  965. * which case the first input is the output from the appropriate SDVO
  966. * channel on the motherboard. In a two-input device, the first input
  967. * will be SDVOB and the second SDVOC.
  968. */
  969. in_out.in0 = intel_sdvo->attached_output;
  970. in_out.in1 = 0;
  971. intel_sdvo_set_value(intel_sdvo,
  972. SDVO_CMD_SET_IN_OUT_MAP,
  973. &in_out, sizeof(in_out));
  974. /* Set the output timings to the screen */
  975. if (!intel_sdvo_set_target_output(intel_sdvo,
  976. intel_sdvo->attached_output))
  977. return;
  978. /* lvds has a special fixed output timing. */
  979. if (intel_sdvo->is_lvds)
  980. intel_sdvo_get_dtd_from_mode(&output_dtd,
  981. intel_sdvo->sdvo_lvds_fixed_mode);
  982. else
  983. intel_sdvo_get_dtd_from_mode(&output_dtd, mode);
  984. if (!intel_sdvo_set_output_timing(intel_sdvo, &output_dtd))
  985. DRM_INFO("Setting output timings on %s failed\n",
  986. SDVO_NAME(intel_sdvo));
  987. /* Set the input timing to the screen. Assume always input 0. */
  988. if (!intel_sdvo_set_target_input(intel_sdvo))
  989. return;
  990. if (intel_sdvo->has_hdmi_monitor) {
  991. intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_HDMI);
  992. intel_sdvo_set_colorimetry(intel_sdvo,
  993. SDVO_COLORIMETRY_RGB256);
  994. intel_sdvo_set_avi_infoframe(intel_sdvo, adjusted_mode);
  995. } else
  996. intel_sdvo_set_encode(intel_sdvo, SDVO_ENCODE_DVI);
  997. if (intel_sdvo->is_tv &&
  998. !intel_sdvo_set_tv_format(intel_sdvo))
  999. return;
  1000. /* We have tried to get input timing in mode_fixup, and filled into
  1001. * adjusted_mode.
  1002. */
  1003. intel_sdvo_get_dtd_from_mode(&input_dtd, adjusted_mode);
  1004. if (intel_sdvo->is_tv || intel_sdvo->is_lvds)
  1005. input_dtd.part2.sdvo_flags = intel_sdvo->dtd_sdvo_flags;
  1006. if (!intel_sdvo_set_input_timing(intel_sdvo, &input_dtd))
  1007. DRM_INFO("Setting input timings on %s failed\n",
  1008. SDVO_NAME(intel_sdvo));
  1009. switch (intel_crtc->config.pixel_multiplier) {
  1010. default:
  1011. case 1: rate = SDVO_CLOCK_RATE_MULT_1X; break;
  1012. case 2: rate = SDVO_CLOCK_RATE_MULT_2X; break;
  1013. case 4: rate = SDVO_CLOCK_RATE_MULT_4X; break;
  1014. }
  1015. if (!intel_sdvo_set_clock_rate_mult(intel_sdvo, rate))
  1016. return;
  1017. /* Set the SDVO control regs. */
  1018. if (INTEL_INFO(dev)->gen >= 4) {
  1019. /* The real mode polarity is set by the SDVO commands, using
  1020. * struct intel_sdvo_dtd. */
  1021. sdvox = SDVO_VSYNC_ACTIVE_HIGH | SDVO_HSYNC_ACTIVE_HIGH;
  1022. if (!HAS_PCH_SPLIT(dev) && intel_sdvo->is_hdmi)
  1023. sdvox |= intel_sdvo->color_range;
  1024. if (INTEL_INFO(dev)->gen < 5)
  1025. sdvox |= SDVO_BORDER_ENABLE;
  1026. } else {
  1027. sdvox = I915_READ(intel_sdvo->sdvo_reg);
  1028. switch (intel_sdvo->sdvo_reg) {
  1029. case GEN3_SDVOB:
  1030. sdvox &= SDVOB_PRESERVE_MASK;
  1031. break;
  1032. case GEN3_SDVOC:
  1033. sdvox &= SDVOC_PRESERVE_MASK;
  1034. break;
  1035. }
  1036. sdvox |= (9 << 19) | SDVO_BORDER_ENABLE;
  1037. }
  1038. if (INTEL_PCH_TYPE(dev) >= PCH_CPT)
  1039. sdvox |= SDVO_PIPE_SEL_CPT(intel_crtc->pipe);
  1040. else
  1041. sdvox |= SDVO_PIPE_SEL(intel_crtc->pipe);
  1042. if (intel_sdvo->has_hdmi_audio)
  1043. sdvox |= SDVO_AUDIO_ENABLE;
  1044. if (INTEL_INFO(dev)->gen >= 4) {
  1045. /* done in crtc_mode_set as the dpll_md reg must be written early */
  1046. } else if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) {
  1047. /* done in crtc_mode_set as it lives inside the dpll register */
  1048. } else {
  1049. sdvox |= (intel_crtc->config.pixel_multiplier - 1)
  1050. << SDVO_PORT_MULTIPLY_SHIFT;
  1051. }
  1052. if (input_dtd.part2.sdvo_flags & SDVO_NEED_TO_STALL &&
  1053. INTEL_INFO(dev)->gen < 5)
  1054. sdvox |= SDVO_STALL_SELECT;
  1055. intel_sdvo_write_sdvox(intel_sdvo, sdvox);
  1056. }
  1057. static bool intel_sdvo_connector_get_hw_state(struct intel_connector *connector)
  1058. {
  1059. struct intel_sdvo_connector *intel_sdvo_connector =
  1060. to_intel_sdvo_connector(&connector->base);
  1061. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(&connector->base);
  1062. u16 active_outputs;
  1063. intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
  1064. if (active_outputs & intel_sdvo_connector->output_flag)
  1065. return true;
  1066. else
  1067. return false;
  1068. }
  1069. static bool intel_sdvo_get_hw_state(struct intel_encoder *encoder,
  1070. enum pipe *pipe)
  1071. {
  1072. struct drm_device *dev = encoder->base.dev;
  1073. struct drm_i915_private *dev_priv = dev->dev_private;
  1074. struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
  1075. u16 active_outputs;
  1076. u32 tmp;
  1077. tmp = I915_READ(intel_sdvo->sdvo_reg);
  1078. intel_sdvo_get_active_outputs(intel_sdvo, &active_outputs);
  1079. if (!(tmp & SDVO_ENABLE) && (active_outputs == 0))
  1080. return false;
  1081. if (HAS_PCH_CPT(dev))
  1082. *pipe = PORT_TO_PIPE_CPT(tmp);
  1083. else
  1084. *pipe = PORT_TO_PIPE(tmp);
  1085. return true;
  1086. }
  1087. static void intel_disable_sdvo(struct intel_encoder *encoder)
  1088. {
  1089. struct drm_i915_private *dev_priv = encoder->base.dev->dev_private;
  1090. struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
  1091. u32 temp;
  1092. intel_sdvo_set_active_outputs(intel_sdvo, 0);
  1093. if (0)
  1094. intel_sdvo_set_encoder_power_state(intel_sdvo,
  1095. DRM_MODE_DPMS_OFF);
  1096. temp = I915_READ(intel_sdvo->sdvo_reg);
  1097. if ((temp & SDVO_ENABLE) != 0) {
  1098. /* HW workaround for IBX, we need to move the port to
  1099. * transcoder A before disabling it. */
  1100. if (HAS_PCH_IBX(encoder->base.dev)) {
  1101. struct drm_crtc *crtc = encoder->base.crtc;
  1102. int pipe = crtc ? to_intel_crtc(crtc)->pipe : -1;
  1103. if (temp & SDVO_PIPE_B_SELECT) {
  1104. temp &= ~SDVO_PIPE_B_SELECT;
  1105. I915_WRITE(intel_sdvo->sdvo_reg, temp);
  1106. POSTING_READ(intel_sdvo->sdvo_reg);
  1107. /* Again we need to write this twice. */
  1108. I915_WRITE(intel_sdvo->sdvo_reg, temp);
  1109. POSTING_READ(intel_sdvo->sdvo_reg);
  1110. /* Transcoder selection bits only update
  1111. * effectively on vblank. */
  1112. if (crtc)
  1113. intel_wait_for_vblank(encoder->base.dev, pipe);
  1114. else
  1115. msleep(50);
  1116. }
  1117. }
  1118. intel_sdvo_write_sdvox(intel_sdvo, temp & ~SDVO_ENABLE);
  1119. }
  1120. }
  1121. static void intel_enable_sdvo(struct intel_encoder *encoder)
  1122. {
  1123. struct drm_device *dev = encoder->base.dev;
  1124. struct drm_i915_private *dev_priv = dev->dev_private;
  1125. struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
  1126. struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
  1127. u32 temp;
  1128. bool input1, input2;
  1129. int i;
  1130. u8 status;
  1131. temp = I915_READ(intel_sdvo->sdvo_reg);
  1132. if ((temp & SDVO_ENABLE) == 0) {
  1133. /* HW workaround for IBX, we need to move the port
  1134. * to transcoder A before disabling it, so restore it here. */
  1135. if (HAS_PCH_IBX(dev))
  1136. temp |= SDVO_PIPE_SEL(intel_crtc->pipe);
  1137. intel_sdvo_write_sdvox(intel_sdvo, temp | SDVO_ENABLE);
  1138. }
  1139. for (i = 0; i < 2; i++)
  1140. intel_wait_for_vblank(dev, intel_crtc->pipe);
  1141. status = intel_sdvo_get_trained_inputs(intel_sdvo, &input1, &input2);
  1142. /* Warn if the device reported failure to sync.
  1143. * A lot of SDVO devices fail to notify of sync, but it's
  1144. * a given it the status is a success, we succeeded.
  1145. */
  1146. if (status == SDVO_CMD_STATUS_SUCCESS && !input1) {
  1147. DRM_DEBUG_KMS("First %s output reported failure to "
  1148. "sync\n", SDVO_NAME(intel_sdvo));
  1149. }
  1150. if (0)
  1151. intel_sdvo_set_encoder_power_state(intel_sdvo,
  1152. DRM_MODE_DPMS_ON);
  1153. intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
  1154. }
  1155. static void intel_sdvo_dpms(struct drm_connector *connector, int mode)
  1156. {
  1157. struct drm_crtc *crtc;
  1158. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1159. /* dvo supports only 2 dpms states. */
  1160. if (mode != DRM_MODE_DPMS_ON)
  1161. mode = DRM_MODE_DPMS_OFF;
  1162. if (mode == connector->dpms)
  1163. return;
  1164. connector->dpms = mode;
  1165. /* Only need to change hw state when actually enabled */
  1166. crtc = intel_sdvo->base.base.crtc;
  1167. if (!crtc) {
  1168. intel_sdvo->base.connectors_active = false;
  1169. return;
  1170. }
  1171. if (mode != DRM_MODE_DPMS_ON) {
  1172. intel_sdvo_set_active_outputs(intel_sdvo, 0);
  1173. if (0)
  1174. intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
  1175. intel_sdvo->base.connectors_active = false;
  1176. intel_crtc_update_dpms(crtc);
  1177. } else {
  1178. intel_sdvo->base.connectors_active = true;
  1179. intel_crtc_update_dpms(crtc);
  1180. if (0)
  1181. intel_sdvo_set_encoder_power_state(intel_sdvo, mode);
  1182. intel_sdvo_set_active_outputs(intel_sdvo, intel_sdvo->attached_output);
  1183. }
  1184. intel_modeset_check_state(connector->dev);
  1185. }
  1186. static int intel_sdvo_mode_valid(struct drm_connector *connector,
  1187. struct drm_display_mode *mode)
  1188. {
  1189. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1190. if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
  1191. return MODE_NO_DBLESCAN;
  1192. if (intel_sdvo->pixel_clock_min > mode->clock)
  1193. return MODE_CLOCK_LOW;
  1194. if (intel_sdvo->pixel_clock_max < mode->clock)
  1195. return MODE_CLOCK_HIGH;
  1196. if (intel_sdvo->is_lvds) {
  1197. if (mode->hdisplay > intel_sdvo->sdvo_lvds_fixed_mode->hdisplay)
  1198. return MODE_PANEL;
  1199. if (mode->vdisplay > intel_sdvo->sdvo_lvds_fixed_mode->vdisplay)
  1200. return MODE_PANEL;
  1201. }
  1202. return MODE_OK;
  1203. }
  1204. static bool intel_sdvo_get_capabilities(struct intel_sdvo *intel_sdvo, struct intel_sdvo_caps *caps)
  1205. {
  1206. BUILD_BUG_ON(sizeof(*caps) != 8);
  1207. if (!intel_sdvo_get_value(intel_sdvo,
  1208. SDVO_CMD_GET_DEVICE_CAPS,
  1209. caps, sizeof(*caps)))
  1210. return false;
  1211. DRM_DEBUG_KMS("SDVO capabilities:\n"
  1212. " vendor_id: %d\n"
  1213. " device_id: %d\n"
  1214. " device_rev_id: %d\n"
  1215. " sdvo_version_major: %d\n"
  1216. " sdvo_version_minor: %d\n"
  1217. " sdvo_inputs_mask: %d\n"
  1218. " smooth_scaling: %d\n"
  1219. " sharp_scaling: %d\n"
  1220. " up_scaling: %d\n"
  1221. " down_scaling: %d\n"
  1222. " stall_support: %d\n"
  1223. " output_flags: %d\n",
  1224. caps->vendor_id,
  1225. caps->device_id,
  1226. caps->device_rev_id,
  1227. caps->sdvo_version_major,
  1228. caps->sdvo_version_minor,
  1229. caps->sdvo_inputs_mask,
  1230. caps->smooth_scaling,
  1231. caps->sharp_scaling,
  1232. caps->up_scaling,
  1233. caps->down_scaling,
  1234. caps->stall_support,
  1235. caps->output_flags);
  1236. return true;
  1237. }
  1238. static uint16_t intel_sdvo_get_hotplug_support(struct intel_sdvo *intel_sdvo)
  1239. {
  1240. struct drm_device *dev = intel_sdvo->base.base.dev;
  1241. uint16_t hotplug;
  1242. /* HW Erratum: SDVO Hotplug is broken on all i945G chips, there's noise
  1243. * on the line. */
  1244. if (IS_I945G(dev) || IS_I945GM(dev))
  1245. return 0;
  1246. if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_HOT_PLUG_SUPPORT,
  1247. &hotplug, sizeof(hotplug)))
  1248. return 0;
  1249. return hotplug;
  1250. }
  1251. static void intel_sdvo_enable_hotplug(struct intel_encoder *encoder)
  1252. {
  1253. struct intel_sdvo *intel_sdvo = to_intel_sdvo(&encoder->base);
  1254. intel_sdvo_write_cmd(intel_sdvo, SDVO_CMD_SET_ACTIVE_HOT_PLUG,
  1255. &intel_sdvo->hotplug_active, 2);
  1256. }
  1257. static bool
  1258. intel_sdvo_multifunc_encoder(struct intel_sdvo *intel_sdvo)
  1259. {
  1260. /* Is there more than one type of output? */
  1261. return hweight16(intel_sdvo->caps.output_flags) > 1;
  1262. }
  1263. static struct edid *
  1264. intel_sdvo_get_edid(struct drm_connector *connector)
  1265. {
  1266. struct intel_sdvo *sdvo = intel_attached_sdvo(connector);
  1267. return drm_get_edid(connector, &sdvo->ddc);
  1268. }
  1269. /* Mac mini hack -- use the same DDC as the analog connector */
  1270. static struct edid *
  1271. intel_sdvo_get_analog_edid(struct drm_connector *connector)
  1272. {
  1273. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  1274. return drm_get_edid(connector,
  1275. intel_gmbus_get_adapter(dev_priv,
  1276. dev_priv->crt_ddc_pin));
  1277. }
  1278. static enum drm_connector_status
  1279. intel_sdvo_tmds_sink_detect(struct drm_connector *connector)
  1280. {
  1281. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1282. enum drm_connector_status status;
  1283. struct edid *edid;
  1284. edid = intel_sdvo_get_edid(connector);
  1285. if (edid == NULL && intel_sdvo_multifunc_encoder(intel_sdvo)) {
  1286. u8 ddc, saved_ddc = intel_sdvo->ddc_bus;
  1287. /*
  1288. * Don't use the 1 as the argument of DDC bus switch to get
  1289. * the EDID. It is used for SDVO SPD ROM.
  1290. */
  1291. for (ddc = intel_sdvo->ddc_bus >> 1; ddc > 1; ddc >>= 1) {
  1292. intel_sdvo->ddc_bus = ddc;
  1293. edid = intel_sdvo_get_edid(connector);
  1294. if (edid)
  1295. break;
  1296. }
  1297. /*
  1298. * If we found the EDID on the other bus,
  1299. * assume that is the correct DDC bus.
  1300. */
  1301. if (edid == NULL)
  1302. intel_sdvo->ddc_bus = saved_ddc;
  1303. }
  1304. /*
  1305. * When there is no edid and no monitor is connected with VGA
  1306. * port, try to use the CRT ddc to read the EDID for DVI-connector.
  1307. */
  1308. if (edid == NULL)
  1309. edid = intel_sdvo_get_analog_edid(connector);
  1310. status = connector_status_unknown;
  1311. if (edid != NULL) {
  1312. /* DDC bus is shared, match EDID to connector type */
  1313. if (edid->input & DRM_EDID_INPUT_DIGITAL) {
  1314. status = connector_status_connected;
  1315. if (intel_sdvo->is_hdmi) {
  1316. intel_sdvo->has_hdmi_monitor = drm_detect_hdmi_monitor(edid);
  1317. intel_sdvo->has_hdmi_audio = drm_detect_monitor_audio(edid);
  1318. intel_sdvo->rgb_quant_range_selectable =
  1319. drm_rgb_quant_range_selectable(edid);
  1320. }
  1321. } else
  1322. status = connector_status_disconnected;
  1323. kfree(edid);
  1324. }
  1325. if (status == connector_status_connected) {
  1326. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1327. if (intel_sdvo_connector->force_audio != HDMI_AUDIO_AUTO)
  1328. intel_sdvo->has_hdmi_audio = (intel_sdvo_connector->force_audio == HDMI_AUDIO_ON);
  1329. }
  1330. return status;
  1331. }
  1332. static bool
  1333. intel_sdvo_connector_matches_edid(struct intel_sdvo_connector *sdvo,
  1334. struct edid *edid)
  1335. {
  1336. bool monitor_is_digital = !!(edid->input & DRM_EDID_INPUT_DIGITAL);
  1337. bool connector_is_digital = !!IS_DIGITAL(sdvo);
  1338. DRM_DEBUG_KMS("connector_is_digital? %d, monitor_is_digital? %d\n",
  1339. connector_is_digital, monitor_is_digital);
  1340. return connector_is_digital == monitor_is_digital;
  1341. }
  1342. static enum drm_connector_status
  1343. intel_sdvo_detect(struct drm_connector *connector, bool force)
  1344. {
  1345. uint16_t response;
  1346. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1347. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1348. enum drm_connector_status ret;
  1349. if (!intel_sdvo_get_value(intel_sdvo,
  1350. SDVO_CMD_GET_ATTACHED_DISPLAYS,
  1351. &response, 2))
  1352. return connector_status_unknown;
  1353. DRM_DEBUG_KMS("SDVO response %d %d [%x]\n",
  1354. response & 0xff, response >> 8,
  1355. intel_sdvo_connector->output_flag);
  1356. if (response == 0)
  1357. return connector_status_disconnected;
  1358. intel_sdvo->attached_output = response;
  1359. intel_sdvo->has_hdmi_monitor = false;
  1360. intel_sdvo->has_hdmi_audio = false;
  1361. intel_sdvo->rgb_quant_range_selectable = false;
  1362. if ((intel_sdvo_connector->output_flag & response) == 0)
  1363. ret = connector_status_disconnected;
  1364. else if (IS_TMDS(intel_sdvo_connector))
  1365. ret = intel_sdvo_tmds_sink_detect(connector);
  1366. else {
  1367. struct edid *edid;
  1368. /* if we have an edid check it matches the connection */
  1369. edid = intel_sdvo_get_edid(connector);
  1370. if (edid == NULL)
  1371. edid = intel_sdvo_get_analog_edid(connector);
  1372. if (edid != NULL) {
  1373. if (intel_sdvo_connector_matches_edid(intel_sdvo_connector,
  1374. edid))
  1375. ret = connector_status_connected;
  1376. else
  1377. ret = connector_status_disconnected;
  1378. kfree(edid);
  1379. } else
  1380. ret = connector_status_connected;
  1381. }
  1382. /* May update encoder flag for like clock for SDVO TV, etc.*/
  1383. if (ret == connector_status_connected) {
  1384. intel_sdvo->is_tv = false;
  1385. intel_sdvo->is_lvds = false;
  1386. intel_sdvo->base.needs_tv_clock = false;
  1387. if (response & SDVO_TV_MASK) {
  1388. intel_sdvo->is_tv = true;
  1389. intel_sdvo->base.needs_tv_clock = true;
  1390. }
  1391. if (response & SDVO_LVDS_MASK)
  1392. intel_sdvo->is_lvds = intel_sdvo->sdvo_lvds_fixed_mode != NULL;
  1393. }
  1394. return ret;
  1395. }
  1396. static void intel_sdvo_get_ddc_modes(struct drm_connector *connector)
  1397. {
  1398. struct edid *edid;
  1399. /* set the bus switch and get the modes */
  1400. edid = intel_sdvo_get_edid(connector);
  1401. /*
  1402. * Mac mini hack. On this device, the DVI-I connector shares one DDC
  1403. * link between analog and digital outputs. So, if the regular SDVO
  1404. * DDC fails, check to see if the analog output is disconnected, in
  1405. * which case we'll look there for the digital DDC data.
  1406. */
  1407. if (edid == NULL)
  1408. edid = intel_sdvo_get_analog_edid(connector);
  1409. if (edid != NULL) {
  1410. if (intel_sdvo_connector_matches_edid(to_intel_sdvo_connector(connector),
  1411. edid)) {
  1412. drm_mode_connector_update_edid_property(connector, edid);
  1413. drm_add_edid_modes(connector, edid);
  1414. }
  1415. kfree(edid);
  1416. }
  1417. }
  1418. /*
  1419. * Set of SDVO TV modes.
  1420. * Note! This is in reply order (see loop in get_tv_modes).
  1421. * XXX: all 60Hz refresh?
  1422. */
  1423. static const struct drm_display_mode sdvo_tv_modes[] = {
  1424. { DRM_MODE("320x200", DRM_MODE_TYPE_DRIVER, 5815, 320, 321, 384,
  1425. 416, 0, 200, 201, 232, 233, 0,
  1426. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1427. { DRM_MODE("320x240", DRM_MODE_TYPE_DRIVER, 6814, 320, 321, 384,
  1428. 416, 0, 240, 241, 272, 273, 0,
  1429. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1430. { DRM_MODE("400x300", DRM_MODE_TYPE_DRIVER, 9910, 400, 401, 464,
  1431. 496, 0, 300, 301, 332, 333, 0,
  1432. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1433. { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 16913, 640, 641, 704,
  1434. 736, 0, 350, 351, 382, 383, 0,
  1435. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1436. { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 19121, 640, 641, 704,
  1437. 736, 0, 400, 401, 432, 433, 0,
  1438. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1439. { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 22654, 640, 641, 704,
  1440. 736, 0, 480, 481, 512, 513, 0,
  1441. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1442. { DRM_MODE("704x480", DRM_MODE_TYPE_DRIVER, 24624, 704, 705, 768,
  1443. 800, 0, 480, 481, 512, 513, 0,
  1444. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1445. { DRM_MODE("704x576", DRM_MODE_TYPE_DRIVER, 29232, 704, 705, 768,
  1446. 800, 0, 576, 577, 608, 609, 0,
  1447. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1448. { DRM_MODE("720x350", DRM_MODE_TYPE_DRIVER, 18751, 720, 721, 784,
  1449. 816, 0, 350, 351, 382, 383, 0,
  1450. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1451. { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 21199, 720, 721, 784,
  1452. 816, 0, 400, 401, 432, 433, 0,
  1453. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1454. { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 25116, 720, 721, 784,
  1455. 816, 0, 480, 481, 512, 513, 0,
  1456. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1457. { DRM_MODE("720x540", DRM_MODE_TYPE_DRIVER, 28054, 720, 721, 784,
  1458. 816, 0, 540, 541, 572, 573, 0,
  1459. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1460. { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 29816, 720, 721, 784,
  1461. 816, 0, 576, 577, 608, 609, 0,
  1462. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1463. { DRM_MODE("768x576", DRM_MODE_TYPE_DRIVER, 31570, 768, 769, 832,
  1464. 864, 0, 576, 577, 608, 609, 0,
  1465. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1466. { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 34030, 800, 801, 864,
  1467. 896, 0, 600, 601, 632, 633, 0,
  1468. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1469. { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 36581, 832, 833, 896,
  1470. 928, 0, 624, 625, 656, 657, 0,
  1471. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1472. { DRM_MODE("920x766", DRM_MODE_TYPE_DRIVER, 48707, 920, 921, 984,
  1473. 1016, 0, 766, 767, 798, 799, 0,
  1474. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1475. { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 53827, 1024, 1025, 1088,
  1476. 1120, 0, 768, 769, 800, 801, 0,
  1477. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1478. { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 87265, 1280, 1281, 1344,
  1479. 1376, 0, 1024, 1025, 1056, 1057, 0,
  1480. DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) },
  1481. };
  1482. static void intel_sdvo_get_tv_modes(struct drm_connector *connector)
  1483. {
  1484. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1485. struct intel_sdvo_sdtv_resolution_request tv_res;
  1486. uint32_t reply = 0, format_map = 0;
  1487. int i;
  1488. /* Read the list of supported input resolutions for the selected TV
  1489. * format.
  1490. */
  1491. format_map = 1 << intel_sdvo->tv_format_index;
  1492. memcpy(&tv_res, &format_map,
  1493. min(sizeof(format_map), sizeof(struct intel_sdvo_sdtv_resolution_request)));
  1494. if (!intel_sdvo_set_target_output(intel_sdvo, intel_sdvo->attached_output))
  1495. return;
  1496. BUILD_BUG_ON(sizeof(tv_res) != 3);
  1497. if (!intel_sdvo_write_cmd(intel_sdvo,
  1498. SDVO_CMD_GET_SDTV_RESOLUTION_SUPPORT,
  1499. &tv_res, sizeof(tv_res)))
  1500. return;
  1501. if (!intel_sdvo_read_response(intel_sdvo, &reply, 3))
  1502. return;
  1503. for (i = 0; i < ARRAY_SIZE(sdvo_tv_modes); i++)
  1504. if (reply & (1 << i)) {
  1505. struct drm_display_mode *nmode;
  1506. nmode = drm_mode_duplicate(connector->dev,
  1507. &sdvo_tv_modes[i]);
  1508. if (nmode)
  1509. drm_mode_probed_add(connector, nmode);
  1510. }
  1511. }
  1512. static void intel_sdvo_get_lvds_modes(struct drm_connector *connector)
  1513. {
  1514. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1515. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  1516. struct drm_display_mode *newmode;
  1517. /*
  1518. * Attempt to get the mode list from DDC.
  1519. * Assume that the preferred modes are
  1520. * arranged in priority order.
  1521. */
  1522. intel_ddc_get_modes(connector, &intel_sdvo->ddc);
  1523. if (list_empty(&connector->probed_modes) == false)
  1524. goto end;
  1525. /* Fetch modes from VBT */
  1526. if (dev_priv->sdvo_lvds_vbt_mode != NULL) {
  1527. newmode = drm_mode_duplicate(connector->dev,
  1528. dev_priv->sdvo_lvds_vbt_mode);
  1529. if (newmode != NULL) {
  1530. /* Guarantee the mode is preferred */
  1531. newmode->type = (DRM_MODE_TYPE_PREFERRED |
  1532. DRM_MODE_TYPE_DRIVER);
  1533. drm_mode_probed_add(connector, newmode);
  1534. }
  1535. }
  1536. end:
  1537. list_for_each_entry(newmode, &connector->probed_modes, head) {
  1538. if (newmode->type & DRM_MODE_TYPE_PREFERRED) {
  1539. intel_sdvo->sdvo_lvds_fixed_mode =
  1540. drm_mode_duplicate(connector->dev, newmode);
  1541. intel_sdvo->is_lvds = true;
  1542. break;
  1543. }
  1544. }
  1545. }
  1546. static int intel_sdvo_get_modes(struct drm_connector *connector)
  1547. {
  1548. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1549. if (IS_TV(intel_sdvo_connector))
  1550. intel_sdvo_get_tv_modes(connector);
  1551. else if (IS_LVDS(intel_sdvo_connector))
  1552. intel_sdvo_get_lvds_modes(connector);
  1553. else
  1554. intel_sdvo_get_ddc_modes(connector);
  1555. return !list_empty(&connector->probed_modes);
  1556. }
  1557. static void
  1558. intel_sdvo_destroy_enhance_property(struct drm_connector *connector)
  1559. {
  1560. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1561. struct drm_device *dev = connector->dev;
  1562. if (intel_sdvo_connector->left)
  1563. drm_property_destroy(dev, intel_sdvo_connector->left);
  1564. if (intel_sdvo_connector->right)
  1565. drm_property_destroy(dev, intel_sdvo_connector->right);
  1566. if (intel_sdvo_connector->top)
  1567. drm_property_destroy(dev, intel_sdvo_connector->top);
  1568. if (intel_sdvo_connector->bottom)
  1569. drm_property_destroy(dev, intel_sdvo_connector->bottom);
  1570. if (intel_sdvo_connector->hpos)
  1571. drm_property_destroy(dev, intel_sdvo_connector->hpos);
  1572. if (intel_sdvo_connector->vpos)
  1573. drm_property_destroy(dev, intel_sdvo_connector->vpos);
  1574. if (intel_sdvo_connector->saturation)
  1575. drm_property_destroy(dev, intel_sdvo_connector->saturation);
  1576. if (intel_sdvo_connector->contrast)
  1577. drm_property_destroy(dev, intel_sdvo_connector->contrast);
  1578. if (intel_sdvo_connector->hue)
  1579. drm_property_destroy(dev, intel_sdvo_connector->hue);
  1580. if (intel_sdvo_connector->sharpness)
  1581. drm_property_destroy(dev, intel_sdvo_connector->sharpness);
  1582. if (intel_sdvo_connector->flicker_filter)
  1583. drm_property_destroy(dev, intel_sdvo_connector->flicker_filter);
  1584. if (intel_sdvo_connector->flicker_filter_2d)
  1585. drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_2d);
  1586. if (intel_sdvo_connector->flicker_filter_adaptive)
  1587. drm_property_destroy(dev, intel_sdvo_connector->flicker_filter_adaptive);
  1588. if (intel_sdvo_connector->tv_luma_filter)
  1589. drm_property_destroy(dev, intel_sdvo_connector->tv_luma_filter);
  1590. if (intel_sdvo_connector->tv_chroma_filter)
  1591. drm_property_destroy(dev, intel_sdvo_connector->tv_chroma_filter);
  1592. if (intel_sdvo_connector->dot_crawl)
  1593. drm_property_destroy(dev, intel_sdvo_connector->dot_crawl);
  1594. if (intel_sdvo_connector->brightness)
  1595. drm_property_destroy(dev, intel_sdvo_connector->brightness);
  1596. }
  1597. static void intel_sdvo_destroy(struct drm_connector *connector)
  1598. {
  1599. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1600. if (intel_sdvo_connector->tv_format)
  1601. drm_property_destroy(connector->dev,
  1602. intel_sdvo_connector->tv_format);
  1603. intel_sdvo_destroy_enhance_property(connector);
  1604. drm_sysfs_connector_remove(connector);
  1605. drm_connector_cleanup(connector);
  1606. kfree(intel_sdvo_connector);
  1607. }
  1608. static bool intel_sdvo_detect_hdmi_audio(struct drm_connector *connector)
  1609. {
  1610. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1611. struct edid *edid;
  1612. bool has_audio = false;
  1613. if (!intel_sdvo->is_hdmi)
  1614. return false;
  1615. edid = intel_sdvo_get_edid(connector);
  1616. if (edid != NULL && edid->input & DRM_EDID_INPUT_DIGITAL)
  1617. has_audio = drm_detect_monitor_audio(edid);
  1618. kfree(edid);
  1619. return has_audio;
  1620. }
  1621. static int
  1622. intel_sdvo_set_property(struct drm_connector *connector,
  1623. struct drm_property *property,
  1624. uint64_t val)
  1625. {
  1626. struct intel_sdvo *intel_sdvo = intel_attached_sdvo(connector);
  1627. struct intel_sdvo_connector *intel_sdvo_connector = to_intel_sdvo_connector(connector);
  1628. struct drm_i915_private *dev_priv = connector->dev->dev_private;
  1629. uint16_t temp_value;
  1630. uint8_t cmd;
  1631. int ret;
  1632. ret = drm_object_property_set_value(&connector->base, property, val);
  1633. if (ret)
  1634. return ret;
  1635. if (property == dev_priv->force_audio_property) {
  1636. int i = val;
  1637. bool has_audio;
  1638. if (i == intel_sdvo_connector->force_audio)
  1639. return 0;
  1640. intel_sdvo_connector->force_audio = i;
  1641. if (i == HDMI_AUDIO_AUTO)
  1642. has_audio = intel_sdvo_detect_hdmi_audio(connector);
  1643. else
  1644. has_audio = (i == HDMI_AUDIO_ON);
  1645. if (has_audio == intel_sdvo->has_hdmi_audio)
  1646. return 0;
  1647. intel_sdvo->has_hdmi_audio = has_audio;
  1648. goto done;
  1649. }
  1650. if (property == dev_priv->broadcast_rgb_property) {
  1651. bool old_auto = intel_sdvo->color_range_auto;
  1652. uint32_t old_range = intel_sdvo->color_range;
  1653. switch (val) {
  1654. case INTEL_BROADCAST_RGB_AUTO:
  1655. intel_sdvo->color_range_auto = true;
  1656. break;
  1657. case INTEL_BROADCAST_RGB_FULL:
  1658. intel_sdvo->color_range_auto = false;
  1659. intel_sdvo->color_range = 0;
  1660. break;
  1661. case INTEL_BROADCAST_RGB_LIMITED:
  1662. intel_sdvo->color_range_auto = false;
  1663. /* FIXME: this bit is only valid when using TMDS
  1664. * encoding and 8 bit per color mode. */
  1665. intel_sdvo->color_range = HDMI_COLOR_RANGE_16_235;
  1666. break;
  1667. default:
  1668. return -EINVAL;
  1669. }
  1670. if (old_auto == intel_sdvo->color_range_auto &&
  1671. old_range == intel_sdvo->color_range)
  1672. return 0;
  1673. goto done;
  1674. }
  1675. #define CHECK_PROPERTY(name, NAME) \
  1676. if (intel_sdvo_connector->name == property) { \
  1677. if (intel_sdvo_connector->cur_##name == temp_value) return 0; \
  1678. if (intel_sdvo_connector->max_##name < temp_value) return -EINVAL; \
  1679. cmd = SDVO_CMD_SET_##NAME; \
  1680. intel_sdvo_connector->cur_##name = temp_value; \
  1681. goto set_value; \
  1682. }
  1683. if (property == intel_sdvo_connector->tv_format) {
  1684. if (val >= TV_FORMAT_NUM)
  1685. return -EINVAL;
  1686. if (intel_sdvo->tv_format_index ==
  1687. intel_sdvo_connector->tv_format_supported[val])
  1688. return 0;
  1689. intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[val];
  1690. goto done;
  1691. } else if (IS_TV_OR_LVDS(intel_sdvo_connector)) {
  1692. temp_value = val;
  1693. if (intel_sdvo_connector->left == property) {
  1694. drm_object_property_set_value(&connector->base,
  1695. intel_sdvo_connector->right, val);
  1696. if (intel_sdvo_connector->left_margin == temp_value)
  1697. return 0;
  1698. intel_sdvo_connector->left_margin = temp_value;
  1699. intel_sdvo_connector->right_margin = temp_value;
  1700. temp_value = intel_sdvo_connector->max_hscan -
  1701. intel_sdvo_connector->left_margin;
  1702. cmd = SDVO_CMD_SET_OVERSCAN_H;
  1703. goto set_value;
  1704. } else if (intel_sdvo_connector->right == property) {
  1705. drm_object_property_set_value(&connector->base,
  1706. intel_sdvo_connector->left, val);
  1707. if (intel_sdvo_connector->right_margin == temp_value)
  1708. return 0;
  1709. intel_sdvo_connector->left_margin = temp_value;
  1710. intel_sdvo_connector->right_margin = temp_value;
  1711. temp_value = intel_sdvo_connector->max_hscan -
  1712. intel_sdvo_connector->left_margin;
  1713. cmd = SDVO_CMD_SET_OVERSCAN_H;
  1714. goto set_value;
  1715. } else if (intel_sdvo_connector->top == property) {
  1716. drm_object_property_set_value(&connector->base,
  1717. intel_sdvo_connector->bottom, val);
  1718. if (intel_sdvo_connector->top_margin == temp_value)
  1719. return 0;
  1720. intel_sdvo_connector->top_margin = temp_value;
  1721. intel_sdvo_connector->bottom_margin = temp_value;
  1722. temp_value = intel_sdvo_connector->max_vscan -
  1723. intel_sdvo_connector->top_margin;
  1724. cmd = SDVO_CMD_SET_OVERSCAN_V;
  1725. goto set_value;
  1726. } else if (intel_sdvo_connector->bottom == property) {
  1727. drm_object_property_set_value(&connector->base,
  1728. intel_sdvo_connector->top, val);
  1729. if (intel_sdvo_connector->bottom_margin == temp_value)
  1730. return 0;
  1731. intel_sdvo_connector->top_margin = temp_value;
  1732. intel_sdvo_connector->bottom_margin = temp_value;
  1733. temp_value = intel_sdvo_connector->max_vscan -
  1734. intel_sdvo_connector->top_margin;
  1735. cmd = SDVO_CMD_SET_OVERSCAN_V;
  1736. goto set_value;
  1737. }
  1738. CHECK_PROPERTY(hpos, HPOS)
  1739. CHECK_PROPERTY(vpos, VPOS)
  1740. CHECK_PROPERTY(saturation, SATURATION)
  1741. CHECK_PROPERTY(contrast, CONTRAST)
  1742. CHECK_PROPERTY(hue, HUE)
  1743. CHECK_PROPERTY(brightness, BRIGHTNESS)
  1744. CHECK_PROPERTY(sharpness, SHARPNESS)
  1745. CHECK_PROPERTY(flicker_filter, FLICKER_FILTER)
  1746. CHECK_PROPERTY(flicker_filter_2d, FLICKER_FILTER_2D)
  1747. CHECK_PROPERTY(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE)
  1748. CHECK_PROPERTY(tv_chroma_filter, TV_CHROMA_FILTER)
  1749. CHECK_PROPERTY(tv_luma_filter, TV_LUMA_FILTER)
  1750. CHECK_PROPERTY(dot_crawl, DOT_CRAWL)
  1751. }
  1752. return -EINVAL; /* unknown property */
  1753. set_value:
  1754. if (!intel_sdvo_set_value(intel_sdvo, cmd, &temp_value, 2))
  1755. return -EIO;
  1756. done:
  1757. if (intel_sdvo->base.base.crtc)
  1758. intel_crtc_restore_mode(intel_sdvo->base.base.crtc);
  1759. return 0;
  1760. #undef CHECK_PROPERTY
  1761. }
  1762. static const struct drm_connector_funcs intel_sdvo_connector_funcs = {
  1763. .dpms = intel_sdvo_dpms,
  1764. .detect = intel_sdvo_detect,
  1765. .fill_modes = drm_helper_probe_single_connector_modes,
  1766. .set_property = intel_sdvo_set_property,
  1767. .destroy = intel_sdvo_destroy,
  1768. };
  1769. static const struct drm_connector_helper_funcs intel_sdvo_connector_helper_funcs = {
  1770. .get_modes = intel_sdvo_get_modes,
  1771. .mode_valid = intel_sdvo_mode_valid,
  1772. .best_encoder = intel_best_encoder,
  1773. };
  1774. static void intel_sdvo_enc_destroy(struct drm_encoder *encoder)
  1775. {
  1776. struct intel_sdvo *intel_sdvo = to_intel_sdvo(encoder);
  1777. if (intel_sdvo->sdvo_lvds_fixed_mode != NULL)
  1778. drm_mode_destroy(encoder->dev,
  1779. intel_sdvo->sdvo_lvds_fixed_mode);
  1780. i2c_del_adapter(&intel_sdvo->ddc);
  1781. intel_encoder_destroy(encoder);
  1782. }
  1783. static const struct drm_encoder_funcs intel_sdvo_enc_funcs = {
  1784. .destroy = intel_sdvo_enc_destroy,
  1785. };
  1786. static void
  1787. intel_sdvo_guess_ddc_bus(struct intel_sdvo *sdvo)
  1788. {
  1789. uint16_t mask = 0;
  1790. unsigned int num_bits;
  1791. /* Make a mask of outputs less than or equal to our own priority in the
  1792. * list.
  1793. */
  1794. switch (sdvo->controlled_output) {
  1795. case SDVO_OUTPUT_LVDS1:
  1796. mask |= SDVO_OUTPUT_LVDS1;
  1797. case SDVO_OUTPUT_LVDS0:
  1798. mask |= SDVO_OUTPUT_LVDS0;
  1799. case SDVO_OUTPUT_TMDS1:
  1800. mask |= SDVO_OUTPUT_TMDS1;
  1801. case SDVO_OUTPUT_TMDS0:
  1802. mask |= SDVO_OUTPUT_TMDS0;
  1803. case SDVO_OUTPUT_RGB1:
  1804. mask |= SDVO_OUTPUT_RGB1;
  1805. case SDVO_OUTPUT_RGB0:
  1806. mask |= SDVO_OUTPUT_RGB0;
  1807. break;
  1808. }
  1809. /* Count bits to find what number we are in the priority list. */
  1810. mask &= sdvo->caps.output_flags;
  1811. num_bits = hweight16(mask);
  1812. /* If more than 3 outputs, default to DDC bus 3 for now. */
  1813. if (num_bits > 3)
  1814. num_bits = 3;
  1815. /* Corresponds to SDVO_CONTROL_BUS_DDCx */
  1816. sdvo->ddc_bus = 1 << num_bits;
  1817. }
  1818. /**
  1819. * Choose the appropriate DDC bus for control bus switch command for this
  1820. * SDVO output based on the controlled output.
  1821. *
  1822. * DDC bus number assignment is in a priority order of RGB outputs, then TMDS
  1823. * outputs, then LVDS outputs.
  1824. */
  1825. static void
  1826. intel_sdvo_select_ddc_bus(struct drm_i915_private *dev_priv,
  1827. struct intel_sdvo *sdvo, u32 reg)
  1828. {
  1829. struct sdvo_device_mapping *mapping;
  1830. if (sdvo->is_sdvob)
  1831. mapping = &(dev_priv->sdvo_mappings[0]);
  1832. else
  1833. mapping = &(dev_priv->sdvo_mappings[1]);
  1834. if (mapping->initialized)
  1835. sdvo->ddc_bus = 1 << ((mapping->ddc_pin & 0xf0) >> 4);
  1836. else
  1837. intel_sdvo_guess_ddc_bus(sdvo);
  1838. }
  1839. static void
  1840. intel_sdvo_select_i2c_bus(struct drm_i915_private *dev_priv,
  1841. struct intel_sdvo *sdvo, u32 reg)
  1842. {
  1843. struct sdvo_device_mapping *mapping;
  1844. u8 pin;
  1845. if (sdvo->is_sdvob)
  1846. mapping = &dev_priv->sdvo_mappings[0];
  1847. else
  1848. mapping = &dev_priv->sdvo_mappings[1];
  1849. if (mapping->initialized && intel_gmbus_is_port_valid(mapping->i2c_pin))
  1850. pin = mapping->i2c_pin;
  1851. else
  1852. pin = GMBUS_PORT_DPB;
  1853. sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin);
  1854. /* With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow
  1855. * our code totally fails once we start using gmbus. Hence fall back to
  1856. * bit banging for now. */
  1857. intel_gmbus_force_bit(sdvo->i2c, true);
  1858. }
  1859. /* undo any changes intel_sdvo_select_i2c_bus() did to sdvo->i2c */
  1860. static void
  1861. intel_sdvo_unselect_i2c_bus(struct intel_sdvo *sdvo)
  1862. {
  1863. intel_gmbus_force_bit(sdvo->i2c, false);
  1864. }
  1865. static bool
  1866. intel_sdvo_is_hdmi_connector(struct intel_sdvo *intel_sdvo, int device)
  1867. {
  1868. return intel_sdvo_check_supp_encode(intel_sdvo);
  1869. }
  1870. static u8
  1871. intel_sdvo_get_slave_addr(struct drm_device *dev, struct intel_sdvo *sdvo)
  1872. {
  1873. struct drm_i915_private *dev_priv = dev->dev_private;
  1874. struct sdvo_device_mapping *my_mapping, *other_mapping;
  1875. if (sdvo->is_sdvob) {
  1876. my_mapping = &dev_priv->sdvo_mappings[0];
  1877. other_mapping = &dev_priv->sdvo_mappings[1];
  1878. } else {
  1879. my_mapping = &dev_priv->sdvo_mappings[1];
  1880. other_mapping = &dev_priv->sdvo_mappings[0];
  1881. }
  1882. /* If the BIOS described our SDVO device, take advantage of it. */
  1883. if (my_mapping->slave_addr)
  1884. return my_mapping->slave_addr;
  1885. /* If the BIOS only described a different SDVO device, use the
  1886. * address that it isn't using.
  1887. */
  1888. if (other_mapping->slave_addr) {
  1889. if (other_mapping->slave_addr == 0x70)
  1890. return 0x72;
  1891. else
  1892. return 0x70;
  1893. }
  1894. /* No SDVO device info is found for another DVO port,
  1895. * so use mapping assumption we had before BIOS parsing.
  1896. */
  1897. if (sdvo->is_sdvob)
  1898. return 0x70;
  1899. else
  1900. return 0x72;
  1901. }
  1902. static void
  1903. intel_sdvo_connector_init(struct intel_sdvo_connector *connector,
  1904. struct intel_sdvo *encoder)
  1905. {
  1906. drm_connector_init(encoder->base.base.dev,
  1907. &connector->base.base,
  1908. &intel_sdvo_connector_funcs,
  1909. connector->base.base.connector_type);
  1910. drm_connector_helper_add(&connector->base.base,
  1911. &intel_sdvo_connector_helper_funcs);
  1912. connector->base.base.interlace_allowed = 1;
  1913. connector->base.base.doublescan_allowed = 0;
  1914. connector->base.base.display_info.subpixel_order = SubPixelHorizontalRGB;
  1915. connector->base.get_hw_state = intel_sdvo_connector_get_hw_state;
  1916. intel_connector_attach_encoder(&connector->base, &encoder->base);
  1917. drm_sysfs_connector_add(&connector->base.base);
  1918. }
  1919. static void
  1920. intel_sdvo_add_hdmi_properties(struct intel_sdvo *intel_sdvo,
  1921. struct intel_sdvo_connector *connector)
  1922. {
  1923. struct drm_device *dev = connector->base.base.dev;
  1924. intel_attach_force_audio_property(&connector->base.base);
  1925. if (INTEL_INFO(dev)->gen >= 4 && IS_MOBILE(dev)) {
  1926. intel_attach_broadcast_rgb_property(&connector->base.base);
  1927. intel_sdvo->color_range_auto = true;
  1928. }
  1929. }
  1930. static bool
  1931. intel_sdvo_dvi_init(struct intel_sdvo *intel_sdvo, int device)
  1932. {
  1933. struct drm_encoder *encoder = &intel_sdvo->base.base;
  1934. struct drm_connector *connector;
  1935. struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
  1936. struct intel_connector *intel_connector;
  1937. struct intel_sdvo_connector *intel_sdvo_connector;
  1938. intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
  1939. if (!intel_sdvo_connector)
  1940. return false;
  1941. if (device == 0) {
  1942. intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS0;
  1943. intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS0;
  1944. } else if (device == 1) {
  1945. intel_sdvo->controlled_output |= SDVO_OUTPUT_TMDS1;
  1946. intel_sdvo_connector->output_flag = SDVO_OUTPUT_TMDS1;
  1947. }
  1948. intel_connector = &intel_sdvo_connector->base;
  1949. connector = &intel_connector->base;
  1950. if (intel_sdvo_get_hotplug_support(intel_sdvo) &
  1951. intel_sdvo_connector->output_flag) {
  1952. intel_sdvo->hotplug_active |= intel_sdvo_connector->output_flag;
  1953. /* Some SDVO devices have one-shot hotplug interrupts.
  1954. * Ensure that they get re-enabled when an interrupt happens.
  1955. */
  1956. intel_encoder->hot_plug = intel_sdvo_enable_hotplug;
  1957. intel_sdvo_enable_hotplug(intel_encoder);
  1958. } else {
  1959. intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
  1960. }
  1961. encoder->encoder_type = DRM_MODE_ENCODER_TMDS;
  1962. connector->connector_type = DRM_MODE_CONNECTOR_DVID;
  1963. if (intel_sdvo_is_hdmi_connector(intel_sdvo, device)) {
  1964. connector->connector_type = DRM_MODE_CONNECTOR_HDMIA;
  1965. intel_sdvo->is_hdmi = true;
  1966. }
  1967. intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
  1968. if (intel_sdvo->is_hdmi)
  1969. intel_sdvo_add_hdmi_properties(intel_sdvo, intel_sdvo_connector);
  1970. return true;
  1971. }
  1972. static bool
  1973. intel_sdvo_tv_init(struct intel_sdvo *intel_sdvo, int type)
  1974. {
  1975. struct drm_encoder *encoder = &intel_sdvo->base.base;
  1976. struct drm_connector *connector;
  1977. struct intel_connector *intel_connector;
  1978. struct intel_sdvo_connector *intel_sdvo_connector;
  1979. intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
  1980. if (!intel_sdvo_connector)
  1981. return false;
  1982. intel_connector = &intel_sdvo_connector->base;
  1983. connector = &intel_connector->base;
  1984. encoder->encoder_type = DRM_MODE_ENCODER_TVDAC;
  1985. connector->connector_type = DRM_MODE_CONNECTOR_SVIDEO;
  1986. intel_sdvo->controlled_output |= type;
  1987. intel_sdvo_connector->output_flag = type;
  1988. intel_sdvo->is_tv = true;
  1989. intel_sdvo->base.needs_tv_clock = true;
  1990. intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
  1991. if (!intel_sdvo_tv_create_property(intel_sdvo, intel_sdvo_connector, type))
  1992. goto err;
  1993. if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
  1994. goto err;
  1995. return true;
  1996. err:
  1997. intel_sdvo_destroy(connector);
  1998. return false;
  1999. }
  2000. static bool
  2001. intel_sdvo_analog_init(struct intel_sdvo *intel_sdvo, int device)
  2002. {
  2003. struct drm_encoder *encoder = &intel_sdvo->base.base;
  2004. struct drm_connector *connector;
  2005. struct intel_connector *intel_connector;
  2006. struct intel_sdvo_connector *intel_sdvo_connector;
  2007. intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
  2008. if (!intel_sdvo_connector)
  2009. return false;
  2010. intel_connector = &intel_sdvo_connector->base;
  2011. connector = &intel_connector->base;
  2012. intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
  2013. encoder->encoder_type = DRM_MODE_ENCODER_DAC;
  2014. connector->connector_type = DRM_MODE_CONNECTOR_VGA;
  2015. if (device == 0) {
  2016. intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB0;
  2017. intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB0;
  2018. } else if (device == 1) {
  2019. intel_sdvo->controlled_output |= SDVO_OUTPUT_RGB1;
  2020. intel_sdvo_connector->output_flag = SDVO_OUTPUT_RGB1;
  2021. }
  2022. intel_sdvo_connector_init(intel_sdvo_connector,
  2023. intel_sdvo);
  2024. return true;
  2025. }
  2026. static bool
  2027. intel_sdvo_lvds_init(struct intel_sdvo *intel_sdvo, int device)
  2028. {
  2029. struct drm_encoder *encoder = &intel_sdvo->base.base;
  2030. struct drm_connector *connector;
  2031. struct intel_connector *intel_connector;
  2032. struct intel_sdvo_connector *intel_sdvo_connector;
  2033. intel_sdvo_connector = kzalloc(sizeof(struct intel_sdvo_connector), GFP_KERNEL);
  2034. if (!intel_sdvo_connector)
  2035. return false;
  2036. intel_connector = &intel_sdvo_connector->base;
  2037. connector = &intel_connector->base;
  2038. encoder->encoder_type = DRM_MODE_ENCODER_LVDS;
  2039. connector->connector_type = DRM_MODE_CONNECTOR_LVDS;
  2040. if (device == 0) {
  2041. intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS0;
  2042. intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS0;
  2043. } else if (device == 1) {
  2044. intel_sdvo->controlled_output |= SDVO_OUTPUT_LVDS1;
  2045. intel_sdvo_connector->output_flag = SDVO_OUTPUT_LVDS1;
  2046. }
  2047. intel_sdvo_connector_init(intel_sdvo_connector, intel_sdvo);
  2048. if (!intel_sdvo_create_enhance_property(intel_sdvo, intel_sdvo_connector))
  2049. goto err;
  2050. return true;
  2051. err:
  2052. intel_sdvo_destroy(connector);
  2053. return false;
  2054. }
  2055. static bool
  2056. intel_sdvo_output_setup(struct intel_sdvo *intel_sdvo, uint16_t flags)
  2057. {
  2058. intel_sdvo->is_tv = false;
  2059. intel_sdvo->base.needs_tv_clock = false;
  2060. intel_sdvo->is_lvds = false;
  2061. /* SDVO requires XXX1 function may not exist unless it has XXX0 function.*/
  2062. if (flags & SDVO_OUTPUT_TMDS0)
  2063. if (!intel_sdvo_dvi_init(intel_sdvo, 0))
  2064. return false;
  2065. if ((flags & SDVO_TMDS_MASK) == SDVO_TMDS_MASK)
  2066. if (!intel_sdvo_dvi_init(intel_sdvo, 1))
  2067. return false;
  2068. /* TV has no XXX1 function block */
  2069. if (flags & SDVO_OUTPUT_SVID0)
  2070. if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_SVID0))
  2071. return false;
  2072. if (flags & SDVO_OUTPUT_CVBS0)
  2073. if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_CVBS0))
  2074. return false;
  2075. if (flags & SDVO_OUTPUT_YPRPB0)
  2076. if (!intel_sdvo_tv_init(intel_sdvo, SDVO_OUTPUT_YPRPB0))
  2077. return false;
  2078. if (flags & SDVO_OUTPUT_RGB0)
  2079. if (!intel_sdvo_analog_init(intel_sdvo, 0))
  2080. return false;
  2081. if ((flags & SDVO_RGB_MASK) == SDVO_RGB_MASK)
  2082. if (!intel_sdvo_analog_init(intel_sdvo, 1))
  2083. return false;
  2084. if (flags & SDVO_OUTPUT_LVDS0)
  2085. if (!intel_sdvo_lvds_init(intel_sdvo, 0))
  2086. return false;
  2087. if ((flags & SDVO_LVDS_MASK) == SDVO_LVDS_MASK)
  2088. if (!intel_sdvo_lvds_init(intel_sdvo, 1))
  2089. return false;
  2090. if ((flags & SDVO_OUTPUT_MASK) == 0) {
  2091. unsigned char bytes[2];
  2092. intel_sdvo->controlled_output = 0;
  2093. memcpy(bytes, &intel_sdvo->caps.output_flags, 2);
  2094. DRM_DEBUG_KMS("%s: Unknown SDVO output type (0x%02x%02x)\n",
  2095. SDVO_NAME(intel_sdvo),
  2096. bytes[0], bytes[1]);
  2097. return false;
  2098. }
  2099. intel_sdvo->base.crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
  2100. return true;
  2101. }
  2102. static void intel_sdvo_output_cleanup(struct intel_sdvo *intel_sdvo)
  2103. {
  2104. struct drm_device *dev = intel_sdvo->base.base.dev;
  2105. struct drm_connector *connector, *tmp;
  2106. list_for_each_entry_safe(connector, tmp,
  2107. &dev->mode_config.connector_list, head) {
  2108. if (intel_attached_encoder(connector) == &intel_sdvo->base)
  2109. intel_sdvo_destroy(connector);
  2110. }
  2111. }
  2112. static bool intel_sdvo_tv_create_property(struct intel_sdvo *intel_sdvo,
  2113. struct intel_sdvo_connector *intel_sdvo_connector,
  2114. int type)
  2115. {
  2116. struct drm_device *dev = intel_sdvo->base.base.dev;
  2117. struct intel_sdvo_tv_format format;
  2118. uint32_t format_map, i;
  2119. if (!intel_sdvo_set_target_output(intel_sdvo, type))
  2120. return false;
  2121. BUILD_BUG_ON(sizeof(format) != 6);
  2122. if (!intel_sdvo_get_value(intel_sdvo,
  2123. SDVO_CMD_GET_SUPPORTED_TV_FORMATS,
  2124. &format, sizeof(format)))
  2125. return false;
  2126. memcpy(&format_map, &format, min(sizeof(format_map), sizeof(format)));
  2127. if (format_map == 0)
  2128. return false;
  2129. intel_sdvo_connector->format_supported_num = 0;
  2130. for (i = 0 ; i < TV_FORMAT_NUM; i++)
  2131. if (format_map & (1 << i))
  2132. intel_sdvo_connector->tv_format_supported[intel_sdvo_connector->format_supported_num++] = i;
  2133. intel_sdvo_connector->tv_format =
  2134. drm_property_create(dev, DRM_MODE_PROP_ENUM,
  2135. "mode", intel_sdvo_connector->format_supported_num);
  2136. if (!intel_sdvo_connector->tv_format)
  2137. return false;
  2138. for (i = 0; i < intel_sdvo_connector->format_supported_num; i++)
  2139. drm_property_add_enum(
  2140. intel_sdvo_connector->tv_format, i,
  2141. i, tv_format_names[intel_sdvo_connector->tv_format_supported[i]]);
  2142. intel_sdvo->tv_format_index = intel_sdvo_connector->tv_format_supported[0];
  2143. drm_object_attach_property(&intel_sdvo_connector->base.base.base,
  2144. intel_sdvo_connector->tv_format, 0);
  2145. return true;
  2146. }
  2147. #define ENHANCEMENT(name, NAME) do { \
  2148. if (enhancements.name) { \
  2149. if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_MAX_##NAME, &data_value, 4) || \
  2150. !intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_##NAME, &response, 2)) \
  2151. return false; \
  2152. intel_sdvo_connector->max_##name = data_value[0]; \
  2153. intel_sdvo_connector->cur_##name = response; \
  2154. intel_sdvo_connector->name = \
  2155. drm_property_create_range(dev, 0, #name, 0, data_value[0]); \
  2156. if (!intel_sdvo_connector->name) return false; \
  2157. drm_object_attach_property(&connector->base, \
  2158. intel_sdvo_connector->name, \
  2159. intel_sdvo_connector->cur_##name); \
  2160. DRM_DEBUG_KMS(#name ": max %d, default %d, current %d\n", \
  2161. data_value[0], data_value[1], response); \
  2162. } \
  2163. } while (0)
  2164. static bool
  2165. intel_sdvo_create_enhance_property_tv(struct intel_sdvo *intel_sdvo,
  2166. struct intel_sdvo_connector *intel_sdvo_connector,
  2167. struct intel_sdvo_enhancements_reply enhancements)
  2168. {
  2169. struct drm_device *dev = intel_sdvo->base.base.dev;
  2170. struct drm_connector *connector = &intel_sdvo_connector->base.base;
  2171. uint16_t response, data_value[2];
  2172. /* when horizontal overscan is supported, Add the left/right property */
  2173. if (enhancements.overscan_h) {
  2174. if (!intel_sdvo_get_value(intel_sdvo,
  2175. SDVO_CMD_GET_MAX_OVERSCAN_H,
  2176. &data_value, 4))
  2177. return false;
  2178. if (!intel_sdvo_get_value(intel_sdvo,
  2179. SDVO_CMD_GET_OVERSCAN_H,
  2180. &response, 2))
  2181. return false;
  2182. intel_sdvo_connector->max_hscan = data_value[0];
  2183. intel_sdvo_connector->left_margin = data_value[0] - response;
  2184. intel_sdvo_connector->right_margin = intel_sdvo_connector->left_margin;
  2185. intel_sdvo_connector->left =
  2186. drm_property_create_range(dev, 0, "left_margin", 0, data_value[0]);
  2187. if (!intel_sdvo_connector->left)
  2188. return false;
  2189. drm_object_attach_property(&connector->base,
  2190. intel_sdvo_connector->left,
  2191. intel_sdvo_connector->left_margin);
  2192. intel_sdvo_connector->right =
  2193. drm_property_create_range(dev, 0, "right_margin", 0, data_value[0]);
  2194. if (!intel_sdvo_connector->right)
  2195. return false;
  2196. drm_object_attach_property(&connector->base,
  2197. intel_sdvo_connector->right,
  2198. intel_sdvo_connector->right_margin);
  2199. DRM_DEBUG_KMS("h_overscan: max %d, "
  2200. "default %d, current %d\n",
  2201. data_value[0], data_value[1], response);
  2202. }
  2203. if (enhancements.overscan_v) {
  2204. if (!intel_sdvo_get_value(intel_sdvo,
  2205. SDVO_CMD_GET_MAX_OVERSCAN_V,
  2206. &data_value, 4))
  2207. return false;
  2208. if (!intel_sdvo_get_value(intel_sdvo,
  2209. SDVO_CMD_GET_OVERSCAN_V,
  2210. &response, 2))
  2211. return false;
  2212. intel_sdvo_connector->max_vscan = data_value[0];
  2213. intel_sdvo_connector->top_margin = data_value[0] - response;
  2214. intel_sdvo_connector->bottom_margin = intel_sdvo_connector->top_margin;
  2215. intel_sdvo_connector->top =
  2216. drm_property_create_range(dev, 0,
  2217. "top_margin", 0, data_value[0]);
  2218. if (!intel_sdvo_connector->top)
  2219. return false;
  2220. drm_object_attach_property(&connector->base,
  2221. intel_sdvo_connector->top,
  2222. intel_sdvo_connector->top_margin);
  2223. intel_sdvo_connector->bottom =
  2224. drm_property_create_range(dev, 0,
  2225. "bottom_margin", 0, data_value[0]);
  2226. if (!intel_sdvo_connector->bottom)
  2227. return false;
  2228. drm_object_attach_property(&connector->base,
  2229. intel_sdvo_connector->bottom,
  2230. intel_sdvo_connector->bottom_margin);
  2231. DRM_DEBUG_KMS("v_overscan: max %d, "
  2232. "default %d, current %d\n",
  2233. data_value[0], data_value[1], response);
  2234. }
  2235. ENHANCEMENT(hpos, HPOS);
  2236. ENHANCEMENT(vpos, VPOS);
  2237. ENHANCEMENT(saturation, SATURATION);
  2238. ENHANCEMENT(contrast, CONTRAST);
  2239. ENHANCEMENT(hue, HUE);
  2240. ENHANCEMENT(sharpness, SHARPNESS);
  2241. ENHANCEMENT(brightness, BRIGHTNESS);
  2242. ENHANCEMENT(flicker_filter, FLICKER_FILTER);
  2243. ENHANCEMENT(flicker_filter_adaptive, FLICKER_FILTER_ADAPTIVE);
  2244. ENHANCEMENT(flicker_filter_2d, FLICKER_FILTER_2D);
  2245. ENHANCEMENT(tv_chroma_filter, TV_CHROMA_FILTER);
  2246. ENHANCEMENT(tv_luma_filter, TV_LUMA_FILTER);
  2247. if (enhancements.dot_crawl) {
  2248. if (!intel_sdvo_get_value(intel_sdvo, SDVO_CMD_GET_DOT_CRAWL, &response, 2))
  2249. return false;
  2250. intel_sdvo_connector->max_dot_crawl = 1;
  2251. intel_sdvo_connector->cur_dot_crawl = response & 0x1;
  2252. intel_sdvo_connector->dot_crawl =
  2253. drm_property_create_range(dev, 0, "dot_crawl", 0, 1);
  2254. if (!intel_sdvo_connector->dot_crawl)
  2255. return false;
  2256. drm_object_attach_property(&connector->base,
  2257. intel_sdvo_connector->dot_crawl,
  2258. intel_sdvo_connector->cur_dot_crawl);
  2259. DRM_DEBUG_KMS("dot crawl: current %d\n", response);
  2260. }
  2261. return true;
  2262. }
  2263. static bool
  2264. intel_sdvo_create_enhance_property_lvds(struct intel_sdvo *intel_sdvo,
  2265. struct intel_sdvo_connector *intel_sdvo_connector,
  2266. struct intel_sdvo_enhancements_reply enhancements)
  2267. {
  2268. struct drm_device *dev = intel_sdvo->base.base.dev;
  2269. struct drm_connector *connector = &intel_sdvo_connector->base.base;
  2270. uint16_t response, data_value[2];
  2271. ENHANCEMENT(brightness, BRIGHTNESS);
  2272. return true;
  2273. }
  2274. #undef ENHANCEMENT
  2275. static bool intel_sdvo_create_enhance_property(struct intel_sdvo *intel_sdvo,
  2276. struct intel_sdvo_connector *intel_sdvo_connector)
  2277. {
  2278. union {
  2279. struct intel_sdvo_enhancements_reply reply;
  2280. uint16_t response;
  2281. } enhancements;
  2282. BUILD_BUG_ON(sizeof(enhancements) != 2);
  2283. enhancements.response = 0;
  2284. intel_sdvo_get_value(intel_sdvo,
  2285. SDVO_CMD_GET_SUPPORTED_ENHANCEMENTS,
  2286. &enhancements, sizeof(enhancements));
  2287. if (enhancements.response == 0) {
  2288. DRM_DEBUG_KMS("No enhancement is supported\n");
  2289. return true;
  2290. }
  2291. if (IS_TV(intel_sdvo_connector))
  2292. return intel_sdvo_create_enhance_property_tv(intel_sdvo, intel_sdvo_connector, enhancements.reply);
  2293. else if (IS_LVDS(intel_sdvo_connector))
  2294. return intel_sdvo_create_enhance_property_lvds(intel_sdvo, intel_sdvo_connector, enhancements.reply);
  2295. else
  2296. return true;
  2297. }
  2298. static int intel_sdvo_ddc_proxy_xfer(struct i2c_adapter *adapter,
  2299. struct i2c_msg *msgs,
  2300. int num)
  2301. {
  2302. struct intel_sdvo *sdvo = adapter->algo_data;
  2303. if (!intel_sdvo_set_control_bus_switch(sdvo, sdvo->ddc_bus))
  2304. return -EIO;
  2305. return sdvo->i2c->algo->master_xfer(sdvo->i2c, msgs, num);
  2306. }
  2307. static u32 intel_sdvo_ddc_proxy_func(struct i2c_adapter *adapter)
  2308. {
  2309. struct intel_sdvo *sdvo = adapter->algo_data;
  2310. return sdvo->i2c->algo->functionality(sdvo->i2c);
  2311. }
  2312. static const struct i2c_algorithm intel_sdvo_ddc_proxy = {
  2313. .master_xfer = intel_sdvo_ddc_proxy_xfer,
  2314. .functionality = intel_sdvo_ddc_proxy_func
  2315. };
  2316. static bool
  2317. intel_sdvo_init_ddc_proxy(struct intel_sdvo *sdvo,
  2318. struct drm_device *dev)
  2319. {
  2320. sdvo->ddc.owner = THIS_MODULE;
  2321. sdvo->ddc.class = I2C_CLASS_DDC;
  2322. snprintf(sdvo->ddc.name, I2C_NAME_SIZE, "SDVO DDC proxy");
  2323. sdvo->ddc.dev.parent = &dev->pdev->dev;
  2324. sdvo->ddc.algo_data = sdvo;
  2325. sdvo->ddc.algo = &intel_sdvo_ddc_proxy;
  2326. return i2c_add_adapter(&sdvo->ddc) == 0;
  2327. }
  2328. bool intel_sdvo_init(struct drm_device *dev, uint32_t sdvo_reg, bool is_sdvob)
  2329. {
  2330. struct drm_i915_private *dev_priv = dev->dev_private;
  2331. struct intel_encoder *intel_encoder;
  2332. struct intel_sdvo *intel_sdvo;
  2333. u32 hotplug_mask;
  2334. int i;
  2335. intel_sdvo = kzalloc(sizeof(struct intel_sdvo), GFP_KERNEL);
  2336. if (!intel_sdvo)
  2337. return false;
  2338. intel_sdvo->sdvo_reg = sdvo_reg;
  2339. intel_sdvo->is_sdvob = is_sdvob;
  2340. intel_sdvo->slave_addr = intel_sdvo_get_slave_addr(dev, intel_sdvo) >> 1;
  2341. intel_sdvo_select_i2c_bus(dev_priv, intel_sdvo, sdvo_reg);
  2342. if (!intel_sdvo_init_ddc_proxy(intel_sdvo, dev))
  2343. goto err_i2c_bus;
  2344. /* encoder type will be decided later */
  2345. intel_encoder = &intel_sdvo->base;
  2346. intel_encoder->type = INTEL_OUTPUT_SDVO;
  2347. drm_encoder_init(dev, &intel_encoder->base, &intel_sdvo_enc_funcs, 0);
  2348. /* Read the regs to test if we can talk to the device */
  2349. for (i = 0; i < 0x40; i++) {
  2350. u8 byte;
  2351. if (!intel_sdvo_read_byte(intel_sdvo, i, &byte)) {
  2352. DRM_DEBUG_KMS("No SDVO device found on %s\n",
  2353. SDVO_NAME(intel_sdvo));
  2354. goto err;
  2355. }
  2356. }
  2357. hotplug_mask = 0;
  2358. if (IS_G4X(dev)) {
  2359. hotplug_mask = intel_sdvo->is_sdvob ?
  2360. SDVOB_HOTPLUG_INT_STATUS_G4X : SDVOC_HOTPLUG_INT_STATUS_G4X;
  2361. } else if (IS_GEN4(dev)) {
  2362. hotplug_mask = intel_sdvo->is_sdvob ?
  2363. SDVOB_HOTPLUG_INT_STATUS_I965 : SDVOC_HOTPLUG_INT_STATUS_I965;
  2364. } else {
  2365. hotplug_mask = intel_sdvo->is_sdvob ?
  2366. SDVOB_HOTPLUG_INT_STATUS_I915 : SDVOC_HOTPLUG_INT_STATUS_I915;
  2367. }
  2368. /* Only enable the hotplug irq if we need it, to work around noisy
  2369. * hotplug lines.
  2370. */
  2371. if (intel_sdvo->hotplug_active)
  2372. intel_encoder->hpd_pin = HPD_SDVO_B ? HPD_SDVO_B : HPD_SDVO_C;
  2373. intel_encoder->compute_config = intel_sdvo_compute_config;
  2374. intel_encoder->disable = intel_disable_sdvo;
  2375. intel_encoder->mode_set = intel_sdvo_mode_set;
  2376. intel_encoder->enable = intel_enable_sdvo;
  2377. intel_encoder->get_hw_state = intel_sdvo_get_hw_state;
  2378. /* In default case sdvo lvds is false */
  2379. if (!intel_sdvo_get_capabilities(intel_sdvo, &intel_sdvo->caps))
  2380. goto err;
  2381. if (intel_sdvo_output_setup(intel_sdvo,
  2382. intel_sdvo->caps.output_flags) != true) {
  2383. DRM_DEBUG_KMS("SDVO output failed to setup on %s\n",
  2384. SDVO_NAME(intel_sdvo));
  2385. /* Output_setup can leave behind connectors! */
  2386. goto err_output;
  2387. }
  2388. /*
  2389. * Cloning SDVO with anything is often impossible, since the SDVO
  2390. * encoder can request a special input timing mode. And even if that's
  2391. * not the case we have evidence that cloning a plain unscaled mode with
  2392. * VGA doesn't really work. Furthermore the cloning flags are way too
  2393. * simplistic anyway to express such constraints, so just give up on
  2394. * cloning for SDVO encoders.
  2395. */
  2396. intel_sdvo->base.cloneable = false;
  2397. intel_sdvo_select_ddc_bus(dev_priv, intel_sdvo, sdvo_reg);
  2398. /* Set the input timing to the screen. Assume always input 0. */
  2399. if (!intel_sdvo_set_target_input(intel_sdvo))
  2400. goto err_output;
  2401. if (!intel_sdvo_get_input_pixel_clock_range(intel_sdvo,
  2402. &intel_sdvo->pixel_clock_min,
  2403. &intel_sdvo->pixel_clock_max))
  2404. goto err_output;
  2405. DRM_DEBUG_KMS("%s device VID/DID: %02X:%02X.%02X, "
  2406. "clock range %dMHz - %dMHz, "
  2407. "input 1: %c, input 2: %c, "
  2408. "output 1: %c, output 2: %c\n",
  2409. SDVO_NAME(intel_sdvo),
  2410. intel_sdvo->caps.vendor_id, intel_sdvo->caps.device_id,
  2411. intel_sdvo->caps.device_rev_id,
  2412. intel_sdvo->pixel_clock_min / 1000,
  2413. intel_sdvo->pixel_clock_max / 1000,
  2414. (intel_sdvo->caps.sdvo_inputs_mask & 0x1) ? 'Y' : 'N',
  2415. (intel_sdvo->caps.sdvo_inputs_mask & 0x2) ? 'Y' : 'N',
  2416. /* check currently supported outputs */
  2417. intel_sdvo->caps.output_flags &
  2418. (SDVO_OUTPUT_TMDS0 | SDVO_OUTPUT_RGB0) ? 'Y' : 'N',
  2419. intel_sdvo->caps.output_flags &
  2420. (SDVO_OUTPUT_TMDS1 | SDVO_OUTPUT_RGB1) ? 'Y' : 'N');
  2421. return true;
  2422. err_output:
  2423. intel_sdvo_output_cleanup(intel_sdvo);
  2424. err:
  2425. drm_encoder_cleanup(&intel_encoder->base);
  2426. i2c_del_adapter(&intel_sdvo->ddc);
  2427. err_i2c_bus:
  2428. intel_sdvo_unselect_i2c_bus(intel_sdvo);
  2429. kfree(intel_sdvo);
  2430. return false;
  2431. }