pxa2xx-i2s.c 7.6 KB

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  1. /*
  2. * pxa2xx-i2s.c -- ALSA Soc Audio Layer
  3. *
  4. * Copyright 2005 Wolfson Microelectronics PLC.
  5. * Author: Liam Girdwood
  6. * liam.girdwood@wolfsonmicro.com or linux@wolfsonmicro.com
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of the GNU General Public License as published by the
  10. * Free Software Foundation; either version 2 of the License, or (at your
  11. * option) any later version.
  12. */
  13. #include <linux/init.h>
  14. #include <linux/module.h>
  15. #include <linux/device.h>
  16. #include <linux/delay.h>
  17. #include <linux/clk.h>
  18. #include <linux/platform_device.h>
  19. #include <sound/core.h>
  20. #include <sound/pcm.h>
  21. #include <sound/initval.h>
  22. #include <sound/soc.h>
  23. #include <mach/hardware.h>
  24. #include <mach/pxa-regs.h>
  25. #include <mach/pxa2xx-gpio.h>
  26. #include <mach/audio.h>
  27. #include "pxa2xx-pcm.h"
  28. #include "pxa2xx-i2s.h"
  29. struct pxa_i2s_port {
  30. u32 sadiv;
  31. u32 sacr0;
  32. u32 sacr1;
  33. u32 saimr;
  34. int master;
  35. u32 fmt;
  36. };
  37. static struct pxa_i2s_port pxa_i2s;
  38. static struct clk *clk_i2s;
  39. static struct pxa2xx_pcm_dma_params pxa2xx_i2s_pcm_stereo_out = {
  40. .name = "I2S PCM Stereo out",
  41. .dev_addr = __PREG(SADR),
  42. .drcmr = &DRCMRTXSADR,
  43. .dcmd = DCMD_INCSRCADDR | DCMD_FLOWTRG |
  44. DCMD_BURST32 | DCMD_WIDTH4,
  45. };
  46. static struct pxa2xx_pcm_dma_params pxa2xx_i2s_pcm_stereo_in = {
  47. .name = "I2S PCM Stereo in",
  48. .dev_addr = __PREG(SADR),
  49. .drcmr = &DRCMRRXSADR,
  50. .dcmd = DCMD_INCTRGADDR | DCMD_FLOWSRC |
  51. DCMD_BURST32 | DCMD_WIDTH4,
  52. };
  53. static struct pxa2xx_gpio gpio_bus[] = {
  54. { /* I2S SoC Slave */
  55. .rx = GPIO29_SDATA_IN_I2S_MD,
  56. .tx = GPIO30_SDATA_OUT_I2S_MD,
  57. .clk = GPIO28_BITCLK_IN_I2S_MD,
  58. .frm = GPIO31_SYNC_I2S_MD,
  59. },
  60. { /* I2S SoC Master */
  61. #ifdef CONFIG_PXA27x
  62. .sys = GPIO113_I2S_SYSCLK_MD,
  63. #else
  64. .sys = GPIO32_SYSCLK_I2S_MD,
  65. #endif
  66. .rx = GPIO29_SDATA_IN_I2S_MD,
  67. .tx = GPIO30_SDATA_OUT_I2S_MD,
  68. .clk = GPIO28_BITCLK_OUT_I2S_MD,
  69. .frm = GPIO31_SYNC_I2S_MD,
  70. },
  71. };
  72. static int pxa2xx_i2s_startup(struct snd_pcm_substream *substream)
  73. {
  74. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  75. struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
  76. if (IS_ERR(clk_i2s))
  77. return PTR_ERR(clk_i2s);
  78. if (!cpu_dai->active) {
  79. SACR0 |= SACR0_RST;
  80. SACR0 = 0;
  81. }
  82. return 0;
  83. }
  84. /* wait for I2S controller to be ready */
  85. static int pxa_i2s_wait(void)
  86. {
  87. int i;
  88. /* flush the Rx FIFO */
  89. for(i = 0; i < 16; i++)
  90. SADR;
  91. return 0;
  92. }
  93. static int pxa2xx_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai,
  94. unsigned int fmt)
  95. {
  96. /* interface format */
  97. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  98. case SND_SOC_DAIFMT_I2S:
  99. pxa_i2s.fmt = 0;
  100. break;
  101. case SND_SOC_DAIFMT_LEFT_J:
  102. pxa_i2s.fmt = SACR1_AMSL;
  103. break;
  104. }
  105. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  106. case SND_SOC_DAIFMT_CBS_CFS:
  107. pxa_i2s.master = 1;
  108. break;
  109. case SND_SOC_DAIFMT_CBM_CFS:
  110. pxa_i2s.master = 0;
  111. break;
  112. default:
  113. break;
  114. }
  115. return 0;
  116. }
  117. static int pxa2xx_i2s_set_dai_sysclk(struct snd_soc_dai *cpu_dai,
  118. int clk_id, unsigned int freq, int dir)
  119. {
  120. if (clk_id != PXA2XX_I2S_SYSCLK)
  121. return -ENODEV;
  122. if (pxa_i2s.master && dir == SND_SOC_CLOCK_OUT)
  123. pxa_gpio_mode(gpio_bus[pxa_i2s.master].sys);
  124. return 0;
  125. }
  126. static int pxa2xx_i2s_hw_params(struct snd_pcm_substream *substream,
  127. struct snd_pcm_hw_params *params)
  128. {
  129. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  130. struct snd_soc_dai *cpu_dai = rtd->dai->cpu_dai;
  131. pxa_gpio_mode(gpio_bus[pxa_i2s.master].rx);
  132. pxa_gpio_mode(gpio_bus[pxa_i2s.master].tx);
  133. pxa_gpio_mode(gpio_bus[pxa_i2s.master].frm);
  134. pxa_gpio_mode(gpio_bus[pxa_i2s.master].clk);
  135. BUG_ON(IS_ERR(clk_i2s));
  136. clk_enable(clk_i2s);
  137. pxa_i2s_wait();
  138. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  139. cpu_dai->dma_data = &pxa2xx_i2s_pcm_stereo_out;
  140. else
  141. cpu_dai->dma_data = &pxa2xx_i2s_pcm_stereo_in;
  142. /* is port used by another stream */
  143. if (!(SACR0 & SACR0_ENB)) {
  144. SACR0 = 0;
  145. SACR1 = 0;
  146. if (pxa_i2s.master)
  147. SACR0 |= SACR0_BCKD;
  148. SACR0 |= SACR0_RFTH(14) | SACR0_TFTH(1);
  149. SACR1 |= pxa_i2s.fmt;
  150. }
  151. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
  152. SAIMR |= SAIMR_TFS;
  153. else
  154. SAIMR |= SAIMR_RFS;
  155. switch (params_rate(params)) {
  156. case 8000:
  157. SADIV = 0x48;
  158. break;
  159. case 11025:
  160. SADIV = 0x34;
  161. break;
  162. case 16000:
  163. SADIV = 0x24;
  164. break;
  165. case 22050:
  166. SADIV = 0x1a;
  167. break;
  168. case 44100:
  169. SADIV = 0xd;
  170. break;
  171. case 48000:
  172. SADIV = 0xc;
  173. break;
  174. case 96000: /* not in manual and possibly slightly inaccurate */
  175. SADIV = 0x6;
  176. break;
  177. }
  178. return 0;
  179. }
  180. static int pxa2xx_i2s_trigger(struct snd_pcm_substream *substream, int cmd)
  181. {
  182. int ret = 0;
  183. switch (cmd) {
  184. case SNDRV_PCM_TRIGGER_START:
  185. SACR0 |= SACR0_ENB;
  186. break;
  187. case SNDRV_PCM_TRIGGER_RESUME:
  188. case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
  189. case SNDRV_PCM_TRIGGER_STOP:
  190. case SNDRV_PCM_TRIGGER_SUSPEND:
  191. case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
  192. break;
  193. default:
  194. ret = -EINVAL;
  195. }
  196. return ret;
  197. }
  198. static void pxa2xx_i2s_shutdown(struct snd_pcm_substream *substream)
  199. {
  200. if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
  201. SACR1 |= SACR1_DRPL;
  202. SAIMR &= ~SAIMR_TFS;
  203. } else {
  204. SACR1 |= SACR1_DREC;
  205. SAIMR &= ~SAIMR_RFS;
  206. }
  207. if (SACR1 & (SACR1_DREC | SACR1_DRPL)) {
  208. SACR0 &= ~SACR0_ENB;
  209. pxa_i2s_wait();
  210. clk_disable(clk_i2s);
  211. }
  212. clk_put(clk_i2s);
  213. }
  214. #ifdef CONFIG_PM
  215. static int pxa2xx_i2s_suspend(struct platform_device *dev,
  216. struct snd_soc_dai *dai)
  217. {
  218. if (!dai->active)
  219. return 0;
  220. /* store registers */
  221. pxa_i2s.sacr0 = SACR0;
  222. pxa_i2s.sacr1 = SACR1;
  223. pxa_i2s.saimr = SAIMR;
  224. pxa_i2s.sadiv = SADIV;
  225. /* deactivate link */
  226. SACR0 &= ~SACR0_ENB;
  227. pxa_i2s_wait();
  228. return 0;
  229. }
  230. static int pxa2xx_i2s_resume(struct platform_device *pdev,
  231. struct snd_soc_dai *dai)
  232. {
  233. if (!dai->active)
  234. return 0;
  235. pxa_i2s_wait();
  236. SACR0 = pxa_i2s.sacr0 &= ~SACR0_ENB;
  237. SACR1 = pxa_i2s.sacr1;
  238. SAIMR = pxa_i2s.saimr;
  239. SADIV = pxa_i2s.sadiv;
  240. SACR0 |= SACR0_ENB;
  241. return 0;
  242. }
  243. #else
  244. #define pxa2xx_i2s_suspend NULL
  245. #define pxa2xx_i2s_resume NULL
  246. #endif
  247. #define PXA2XX_I2S_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_11025 |\
  248. SNDRV_PCM_RATE_16000 | SNDRV_PCM_RATE_22050 | SNDRV_PCM_RATE_44100 | \
  249. SNDRV_PCM_RATE_48000 | SNDRV_PCM_RATE_96000)
  250. struct snd_soc_dai pxa_i2s_dai = {
  251. .name = "pxa2xx-i2s",
  252. .id = 0,
  253. .type = SND_SOC_DAI_I2S,
  254. .suspend = pxa2xx_i2s_suspend,
  255. .resume = pxa2xx_i2s_resume,
  256. .playback = {
  257. .channels_min = 2,
  258. .channels_max = 2,
  259. .rates = PXA2XX_I2S_RATES,
  260. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  261. .capture = {
  262. .channels_min = 2,
  263. .channels_max = 2,
  264. .rates = PXA2XX_I2S_RATES,
  265. .formats = SNDRV_PCM_FMTBIT_S16_LE,},
  266. .ops = {
  267. .startup = pxa2xx_i2s_startup,
  268. .shutdown = pxa2xx_i2s_shutdown,
  269. .trigger = pxa2xx_i2s_trigger,
  270. .hw_params = pxa2xx_i2s_hw_params,},
  271. .dai_ops = {
  272. .set_fmt = pxa2xx_i2s_set_dai_fmt,
  273. .set_sysclk = pxa2xx_i2s_set_dai_sysclk,
  274. },
  275. };
  276. EXPORT_SYMBOL_GPL(pxa_i2s_dai);
  277. static int pxa2xx_i2s_probe(struct platform_device *dev)
  278. {
  279. clk_i2s = clk_get(&dev->dev, "I2SCLK");
  280. return IS_ERR(clk_i2s) ? PTR_ERR(clk_i2s) : 0;
  281. }
  282. static int __devexit pxa2xx_i2s_remove(struct platform_device *dev)
  283. {
  284. clk_put(clk_i2s);
  285. clk_i2s = ERR_PTR(-ENOENT);
  286. return 0;
  287. }
  288. static struct platform_driver pxa2xx_i2s_driver = {
  289. .probe = pxa2xx_i2s_probe,
  290. .remove = __devexit_p(pxa2xx_i2s_remove),
  291. .driver = {
  292. .name = "pxa2xx-i2s",
  293. .owner = THIS_MODULE,
  294. },
  295. };
  296. static int __init pxa2xx_i2s_init(void)
  297. {
  298. clk_i2s = ERR_PTR(-ENOENT);
  299. return platform_driver_register(&pxa2xx_i2s_driver);
  300. }
  301. static void __exit pxa2xx_i2s_exit(void)
  302. {
  303. platform_driver_unregister(&pxa2xx_i2s_driver);
  304. }
  305. module_init(pxa2xx_i2s_init);
  306. module_exit(pxa2xx_i2s_exit);
  307. /* Module information */
  308. MODULE_AUTHOR("Liam Girdwood, liam.girdwood@wolfsonmicro.com, www.wolfsonmicro.com");
  309. MODULE_DESCRIPTION("pxa2xx I2S SoC Interface");
  310. MODULE_LICENSE("GPL");