ste-nomadik-stn8815.dtsi 6.6 KB

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  1. /*
  2. * Device Tree for the ST-Ericsson Nomadik 8815 STn8815 SoC
  3. */
  4. /include/ "skeleton.dtsi"
  5. / {
  6. #address-cells = <1>;
  7. #size-cells = <1>;
  8. memory {
  9. reg = <0x00000000 0x04000000>,
  10. <0x08000000 0x04000000>;
  11. };
  12. L2: l2-cache {
  13. compatible = "arm,l210-cache";
  14. reg = <0x10210000 0x1000>;
  15. interrupt-parent = <&vica>;
  16. interrupts = <30>;
  17. cache-unified;
  18. cache-level = <2>;
  19. };
  20. mtu0 {
  21. /* Nomadik system timer */
  22. reg = <0x101e2000 0x1000>;
  23. interrupt-parent = <&vica>;
  24. interrupts = <4>;
  25. };
  26. mtu1 {
  27. /* Secondary timer */
  28. reg = <0x101e3000 0x1000>;
  29. interrupt-parent = <&vica>;
  30. interrupts = <5>;
  31. };
  32. gpio0: gpio@101e4000 {
  33. compatible = "st,nomadik-gpio";
  34. reg = <0x101e4000 0x80>;
  35. interrupt-parent = <&vica>;
  36. interrupts = <6>;
  37. interrupt-controller;
  38. #interrupt-cells = <2>;
  39. gpio-controller;
  40. #gpio-cells = <2>;
  41. gpio-bank = <0>;
  42. clocks = <&pclk>;
  43. };
  44. gpio1: gpio@101e5000 {
  45. compatible = "st,nomadik-gpio";
  46. reg = <0x101e5000 0x80>;
  47. interrupt-parent = <&vica>;
  48. interrupts = <7>;
  49. interrupt-controller;
  50. #interrupt-cells = <2>;
  51. gpio-controller;
  52. #gpio-cells = <2>;
  53. gpio-bank = <1>;
  54. clocks = <&pclk>;
  55. };
  56. gpio2: gpio@101e6000 {
  57. compatible = "st,nomadik-gpio";
  58. reg = <0x101e6000 0x80>;
  59. interrupt-parent = <&vica>;
  60. interrupts = <8>;
  61. interrupt-controller;
  62. #interrupt-cells = <2>;
  63. gpio-controller;
  64. #gpio-cells = <2>;
  65. gpio-bank = <2>;
  66. clocks = <&pclk>;
  67. };
  68. gpio3: gpio@101e7000 {
  69. compatible = "st,nomadik-gpio";
  70. reg = <0x101e7000 0x80>;
  71. interrupt-parent = <&vica>;
  72. interrupts = <9>;
  73. interrupt-controller;
  74. #interrupt-cells = <2>;
  75. gpio-controller;
  76. #gpio-cells = <2>;
  77. gpio-bank = <3>;
  78. clocks = <&pclk>;
  79. };
  80. pinctrl {
  81. compatible = "stericsson,nmk-pinctrl-stn8815";
  82. };
  83. src: src@101e0000 {
  84. compatible = "stericsson,nomadik-src";
  85. reg = <0x101e0000 0x1000>;
  86. clocks {
  87. /*
  88. * Dummy clock for primecells
  89. */
  90. pclk: pclk@0 {
  91. #clock-cells = <0>;
  92. compatible = "fixed-clock";
  93. clock-frequency = <2400000>;
  94. };
  95. /*
  96. * The 2.4 MHz TIMCLK reference clock is active at
  97. * boot time, this is actually the MXTALCLK @19.2 MHz
  98. * divided by 8. This clock is used by the timers and
  99. * watchdog. See page 105 ff.
  100. */
  101. timclk: timclk@2.4M {
  102. #clock-cells = <0>;
  103. compatible = "fixed-clock";
  104. clock-frequency = <2400000>;
  105. };
  106. /*
  107. * At boot time, PLL2 is set to generate a set of
  108. * fixed clocks, one of them is CLK48, the 48 MHz
  109. * clock, routed to the UART, MMC/SD, I2C, IrDA,
  110. * USB and SSP blocks.
  111. */
  112. clk48: clk48@48M {
  113. #clock-cells = <0>;
  114. compatible = "fixed-clock";
  115. clock-frequency = <48000000>;
  116. };
  117. };
  118. };
  119. /* A NAND flash of 128 MiB */
  120. fsmc: flash@40000000 {
  121. compatible = "stericsson,fsmc-nand";
  122. #address-cells = <1>;
  123. #size-cells = <1>;
  124. reg = <0x10100000 0x1000>, /* FSMC Register*/
  125. <0x40000000 0x2000>, /* NAND Base DATA */
  126. <0x41000000 0x2000>, /* NAND Base ADDR */
  127. <0x40800000 0x2000>; /* NAND Base CMD */
  128. reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
  129. clocks = <&pclk>;
  130. status = "okay";
  131. partition@0 {
  132. label = "X-Loader(NAND)";
  133. reg = <0x0 0x40000>;
  134. };
  135. partition@40000 {
  136. label = "MemInit(NAND)";
  137. reg = <0x40000 0x40000>;
  138. };
  139. partition@80000 {
  140. label = "BootLoader(NAND)";
  141. reg = <0x80000 0x200000>;
  142. };
  143. partition@280000 {
  144. label = "Kernel zImage(NAND)";
  145. reg = <0x280000 0x300000>;
  146. };
  147. partition@580000 {
  148. label = "Root Filesystem(NAND)";
  149. reg = <0x580000 0x1600000>;
  150. };
  151. partition@1b80000 {
  152. label = "User Filesystem(NAND)";
  153. reg = <0x1b80000 0x6480000>;
  154. };
  155. };
  156. external-bus@34000000 {
  157. compatible = "simple-bus";
  158. reg = <0x34000000 0x1000000>;
  159. #address-cells = <1>;
  160. #size-cells = <1>;
  161. ranges = <0 0x34000000 0x1000000>;
  162. ethernet@300 {
  163. compatible = "smsc,lan91c111";
  164. reg = <0x300 0x0fd00>;
  165. };
  166. };
  167. /* I2C0 connected to the STw4811 power management chip */
  168. i2c0 {
  169. compatible = "i2c-gpio";
  170. gpios = <&gpio1 31 0>, /* sda */
  171. <&gpio1 30 0>; /* scl */
  172. #address-cells = <1>;
  173. #size-cells = <0>;
  174. stw4811@2d {
  175. compatible = "st,stw4811";
  176. reg = <0x2d>;
  177. };
  178. };
  179. /* I2C1 connected to various sensors */
  180. i2c1 {
  181. compatible = "i2c-gpio";
  182. gpios = <&gpio1 22 0>, /* sda */
  183. <&gpio1 21 0>; /* scl */
  184. #address-cells = <1>;
  185. #size-cells = <0>;
  186. camera@2d {
  187. compatible = "st,camera";
  188. reg = <0x10>;
  189. };
  190. stw5095@1a {
  191. compatible = "st,stw5095";
  192. reg = <0x1a>;
  193. };
  194. lis3lv02dl@1d {
  195. compatible = "st,lis3lv02dl";
  196. reg = <0x1d>;
  197. };
  198. };
  199. /* I2C2 connected to the USB portions of the STw4811 only */
  200. i2c2 {
  201. compatible = "i2c-gpio";
  202. gpios = <&gpio2 10 0>, /* sda */
  203. <&gpio2 9 0>; /* scl */
  204. #address-cells = <1>;
  205. #size-cells = <0>;
  206. stw4811@2d {
  207. compatible = "st,stw4811-usb";
  208. reg = <0x2d>;
  209. };
  210. };
  211. amba {
  212. compatible = "arm,amba-bus";
  213. #address-cells = <1>;
  214. #size-cells = <1>;
  215. ranges;
  216. vica: intc@0x10140000 {
  217. compatible = "arm,versatile-vic";
  218. interrupt-controller;
  219. #interrupt-cells = <1>;
  220. reg = <0x10140000 0x20>;
  221. };
  222. vicb: intc@0x10140020 {
  223. compatible = "arm,versatile-vic";
  224. interrupt-controller;
  225. #interrupt-cells = <1>;
  226. reg = <0x10140020 0x20>;
  227. };
  228. uart0: uart@101fd000 {
  229. compatible = "arm,pl011", "arm,primecell";
  230. reg = <0x101fd000 0x1000>;
  231. interrupt-parent = <&vica>;
  232. interrupts = <12>;
  233. clocks = <&clk48>, <&pclk>;
  234. clock-names = "uartclk", "apb_pclk";
  235. };
  236. uart1: uart@101fb000 {
  237. compatible = "arm,pl011", "arm,primecell";
  238. reg = <0x101fb000 0x1000>;
  239. interrupt-parent = <&vica>;
  240. interrupts = <17>;
  241. clocks = <&clk48>, <&pclk>;
  242. clock-names = "uartclk", "apb_pclk";
  243. };
  244. uart2: uart@101f2000 {
  245. compatible = "arm,pl011", "arm,primecell";
  246. reg = <0x101f2000 0x1000>;
  247. interrupt-parent = <&vica>;
  248. interrupts = <28>;
  249. clocks = <&clk48>, <&pclk>;
  250. clock-names = "uartclk", "apb_pclk";
  251. status = "disabled";
  252. };
  253. rng: rng@101b0000 {
  254. compatible = "arm,primecell";
  255. reg = <0x101b0000 0x1000>;
  256. clocks = <&clk48>, <&pclk>;
  257. clock-names = "rng", "apb_pclk";
  258. };
  259. rtc: rtc@101e8000 {
  260. compatible = "arm,pl031", "arm,primecell";
  261. reg = <0x101e8000 0x1000>;
  262. clocks = <&pclk>;
  263. clock-names = "apb_pclk";
  264. interrupt-parent = <&vica>;
  265. interrupts = <10>;
  266. };
  267. mmcsd: sdi@101f6000 {
  268. compatible = "arm,pl18x", "arm,primecell";
  269. reg = <0x101f6000 0x1000>;
  270. clocks = <&clk48>, <&pclk>;
  271. clock-names = "mclk", "apb_pclk";
  272. interrupt-parent = <&vica>;
  273. interrupts = <22>;
  274. max-frequency = <48000000>;
  275. bus-width = <4>;
  276. mmc-cap-mmc-highspeed;
  277. mmc-cap-sd-highspeed;
  278. cd-gpios = <&gpio3 15 0x1>;
  279. cd-inverted;
  280. };
  281. };
  282. };