at91sam9x5.dtsi 3.5 KB

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  1. /*
  2. * at91sam9x5.dtsi - Device Tree Include file for AT91SAM9x5 family SoC
  3. * applies to AT91SAM9G15, AT91SAM9G25, AT91SAM9G35,
  4. * AT91SAM9X25, AT91SAM9X35 SoC
  5. *
  6. * Copyright (C) 2012 Atmel,
  7. * 2012 Nicolas Ferre <nicolas.ferre@atmel.com>
  8. *
  9. * Licensed under GPLv2 or later.
  10. */
  11. /include/ "skeleton.dtsi"
  12. / {
  13. model = "Atmel AT91SAM9x5 family SoC";
  14. compatible = "atmel,at91sam9x5";
  15. interrupt-parent = <&aic>;
  16. aliases {
  17. serial0 = &dbgu;
  18. serial1 = &usart0;
  19. serial2 = &usart1;
  20. serial3 = &usart2;
  21. gpio0 = &pioA;
  22. gpio1 = &pioB;
  23. gpio2 = &pioC;
  24. gpio3 = &pioD;
  25. tcb0 = &tcb0;
  26. tcb1 = &tcb1;
  27. };
  28. cpus {
  29. cpu@0 {
  30. compatible = "arm,arm926ejs";
  31. };
  32. };
  33. memory@20000000 {
  34. reg = <0x20000000 0x10000000>;
  35. };
  36. ahb {
  37. compatible = "simple-bus";
  38. #address-cells = <1>;
  39. #size-cells = <1>;
  40. ranges;
  41. apb {
  42. compatible = "simple-bus";
  43. #address-cells = <1>;
  44. #size-cells = <1>;
  45. ranges;
  46. aic: interrupt-controller@fffff000 {
  47. #interrupt-cells = <2>;
  48. compatible = "atmel,at91rm9200-aic";
  49. interrupt-controller;
  50. interrupt-parent;
  51. reg = <0xfffff000 0x200>;
  52. };
  53. pit: timer@fffffe30 {
  54. compatible = "atmel,at91sam9260-pit";
  55. reg = <0xfffffe30 0xf>;
  56. interrupts = <1 4>;
  57. };
  58. tcb0: timer@f8008000 {
  59. compatible = "atmel,at91sam9x5-tcb";
  60. reg = <0xf8008000 0x100>;
  61. interrupts = <17 4>;
  62. };
  63. tcb1: timer@f800c000 {
  64. compatible = "atmel,at91sam9x5-tcb";
  65. reg = <0xf800c000 0x100>;
  66. interrupts = <17 4>;
  67. };
  68. dma0: dma-controller@ffffec00 {
  69. compatible = "atmel,at91sam9g45-dma";
  70. reg = <0xffffec00 0x200>;
  71. interrupts = <20 4>;
  72. };
  73. dma1: dma-controller@ffffee00 {
  74. compatible = "atmel,at91sam9g45-dma";
  75. reg = <0xffffee00 0x200>;
  76. interrupts = <21 4>;
  77. };
  78. pioA: gpio@fffff400 {
  79. compatible = "atmel,at91rm9200-gpio";
  80. reg = <0xfffff400 0x100>;
  81. interrupts = <2 4>;
  82. #gpio-cells = <2>;
  83. gpio-controller;
  84. };
  85. pioB: gpio@fffff600 {
  86. compatible = "atmel,at91rm9200-gpio";
  87. reg = <0xfffff600 0x100>;
  88. interrupts = <2 4>;
  89. #gpio-cells = <2>;
  90. gpio-controller;
  91. };
  92. pioC: gpio@fffff800 {
  93. compatible = "atmel,at91rm9200-gpio";
  94. reg = <0xfffff800 0x100>;
  95. interrupts = <3 4>;
  96. #gpio-cells = <2>;
  97. gpio-controller;
  98. };
  99. pioD: gpio@fffffa00 {
  100. compatible = "atmel,at91rm9200-gpio";
  101. reg = <0xfffffa00 0x100>;
  102. interrupts = <3 4>;
  103. #gpio-cells = <2>;
  104. gpio-controller;
  105. };
  106. dbgu: serial@fffff200 {
  107. compatible = "atmel,at91sam9260-usart";
  108. reg = <0xfffff200 0x200>;
  109. interrupts = <1 4>;
  110. status = "disabled";
  111. };
  112. usart0: serial@f801c000 {
  113. compatible = "atmel,at91sam9260-usart";
  114. reg = <0xf801c000 0x200>;
  115. interrupts = <5 4>;
  116. atmel,use-dma-rx;
  117. atmel,use-dma-tx;
  118. status = "disabled";
  119. };
  120. usart1: serial@f8020000 {
  121. compatible = "atmel,at91sam9260-usart";
  122. reg = <0xf8020000 0x200>;
  123. interrupts = <6 4>;
  124. atmel,use-dma-rx;
  125. atmel,use-dma-tx;
  126. status = "disabled";
  127. };
  128. usart2: serial@f8024000 {
  129. compatible = "atmel,at91sam9260-usart";
  130. reg = <0xf8024000 0x200>;
  131. interrupts = <7 4>;
  132. atmel,use-dma-rx;
  133. atmel,use-dma-tx;
  134. status = "disabled";
  135. };
  136. macb0: ethernet@f802c000 {
  137. compatible = "cdns,at32ap7000-macb", "cdns,macb";
  138. reg = <0xf802c000 0x100>;
  139. interrupts = <24 4>;
  140. status = "disabled";
  141. };
  142. macb1: ethernet@f8030000 {
  143. compatible = "cdns,at32ap7000-macb", "cdns,macb";
  144. reg = <0xf8030000 0x100>;
  145. interrupts = <27 4>;
  146. status = "disabled";
  147. };
  148. };
  149. };
  150. };